drivers/net/ethernet/renesas/sh_eth.c

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   6  *  Copyright (C) 2013 Cogent Embedded, Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *  You should have received a copy of the GNU General Public License along with
  17  *  this program; if not, write to the Free Software Foundation, Inc.,
  18  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  *  The full GNU General Public License is included in this distribution in
  21  *  the file called "COPYING".
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/mdio-bitbang.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44
  45 #include "sh_eth.h"
  46
  47 #define SH_ETH_DEF_MSG_ENABLE \
  48                 (NETIF_MSG_LINK | \
  49                 NETIF_MSG_TIMER | \
  50                 NETIF_MSG_RX_ERR| \
  51                 NETIF_MSG_TX_ERR)
  52
  53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  54         [EDSR]          = 0x0000,
  55         [EDMR]          = 0x0400,
  56         [EDTRR]         = 0x0408,
  57         [EDRRR]         = 0x0410,
  58         [EESR]          = 0x0428,
  59         [EESIPR]        = 0x0430,
  60         [TDLAR]         = 0x0010,
  61         [TDFAR]         = 0x0014,
  62         [TDFXR]         = 0x0018,
  63         [TDFFR]         = 0x001c,
  64         [RDLAR]         = 0x0030,
  65         [RDFAR]         = 0x0034,
  66         [RDFXR]         = 0x0038,
  67         [RDFFR]         = 0x003c,
  68         [TRSCER]        = 0x0438,
  69         [RMFCR]         = 0x0440,
  70         [TFTR]          = 0x0448,
  71         [FDR]           = 0x0450,
  72         [RMCR]          = 0x0458,
  73         [RPADIR]        = 0x0460,
  74         [FCFTR]         = 0x0468,
  75         [CSMR]          = 0x04E4,
  76
  77         [ECMR]          = 0x0500,
  78         [ECSR]          = 0x0510,
  79         [ECSIPR]        = 0x0518,
  80         [PIR]           = 0x0520,
  81         [PSR]           = 0x0528,
  82         [PIPR]          = 0x052c,
  83         [RFLR]          = 0x0508,
  84         [APR]           = 0x0554,
  85         [MPR]           = 0x0558,
  86         [PFTCR]         = 0x055c,
  87         [PFRCR]         = 0x0560,
  88         [TPAUSER]       = 0x0564,
  89         [GECMR]         = 0x05b0,
  90         [BCULR]         = 0x05b4,
  91         [MAHR]          = 0x05c0,
  92         [MALR]          = 0x05c8,
  93         [TROCR]         = 0x0700,
  94         [CDCR]          = 0x0708,
  95         [LCCR]          = 0x0710,
  96         [CEFCR]         = 0x0740,
  97         [FRECR]         = 0x0748,
  98         [TSFRCR]        = 0x0750,
  99         [TLFRCR]        = 0x0758,
 100         [RFCR]          = 0x0760,
 101         [CERCR]         = 0x0768,
 102         [CEECR]         = 0x0770,
 103         [MAFCR]         = 0x0778,
 104         [RMII_MII]      = 0x0790,
 105
 106         [ARSTR]         = 0x0000,
 107         [TSU_CTRST]     = 0x0004,
 108         [TSU_FWEN0]     = 0x0010,
 109         [TSU_FWEN1]     = 0x0014,
 110         [TSU_FCM]       = 0x0018,
 111         [TSU_BSYSL0]    = 0x0020,
 112         [TSU_BSYSL1]    = 0x0024,
 113         [TSU_PRISL0]    = 0x0028,
 114         [TSU_PRISL1]    = 0x002c,
 115         [TSU_FWSL0]     = 0x0030,
 116         [TSU_FWSL1]     = 0x0034,
 117         [TSU_FWSLC]     = 0x0038,
 118         [TSU_QTAG0]     = 0x0040,
 119         [TSU_QTAG1]     = 0x0044,
 120         [TSU_FWSR]      = 0x0050,
 121         [TSU_FWINMK]    = 0x0054,
 122         [TSU_ADQT0]     = 0x0048,
 123         [TSU_ADQT1]     = 0x004c,
 124         [TSU_VTAG0]     = 0x0058,
 125         [TSU_VTAG1]     = 0x005c,
 126         [TSU_ADSBSY]    = 0x0060,
 127         [TSU_TEN]       = 0x0064,
 128         [TSU_POST1]     = 0x0070,
 129         [TSU_POST2]     = 0x0074,
 130         [TSU_POST3]     = 0x0078,
 131         [TSU_POST4]     = 0x007c,
 132         [TSU_ADRH0]     = 0x0100,
 133         [TSU_ADRL0]     = 0x0104,
 134         [TSU_ADRH31]    = 0x01f8,
 135         [TSU_ADRL31]    = 0x01fc,
 136
 137         [TXNLCR0]       = 0x0080,
 138         [TXALCR0]       = 0x0084,
 139         [RXNLCR0]       = 0x0088,
 140         [RXALCR0]       = 0x008c,
 141         [FWNLCR0]       = 0x0090,
 142         [FWALCR0]       = 0x0094,
 143         [TXNLCR1]       = 0x00a0,
 144         [TXALCR1]       = 0x00a0,
 145         [RXNLCR1]       = 0x00a8,
 146         [RXALCR1]       = 0x00ac,
 147         [FWNLCR1]       = 0x00b0,
 148         [FWALCR1]       = 0x00b4,
 149 };
 150
 151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 152         [ECMR]          = 0x0300,
 153         [RFLR]          = 0x0308,
 154         [ECSR]          = 0x0310,
 155         [ECSIPR]        = 0x0318,
 156         [PIR]           = 0x0320,
 157         [PSR]           = 0x0328,
 158         [RDMLR]         = 0x0340,
 159         [IPGR]          = 0x0350,
 160         [APR]           = 0x0354,
 161         [MPR]           = 0x0358,
 162         [RFCF]          = 0x0360,
 163         [TPAUSER]       = 0x0364,
 164         [TPAUSECR]      = 0x0368,
 165         [MAHR]          = 0x03c0,
 166         [MALR]          = 0x03c8,
 167         [TROCR]         = 0x03d0,
 168         [CDCR]          = 0x03d4,
 169         [LCCR]          = 0x03d8,
 170         [CNDCR]         = 0x03dc,
 171         [CEFCR]         = 0x03e4,
 172         [FRECR]         = 0x03e8,
 173         [TSFRCR]        = 0x03ec,
 174         [TLFRCR]        = 0x03f0,
 175         [RFCR]          = 0x03f4,
 176         [MAFCR]         = 0x03f8,
 177
 178         [EDMR]          = 0x0200,
 179         [EDTRR]         = 0x0208,
 180         [EDRRR]         = 0x0210,
 181         [TDLAR]         = 0x0218,
 182         [RDLAR]         = 0x0220,
 183         [EESR]          = 0x0228,
 184         [EESIPR]        = 0x0230,
 185         [TRSCER]        = 0x0238,
 186         [RMFCR]         = 0x0240,
 187         [TFTR]          = 0x0248,
 188         [FDR]           = 0x0250,
 189         [RMCR]          = 0x0258,
 190         [TFUCR]         = 0x0264,
 191         [RFOCR]         = 0x0268,
 192         [FCFTR]         = 0x0270,
 193         [TRIMD]         = 0x027c,
 194 };
 195
 196 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 197         [ECMR]          = 0x0100,
 198         [RFLR]          = 0x0108,
 199         [ECSR]          = 0x0110,
 200         [ECSIPR]        = 0x0118,
 201         [PIR]           = 0x0120,
 202         [PSR]           = 0x0128,
 203         [RDMLR]         = 0x0140,
 204         [IPGR]          = 0x0150,
 205         [APR]           = 0x0154,
 206         [MPR]           = 0x0158,
 207         [TPAUSER]       = 0x0164,
 208         [RFCF]          = 0x0160,
 209         [TPAUSECR]      = 0x0168,
 210         [BCFRR]         = 0x016c,
 211         [MAHR]          = 0x01c0,
 212         [MALR]          = 0x01c8,
 213         [TROCR]         = 0x01d0,
 214         [CDCR]          = 0x01d4,
 215         [LCCR]          = 0x01d8,
 216         [CNDCR]         = 0x01dc,
 217         [CEFCR]         = 0x01e4,
 218         [FRECR]         = 0x01e8,
 219         [TSFRCR]        = 0x01ec,
 220         [TLFRCR]        = 0x01f0,
 221         [RFCR]          = 0x01f4,
 222         [MAFCR]         = 0x01f8,
 223         [RTRATE]        = 0x01fc,
 224
 225         [EDMR]          = 0x0000,
 226         [EDTRR]         = 0x0008,
 227         [EDRRR]         = 0x0010,
 228         [TDLAR]         = 0x0018,
 229         [RDLAR]         = 0x0020,
 230         [EESR]          = 0x0028,
 231         [EESIPR]        = 0x0030,
 232         [TRSCER]        = 0x0038,
 233         [RMFCR]         = 0x0040,
 234         [TFTR]          = 0x0048,
 235         [FDR]           = 0x0050,
 236         [RMCR]          = 0x0058,
 237         [TFUCR]         = 0x0064,
 238         [RFOCR]         = 0x0068,
 239         [FCFTR]         = 0x0070,
 240         [RPADIR]        = 0x0078,
 241         [TRIMD]         = 0x007c,
 242         [RBWAR]         = 0x00c8,
 243         [RDFAR]         = 0x00cc,
 244         [TBRAR]         = 0x00d4,
 245         [TDFAR]         = 0x00d8,
 246 };
 247
 248 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 249         [ECMR]          = 0x0160,
 250         [ECSR]          = 0x0164,
 251         [ECSIPR]        = 0x0168,
 252         [PIR]           = 0x016c,
 253         [MAHR]          = 0x0170,
 254         [MALR]          = 0x0174,
 255         [RFLR]          = 0x0178,
 256         [PSR]           = 0x017c,
 257         [TROCR]         = 0x0180,
 258         [CDCR]          = 0x0184,
 259         [LCCR]          = 0x0188,
 260         [CNDCR]         = 0x018c,
 261         [CEFCR]         = 0x0194,
 262         [FRECR]         = 0x0198,
 263         [TSFRCR]        = 0x019c,
 264         [TLFRCR]        = 0x01a0,
 265         [RFCR]          = 0x01a4,
 266         [MAFCR]         = 0x01a8,
 267         [IPGR]          = 0x01b4,
 268         [APR]           = 0x01b8,
 269         [MPR]           = 0x01bc,
 270         [TPAUSER]       = 0x01c4,
 271         [BCFR]          = 0x01cc,
 272
 273         [ARSTR]         = 0x0000,
 274         [TSU_CTRST]     = 0x0004,
 275         [TSU_FWEN0]     = 0x0010,
 276         [TSU_FWEN1]     = 0x0014,
 277         [TSU_FCM]       = 0x0018,
 278         [TSU_BSYSL0]    = 0x0020,
 279         [TSU_BSYSL1]    = 0x0024,
 280         [TSU_PRISL0]    = 0x0028,
 281         [TSU_PRISL1]    = 0x002c,
 282         [TSU_FWSL0]     = 0x0030,
 283         [TSU_FWSL1]     = 0x0034,
 284         [TSU_FWSLC]     = 0x0038,
 285         [TSU_QTAGM0]    = 0x0040,
 286         [TSU_QTAGM1]    = 0x0044,
 287         [TSU_ADQT0]     = 0x0048,
 288         [TSU_ADQT1]     = 0x004c,
 289         [TSU_FWSR]      = 0x0050,
 290         [TSU_FWINMK]    = 0x0054,
 291         [TSU_ADSBSY]    = 0x0060,
 292         [TSU_TEN]       = 0x0064,
 293         [TSU_POST1]     = 0x0070,
 294         [TSU_POST2]     = 0x0074,
 295         [TSU_POST3]     = 0x0078,
 296         [TSU_POST4]     = 0x007c,
 297
 298         [TXNLCR0]       = 0x0080,
 299         [TXALCR0]       = 0x0084,
 300         [RXNLCR0]       = 0x0088,
 301         [RXALCR0]       = 0x008c,
 302         [FWNLCR0]       = 0x0090,
 303         [FWALCR0]       = 0x0094,
 304         [TXNLCR1]       = 0x00a0,
 305         [TXALCR1]       = 0x00a0,
 306         [RXNLCR1]       = 0x00a8,
 307         [RXALCR1]       = 0x00ac,
 308         [FWNLCR1]       = 0x00b0,
 309         [FWALCR1]       = 0x00b4,
 310
 311         [TSU_ADRH0]     = 0x0100,
 312         [TSU_ADRL0]     = 0x0104,
 313         [TSU_ADRL31]    = 0x01fc,
 314 };
 315
 316 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
 317         defined(CONFIG_CPU_SUBTYPE_SH7763) || \
 318         defined(CONFIG_ARCH_R8A7740)
 319 static void sh_eth_select_mii(struct net_device *ndev)
 320 {
 321         u32 value = 0x0;
 322         struct sh_eth_private *mdp = netdev_priv(ndev);
 323
 324         switch (mdp->phy_interface) {
 325         case PHY_INTERFACE_MODE_GMII:
 326                 value = 0x2;
 327                 break;
 328         case PHY_INTERFACE_MODE_MII:
 329                 value = 0x1;
 330                 break;
 331         case PHY_INTERFACE_MODE_RMII:
 332                 value = 0x0;
 333                 break;
 334         default:
 335                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 336                 value = 0x1;
 337                 break;
 338         }
 339
 340         sh_eth_write(ndev, value, RMII_MII);
 341 }
 342 #endif
 343
 344 /* There is CPU dependent code */
 345 #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
 346 #define SH_ETH_RESET_DEFAULT    1
 347 static void sh_eth_set_duplex(struct net_device *ndev)
 348 {
 349         struct sh_eth_private *mdp = netdev_priv(ndev);
 350
 351         if (mdp->duplex) /* Full */
 352                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 353         else            /* Half */
 354                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 355 }
 356
 357 static void sh_eth_set_rate(struct net_device *ndev)
 358 {
 359         struct sh_eth_private *mdp = netdev_priv(ndev);
 360
 361         switch (mdp->speed) {
 362         case 10: /* 10BASE */
 363                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 364                 break;
 365         case 100:/* 100BASE */
 366                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 367                 break;
 368         default:
 369                 break;
 370         }
 371 }
 372
 373 /* R8A7778/9 */
 374 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 375         .set_duplex     = sh_eth_set_duplex,
 376         .set_rate       = sh_eth_set_rate,
 377
 378         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 379         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 380         .eesipr_value   = 0x01ff009f,
 381
 382         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 383         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 384                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 385         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 386
 387         .apr            = 1,
 388         .mpr            = 1,
 389         .tpauser        = 1,
 390         .hw_swap        = 1,
 391 };
 392 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
 393 #define SH_ETH_RESET_DEFAULT    1
 394 static void sh_eth_set_duplex(struct net_device *ndev)
 395 {
 396         struct sh_eth_private *mdp = netdev_priv(ndev);
 397
 398         if (mdp->duplex) /* Full */
 399                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 400         else            /* Half */
 401                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 402 }
 403
 404 static void sh_eth_set_rate(struct net_device *ndev)
 405 {
 406         struct sh_eth_private *mdp = netdev_priv(ndev);
 407
 408         switch (mdp->speed) {
 409         case 10: /* 10BASE */
 410                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 411                 break;
 412         case 100:/* 100BASE */
 413                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 414                 break;
 415         default:
 416                 break;
 417         }
 418 }
 419
 420 /* SH7724 */
 421 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 422         .set_duplex     = sh_eth_set_duplex,
 423         .set_rate       = sh_eth_set_rate,
 424
 425         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 426         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 427         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
 428
 429         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 430         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 431                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 432         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 433
 434         .apr            = 1,
 435         .mpr            = 1,
 436         .tpauser        = 1,
 437         .hw_swap        = 1,
 438         .rpadir         = 1,
 439         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 440 };
 441 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
 442 #define SH_ETH_HAS_BOTH_MODULES 1
 443 #define SH_ETH_HAS_TSU  1
 444 static int sh_eth_check_reset(struct net_device *ndev);
 445
 446 static void sh_eth_set_duplex(struct net_device *ndev)
 447 {
 448         struct sh_eth_private *mdp = netdev_priv(ndev);
 449
 450         if (mdp->duplex) /* Full */
 451                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 452         else            /* Half */
 453                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 454 }
 455
 456 static void sh_eth_set_rate(struct net_device *ndev)
 457 {
 458         struct sh_eth_private *mdp = netdev_priv(ndev);
 459
 460         switch (mdp->speed) {
 461         case 10: /* 10BASE */
 462                 sh_eth_write(ndev, 0, RTRATE);
 463                 break;
 464         case 100:/* 100BASE */
 465                 sh_eth_write(ndev, 1, RTRATE);
 466                 break;
 467         default:
 468                 break;
 469         }
 470 }
 471
 472 /* SH7757 */
 473 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 474         .set_duplex             = sh_eth_set_duplex,
 475         .set_rate               = sh_eth_set_rate,
 476
 477         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 478         .rmcr_value     = 0x00000001,
 479
 480         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 481         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 482                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 483         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 484
 485         .apr            = 1,
 486         .mpr            = 1,
 487         .tpauser        = 1,
 488         .hw_swap        = 1,
 489         .no_ade         = 1,
 490         .rpadir         = 1,
 491         .rpadir_value   = 2 << 16,
 492 };
 493
 494 #define SH_GIGA_ETH_BASE        0xfee00000
 495 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 496 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 497 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 498 {
 499         int i;
 500         unsigned long mahr[2], malr[2];
 501
 502         /* save MAHR and MALR */
 503         for (i = 0; i < 2; i++) {
 504                 malr[i] = ioread32((void *)GIGA_MALR(i));
 505                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 506         }
 507
 508         /* reset device */
 509         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 510         mdelay(1);
 511
 512         /* restore MAHR and MALR */
 513         for (i = 0; i < 2; i++) {
 514                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 515                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 516         }
 517 }
 518
 519 static int sh_eth_is_gether(struct sh_eth_private *mdp);
 520 static int sh_eth_reset(struct net_device *ndev)
 521 {
 522         struct sh_eth_private *mdp = netdev_priv(ndev);
 523         int ret = 0;
 524
 525         if (sh_eth_is_gether(mdp)) {
 526                 sh_eth_write(ndev, 0x03, EDSR);
 527                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 528                                 EDMR);
 529
 530                 ret = sh_eth_check_reset(ndev);
 531                 if (ret)
 532                         goto out;
 533
 534                 /* Table Init */
 535                 sh_eth_write(ndev, 0x0, TDLAR);
 536                 sh_eth_write(ndev, 0x0, TDFAR);
 537                 sh_eth_write(ndev, 0x0, TDFXR);
 538                 sh_eth_write(ndev, 0x0, TDFFR);
 539                 sh_eth_write(ndev, 0x0, RDLAR);
 540                 sh_eth_write(ndev, 0x0, RDFAR);
 541                 sh_eth_write(ndev, 0x0, RDFXR);
 542                 sh_eth_write(ndev, 0x0, RDFFR);
 543         } else {
 544                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 545                                 EDMR);
 546                 mdelay(3);
 547                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 548                                 EDMR);
 549         }
 550
 551 out:
 552         return ret;
 553 }
 554
 555 static void sh_eth_set_duplex_giga(struct net_device *ndev)
 556 {
 557         struct sh_eth_private *mdp = netdev_priv(ndev);
 558
 559         if (mdp->duplex) /* Full */
 560                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 561         else            /* Half */
 562                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 563 }
 564
 565 static void sh_eth_set_rate_giga(struct net_device *ndev)
 566 {
 567         struct sh_eth_private *mdp = netdev_priv(ndev);
 568
 569         switch (mdp->speed) {
 570         case 10: /* 10BASE */
 571                 sh_eth_write(ndev, 0x00000000, GECMR);
 572                 break;
 573         case 100:/* 100BASE */
 574                 sh_eth_write(ndev, 0x00000010, GECMR);
 575                 break;
 576         case 1000: /* 1000BASE */
 577                 sh_eth_write(ndev, 0x00000020, GECMR);
 578                 break;
 579         default:
 580                 break;
 581         }
 582 }
 583
 584 /* SH7757(GETHERC) */
 585 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
 586         .chip_reset     = sh_eth_chip_reset_giga,
 587         .set_duplex     = sh_eth_set_duplex_giga,
 588         .set_rate       = sh_eth_set_rate_giga,
 589
 590         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 591         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 592         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 593
 594         .tx_check       = EESR_TC1 | EESR_FTC,
 595         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 596                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 597                           EESR_ECI,
 598         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 599                           EESR_TFE,
 600         .fdr_value      = 0x0000072f,
 601         .rmcr_value     = 0x00000001,
 602
 603         .apr            = 1,
 604         .mpr            = 1,
 605         .tpauser        = 1,
 606         .bculr          = 1,
 607         .hw_swap        = 1,
 608         .rpadir         = 1,
 609         .rpadir_value   = 2 << 16,
 610         .no_trimd       = 1,
 611         .no_ade         = 1,
 612         .tsu            = 1,
 613 };
 614
 615 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
 616 {
 617         if (sh_eth_is_gether(mdp))
 618                 return &sh_eth_my_cpu_data_giga;
 619         else
 620                 return &sh_eth_my_cpu_data;
 621 }
 622
 623 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
 624 #define SH_ETH_HAS_TSU  1
 625 static int sh_eth_check_reset(struct net_device *ndev);
 626 static void sh_eth_reset_hw_crc(struct net_device *ndev);
 627
 628 static void sh_eth_chip_reset(struct net_device *ndev)
 629 {
 630         struct sh_eth_private *mdp = netdev_priv(ndev);
 631
 632         /* reset device */
 633         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 634         mdelay(1);
 635 }
 636
 637 static void sh_eth_set_duplex(struct net_device *ndev)
 638 {
 639         struct sh_eth_private *mdp = netdev_priv(ndev);
 640
 641         if (mdp->duplex) /* Full */
 642                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 643         else            /* Half */
 644                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 645 }
 646
 647 static void sh_eth_set_rate(struct net_device *ndev)
 648 {
 649         struct sh_eth_private *mdp = netdev_priv(ndev);
 650
 651         switch (mdp->speed) {
 652         case 10: /* 10BASE */
 653                 sh_eth_write(ndev, GECMR_10, GECMR);
 654                 break;
 655         case 100:/* 100BASE */
 656                 sh_eth_write(ndev, GECMR_100, GECMR);
 657                 break;
 658         case 1000: /* 1000BASE */
 659                 sh_eth_write(ndev, GECMR_1000, GECMR);
 660                 break;
 661         default:
 662                 break;
 663         }
 664 }
 665
 666 /* sh7763 */
 667 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 668         .chip_reset     = sh_eth_chip_reset,
 669         .set_duplex     = sh_eth_set_duplex,
 670         .set_rate       = sh_eth_set_rate,
 671
 672         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 673         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 674         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 675
 676         .tx_check       = EESR_TC1 | EESR_FTC,
 677         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 678                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 679                           EESR_ECI,
 680         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 681                           EESR_TFE,
 682
 683         .apr            = 1,
 684         .mpr            = 1,
 685         .tpauser        = 1,
 686         .bculr          = 1,
 687         .hw_swap        = 1,
 688         .no_trimd       = 1,
 689         .no_ade         = 1,
 690         .tsu            = 1,
 691 #if defined(CONFIG_CPU_SUBTYPE_SH7734)
 692         .hw_crc     = 1,
 693         .select_mii = 1,
 694 #endif
 695 };
 696
 697 static int sh_eth_reset(struct net_device *ndev)
 698 {
 699         int ret = 0;
 700
 701         sh_eth_write(ndev, EDSR_ENALL, EDSR);
 702         sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
 703
 704         ret = sh_eth_check_reset(ndev);
 705         if (ret)
 706                 goto out;
 707
 708         /* Table Init */
 709         sh_eth_write(ndev, 0x0, TDLAR);
 710         sh_eth_write(ndev, 0x0, TDFAR);
 711         sh_eth_write(ndev, 0x0, TDFXR);
 712         sh_eth_write(ndev, 0x0, TDFFR);
 713         sh_eth_write(ndev, 0x0, RDLAR);
 714         sh_eth_write(ndev, 0x0, RDFAR);
 715         sh_eth_write(ndev, 0x0, RDFXR);
 716         sh_eth_write(ndev, 0x0, RDFFR);
 717
 718         /* Reset HW CRC register */
 719         sh_eth_reset_hw_crc(ndev);
 720
 721         /* Select MII mode */
 722         if (sh_eth_my_cpu_data.select_mii)
 723                 sh_eth_select_mii(ndev);
 724 out:
 725         return ret;
 726 }
 727
 728 static void sh_eth_reset_hw_crc(struct net_device *ndev)
 729 {
 730         if (sh_eth_my_cpu_data.hw_crc)
 731                 sh_eth_write(ndev, 0x0, CSMR);
 732 }
 733
 734 #elif defined(CONFIG_ARCH_R8A7740)
 735 #define SH_ETH_HAS_TSU  1
 736 static int sh_eth_check_reset(struct net_device *ndev);
 737
 738 static void sh_eth_chip_reset(struct net_device *ndev)
 739 {
 740         struct sh_eth_private *mdp = netdev_priv(ndev);
 741
 742         /* reset device */
 743         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 744         mdelay(1);
 745
 746         sh_eth_select_mii(ndev);
 747 }
 748
 749 static int sh_eth_reset(struct net_device *ndev)
 750 {
 751         int ret = 0;
 752
 753         sh_eth_write(ndev, EDSR_ENALL, EDSR);
 754         sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
 755
 756         ret = sh_eth_check_reset(ndev);
 757         if (ret)
 758                 goto out;
 759
 760         /* Table Init */
 761         sh_eth_write(ndev, 0x0, TDLAR);
 762         sh_eth_write(ndev, 0x0, TDFAR);
 763         sh_eth_write(ndev, 0x0, TDFXR);
 764         sh_eth_write(ndev, 0x0, TDFFR);
 765         sh_eth_write(ndev, 0x0, RDLAR);
 766         sh_eth_write(ndev, 0x0, RDFAR);
 767         sh_eth_write(ndev, 0x0, RDFXR);
 768         sh_eth_write(ndev, 0x0, RDFFR);
 769
 770 out:
 771         return ret;
 772 }
 773
 774 static void sh_eth_set_duplex(struct net_device *ndev)
 775 {
 776         struct sh_eth_private *mdp = netdev_priv(ndev);
 777
 778         if (mdp->duplex) /* Full */
 779                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 780         else            /* Half */
 781                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 782 }
 783
 784 static void sh_eth_set_rate(struct net_device *ndev)
 785 {
 786         struct sh_eth_private *mdp = netdev_priv(ndev);
 787
 788         switch (mdp->speed) {
 789         case 10: /* 10BASE */
 790                 sh_eth_write(ndev, GECMR_10, GECMR);
 791                 break;
 792         case 100:/* 100BASE */
 793                 sh_eth_write(ndev, GECMR_100, GECMR);
 794                 break;
 795         case 1000: /* 1000BASE */
 796                 sh_eth_write(ndev, GECMR_1000, GECMR);
 797                 break;
 798         default:
 799                 break;
 800         }
 801 }
 802
 803 /* R8A7740 */
 804 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 805         .chip_reset     = sh_eth_chip_reset,
 806         .set_duplex     = sh_eth_set_duplex,
 807         .set_rate       = sh_eth_set_rate,
 808
 809         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 810         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 811         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 812
 813         .tx_check       = EESR_TC1 | EESR_FTC,
 814         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 815                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 816                           EESR_ECI,
 817         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 818                           EESR_TFE,
 819
 820         .apr            = 1,
 821         .mpr            = 1,
 822         .tpauser        = 1,
 823         .bculr          = 1,
 824         .hw_swap        = 1,
 825         .no_trimd       = 1,
 826         .no_ade         = 1,
 827         .tsu            = 1,
 828         .select_mii     = 1,
 829 };
 830
 831 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 832 #define SH_ETH_RESET_DEFAULT    1
 833 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 834         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 835
 836         .apr            = 1,
 837         .mpr            = 1,
 838         .tpauser        = 1,
 839         .hw_swap        = 1,
 840 };
 841 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 842 #define SH_ETH_RESET_DEFAULT    1
 843 #define SH_ETH_HAS_TSU  1
 844 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 845         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 846         .tsu            = 1,
 847 };
 848 #endif
 849
 850 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 851 {
 852         if (!cd->ecsr_value)
 853                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 854
 855         if (!cd->ecsipr_value)
 856                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 857
 858         if (!cd->fcftr_value)
 859                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
 860                                   DEFAULT_FIFO_F_D_RFD;
 861
 862         if (!cd->fdr_value)
 863                 cd->fdr_value = DEFAULT_FDR_INIT;
 864
 865         if (!cd->rmcr_value)
 866                 cd->rmcr_value = DEFAULT_RMCR_VALUE;
 867
 868         if (!cd->tx_check)
 869                 cd->tx_check = DEFAULT_TX_CHECK;
 870
 871         if (!cd->eesr_err_check)
 872                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 873
 874         if (!cd->tx_error_check)
 875                 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
 876 }
 877
 878 #if defined(SH_ETH_RESET_DEFAULT)
 879 /* Chip Reset */
 880 static int  sh_eth_reset(struct net_device *ndev)
 881 {
 882         sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
 883         mdelay(3);
 884         sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
 885
 886         return 0;
 887 }
 888 #else
 889 static int sh_eth_check_reset(struct net_device *ndev)
 890 {
 891         int ret = 0;
 892         int cnt = 100;
 893
 894         while (cnt > 0) {
 895                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 896                         break;
 897                 mdelay(1);
 898                 cnt--;
 899         }
 900         if (cnt <= 0) {
 901                 pr_err("Device reset failed\n");
 902                 ret = -ETIMEDOUT;
 903         }
 904         return ret;
 905 }
 906 #endif
 907
 908 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 909 static void sh_eth_set_receive_align(struct sk_buff *skb)
 910 {
 911         int reserve;
 912
 913         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 914         if (reserve)
 915                 skb_reserve(skb, reserve);
 916 }
 917 #else
 918 static void sh_eth_set_receive_align(struct sk_buff *skb)
 919 {
 920         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 921 }
 922 #endif
 923
 924
 925 /* CPU <-> EDMAC endian convert */
 926 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 927 {
 928         switch (mdp->edmac_endian) {
 929         case EDMAC_LITTLE_ENDIAN:
 930                 return cpu_to_le32(x);
 931         case EDMAC_BIG_ENDIAN:
 932                 return cpu_to_be32(x);
 933         }
 934         return x;
 935 }
 936
 937 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 938 {
 939         switch (mdp->edmac_endian) {
 940         case EDMAC_LITTLE_ENDIAN:
 941                 return le32_to_cpu(x);
 942         case EDMAC_BIG_ENDIAN:
 943                 return be32_to_cpu(x);
 944         }
 945         return x;
 946 }
 947
 948 /*
 949  * Program the hardware MAC address from dev->dev_addr.
 950  */
 951 static void update_mac_address(struct net_device *ndev)
 952 {
 953         sh_eth_write(ndev,
 954                 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 955                 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 956         sh_eth_write(ndev,
 957                 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 958 }
 959
 960 /*
 961  * Get MAC address from SuperH MAC address register
 962  *
 963  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 964  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 965  * When you want use this device, you must set MAC address in bootloader.
 966  *
 967  */
 968 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 969 {
 970         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 971                 memcpy(ndev->dev_addr, mac, 6);
 972         } else {
 973                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 974                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 975                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 976                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 977                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 978                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 979         }
 980 }
 981
 982 static int sh_eth_is_gether(struct sh_eth_private *mdp)
 983 {
 984         if (mdp->reg_offset == sh_eth_offset_gigabit)
 985                 return 1;
 986         else
 987                 return 0;
 988 }
 989
 990 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 991 {
 992         if (sh_eth_is_gether(mdp))
 993                 return EDTRR_TRNS_GETHER;
 994         else
 995                 return EDTRR_TRNS_ETHER;
 996 }
 997
 998 struct bb_info {
 999         void (*set_gate)(void *addr);
1000         struct mdiobb_ctrl ctrl;
1001         void *addr;
1002         u32 mmd_msk;/* MMD */
1003         u32 mdo_msk;
1004         u32 mdi_msk;
1005         u32 mdc_msk;
1006 };
1007
1008 /* PHY bit set */
1009 static void bb_set(void *addr, u32 msk)
1010 {
1011         iowrite32(ioread32(addr) | msk, addr);
1012 }
1013
1014 /* PHY bit clear */
1015 static void bb_clr(void *addr, u32 msk)
1016 {
1017         iowrite32((ioread32(addr) & ~msk), addr);
1018 }
1019
1020 /* PHY bit read */
1021 static int bb_read(void *addr, u32 msk)
1022 {
1023         return (ioread32(addr) & msk) != 0;
1024 }
1025
1026 /* Data I/O pin control */
1027 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1028 {
1029         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1030
1031         if (bitbang->set_gate)
1032                 bitbang->set_gate(bitbang->addr);
1033
1034         if (bit)
1035                 bb_set(bitbang->addr, bitbang->mmd_msk);
1036         else
1037                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1038 }
1039
1040 /* Set bit data*/
1041 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1042 {
1043         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1044
1045         if (bitbang->set_gate)
1046                 bitbang->set_gate(bitbang->addr);
1047
1048         if (bit)
1049                 bb_set(bitbang->addr, bitbang->mdo_msk);
1050         else
1051                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1052 }
1053
1054 /* Get bit data*/
1055 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1056 {
1057         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1058
1059         if (bitbang->set_gate)
1060                 bitbang->set_gate(bitbang->addr);
1061
1062         return bb_read(bitbang->addr, bitbang->mdi_msk);
1063 }
1064
1065 /* MDC pin control */
1066 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1067 {
1068         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1069
1070         if (bitbang->set_gate)
1071                 bitbang->set_gate(bitbang->addr);
1072
1073         if (bit)
1074                 bb_set(bitbang->addr, bitbang->mdc_msk);
1075         else
1076                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1077 }
1078
1079 /* mdio bus control struct */
1080 static struct mdiobb_ops bb_ops = {
1081         .owner = THIS_MODULE,
1082         .set_mdc = sh_mdc_ctrl,
1083         .set_mdio_dir = sh_mmd_ctrl,
1084         .set_mdio_data = sh_set_mdio,
1085         .get_mdio_data = sh_get_mdio,
1086 };
1087
1088 /* free skb and descriptor buffer */
1089 static void sh_eth_ring_free(struct net_device *ndev)
1090 {
1091         struct sh_eth_private *mdp = netdev_priv(ndev);
1092         int i;
1093
1094         /* Free Rx skb ringbuffer */
1095         if (mdp->rx_skbuff) {
1096                 for (i = 0; i < mdp->num_rx_ring; i++) {
1097                         if (mdp->rx_skbuff[i])
1098                                 dev_kfree_skb(mdp->rx_skbuff[i]);
1099                 }
1100         }
1101         kfree(mdp->rx_skbuff);
1102         mdp->rx_skbuff = NULL;
1103
1104         /* Free Tx skb ringbuffer */
1105         if (mdp->tx_skbuff) {
1106                 for (i = 0; i < mdp->num_tx_ring; i++) {
1107                         if (mdp->tx_skbuff[i])
1108                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1109                 }
1110         }
1111         kfree(mdp->tx_skbuff);
1112         mdp->tx_skbuff = NULL;
1113 }
1114
1115 /* format skb and descriptor buffer */
1116 static void sh_eth_ring_format(struct net_device *ndev)
1117 {
1118         struct sh_eth_private *mdp = netdev_priv(ndev);
1119         int i;
1120         struct sk_buff *skb;
1121         struct sh_eth_rxdesc *rxdesc = NULL;
1122         struct sh_eth_txdesc *txdesc = NULL;
1123         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1124         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1125
1126         mdp->cur_rx = mdp->cur_tx = 0;
1127         mdp->dirty_rx = mdp->dirty_tx = 0;
1128
1129         memset(mdp->rx_ring, 0, rx_ringsize);
1130
1131         /* build Rx ring buffer */
1132         for (i = 0; i < mdp->num_rx_ring; i++) {
1133                 /* skb */
1134                 mdp->rx_skbuff[i] = NULL;
1135                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1136                 mdp->rx_skbuff[i] = skb;
1137                 if (skb == NULL)
1138                         break;
1139                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1140                                 DMA_FROM_DEVICE);
1141                 sh_eth_set_receive_align(skb);
1142
1143                 /* RX descriptor */
1144                 rxdesc = &mdp->rx_ring[i];
1145                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1146                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1147
1148                 /* The size of the buffer is 16 byte boundary. */
1149                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1150                 /* Rx descriptor address set */
1151                 if (i == 0) {
1152                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1153                         if (sh_eth_is_gether(mdp))
1154                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1155                 }
1156         }
1157
1158         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1159
1160         /* Mark the last entry as wrapping the ring. */
1161         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1162
1163         memset(mdp->tx_ring, 0, tx_ringsize);
1164
1165         /* build Tx ring buffer */
1166         for (i = 0; i < mdp->num_tx_ring; i++) {
1167                 mdp->tx_skbuff[i] = NULL;
1168                 txdesc = &mdp->tx_ring[i];
1169                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1170                 txdesc->buffer_length = 0;
1171                 if (i == 0) {
1172                         /* Tx descriptor address set */
1173                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1174                         if (sh_eth_is_gether(mdp))
1175                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1176                 }
1177         }
1178
1179         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1180 }
1181
1182 /* Get skb and descriptor buffer */
1183 static int sh_eth_ring_init(struct net_device *ndev)
1184 {
1185         struct sh_eth_private *mdp = netdev_priv(ndev);
1186         int rx_ringsize, tx_ringsize, ret = 0;
1187
1188         /*
1189          * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1190          * card needs room to do 8 byte alignment, +2 so we can reserve
1191          * the first 2 bytes, and +16 gets room for the status word from the
1192          * card.
1193          */
1194         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1195                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1196         if (mdp->cd->rpadir)
1197                 mdp->rx_buf_sz += NET_IP_ALIGN;
1198
1199         /* Allocate RX and TX skb rings */
1200         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1201                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1202         if (!mdp->rx_skbuff) {
1203                 ret = -ENOMEM;
1204                 return ret;
1205         }
1206
1207         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1208                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1209         if (!mdp->tx_skbuff) {
1210                 ret = -ENOMEM;
1211                 goto skb_ring_free;
1212         }
1213
1214         /* Allocate all Rx descriptors. */
1215         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1216         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1217                                           GFP_KERNEL);
1218         if (!mdp->rx_ring) {
1219                 ret = -ENOMEM;
1220                 goto desc_ring_free;
1221         }
1222
1223         mdp->dirty_rx = 0;
1224
1225         /* Allocate all Tx descriptors. */
1226         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1227         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1228                                           GFP_KERNEL);
1229         if (!mdp->tx_ring) {
1230                 ret = -ENOMEM;
1231                 goto desc_ring_free;
1232         }
1233         return ret;
1234
1235 desc_ring_free:
1236         /* free DMA buffer */
1237         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1238
1239 skb_ring_free:
1240         /* Free Rx and Tx skb ring buffer */
1241         sh_eth_ring_free(ndev);
1242         mdp->tx_ring = NULL;
1243         mdp->rx_ring = NULL;
1244
1245         return ret;
1246 }
1247
1248 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1249 {
1250         int ringsize;
1251
1252         if (mdp->rx_ring) {
1253                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1254                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1255                                   mdp->rx_desc_dma);
1256                 mdp->rx_ring = NULL;
1257         }
1258
1259         if (mdp->tx_ring) {
1260                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1261                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1262                                   mdp->tx_desc_dma);
1263                 mdp->tx_ring = NULL;
1264         }
1265 }
1266
1267 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1268 {
1269         int ret = 0;
1270         struct sh_eth_private *mdp = netdev_priv(ndev);
1271         u32 val;
1272
1273         /* Soft Reset */
1274         ret = sh_eth_reset(ndev);
1275         if (ret)
1276                 goto out;
1277
1278         /* Descriptor format */
1279         sh_eth_ring_format(ndev);
1280         if (mdp->cd->rpadir)
1281                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1282
1283         /* all sh_eth int mask */
1284         sh_eth_write(ndev, 0, EESIPR);
1285
1286 #if defined(__LITTLE_ENDIAN)
1287         if (mdp->cd->hw_swap)
1288                 sh_eth_write(ndev, EDMR_EL, EDMR);
1289         else
1290 #endif
1291                 sh_eth_write(ndev, 0, EDMR);
1292
1293         /* FIFO size set */
1294         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1295         sh_eth_write(ndev, 0, TFTR);
1296
1297         /* Frame recv control */
1298         sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1299
1300         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1301
1302         if (mdp->cd->bculr)
1303                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1304
1305         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1306
1307         if (!mdp->cd->no_trimd)
1308                 sh_eth_write(ndev, 0, TRIMD);
1309
1310         /* Recv frame limit set register */
1311         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1312                      RFLR);
1313
1314         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1315         if (start)
1316                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1317
1318         /* PAUSE Prohibition */
1319         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1320                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1321
1322         sh_eth_write(ndev, val, ECMR);
1323
1324         if (mdp->cd->set_rate)
1325                 mdp->cd->set_rate(ndev);
1326
1327         /* E-MAC Status Register clear */
1328         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1329
1330         /* E-MAC Interrupt Enable register */
1331         if (start)
1332                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1333
1334         /* Set MAC address */
1335         update_mac_address(ndev);
1336
1337         /* mask reset */
1338         if (mdp->cd->apr)
1339                 sh_eth_write(ndev, APR_AP, APR);
1340         if (mdp->cd->mpr)
1341                 sh_eth_write(ndev, MPR_MP, MPR);
1342         if (mdp->cd->tpauser)
1343                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1344
1345         if (start) {
1346                 /* Setting the Rx mode will start the Rx process. */
1347                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1348
1349                 netif_start_queue(ndev);
1350         }
1351
1352 out:
1353         return ret;
1354 }
1355
1356 /* free Tx skb function */
1357 static int sh_eth_txfree(struct net_device *ndev)
1358 {
1359         struct sh_eth_private *mdp = netdev_priv(ndev);
1360         struct sh_eth_txdesc *txdesc;
1361         int freeNum = 0;
1362         int entry = 0;
1363
1364         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1365                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1366                 txdesc = &mdp->tx_ring[entry];
1367                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1368                         break;
1369                 /* Free the original skb. */
1370                 if (mdp->tx_skbuff[entry]) {
1371                         dma_unmap_single(&ndev->dev, txdesc->addr,
1372                                          txdesc->buffer_length, DMA_TO_DEVICE);
1373                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1374                         mdp->tx_skbuff[entry] = NULL;
1375                         freeNum++;
1376                 }
1377                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1378                 if (entry >= mdp->num_tx_ring - 1)
1379                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1380
1381                 ndev->stats.tx_packets++;
1382                 ndev->stats.tx_bytes += txdesc->buffer_length;
1383         }
1384         return freeNum;
1385 }
1386
1387 /* Packet receive function */
1388 static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
1389 {
1390         struct sh_eth_private *mdp = netdev_priv(ndev);
1391         struct sh_eth_rxdesc *rxdesc;
1392
1393         int entry = mdp->cur_rx % mdp->num_rx_ring;
1394         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1395         struct sk_buff *skb;
1396         u16 pkt_len = 0;
1397         u32 desc_status;
1398
1399         rxdesc = &mdp->rx_ring[entry];
1400         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1401                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1402                 pkt_len = rxdesc->frame_length;
1403
1404                 if (--boguscnt < 0)
1405                         break;
1406
1407                 if (!(desc_status & RDFEND))
1408                         ndev->stats.rx_length_errors++;
1409
1410 #if defined(CONFIG_ARCH_R8A7740)
1411                 /*
1412                  * In case of almost all GETHER/ETHERs, the Receive Frame State
1413                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1414                  * bit 0. However, in case of the R8A7740's GETHER, the RFS
1415                  * bits are from bit 25 to bit 16. So, the driver needs right
1416                  * shifting by 16.
1417                  */
1418                 desc_status >>= 16;
1419 #endif
1420
1421                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1422                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1423                         ndev->stats.rx_errors++;
1424                         if (desc_status & RD_RFS1)
1425                                 ndev->stats.rx_crc_errors++;
1426                         if (desc_status & RD_RFS2)
1427                                 ndev->stats.rx_frame_errors++;
1428                         if (desc_status & RD_RFS3)
1429                                 ndev->stats.rx_length_errors++;
1430                         if (desc_status & RD_RFS4)
1431                                 ndev->stats.rx_length_errors++;
1432                         if (desc_status & RD_RFS6)
1433                                 ndev->stats.rx_missed_errors++;
1434                         if (desc_status & RD_RFS10)
1435                                 ndev->stats.rx_over_errors++;
1436                 } else {
1437                         if (!mdp->cd->hw_swap)
1438                                 sh_eth_soft_swap(
1439                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1440                                         pkt_len + 2);
1441                         skb = mdp->rx_skbuff[entry];
1442                         mdp->rx_skbuff[entry] = NULL;
1443                         if (mdp->cd->rpadir)
1444                                 skb_reserve(skb, NET_IP_ALIGN);
1445                         skb_put(skb, pkt_len);
1446                         skb->protocol = eth_type_trans(skb, ndev);
1447                         netif_rx(skb);
1448                         ndev->stats.rx_packets++;
1449                         ndev->stats.rx_bytes += pkt_len;
1450                 }
1451                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1452                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1453                 rxdesc = &mdp->rx_ring[entry];
1454         }
1455
1456         /* Refill the Rx ring buffers. */
1457         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1458                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1459                 rxdesc = &mdp->rx_ring[entry];
1460                 /* The size of the buffer is 16 byte boundary. */
1461                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1462
1463                 if (mdp->rx_skbuff[entry] == NULL) {
1464                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1465                         mdp->rx_skbuff[entry] = skb;
1466                         if (skb == NULL)
1467                                 break;  /* Better luck next round. */
1468                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1469                                         DMA_FROM_DEVICE);
1470                         sh_eth_set_receive_align(skb);
1471
1472                         skb_checksum_none_assert(skb);
1473                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1474                 }
1475                 if (entry >= mdp->num_rx_ring - 1)
1476                         rxdesc->status |=
1477                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1478                 else
1479                         rxdesc->status |=
1480                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1481         }
1482
1483         /* Restart Rx engine if stopped. */
1484         /* If we don't need to check status, don't. -KDU */
1485         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1486                 /* fix the values for the next receiving if RDE is set */
1487                 if (intr_status & EESR_RDE)
1488                         mdp->cur_rx = mdp->dirty_rx =
1489                                 (sh_eth_read(ndev, RDFAR) -
1490                                  sh_eth_read(ndev, RDLAR)) >> 4;
1491                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1492         }
1493
1494         return 0;
1495 }
1496
1497 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1498 {
1499         /* disable tx and rx */
1500         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1501                 ~(ECMR_RE | ECMR_TE), ECMR);
1502 }
1503
1504 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1505 {
1506         /* enable tx and rx */
1507         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1508                 (ECMR_RE | ECMR_TE), ECMR);
1509 }
1510
1511 /* error control function */
1512 static void sh_eth_error(struct net_device *ndev, int intr_status)
1513 {
1514         struct sh_eth_private *mdp = netdev_priv(ndev);
1515         u32 felic_stat;
1516         u32 link_stat;
1517         u32 mask;
1518
1519         if (intr_status & EESR_ECI) {
1520                 felic_stat = sh_eth_read(ndev, ECSR);
1521                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1522                 if (felic_stat & ECSR_ICD)
1523                         ndev->stats.tx_carrier_errors++;
1524                 if (felic_stat & ECSR_LCHNG) {
1525                         /* Link Changed */
1526                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1527                                 goto ignore_link;
1528                         } else {
1529                                 link_stat = (sh_eth_read(ndev, PSR));
1530                                 if (mdp->ether_link_active_low)
1531                                         link_stat = ~link_stat;
1532                         }
1533                         if (!(link_stat & PHY_ST_LINK))
1534                                 sh_eth_rcv_snd_disable(ndev);
1535                         else {
1536                                 /* Link Up */
1537                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1538                                           ~DMAC_M_ECI, EESIPR);
1539                                 /*clear int */
1540                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1541                                           ECSR);
1542                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1543                                           DMAC_M_ECI, EESIPR);
1544                                 /* enable tx and rx */
1545                                 sh_eth_rcv_snd_enable(ndev);
1546                         }
1547                 }
1548         }
1549
1550 ignore_link:
1551         if (intr_status & EESR_TWB) {
1552                 /* Write buck end. unused write back interrupt */
1553                 if (intr_status & EESR_TABT)    /* Transmit Abort int */
1554                         ndev->stats.tx_aborted_errors++;
1555                         if (netif_msg_tx_err(mdp))
1556                                 dev_err(&ndev->dev, "Transmit Abort\n");
1557         }
1558
1559         if (intr_status & EESR_RABT) {
1560                 /* Receive Abort int */
1561                 if (intr_status & EESR_RFRMER) {
1562                         /* Receive Frame Overflow int */
1563                         ndev->stats.rx_frame_errors++;
1564                         if (netif_msg_rx_err(mdp))
1565                                 dev_err(&ndev->dev, "Receive Abort\n");
1566                 }
1567         }
1568
1569         if (intr_status & EESR_TDE) {
1570                 /* Transmit Descriptor Empty int */
1571                 ndev->stats.tx_fifo_errors++;
1572                 if (netif_msg_tx_err(mdp))
1573                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1574         }
1575
1576         if (intr_status & EESR_TFE) {
1577                 /* FIFO under flow */
1578                 ndev->stats.tx_fifo_errors++;
1579                 if (netif_msg_tx_err(mdp))
1580                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1581         }
1582
1583         if (intr_status & EESR_RDE) {
1584                 /* Receive Descriptor Empty int */
1585                 ndev->stats.rx_over_errors++;
1586
1587                 if (netif_msg_rx_err(mdp))
1588                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1589         }
1590
1591         if (intr_status & EESR_RFE) {
1592                 /* Receive FIFO Overflow int */
1593                 ndev->stats.rx_fifo_errors++;
1594                 if (netif_msg_rx_err(mdp))
1595                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1596         }
1597
1598         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1599                 /* Address Error */
1600                 ndev->stats.tx_fifo_errors++;
1601                 if (netif_msg_tx_err(mdp))
1602                         dev_err(&ndev->dev, "Address Error\n");
1603         }
1604
1605         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1606         if (mdp->cd->no_ade)
1607                 mask &= ~EESR_ADE;
1608         if (intr_status & mask) {
1609                 /* Tx error */
1610                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1611                 /* dmesg */
1612                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1613                                 intr_status, mdp->cur_tx);
1614                 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1615                                 mdp->dirty_tx, (u32) ndev->state, edtrr);
1616                 /* dirty buffer free */
1617                 sh_eth_txfree(ndev);
1618
1619                 /* SH7712 BUG */
1620                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1621                         /* tx dma start */
1622                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1623                 }
1624                 /* wakeup */
1625                 netif_wake_queue(ndev);
1626         }
1627 }
1628
1629 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1630 {
1631         struct net_device *ndev = netdev;
1632         struct sh_eth_private *mdp = netdev_priv(ndev);
1633         struct sh_eth_cpu_data *cd = mdp->cd;
1634         irqreturn_t ret = IRQ_NONE;
1635         unsigned long intr_status;
1636
1637         spin_lock(&mdp->lock);
1638
1639         /* Get interrupt status */
1640         intr_status = sh_eth_read(ndev, EESR);
1641         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1642          * enabled since it's the one that  comes thru regardless of the mask,
1643          * and we need to fully handle it in sh_eth_error() in order to quench
1644          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1645          */
1646         intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
1647         /* Clear interrupt */
1648         if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1649                         EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1650                         cd->tx_check | cd->eesr_err_check)) {
1651                 sh_eth_write(ndev, intr_status, EESR);
1652                 ret = IRQ_HANDLED;
1653         } else
1654                 goto other_irq;
1655
1656         if (intr_status & (EESR_FRC | /* Frame recv*/
1657                         EESR_RMAF | /* Multi cast address recv*/
1658                         EESR_RRF  | /* Bit frame recv */
1659                         EESR_RTLF | /* Long frame recv*/
1660                         EESR_RTSF | /* short frame recv */
1661                         EESR_PRE  | /* PHY-LSI recv error */
1662                         EESR_CERF)){ /* recv frame CRC error */
1663                 sh_eth_rx(ndev, intr_status);
1664         }
1665
1666         /* Tx Check */
1667         if (intr_status & cd->tx_check) {
1668                 sh_eth_txfree(ndev);
1669                 netif_wake_queue(ndev);
1670         }
1671
1672         if (intr_status & cd->eesr_err_check)
1673                 sh_eth_error(ndev, intr_status);
1674
1675 other_irq:
1676         spin_unlock(&mdp->lock);
1677
1678         return ret;
1679 }
1680
1681 /* PHY state control function */
1682 static void sh_eth_adjust_link(struct net_device *ndev)
1683 {
1684         struct sh_eth_private *mdp = netdev_priv(ndev);
1685         struct phy_device *phydev = mdp->phydev;
1686         int new_state = 0;
1687
1688         if (phydev->link) {
1689                 if (phydev->duplex != mdp->duplex) {
1690                         new_state = 1;
1691                         mdp->duplex = phydev->duplex;
1692                         if (mdp->cd->set_duplex)
1693                                 mdp->cd->set_duplex(ndev);
1694                 }
1695
1696                 if (phydev->speed != mdp->speed) {
1697                         new_state = 1;
1698                         mdp->speed = phydev->speed;
1699                         if (mdp->cd->set_rate)
1700                                 mdp->cd->set_rate(ndev);
1701                 }
1702                 if (!mdp->link) {
1703                         sh_eth_write(ndev,
1704                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1705                         new_state = 1;
1706                         mdp->link = phydev->link;
1707                         if (mdp->cd->no_psr || mdp->no_ether_link)
1708                                 sh_eth_rcv_snd_enable(ndev);
1709                 }
1710         } else if (mdp->link) {
1711                 new_state = 1;
1712                 mdp->link = 0;
1713                 mdp->speed = 0;
1714                 mdp->duplex = -1;
1715                 if (mdp->cd->no_psr || mdp->no_ether_link)
1716                         sh_eth_rcv_snd_disable(ndev);
1717         }
1718
1719         if (new_state && netif_msg_link(mdp))
1720                 phy_print_status(phydev);
1721 }
1722
1723 /* PHY init function */
1724 static int sh_eth_phy_init(struct net_device *ndev)
1725 {
1726         struct sh_eth_private *mdp = netdev_priv(ndev);
1727         char phy_id[MII_BUS_ID_SIZE + 3];
1728         struct phy_device *phydev = NULL;
1729
1730         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1731                 mdp->mii_bus->id , mdp->phy_id);
1732
1733         mdp->link = 0;
1734         mdp->speed = 0;
1735         mdp->duplex = -1;
1736
1737         /* Try connect to PHY */
1738         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1739                              mdp->phy_interface);
1740         if (IS_ERR(phydev)) {
1741                 dev_err(&ndev->dev, "phy_connect failed\n");
1742                 return PTR_ERR(phydev);
1743         }
1744
1745         dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1746                 phydev->addr, phydev->drv->name);
1747
1748         mdp->phydev = phydev;
1749
1750         return 0;
1751 }
1752
1753 /* PHY control start function */
1754 static int sh_eth_phy_start(struct net_device *ndev)
1755 {
1756         struct sh_eth_private *mdp = netdev_priv(ndev);
1757         int ret;
1758
1759         ret = sh_eth_phy_init(ndev);
1760         if (ret)
1761                 return ret;
1762
1763         /* reset phy - this also wakes it from PDOWN */
1764         phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1765         phy_start(mdp->phydev);
1766
1767         return 0;
1768 }
1769
1770 static int sh_eth_get_settings(struct net_device *ndev,
1771                         struct ethtool_cmd *ecmd)
1772 {
1773         struct sh_eth_private *mdp = netdev_priv(ndev);
1774         unsigned long flags;
1775         int ret;
1776
1777         spin_lock_irqsave(&mdp->lock, flags);
1778         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1779         spin_unlock_irqrestore(&mdp->lock, flags);
1780
1781         return ret;
1782 }
1783
1784 static int sh_eth_set_settings(struct net_device *ndev,
1785                 struct ethtool_cmd *ecmd)
1786 {
1787         struct sh_eth_private *mdp = netdev_priv(ndev);
1788         unsigned long flags;
1789         int ret;
1790
1791         spin_lock_irqsave(&mdp->lock, flags);
1792
1793         /* disable tx and rx */
1794         sh_eth_rcv_snd_disable(ndev);
1795
1796         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1797         if (ret)
1798                 goto error_exit;
1799
1800         if (ecmd->duplex == DUPLEX_FULL)
1801                 mdp->duplex = 1;
1802         else
1803                 mdp->duplex = 0;
1804
1805         if (mdp->cd->set_duplex)
1806                 mdp->cd->set_duplex(ndev);
1807
1808 error_exit:
1809         mdelay(1);
1810
1811         /* enable tx and rx */
1812         sh_eth_rcv_snd_enable(ndev);
1813
1814         spin_unlock_irqrestore(&mdp->lock, flags);
1815
1816         return ret;
1817 }
1818
1819 static int sh_eth_nway_reset(struct net_device *ndev)
1820 {
1821         struct sh_eth_private *mdp = netdev_priv(ndev);
1822         unsigned long flags;
1823         int ret;
1824
1825         spin_lock_irqsave(&mdp->lock, flags);
1826         ret = phy_start_aneg(mdp->phydev);
1827         spin_unlock_irqrestore(&mdp->lock, flags);
1828
1829         return ret;
1830 }
1831
1832 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1833 {
1834         struct sh_eth_private *mdp = netdev_priv(ndev);
1835         return mdp->msg_enable;
1836 }
1837
1838 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1839 {
1840         struct sh_eth_private *mdp = netdev_priv(ndev);
1841         mdp->msg_enable = value;
1842 }
1843
1844 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1845         "rx_current", "tx_current",
1846         "rx_dirty", "tx_dirty",
1847 };
1848 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1849
1850 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1851 {
1852         switch (sset) {
1853         case ETH_SS_STATS:
1854                 return SH_ETH_STATS_LEN;
1855         default:
1856                 return -EOPNOTSUPP;
1857         }
1858 }
1859
1860 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1861                         struct ethtool_stats *stats, u64 *data)
1862 {
1863         struct sh_eth_private *mdp = netdev_priv(ndev);
1864         int i = 0;
1865
1866         /* device-specific stats */
1867         data[i++] = mdp->cur_rx;
1868         data[i++] = mdp->cur_tx;
1869         data[i++] = mdp->dirty_rx;
1870         data[i++] = mdp->dirty_tx;
1871 }
1872
1873 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1874 {
1875         switch (stringset) {
1876         case ETH_SS_STATS:
1877                 memcpy(data, *sh_eth_gstrings_stats,
1878                                         sizeof(sh_eth_gstrings_stats));
1879                 break;
1880         }
1881 }
1882
1883 static void sh_eth_get_ringparam(struct net_device *ndev,
1884                                  struct ethtool_ringparam *ring)
1885 {
1886         struct sh_eth_private *mdp = netdev_priv(ndev);
1887
1888         ring->rx_max_pending = RX_RING_MAX;
1889         ring->tx_max_pending = TX_RING_MAX;
1890         ring->rx_pending = mdp->num_rx_ring;
1891         ring->tx_pending = mdp->num_tx_ring;
1892 }
1893
1894 static int sh_eth_set_ringparam(struct net_device *ndev,
1895                                 struct ethtool_ringparam *ring)
1896 {
1897         struct sh_eth_private *mdp = netdev_priv(ndev);
1898         int ret;
1899
1900         if (ring->tx_pending > TX_RING_MAX ||
1901             ring->rx_pending > RX_RING_MAX ||
1902             ring->tx_pending < TX_RING_MIN ||
1903             ring->rx_pending < RX_RING_MIN)
1904                 return -EINVAL;
1905         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1906                 return -EINVAL;
1907
1908         if (netif_running(ndev)) {
1909                 netif_tx_disable(ndev);
1910                 /* Disable interrupts by clearing the interrupt mask. */
1911                 sh_eth_write(ndev, 0x0000, EESIPR);
1912                 /* Stop the chip's Tx and Rx processes. */
1913                 sh_eth_write(ndev, 0, EDTRR);
1914                 sh_eth_write(ndev, 0, EDRRR);
1915                 synchronize_irq(ndev->irq);
1916         }
1917
1918         /* Free all the skbuffs in the Rx queue. */
1919         sh_eth_ring_free(ndev);
1920         /* Free DMA buffer */
1921         sh_eth_free_dma_buffer(mdp);
1922
1923         /* Set new parameters */
1924         mdp->num_rx_ring = ring->rx_pending;
1925         mdp->num_tx_ring = ring->tx_pending;
1926
1927         ret = sh_eth_ring_init(ndev);
1928         if (ret < 0) {
1929                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1930                 return ret;
1931         }
1932         ret = sh_eth_dev_init(ndev, false);
1933         if (ret < 0) {
1934                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1935                 return ret;
1936         }
1937
1938         if (netif_running(ndev)) {
1939                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1940                 /* Setting the Rx mode will start the Rx process. */
1941                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1942                 netif_wake_queue(ndev);
1943         }
1944
1945         return 0;
1946 }
1947
1948 static const struct ethtool_ops sh_eth_ethtool_ops = {
1949         .get_settings   = sh_eth_get_settings,
1950         .set_settings   = sh_eth_set_settings,
1951         .nway_reset     = sh_eth_nway_reset,
1952         .get_msglevel   = sh_eth_get_msglevel,
1953         .set_msglevel   = sh_eth_set_msglevel,
1954         .get_link       = ethtool_op_get_link,
1955         .get_strings    = sh_eth_get_strings,
1956         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1957         .get_sset_count     = sh_eth_get_sset_count,
1958         .get_ringparam  = sh_eth_get_ringparam,
1959         .set_ringparam  = sh_eth_set_ringparam,
1960 };
1961
1962 /* network device open function */
1963 static int sh_eth_open(struct net_device *ndev)
1964 {
1965         int ret = 0;
1966         struct sh_eth_private *mdp = netdev_priv(ndev);
1967
1968         pm_runtime_get_sync(&mdp->pdev->dev);
1969
1970         ret = request_irq(ndev->irq, sh_eth_interrupt,
1971 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1972         defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1973         defined(CONFIG_CPU_SUBTYPE_SH7757)
1974                                 IRQF_SHARED,
1975 #else
1976                                 0,
1977 #endif
1978                                 ndev->name, ndev);
1979         if (ret) {
1980                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1981                 return ret;
1982         }
1983
1984         /* Descriptor set */
1985         ret = sh_eth_ring_init(ndev);
1986         if (ret)
1987                 goto out_free_irq;
1988
1989         /* device init */
1990         ret = sh_eth_dev_init(ndev, true);
1991         if (ret)
1992                 goto out_free_irq;
1993
1994         /* PHY control start*/
1995         ret = sh_eth_phy_start(ndev);
1996         if (ret)
1997                 goto out_free_irq;
1998
1999         return ret;
2000
2001 out_free_irq:
2002         free_irq(ndev->irq, ndev);
2003         pm_runtime_put_sync(&mdp->pdev->dev);
2004         return ret;
2005 }
2006
2007 /* Timeout function */
2008 static void sh_eth_tx_timeout(struct net_device *ndev)
2009 {
2010         struct sh_eth_private *mdp = netdev_priv(ndev);
2011         struct sh_eth_rxdesc *rxdesc;
2012         int i;
2013
2014         netif_stop_queue(ndev);
2015
2016         if (netif_msg_timer(mdp))
2017                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
2018                " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
2019
2020         /* tx_errors count up */
2021         ndev->stats.tx_errors++;
2022
2023         /* Free all the skbuffs in the Rx queue. */
2024         for (i = 0; i < mdp->num_rx_ring; i++) {
2025                 rxdesc = &mdp->rx_ring[i];
2026                 rxdesc->status = 0;
2027                 rxdesc->addr = 0xBADF00D0;
2028                 if (mdp->rx_skbuff[i])
2029                         dev_kfree_skb(mdp->rx_skbuff[i]);
2030                 mdp->rx_skbuff[i] = NULL;
2031         }
2032         for (i = 0; i < mdp->num_tx_ring; i++) {
2033                 if (mdp->tx_skbuff[i])
2034                         dev_kfree_skb(mdp->tx_skbuff[i]);
2035                 mdp->tx_skbuff[i] = NULL;
2036         }
2037
2038         /* device init */
2039         sh_eth_dev_init(ndev, true);
2040 }
2041
2042 /* Packet transmit function */
2043 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2044 {
2045         struct sh_eth_private *mdp = netdev_priv(ndev);
2046         struct sh_eth_txdesc *txdesc;
2047         u32 entry;
2048         unsigned long flags;
2049
2050         spin_lock_irqsave(&mdp->lock, flags);
2051         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2052                 if (!sh_eth_txfree(ndev)) {
2053                         if (netif_msg_tx_queued(mdp))
2054                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
2055                         netif_stop_queue(ndev);
2056                         spin_unlock_irqrestore(&mdp->lock, flags);
2057                         return NETDEV_TX_BUSY;
2058                 }
2059         }
2060         spin_unlock_irqrestore(&mdp->lock, flags);
2061
2062         entry = mdp->cur_tx % mdp->num_tx_ring;
2063         mdp->tx_skbuff[entry] = skb;
2064         txdesc = &mdp->tx_ring[entry];
2065         /* soft swap. */
2066         if (!mdp->cd->hw_swap)
2067                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2068                                  skb->len + 2);
2069         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2070                                       DMA_TO_DEVICE);
2071         if (skb->len < ETHERSMALL)
2072                 txdesc->buffer_length = ETHERSMALL;
2073         else
2074                 txdesc->buffer_length = skb->len;
2075
2076         if (entry >= mdp->num_tx_ring - 1)
2077                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2078         else
2079                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2080
2081         mdp->cur_tx++;
2082
2083         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2084                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2085
2086         return NETDEV_TX_OK;
2087 }
2088
2089 /* device close function */
2090 static int sh_eth_close(struct net_device *ndev)
2091 {
2092         struct sh_eth_private *mdp = netdev_priv(ndev);
2093
2094         netif_stop_queue(ndev);
2095
2096         /* Disable interrupts by clearing the interrupt mask. */
2097         sh_eth_write(ndev, 0x0000, EESIPR);
2098
2099         /* Stop the chip's Tx and Rx processes. */
2100         sh_eth_write(ndev, 0, EDTRR);
2101         sh_eth_write(ndev, 0, EDRRR);
2102
2103         /* PHY Disconnect */
2104         if (mdp->phydev) {
2105                 phy_stop(mdp->phydev);
2106                 phy_disconnect(mdp->phydev);
2107         }
2108
2109         free_irq(ndev->irq, ndev);
2110
2111         /* Free all the skbuffs in the Rx queue. */
2112         sh_eth_ring_free(ndev);
2113
2114         /* free DMA buffer */
2115         sh_eth_free_dma_buffer(mdp);
2116
2117         pm_runtime_put_sync(&mdp->pdev->dev);
2118
2119         return 0;
2120 }
2121
2122 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2123 {
2124         struct sh_eth_private *mdp = netdev_priv(ndev);
2125
2126         pm_runtime_get_sync(&mdp->pdev->dev);
2127
2128         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2129         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2130         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2131         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2132         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2133         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2134         if (sh_eth_is_gether(mdp)) {
2135                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2136                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2137                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2138                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2139         } else {
2140                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2141                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2142         }
2143         pm_runtime_put_sync(&mdp->pdev->dev);
2144
2145         return &ndev->stats;
2146 }
2147
2148 /* ioctl to device function */
2149 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2150                                 int cmd)
2151 {
2152         struct sh_eth_private *mdp = netdev_priv(ndev);
2153         struct phy_device *phydev = mdp->phydev;
2154
2155         if (!netif_running(ndev))
2156                 return -EINVAL;
2157
2158         if (!phydev)
2159                 return -ENODEV;
2160
2161         return phy_mii_ioctl(phydev, rq, cmd);
2162 }
2163
2164 #if defined(SH_ETH_HAS_TSU)
2165 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2166 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2167                                             int entry)
2168 {
2169         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2170 }
2171
2172 static u32 sh_eth_tsu_get_post_mask(int entry)
2173 {
2174         return 0x0f << (28 - ((entry % 8) * 4));
2175 }
2176
2177 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2178 {
2179         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2180 }
2181
2182 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2183                                              int entry)
2184 {
2185         struct sh_eth_private *mdp = netdev_priv(ndev);
2186         u32 tmp;
2187         void *reg_offset;
2188
2189         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2190         tmp = ioread32(reg_offset);
2191         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2192 }
2193
2194 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2195                                               int entry)
2196 {
2197         struct sh_eth_private *mdp = netdev_priv(ndev);
2198         u32 post_mask, ref_mask, tmp;
2199         void *reg_offset;
2200
2201         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2202         post_mask = sh_eth_tsu_get_post_mask(entry);
2203         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2204
2205         tmp = ioread32(reg_offset);
2206         iowrite32(tmp & ~post_mask, reg_offset);
2207
2208         /* If other port enables, the function returns "true" */
2209         return tmp & ref_mask;
2210 }
2211
2212 static int sh_eth_tsu_busy(struct net_device *ndev)
2213 {
2214         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2215         struct sh_eth_private *mdp = netdev_priv(ndev);
2216
2217         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2218                 udelay(10);
2219                 timeout--;
2220                 if (timeout <= 0) {
2221                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2222                         return -ETIMEDOUT;
2223                 }
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2230                                   const u8 *addr)
2231 {
2232         u32 val;
2233
2234         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2235         iowrite32(val, reg);
2236         if (sh_eth_tsu_busy(ndev) < 0)
2237                 return -EBUSY;
2238
2239         val = addr[4] << 8 | addr[5];
2240         iowrite32(val, reg + 4);
2241         if (sh_eth_tsu_busy(ndev) < 0)
2242                 return -EBUSY;
2243
2244         return 0;
2245 }
2246
2247 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2248 {
2249         u32 val;
2250
2251         val = ioread32(reg);
2252         addr[0] = (val >> 24) & 0xff;
2253         addr[1] = (val >> 16) & 0xff;
2254         addr[2] = (val >> 8) & 0xff;
2255         addr[3] = val & 0xff;
2256         val = ioread32(reg + 4);
2257         addr[4] = (val >> 8) & 0xff;
2258         addr[5] = val & 0xff;
2259 }
2260
2261
2262 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2263 {
2264         struct sh_eth_private *mdp = netdev_priv(ndev);
2265         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2266         int i;
2267         u8 c_addr[ETH_ALEN];
2268
2269         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2270                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2271                 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2272                         return i;
2273         }
2274
2275         return -ENOENT;
2276 }
2277
2278 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2279 {
2280         u8 blank[ETH_ALEN];
2281         int entry;
2282
2283         memset(blank, 0, sizeof(blank));
2284         entry = sh_eth_tsu_find_entry(ndev, blank);
2285         return (entry < 0) ? -ENOMEM : entry;
2286 }
2287
2288 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2289                                               int entry)
2290 {
2291         struct sh_eth_private *mdp = netdev_priv(ndev);
2292         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2293         int ret;
2294         u8 blank[ETH_ALEN];
2295
2296         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2297                          ~(1 << (31 - entry)), TSU_TEN);
2298
2299         memset(blank, 0, sizeof(blank));
2300         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2301         if (ret < 0)
2302                 return ret;
2303         return 0;
2304 }
2305
2306 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2307 {
2308         struct sh_eth_private *mdp = netdev_priv(ndev);
2309         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2310         int i, ret;
2311
2312         if (!mdp->cd->tsu)
2313                 return 0;
2314
2315         i = sh_eth_tsu_find_entry(ndev, addr);
2316         if (i < 0) {
2317                 /* No entry found, create one */
2318                 i = sh_eth_tsu_find_empty(ndev);
2319                 if (i < 0)
2320                         return -ENOMEM;
2321                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2322                 if (ret < 0)
2323                         return ret;
2324
2325                 /* Enable the entry */
2326                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2327                                  (1 << (31 - i)), TSU_TEN);
2328         }
2329
2330         /* Entry found or created, enable POST */
2331         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2332
2333         return 0;
2334 }
2335
2336 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2337 {
2338         struct sh_eth_private *mdp = netdev_priv(ndev);
2339         int i, ret;
2340
2341         if (!mdp->cd->tsu)
2342                 return 0;
2343
2344         i = sh_eth_tsu_find_entry(ndev, addr);
2345         if (i) {
2346                 /* Entry found */
2347                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2348                         goto done;
2349
2350                 /* Disable the entry if both ports was disabled */
2351                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2352                 if (ret < 0)
2353                         return ret;
2354         }
2355 done:
2356         return 0;
2357 }
2358
2359 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2360 {
2361         struct sh_eth_private *mdp = netdev_priv(ndev);
2362         int i, ret;
2363
2364         if (unlikely(!mdp->cd->tsu))
2365                 return 0;
2366
2367         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2368                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2369                         continue;
2370
2371                 /* Disable the entry if both ports was disabled */
2372                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2373                 if (ret < 0)
2374                         return ret;
2375         }
2376
2377         return 0;
2378 }
2379
2380 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2381 {
2382         struct sh_eth_private *mdp = netdev_priv(ndev);
2383         u8 addr[ETH_ALEN];
2384         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2385         int i;
2386
2387         if (unlikely(!mdp->cd->tsu))
2388                 return;
2389
2390         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2391                 sh_eth_tsu_read_entry(reg_offset, addr);
2392                 if (is_multicast_ether_addr(addr))
2393                         sh_eth_tsu_del_entry(ndev, addr);
2394         }
2395 }
2396
2397 /* Multicast reception directions set */
2398 static void sh_eth_set_multicast_list(struct net_device *ndev)
2399 {
2400         struct sh_eth_private *mdp = netdev_priv(ndev);
2401         u32 ecmr_bits;
2402         int mcast_all = 0;
2403         unsigned long flags;
2404
2405         spin_lock_irqsave(&mdp->lock, flags);
2406         /*
2407          * Initial condition is MCT = 1, PRM = 0.
2408          * Depending on ndev->flags, set PRM or clear MCT
2409          */
2410         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2411
2412         if (!(ndev->flags & IFF_MULTICAST)) {
2413                 sh_eth_tsu_purge_mcast(ndev);
2414                 mcast_all = 1;
2415         }
2416         if (ndev->flags & IFF_ALLMULTI) {
2417                 sh_eth_tsu_purge_mcast(ndev);
2418                 ecmr_bits &= ~ECMR_MCT;
2419                 mcast_all = 1;
2420         }
2421
2422         if (ndev->flags & IFF_PROMISC) {
2423                 sh_eth_tsu_purge_all(ndev);
2424                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2425         } else if (mdp->cd->tsu) {
2426                 struct netdev_hw_addr *ha;
2427                 netdev_for_each_mc_addr(ha, ndev) {
2428                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2429                                 continue;
2430
2431                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2432                                 if (!mcast_all) {
2433                                         sh_eth_tsu_purge_mcast(ndev);
2434                                         ecmr_bits &= ~ECMR_MCT;
2435                                         mcast_all = 1;
2436                                 }
2437                         }
2438                 }
2439         } else {
2440                 /* Normal, unicast/broadcast-only mode. */
2441                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2442         }
2443
2444         /* update the ethernet mode */
2445         sh_eth_write(ndev, ecmr_bits, ECMR);
2446
2447         spin_unlock_irqrestore(&mdp->lock, flags);
2448 }
2449
2450 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2451 {
2452         if (!mdp->port)
2453                 return TSU_VTAG0;
2454         else
2455                 return TSU_VTAG1;
2456 }
2457
2458 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2459                                   __be16 proto, u16 vid)
2460 {
2461         struct sh_eth_private *mdp = netdev_priv(ndev);
2462         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2463
2464         if (unlikely(!mdp->cd->tsu))
2465                 return -EPERM;
2466
2467         /* No filtering if vid = 0 */
2468         if (!vid)
2469                 return 0;
2470
2471         mdp->vlan_num_ids++;
2472
2473         /*
2474          * The controller has one VLAN tag HW filter. So, if the filter is
2475          * already enabled, the driver disables it and the filte
2476          */
2477         if (mdp->vlan_num_ids > 1) {
2478                 /* disable VLAN filter */
2479                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2480                 return 0;
2481         }
2482
2483         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2484                          vtag_reg_index);
2485
2486         return 0;
2487 }
2488
2489 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2490                                    __be16 proto, u16 vid)
2491 {
2492         struct sh_eth_private *mdp = netdev_priv(ndev);
2493         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2494
2495         if (unlikely(!mdp->cd->tsu))
2496                 return -EPERM;
2497
2498         /* No filtering if vid = 0 */
2499         if (!vid)
2500                 return 0;
2501
2502         mdp->vlan_num_ids--;
2503         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2504
2505         return 0;
2506 }
2507 #endif /* SH_ETH_HAS_TSU */
2508
2509 /* SuperH's TSU register init function */
2510 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2511 {
2512         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2513         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2514         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2515         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2516         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2517         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2518         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2519         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2520         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2521         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2522         if (sh_eth_is_gether(mdp)) {
2523                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2524                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2525         } else {
2526                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2527                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2528         }
2529         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2530         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2531         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2532         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2533         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2534         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2535         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2536 }
2537
2538 /* MDIO bus release function */
2539 static int sh_mdio_release(struct net_device *ndev)
2540 {
2541         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2542
2543         /* unregister mdio bus */
2544         mdiobus_unregister(bus);
2545
2546         /* remove mdio bus info from net_device */
2547         dev_set_drvdata(&ndev->dev, NULL);
2548
2549         /* free bitbang info */
2550         free_mdio_bitbang(bus);
2551
2552         return 0;
2553 }
2554
2555 /* MDIO bus init function */
2556 static int sh_mdio_init(struct net_device *ndev, int id,
2557                         struct sh_eth_plat_data *pd)
2558 {
2559         int ret, i;
2560         struct bb_info *bitbang;
2561         struct sh_eth_private *mdp = netdev_priv(ndev);
2562
2563         /* create bit control struct for PHY */
2564         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2565                                GFP_KERNEL);
2566         if (!bitbang) {
2567                 ret = -ENOMEM;
2568                 goto out;
2569         }
2570
2571         /* bitbang init */
2572         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2573         bitbang->set_gate = pd->set_mdio_gate;
2574         bitbang->mdi_msk = PIR_MDI;
2575         bitbang->mdo_msk = PIR_MDO;
2576         bitbang->mmd_msk = PIR_MMD;
2577         bitbang->mdc_msk = PIR_MDC;
2578         bitbang->ctrl.ops = &bb_ops;
2579
2580         /* MII controller setting */
2581         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2582         if (!mdp->mii_bus) {
2583                 ret = -ENOMEM;
2584                 goto out;
2585         }
2586
2587         /* Hook up MII support for ethtool */
2588         mdp->mii_bus->name = "sh_mii";
2589         mdp->mii_bus->parent = &ndev->dev;
2590         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2591                 mdp->pdev->name, id);
2592
2593         /* PHY IRQ */
2594         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2595                                          sizeof(int) * PHY_MAX_ADDR,
2596                                          GFP_KERNEL);
2597         if (!mdp->mii_bus->irq) {
2598                 ret = -ENOMEM;
2599                 goto out_free_bus;
2600         }
2601
2602         for (i = 0; i < PHY_MAX_ADDR; i++)
2603                 mdp->mii_bus->irq[i] = PHY_POLL;
2604
2605         /* register mdio bus */
2606         ret = mdiobus_register(mdp->mii_bus);
2607         if (ret)
2608                 goto out_free_bus;
2609
2610         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2611
2612         return 0;
2613
2614 out_free_bus:
2615         free_mdio_bitbang(mdp->mii_bus);
2616
2617 out:
2618         return ret;
2619 }
2620
2621 static const u16 *sh_eth_get_register_offset(int register_type)
2622 {
2623         const u16 *reg_offset = NULL;
2624
2625         switch (register_type) {
2626         case SH_ETH_REG_GIGABIT:
2627                 reg_offset = sh_eth_offset_gigabit;
2628                 break;
2629         case SH_ETH_REG_FAST_RCAR:
2630                 reg_offset = sh_eth_offset_fast_rcar;
2631                 break;
2632         case SH_ETH_REG_FAST_SH4:
2633                 reg_offset = sh_eth_offset_fast_sh4;
2634                 break;
2635         case SH_ETH_REG_FAST_SH3_SH2:
2636                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2637                 break;
2638         default:
2639                 pr_err("Unknown register type (%d)\n", register_type);
2640                 break;
2641         }
2642
2643         return reg_offset;
2644 }
2645
2646 static const struct net_device_ops sh_eth_netdev_ops = {
2647         .ndo_open               = sh_eth_open,
2648         .ndo_stop               = sh_eth_close,
2649         .ndo_start_xmit         = sh_eth_start_xmit,
2650         .ndo_get_stats          = sh_eth_get_stats,
2651 #if defined(SH_ETH_HAS_TSU)
2652         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2653         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2654         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2655 #endif
2656         .ndo_tx_timeout         = sh_eth_tx_timeout,
2657         .ndo_do_ioctl           = sh_eth_do_ioctl,
2658         .ndo_validate_addr      = eth_validate_addr,
2659         .ndo_set_mac_address    = eth_mac_addr,
2660         .ndo_change_mtu         = eth_change_mtu,
2661 };
2662
2663 static int sh_eth_drv_probe(struct platform_device *pdev)
2664 {
2665         int ret, devno = 0;
2666         struct resource *res;
2667         struct net_device *ndev = NULL;
2668         struct sh_eth_private *mdp = NULL;
2669         struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2670
2671         /* get base addr */
2672         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2673         if (unlikely(res == NULL)) {
2674                 dev_err(&pdev->dev, "invalid resource\n");
2675                 ret = -EINVAL;
2676                 goto out;
2677         }
2678
2679         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2680         if (!ndev) {
2681                 ret = -ENOMEM;
2682                 goto out;
2683         }
2684
2685         /* The sh Ether-specific entries in the device structure. */
2686         ndev->base_addr = res->start;
2687         devno = pdev->id;
2688         if (devno < 0)
2689                 devno = 0;
2690
2691         ndev->dma = -1;
2692         ret = platform_get_irq(pdev, 0);
2693         if (ret < 0) {
2694                 ret = -ENODEV;
2695                 goto out_release;
2696         }
2697         ndev->irq = ret;
2698
2699         SET_NETDEV_DEV(ndev, &pdev->dev);
2700
2701         /* Fill in the fields of the device structure with ethernet values. */
2702         ether_setup(ndev);
2703
2704         mdp = netdev_priv(ndev);
2705         mdp->num_tx_ring = TX_RING_SIZE;
2706         mdp->num_rx_ring = RX_RING_SIZE;
2707         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2708         if (IS_ERR(mdp->addr)) {
2709                 ret = PTR_ERR(mdp->addr);
2710                 goto out_release;
2711         }
2712
2713         spin_lock_init(&mdp->lock);
2714         mdp->pdev = pdev;
2715         pm_runtime_enable(&pdev->dev);
2716         pm_runtime_resume(&pdev->dev);
2717
2718         /* get PHY ID */
2719         mdp->phy_id = pd->phy;
2720         mdp->phy_interface = pd->phy_interface;
2721         /* EDMAC endian */
2722         mdp->edmac_endian = pd->edmac_endian;
2723         mdp->no_ether_link = pd->no_ether_link;
2724         mdp->ether_link_active_low = pd->ether_link_active_low;
2725         mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2726
2727         /* set cpu data */
2728 #if defined(SH_ETH_HAS_BOTH_MODULES)
2729         mdp->cd = sh_eth_get_cpu_data(mdp);
2730 #else
2731         mdp->cd = &sh_eth_my_cpu_data;
2732 #endif
2733         sh_eth_set_default_cpu_data(mdp->cd);
2734
2735         /* set function */
2736         ndev->netdev_ops = &sh_eth_netdev_ops;
2737         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2738         ndev->watchdog_timeo = TX_TIMEOUT;
2739
2740         /* debug message level */
2741         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2742
2743         /* read and set MAC address */
2744         read_mac_address(ndev, pd->mac_addr);
2745         if (!is_valid_ether_addr(ndev->dev_addr)) {
2746                 dev_warn(&pdev->dev,
2747                          "no valid MAC address supplied, using a random one.\n");
2748                 eth_hw_addr_random(ndev);
2749         }
2750
2751         /* ioremap the TSU registers */
2752         if (mdp->cd->tsu) {
2753                 struct resource *rtsu;
2754                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2755                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2756                 if (IS_ERR(mdp->tsu_addr)) {
2757                         ret = PTR_ERR(mdp->tsu_addr);
2758                         goto out_release;
2759                 }
2760                 mdp->port = devno % 2;
2761                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2762         }
2763
2764         /* initialize first or needed device */
2765         if (!devno || pd->needs_init) {
2766                 if (mdp->cd->chip_reset)
2767                         mdp->cd->chip_reset(ndev);
2768
2769                 if (mdp->cd->tsu) {
2770                         /* TSU init (Init only)*/
2771                         sh_eth_tsu_init(mdp);
2772                 }
2773         }
2774
2775         /* network device register */
2776         ret = register_netdev(ndev);
2777         if (ret)
2778                 goto out_release;
2779
2780         /* mdio bus init */
2781         ret = sh_mdio_init(ndev, pdev->id, pd);
2782         if (ret)
2783                 goto out_unregister;
2784
2785         /* print device information */
2786         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2787                (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2788
2789         platform_set_drvdata(pdev, ndev);
2790
2791         return ret;
2792
2793 out_unregister:
2794         unregister_netdev(ndev);
2795
2796 out_release:
2797         /* net_dev free */
2798         if (ndev)
2799                 free_netdev(ndev);
2800
2801 out:
2802         return ret;
2803 }
2804
2805 static int sh_eth_drv_remove(struct platform_device *pdev)
2806 {
2807         struct net_device *ndev = platform_get_drvdata(pdev);
2808
2809         sh_mdio_release(ndev);
2810         unregister_netdev(ndev);
2811         pm_runtime_disable(&pdev->dev);
2812         free_netdev(ndev);
2813         platform_set_drvdata(pdev, NULL);
2814
2815         return 0;
2816 }
2817
2818 static int sh_eth_runtime_nop(struct device *dev)
2819 {
2820         /*
2821          * Runtime PM callback shared between ->runtime_suspend()
2822          * and ->runtime_resume(). Simply returns success.
2823          *
2824          * This driver re-initializes all registers after
2825          * pm_runtime_get_sync() anyway so there is no need
2826          * to save and restore registers here.
2827          */
2828         return 0;
2829 }
2830
2831 static struct dev_pm_ops sh_eth_dev_pm_ops = {
2832         .runtime_suspend = sh_eth_runtime_nop,
2833         .runtime_resume = sh_eth_runtime_nop,
2834 };
2835
2836 static struct platform_driver sh_eth_driver = {
2837         .probe = sh_eth_drv_probe,
2838         .remove = sh_eth_drv_remove,
2839         .driver = {
2840                    .name = CARDNAME,
2841                    .pm = &sh_eth_dev_pm_ops,
2842         },
2843 };
2844
2845 module_platform_driver(sh_eth_driver);
2846
2847 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2848 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2849 MODULE_LICENSE("GPL v2");