drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014 Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/sh_eth.h>
  44 #include <linux/of_mdio.h>
  45
  46 #include "sh_eth.h"
  47
  48 #define SH_ETH_DEF_MSG_ENABLE \
  49                 (NETIF_MSG_LINK | \
  50                 NETIF_MSG_TIMER | \
  51                 NETIF_MSG_RX_ERR| \
  52                 NETIF_MSG_TX_ERR)
  53
  54 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  55
  56 #define SH_ETH_OFFSET_DEFAULTS                  \
  57         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  58
  59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  60         SH_ETH_OFFSET_DEFAULTS,
  61
  62         [EDSR]          = 0x0000,
  63         [EDMR]          = 0x0400,
  64         [EDTRR]         = 0x0408,
  65         [EDRRR]         = 0x0410,
  66         [EESR]          = 0x0428,
  67         [EESIPR]        = 0x0430,
  68         [TDLAR]         = 0x0010,
  69         [TDFAR]         = 0x0014,
  70         [TDFXR]         = 0x0018,
  71         [TDFFR]         = 0x001c,
  72         [RDLAR]         = 0x0030,
  73         [RDFAR]         = 0x0034,
  74         [RDFXR]         = 0x0038,
  75         [RDFFR]         = 0x003c,
  76         [TRSCER]        = 0x0438,
  77         [RMFCR]         = 0x0440,
  78         [TFTR]          = 0x0448,
  79         [FDR]           = 0x0450,
  80         [RMCR]          = 0x0458,
  81         [RPADIR]        = 0x0460,
  82         [FCFTR]         = 0x0468,
  83         [CSMR]          = 0x04E4,
  84
  85         [ECMR]          = 0x0500,
  86         [ECSR]          = 0x0510,
  87         [ECSIPR]        = 0x0518,
  88         [PIR]           = 0x0520,
  89         [PSR]           = 0x0528,
  90         [PIPR]          = 0x052c,
  91         [RFLR]          = 0x0508,
  92         [APR]           = 0x0554,
  93         [MPR]           = 0x0558,
  94         [PFTCR]         = 0x055c,
  95         [PFRCR]         = 0x0560,
  96         [TPAUSER]       = 0x0564,
  97         [GECMR]         = 0x05b0,
  98         [BCULR]         = 0x05b4,
  99         [MAHR]          = 0x05c0,
 100         [MALR]          = 0x05c8,
 101         [TROCR]         = 0x0700,
 102         [CDCR]          = 0x0708,
 103         [LCCR]          = 0x0710,
 104         [CEFCR]         = 0x0740,
 105         [FRECR]         = 0x0748,
 106         [TSFRCR]        = 0x0750,
 107         [TLFRCR]        = 0x0758,
 108         [RFCR]          = 0x0760,
 109         [CERCR]         = 0x0768,
 110         [CEECR]         = 0x0770,
 111         [MAFCR]         = 0x0778,
 112         [RMII_MII]      = 0x0790,
 113
 114         [ARSTR]         = 0x0000,
 115         [TSU_CTRST]     = 0x0004,
 116         [TSU_FWEN0]     = 0x0010,
 117         [TSU_FWEN1]     = 0x0014,
 118         [TSU_FCM]       = 0x0018,
 119         [TSU_BSYSL0]    = 0x0020,
 120         [TSU_BSYSL1]    = 0x0024,
 121         [TSU_PRISL0]    = 0x0028,
 122         [TSU_PRISL1]    = 0x002c,
 123         [TSU_FWSL0]     = 0x0030,
 124         [TSU_FWSL1]     = 0x0034,
 125         [TSU_FWSLC]     = 0x0038,
 126         [TSU_QTAGM0]    = 0x0040,
 127         [TSU_QTAGM1]    = 0x0044,
 128         [TSU_FWSR]      = 0x0050,
 129         [TSU_FWINMK]    = 0x0054,
 130         [TSU_ADQT0]     = 0x0048,
 131         [TSU_ADQT1]     = 0x004c,
 132         [TSU_VTAG0]     = 0x0058,
 133         [TSU_VTAG1]     = 0x005c,
 134         [TSU_ADSBSY]    = 0x0060,
 135         [TSU_TEN]       = 0x0064,
 136         [TSU_POST1]     = 0x0070,
 137         [TSU_POST2]     = 0x0074,
 138         [TSU_POST3]     = 0x0078,
 139         [TSU_POST4]     = 0x007c,
 140         [TSU_ADRH0]     = 0x0100,
 141
 142         [TXNLCR0]       = 0x0080,
 143         [TXALCR0]       = 0x0084,
 144         [RXNLCR0]       = 0x0088,
 145         [RXALCR0]       = 0x008c,
 146         [FWNLCR0]       = 0x0090,
 147         [FWALCR0]       = 0x0094,
 148         [TXNLCR1]       = 0x00a0,
 149         [TXALCR1]       = 0x00a4,
 150         [RXNLCR1]       = 0x00a8,
 151         [RXALCR1]       = 0x00ac,
 152         [FWNLCR1]       = 0x00b0,
 153         [FWALCR1]       = 0x00b4,
 154 };
 155
 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 157         SH_ETH_OFFSET_DEFAULTS,
 158
 159         [EDSR]          = 0x0000,
 160         [EDMR]          = 0x0400,
 161         [EDTRR]         = 0x0408,
 162         [EDRRR]         = 0x0410,
 163         [EESR]          = 0x0428,
 164         [EESIPR]        = 0x0430,
 165         [TDLAR]         = 0x0010,
 166         [TDFAR]         = 0x0014,
 167         [TDFXR]         = 0x0018,
 168         [TDFFR]         = 0x001c,
 169         [RDLAR]         = 0x0030,
 170         [RDFAR]         = 0x0034,
 171         [RDFXR]         = 0x0038,
 172         [RDFFR]         = 0x003c,
 173         [TRSCER]        = 0x0438,
 174         [RMFCR]         = 0x0440,
 175         [TFTR]          = 0x0448,
 176         [FDR]           = 0x0450,
 177         [RMCR]          = 0x0458,
 178         [RPADIR]        = 0x0460,
 179         [FCFTR]         = 0x0468,
 180         [CSMR]          = 0x04E4,
 181
 182         [ECMR]          = 0x0500,
 183         [RFLR]          = 0x0508,
 184         [ECSR]          = 0x0510,
 185         [ECSIPR]        = 0x0518,
 186         [PIR]           = 0x0520,
 187         [APR]           = 0x0554,
 188         [MPR]           = 0x0558,
 189         [PFTCR]         = 0x055c,
 190         [PFRCR]         = 0x0560,
 191         [TPAUSER]       = 0x0564,
 192         [MAHR]          = 0x05c0,
 193         [MALR]          = 0x05c8,
 194         [CEFCR]         = 0x0740,
 195         [FRECR]         = 0x0748,
 196         [TSFRCR]        = 0x0750,
 197         [TLFRCR]        = 0x0758,
 198         [RFCR]          = 0x0760,
 199         [MAFCR]         = 0x0778,
 200
 201         [ARSTR]         = 0x0000,
 202         [TSU_CTRST]     = 0x0004,
 203         [TSU_FWSLC]     = 0x0038,
 204         [TSU_VTAG0]     = 0x0058,
 205         [TSU_ADSBSY]    = 0x0060,
 206         [TSU_TEN]       = 0x0064,
 207         [TSU_POST1]     = 0x0070,
 208         [TSU_POST2]     = 0x0074,
 209         [TSU_POST3]     = 0x0078,
 210         [TSU_POST4]     = 0x007c,
 211         [TSU_ADRH0]     = 0x0100,
 212
 213         [TXNLCR0]       = 0x0080,
 214         [TXALCR0]       = 0x0084,
 215         [RXNLCR0]       = 0x0088,
 216         [RXALCR0]       = 0x008C,
 217 };
 218
 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 220         SH_ETH_OFFSET_DEFAULTS,
 221
 222         [ECMR]          = 0x0300,
 223         [RFLR]          = 0x0308,
 224         [ECSR]          = 0x0310,
 225         [ECSIPR]        = 0x0318,
 226         [PIR]           = 0x0320,
 227         [PSR]           = 0x0328,
 228         [RDMLR]         = 0x0340,
 229         [IPGR]          = 0x0350,
 230         [APR]           = 0x0354,
 231         [MPR]           = 0x0358,
 232         [RFCF]          = 0x0360,
 233         [TPAUSER]       = 0x0364,
 234         [TPAUSECR]      = 0x0368,
 235         [MAHR]          = 0x03c0,
 236         [MALR]          = 0x03c8,
 237         [TROCR]         = 0x03d0,
 238         [CDCR]          = 0x03d4,
 239         [LCCR]          = 0x03d8,
 240         [CNDCR]         = 0x03dc,
 241         [CEFCR]         = 0x03e4,
 242         [FRECR]         = 0x03e8,
 243         [TSFRCR]        = 0x03ec,
 244         [TLFRCR]        = 0x03f0,
 245         [RFCR]          = 0x03f4,
 246         [MAFCR]         = 0x03f8,
 247
 248         [EDMR]          = 0x0200,
 249         [EDTRR]         = 0x0208,
 250         [EDRRR]         = 0x0210,
 251         [TDLAR]         = 0x0218,
 252         [RDLAR]         = 0x0220,
 253         [EESR]          = 0x0228,
 254         [EESIPR]        = 0x0230,
 255         [TRSCER]        = 0x0238,
 256         [RMFCR]         = 0x0240,
 257         [TFTR]          = 0x0248,
 258         [FDR]           = 0x0250,
 259         [RMCR]          = 0x0258,
 260         [TFUCR]         = 0x0264,
 261         [RFOCR]         = 0x0268,
 262         [RMIIMODE]      = 0x026c,
 263         [FCFTR]         = 0x0270,
 264         [TRIMD]         = 0x027c,
 265 };
 266
 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 268         SH_ETH_OFFSET_DEFAULTS,
 269
 270         [ECMR]          = 0x0100,
 271         [RFLR]          = 0x0108,
 272         [ECSR]          = 0x0110,
 273         [ECSIPR]        = 0x0118,
 274         [PIR]           = 0x0120,
 275         [PSR]           = 0x0128,
 276         [RDMLR]         = 0x0140,
 277         [IPGR]          = 0x0150,
 278         [APR]           = 0x0154,
 279         [MPR]           = 0x0158,
 280         [TPAUSER]       = 0x0164,
 281         [RFCF]          = 0x0160,
 282         [TPAUSECR]      = 0x0168,
 283         [BCFRR]         = 0x016c,
 284         [MAHR]          = 0x01c0,
 285         [MALR]          = 0x01c8,
 286         [TROCR]         = 0x01d0,
 287         [CDCR]          = 0x01d4,
 288         [LCCR]          = 0x01d8,
 289         [CNDCR]         = 0x01dc,
 290         [CEFCR]         = 0x01e4,
 291         [FRECR]         = 0x01e8,
 292         [TSFRCR]        = 0x01ec,
 293         [TLFRCR]        = 0x01f0,
 294         [RFCR]          = 0x01f4,
 295         [MAFCR]         = 0x01f8,
 296         [RTRATE]        = 0x01fc,
 297
 298         [EDMR]          = 0x0000,
 299         [EDTRR]         = 0x0008,
 300         [EDRRR]         = 0x0010,
 301         [TDLAR]         = 0x0018,
 302         [RDLAR]         = 0x0020,
 303         [EESR]          = 0x0028,
 304         [EESIPR]        = 0x0030,
 305         [TRSCER]        = 0x0038,
 306         [RMFCR]         = 0x0040,
 307         [TFTR]          = 0x0048,
 308         [FDR]           = 0x0050,
 309         [RMCR]          = 0x0058,
 310         [TFUCR]         = 0x0064,
 311         [RFOCR]         = 0x0068,
 312         [FCFTR]         = 0x0070,
 313         [RPADIR]        = 0x0078,
 314         [TRIMD]         = 0x007c,
 315         [RBWAR]         = 0x00c8,
 316         [RDFAR]         = 0x00cc,
 317         [TBRAR]         = 0x00d4,
 318         [TDFAR]         = 0x00d8,
 319 };
 320
 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 322         SH_ETH_OFFSET_DEFAULTS,
 323
 324         [EDMR]          = 0x0000,
 325         [EDTRR]         = 0x0004,
 326         [EDRRR]         = 0x0008,
 327         [TDLAR]         = 0x000c,
 328         [RDLAR]         = 0x0010,
 329         [EESR]          = 0x0014,
 330         [EESIPR]        = 0x0018,
 331         [TRSCER]        = 0x001c,
 332         [RMFCR]         = 0x0020,
 333         [TFTR]          = 0x0024,
 334         [FDR]           = 0x0028,
 335         [RMCR]          = 0x002c,
 336         [EDOCR]         = 0x0030,
 337         [FCFTR]         = 0x0034,
 338         [RPADIR]        = 0x0038,
 339         [TRIMD]         = 0x003c,
 340         [RBWAR]         = 0x0040,
 341         [RDFAR]         = 0x0044,
 342         [TBRAR]         = 0x004c,
 343         [TDFAR]         = 0x0050,
 344
 345         [ECMR]          = 0x0160,
 346         [ECSR]          = 0x0164,
 347         [ECSIPR]        = 0x0168,
 348         [PIR]           = 0x016c,
 349         [MAHR]          = 0x0170,
 350         [MALR]          = 0x0174,
 351         [RFLR]          = 0x0178,
 352         [PSR]           = 0x017c,
 353         [TROCR]         = 0x0180,
 354         [CDCR]          = 0x0184,
 355         [LCCR]          = 0x0188,
 356         [CNDCR]         = 0x018c,
 357         [CEFCR]         = 0x0194,
 358         [FRECR]         = 0x0198,
 359         [TSFRCR]        = 0x019c,
 360         [TLFRCR]        = 0x01a0,
 361         [RFCR]          = 0x01a4,
 362         [MAFCR]         = 0x01a8,
 363         [IPGR]          = 0x01b4,
 364         [APR]           = 0x01b8,
 365         [MPR]           = 0x01bc,
 366         [TPAUSER]       = 0x01c4,
 367         [BCFR]          = 0x01cc,
 368
 369         [ARSTR]         = 0x0000,
 370         [TSU_CTRST]     = 0x0004,
 371         [TSU_FWEN0]     = 0x0010,
 372         [TSU_FWEN1]     = 0x0014,
 373         [TSU_FCM]       = 0x0018,
 374         [TSU_BSYSL0]    = 0x0020,
 375         [TSU_BSYSL1]    = 0x0024,
 376         [TSU_PRISL0]    = 0x0028,
 377         [TSU_PRISL1]    = 0x002c,
 378         [TSU_FWSL0]     = 0x0030,
 379         [TSU_FWSL1]     = 0x0034,
 380         [TSU_FWSLC]     = 0x0038,
 381         [TSU_QTAGM0]    = 0x0040,
 382         [TSU_QTAGM1]    = 0x0044,
 383         [TSU_ADQT0]     = 0x0048,
 384         [TSU_ADQT1]     = 0x004c,
 385         [TSU_FWSR]      = 0x0050,
 386         [TSU_FWINMK]    = 0x0054,
 387         [TSU_ADSBSY]    = 0x0060,
 388         [TSU_TEN]       = 0x0064,
 389         [TSU_POST1]     = 0x0070,
 390         [TSU_POST2]     = 0x0074,
 391         [TSU_POST3]     = 0x0078,
 392         [TSU_POST4]     = 0x007c,
 393
 394         [TXNLCR0]       = 0x0080,
 395         [TXALCR0]       = 0x0084,
 396         [RXNLCR0]       = 0x0088,
 397         [RXALCR0]       = 0x008c,
 398         [FWNLCR0]       = 0x0090,
 399         [FWALCR0]       = 0x0094,
 400         [TXNLCR1]       = 0x00a0,
 401         [TXALCR1]       = 0x00a4,
 402         [RXNLCR1]       = 0x00a8,
 403         [RXALCR1]       = 0x00ac,
 404         [FWNLCR1]       = 0x00b0,
 405         [FWALCR1]       = 0x00b4,
 406
 407         [TSU_ADRH0]     = 0x0100,
 408 };
 409
 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 412
 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 414 {
 415         struct sh_eth_private *mdp = netdev_priv(ndev);
 416         u16 offset = mdp->reg_offset[enum_index];
 417
 418         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 419                 return;
 420
 421         iowrite32(data, mdp->addr + offset);
 422 }
 423
 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 425 {
 426         struct sh_eth_private *mdp = netdev_priv(ndev);
 427         u16 offset = mdp->reg_offset[enum_index];
 428
 429         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 430                 return ~0U;
 431
 432         return ioread32(mdp->addr + offset);
 433 }
 434
 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 436                           u32 set)
 437 {
 438         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 439                      enum_index);
 440 }
 441
 442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
 443                              int enum_index)
 444 {
 445         u16 offset = mdp->reg_offset[enum_index];
 446
 447         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 448                 return;
 449
 450         iowrite32(data, mdp->tsu_addr + offset);
 451 }
 452
 453 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
 454 {
 455         u16 offset = mdp->reg_offset[enum_index];
 456
 457         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 458                 return ~0U;
 459
 460         return ioread32(mdp->tsu_addr + offset);
 461 }
 462
 463 static void sh_eth_soft_swap(char *src, int len)
 464 {
 465 #ifdef __LITTLE_ENDIAN
 466         u32 *p = (u32 *)src;
 467         u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
 468
 469         for (; p < maxp; p++)
 470                 *p = swab32(*p);
 471 #endif
 472 }
 473
 474 static void sh_eth_select_mii(struct net_device *ndev)
 475 {
 476         struct sh_eth_private *mdp = netdev_priv(ndev);
 477         u32 value;
 478
 479         switch (mdp->phy_interface) {
 480         case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
 481                 value = 0x3;
 482                 break;
 483         case PHY_INTERFACE_MODE_GMII:
 484                 value = 0x2;
 485                 break;
 486         case PHY_INTERFACE_MODE_MII:
 487                 value = 0x1;
 488                 break;
 489         case PHY_INTERFACE_MODE_RMII:
 490                 value = 0x0;
 491                 break;
 492         default:
 493                 netdev_warn(ndev,
 494                             "PHY interface mode was not setup. Set to MII.\n");
 495                 value = 0x1;
 496                 break;
 497         }
 498
 499         sh_eth_write(ndev, value, RMII_MII);
 500 }
 501
 502 static void sh_eth_set_duplex(struct net_device *ndev)
 503 {
 504         struct sh_eth_private *mdp = netdev_priv(ndev);
 505
 506         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 507 }
 508
 509 static void sh_eth_chip_reset(struct net_device *ndev)
 510 {
 511         struct sh_eth_private *mdp = netdev_priv(ndev);
 512
 513         /* reset device */
 514         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 515         mdelay(1);
 516 }
 517
 518 static int sh_eth_soft_reset(struct net_device *ndev)
 519 {
 520         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 521         mdelay(3);
 522         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 523
 524         return 0;
 525 }
 526
 527 static int sh_eth_check_soft_reset(struct net_device *ndev)
 528 {
 529         int cnt;
 530
 531         for (cnt = 100; cnt > 0; cnt--) {
 532                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 533                         return 0;
 534                 mdelay(1);
 535         }
 536
 537         netdev_err(ndev, "Device reset failed\n");
 538         return -ETIMEDOUT;
 539 }
 540
 541 static int sh_eth_soft_reset_gether(struct net_device *ndev)
 542 {
 543         struct sh_eth_private *mdp = netdev_priv(ndev);
 544         int ret;
 545
 546         sh_eth_write(ndev, EDSR_ENALL, EDSR);
 547         sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 548
 549         ret = sh_eth_check_soft_reset(ndev);
 550         if (ret)
 551                 return ret;
 552
 553         /* Table Init */
 554         sh_eth_write(ndev, 0, TDLAR);
 555         sh_eth_write(ndev, 0, TDFAR);
 556         sh_eth_write(ndev, 0, TDFXR);
 557         sh_eth_write(ndev, 0, TDFFR);
 558         sh_eth_write(ndev, 0, RDLAR);
 559         sh_eth_write(ndev, 0, RDFAR);
 560         sh_eth_write(ndev, 0, RDFXR);
 561         sh_eth_write(ndev, 0, RDFFR);
 562
 563         /* Reset HW CRC register */
 564         if (mdp->cd->hw_checksum)
 565                 sh_eth_write(ndev, 0, CSMR);
 566
 567         /* Select MII mode */
 568         if (mdp->cd->select_mii)
 569                 sh_eth_select_mii(ndev);
 570
 571         return ret;
 572 }
 573
 574 static void sh_eth_set_rate_gether(struct net_device *ndev)
 575 {
 576         struct sh_eth_private *mdp = netdev_priv(ndev);
 577
 578         switch (mdp->speed) {
 579         case 10: /* 10BASE */
 580                 sh_eth_write(ndev, GECMR_10, GECMR);
 581                 break;
 582         case 100:/* 100BASE */
 583                 sh_eth_write(ndev, GECMR_100, GECMR);
 584                 break;
 585         case 1000: /* 1000BASE */
 586                 sh_eth_write(ndev, GECMR_1000, GECMR);
 587                 break;
 588         }
 589 }
 590
 591 #ifdef CONFIG_OF
 592 /* R7S72100 */
 593 static struct sh_eth_cpu_data r7s72100_data = {
 594         .soft_reset     = sh_eth_soft_reset_gether,
 595
 596         .chip_reset     = sh_eth_chip_reset,
 597         .set_duplex     = sh_eth_set_duplex,
 598
 599         .register_type  = SH_ETH_REG_FAST_RZ,
 600
 601         .edtrr_trns     = EDTRR_TRNS_GETHER,
 602         .ecsr_value     = ECSR_ICD,
 603         .ecsipr_value   = ECSIPR_ICDIP,
 604         .eesipr_value   = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
 605                           EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
 606                           EESIPR_ECIIP |
 607                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 608                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 609                           EESIPR_RMAFIP | EESIPR_RRFIP |
 610                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 611                           EESIPR_PREIP | EESIPR_CERFIP,
 612
 613         .tx_check       = EESR_TC1 | EESR_FTC,
 614         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 615                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 616                           EESR_TDE,
 617         .fdr_value      = 0x0000070f,
 618
 619         .no_psr         = 1,
 620         .apr            = 1,
 621         .mpr            = 1,
 622         .tpauser        = 1,
 623         .hw_swap        = 1,
 624         .rpadir         = 1,
 625         .rpadir_value   = 2 << 16,
 626         .no_trimd       = 1,
 627         .no_ade         = 1,
 628         .xdfar_rw       = 1,
 629         .hw_checksum    = 1,
 630         .tsu            = 1,
 631         .no_tx_cntrs    = 1,
 632 };
 633
 634 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 635 {
 636         sh_eth_chip_reset(ndev);
 637
 638         sh_eth_select_mii(ndev);
 639 }
 640
 641 /* R8A7740 */
 642 static struct sh_eth_cpu_data r8a7740_data = {
 643         .soft_reset     = sh_eth_soft_reset_gether,
 644
 645         .chip_reset     = sh_eth_chip_reset_r8a7740,
 646         .set_duplex     = sh_eth_set_duplex,
 647         .set_rate       = sh_eth_set_rate_gether,
 648
 649         .register_type  = SH_ETH_REG_GIGABIT,
 650
 651         .edtrr_trns     = EDTRR_TRNS_GETHER,
 652         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 653         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 654         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 655                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 656                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 657                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 658                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 659                           EESIPR_CEEFIP | EESIPR_CELFIP |
 660                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 661                           EESIPR_PREIP | EESIPR_CERFIP,
 662
 663         .tx_check       = EESR_TC1 | EESR_FTC,
 664         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 665                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 666                           EESR_TDE,
 667         .fdr_value      = 0x0000070f,
 668
 669         .apr            = 1,
 670         .mpr            = 1,
 671         .tpauser        = 1,
 672         .bculr          = 1,
 673         .hw_swap        = 1,
 674         .rpadir         = 1,
 675         .rpadir_value   = 2 << 16,
 676         .no_trimd       = 1,
 677         .no_ade         = 1,
 678         .xdfar_rw       = 1,
 679         .hw_checksum    = 1,
 680         .tsu            = 1,
 681         .select_mii     = 1,
 682         .magic          = 1,
 683         .cexcr          = 1,
 684 };
 685
 686 /* There is CPU dependent code */
 687 static void sh_eth_set_rate_rcar(struct net_device *ndev)
 688 {
 689         struct sh_eth_private *mdp = netdev_priv(ndev);
 690
 691         switch (mdp->speed) {
 692         case 10: /* 10BASE */
 693                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 694                 break;
 695         case 100:/* 100BASE */
 696                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 697                 break;
 698         }
 699 }
 700
 701 /* R-Car Gen1 */
 702 static struct sh_eth_cpu_data rcar_gen1_data = {
 703         .soft_reset     = sh_eth_soft_reset,
 704
 705         .set_duplex     = sh_eth_set_duplex,
 706         .set_rate       = sh_eth_set_rate_rcar,
 707
 708         .register_type  = SH_ETH_REG_FAST_RCAR,
 709
 710         .edtrr_trns     = EDTRR_TRNS_ETHER,
 711         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 712         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 713         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 714                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 715                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 716                           EESIPR_RMAFIP | EESIPR_RRFIP |
 717                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 718                           EESIPR_PREIP | EESIPR_CERFIP,
 719
 720         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 721         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 722                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 723         .fdr_value      = 0x00000f0f,
 724
 725         .apr            = 1,
 726         .mpr            = 1,
 727         .tpauser        = 1,
 728         .hw_swap        = 1,
 729         .no_xdfar       = 1,
 730 };
 731
 732 /* R-Car Gen2 and RZ/G1 */
 733 static struct sh_eth_cpu_data rcar_gen2_data = {
 734         .soft_reset     = sh_eth_soft_reset,
 735
 736         .set_duplex     = sh_eth_set_duplex,
 737         .set_rate       = sh_eth_set_rate_rcar,
 738
 739         .register_type  = SH_ETH_REG_FAST_RCAR,
 740
 741         .edtrr_trns     = EDTRR_TRNS_ETHER,
 742         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 743         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 744                           ECSIPR_MPDIP,
 745         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 746                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 747                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 748                           EESIPR_RMAFIP | EESIPR_RRFIP |
 749                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 750                           EESIPR_PREIP | EESIPR_CERFIP,
 751
 752         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 753         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 754                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 755         .fdr_value      = 0x00000f0f,
 756
 757         .trscer_err_mask = DESC_I_RINT8,
 758
 759         .apr            = 1,
 760         .mpr            = 1,
 761         .tpauser        = 1,
 762         .hw_swap        = 1,
 763         .no_xdfar       = 1,
 764         .rmiimode       = 1,
 765         .magic          = 1,
 766 };
 767
 768 /* R8A77980 */
 769 static struct sh_eth_cpu_data r8a77980_data = {
 770         .soft_reset     = sh_eth_soft_reset_gether,
 771
 772         .set_duplex     = sh_eth_set_duplex,
 773         .set_rate       = sh_eth_set_rate_gether,
 774
 775         .register_type  = SH_ETH_REG_GIGABIT,
 776
 777         .edtrr_trns     = EDTRR_TRNS_GETHER,
 778         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 779         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 780                           ECSIPR_MPDIP,
 781         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 782                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 783                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 784                           EESIPR_RMAFIP | EESIPR_RRFIP |
 785                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 786                           EESIPR_PREIP | EESIPR_CERFIP,
 787
 788         .tx_check       = EESR_FTC | EESR_CD | EESR_TRO,
 789         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 790                           EESR_RFE | EESR_RDE | EESR_RFRMER |
 791                           EESR_TFE | EESR_TDE | EESR_ECI,
 792         .fdr_value      = 0x0000070f,
 793
 794         .apr            = 1,
 795         .mpr            = 1,
 796         .tpauser        = 1,
 797         .bculr          = 1,
 798         .hw_swap        = 1,
 799         .nbst           = 1,
 800         .rpadir         = 1,
 801         .rpadir_value   = 2 << 16,
 802         .no_trimd       = 1,
 803         .no_ade         = 1,
 804         .xdfar_rw       = 1,
 805         .hw_checksum    = 1,
 806         .select_mii     = 1,
 807         .magic          = 1,
 808         .cexcr          = 1,
 809 };
 810 #endif /* CONFIG_OF */
 811
 812 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 813 {
 814         struct sh_eth_private *mdp = netdev_priv(ndev);
 815
 816         switch (mdp->speed) {
 817         case 10: /* 10BASE */
 818                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 819                 break;
 820         case 100:/* 100BASE */
 821                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 822                 break;
 823         }
 824 }
 825
 826 /* SH7724 */
 827 static struct sh_eth_cpu_data sh7724_data = {
 828         .soft_reset     = sh_eth_soft_reset,
 829
 830         .set_duplex     = sh_eth_set_duplex,
 831         .set_rate       = sh_eth_set_rate_sh7724,
 832
 833         .register_type  = SH_ETH_REG_FAST_SH4,
 834
 835         .edtrr_trns     = EDTRR_TRNS_ETHER,
 836         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 837         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 838         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 839                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 840                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 841                           EESIPR_RMAFIP | EESIPR_RRFIP |
 842                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 843                           EESIPR_PREIP | EESIPR_CERFIP,
 844
 845         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 846         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 847                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 848
 849         .apr            = 1,
 850         .mpr            = 1,
 851         .tpauser        = 1,
 852         .hw_swap        = 1,
 853         .rpadir         = 1,
 854         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 855 };
 856
 857 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 858 {
 859         struct sh_eth_private *mdp = netdev_priv(ndev);
 860
 861         switch (mdp->speed) {
 862         case 10: /* 10BASE */
 863                 sh_eth_write(ndev, 0, RTRATE);
 864                 break;
 865         case 100:/* 100BASE */
 866                 sh_eth_write(ndev, 1, RTRATE);
 867                 break;
 868         }
 869 }
 870
 871 /* SH7757 */
 872 static struct sh_eth_cpu_data sh7757_data = {
 873         .soft_reset     = sh_eth_soft_reset,
 874
 875         .set_duplex     = sh_eth_set_duplex,
 876         .set_rate       = sh_eth_set_rate_sh7757,
 877
 878         .register_type  = SH_ETH_REG_FAST_SH4,
 879
 880         .edtrr_trns     = EDTRR_TRNS_ETHER,
 881         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 882                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 883                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 884                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 885                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 886                           EESIPR_CEEFIP | EESIPR_CELFIP |
 887                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 888                           EESIPR_PREIP | EESIPR_CERFIP,
 889
 890         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 891         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 892                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 893
 894         .irq_flags      = IRQF_SHARED,
 895         .apr            = 1,
 896         .mpr            = 1,
 897         .tpauser        = 1,
 898         .hw_swap        = 1,
 899         .no_ade         = 1,
 900         .rpadir         = 1,
 901         .rpadir_value   = 2 << 16,
 902         .rtrate         = 1,
 903         .dual_port      = 1,
 904 };
 905
 906 #define SH_GIGA_ETH_BASE        0xfee00000UL
 907 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 908 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 909 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 910 {
 911         u32 mahr[2], malr[2];
 912         int i;
 913
 914         /* save MAHR and MALR */
 915         for (i = 0; i < 2; i++) {
 916                 malr[i] = ioread32((void *)GIGA_MALR(i));
 917                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 918         }
 919
 920         sh_eth_chip_reset(ndev);
 921
 922         /* restore MAHR and MALR */
 923         for (i = 0; i < 2; i++) {
 924                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 925                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 926         }
 927 }
 928
 929 static void sh_eth_set_rate_giga(struct net_device *ndev)
 930 {
 931         struct sh_eth_private *mdp = netdev_priv(ndev);
 932
 933         switch (mdp->speed) {
 934         case 10: /* 10BASE */
 935                 sh_eth_write(ndev, 0x00000000, GECMR);
 936                 break;
 937         case 100:/* 100BASE */
 938                 sh_eth_write(ndev, 0x00000010, GECMR);
 939                 break;
 940         case 1000: /* 1000BASE */
 941                 sh_eth_write(ndev, 0x00000020, GECMR);
 942                 break;
 943         }
 944 }
 945
 946 /* SH7757(GETHERC) */
 947 static struct sh_eth_cpu_data sh7757_data_giga = {
 948         .soft_reset     = sh_eth_soft_reset_gether,
 949
 950         .chip_reset     = sh_eth_chip_reset_giga,
 951         .set_duplex     = sh_eth_set_duplex,
 952         .set_rate       = sh_eth_set_rate_giga,
 953
 954         .register_type  = SH_ETH_REG_GIGABIT,
 955
 956         .edtrr_trns     = EDTRR_TRNS_GETHER,
 957         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 958         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 959         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 960                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 961                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 962                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 963                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 964                           EESIPR_CEEFIP | EESIPR_CELFIP |
 965                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 966                           EESIPR_PREIP | EESIPR_CERFIP,
 967
 968         .tx_check       = EESR_TC1 | EESR_FTC,
 969         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 970                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 971                           EESR_TDE,
 972         .fdr_value      = 0x0000072f,
 973
 974         .irq_flags      = IRQF_SHARED,
 975         .apr            = 1,
 976         .mpr            = 1,
 977         .tpauser        = 1,
 978         .bculr          = 1,
 979         .hw_swap        = 1,
 980         .rpadir         = 1,
 981         .rpadir_value   = 2 << 16,
 982         .no_trimd       = 1,
 983         .no_ade         = 1,
 984         .xdfar_rw       = 1,
 985         .tsu            = 1,
 986         .cexcr          = 1,
 987         .dual_port      = 1,
 988 };
 989
 990 /* SH7734 */
 991 static struct sh_eth_cpu_data sh7734_data = {
 992         .soft_reset     = sh_eth_soft_reset_gether,
 993
 994         .chip_reset     = sh_eth_chip_reset,
 995         .set_duplex     = sh_eth_set_duplex,
 996         .set_rate       = sh_eth_set_rate_gether,
 997
 998         .register_type  = SH_ETH_REG_GIGABIT,
 999
1000         .edtrr_trns     = EDTRR_TRNS_GETHER,
1001         .ecsr_value     = ECSR_ICD | ECSR_MPD,
1002         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1003         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1004                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1005                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1006                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1007                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1008                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1009                           EESIPR_PREIP | EESIPR_CERFIP,
1010
1011         .tx_check       = EESR_TC1 | EESR_FTC,
1012         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1013                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1014                           EESR_TDE,
1015
1016         .apr            = 1,
1017         .mpr            = 1,
1018         .tpauser        = 1,
1019         .bculr          = 1,
1020         .hw_swap        = 1,
1021         .no_trimd       = 1,
1022         .no_ade         = 1,
1023         .xdfar_rw       = 1,
1024         .tsu            = 1,
1025         .hw_checksum    = 1,
1026         .select_mii     = 1,
1027         .magic          = 1,
1028         .cexcr          = 1,
1029 };
1030
1031 /* SH7763 */
1032 static struct sh_eth_cpu_data sh7763_data = {
1033         .soft_reset     = sh_eth_soft_reset_gether,
1034
1035         .chip_reset     = sh_eth_chip_reset,
1036         .set_duplex     = sh_eth_set_duplex,
1037         .set_rate       = sh_eth_set_rate_gether,
1038
1039         .register_type  = SH_ETH_REG_GIGABIT,
1040
1041         .edtrr_trns     = EDTRR_TRNS_GETHER,
1042         .ecsr_value     = ECSR_ICD | ECSR_MPD,
1043         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1044         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1045                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1046                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1047                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1048                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1049                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1050                           EESIPR_PREIP | EESIPR_CERFIP,
1051
1052         .tx_check       = EESR_TC1 | EESR_FTC,
1053         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1054                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1055
1056         .apr            = 1,
1057         .mpr            = 1,
1058         .tpauser        = 1,
1059         .bculr          = 1,
1060         .hw_swap        = 1,
1061         .no_trimd       = 1,
1062         .no_ade         = 1,
1063         .xdfar_rw       = 1,
1064         .tsu            = 1,
1065         .irq_flags      = IRQF_SHARED,
1066         .magic          = 1,
1067         .cexcr          = 1,
1068         .dual_port      = 1,
1069 };
1070
1071 static struct sh_eth_cpu_data sh7619_data = {
1072         .soft_reset     = sh_eth_soft_reset,
1073
1074         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1075
1076         .edtrr_trns     = EDTRR_TRNS_ETHER,
1077         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1078                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1079                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1080                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1081                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1082                           EESIPR_CEEFIP | EESIPR_CELFIP |
1083                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1084                           EESIPR_PREIP | EESIPR_CERFIP,
1085
1086         .apr            = 1,
1087         .mpr            = 1,
1088         .tpauser        = 1,
1089         .hw_swap        = 1,
1090 };
1091
1092 static struct sh_eth_cpu_data sh771x_data = {
1093         .soft_reset     = sh_eth_soft_reset,
1094
1095         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1096
1097         .edtrr_trns     = EDTRR_TRNS_ETHER,
1098         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1099                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1100                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1101                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1102                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1103                           EESIPR_CEEFIP | EESIPR_CELFIP |
1104                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1105                           EESIPR_PREIP | EESIPR_CERFIP,
1106         .tsu            = 1,
1107         .dual_port      = 1,
1108 };
1109
1110 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1111 {
1112         if (!cd->ecsr_value)
1113                 cd->ecsr_value = DEFAULT_ECSR_INIT;
1114
1115         if (!cd->ecsipr_value)
1116                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1117
1118         if (!cd->fcftr_value)
1119                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1120                                   DEFAULT_FIFO_F_D_RFD;
1121
1122         if (!cd->fdr_value)
1123                 cd->fdr_value = DEFAULT_FDR_INIT;
1124
1125         if (!cd->tx_check)
1126                 cd->tx_check = DEFAULT_TX_CHECK;
1127
1128         if (!cd->eesr_err_check)
1129                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1130
1131         if (!cd->trscer_err_mask)
1132                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1133 }
1134
1135 static void sh_eth_set_receive_align(struct sk_buff *skb)
1136 {
1137         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1138
1139         if (reserve)
1140                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1141 }
1142
1143 /* Program the hardware MAC address from dev->dev_addr. */
1144 static void update_mac_address(struct net_device *ndev)
1145 {
1146         sh_eth_write(ndev,
1147                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1148                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1149         sh_eth_write(ndev,
1150                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1151 }
1152
1153 /* Get MAC address from SuperH MAC address register
1154  *
1155  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1156  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1157  * When you want use this device, you must set MAC address in bootloader.
1158  *
1159  */
1160 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1161 {
1162         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1163                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1164         } else {
1165                 u32 mahr = sh_eth_read(ndev, MAHR);
1166                 u32 malr = sh_eth_read(ndev, MALR);
1167
1168                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1169                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1170                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
1171                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1172                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1173                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1174         }
1175 }
1176
1177 struct bb_info {
1178         void (*set_gate)(void *addr);
1179         struct mdiobb_ctrl ctrl;
1180         void *addr;
1181 };
1182
1183 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1184 {
1185         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1186         u32 pir;
1187
1188         if (bitbang->set_gate)
1189                 bitbang->set_gate(bitbang->addr);
1190
1191         pir = ioread32(bitbang->addr);
1192         if (set)
1193                 pir |=  mask;
1194         else
1195                 pir &= ~mask;
1196         iowrite32(pir, bitbang->addr);
1197 }
1198
1199 /* Data I/O pin control */
1200 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1201 {
1202         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1203 }
1204
1205 /* Set bit data*/
1206 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1207 {
1208         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1209 }
1210
1211 /* Get bit data*/
1212 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1213 {
1214         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1215
1216         if (bitbang->set_gate)
1217                 bitbang->set_gate(bitbang->addr);
1218
1219         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1220 }
1221
1222 /* MDC pin control */
1223 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1224 {
1225         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1226 }
1227
1228 /* mdio bus control struct */
1229 static struct mdiobb_ops bb_ops = {
1230         .owner = THIS_MODULE,
1231         .set_mdc = sh_mdc_ctrl,
1232         .set_mdio_dir = sh_mmd_ctrl,
1233         .set_mdio_data = sh_set_mdio,
1234         .get_mdio_data = sh_get_mdio,
1235 };
1236
1237 /* free Tx skb function */
1238 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1239 {
1240         struct sh_eth_private *mdp = netdev_priv(ndev);
1241         struct sh_eth_txdesc *txdesc;
1242         int free_num = 0;
1243         int entry;
1244         bool sent;
1245
1246         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1247                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1248                 txdesc = &mdp->tx_ring[entry];
1249                 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1250                 if (sent_only && !sent)
1251                         break;
1252                 /* TACT bit must be checked before all the following reads */
1253                 dma_rmb();
1254                 netif_info(mdp, tx_done, ndev,
1255                            "tx entry %d status 0x%08x\n",
1256                            entry, le32_to_cpu(txdesc->status));
1257                 /* Free the original skb. */
1258                 if (mdp->tx_skbuff[entry]) {
1259                         dma_unmap_single(&mdp->pdev->dev,
1260                                          le32_to_cpu(txdesc->addr),
1261                                          le32_to_cpu(txdesc->len) >> 16,
1262                                          DMA_TO_DEVICE);
1263                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1264                         mdp->tx_skbuff[entry] = NULL;
1265                         free_num++;
1266                 }
1267                 txdesc->status = cpu_to_le32(TD_TFP);
1268                 if (entry >= mdp->num_tx_ring - 1)
1269                         txdesc->status |= cpu_to_le32(TD_TDLE);
1270
1271                 if (sent) {
1272                         ndev->stats.tx_packets++;
1273                         ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1274                 }
1275         }
1276         return free_num;
1277 }
1278
1279 /* free skb and descriptor buffer */
1280 static void sh_eth_ring_free(struct net_device *ndev)
1281 {
1282         struct sh_eth_private *mdp = netdev_priv(ndev);
1283         int ringsize, i;
1284
1285         if (mdp->rx_ring) {
1286                 for (i = 0; i < mdp->num_rx_ring; i++) {
1287                         if (mdp->rx_skbuff[i]) {
1288                                 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1289
1290                                 dma_unmap_single(&mdp->pdev->dev,
1291                                                  le32_to_cpu(rxdesc->addr),
1292                                                  ALIGN(mdp->rx_buf_sz, 32),
1293                                                  DMA_FROM_DEVICE);
1294                         }
1295                 }
1296                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1297                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1298                                   mdp->rx_desc_dma);
1299                 mdp->rx_ring = NULL;
1300         }
1301
1302         /* Free Rx skb ringbuffer */
1303         if (mdp->rx_skbuff) {
1304                 for (i = 0; i < mdp->num_rx_ring; i++)
1305                         dev_kfree_skb(mdp->rx_skbuff[i]);
1306         }
1307         kfree(mdp->rx_skbuff);
1308         mdp->rx_skbuff = NULL;
1309
1310         if (mdp->tx_ring) {
1311                 sh_eth_tx_free(ndev, false);
1312
1313                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1314                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1315                                   mdp->tx_desc_dma);
1316                 mdp->tx_ring = NULL;
1317         }
1318
1319         /* Free Tx skb ringbuffer */
1320         kfree(mdp->tx_skbuff);
1321         mdp->tx_skbuff = NULL;
1322 }
1323
1324 /* format skb and descriptor buffer */
1325 static void sh_eth_ring_format(struct net_device *ndev)
1326 {
1327         struct sh_eth_private *mdp = netdev_priv(ndev);
1328         int i;
1329         struct sk_buff *skb;
1330         struct sh_eth_rxdesc *rxdesc = NULL;
1331         struct sh_eth_txdesc *txdesc = NULL;
1332         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1333         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1334         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1335         dma_addr_t dma_addr;
1336         u32 buf_len;
1337
1338         mdp->cur_rx = 0;
1339         mdp->cur_tx = 0;
1340         mdp->dirty_rx = 0;
1341         mdp->dirty_tx = 0;
1342
1343         memset(mdp->rx_ring, 0, rx_ringsize);
1344
1345         /* build Rx ring buffer */
1346         for (i = 0; i < mdp->num_rx_ring; i++) {
1347                 /* skb */
1348                 mdp->rx_skbuff[i] = NULL;
1349                 skb = netdev_alloc_skb(ndev, skbuff_size);
1350                 if (skb == NULL)
1351                         break;
1352                 sh_eth_set_receive_align(skb);
1353
1354                 /* The size of the buffer is a multiple of 32 bytes. */
1355                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1356                 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1357                                           DMA_FROM_DEVICE);
1358                 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1359                         kfree_skb(skb);
1360                         break;
1361                 }
1362                 mdp->rx_skbuff[i] = skb;
1363
1364                 /* RX descriptor */
1365                 rxdesc = &mdp->rx_ring[i];
1366                 rxdesc->len = cpu_to_le32(buf_len << 16);
1367                 rxdesc->addr = cpu_to_le32(dma_addr);
1368                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1369
1370                 /* Rx descriptor address set */
1371                 if (i == 0) {
1372                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1373                         if (mdp->cd->xdfar_rw)
1374                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1375                 }
1376         }
1377
1378         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1379
1380         /* Mark the last entry as wrapping the ring. */
1381         if (rxdesc)
1382                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1383
1384         memset(mdp->tx_ring, 0, tx_ringsize);
1385
1386         /* build Tx ring buffer */
1387         for (i = 0; i < mdp->num_tx_ring; i++) {
1388                 mdp->tx_skbuff[i] = NULL;
1389                 txdesc = &mdp->tx_ring[i];
1390                 txdesc->status = cpu_to_le32(TD_TFP);
1391                 txdesc->len = cpu_to_le32(0);
1392                 if (i == 0) {
1393                         /* Tx descriptor address set */
1394                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1395                         if (mdp->cd->xdfar_rw)
1396                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1397                 }
1398         }
1399
1400         txdesc->status |= cpu_to_le32(TD_TDLE);
1401 }
1402
1403 /* Get skb and descriptor buffer */
1404 static int sh_eth_ring_init(struct net_device *ndev)
1405 {
1406         struct sh_eth_private *mdp = netdev_priv(ndev);
1407         int rx_ringsize, tx_ringsize;
1408
1409         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1410          * card needs room to do 8 byte alignment, +2 so we can reserve
1411          * the first 2 bytes, and +16 gets room for the status word from the
1412          * card.
1413          */
1414         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1415                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1416         if (mdp->cd->rpadir)
1417                 mdp->rx_buf_sz += NET_IP_ALIGN;
1418
1419         /* Allocate RX and TX skb rings */
1420         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1421                                  GFP_KERNEL);
1422         if (!mdp->rx_skbuff)
1423                 return -ENOMEM;
1424
1425         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1426                                  GFP_KERNEL);
1427         if (!mdp->tx_skbuff)
1428                 goto ring_free;
1429
1430         /* Allocate all Rx descriptors. */
1431         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1432         mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1433                                           &mdp->rx_desc_dma, GFP_KERNEL);
1434         if (!mdp->rx_ring)
1435                 goto ring_free;
1436
1437         mdp->dirty_rx = 0;
1438
1439         /* Allocate all Tx descriptors. */
1440         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1441         mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1442                                           &mdp->tx_desc_dma, GFP_KERNEL);
1443         if (!mdp->tx_ring)
1444                 goto ring_free;
1445         return 0;
1446
1447 ring_free:
1448         /* Free Rx and Tx skb ring buffer and DMA buffer */
1449         sh_eth_ring_free(ndev);
1450
1451         return -ENOMEM;
1452 }
1453
1454 static int sh_eth_dev_init(struct net_device *ndev)
1455 {
1456         struct sh_eth_private *mdp = netdev_priv(ndev);
1457         int ret;
1458
1459         /* Soft Reset */
1460         ret = mdp->cd->soft_reset(ndev);
1461         if (ret)
1462                 return ret;
1463
1464         if (mdp->cd->rmiimode)
1465                 sh_eth_write(ndev, 0x1, RMIIMODE);
1466
1467         /* Descriptor format */
1468         sh_eth_ring_format(ndev);
1469         if (mdp->cd->rpadir)
1470                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1471
1472         /* all sh_eth int mask */
1473         sh_eth_write(ndev, 0, EESIPR);
1474
1475 #if defined(__LITTLE_ENDIAN)
1476         if (mdp->cd->hw_swap)
1477                 sh_eth_write(ndev, EDMR_EL, EDMR);
1478         else
1479 #endif
1480                 sh_eth_write(ndev, 0, EDMR);
1481
1482         /* FIFO size set */
1483         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1484         sh_eth_write(ndev, 0, TFTR);
1485
1486         /* Frame recv control (enable multiple-packets per rx irq) */
1487         sh_eth_write(ndev, RMCR_RNC, RMCR);
1488
1489         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1490
1491         /* DMA transfer burst mode */
1492         if (mdp->cd->nbst)
1493                 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1494
1495         /* Burst cycle count upper-limit */
1496         if (mdp->cd->bculr)
1497                 sh_eth_write(ndev, 0x800, BCULR);
1498
1499         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1500
1501         if (!mdp->cd->no_trimd)
1502                 sh_eth_write(ndev, 0, TRIMD);
1503
1504         /* Recv frame limit set register */
1505         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1506                      RFLR);
1507
1508         sh_eth_modify(ndev, EESR, 0, 0);
1509         mdp->irq_enabled = true;
1510         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1511
1512         /* PAUSE Prohibition */
1513         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1514                      ECMR_TE | ECMR_RE, ECMR);
1515
1516         if (mdp->cd->set_rate)
1517                 mdp->cd->set_rate(ndev);
1518
1519         /* E-MAC Status Register clear */
1520         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1521
1522         /* E-MAC Interrupt Enable register */
1523         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1524
1525         /* Set MAC address */
1526         update_mac_address(ndev);
1527
1528         /* mask reset */
1529         if (mdp->cd->apr)
1530                 sh_eth_write(ndev, APR_AP, APR);
1531         if (mdp->cd->mpr)
1532                 sh_eth_write(ndev, MPR_MP, MPR);
1533         if (mdp->cd->tpauser)
1534                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1535
1536         /* Setting the Rx mode will start the Rx process. */
1537         sh_eth_write(ndev, EDRRR_R, EDRRR);
1538
1539         return ret;
1540 }
1541
1542 static void sh_eth_dev_exit(struct net_device *ndev)
1543 {
1544         struct sh_eth_private *mdp = netdev_priv(ndev);
1545         int i;
1546
1547         /* Deactivate all TX descriptors, so DMA should stop at next
1548          * packet boundary if it's currently running
1549          */
1550         for (i = 0; i < mdp->num_tx_ring; i++)
1551                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1552
1553         /* Disable TX FIFO egress to MAC */
1554         sh_eth_rcv_snd_disable(ndev);
1555
1556         /* Stop RX DMA at next packet boundary */
1557         sh_eth_write(ndev, 0, EDRRR);
1558
1559         /* Aside from TX DMA, we can't tell when the hardware is
1560          * really stopped, so we need to reset to make sure.
1561          * Before doing that, wait for long enough to *probably*
1562          * finish transmitting the last packet and poll stats.
1563          */
1564         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1565         sh_eth_get_stats(ndev);
1566         mdp->cd->soft_reset(ndev);
1567
1568         /* Set MAC address again */
1569         update_mac_address(ndev);
1570 }
1571
1572 /* Packet receive function */
1573 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1574 {
1575         struct sh_eth_private *mdp = netdev_priv(ndev);
1576         struct sh_eth_rxdesc *rxdesc;
1577
1578         int entry = mdp->cur_rx % mdp->num_rx_ring;
1579         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1580         int limit;
1581         struct sk_buff *skb;
1582         u32 desc_status;
1583         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1584         dma_addr_t dma_addr;
1585         u16 pkt_len;
1586         u32 buf_len;
1587
1588         boguscnt = min(boguscnt, *quota);
1589         limit = boguscnt;
1590         rxdesc = &mdp->rx_ring[entry];
1591         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1592                 /* RACT bit must be checked before all the following reads */
1593                 dma_rmb();
1594                 desc_status = le32_to_cpu(rxdesc->status);
1595                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1596
1597                 if (--boguscnt < 0)
1598                         break;
1599
1600                 netif_info(mdp, rx_status, ndev,
1601                            "rx entry %d status 0x%08x len %d\n",
1602                            entry, desc_status, pkt_len);
1603
1604                 if (!(desc_status & RDFEND))
1605                         ndev->stats.rx_length_errors++;
1606
1607                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1608                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1609                  * bit 0. However, in case of the R8A7740 and R7S72100
1610                  * the RFS bits are from bit 25 to bit 16. So, the
1611                  * driver needs right shifting by 16.
1612                  */
1613                 if (mdp->cd->hw_checksum)
1614                         desc_status >>= 16;
1615
1616                 skb = mdp->rx_skbuff[entry];
1617                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1618                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1619                         ndev->stats.rx_errors++;
1620                         if (desc_status & RD_RFS1)
1621                                 ndev->stats.rx_crc_errors++;
1622                         if (desc_status & RD_RFS2)
1623                                 ndev->stats.rx_frame_errors++;
1624                         if (desc_status & RD_RFS3)
1625                                 ndev->stats.rx_length_errors++;
1626                         if (desc_status & RD_RFS4)
1627                                 ndev->stats.rx_length_errors++;
1628                         if (desc_status & RD_RFS6)
1629                                 ndev->stats.rx_missed_errors++;
1630                         if (desc_status & RD_RFS10)
1631                                 ndev->stats.rx_over_errors++;
1632                 } else  if (skb) {
1633                         dma_addr = le32_to_cpu(rxdesc->addr);
1634                         if (!mdp->cd->hw_swap)
1635                                 sh_eth_soft_swap(
1636                                         phys_to_virt(ALIGN(dma_addr, 4)),
1637                                         pkt_len + 2);
1638                         mdp->rx_skbuff[entry] = NULL;
1639                         if (mdp->cd->rpadir)
1640                                 skb_reserve(skb, NET_IP_ALIGN);
1641                         dma_unmap_single(&mdp->pdev->dev, dma_addr,
1642                                          ALIGN(mdp->rx_buf_sz, 32),
1643                                          DMA_FROM_DEVICE);
1644                         skb_put(skb, pkt_len);
1645                         skb->protocol = eth_type_trans(skb, ndev);
1646                         netif_receive_skb(skb);
1647                         ndev->stats.rx_packets++;
1648                         ndev->stats.rx_bytes += pkt_len;
1649                         if (desc_status & RD_RFS8)
1650                                 ndev->stats.multicast++;
1651                 }
1652                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1653                 rxdesc = &mdp->rx_ring[entry];
1654         }
1655
1656         /* Refill the Rx ring buffers. */
1657         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1658                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1659                 rxdesc = &mdp->rx_ring[entry];
1660                 /* The size of the buffer is 32 byte boundary. */
1661                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1662                 rxdesc->len = cpu_to_le32(buf_len << 16);
1663
1664                 if (mdp->rx_skbuff[entry] == NULL) {
1665                         skb = netdev_alloc_skb(ndev, skbuff_size);
1666                         if (skb == NULL)
1667                                 break;  /* Better luck next round. */
1668                         sh_eth_set_receive_align(skb);
1669                         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1670                                                   buf_len, DMA_FROM_DEVICE);
1671                         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1672                                 kfree_skb(skb);
1673                                 break;
1674                         }
1675                         mdp->rx_skbuff[entry] = skb;
1676
1677                         skb_checksum_none_assert(skb);
1678                         rxdesc->addr = cpu_to_le32(dma_addr);
1679                 }
1680                 dma_wmb(); /* RACT bit must be set after all the above writes */
1681                 if (entry >= mdp->num_rx_ring - 1)
1682                         rxdesc->status |=
1683                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1684                 else
1685                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1686         }
1687
1688         /* Restart Rx engine if stopped. */
1689         /* If we don't need to check status, don't. -KDU */
1690         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1691                 /* fix the values for the next receiving if RDE is set */
1692                 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1693                         u32 count = (sh_eth_read(ndev, RDFAR) -
1694                                      sh_eth_read(ndev, RDLAR)) >> 4;
1695
1696                         mdp->cur_rx = count;
1697                         mdp->dirty_rx = count;
1698                 }
1699                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1700         }
1701
1702         *quota -= limit - boguscnt - 1;
1703
1704         return *quota <= 0;
1705 }
1706
1707 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1708 {
1709         /* disable tx and rx */
1710         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1711 }
1712
1713 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1714 {
1715         /* enable tx and rx */
1716         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1717 }
1718
1719 /* E-MAC interrupt handler */
1720 static void sh_eth_emac_interrupt(struct net_device *ndev)
1721 {
1722         struct sh_eth_private *mdp = netdev_priv(ndev);
1723         u32 felic_stat;
1724         u32 link_stat;
1725
1726         felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1727         sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1728         if (felic_stat & ECSR_ICD)
1729                 ndev->stats.tx_carrier_errors++;
1730         if (felic_stat & ECSR_MPD)
1731                 pm_wakeup_event(&mdp->pdev->dev, 0);
1732         if (felic_stat & ECSR_LCHNG) {
1733                 /* Link Changed */
1734                 if (mdp->cd->no_psr || mdp->no_ether_link)
1735                         return;
1736                 link_stat = sh_eth_read(ndev, PSR);
1737                 if (mdp->ether_link_active_low)
1738                         link_stat = ~link_stat;
1739                 if (!(link_stat & PHY_ST_LINK)) {
1740                         sh_eth_rcv_snd_disable(ndev);
1741                 } else {
1742                         /* Link Up */
1743                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1744                         /* clear int */
1745                         sh_eth_modify(ndev, ECSR, 0, 0);
1746                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1747                         /* enable tx and rx */
1748                         sh_eth_rcv_snd_enable(ndev);
1749                 }
1750         }
1751 }
1752
1753 /* error control function */
1754 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1755 {
1756         struct sh_eth_private *mdp = netdev_priv(ndev);
1757         u32 mask;
1758
1759         if (intr_status & EESR_TWB) {
1760                 /* Unused write back interrupt */
1761                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1762                         ndev->stats.tx_aborted_errors++;
1763                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1764                 }
1765         }
1766
1767         if (intr_status & EESR_RABT) {
1768                 /* Receive Abort int */
1769                 if (intr_status & EESR_RFRMER) {
1770                         /* Receive Frame Overflow int */
1771                         ndev->stats.rx_frame_errors++;
1772                 }
1773         }
1774
1775         if (intr_status & EESR_TDE) {
1776                 /* Transmit Descriptor Empty int */
1777                 ndev->stats.tx_fifo_errors++;
1778                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1779         }
1780
1781         if (intr_status & EESR_TFE) {
1782                 /* FIFO under flow */
1783                 ndev->stats.tx_fifo_errors++;
1784                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1785         }
1786
1787         if (intr_status & EESR_RDE) {
1788                 /* Receive Descriptor Empty int */
1789                 ndev->stats.rx_over_errors++;
1790         }
1791
1792         if (intr_status & EESR_RFE) {
1793                 /* Receive FIFO Overflow int */
1794                 ndev->stats.rx_fifo_errors++;
1795         }
1796
1797         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1798                 /* Address Error */
1799                 ndev->stats.tx_fifo_errors++;
1800                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1801         }
1802
1803         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1804         if (mdp->cd->no_ade)
1805                 mask &= ~EESR_ADE;
1806         if (intr_status & mask) {
1807                 /* Tx error */
1808                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1809
1810                 /* dmesg */
1811                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1812                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1813                            (u32)ndev->state, edtrr);
1814                 /* dirty buffer free */
1815                 sh_eth_tx_free(ndev, true);
1816
1817                 /* SH7712 BUG */
1818                 if (edtrr ^ mdp->cd->edtrr_trns) {
1819                         /* tx dma start */
1820                         sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1821                 }
1822                 /* wakeup */
1823                 netif_wake_queue(ndev);
1824         }
1825 }
1826
1827 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1828 {
1829         struct net_device *ndev = netdev;
1830         struct sh_eth_private *mdp = netdev_priv(ndev);
1831         struct sh_eth_cpu_data *cd = mdp->cd;
1832         irqreturn_t ret = IRQ_NONE;
1833         u32 intr_status, intr_enable;
1834
1835         spin_lock(&mdp->lock);
1836
1837         /* Get interrupt status */
1838         intr_status = sh_eth_read(ndev, EESR);
1839         /* Mask it with the interrupt mask, forcing ECI interrupt  to be always
1840          * enabled since it's the one that  comes  thru regardless of the mask,
1841          * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
1842          * to quench it as it doesn't get cleared by just writing 1 to the  ECI
1843          * bit...
1844          */
1845         intr_enable = sh_eth_read(ndev, EESIPR);
1846         intr_status &= intr_enable | EESIPR_ECIIP;
1847         if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1848                            cd->eesr_err_check))
1849                 ret = IRQ_HANDLED;
1850         else
1851                 goto out;
1852
1853         if (unlikely(!mdp->irq_enabled)) {
1854                 sh_eth_write(ndev, 0, EESIPR);
1855                 goto out;
1856         }
1857
1858         if (intr_status & EESR_RX_CHECK) {
1859                 if (napi_schedule_prep(&mdp->napi)) {
1860                         /* Mask Rx interrupts */
1861                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1862                                      EESIPR);
1863                         __napi_schedule(&mdp->napi);
1864                 } else {
1865                         netdev_warn(ndev,
1866                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1867                                     intr_status, intr_enable);
1868                 }
1869         }
1870
1871         /* Tx Check */
1872         if (intr_status & cd->tx_check) {
1873                 /* Clear Tx interrupts */
1874                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1875
1876                 sh_eth_tx_free(ndev, true);
1877                 netif_wake_queue(ndev);
1878         }
1879
1880         /* E-MAC interrupt */
1881         if (intr_status & EESR_ECI)
1882                 sh_eth_emac_interrupt(ndev);
1883
1884         if (intr_status & cd->eesr_err_check) {
1885                 /* Clear error interrupts */
1886                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1887
1888                 sh_eth_error(ndev, intr_status);
1889         }
1890
1891 out:
1892         spin_unlock(&mdp->lock);
1893
1894         return ret;
1895 }
1896
1897 static int sh_eth_poll(struct napi_struct *napi, int budget)
1898 {
1899         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1900                                                   napi);
1901         struct net_device *ndev = napi->dev;
1902         int quota = budget;
1903         u32 intr_status;
1904
1905         for (;;) {
1906                 intr_status = sh_eth_read(ndev, EESR);
1907                 if (!(intr_status & EESR_RX_CHECK))
1908                         break;
1909                 /* Clear Rx interrupts */
1910                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1911
1912                 if (sh_eth_rx(ndev, intr_status, &quota))
1913                         goto out;
1914         }
1915
1916         napi_complete(napi);
1917
1918         /* Reenable Rx interrupts */
1919         if (mdp->irq_enabled)
1920                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1921 out:
1922         return budget - quota;
1923 }
1924
1925 /* PHY state control function */
1926 static void sh_eth_adjust_link(struct net_device *ndev)
1927 {
1928         struct sh_eth_private *mdp = netdev_priv(ndev);
1929         struct phy_device *phydev = ndev->phydev;
1930         unsigned long flags;
1931         int new_state = 0;
1932
1933         spin_lock_irqsave(&mdp->lock, flags);
1934
1935         /* Disable TX and RX right over here, if E-MAC change is ignored */
1936         if (mdp->cd->no_psr || mdp->no_ether_link)
1937                 sh_eth_rcv_snd_disable(ndev);
1938
1939         if (phydev->link) {
1940                 if (phydev->duplex != mdp->duplex) {
1941                         new_state = 1;
1942                         mdp->duplex = phydev->duplex;
1943                         if (mdp->cd->set_duplex)
1944                                 mdp->cd->set_duplex(ndev);
1945                 }
1946
1947                 if (phydev->speed != mdp->speed) {
1948                         new_state = 1;
1949                         mdp->speed = phydev->speed;
1950                         if (mdp->cd->set_rate)
1951                                 mdp->cd->set_rate(ndev);
1952                 }
1953                 if (!mdp->link) {
1954                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1955                         new_state = 1;
1956                         mdp->link = phydev->link;
1957                 }
1958         } else if (mdp->link) {
1959                 new_state = 1;
1960                 mdp->link = 0;
1961                 mdp->speed = 0;
1962                 mdp->duplex = -1;
1963         }
1964
1965         /* Enable TX and RX right over here, if E-MAC change is ignored */
1966         if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1967                 sh_eth_rcv_snd_enable(ndev);
1968
1969         mmiowb();
1970         spin_unlock_irqrestore(&mdp->lock, flags);
1971
1972         if (new_state && netif_msg_link(mdp))
1973                 phy_print_status(phydev);
1974 }
1975
1976 /* PHY init function */
1977 static int sh_eth_phy_init(struct net_device *ndev)
1978 {
1979         struct device_node *np = ndev->dev.parent->of_node;
1980         struct sh_eth_private *mdp = netdev_priv(ndev);
1981         struct phy_device *phydev;
1982
1983         mdp->link = 0;
1984         mdp->speed = 0;
1985         mdp->duplex = -1;
1986
1987         /* Try connect to PHY */
1988         if (np) {
1989                 struct device_node *pn;
1990
1991                 pn = of_parse_phandle(np, "phy-handle", 0);
1992                 phydev = of_phy_connect(ndev, pn,
1993                                         sh_eth_adjust_link, 0,
1994                                         mdp->phy_interface);
1995
1996                 of_node_put(pn);
1997                 if (!phydev)
1998                         phydev = ERR_PTR(-ENOENT);
1999         } else {
2000                 char phy_id[MII_BUS_ID_SIZE + 3];
2001
2002                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2003                          mdp->mii_bus->id, mdp->phy_id);
2004
2005                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2006                                      mdp->phy_interface);
2007         }
2008
2009         if (IS_ERR(phydev)) {
2010                 netdev_err(ndev, "failed to connect PHY\n");
2011                 return PTR_ERR(phydev);
2012         }
2013
2014         /* mask with MAC supported features */
2015         if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2016                 int err = phy_set_max_speed(phydev, SPEED_100);
2017                 if (err) {
2018                         netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2019                         phy_disconnect(phydev);
2020                         return err;
2021                 }
2022         }
2023
2024         phy_attached_info(phydev);
2025
2026         return 0;
2027 }
2028
2029 /* PHY control start function */
2030 static int sh_eth_phy_start(struct net_device *ndev)
2031 {
2032         int ret;
2033
2034         ret = sh_eth_phy_init(ndev);
2035         if (ret)
2036                 return ret;
2037
2038         phy_start(ndev->phydev);
2039
2040         return 0;
2041 }
2042
2043 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2044  * version must be bumped as well.  Just adding registers up to that
2045  * limit is fine, as long as the existing register indices don't
2046  * change.
2047  */
2048 #define SH_ETH_REG_DUMP_VERSION         1
2049 #define SH_ETH_REG_DUMP_MAX_REGS        256
2050
2051 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2052 {
2053         struct sh_eth_private *mdp = netdev_priv(ndev);
2054         struct sh_eth_cpu_data *cd = mdp->cd;
2055         u32 *valid_map;
2056         size_t len;
2057
2058         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2059
2060         /* Dump starts with a bitmap that tells ethtool which
2061          * registers are defined for this chip.
2062          */
2063         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2064         if (buf) {
2065                 valid_map = buf;
2066                 buf += len;
2067         } else {
2068                 valid_map = NULL;
2069         }
2070
2071         /* Add a register to the dump, if it has a defined offset.
2072          * This automatically skips most undefined registers, but for
2073          * some it is also necessary to check a capability flag in
2074          * struct sh_eth_cpu_data.
2075          */
2076 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2077 #define add_reg_from(reg, read_expr) do {                               \
2078                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
2079                         if (buf) {                                      \
2080                                 mark_reg_valid(reg);                    \
2081                                 *buf++ = read_expr;                     \
2082                         }                                               \
2083                         ++len;                                          \
2084                 }                                                       \
2085         } while (0)
2086 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2087 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2088
2089         add_reg(EDSR);
2090         add_reg(EDMR);
2091         add_reg(EDTRR);
2092         add_reg(EDRRR);
2093         add_reg(EESR);
2094         add_reg(EESIPR);
2095         add_reg(TDLAR);
2096         add_reg(TDFAR);
2097         add_reg(TDFXR);
2098         add_reg(TDFFR);
2099         add_reg(RDLAR);
2100         add_reg(RDFAR);
2101         add_reg(RDFXR);
2102         add_reg(RDFFR);
2103         add_reg(TRSCER);
2104         add_reg(RMFCR);
2105         add_reg(TFTR);
2106         add_reg(FDR);
2107         add_reg(RMCR);
2108         add_reg(TFUCR);
2109         add_reg(RFOCR);
2110         if (cd->rmiimode)
2111                 add_reg(RMIIMODE);
2112         add_reg(FCFTR);
2113         if (cd->rpadir)
2114                 add_reg(RPADIR);
2115         if (!cd->no_trimd)
2116                 add_reg(TRIMD);
2117         add_reg(ECMR);
2118         add_reg(ECSR);
2119         add_reg(ECSIPR);
2120         add_reg(PIR);
2121         if (!cd->no_psr)
2122                 add_reg(PSR);
2123         add_reg(RDMLR);
2124         add_reg(RFLR);
2125         add_reg(IPGR);
2126         if (cd->apr)
2127                 add_reg(APR);
2128         if (cd->mpr)
2129                 add_reg(MPR);
2130         add_reg(RFCR);
2131         add_reg(RFCF);
2132         if (cd->tpauser)
2133                 add_reg(TPAUSER);
2134         add_reg(TPAUSECR);
2135         add_reg(GECMR);
2136         if (cd->bculr)
2137                 add_reg(BCULR);
2138         add_reg(MAHR);
2139         add_reg(MALR);
2140         add_reg(TROCR);
2141         add_reg(CDCR);
2142         add_reg(LCCR);
2143         add_reg(CNDCR);
2144         add_reg(CEFCR);
2145         add_reg(FRECR);
2146         add_reg(TSFRCR);
2147         add_reg(TLFRCR);
2148         add_reg(CERCR);
2149         add_reg(CEECR);
2150         add_reg(MAFCR);
2151         if (cd->rtrate)
2152                 add_reg(RTRATE);
2153         if (cd->hw_checksum)
2154                 add_reg(CSMR);
2155         if (cd->select_mii)
2156                 add_reg(RMII_MII);
2157         if (cd->tsu) {
2158                 add_tsu_reg(ARSTR);
2159                 add_tsu_reg(TSU_CTRST);
2160                 add_tsu_reg(TSU_FWEN0);
2161                 add_tsu_reg(TSU_FWEN1);
2162                 add_tsu_reg(TSU_FCM);
2163                 add_tsu_reg(TSU_BSYSL0);
2164                 add_tsu_reg(TSU_BSYSL1);
2165                 add_tsu_reg(TSU_PRISL0);
2166                 add_tsu_reg(TSU_PRISL1);
2167                 add_tsu_reg(TSU_FWSL0);
2168                 add_tsu_reg(TSU_FWSL1);
2169                 add_tsu_reg(TSU_FWSLC);
2170                 add_tsu_reg(TSU_QTAGM0);
2171                 add_tsu_reg(TSU_QTAGM1);
2172                 add_tsu_reg(TSU_FWSR);
2173                 add_tsu_reg(TSU_FWINMK);
2174                 add_tsu_reg(TSU_ADQT0);
2175                 add_tsu_reg(TSU_ADQT1);
2176                 add_tsu_reg(TSU_VTAG0);
2177                 add_tsu_reg(TSU_VTAG1);
2178                 add_tsu_reg(TSU_ADSBSY);
2179                 add_tsu_reg(TSU_TEN);
2180                 add_tsu_reg(TSU_POST1);
2181                 add_tsu_reg(TSU_POST2);
2182                 add_tsu_reg(TSU_POST3);
2183                 add_tsu_reg(TSU_POST4);
2184                 /* This is the start of a table, not just a single register. */
2185                 if (buf) {
2186                         unsigned int i;
2187
2188                         mark_reg_valid(TSU_ADRH0);
2189                         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2190                                 *buf++ = ioread32(mdp->tsu_addr +
2191                                                   mdp->reg_offset[TSU_ADRH0] +
2192                                                   i * 4);
2193                 }
2194                 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2195         }
2196
2197 #undef mark_reg_valid
2198 #undef add_reg_from
2199 #undef add_reg
2200 #undef add_tsu_reg
2201
2202         return len * 4;
2203 }
2204
2205 static int sh_eth_get_regs_len(struct net_device *ndev)
2206 {
2207         return __sh_eth_get_regs(ndev, NULL);
2208 }
2209
2210 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2211                             void *buf)
2212 {
2213         struct sh_eth_private *mdp = netdev_priv(ndev);
2214
2215         regs->version = SH_ETH_REG_DUMP_VERSION;
2216
2217         pm_runtime_get_sync(&mdp->pdev->dev);
2218         __sh_eth_get_regs(ndev, buf);
2219         pm_runtime_put_sync(&mdp->pdev->dev);
2220 }
2221
2222 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2223 {
2224         struct sh_eth_private *mdp = netdev_priv(ndev);
2225         return mdp->msg_enable;
2226 }
2227
2228 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2229 {
2230         struct sh_eth_private *mdp = netdev_priv(ndev);
2231         mdp->msg_enable = value;
2232 }
2233
2234 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2235         "rx_current", "tx_current",
2236         "rx_dirty", "tx_dirty",
2237 };
2238 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2239
2240 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2241 {
2242         switch (sset) {
2243         case ETH_SS_STATS:
2244                 return SH_ETH_STATS_LEN;
2245         default:
2246                 return -EOPNOTSUPP;
2247         }
2248 }
2249
2250 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2251                                      struct ethtool_stats *stats, u64 *data)
2252 {
2253         struct sh_eth_private *mdp = netdev_priv(ndev);
2254         int i = 0;
2255
2256         /* device-specific stats */
2257         data[i++] = mdp->cur_rx;
2258         data[i++] = mdp->cur_tx;
2259         data[i++] = mdp->dirty_rx;
2260         data[i++] = mdp->dirty_tx;
2261 }
2262
2263 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2264 {
2265         switch (stringset) {
2266         case ETH_SS_STATS:
2267                 memcpy(data, *sh_eth_gstrings_stats,
2268                        sizeof(sh_eth_gstrings_stats));
2269                 break;
2270         }
2271 }
2272
2273 static void sh_eth_get_ringparam(struct net_device *ndev,
2274                                  struct ethtool_ringparam *ring)
2275 {
2276         struct sh_eth_private *mdp = netdev_priv(ndev);
2277
2278         ring->rx_max_pending = RX_RING_MAX;
2279         ring->tx_max_pending = TX_RING_MAX;
2280         ring->rx_pending = mdp->num_rx_ring;
2281         ring->tx_pending = mdp->num_tx_ring;
2282 }
2283
2284 static int sh_eth_set_ringparam(struct net_device *ndev,
2285                                 struct ethtool_ringparam *ring)
2286 {
2287         struct sh_eth_private *mdp = netdev_priv(ndev);
2288         int ret;
2289
2290         if (ring->tx_pending > TX_RING_MAX ||
2291             ring->rx_pending > RX_RING_MAX ||
2292             ring->tx_pending < TX_RING_MIN ||
2293             ring->rx_pending < RX_RING_MIN)
2294                 return -EINVAL;
2295         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2296                 return -EINVAL;
2297
2298         if (netif_running(ndev)) {
2299                 netif_device_detach(ndev);
2300                 netif_tx_disable(ndev);
2301
2302                 /* Serialise with the interrupt handler and NAPI, then
2303                  * disable interrupts.  We have to clear the
2304                  * irq_enabled flag first to ensure that interrupts
2305                  * won't be re-enabled.
2306                  */
2307                 mdp->irq_enabled = false;
2308                 synchronize_irq(ndev->irq);
2309                 napi_synchronize(&mdp->napi);
2310                 sh_eth_write(ndev, 0x0000, EESIPR);
2311
2312                 sh_eth_dev_exit(ndev);
2313
2314                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2315                 sh_eth_ring_free(ndev);
2316         }
2317
2318         /* Set new parameters */
2319         mdp->num_rx_ring = ring->rx_pending;
2320         mdp->num_tx_ring = ring->tx_pending;
2321
2322         if (netif_running(ndev)) {
2323                 ret = sh_eth_ring_init(ndev);
2324                 if (ret < 0) {
2325                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2326                                    __func__);
2327                         return ret;
2328                 }
2329                 ret = sh_eth_dev_init(ndev);
2330                 if (ret < 0) {
2331                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2332                                    __func__);
2333                         return ret;
2334                 }
2335
2336                 netif_device_attach(ndev);
2337         }
2338
2339         return 0;
2340 }
2341
2342 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2343 {
2344         struct sh_eth_private *mdp = netdev_priv(ndev);
2345
2346         wol->supported = 0;
2347         wol->wolopts = 0;
2348
2349         if (mdp->cd->magic) {
2350                 wol->supported = WAKE_MAGIC;
2351                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2352         }
2353 }
2354
2355 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2356 {
2357         struct sh_eth_private *mdp = netdev_priv(ndev);
2358
2359         if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2360                 return -EOPNOTSUPP;
2361
2362         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2363
2364         device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2365
2366         return 0;
2367 }
2368
2369 static const struct ethtool_ops sh_eth_ethtool_ops = {
2370         .get_regs_len   = sh_eth_get_regs_len,
2371         .get_regs       = sh_eth_get_regs,
2372         .nway_reset     = phy_ethtool_nway_reset,
2373         .get_msglevel   = sh_eth_get_msglevel,
2374         .set_msglevel   = sh_eth_set_msglevel,
2375         .get_link       = ethtool_op_get_link,
2376         .get_strings    = sh_eth_get_strings,
2377         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2378         .get_sset_count     = sh_eth_get_sset_count,
2379         .get_ringparam  = sh_eth_get_ringparam,
2380         .set_ringparam  = sh_eth_set_ringparam,
2381         .get_link_ksettings = phy_ethtool_get_link_ksettings,
2382         .set_link_ksettings = phy_ethtool_set_link_ksettings,
2383         .get_wol        = sh_eth_get_wol,
2384         .set_wol        = sh_eth_set_wol,
2385 };
2386
2387 /* network device open function */
2388 static int sh_eth_open(struct net_device *ndev)
2389 {
2390         struct sh_eth_private *mdp = netdev_priv(ndev);
2391         int ret;
2392
2393         pm_runtime_get_sync(&mdp->pdev->dev);
2394
2395         napi_enable(&mdp->napi);
2396
2397         ret = request_irq(ndev->irq, sh_eth_interrupt,
2398                           mdp->cd->irq_flags, ndev->name, ndev);
2399         if (ret) {
2400                 netdev_err(ndev, "Can not assign IRQ number\n");
2401                 goto out_napi_off;
2402         }
2403
2404         /* Descriptor set */
2405         ret = sh_eth_ring_init(ndev);
2406         if (ret)
2407                 goto out_free_irq;
2408
2409         /* device init */
2410         ret = sh_eth_dev_init(ndev);
2411         if (ret)
2412                 goto out_free_irq;
2413
2414         /* PHY control start*/
2415         ret = sh_eth_phy_start(ndev);
2416         if (ret)
2417                 goto out_free_irq;
2418
2419         netif_start_queue(ndev);
2420
2421         mdp->is_opened = 1;
2422
2423         return ret;
2424
2425 out_free_irq:
2426         free_irq(ndev->irq, ndev);
2427 out_napi_off:
2428         napi_disable(&mdp->napi);
2429         pm_runtime_put_sync(&mdp->pdev->dev);
2430         return ret;
2431 }
2432
2433 /* Timeout function */
2434 static void sh_eth_tx_timeout(struct net_device *ndev)
2435 {
2436         struct sh_eth_private *mdp = netdev_priv(ndev);
2437         struct sh_eth_rxdesc *rxdesc;
2438         int i;
2439
2440         netif_stop_queue(ndev);
2441
2442         netif_err(mdp, timer, ndev,
2443                   "transmit timed out, status %8.8x, resetting...\n",
2444                   sh_eth_read(ndev, EESR));
2445
2446         /* tx_errors count up */
2447         ndev->stats.tx_errors++;
2448
2449         /* Free all the skbuffs in the Rx queue. */
2450         for (i = 0; i < mdp->num_rx_ring; i++) {
2451                 rxdesc = &mdp->rx_ring[i];
2452                 rxdesc->status = cpu_to_le32(0);
2453                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2454                 dev_kfree_skb(mdp->rx_skbuff[i]);
2455                 mdp->rx_skbuff[i] = NULL;
2456         }
2457         for (i = 0; i < mdp->num_tx_ring; i++) {
2458                 dev_kfree_skb(mdp->tx_skbuff[i]);
2459                 mdp->tx_skbuff[i] = NULL;
2460         }
2461
2462         /* device init */
2463         sh_eth_dev_init(ndev);
2464
2465         netif_start_queue(ndev);
2466 }
2467
2468 /* Packet transmit function */
2469 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2470 {
2471         struct sh_eth_private *mdp = netdev_priv(ndev);
2472         struct sh_eth_txdesc *txdesc;
2473         dma_addr_t dma_addr;
2474         u32 entry;
2475         unsigned long flags;
2476
2477         spin_lock_irqsave(&mdp->lock, flags);
2478         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2479                 if (!sh_eth_tx_free(ndev, true)) {
2480                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2481                         netif_stop_queue(ndev);
2482                         spin_unlock_irqrestore(&mdp->lock, flags);
2483                         return NETDEV_TX_BUSY;
2484                 }
2485         }
2486         spin_unlock_irqrestore(&mdp->lock, flags);
2487
2488         if (skb_put_padto(skb, ETH_ZLEN))
2489                 return NETDEV_TX_OK;
2490
2491         entry = mdp->cur_tx % mdp->num_tx_ring;
2492         mdp->tx_skbuff[entry] = skb;
2493         txdesc = &mdp->tx_ring[entry];
2494         /* soft swap. */
2495         if (!mdp->cd->hw_swap)
2496                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2497         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2498                                   DMA_TO_DEVICE);
2499         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2500                 kfree_skb(skb);
2501                 return NETDEV_TX_OK;
2502         }
2503         txdesc->addr = cpu_to_le32(dma_addr);
2504         txdesc->len  = cpu_to_le32(skb->len << 16);
2505
2506         dma_wmb(); /* TACT bit must be set after all the above writes */
2507         if (entry >= mdp->num_tx_ring - 1)
2508                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2509         else
2510                 txdesc->status |= cpu_to_le32(TD_TACT);
2511
2512         mdp->cur_tx++;
2513
2514         if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2515                 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2516
2517         return NETDEV_TX_OK;
2518 }
2519
2520 /* The statistics registers have write-clear behaviour, which means we
2521  * will lose any increment between the read and write.  We mitigate
2522  * this by only clearing when we read a non-zero value, so we will
2523  * never falsely report a total of zero.
2524  */
2525 static void
2526 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2527 {
2528         u32 delta = sh_eth_read(ndev, reg);
2529
2530         if (delta) {
2531                 *stat += delta;
2532                 sh_eth_write(ndev, 0, reg);
2533         }
2534 }
2535
2536 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2537 {
2538         struct sh_eth_private *mdp = netdev_priv(ndev);
2539
2540         if (mdp->cd->no_tx_cntrs)
2541                 return &ndev->stats;
2542
2543         if (!mdp->is_opened)
2544                 return &ndev->stats;
2545
2546         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2547         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2548         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2549
2550         if (mdp->cd->cexcr) {
2551                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2552                                    CERCR);
2553                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2554                                    CEECR);
2555         } else {
2556                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2557                                    CNDCR);
2558         }
2559
2560         return &ndev->stats;
2561 }
2562
2563 /* device close function */
2564 static int sh_eth_close(struct net_device *ndev)
2565 {
2566         struct sh_eth_private *mdp = netdev_priv(ndev);
2567
2568         netif_stop_queue(ndev);
2569
2570         /* Serialise with the interrupt handler and NAPI, then disable
2571          * interrupts.  We have to clear the irq_enabled flag first to
2572          * ensure that interrupts won't be re-enabled.
2573          */
2574         mdp->irq_enabled = false;
2575         synchronize_irq(ndev->irq);
2576         napi_disable(&mdp->napi);
2577         sh_eth_write(ndev, 0x0000, EESIPR);
2578
2579         sh_eth_dev_exit(ndev);
2580
2581         /* PHY Disconnect */
2582         if (ndev->phydev) {
2583                 phy_stop(ndev->phydev);
2584                 phy_disconnect(ndev->phydev);
2585         }
2586
2587         free_irq(ndev->irq, ndev);
2588
2589         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2590         sh_eth_ring_free(ndev);
2591
2592         pm_runtime_put_sync(&mdp->pdev->dev);
2593
2594         mdp->is_opened = 0;
2595
2596         return 0;
2597 }
2598
2599 /* ioctl to device function */
2600 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2601 {
2602         struct phy_device *phydev = ndev->phydev;
2603
2604         if (!netif_running(ndev))
2605                 return -EINVAL;
2606
2607         if (!phydev)
2608                 return -ENODEV;
2609
2610         return phy_mii_ioctl(phydev, rq, cmd);
2611 }
2612
2613 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2614 {
2615         if (netif_running(ndev))
2616                 return -EBUSY;
2617
2618         ndev->mtu = new_mtu;
2619         netdev_update_features(ndev);
2620
2621         return 0;
2622 }
2623
2624 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2625 static u32 sh_eth_tsu_get_post_mask(int entry)
2626 {
2627         return 0x0f << (28 - ((entry % 8) * 4));
2628 }
2629
2630 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2631 {
2632         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2633 }
2634
2635 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2636                                              int entry)
2637 {
2638         struct sh_eth_private *mdp = netdev_priv(ndev);
2639         int reg = TSU_POST1 + entry / 8;
2640         u32 tmp;
2641
2642         tmp = sh_eth_tsu_read(mdp, reg);
2643         sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2644 }
2645
2646 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2647                                               int entry)
2648 {
2649         struct sh_eth_private *mdp = netdev_priv(ndev);
2650         int reg = TSU_POST1 + entry / 8;
2651         u32 post_mask, ref_mask, tmp;
2652
2653         post_mask = sh_eth_tsu_get_post_mask(entry);
2654         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2655
2656         tmp = sh_eth_tsu_read(mdp, reg);
2657         sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2658
2659         /* If other port enables, the function returns "true" */
2660         return tmp & ref_mask;
2661 }
2662
2663 static int sh_eth_tsu_busy(struct net_device *ndev)
2664 {
2665         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2666         struct sh_eth_private *mdp = netdev_priv(ndev);
2667
2668         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2669                 udelay(10);
2670                 timeout--;
2671                 if (timeout <= 0) {
2672                         netdev_err(ndev, "%s: timeout\n", __func__);
2673                         return -ETIMEDOUT;
2674                 }
2675         }
2676
2677         return 0;
2678 }
2679
2680 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2681                                   const u8 *addr)
2682 {
2683         u32 val;
2684
2685         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2686         iowrite32(val, reg);
2687         if (sh_eth_tsu_busy(ndev) < 0)
2688                 return -EBUSY;
2689
2690         val = addr[4] << 8 | addr[5];
2691         iowrite32(val, reg + 4);
2692         if (sh_eth_tsu_busy(ndev) < 0)
2693                 return -EBUSY;
2694
2695         return 0;
2696 }
2697
2698 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2699 {
2700         u32 val;
2701
2702         val = ioread32(reg);
2703         addr[0] = (val >> 24) & 0xff;
2704         addr[1] = (val >> 16) & 0xff;
2705         addr[2] = (val >> 8) & 0xff;
2706         addr[3] = val & 0xff;
2707         val = ioread32(reg + 4);
2708         addr[4] = (val >> 8) & 0xff;
2709         addr[5] = val & 0xff;
2710 }
2711
2712
2713 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2714 {
2715         struct sh_eth_private *mdp = netdev_priv(ndev);
2716         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2717         int i;
2718         u8 c_addr[ETH_ALEN];
2719
2720         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2721                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2722                 if (ether_addr_equal(addr, c_addr))
2723                         return i;
2724         }
2725
2726         return -ENOENT;
2727 }
2728
2729 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2730 {
2731         u8 blank[ETH_ALEN];
2732         int entry;
2733
2734         memset(blank, 0, sizeof(blank));
2735         entry = sh_eth_tsu_find_entry(ndev, blank);
2736         return (entry < 0) ? -ENOMEM : entry;
2737 }
2738
2739 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2740                                               int entry)
2741 {
2742         struct sh_eth_private *mdp = netdev_priv(ndev);
2743         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2744         int ret;
2745         u8 blank[ETH_ALEN];
2746
2747         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2748                          ~(1 << (31 - entry)), TSU_TEN);
2749
2750         memset(blank, 0, sizeof(blank));
2751         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2752         if (ret < 0)
2753                 return ret;
2754         return 0;
2755 }
2756
2757 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2758 {
2759         struct sh_eth_private *mdp = netdev_priv(ndev);
2760         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2761         int i, ret;
2762
2763         if (!mdp->cd->tsu)
2764                 return 0;
2765
2766         i = sh_eth_tsu_find_entry(ndev, addr);
2767         if (i < 0) {
2768                 /* No entry found, create one */
2769                 i = sh_eth_tsu_find_empty(ndev);
2770                 if (i < 0)
2771                         return -ENOMEM;
2772                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2773                 if (ret < 0)
2774                         return ret;
2775
2776                 /* Enable the entry */
2777                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2778                                  (1 << (31 - i)), TSU_TEN);
2779         }
2780
2781         /* Entry found or created, enable POST */
2782         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2783
2784         return 0;
2785 }
2786
2787 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2788 {
2789         struct sh_eth_private *mdp = netdev_priv(ndev);
2790         int i, ret;
2791
2792         if (!mdp->cd->tsu)
2793                 return 0;
2794
2795         i = sh_eth_tsu_find_entry(ndev, addr);
2796         if (i) {
2797                 /* Entry found */
2798                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2799                         goto done;
2800
2801                 /* Disable the entry if both ports was disabled */
2802                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2803                 if (ret < 0)
2804                         return ret;
2805         }
2806 done:
2807         return 0;
2808 }
2809
2810 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2811 {
2812         struct sh_eth_private *mdp = netdev_priv(ndev);
2813         int i, ret;
2814
2815         if (!mdp->cd->tsu)
2816                 return 0;
2817
2818         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2819                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2820                         continue;
2821
2822                 /* Disable the entry if both ports was disabled */
2823                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2824                 if (ret < 0)
2825                         return ret;
2826         }
2827
2828         return 0;
2829 }
2830
2831 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2832 {
2833         struct sh_eth_private *mdp = netdev_priv(ndev);
2834         u8 addr[ETH_ALEN];
2835         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2836         int i;
2837
2838         if (!mdp->cd->tsu)
2839                 return;
2840
2841         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2842                 sh_eth_tsu_read_entry(reg_offset, addr);
2843                 if (is_multicast_ether_addr(addr))
2844                         sh_eth_tsu_del_entry(ndev, addr);
2845         }
2846 }
2847
2848 /* Update promiscuous flag and multicast filter */
2849 static void sh_eth_set_rx_mode(struct net_device *ndev)
2850 {
2851         struct sh_eth_private *mdp = netdev_priv(ndev);
2852         u32 ecmr_bits;
2853         int mcast_all = 0;
2854         unsigned long flags;
2855
2856         spin_lock_irqsave(&mdp->lock, flags);
2857         /* Initial condition is MCT = 1, PRM = 0.
2858          * Depending on ndev->flags, set PRM or clear MCT
2859          */
2860         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2861         if (mdp->cd->tsu)
2862                 ecmr_bits |= ECMR_MCT;
2863
2864         if (!(ndev->flags & IFF_MULTICAST)) {
2865                 sh_eth_tsu_purge_mcast(ndev);
2866                 mcast_all = 1;
2867         }
2868         if (ndev->flags & IFF_ALLMULTI) {
2869                 sh_eth_tsu_purge_mcast(ndev);
2870                 ecmr_bits &= ~ECMR_MCT;
2871                 mcast_all = 1;
2872         }
2873
2874         if (ndev->flags & IFF_PROMISC) {
2875                 sh_eth_tsu_purge_all(ndev);
2876                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2877         } else if (mdp->cd->tsu) {
2878                 struct netdev_hw_addr *ha;
2879                 netdev_for_each_mc_addr(ha, ndev) {
2880                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2881                                 continue;
2882
2883                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2884                                 if (!mcast_all) {
2885                                         sh_eth_tsu_purge_mcast(ndev);
2886                                         ecmr_bits &= ~ECMR_MCT;
2887                                         mcast_all = 1;
2888                                 }
2889                         }
2890                 }
2891         }
2892
2893         /* update the ethernet mode */
2894         sh_eth_write(ndev, ecmr_bits, ECMR);
2895
2896         spin_unlock_irqrestore(&mdp->lock, flags);
2897 }
2898
2899 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2900 {
2901         if (!mdp->port)
2902                 return TSU_VTAG0;
2903         else
2904                 return TSU_VTAG1;
2905 }
2906
2907 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2908                                   __be16 proto, u16 vid)
2909 {
2910         struct sh_eth_private *mdp = netdev_priv(ndev);
2911         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2912
2913         if (unlikely(!mdp->cd->tsu))
2914                 return -EPERM;
2915
2916         /* No filtering if vid = 0 */
2917         if (!vid)
2918                 return 0;
2919
2920         mdp->vlan_num_ids++;
2921
2922         /* The controller has one VLAN tag HW filter. So, if the filter is
2923          * already enabled, the driver disables it and the filte
2924          */
2925         if (mdp->vlan_num_ids > 1) {
2926                 /* disable VLAN filter */
2927                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2928                 return 0;
2929         }
2930
2931         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2932                          vtag_reg_index);
2933
2934         return 0;
2935 }
2936
2937 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2938                                    __be16 proto, u16 vid)
2939 {
2940         struct sh_eth_private *mdp = netdev_priv(ndev);
2941         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2942
2943         if (unlikely(!mdp->cd->tsu))
2944                 return -EPERM;
2945
2946         /* No filtering if vid = 0 */
2947         if (!vid)
2948                 return 0;
2949
2950         mdp->vlan_num_ids--;
2951         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2952
2953         return 0;
2954 }
2955
2956 /* SuperH's TSU register init function */
2957 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2958 {
2959         if (!mdp->cd->dual_port) {
2960                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2961                 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2962                                  TSU_FWSLC);    /* Enable POST registers */
2963                 return;
2964         }
2965
2966         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2967         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2968         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2969         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2970         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2971         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2972         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2973         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2974         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2975         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2976         sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2977         sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2978         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2979         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2980         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2981         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2982         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2983         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2984         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2985 }
2986
2987 /* MDIO bus release function */
2988 static int sh_mdio_release(struct sh_eth_private *mdp)
2989 {
2990         /* unregister mdio bus */
2991         mdiobus_unregister(mdp->mii_bus);
2992
2993         /* free bitbang info */
2994         free_mdio_bitbang(mdp->mii_bus);
2995
2996         return 0;
2997 }
2998
2999 /* MDIO bus init function */
3000 static int sh_mdio_init(struct sh_eth_private *mdp,
3001                         struct sh_eth_plat_data *pd)
3002 {
3003         int ret;
3004         struct bb_info *bitbang;
3005         struct platform_device *pdev = mdp->pdev;
3006         struct device *dev = &mdp->pdev->dev;
3007
3008         /* create bit control struct for PHY */
3009         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3010         if (!bitbang)
3011                 return -ENOMEM;
3012
3013         /* bitbang init */
3014         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3015         bitbang->set_gate = pd->set_mdio_gate;
3016         bitbang->ctrl.ops = &bb_ops;
3017
3018         /* MII controller setting */
3019         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3020         if (!mdp->mii_bus)
3021                 return -ENOMEM;
3022
3023         /* Hook up MII support for ethtool */
3024         mdp->mii_bus->name = "sh_mii";
3025         mdp->mii_bus->parent = dev;
3026         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3027                  pdev->name, pdev->id);
3028
3029         /* register MDIO bus */
3030         if (pd->phy_irq > 0)
3031                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3032
3033         ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3034         if (ret)
3035                 goto out_free_bus;
3036
3037         return 0;
3038
3039 out_free_bus:
3040         free_mdio_bitbang(mdp->mii_bus);
3041         return ret;
3042 }
3043
3044 static const u16 *sh_eth_get_register_offset(int register_type)
3045 {
3046         const u16 *reg_offset = NULL;
3047
3048         switch (register_type) {
3049         case SH_ETH_REG_GIGABIT:
3050                 reg_offset = sh_eth_offset_gigabit;
3051                 break;
3052         case SH_ETH_REG_FAST_RZ:
3053                 reg_offset = sh_eth_offset_fast_rz;
3054                 break;
3055         case SH_ETH_REG_FAST_RCAR:
3056                 reg_offset = sh_eth_offset_fast_rcar;
3057                 break;
3058         case SH_ETH_REG_FAST_SH4:
3059                 reg_offset = sh_eth_offset_fast_sh4;
3060                 break;
3061         case SH_ETH_REG_FAST_SH3_SH2:
3062                 reg_offset = sh_eth_offset_fast_sh3_sh2;
3063                 break;
3064         }
3065
3066         return reg_offset;
3067 }
3068
3069 static const struct net_device_ops sh_eth_netdev_ops = {
3070         .ndo_open               = sh_eth_open,
3071         .ndo_stop               = sh_eth_close,
3072         .ndo_start_xmit         = sh_eth_start_xmit,
3073         .ndo_get_stats          = sh_eth_get_stats,
3074         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3075         .ndo_tx_timeout         = sh_eth_tx_timeout,
3076         .ndo_do_ioctl           = sh_eth_do_ioctl,
3077         .ndo_change_mtu         = sh_eth_change_mtu,
3078         .ndo_validate_addr      = eth_validate_addr,
3079         .ndo_set_mac_address    = eth_mac_addr,
3080 };
3081
3082 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3083         .ndo_open               = sh_eth_open,
3084         .ndo_stop               = sh_eth_close,
3085         .ndo_start_xmit         = sh_eth_start_xmit,
3086         .ndo_get_stats          = sh_eth_get_stats,
3087         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3088         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
3089         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
3090         .ndo_tx_timeout         = sh_eth_tx_timeout,
3091         .ndo_do_ioctl           = sh_eth_do_ioctl,
3092         .ndo_change_mtu         = sh_eth_change_mtu,
3093         .ndo_validate_addr      = eth_validate_addr,
3094         .ndo_set_mac_address    = eth_mac_addr,
3095 };
3096
3097 #ifdef CONFIG_OF
3098 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3099 {
3100         struct device_node *np = dev->of_node;
3101         struct sh_eth_plat_data *pdata;
3102         const char *mac_addr;
3103
3104         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3105         if (!pdata)
3106                 return NULL;
3107
3108         pdata->phy_interface = of_get_phy_mode(np);
3109
3110         mac_addr = of_get_mac_address(np);
3111         if (mac_addr)
3112                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3113
3114         pdata->no_ether_link =
3115                 of_property_read_bool(np, "renesas,no-ether-link");
3116         pdata->ether_link_active_low =
3117                 of_property_read_bool(np, "renesas,ether-link-active-low");
3118
3119         return pdata;
3120 }
3121
3122 static const struct of_device_id sh_eth_match_table[] = {
3123         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3124         { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3125         { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3126         { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3127         { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3128         { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3129         { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3130         { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3131         { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3132         { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3133         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3134         { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3135         { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3136         { }
3137 };
3138 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3139 #else
3140 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3141 {
3142         return NULL;
3143 }
3144 #endif
3145
3146 static int sh_eth_drv_probe(struct platform_device *pdev)
3147 {
3148         struct resource *res;
3149         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3150         const struct platform_device_id *id = platform_get_device_id(pdev);
3151         struct sh_eth_private *mdp;
3152         struct net_device *ndev;
3153         int ret;
3154
3155         /* get base addr */
3156         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3157
3158         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3159         if (!ndev)
3160                 return -ENOMEM;
3161
3162         pm_runtime_enable(&pdev->dev);
3163         pm_runtime_get_sync(&pdev->dev);
3164
3165         ret = platform_get_irq(pdev, 0);
3166         if (ret < 0)
3167                 goto out_release;
3168         ndev->irq = ret;
3169
3170         SET_NETDEV_DEV(ndev, &pdev->dev);
3171
3172         mdp = netdev_priv(ndev);
3173         mdp->num_tx_ring = TX_RING_SIZE;
3174         mdp->num_rx_ring = RX_RING_SIZE;
3175         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3176         if (IS_ERR(mdp->addr)) {
3177                 ret = PTR_ERR(mdp->addr);
3178                 goto out_release;
3179         }
3180
3181         ndev->base_addr = res->start;
3182
3183         spin_lock_init(&mdp->lock);
3184         mdp->pdev = pdev;
3185
3186         if (pdev->dev.of_node)
3187                 pd = sh_eth_parse_dt(&pdev->dev);
3188         if (!pd) {
3189                 dev_err(&pdev->dev, "no platform data\n");
3190                 ret = -EINVAL;
3191                 goto out_release;
3192         }
3193
3194         /* get PHY ID */
3195         mdp->phy_id = pd->phy;
3196         mdp->phy_interface = pd->phy_interface;
3197         mdp->no_ether_link = pd->no_ether_link;
3198         mdp->ether_link_active_low = pd->ether_link_active_low;
3199
3200         /* set cpu data */
3201         if (id)
3202                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3203         else
3204                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3205
3206         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3207         if (!mdp->reg_offset) {
3208                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3209                         mdp->cd->register_type);
3210                 ret = -EINVAL;
3211                 goto out_release;
3212         }
3213         sh_eth_set_default_cpu_data(mdp->cd);
3214
3215         /* User's manual states max MTU should be 2048 but due to the
3216          * alignment calculations in sh_eth_ring_init() the practical
3217          * MTU is a bit less. Maybe this can be optimized some more.
3218          */
3219         ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3220         ndev->min_mtu = ETH_MIN_MTU;
3221
3222         /* set function */
3223         if (mdp->cd->tsu)
3224                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3225         else
3226                 ndev->netdev_ops = &sh_eth_netdev_ops;
3227         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3228         ndev->watchdog_timeo = TX_TIMEOUT;
3229
3230         /* debug message level */
3231         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3232
3233         /* read and set MAC address */
3234         read_mac_address(ndev, pd->mac_addr);
3235         if (!is_valid_ether_addr(ndev->dev_addr)) {
3236                 dev_warn(&pdev->dev,
3237                          "no valid MAC address supplied, using a random one.\n");
3238                 eth_hw_addr_random(ndev);
3239         }
3240
3241         if (mdp->cd->tsu) {
3242                 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3243                 struct resource *rtsu;
3244
3245                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3246                 if (!rtsu) {
3247                         dev_err(&pdev->dev, "no TSU resource\n");
3248                         ret = -ENODEV;
3249                         goto out_release;
3250                 }
3251                 /* We can only request the  TSU region  for the first port
3252                  * of the two  sharing this TSU for the probe to succeed...
3253                  */
3254                 if (port == 0 &&
3255                     !devm_request_mem_region(&pdev->dev, rtsu->start,
3256                                              resource_size(rtsu),
3257                                              dev_name(&pdev->dev))) {
3258                         dev_err(&pdev->dev, "can't request TSU resource.\n");
3259                         ret = -EBUSY;
3260                         goto out_release;
3261                 }
3262                 /* ioremap the TSU registers */
3263                 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3264                                              resource_size(rtsu));
3265                 if (!mdp->tsu_addr) {
3266                         dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3267                         ret = -ENOMEM;
3268                         goto out_release;
3269                 }
3270                 mdp->port = port;
3271                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3272
3273                 /* Need to init only the first port of the two sharing a TSU */
3274                 if (port == 0) {
3275                         if (mdp->cd->chip_reset)
3276                                 mdp->cd->chip_reset(ndev);
3277
3278                         /* TSU init (Init only)*/
3279                         sh_eth_tsu_init(mdp);
3280                 }
3281         }
3282
3283         if (mdp->cd->rmiimode)
3284                 sh_eth_write(ndev, 0x1, RMIIMODE);
3285
3286         /* MDIO bus init */
3287         ret = sh_mdio_init(mdp, pd);
3288         if (ret) {
3289                 if (ret != -EPROBE_DEFER)
3290                         dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3291                 goto out_release;
3292         }
3293
3294         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3295
3296         /* network device register */
3297         ret = register_netdev(ndev);
3298         if (ret)
3299                 goto out_napi_del;
3300
3301         if (mdp->cd->magic)
3302                 device_set_wakeup_capable(&pdev->dev, 1);
3303
3304         /* print device information */
3305         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3306                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3307
3308         pm_runtime_put(&pdev->dev);
3309         platform_set_drvdata(pdev, ndev);
3310
3311         return ret;
3312
3313 out_napi_del:
3314         netif_napi_del(&mdp->napi);
3315         sh_mdio_release(mdp);
3316
3317 out_release:
3318         /* net_dev free */
3319         free_netdev(ndev);
3320
3321         pm_runtime_put(&pdev->dev);
3322         pm_runtime_disable(&pdev->dev);
3323         return ret;
3324 }
3325
3326 static int sh_eth_drv_remove(struct platform_device *pdev)
3327 {
3328         struct net_device *ndev = platform_get_drvdata(pdev);
3329         struct sh_eth_private *mdp = netdev_priv(ndev);
3330
3331         unregister_netdev(ndev);
3332         netif_napi_del(&mdp->napi);
3333         sh_mdio_release(mdp);
3334         pm_runtime_disable(&pdev->dev);
3335         free_netdev(ndev);
3336
3337         return 0;
3338 }
3339
3340 #ifdef CONFIG_PM
3341 #ifdef CONFIG_PM_SLEEP
3342 static int sh_eth_wol_setup(struct net_device *ndev)
3343 {
3344         struct sh_eth_private *mdp = netdev_priv(ndev);
3345
3346         /* Only allow ECI interrupts */
3347         synchronize_irq(ndev->irq);
3348         napi_disable(&mdp->napi);
3349         sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3350
3351         /* Enable MagicPacket */
3352         sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3353
3354         return enable_irq_wake(ndev->irq);
3355 }
3356
3357 static int sh_eth_wol_restore(struct net_device *ndev)
3358 {
3359         struct sh_eth_private *mdp = netdev_priv(ndev);
3360         int ret;
3361
3362         napi_enable(&mdp->napi);
3363
3364         /* Disable MagicPacket */
3365         sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3366
3367         /* The device needs to be reset to restore MagicPacket logic
3368          * for next wakeup. If we close and open the device it will
3369          * both be reset and all registers restored. This is what
3370          * happens during suspend and resume without WoL enabled.
3371          */
3372         ret = sh_eth_close(ndev);
3373         if (ret < 0)
3374                 return ret;
3375         ret = sh_eth_open(ndev);
3376         if (ret < 0)
3377                 return ret;
3378
3379         return disable_irq_wake(ndev->irq);
3380 }
3381
3382 static int sh_eth_suspend(struct device *dev)
3383 {
3384         struct net_device *ndev = dev_get_drvdata(dev);
3385         struct sh_eth_private *mdp = netdev_priv(ndev);
3386         int ret = 0;
3387
3388         if (!netif_running(ndev))
3389                 return 0;
3390
3391         netif_device_detach(ndev);
3392
3393         if (mdp->wol_enabled)
3394                 ret = sh_eth_wol_setup(ndev);
3395         else
3396                 ret = sh_eth_close(ndev);
3397
3398         return ret;
3399 }
3400
3401 static int sh_eth_resume(struct device *dev)
3402 {
3403         struct net_device *ndev = dev_get_drvdata(dev);
3404         struct sh_eth_private *mdp = netdev_priv(ndev);
3405         int ret = 0;
3406
3407         if (!netif_running(ndev))
3408                 return 0;
3409
3410         if (mdp->wol_enabled)
3411                 ret = sh_eth_wol_restore(ndev);
3412         else
3413                 ret = sh_eth_open(ndev);
3414
3415         if (ret < 0)
3416                 return ret;
3417
3418         netif_device_attach(ndev);
3419
3420         return ret;
3421 }
3422 #endif
3423
3424 static int sh_eth_runtime_nop(struct device *dev)
3425 {
3426         /* Runtime PM callback shared between ->runtime_suspend()
3427          * and ->runtime_resume(). Simply returns success.
3428          *
3429          * This driver re-initializes all registers after
3430          * pm_runtime_get_sync() anyway so there is no need
3431          * to save and restore registers here.
3432          */
3433         return 0;
3434 }
3435
3436 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3437         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3438         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3439 };
3440 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3441 #else
3442 #define SH_ETH_PM_OPS NULL
3443 #endif
3444
3445 static const struct platform_device_id sh_eth_id_table[] = {
3446         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3447         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3448         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3449         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3450         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3451         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3452         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3453         { }
3454 };
3455 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3456
3457 static struct platform_driver sh_eth_driver = {
3458         .probe = sh_eth_drv_probe,
3459         .remove = sh_eth_drv_remove,
3460         .id_table = sh_eth_id_table,
3461         .driver = {
3462                    .name = CARDNAME,
3463                    .pm = SH_ETH_PM_OPS,
3464                    .of_match_table = of_match_ptr(sh_eth_match_table),
3465         },
3466 };
3467
3468 module_platform_driver(sh_eth_driver);
3469
3470 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3471 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3472 MODULE_LICENSE("GPL v2");