drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
 103 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
 104 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
 105 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
 106 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
 107 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 332         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 333         { PCI_VENDOR_ID_DLINK,                  0x4300,
 334                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 338         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 339         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 340                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 341         { 0x0001,                               0x8168,
 342                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 343         {0,},
 344 };
 345
 346 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 347
 348 static int rx_buf_sz = 16383;
 349 static int use_dac = -1;
 350 static struct {
 351         u32 msg_enable;
 352 } debug = { -1 };
 353
 354 enum rtl_registers {
 355         MAC0            = 0,    /* Ethernet hardware address. */
 356         MAC4            = 4,
 357         MAR0            = 8,    /* Multicast filter. */
 358         CounterAddrLow          = 0x10,
 359         CounterAddrHigh         = 0x14,
 360         TxDescStartAddrLow      = 0x20,
 361         TxDescStartAddrHigh     = 0x24,
 362         TxHDescStartAddrLow     = 0x28,
 363         TxHDescStartAddrHigh    = 0x2c,
 364         FLASH           = 0x30,
 365         ERSR            = 0x36,
 366         ChipCmd         = 0x37,
 367         TxPoll          = 0x38,
 368         IntrMask        = 0x3c,
 369         IntrStatus      = 0x3e,
 370
 371         TxConfig        = 0x40,
 372 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 373 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 374
 375         RxConfig        = 0x44,
 376 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 377 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 378 #define RXCFG_FIFO_SHIFT                13
 379                                         /* No threshold before first PCI xfer */
 380 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 381 #define RX_EARLY_OFF                    (1 << 11)
 382 #define RXCFG_DMA_SHIFT                 8
 383                                         /* Unlimited maximum PCI burst. */
 384 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 385
 386         RxMissed        = 0x4c,
 387         Cfg9346         = 0x50,
 388         Config0         = 0x51,
 389         Config1         = 0x52,
 390         Config2         = 0x53,
 391 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 392
 393         Config3         = 0x54,
 394         Config4         = 0x55,
 395         Config5         = 0x56,
 396         MultiIntr       = 0x5c,
 397         PHYAR           = 0x60,
 398         PHYstatus       = 0x6c,
 399         RxMaxSize       = 0xda,
 400         CPlusCmd        = 0xe0,
 401         IntrMitigate    = 0xe2,
 402
 403 #define RTL_COALESCE_MASK       0x0f
 404 #define RTL_COALESCE_SHIFT      4
 405 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 406 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 407
 408         RxDescAddrLow   = 0xe4,
 409         RxDescAddrHigh  = 0xe8,
 410         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 411
 412 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 413
 414         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 415
 416 #define TxPacketMax     (8064 >> 7)
 417 #define EarlySize       0x27
 418
 419         FuncEvent       = 0xf0,
 420         FuncEventMask   = 0xf4,
 421         FuncPresetState = 0xf8,
 422         IBCR0           = 0xf8,
 423         IBCR2           = 0xf9,
 424         IBIMR0          = 0xfa,
 425         IBISR0          = 0xfb,
 426         FuncForceEvent  = 0xfc,
 427 };
 428
 429 enum rtl8110_registers {
 430         TBICSR                  = 0x64,
 431         TBI_ANAR                = 0x68,
 432         TBI_LPAR                = 0x6a,
 433 };
 434
 435 enum rtl8168_8101_registers {
 436         CSIDR                   = 0x64,
 437         CSIAR                   = 0x68,
 438 #define CSIAR_FLAG                      0x80000000
 439 #define CSIAR_WRITE_CMD                 0x80000000
 440 #define CSIAR_BYTE_ENABLE               0x0f
 441 #define CSIAR_BYTE_ENABLE_SHIFT         12
 442 #define CSIAR_ADDR_MASK                 0x0fff
 443 #define CSIAR_FUNC_CARD                 0x00000000
 444 #define CSIAR_FUNC_SDIO                 0x00010000
 445 #define CSIAR_FUNC_NIC                  0x00020000
 446 #define CSIAR_FUNC_NIC2                 0x00010000
 447         PMCH                    = 0x6f,
 448         EPHYAR                  = 0x80,
 449 #define EPHYAR_FLAG                     0x80000000
 450 #define EPHYAR_WRITE_CMD                0x80000000
 451 #define EPHYAR_REG_MASK                 0x1f
 452 #define EPHYAR_REG_SHIFT                16
 453 #define EPHYAR_DATA_MASK                0xffff
 454         DLLPR                   = 0xd0,
 455 #define PFM_EN                          (1 << 6)
 456 #define TX_10M_PS_EN                    (1 << 7)
 457         DBG_REG                 = 0xd1,
 458 #define FIX_NAK_1                       (1 << 4)
 459 #define FIX_NAK_2                       (1 << 3)
 460         TWSI                    = 0xd2,
 461         MCU                     = 0xd3,
 462 #define NOW_IS_OOB                      (1 << 7)
 463 #define TX_EMPTY                        (1 << 5)
 464 #define RX_EMPTY                        (1 << 4)
 465 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 466 #define EN_NDP                          (1 << 3)
 467 #define EN_OOB_RESET                    (1 << 2)
 468 #define LINK_LIST_RDY                   (1 << 1)
 469         EFUSEAR                 = 0xdc,
 470 #define EFUSEAR_FLAG                    0x80000000
 471 #define EFUSEAR_WRITE_CMD               0x80000000
 472 #define EFUSEAR_READ_CMD                0x00000000
 473 #define EFUSEAR_REG_MASK                0x03ff
 474 #define EFUSEAR_REG_SHIFT               8
 475 #define EFUSEAR_DATA_MASK               0xff
 476         MISC_1                  = 0xf2,
 477 #define PFM_D3COLD_EN                   (1 << 6)
 478 };
 479
 480 enum rtl8168_registers {
 481         LED_FREQ                = 0x1a,
 482         EEE_LED                 = 0x1b,
 483         ERIDR                   = 0x70,
 484         ERIAR                   = 0x74,
 485 #define ERIAR_FLAG                      0x80000000
 486 #define ERIAR_WRITE_CMD                 0x80000000
 487 #define ERIAR_READ_CMD                  0x00000000
 488 #define ERIAR_ADDR_BYTE_ALIGN           4
 489 #define ERIAR_TYPE_SHIFT                16
 490 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 491 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 492 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 493 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 494 #define ERIAR_MASK_SHIFT                12
 495 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 496 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 497 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 498 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 499 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 500         EPHY_RXER_NUM           = 0x7c,
 501         OCPDR                   = 0xb0, /* OCP GPHY access */
 502 #define OCPDR_WRITE_CMD                 0x80000000
 503 #define OCPDR_READ_CMD                  0x00000000
 504 #define OCPDR_REG_MASK                  0x7f
 505 #define OCPDR_GPHY_REG_SHIFT            16
 506 #define OCPDR_DATA_MASK                 0xffff
 507         OCPAR                   = 0xb4,
 508 #define OCPAR_FLAG                      0x80000000
 509 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 510 #define OCPAR_GPHY_READ_CMD             0x0000f060
 511         GPHY_OCP                = 0xb8,
 512         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 513         MISC                    = 0xf0, /* 8168e only. */
 514 #define TXPLA_RST                       (1 << 29)
 515 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 516 #define PWM_EN                          (1 << 22)
 517 #define RXDV_GATED_EN                   (1 << 19)
 518 #define EARLY_TALLY_EN                  (1 << 16)
 519 };
 520
 521 enum rtl_register_content {
 522         /* InterruptStatusBits */
 523         SYSErr          = 0x8000,
 524         PCSTimeout      = 0x4000,
 525         SWInt           = 0x0100,
 526         TxDescUnavail   = 0x0080,
 527         RxFIFOOver      = 0x0040,
 528         LinkChg         = 0x0020,
 529         RxOverflow      = 0x0010,
 530         TxErr           = 0x0008,
 531         TxOK            = 0x0004,
 532         RxErr           = 0x0002,
 533         RxOK            = 0x0001,
 534
 535         /* RxStatusDesc */
 536         RxBOVF  = (1 << 24),
 537         RxFOVF  = (1 << 23),
 538         RxRWT   = (1 << 22),
 539         RxRES   = (1 << 21),
 540         RxRUNT  = (1 << 20),
 541         RxCRC   = (1 << 19),
 542
 543         /* ChipCmdBits */
 544         StopReq         = 0x80,
 545         CmdReset        = 0x10,
 546         CmdRxEnb        = 0x08,
 547         CmdTxEnb        = 0x04,
 548         RxBufEmpty      = 0x01,
 549
 550         /* TXPoll register p.5 */
 551         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 552         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 553         FSWInt          = 0x01,         /* Forced software interrupt */
 554
 555         /* Cfg9346Bits */
 556         Cfg9346_Lock    = 0x00,
 557         Cfg9346_Unlock  = 0xc0,
 558
 559         /* rx_mode_bits */
 560         AcceptErr       = 0x20,
 561         AcceptRunt      = 0x10,
 562         AcceptBroadcast = 0x08,
 563         AcceptMulticast = 0x04,
 564         AcceptMyPhys    = 0x02,
 565         AcceptAllPhys   = 0x01,
 566 #define RX_CONFIG_ACCEPT_MASK           0x3f
 567
 568         /* TxConfigBits */
 569         TxInterFrameGapShift = 24,
 570         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 571
 572         /* Config1 register p.24 */
 573         LEDS1           = (1 << 7),
 574         LEDS0           = (1 << 6),
 575         Speed_down      = (1 << 4),
 576         MEMMAP          = (1 << 3),
 577         IOMAP           = (1 << 2),
 578         VPD             = (1 << 1),
 579         PMEnable        = (1 << 0),     /* Power Management Enable */
 580
 581         /* Config2 register p. 25 */
 582         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 583         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 584         PCI_Clock_66MHz = 0x01,
 585         PCI_Clock_33MHz = 0x00,
 586
 587         /* Config3 register p.25 */
 588         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 589         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 590         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 591         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 592         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 593
 594         /* Config4 register */
 595         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 596
 597         /* Config5 register p.27 */
 598         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 599         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 600         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 601         Spi_en          = (1 << 3),
 602         LanWake         = (1 << 1),     /* LanWake enable/disable */
 603         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 604         ASPM_en         = (1 << 0),     /* ASPM enable */
 605
 606         /* TBICSR p.28 */
 607         TBIReset        = 0x80000000,
 608         TBILoopback     = 0x40000000,
 609         TBINwEnable     = 0x20000000,
 610         TBINwRestart    = 0x10000000,
 611         TBILinkOk       = 0x02000000,
 612         TBINwComplete   = 0x01000000,
 613
 614         /* CPlusCmd p.31 */
 615         EnableBist      = (1 << 15),    // 8168 8101
 616         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 617         Normal_mode     = (1 << 13),    // unused
 618         Force_half_dup  = (1 << 12),    // 8168 8101
 619         Force_rxflow_en = (1 << 11),    // 8168 8101
 620         Force_txflow_en = (1 << 10),    // 8168 8101
 621         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 622         ASF             = (1 << 8),     // 8168 8101
 623         PktCntrDisable  = (1 << 7),     // 8168 8101
 624         Mac_dbgo_sel    = 0x001c,       // 8168
 625         RxVlan          = (1 << 6),
 626         RxChkSum        = (1 << 5),
 627         PCIDAC          = (1 << 4),
 628         PCIMulRW        = (1 << 3),
 629         INTT_0          = 0x0000,       // 8168
 630         INTT_1          = 0x0001,       // 8168
 631         INTT_2          = 0x0002,       // 8168
 632         INTT_3          = 0x0003,       // 8168
 633
 634         /* rtl8169_PHYstatus */
 635         TBI_Enable      = 0x80,
 636         TxFlowCtrl      = 0x40,
 637         RxFlowCtrl      = 0x20,
 638         _1000bpsF       = 0x10,
 639         _100bps         = 0x08,
 640         _10bps          = 0x04,
 641         LinkStatus      = 0x02,
 642         FullDup         = 0x01,
 643
 644         /* _TBICSRBit */
 645         TBILinkOK       = 0x02000000,
 646
 647         /* ResetCounterCommand */
 648         CounterReset    = 0x1,
 649
 650         /* DumpCounterCommand */
 651         CounterDump     = 0x8,
 652
 653         /* magic enable v2 */
 654         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 655 };
 656
 657 enum rtl_desc_bit {
 658         /* First doubleword. */
 659         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 660         RingEnd         = (1 << 30), /* End of descriptor ring */
 661         FirstFrag       = (1 << 29), /* First segment of a packet */
 662         LastFrag        = (1 << 28), /* Final segment of a packet */
 663 };
 664
 665 /* Generic case. */
 666 enum rtl_tx_desc_bit {
 667         /* First doubleword. */
 668         TD_LSO          = (1 << 27),            /* Large Send Offload */
 669 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 670
 671         /* Second doubleword. */
 672         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 673 };
 674
 675 /* 8169, 8168b and 810x except 8102e. */
 676 enum rtl_tx_desc_bit_0 {
 677         /* First doubleword. */
 678 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 679         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 680         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 681         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 682 };
 683
 684 /* 8102e, 8168c and beyond. */
 685 enum rtl_tx_desc_bit_1 {
 686         /* First doubleword. */
 687         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 688         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 689 #define GTTCPHO_SHIFT                   18
 690 #define GTTCPHO_MAX                     0x7fU
 691
 692         /* Second doubleword. */
 693 #define TCPHO_SHIFT                     18
 694 #define TCPHO_MAX                       0x3ffU
 695 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 696         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 697         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 698         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 699         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 700 };
 701
 702 enum rtl_rx_desc_bit {
 703         /* Rx private */
 704         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 705         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 706
 707 #define RxProtoUDP      (PID1)
 708 #define RxProtoTCP      (PID0)
 709 #define RxProtoIP       (PID1 | PID0)
 710 #define RxProtoMask     RxProtoIP
 711
 712         IPFail          = (1 << 16), /* IP checksum failed */
 713         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 714         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 715         RxVlanTag       = (1 << 16), /* VLAN tag available */
 716 };
 717
 718 #define RsvdMask        0x3fffc000
 719
 720 struct TxDesc {
 721         __le32 opts1;
 722         __le32 opts2;
 723         __le64 addr;
 724 };
 725
 726 struct RxDesc {
 727         __le32 opts1;
 728         __le32 opts2;
 729         __le64 addr;
 730 };
 731
 732 struct ring_info {
 733         struct sk_buff  *skb;
 734         u32             len;
 735         u8              __pad[sizeof(void *) - sizeof(u32)];
 736 };
 737
 738 struct rtl8169_counters {
 739         __le64  tx_packets;
 740         __le64  rx_packets;
 741         __le64  tx_errors;
 742         __le32  rx_errors;
 743         __le16  rx_missed;
 744         __le16  align_errors;
 745         __le32  tx_one_collision;
 746         __le32  tx_multi_collision;
 747         __le64  rx_unicast;
 748         __le64  rx_broadcast;
 749         __le32  rx_multicast;
 750         __le16  tx_aborted;
 751         __le16  tx_underun;
 752 };
 753
 754 struct rtl8169_tc_offsets {
 755         bool    inited;
 756         __le64  tx_errors;
 757         __le32  tx_multi_collision;
 758         __le16  tx_aborted;
 759 };
 760
 761 enum rtl_flag {
 762         RTL_FLAG_TASK_ENABLED,
 763         RTL_FLAG_TASK_SLOW_PENDING,
 764         RTL_FLAG_TASK_RESET_PENDING,
 765         RTL_FLAG_TASK_PHY_PENDING,
 766         RTL_FLAG_MAX
 767 };
 768
 769 struct rtl8169_stats {
 770         u64                     packets;
 771         u64                     bytes;
 772         struct u64_stats_sync   syncp;
 773 };
 774
 775 struct rtl8169_private {
 776         void __iomem *mmio_addr;        /* memory map physical address */
 777         struct pci_dev *pci_dev;
 778         struct net_device *dev;
 779         struct napi_struct napi;
 780         u32 msg_enable;
 781         u16 txd_version;
 782         u16 mac_version;
 783         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 784         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 785         u32 dirty_tx;
 786         struct rtl8169_stats rx_stats;
 787         struct rtl8169_stats tx_stats;
 788         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 789         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 790         dma_addr_t TxPhyAddr;
 791         dma_addr_t RxPhyAddr;
 792         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 793         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 794         struct timer_list timer;
 795         u16 cp_cmd;
 796
 797         u16 event_slow;
 798         const struct rtl_coalesce_info *coalesce_info;
 799
 800         struct mdio_ops {
 801                 void (*write)(struct rtl8169_private *, int, int);
 802                 int (*read)(struct rtl8169_private *, int);
 803         } mdio_ops;
 804
 805         struct pll_power_ops {
 806                 void (*down)(struct rtl8169_private *);
 807                 void (*up)(struct rtl8169_private *);
 808         } pll_power_ops;
 809
 810         struct jumbo_ops {
 811                 void (*enable)(struct rtl8169_private *);
 812                 void (*disable)(struct rtl8169_private *);
 813         } jumbo_ops;
 814
 815         struct csi_ops {
 816                 void (*write)(struct rtl8169_private *, int, int);
 817                 u32 (*read)(struct rtl8169_private *, int);
 818         } csi_ops;
 819
 820         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 821         int (*get_link_ksettings)(struct net_device *,
 822                                   struct ethtool_link_ksettings *);
 823         void (*phy_reset_enable)(struct rtl8169_private *tp);
 824         void (*hw_start)(struct net_device *);
 825         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 826         unsigned int (*link_ok)(struct rtl8169_private *tp);
 827         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 828         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 829
 830         struct {
 831                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 832                 struct mutex mutex;
 833                 struct work_struct work;
 834         } wk;
 835
 836         unsigned features;
 837
 838         struct mii_if_info mii;
 839         dma_addr_t counters_phys_addr;
 840         struct rtl8169_counters *counters;
 841         struct rtl8169_tc_offsets tc_offset;
 842         u32 saved_wolopts;
 843         u32 opts1_mask;
 844
 845         struct rtl_fw {
 846                 const struct firmware *fw;
 847
 848 #define RTL_VER_SIZE            32
 849
 850                 char version[RTL_VER_SIZE];
 851
 852                 struct rtl_fw_phy_action {
 853                         __le32 *code;
 854                         size_t size;
 855                 } phy_action;
 856         } *rtl_fw;
 857 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 858
 859         u32 ocp_base;
 860 };
 861
 862 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 863 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 864 module_param(use_dac, int, 0);
 865 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 866 module_param_named(debug, debug.msg_enable, int, 0);
 867 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 868 MODULE_LICENSE("GPL");
 869 MODULE_VERSION(RTL8169_VERSION);
 870 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 871 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 872 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 873 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 874 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 875 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 876 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 877 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 878 MODULE_FIRMWARE(FIRMWARE_8402_1);
 879 MODULE_FIRMWARE(FIRMWARE_8411_1);
 880 MODULE_FIRMWARE(FIRMWARE_8411_2);
 881 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 882 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 883 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 884 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 885 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 886 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 887 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 888 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 889
 890 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 891 {
 892         return &tp->pci_dev->dev;
 893 }
 894
 895 static void rtl_lock_work(struct rtl8169_private *tp)
 896 {
 897         mutex_lock(&tp->wk.mutex);
 898 }
 899
 900 static void rtl_unlock_work(struct rtl8169_private *tp)
 901 {
 902         mutex_unlock(&tp->wk.mutex);
 903 }
 904
 905 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 906 {
 907         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 908                                            PCI_EXP_DEVCTL_READRQ, force);
 909 }
 910
 911 struct rtl_cond {
 912         bool (*check)(struct rtl8169_private *);
 913         const char *msg;
 914 };
 915
 916 static void rtl_udelay(unsigned int d)
 917 {
 918         udelay(d);
 919 }
 920
 921 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 922                           void (*delay)(unsigned int), unsigned int d, int n,
 923                           bool high)
 924 {
 925         int i;
 926
 927         for (i = 0; i < n; i++) {
 928                 delay(d);
 929                 if (c->check(tp) == high)
 930                         return true;
 931         }
 932         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 933                   c->msg, !high, n, d);
 934         return false;
 935 }
 936
 937 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 938                                       const struct rtl_cond *c,
 939                                       unsigned int d, int n)
 940 {
 941         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 942 }
 943
 944 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 945                                      const struct rtl_cond *c,
 946                                      unsigned int d, int n)
 947 {
 948         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 949 }
 950
 951 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 952                                       const struct rtl_cond *c,
 953                                       unsigned int d, int n)
 954 {
 955         return rtl_loop_wait(tp, c, msleep, d, n, true);
 956 }
 957
 958 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 959                                      const struct rtl_cond *c,
 960                                      unsigned int d, int n)
 961 {
 962         return rtl_loop_wait(tp, c, msleep, d, n, false);
 963 }
 964
 965 #define DECLARE_RTL_COND(name)                          \
 966 static bool name ## _check(struct rtl8169_private *);   \
 967                                                         \
 968 static const struct rtl_cond name = {                   \
 969         .check  = name ## _check,                       \
 970         .msg    = #name                                 \
 971 };                                                      \
 972                                                         \
 973 static bool name ## _check(struct rtl8169_private *tp)
 974
 975 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 976 {
 977         if (reg & 0xffff0001) {
 978                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 979                 return true;
 980         }
 981         return false;
 982 }
 983
 984 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 985 {
 986         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 987 }
 988
 989 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 990 {
 991         if (rtl_ocp_reg_failure(tp, reg))
 992                 return;
 993
 994         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 995
 996         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 997 }
 998
 999 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1000 {
1001         if (rtl_ocp_reg_failure(tp, reg))
1002                 return 0;
1003
1004         RTL_W32(tp, GPHY_OCP, reg << 15);
1005
1006         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1007                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
1008 }
1009
1010 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1011 {
1012         if (rtl_ocp_reg_failure(tp, reg))
1013                 return;
1014
1015         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1016 }
1017
1018 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019 {
1020         if (rtl_ocp_reg_failure(tp, reg))
1021                 return 0;
1022
1023         RTL_W32(tp, OCPDR, reg << 15);
1024
1025         return RTL_R32(tp, OCPDR);
1026 }
1027
1028 #define OCP_STD_PHY_BASE        0xa400
1029
1030 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1031 {
1032         if (reg == 0x1f) {
1033                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1034                 return;
1035         }
1036
1037         if (tp->ocp_base != OCP_STD_PHY_BASE)
1038                 reg -= 0x10;
1039
1040         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1041 }
1042
1043 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1044 {
1045         if (tp->ocp_base != OCP_STD_PHY_BASE)
1046                 reg -= 0x10;
1047
1048         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1049 }
1050
1051 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1052 {
1053         if (reg == 0x1f) {
1054                 tp->ocp_base = value << 4;
1055                 return;
1056         }
1057
1058         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1059 }
1060
1061 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1062 {
1063         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1064 }
1065
1066 DECLARE_RTL_COND(rtl_phyar_cond)
1067 {
1068         return RTL_R32(tp, PHYAR) & 0x80000000;
1069 }
1070
1071 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1072 {
1073         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1074
1075         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1076         /*
1077          * According to hardware specs a 20us delay is required after write
1078          * complete indication, but before sending next command.
1079          */
1080         udelay(20);
1081 }
1082
1083 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1084 {
1085         int value;
1086
1087         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1088
1089         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1090                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1091
1092         /*
1093          * According to hardware specs a 20us delay is required after read
1094          * complete indication, but before sending next command.
1095          */
1096         udelay(20);
1097
1098         return value;
1099 }
1100
1101 DECLARE_RTL_COND(rtl_ocpar_cond)
1102 {
1103         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1104 }
1105
1106 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1107 {
1108         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1109         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1110         RTL_W32(tp, EPHY_RXER_NUM, 0);
1111
1112         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1113 }
1114
1115 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1116 {
1117         r8168dp_1_mdio_access(tp, reg,
1118                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1119 }
1120
1121 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1122 {
1123         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1124
1125         mdelay(1);
1126         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1127         RTL_W32(tp, EPHY_RXER_NUM, 0);
1128
1129         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1130                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1131 }
1132
1133 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1134
1135 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1136 {
1137         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1138 }
1139
1140 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1141 {
1142         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1143 }
1144
1145 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1146 {
1147         r8168dp_2_mdio_start(tp);
1148
1149         r8169_mdio_write(tp, reg, value);
1150
1151         r8168dp_2_mdio_stop(tp);
1152 }
1153
1154 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1155 {
1156         int value;
1157
1158         r8168dp_2_mdio_start(tp);
1159
1160         value = r8169_mdio_read(tp, reg);
1161
1162         r8168dp_2_mdio_stop(tp);
1163
1164         return value;
1165 }
1166
1167 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1168 {
1169         tp->mdio_ops.write(tp, location, val);
1170 }
1171
1172 static int rtl_readphy(struct rtl8169_private *tp, int location)
1173 {
1174         return tp->mdio_ops.read(tp, location);
1175 }
1176
1177 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1178 {
1179         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1180 }
1181
1182 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1183 {
1184         int val;
1185
1186         val = rtl_readphy(tp, reg_addr);
1187         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1188 }
1189
1190 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1191                            int val)
1192 {
1193         struct rtl8169_private *tp = netdev_priv(dev);
1194
1195         rtl_writephy(tp, location, val);
1196 }
1197
1198 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1199 {
1200         struct rtl8169_private *tp = netdev_priv(dev);
1201
1202         return rtl_readphy(tp, location);
1203 }
1204
1205 DECLARE_RTL_COND(rtl_ephyar_cond)
1206 {
1207         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1208 }
1209
1210 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1211 {
1212         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1213                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1214
1215         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1216
1217         udelay(10);
1218 }
1219
1220 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1221 {
1222         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1223
1224         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1225                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1226 }
1227
1228 DECLARE_RTL_COND(rtl_eriar_cond)
1229 {
1230         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1231 }
1232
1233 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1234                           u32 val, int type)
1235 {
1236         BUG_ON((addr & 3) || (mask == 0));
1237         RTL_W32(tp, ERIDR, val);
1238         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1239
1240         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1241 }
1242
1243 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1244 {
1245         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1246
1247         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1248                 RTL_R32(tp, ERIDR) : ~0;
1249 }
1250
1251 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1252                          u32 m, int type)
1253 {
1254         u32 val;
1255
1256         val = rtl_eri_read(tp, addr, type);
1257         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1258 }
1259
1260 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1261 {
1262         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1263         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1264                 RTL_R32(tp, OCPDR) : ~0;
1265 }
1266
1267 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1268 {
1269         return rtl_eri_read(tp, reg, ERIAR_OOB);
1270 }
1271
1272 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1273 {
1274         switch (tp->mac_version) {
1275         case RTL_GIGA_MAC_VER_27:
1276         case RTL_GIGA_MAC_VER_28:
1277         case RTL_GIGA_MAC_VER_31:
1278                 return r8168dp_ocp_read(tp, mask, reg);
1279         case RTL_GIGA_MAC_VER_49:
1280         case RTL_GIGA_MAC_VER_50:
1281         case RTL_GIGA_MAC_VER_51:
1282                 return r8168ep_ocp_read(tp, mask, reg);
1283         default:
1284                 BUG();
1285                 return ~0;
1286         }
1287 }
1288
1289 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1290                               u32 data)
1291 {
1292         RTL_W32(tp, OCPDR, data);
1293         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1294         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1295 }
1296
1297 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1298                               u32 data)
1299 {
1300         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1301                       data, ERIAR_OOB);
1302 }
1303
1304 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1305 {
1306         switch (tp->mac_version) {
1307         case RTL_GIGA_MAC_VER_27:
1308         case RTL_GIGA_MAC_VER_28:
1309         case RTL_GIGA_MAC_VER_31:
1310                 r8168dp_ocp_write(tp, mask, reg, data);
1311                 break;
1312         case RTL_GIGA_MAC_VER_49:
1313         case RTL_GIGA_MAC_VER_50:
1314         case RTL_GIGA_MAC_VER_51:
1315                 r8168ep_ocp_write(tp, mask, reg, data);
1316                 break;
1317         default:
1318                 BUG();
1319                 break;
1320         }
1321 }
1322
1323 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1324 {
1325         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1326
1327         ocp_write(tp, 0x1, 0x30, 0x00000001);
1328 }
1329
1330 #define OOB_CMD_RESET           0x00
1331 #define OOB_CMD_DRIVER_START    0x05
1332 #define OOB_CMD_DRIVER_STOP     0x06
1333
1334 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1335 {
1336         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1337 }
1338
1339 DECLARE_RTL_COND(rtl_ocp_read_cond)
1340 {
1341         u16 reg;
1342
1343         reg = rtl8168_get_ocp_reg(tp);
1344
1345         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1346 }
1347
1348 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1349 {
1350         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1351 }
1352
1353 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1354 {
1355         return RTL_R8(tp, IBISR0) & 0x20;
1356 }
1357
1358 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1359 {
1360         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1361         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1362         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1363         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1364 }
1365
1366 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1367 {
1368         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1369         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1370 }
1371
1372 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1373 {
1374         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1375         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1376         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1377 }
1378
1379 static void rtl8168_driver_start(struct rtl8169_private *tp)
1380 {
1381         switch (tp->mac_version) {
1382         case RTL_GIGA_MAC_VER_27:
1383         case RTL_GIGA_MAC_VER_28:
1384         case RTL_GIGA_MAC_VER_31:
1385                 rtl8168dp_driver_start(tp);
1386                 break;
1387         case RTL_GIGA_MAC_VER_49:
1388         case RTL_GIGA_MAC_VER_50:
1389         case RTL_GIGA_MAC_VER_51:
1390                 rtl8168ep_driver_start(tp);
1391                 break;
1392         default:
1393                 BUG();
1394                 break;
1395         }
1396 }
1397
1398 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1399 {
1400         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1401         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1402 }
1403
1404 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1405 {
1406         rtl8168ep_stop_cmac(tp);
1407         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1408         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1409         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1410 }
1411
1412 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1413 {
1414         switch (tp->mac_version) {
1415         case RTL_GIGA_MAC_VER_27:
1416         case RTL_GIGA_MAC_VER_28:
1417         case RTL_GIGA_MAC_VER_31:
1418                 rtl8168dp_driver_stop(tp);
1419                 break;
1420         case RTL_GIGA_MAC_VER_49:
1421         case RTL_GIGA_MAC_VER_50:
1422         case RTL_GIGA_MAC_VER_51:
1423                 rtl8168ep_driver_stop(tp);
1424                 break;
1425         default:
1426                 BUG();
1427                 break;
1428         }
1429 }
1430
1431 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1432 {
1433         u16 reg = rtl8168_get_ocp_reg(tp);
1434
1435         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1436 }
1437
1438 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1439 {
1440         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1441 }
1442
1443 static bool r8168_check_dash(struct rtl8169_private *tp)
1444 {
1445         switch (tp->mac_version) {
1446         case RTL_GIGA_MAC_VER_27:
1447         case RTL_GIGA_MAC_VER_28:
1448         case RTL_GIGA_MAC_VER_31:
1449                 return r8168dp_check_dash(tp);
1450         case RTL_GIGA_MAC_VER_49:
1451         case RTL_GIGA_MAC_VER_50:
1452         case RTL_GIGA_MAC_VER_51:
1453                 return r8168ep_check_dash(tp);
1454         default:
1455                 return false;
1456         }
1457 }
1458
1459 struct exgmac_reg {
1460         u16 addr;
1461         u16 mask;
1462         u32 val;
1463 };
1464
1465 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1466                                    const struct exgmac_reg *r, int len)
1467 {
1468         while (len-- > 0) {
1469                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1470                 r++;
1471         }
1472 }
1473
1474 DECLARE_RTL_COND(rtl_efusear_cond)
1475 {
1476         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1477 }
1478
1479 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1480 {
1481         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1482
1483         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1484                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1485 }
1486
1487 static u16 rtl_get_events(struct rtl8169_private *tp)
1488 {
1489         return RTL_R16(tp, IntrStatus);
1490 }
1491
1492 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1493 {
1494         RTL_W16(tp, IntrStatus, bits);
1495         mmiowb();
1496 }
1497
1498 static void rtl_irq_disable(struct rtl8169_private *tp)
1499 {
1500         RTL_W16(tp, IntrMask, 0);
1501         mmiowb();
1502 }
1503
1504 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1505 {
1506         RTL_W16(tp, IntrMask, bits);
1507 }
1508
1509 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1510 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1511 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1512
1513 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1514 {
1515         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1516 }
1517
1518 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1519 {
1520         rtl_irq_disable(tp);
1521         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1522         RTL_R8(tp, ChipCmd);
1523 }
1524
1525 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1526 {
1527         return RTL_R32(tp, TBICSR) & TBIReset;
1528 }
1529
1530 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1531 {
1532         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1533 }
1534
1535 static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp)
1536 {
1537         return RTL_R32(tp, TBICSR) & TBILinkOk;
1538 }
1539
1540 static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
1541 {
1542         return RTL_R8(tp, PHYstatus) & LinkStatus;
1543 }
1544
1545 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1546 {
1547         RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset);
1548 }
1549
1550 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1551 {
1552         unsigned int val;
1553
1554         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1555         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1556 }
1557
1558 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1559 {
1560         struct net_device *dev = tp->dev;
1561
1562         if (!netif_running(dev))
1563                 return;
1564
1565         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1566             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1567                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1568                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1569                                       ERIAR_EXGMAC);
1570                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1571                                       ERIAR_EXGMAC);
1572                 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1573                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1574                                       ERIAR_EXGMAC);
1575                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1576                                       ERIAR_EXGMAC);
1577                 } else {
1578                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1579                                       ERIAR_EXGMAC);
1580                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1581                                       ERIAR_EXGMAC);
1582                 }
1583                 /* Reset packet filter */
1584                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1585                              ERIAR_EXGMAC);
1586                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1587                              ERIAR_EXGMAC);
1588         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1589                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1590                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1591                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1592                                       ERIAR_EXGMAC);
1593                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1594                                       ERIAR_EXGMAC);
1595                 } else {
1596                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1597                                       ERIAR_EXGMAC);
1598                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1599                                       ERIAR_EXGMAC);
1600                 }
1601         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1602                 if (RTL_R8(tp, PHYstatus) & _10bps) {
1603                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1604                                       ERIAR_EXGMAC);
1605                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1606                                       ERIAR_EXGMAC);
1607                 } else {
1608                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1609                                       ERIAR_EXGMAC);
1610                 }
1611         }
1612 }
1613
1614 static void rtl8169_check_link_status(struct net_device *dev,
1615                                       struct rtl8169_private *tp)
1616 {
1617         struct device *d = tp_to_dev(tp);
1618
1619         if (tp->link_ok(tp)) {
1620                 rtl_link_chg_patch(tp);
1621                 /* This is to cancel a scheduled suspend if there's one. */
1622                 pm_request_resume(d);
1623                 netif_carrier_on(dev);
1624                 if (net_ratelimit())
1625                         netif_info(tp, ifup, dev, "link up\n");
1626         } else {
1627                 netif_carrier_off(dev);
1628                 netif_info(tp, ifdown, dev, "link down\n");
1629                 pm_runtime_idle(d);
1630         }
1631 }
1632
1633 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1634
1635 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1636 {
1637         u8 options;
1638         u32 wolopts = 0;
1639
1640         options = RTL_R8(tp, Config1);
1641         if (!(options & PMEnable))
1642                 return 0;
1643
1644         options = RTL_R8(tp, Config3);
1645         if (options & LinkUp)
1646                 wolopts |= WAKE_PHY;
1647         switch (tp->mac_version) {
1648         case RTL_GIGA_MAC_VER_34:
1649         case RTL_GIGA_MAC_VER_35:
1650         case RTL_GIGA_MAC_VER_36:
1651         case RTL_GIGA_MAC_VER_37:
1652         case RTL_GIGA_MAC_VER_38:
1653         case RTL_GIGA_MAC_VER_40:
1654         case RTL_GIGA_MAC_VER_41:
1655         case RTL_GIGA_MAC_VER_42:
1656         case RTL_GIGA_MAC_VER_43:
1657         case RTL_GIGA_MAC_VER_44:
1658         case RTL_GIGA_MAC_VER_45:
1659         case RTL_GIGA_MAC_VER_46:
1660         case RTL_GIGA_MAC_VER_47:
1661         case RTL_GIGA_MAC_VER_48:
1662         case RTL_GIGA_MAC_VER_49:
1663         case RTL_GIGA_MAC_VER_50:
1664         case RTL_GIGA_MAC_VER_51:
1665                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1666                         wolopts |= WAKE_MAGIC;
1667                 break;
1668         default:
1669                 if (options & MagicPacket)
1670                         wolopts |= WAKE_MAGIC;
1671                 break;
1672         }
1673
1674         options = RTL_R8(tp, Config5);
1675         if (options & UWF)
1676                 wolopts |= WAKE_UCAST;
1677         if (options & BWF)
1678                 wolopts |= WAKE_BCAST;
1679         if (options & MWF)
1680                 wolopts |= WAKE_MCAST;
1681
1682         return wolopts;
1683 }
1684
1685 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1686 {
1687         struct rtl8169_private *tp = netdev_priv(dev);
1688         struct device *d = tp_to_dev(tp);
1689
1690         pm_runtime_get_noresume(d);
1691
1692         rtl_lock_work(tp);
1693
1694         wol->supported = WAKE_ANY;
1695         if (pm_runtime_active(d))
1696                 wol->wolopts = __rtl8169_get_wol(tp);
1697         else
1698                 wol->wolopts = tp->saved_wolopts;
1699
1700         rtl_unlock_work(tp);
1701
1702         pm_runtime_put_noidle(d);
1703 }
1704
1705 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1706 {
1707         unsigned int i, tmp;
1708         static const struct {
1709                 u32 opt;
1710                 u16 reg;
1711                 u8  mask;
1712         } cfg[] = {
1713                 { WAKE_PHY,   Config3, LinkUp },
1714                 { WAKE_UCAST, Config5, UWF },
1715                 { WAKE_BCAST, Config5, BWF },
1716                 { WAKE_MCAST, Config5, MWF },
1717                 { WAKE_ANY,   Config5, LanWake },
1718                 { WAKE_MAGIC, Config3, MagicPacket }
1719         };
1720         u8 options;
1721
1722         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1723
1724         switch (tp->mac_version) {
1725         case RTL_GIGA_MAC_VER_34:
1726         case RTL_GIGA_MAC_VER_35:
1727         case RTL_GIGA_MAC_VER_36:
1728         case RTL_GIGA_MAC_VER_37:
1729         case RTL_GIGA_MAC_VER_38:
1730         case RTL_GIGA_MAC_VER_40:
1731         case RTL_GIGA_MAC_VER_41:
1732         case RTL_GIGA_MAC_VER_42:
1733         case RTL_GIGA_MAC_VER_43:
1734         case RTL_GIGA_MAC_VER_44:
1735         case RTL_GIGA_MAC_VER_45:
1736         case RTL_GIGA_MAC_VER_46:
1737         case RTL_GIGA_MAC_VER_47:
1738         case RTL_GIGA_MAC_VER_48:
1739         case RTL_GIGA_MAC_VER_49:
1740         case RTL_GIGA_MAC_VER_50:
1741         case RTL_GIGA_MAC_VER_51:
1742                 tmp = ARRAY_SIZE(cfg) - 1;
1743                 if (wolopts & WAKE_MAGIC)
1744                         rtl_w0w1_eri(tp,
1745                                      0x0dc,
1746                                      ERIAR_MASK_0100,
1747                                      MagicPacket_v2,
1748                                      0x0000,
1749                                      ERIAR_EXGMAC);
1750                 else
1751                         rtl_w0w1_eri(tp,
1752                                      0x0dc,
1753                                      ERIAR_MASK_0100,
1754                                      0x0000,
1755                                      MagicPacket_v2,
1756                                      ERIAR_EXGMAC);
1757                 break;
1758         default:
1759                 tmp = ARRAY_SIZE(cfg);
1760                 break;
1761         }
1762
1763         for (i = 0; i < tmp; i++) {
1764                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1765                 if (wolopts & cfg[i].opt)
1766                         options |= cfg[i].mask;
1767                 RTL_W8(tp, cfg[i].reg, options);
1768         }
1769
1770         switch (tp->mac_version) {
1771         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1772                 options = RTL_R8(tp, Config1) & ~PMEnable;
1773                 if (wolopts)
1774                         options |= PMEnable;
1775                 RTL_W8(tp, Config1, options);
1776                 break;
1777         default:
1778                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1779                 if (wolopts)
1780                         options |= PME_SIGNAL;
1781                 RTL_W8(tp, Config2, options);
1782                 break;
1783         }
1784
1785         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1786 }
1787
1788 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1789 {
1790         struct rtl8169_private *tp = netdev_priv(dev);
1791         struct device *d = tp_to_dev(tp);
1792
1793         pm_runtime_get_noresume(d);
1794
1795         rtl_lock_work(tp);
1796
1797         if (pm_runtime_active(d))
1798                 __rtl8169_set_wol(tp, wol->wolopts);
1799         else
1800                 tp->saved_wolopts = wol->wolopts;
1801
1802         rtl_unlock_work(tp);
1803
1804         device_set_wakeup_enable(d, wol->wolopts);
1805
1806         pm_runtime_put_noidle(d);
1807
1808         return 0;
1809 }
1810
1811 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1812 {
1813         return rtl_chip_infos[tp->mac_version].fw_name;
1814 }
1815
1816 static void rtl8169_get_drvinfo(struct net_device *dev,
1817                                 struct ethtool_drvinfo *info)
1818 {
1819         struct rtl8169_private *tp = netdev_priv(dev);
1820         struct rtl_fw *rtl_fw = tp->rtl_fw;
1821
1822         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1823         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1824         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1825         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1826         if (!IS_ERR_OR_NULL(rtl_fw))
1827                 strlcpy(info->fw_version, rtl_fw->version,
1828                         sizeof(info->fw_version));
1829 }
1830
1831 static int rtl8169_get_regs_len(struct net_device *dev)
1832 {
1833         return R8169_REGS_SIZE;
1834 }
1835
1836 static int rtl8169_set_speed_tbi(struct net_device *dev,
1837                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1838 {
1839         struct rtl8169_private *tp = netdev_priv(dev);
1840         int ret = 0;
1841         u32 reg;
1842
1843         reg = RTL_R32(tp, TBICSR);
1844         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1845             (duplex == DUPLEX_FULL)) {
1846                 RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1847         } else if (autoneg == AUTONEG_ENABLE)
1848                 RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart);
1849         else {
1850                 netif_warn(tp, link, dev,
1851                            "incorrect speed setting refused in TBI mode\n");
1852                 ret = -EOPNOTSUPP;
1853         }
1854
1855         return ret;
1856 }
1857
1858 static int rtl8169_set_speed_xmii(struct net_device *dev,
1859                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1860 {
1861         struct rtl8169_private *tp = netdev_priv(dev);
1862         int giga_ctrl, bmcr;
1863         int rc = -EINVAL;
1864
1865         rtl_writephy(tp, 0x1f, 0x0000);
1866
1867         if (autoneg == AUTONEG_ENABLE) {
1868                 int auto_nego;
1869
1870                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1871                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1872                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1873
1874                 if (adv & ADVERTISED_10baseT_Half)
1875                         auto_nego |= ADVERTISE_10HALF;
1876                 if (adv & ADVERTISED_10baseT_Full)
1877                         auto_nego |= ADVERTISE_10FULL;
1878                 if (adv & ADVERTISED_100baseT_Half)
1879                         auto_nego |= ADVERTISE_100HALF;
1880                 if (adv & ADVERTISED_100baseT_Full)
1881                         auto_nego |= ADVERTISE_100FULL;
1882
1883                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1884
1885                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1886                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1887
1888                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1889                 if (tp->mii.supports_gmii) {
1890                         if (adv & ADVERTISED_1000baseT_Half)
1891                                 giga_ctrl |= ADVERTISE_1000HALF;
1892                         if (adv & ADVERTISED_1000baseT_Full)
1893                                 giga_ctrl |= ADVERTISE_1000FULL;
1894                 } else if (adv & (ADVERTISED_1000baseT_Half |
1895                                   ADVERTISED_1000baseT_Full)) {
1896                         netif_info(tp, link, dev,
1897                                    "PHY does not support 1000Mbps\n");
1898                         goto out;
1899                 }
1900
1901                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1902
1903                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1904                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1905         } else {
1906                 if (speed == SPEED_10)
1907                         bmcr = 0;
1908                 else if (speed == SPEED_100)
1909                         bmcr = BMCR_SPEED100;
1910                 else
1911                         goto out;
1912
1913                 if (duplex == DUPLEX_FULL)
1914                         bmcr |= BMCR_FULLDPLX;
1915         }
1916
1917         rtl_writephy(tp, MII_BMCR, bmcr);
1918
1919         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1920             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1921                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1922                         rtl_writephy(tp, 0x17, 0x2138);
1923                         rtl_writephy(tp, 0x0e, 0x0260);
1924                 } else {
1925                         rtl_writephy(tp, 0x17, 0x2108);
1926                         rtl_writephy(tp, 0x0e, 0x0000);
1927                 }
1928         }
1929
1930         rc = 0;
1931 out:
1932         return rc;
1933 }
1934
1935 static int rtl8169_set_speed(struct net_device *dev,
1936                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1937 {
1938         struct rtl8169_private *tp = netdev_priv(dev);
1939         int ret;
1940
1941         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1942         if (ret < 0)
1943                 goto out;
1944
1945         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1946             (advertising & ADVERTISED_1000baseT_Full) &&
1947             !pci_is_pcie(tp->pci_dev)) {
1948                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1949         }
1950 out:
1951         return ret;
1952 }
1953
1954 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1955         netdev_features_t features)
1956 {
1957         struct rtl8169_private *tp = netdev_priv(dev);
1958
1959         if (dev->mtu > TD_MSS_MAX)
1960                 features &= ~NETIF_F_ALL_TSO;
1961
1962         if (dev->mtu > JUMBO_1K &&
1963             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1964                 features &= ~NETIF_F_IP_CSUM;
1965
1966         return features;
1967 }
1968
1969 static void __rtl8169_set_features(struct net_device *dev,
1970                                    netdev_features_t features)
1971 {
1972         struct rtl8169_private *tp = netdev_priv(dev);
1973         u32 rx_config;
1974
1975         rx_config = RTL_R32(tp, RxConfig);
1976         if (features & NETIF_F_RXALL)
1977                 rx_config |= (AcceptErr | AcceptRunt);
1978         else
1979                 rx_config &= ~(AcceptErr | AcceptRunt);
1980
1981         RTL_W32(tp, RxConfig, rx_config);
1982
1983         if (features & NETIF_F_RXCSUM)
1984                 tp->cp_cmd |= RxChkSum;
1985         else
1986                 tp->cp_cmd &= ~RxChkSum;
1987
1988         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1989                 tp->cp_cmd |= RxVlan;
1990         else
1991                 tp->cp_cmd &= ~RxVlan;
1992
1993         tp->cp_cmd |= RTL_R16(tp, CPlusCmd) & ~(RxVlan | RxChkSum);
1994
1995         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1996         RTL_R16(tp, CPlusCmd);
1997 }
1998
1999 static int rtl8169_set_features(struct net_device *dev,
2000                                 netdev_features_t features)
2001 {
2002         struct rtl8169_private *tp = netdev_priv(dev);
2003
2004         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2005
2006         rtl_lock_work(tp);
2007         if (features ^ dev->features)
2008                 __rtl8169_set_features(dev, features);
2009         rtl_unlock_work(tp);
2010
2011         return 0;
2012 }
2013
2014
2015 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2016 {
2017         return (skb_vlan_tag_present(skb)) ?
2018                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2019 }
2020
2021 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2022 {
2023         u32 opts2 = le32_to_cpu(desc->opts2);
2024
2025         if (opts2 & RxVlanTag)
2026                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2027 }
2028
2029 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2030                                           struct ethtool_link_ksettings *cmd)
2031 {
2032         struct rtl8169_private *tp = netdev_priv(dev);
2033         u32 status;
2034         u32 supported, advertising;
2035
2036         supported =
2037                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2038         cmd->base.port = PORT_FIBRE;
2039
2040         status = RTL_R32(tp, TBICSR);
2041         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2042         cmd->base.autoneg = !!(status & TBINwEnable);
2043
2044         cmd->base.speed = SPEED_1000;
2045         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2046
2047         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2048                                                 supported);
2049         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2050                                                 advertising);
2051
2052         return 0;
2053 }
2054
2055 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2056                                            struct ethtool_link_ksettings *cmd)
2057 {
2058         struct rtl8169_private *tp = netdev_priv(dev);
2059
2060         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2061
2062         return 0;
2063 }
2064
2065 static int rtl8169_get_link_ksettings(struct net_device *dev,
2066                                       struct ethtool_link_ksettings *cmd)
2067 {
2068         struct rtl8169_private *tp = netdev_priv(dev);
2069         int rc;
2070
2071         rtl_lock_work(tp);
2072         rc = tp->get_link_ksettings(dev, cmd);
2073         rtl_unlock_work(tp);
2074
2075         return rc;
2076 }
2077
2078 static int rtl8169_set_link_ksettings(struct net_device *dev,
2079                                       const struct ethtool_link_ksettings *cmd)
2080 {
2081         struct rtl8169_private *tp = netdev_priv(dev);
2082         int rc;
2083         u32 advertising;
2084
2085         if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2086             cmd->link_modes.advertising))
2087                 return -EINVAL;
2088
2089         del_timer_sync(&tp->timer);
2090
2091         rtl_lock_work(tp);
2092         rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2093                                cmd->base.duplex, advertising);
2094         rtl_unlock_work(tp);
2095
2096         return rc;
2097 }
2098
2099 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2100                              void *p)
2101 {
2102         struct rtl8169_private *tp = netdev_priv(dev);
2103         u32 __iomem *data = tp->mmio_addr;
2104         u32 *dw = p;
2105         int i;
2106
2107         rtl_lock_work(tp);
2108         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2109                 memcpy_fromio(dw++, data++, 4);
2110         rtl_unlock_work(tp);
2111 }
2112
2113 static u32 rtl8169_get_msglevel(struct net_device *dev)
2114 {
2115         struct rtl8169_private *tp = netdev_priv(dev);
2116
2117         return tp->msg_enable;
2118 }
2119
2120 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2121 {
2122         struct rtl8169_private *tp = netdev_priv(dev);
2123
2124         tp->msg_enable = value;
2125 }
2126
2127 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2128         "tx_packets",
2129         "rx_packets",
2130         "tx_errors",
2131         "rx_errors",
2132         "rx_missed",
2133         "align_errors",
2134         "tx_single_collisions",
2135         "tx_multi_collisions",
2136         "unicast",
2137         "broadcast",
2138         "multicast",
2139         "tx_aborted",
2140         "tx_underrun",
2141 };
2142
2143 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2144 {
2145         switch (sset) {
2146         case ETH_SS_STATS:
2147                 return ARRAY_SIZE(rtl8169_gstrings);
2148         default:
2149                 return -EOPNOTSUPP;
2150         }
2151 }
2152
2153 DECLARE_RTL_COND(rtl_counters_cond)
2154 {
2155         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
2156 }
2157
2158 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2159 {
2160         struct rtl8169_private *tp = netdev_priv(dev);
2161         dma_addr_t paddr = tp->counters_phys_addr;
2162         u32 cmd;
2163
2164         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2165         RTL_R32(tp, CounterAddrHigh);
2166         cmd = (u64)paddr & DMA_BIT_MASK(32);
2167         RTL_W32(tp, CounterAddrLow, cmd);
2168         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
2169
2170         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2171 }
2172
2173 static bool rtl8169_reset_counters(struct net_device *dev)
2174 {
2175         struct rtl8169_private *tp = netdev_priv(dev);
2176
2177         /*
2178          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2179          * tally counters.
2180          */
2181         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2182                 return true;
2183
2184         return rtl8169_do_counters(dev, CounterReset);
2185 }
2186
2187 static bool rtl8169_update_counters(struct net_device *dev)
2188 {
2189         struct rtl8169_private *tp = netdev_priv(dev);
2190
2191         /*
2192          * Some chips are unable to dump tally counters when the receiver
2193          * is disabled.
2194          */
2195         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
2196                 return true;
2197
2198         return rtl8169_do_counters(dev, CounterDump);
2199 }
2200
2201 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2202 {
2203         struct rtl8169_private *tp = netdev_priv(dev);
2204         struct rtl8169_counters *counters = tp->counters;
2205         bool ret = false;
2206
2207         /*
2208          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2209          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2210          * reset by a power cycle, while the counter values collected by the
2211          * driver are reset at every driver unload/load cycle.
2212          *
2213          * To make sure the HW values returned by @get_stats64 match the SW
2214          * values, we collect the initial values at first open(*) and use them
2215          * as offsets to normalize the values returned by @get_stats64.
2216          *
2217          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2218          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2219          * set at open time by rtl_hw_start.
2220          */
2221
2222         if (tp->tc_offset.inited)
2223                 return true;
2224
2225         /* If both, reset and update fail, propagate to caller. */
2226         if (rtl8169_reset_counters(dev))
2227                 ret = true;
2228
2229         if (rtl8169_update_counters(dev))
2230                 ret = true;
2231
2232         tp->tc_offset.tx_errors = counters->tx_errors;
2233         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2234         tp->tc_offset.tx_aborted = counters->tx_aborted;
2235         tp->tc_offset.inited = true;
2236
2237         return ret;
2238 }
2239
2240 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2241                                       struct ethtool_stats *stats, u64 *data)
2242 {
2243         struct rtl8169_private *tp = netdev_priv(dev);
2244         struct device *d = tp_to_dev(tp);
2245         struct rtl8169_counters *counters = tp->counters;
2246
2247         ASSERT_RTNL();
2248
2249         pm_runtime_get_noresume(d);
2250
2251         if (pm_runtime_active(d))
2252                 rtl8169_update_counters(dev);
2253
2254         pm_runtime_put_noidle(d);
2255
2256         data[0] = le64_to_cpu(counters->tx_packets);
2257         data[1] = le64_to_cpu(counters->rx_packets);
2258         data[2] = le64_to_cpu(counters->tx_errors);
2259         data[3] = le32_to_cpu(counters->rx_errors);
2260         data[4] = le16_to_cpu(counters->rx_missed);
2261         data[5] = le16_to_cpu(counters->align_errors);
2262         data[6] = le32_to_cpu(counters->tx_one_collision);
2263         data[7] = le32_to_cpu(counters->tx_multi_collision);
2264         data[8] = le64_to_cpu(counters->rx_unicast);
2265         data[9] = le64_to_cpu(counters->rx_broadcast);
2266         data[10] = le32_to_cpu(counters->rx_multicast);
2267         data[11] = le16_to_cpu(counters->tx_aborted);
2268         data[12] = le16_to_cpu(counters->tx_underun);
2269 }
2270
2271 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2272 {
2273         switch(stringset) {
2274         case ETH_SS_STATS:
2275                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2276                 break;
2277         }
2278 }
2279
2280 static int rtl8169_nway_reset(struct net_device *dev)
2281 {
2282         struct rtl8169_private *tp = netdev_priv(dev);
2283
2284         return mii_nway_restart(&tp->mii);
2285 }
2286
2287 /*
2288  * Interrupt coalescing
2289  *
2290  * > 1 - the availability of the IntrMitigate (0xe2) register through the
2291  * >     8169, 8168 and 810x line of chipsets
2292  *
2293  * 8169, 8168, and 8136(810x) serial chipsets support it.
2294  *
2295  * > 2 - the Tx timer unit at gigabit speed
2296  *
2297  * The unit of the timer depends on both the speed and the setting of CPlusCmd
2298  * (0xe0) bit 1 and bit 0.
2299  *
2300  * For 8169
2301  * bit[1:0] \ speed        1000M           100M            10M
2302  * 0 0                     320ns           2.56us          40.96us
2303  * 0 1                     2.56us          20.48us         327.7us
2304  * 1 0                     5.12us          40.96us         655.4us
2305  * 1 1                     10.24us         81.92us         1.31ms
2306  *
2307  * For the other
2308  * bit[1:0] \ speed        1000M           100M            10M
2309  * 0 0                     5us             2.56us          40.96us
2310  * 0 1                     40us            20.48us         327.7us
2311  * 1 0                     80us            40.96us         655.4us
2312  * 1 1                     160us           81.92us         1.31ms
2313  */
2314
2315 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2316 struct rtl_coalesce_scale {
2317         /* Rx / Tx */
2318         u32 nsecs[2];
2319 };
2320
2321 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2322 struct rtl_coalesce_info {
2323         u32 speed;
2324         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
2325 };
2326
2327 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2328 #define rxtx_x1822(r, t) {              \
2329         {{(r),          (t)}},          \
2330         {{(r)*8,        (t)*8}},        \
2331         {{(r)*8*2,      (t)*8*2}},      \
2332         {{(r)*8*2*2,    (t)*8*2*2}},    \
2333 }
2334 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2335         /* speed        delays:     rx00   tx00 */
2336         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2337         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2338         { SPEED_1000,   rxtx_x1822(  320,   320)        },
2339         { 0 },
2340 };
2341
2342 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2343         /* speed        delays:     rx00   tx00 */
2344         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2345         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2346         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
2347         { 0 },
2348 };
2349 #undef rxtx_x1822
2350
2351 /* get rx/tx scale vector corresponding to current speed */
2352 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2353 {
2354         struct rtl8169_private *tp = netdev_priv(dev);
2355         struct ethtool_link_ksettings ecmd;
2356         const struct rtl_coalesce_info *ci;
2357         int rc;
2358
2359         rc = rtl8169_get_link_ksettings(dev, &ecmd);
2360         if (rc < 0)
2361                 return ERR_PTR(rc);
2362
2363         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2364                 if (ecmd.base.speed == ci->speed) {
2365                         return ci;
2366                 }
2367         }
2368
2369         return ERR_PTR(-ELNRNG);
2370 }
2371
2372 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2373 {
2374         struct rtl8169_private *tp = netdev_priv(dev);
2375         const struct rtl_coalesce_info *ci;
2376         const struct rtl_coalesce_scale *scale;
2377         struct {
2378                 u32 *max_frames;
2379                 u32 *usecs;
2380         } coal_settings [] = {
2381                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2382                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2383         }, *p = coal_settings;
2384         int i;
2385         u16 w;
2386
2387         memset(ec, 0, sizeof(*ec));
2388
2389         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2390         ci = rtl_coalesce_info(dev);
2391         if (IS_ERR(ci))
2392                 return PTR_ERR(ci);
2393
2394         scale = &ci->scalev[RTL_R16(tp, CPlusCmd) & 3];
2395
2396         /* read IntrMitigate and adjust according to scale */
2397         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2398                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2399                 w >>= RTL_COALESCE_SHIFT;
2400                 *p->usecs = w & RTL_COALESCE_MASK;
2401         }
2402
2403         for (i = 0; i < 2; i++) {
2404                 p = coal_settings + i;
2405                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2406
2407                 /*
2408                  * ethtool_coalesce says it is illegal to set both usecs and
2409                  * max_frames to 0.
2410                  */
2411                 if (!*p->usecs && !*p->max_frames)
2412                         *p->max_frames = 1;
2413         }
2414
2415         return 0;
2416 }
2417
2418 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2419 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2420                         struct net_device *dev, u32 nsec, u16 *cp01)
2421 {
2422         const struct rtl_coalesce_info *ci;
2423         u16 i;
2424
2425         ci = rtl_coalesce_info(dev);
2426         if (IS_ERR(ci))
2427                 return ERR_CAST(ci);
2428
2429         for (i = 0; i < 4; i++) {
2430                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2431                                         ci->scalev[i].nsecs[1]);
2432                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2433                         *cp01 = i;
2434                         return &ci->scalev[i];
2435                 }
2436         }
2437
2438         return ERR_PTR(-EINVAL);
2439 }
2440
2441 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2442 {
2443         struct rtl8169_private *tp = netdev_priv(dev);
2444         const struct rtl_coalesce_scale *scale;
2445         struct {
2446                 u32 frames;
2447                 u32 usecs;
2448         } coal_settings [] = {
2449                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2450                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2451         }, *p = coal_settings;
2452         u16 w = 0, cp01;
2453         int i;
2454
2455         scale = rtl_coalesce_choose_scale(dev,
2456                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2457         if (IS_ERR(scale))
2458                 return PTR_ERR(scale);
2459
2460         for (i = 0; i < 2; i++, p++) {
2461                 u32 units;
2462
2463                 /*
2464                  * accept max_frames=1 we returned in rtl_get_coalesce.
2465                  * accept it not only when usecs=0 because of e.g. the following scenario:
2466                  *
2467                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2468                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2469                  * - then user does `ethtool -C eth0 rx-usecs 100`
2470                  *
2471                  * since ethtool sends to kernel whole ethtool_coalesce
2472                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2473                  * we'll reject it below in `frames % 4 != 0`.
2474                  */
2475                 if (p->frames == 1) {
2476                         p->frames = 0;
2477                 }
2478
2479                 units = p->usecs * 1000 / scale->nsecs[i];
2480                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2481                         return -EINVAL;
2482
2483                 w <<= RTL_COALESCE_SHIFT;
2484                 w |= units;
2485                 w <<= RTL_COALESCE_SHIFT;
2486                 w |= p->frames >> 2;
2487         }
2488
2489         rtl_lock_work(tp);
2490
2491         RTL_W16(tp, IntrMitigate, swab16(w));
2492
2493         tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2494         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2495         RTL_R16(tp, CPlusCmd);
2496
2497         rtl_unlock_work(tp);
2498
2499         return 0;
2500 }
2501
2502 static const struct ethtool_ops rtl8169_ethtool_ops = {
2503         .get_drvinfo            = rtl8169_get_drvinfo,
2504         .get_regs_len           = rtl8169_get_regs_len,
2505         .get_link               = ethtool_op_get_link,
2506         .get_coalesce           = rtl_get_coalesce,
2507         .set_coalesce           = rtl_set_coalesce,
2508         .get_msglevel           = rtl8169_get_msglevel,
2509         .set_msglevel           = rtl8169_set_msglevel,
2510         .get_regs               = rtl8169_get_regs,
2511         .get_wol                = rtl8169_get_wol,
2512         .set_wol                = rtl8169_set_wol,
2513         .get_strings            = rtl8169_get_strings,
2514         .get_sset_count         = rtl8169_get_sset_count,
2515         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2516         .get_ts_info            = ethtool_op_get_ts_info,
2517         .nway_reset             = rtl8169_nway_reset,
2518         .get_link_ksettings     = rtl8169_get_link_ksettings,
2519         .set_link_ksettings     = rtl8169_set_link_ksettings,
2520 };
2521
2522 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2523                                     struct net_device *dev, u8 default_version)
2524 {
2525         /*
2526          * The driver currently handles the 8168Bf and the 8168Be identically
2527          * but they can be identified more specifically through the test below
2528          * if needed:
2529          *
2530          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2531          *
2532          * Same thing for the 8101Eb and the 8101Ec:
2533          *
2534          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2535          */
2536         static const struct rtl_mac_info {
2537                 u32 mask;
2538                 u32 val;
2539                 int mac_version;
2540         } mac_info[] = {
2541                 /* 8168EP family. */
2542                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2543                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2544                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2545
2546                 /* 8168H family. */
2547                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2548                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2549
2550                 /* 8168G family. */
2551                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2552                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2553                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2554                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2555
2556                 /* 8168F family. */
2557                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2558                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2559                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2560
2561                 /* 8168E family. */
2562                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2563                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2564                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2565                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2566
2567                 /* 8168D family. */
2568                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2569                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2570                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2571
2572                 /* 8168DP family. */
2573                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2574                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2575                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2576
2577                 /* 8168C family. */
2578                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2579                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2580                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2581                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2582                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2583                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2584                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2585                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2586                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2587
2588                 /* 8168B family. */
2589                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2590                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2591                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2592                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2593
2594                 /* 8101 family. */
2595                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2596                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2597                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2598                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2599                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2600                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2601                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2602                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2603                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2604                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2605                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2606                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2607                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2608                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2609                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2610                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2611                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2612                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2613                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2614                 /* FIXME: where did these entries come from ? -- FR */
2615                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2616                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2617
2618                 /* 8110 family. */
2619                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2620                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2621                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2622                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2623                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2624                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2625
2626                 /* Catch-all */
2627                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2628         };
2629         const struct rtl_mac_info *p = mac_info;
2630         u32 reg;
2631
2632         reg = RTL_R32(tp, TxConfig);
2633         while ((reg & p->mask) != p->val)
2634                 p++;
2635         tp->mac_version = p->mac_version;
2636
2637         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2638                 netif_notice(tp, probe, dev,
2639                              "unknown MAC, using family default\n");
2640                 tp->mac_version = default_version;
2641         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2642                 tp->mac_version = tp->mii.supports_gmii ?
2643                                   RTL_GIGA_MAC_VER_42 :
2644                                   RTL_GIGA_MAC_VER_43;
2645         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2646                 tp->mac_version = tp->mii.supports_gmii ?
2647                                   RTL_GIGA_MAC_VER_45 :
2648                                   RTL_GIGA_MAC_VER_47;
2649         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2650                 tp->mac_version = tp->mii.supports_gmii ?
2651                                   RTL_GIGA_MAC_VER_46 :
2652                                   RTL_GIGA_MAC_VER_48;
2653         }
2654 }
2655
2656 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2657 {
2658         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2659 }
2660
2661 struct phy_reg {
2662         u16 reg;
2663         u16 val;
2664 };
2665
2666 static void rtl_writephy_batch(struct rtl8169_private *tp,
2667                                const struct phy_reg *regs, int len)
2668 {
2669         while (len-- > 0) {
2670                 rtl_writephy(tp, regs->reg, regs->val);
2671                 regs++;
2672         }
2673 }
2674
2675 #define PHY_READ                0x00000000
2676 #define PHY_DATA_OR             0x10000000
2677 #define PHY_DATA_AND            0x20000000
2678 #define PHY_BJMPN               0x30000000
2679 #define PHY_MDIO_CHG            0x40000000
2680 #define PHY_CLEAR_READCOUNT     0x70000000
2681 #define PHY_WRITE               0x80000000
2682 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2683 #define PHY_COMP_EQ_SKIPN       0xa0000000
2684 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2685 #define PHY_WRITE_PREVIOUS      0xc0000000
2686 #define PHY_SKIPN               0xd0000000
2687 #define PHY_DELAY_MS            0xe0000000
2688
2689 struct fw_info {
2690         u32     magic;
2691         char    version[RTL_VER_SIZE];
2692         __le32  fw_start;
2693         __le32  fw_len;
2694         u8      chksum;
2695 } __packed;
2696
2697 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2698
2699 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2700 {
2701         const struct firmware *fw = rtl_fw->fw;
2702         struct fw_info *fw_info = (struct fw_info *)fw->data;
2703         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2704         char *version = rtl_fw->version;
2705         bool rc = false;
2706
2707         if (fw->size < FW_OPCODE_SIZE)
2708                 goto out;
2709
2710         if (!fw_info->magic) {
2711                 size_t i, size, start;
2712                 u8 checksum = 0;
2713
2714                 if (fw->size < sizeof(*fw_info))
2715                         goto out;
2716
2717                 for (i = 0; i < fw->size; i++)
2718                         checksum += fw->data[i];
2719                 if (checksum != 0)
2720                         goto out;
2721
2722                 start = le32_to_cpu(fw_info->fw_start);
2723                 if (start > fw->size)
2724                         goto out;
2725
2726                 size = le32_to_cpu(fw_info->fw_len);
2727                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2728                         goto out;
2729
2730                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2731
2732                 pa->code = (__le32 *)(fw->data + start);
2733                 pa->size = size;
2734         } else {
2735                 if (fw->size % FW_OPCODE_SIZE)
2736                         goto out;
2737
2738                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2739
2740                 pa->code = (__le32 *)fw->data;
2741                 pa->size = fw->size / FW_OPCODE_SIZE;
2742         }
2743         version[RTL_VER_SIZE - 1] = 0;
2744
2745         rc = true;
2746 out:
2747         return rc;
2748 }
2749
2750 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2751                            struct rtl_fw_phy_action *pa)
2752 {
2753         bool rc = false;
2754         size_t index;
2755
2756         for (index = 0; index < pa->size; index++) {
2757                 u32 action = le32_to_cpu(pa->code[index]);
2758                 u32 regno = (action & 0x0fff0000) >> 16;
2759
2760                 switch(action & 0xf0000000) {
2761                 case PHY_READ:
2762                 case PHY_DATA_OR:
2763                 case PHY_DATA_AND:
2764                 case PHY_MDIO_CHG:
2765                 case PHY_CLEAR_READCOUNT:
2766                 case PHY_WRITE:
2767                 case PHY_WRITE_PREVIOUS:
2768                 case PHY_DELAY_MS:
2769                         break;
2770
2771                 case PHY_BJMPN:
2772                         if (regno > index) {
2773                                 netif_err(tp, ifup, tp->dev,
2774                                           "Out of range of firmware\n");
2775                                 goto out;
2776                         }
2777                         break;
2778                 case PHY_READCOUNT_EQ_SKIP:
2779                         if (index + 2 >= pa->size) {
2780                                 netif_err(tp, ifup, tp->dev,
2781                                           "Out of range of firmware\n");
2782                                 goto out;
2783                         }
2784                         break;
2785                 case PHY_COMP_EQ_SKIPN:
2786                 case PHY_COMP_NEQ_SKIPN:
2787                 case PHY_SKIPN:
2788                         if (index + 1 + regno >= pa->size) {
2789                                 netif_err(tp, ifup, tp->dev,
2790                                           "Out of range of firmware\n");
2791                                 goto out;
2792                         }
2793                         break;
2794
2795                 default:
2796                         netif_err(tp, ifup, tp->dev,
2797                                   "Invalid action 0x%08x\n", action);
2798                         goto out;
2799                 }
2800         }
2801         rc = true;
2802 out:
2803         return rc;
2804 }
2805
2806 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2807 {
2808         struct net_device *dev = tp->dev;
2809         int rc = -EINVAL;
2810
2811         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2812                 netif_err(tp, ifup, dev, "invalid firmware\n");
2813                 goto out;
2814         }
2815
2816         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2817                 rc = 0;
2818 out:
2819         return rc;
2820 }
2821
2822 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2823 {
2824         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2825         struct mdio_ops org, *ops = &tp->mdio_ops;
2826         u32 predata, count;
2827         size_t index;
2828
2829         predata = count = 0;
2830         org.write = ops->write;
2831         org.read = ops->read;
2832
2833         for (index = 0; index < pa->size; ) {
2834                 u32 action = le32_to_cpu(pa->code[index]);
2835                 u32 data = action & 0x0000ffff;
2836                 u32 regno = (action & 0x0fff0000) >> 16;
2837
2838                 if (!action)
2839                         break;
2840
2841                 switch(action & 0xf0000000) {
2842                 case PHY_READ:
2843                         predata = rtl_readphy(tp, regno);
2844                         count++;
2845                         index++;
2846                         break;
2847                 case PHY_DATA_OR:
2848                         predata |= data;
2849                         index++;
2850                         break;
2851                 case PHY_DATA_AND:
2852                         predata &= data;
2853                         index++;
2854                         break;
2855                 case PHY_BJMPN:
2856                         index -= regno;
2857                         break;
2858                 case PHY_MDIO_CHG:
2859                         if (data == 0) {
2860                                 ops->write = org.write;
2861                                 ops->read = org.read;
2862                         } else if (data == 1) {
2863                                 ops->write = mac_mcu_write;
2864                                 ops->read = mac_mcu_read;
2865                         }
2866
2867                         index++;
2868                         break;
2869                 case PHY_CLEAR_READCOUNT:
2870                         count = 0;
2871                         index++;
2872                         break;
2873                 case PHY_WRITE:
2874                         rtl_writephy(tp, regno, data);
2875                         index++;
2876                         break;
2877                 case PHY_READCOUNT_EQ_SKIP:
2878                         index += (count == data) ? 2 : 1;
2879                         break;
2880                 case PHY_COMP_EQ_SKIPN:
2881                         if (predata == data)
2882                                 index += regno;
2883                         index++;
2884                         break;
2885                 case PHY_COMP_NEQ_SKIPN:
2886                         if (predata != data)
2887                                 index += regno;
2888                         index++;
2889                         break;
2890                 case PHY_WRITE_PREVIOUS:
2891                         rtl_writephy(tp, regno, predata);
2892                         index++;
2893                         break;
2894                 case PHY_SKIPN:
2895                         index += regno + 1;
2896                         break;
2897                 case PHY_DELAY_MS:
2898                         mdelay(data);
2899                         index++;
2900                         break;
2901
2902                 default:
2903                         BUG();
2904                 }
2905         }
2906
2907         ops->write = org.write;
2908         ops->read = org.read;
2909 }
2910
2911 static void rtl_release_firmware(struct rtl8169_private *tp)
2912 {
2913         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2914                 release_firmware(tp->rtl_fw->fw);
2915                 kfree(tp->rtl_fw);
2916         }
2917         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2918 }
2919
2920 static void rtl_apply_firmware(struct rtl8169_private *tp)
2921 {
2922         struct rtl_fw *rtl_fw = tp->rtl_fw;
2923
2924         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2925         if (!IS_ERR_OR_NULL(rtl_fw))
2926                 rtl_phy_write_fw(tp, rtl_fw);
2927 }
2928
2929 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2930 {
2931         if (rtl_readphy(tp, reg) != val)
2932                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2933         else
2934                 rtl_apply_firmware(tp);
2935 }
2936
2937 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2938 {
2939         static const struct phy_reg phy_reg_init[] = {
2940                 { 0x1f, 0x0001 },
2941                 { 0x06, 0x006e },
2942                 { 0x08, 0x0708 },
2943                 { 0x15, 0x4000 },
2944                 { 0x18, 0x65c7 },
2945
2946                 { 0x1f, 0x0001 },
2947                 { 0x03, 0x00a1 },
2948                 { 0x02, 0x0008 },
2949                 { 0x01, 0x0120 },
2950                 { 0x00, 0x1000 },
2951                 { 0x04, 0x0800 },
2952                 { 0x04, 0x0000 },
2953
2954                 { 0x03, 0xff41 },
2955                 { 0x02, 0xdf60 },
2956                 { 0x01, 0x0140 },
2957                 { 0x00, 0x0077 },
2958                 { 0x04, 0x7800 },
2959                 { 0x04, 0x7000 },
2960
2961                 { 0x03, 0x802f },
2962                 { 0x02, 0x4f02 },
2963                 { 0x01, 0x0409 },
2964                 { 0x00, 0xf0f9 },
2965                 { 0x04, 0x9800 },
2966                 { 0x04, 0x9000 },
2967
2968                 { 0x03, 0xdf01 },
2969                 { 0x02, 0xdf20 },
2970                 { 0x01, 0xff95 },
2971                 { 0x00, 0xba00 },
2972                 { 0x04, 0xa800 },
2973                 { 0x04, 0xa000 },
2974
2975                 { 0x03, 0xff41 },
2976                 { 0x02, 0xdf20 },
2977                 { 0x01, 0x0140 },
2978                 { 0x00, 0x00bb },
2979                 { 0x04, 0xb800 },
2980                 { 0x04, 0xb000 },
2981
2982                 { 0x03, 0xdf41 },
2983                 { 0x02, 0xdc60 },
2984                 { 0x01, 0x6340 },
2985                 { 0x00, 0x007d },
2986                 { 0x04, 0xd800 },
2987                 { 0x04, 0xd000 },
2988
2989                 { 0x03, 0xdf01 },
2990                 { 0x02, 0xdf20 },
2991                 { 0x01, 0x100a },
2992                 { 0x00, 0xa0ff },
2993                 { 0x04, 0xf800 },
2994                 { 0x04, 0xf000 },
2995
2996                 { 0x1f, 0x0000 },
2997                 { 0x0b, 0x0000 },
2998                 { 0x00, 0x9200 }
2999         };
3000
3001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3002 }
3003
3004 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
3005 {
3006         static const struct phy_reg phy_reg_init[] = {
3007                 { 0x1f, 0x0002 },
3008                 { 0x01, 0x90d0 },
3009                 { 0x1f, 0x0000 }
3010         };
3011
3012         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3013 }
3014
3015 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
3016 {
3017         struct pci_dev *pdev = tp->pci_dev;
3018
3019         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3020             (pdev->subsystem_device != 0xe000))
3021                 return;
3022
3023         rtl_writephy(tp, 0x1f, 0x0001);
3024         rtl_writephy(tp, 0x10, 0xf01b);
3025         rtl_writephy(tp, 0x1f, 0x0000);
3026 }
3027
3028 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
3029 {
3030         static const struct phy_reg phy_reg_init[] = {
3031                 { 0x1f, 0x0001 },
3032                 { 0x04, 0x0000 },
3033                 { 0x03, 0x00a1 },
3034                 { 0x02, 0x0008 },
3035                 { 0x01, 0x0120 },
3036                 { 0x00, 0x1000 },
3037                 { 0x04, 0x0800 },
3038                 { 0x04, 0x9000 },
3039                 { 0x03, 0x802f },
3040                 { 0x02, 0x4f02 },
3041                 { 0x01, 0x0409 },
3042                 { 0x00, 0xf099 },
3043                 { 0x04, 0x9800 },
3044                 { 0x04, 0xa000 },
3045                 { 0x03, 0xdf01 },
3046                 { 0x02, 0xdf20 },
3047                 { 0x01, 0xff95 },
3048                 { 0x00, 0xba00 },
3049                 { 0x04, 0xa800 },
3050                 { 0x04, 0xf000 },
3051                 { 0x03, 0xdf01 },
3052                 { 0x02, 0xdf20 },
3053                 { 0x01, 0x101a },
3054                 { 0x00, 0xa0ff },
3055                 { 0x04, 0xf800 },
3056                 { 0x04, 0x0000 },
3057                 { 0x1f, 0x0000 },
3058
3059                 { 0x1f, 0x0001 },
3060                 { 0x10, 0xf41b },
3061                 { 0x14, 0xfb54 },
3062                 { 0x18, 0xf5c7 },
3063                 { 0x1f, 0x0000 },
3064
3065                 { 0x1f, 0x0001 },
3066                 { 0x17, 0x0cc0 },
3067                 { 0x1f, 0x0000 }
3068         };
3069
3070         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3071
3072         rtl8169scd_hw_phy_config_quirk(tp);
3073 }
3074
3075 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
3076 {
3077         static const struct phy_reg phy_reg_init[] = {
3078                 { 0x1f, 0x0001 },
3079                 { 0x04, 0x0000 },
3080                 { 0x03, 0x00a1 },
3081                 { 0x02, 0x0008 },
3082                 { 0x01, 0x0120 },
3083                 { 0x00, 0x1000 },
3084                 { 0x04, 0x0800 },
3085                 { 0x04, 0x9000 },
3086                 { 0x03, 0x802f },
3087                 { 0x02, 0x4f02 },
3088                 { 0x01, 0x0409 },
3089                 { 0x00, 0xf099 },
3090                 { 0x04, 0x9800 },
3091                 { 0x04, 0xa000 },
3092                 { 0x03, 0xdf01 },
3093                 { 0x02, 0xdf20 },
3094                 { 0x01, 0xff95 },
3095                 { 0x00, 0xba00 },
3096                 { 0x04, 0xa800 },
3097                 { 0x04, 0xf000 },
3098                 { 0x03, 0xdf01 },
3099                 { 0x02, 0xdf20 },
3100                 { 0x01, 0x101a },
3101                 { 0x00, 0xa0ff },
3102                 { 0x04, 0xf800 },
3103                 { 0x04, 0x0000 },
3104                 { 0x1f, 0x0000 },
3105
3106                 { 0x1f, 0x0001 },
3107                 { 0x0b, 0x8480 },
3108                 { 0x1f, 0x0000 },
3109
3110                 { 0x1f, 0x0001 },
3111                 { 0x18, 0x67c7 },
3112                 { 0x04, 0x2000 },
3113                 { 0x03, 0x002f },
3114                 { 0x02, 0x4360 },
3115                 { 0x01, 0x0109 },
3116                 { 0x00, 0x3022 },
3117                 { 0x04, 0x2800 },
3118                 { 0x1f, 0x0000 },
3119
3120                 { 0x1f, 0x0001 },
3121                 { 0x17, 0x0cc0 },
3122                 { 0x1f, 0x0000 }
3123         };
3124
3125         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3126 }
3127
3128 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3129 {
3130         static const struct phy_reg phy_reg_init[] = {
3131                 { 0x10, 0xf41b },
3132                 { 0x1f, 0x0000 }
3133         };
3134
3135         rtl_writephy(tp, 0x1f, 0x0001);
3136         rtl_patchphy(tp, 0x16, 1 << 0);
3137
3138         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3139 }
3140
3141 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3142 {
3143         static const struct phy_reg phy_reg_init[] = {
3144                 { 0x1f, 0x0001 },
3145                 { 0x10, 0xf41b },
3146                 { 0x1f, 0x0000 }
3147         };
3148
3149         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3150 }
3151
3152 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3153 {
3154         static const struct phy_reg phy_reg_init[] = {
3155                 { 0x1f, 0x0000 },
3156                 { 0x1d, 0x0f00 },
3157                 { 0x1f, 0x0002 },
3158                 { 0x0c, 0x1ec8 },
3159                 { 0x1f, 0x0000 }
3160         };
3161
3162         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3163 }
3164
3165 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3166 {
3167         static const struct phy_reg phy_reg_init[] = {
3168                 { 0x1f, 0x0001 },
3169                 { 0x1d, 0x3d98 },
3170                 { 0x1f, 0x0000 }
3171         };
3172
3173         rtl_writephy(tp, 0x1f, 0x0000);
3174         rtl_patchphy(tp, 0x14, 1 << 5);
3175         rtl_patchphy(tp, 0x0d, 1 << 5);
3176
3177         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3178 }
3179
3180 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3181 {
3182         static const struct phy_reg phy_reg_init[] = {
3183                 { 0x1f, 0x0001 },
3184                 { 0x12, 0x2300 },
3185                 { 0x1f, 0x0002 },
3186                 { 0x00, 0x88d4 },
3187                 { 0x01, 0x82b1 },
3188                 { 0x03, 0x7002 },
3189                 { 0x08, 0x9e30 },
3190                 { 0x09, 0x01f0 },
3191                 { 0x0a, 0x5500 },
3192                 { 0x0c, 0x00c8 },
3193                 { 0x1f, 0x0003 },
3194                 { 0x12, 0xc096 },
3195                 { 0x16, 0x000a },
3196                 { 0x1f, 0x0000 },
3197                 { 0x1f, 0x0000 },
3198                 { 0x09, 0x2000 },
3199                 { 0x09, 0x0000 }
3200         };
3201
3202         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3203
3204         rtl_patchphy(tp, 0x14, 1 << 5);
3205         rtl_patchphy(tp, 0x0d, 1 << 5);
3206         rtl_writephy(tp, 0x1f, 0x0000);
3207 }
3208
3209 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3210 {
3211         static const struct phy_reg phy_reg_init[] = {
3212                 { 0x1f, 0x0001 },
3213                 { 0x12, 0x2300 },
3214                 { 0x03, 0x802f },
3215                 { 0x02, 0x4f02 },
3216                 { 0x01, 0x0409 },
3217                 { 0x00, 0xf099 },
3218                 { 0x04, 0x9800 },
3219                 { 0x04, 0x9000 },
3220                 { 0x1d, 0x3d98 },
3221                 { 0x1f, 0x0002 },
3222                 { 0x0c, 0x7eb8 },
3223                 { 0x06, 0x0761 },
3224                 { 0x1f, 0x0003 },
3225                 { 0x16, 0x0f0a },
3226                 { 0x1f, 0x0000 }
3227         };
3228
3229         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3230
3231         rtl_patchphy(tp, 0x16, 1 << 0);
3232         rtl_patchphy(tp, 0x14, 1 << 5);
3233         rtl_patchphy(tp, 0x0d, 1 << 5);
3234         rtl_writephy(tp, 0x1f, 0x0000);
3235 }
3236
3237 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3238 {
3239         static const struct phy_reg phy_reg_init[] = {
3240                 { 0x1f, 0x0001 },
3241                 { 0x12, 0x2300 },
3242                 { 0x1d, 0x3d98 },
3243                 { 0x1f, 0x0002 },
3244                 { 0x0c, 0x7eb8 },
3245                 { 0x06, 0x5461 },
3246                 { 0x1f, 0x0003 },
3247                 { 0x16, 0x0f0a },
3248                 { 0x1f, 0x0000 }
3249         };
3250
3251         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3252
3253         rtl_patchphy(tp, 0x16, 1 << 0);
3254         rtl_patchphy(tp, 0x14, 1 << 5);
3255         rtl_patchphy(tp, 0x0d, 1 << 5);
3256         rtl_writephy(tp, 0x1f, 0x0000);
3257 }
3258
3259 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3260 {
3261         rtl8168c_3_hw_phy_config(tp);
3262 }
3263
3264 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3265 {
3266         static const struct phy_reg phy_reg_init_0[] = {
3267                 /* Channel Estimation */
3268                 { 0x1f, 0x0001 },
3269                 { 0x06, 0x4064 },
3270                 { 0x07, 0x2863 },
3271                 { 0x08, 0x059c },
3272                 { 0x09, 0x26b4 },
3273                 { 0x0a, 0x6a19 },
3274                 { 0x0b, 0xdcc8 },
3275                 { 0x10, 0xf06d },
3276                 { 0x14, 0x7f68 },
3277                 { 0x18, 0x7fd9 },
3278                 { 0x1c, 0xf0ff },
3279                 { 0x1d, 0x3d9c },
3280                 { 0x1f, 0x0003 },
3281                 { 0x12, 0xf49f },
3282                 { 0x13, 0x070b },
3283                 { 0x1a, 0x05ad },
3284                 { 0x14, 0x94c0 },
3285
3286                 /*
3287                  * Tx Error Issue
3288                  * Enhance line driver power
3289                  */
3290                 { 0x1f, 0x0002 },
3291                 { 0x06, 0x5561 },
3292                 { 0x1f, 0x0005 },
3293                 { 0x05, 0x8332 },
3294                 { 0x06, 0x5561 },
3295
3296                 /*
3297                  * Can not link to 1Gbps with bad cable
3298                  * Decrease SNR threshold form 21.07dB to 19.04dB
3299                  */
3300                 { 0x1f, 0x0001 },
3301                 { 0x17, 0x0cc0 },
3302
3303                 { 0x1f, 0x0000 },
3304                 { 0x0d, 0xf880 }
3305         };
3306
3307         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3308
3309         /*
3310          * Rx Error Issue
3311          * Fine Tune Switching regulator parameter
3312          */
3313         rtl_writephy(tp, 0x1f, 0x0002);
3314         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3315         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3316
3317         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3318                 static const struct phy_reg phy_reg_init[] = {
3319                         { 0x1f, 0x0002 },
3320                         { 0x05, 0x669a },
3321                         { 0x1f, 0x0005 },
3322                         { 0x05, 0x8330 },
3323                         { 0x06, 0x669a },
3324                         { 0x1f, 0x0002 }
3325                 };
3326                 int val;
3327
3328                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3329
3330                 val = rtl_readphy(tp, 0x0d);
3331
3332                 if ((val & 0x00ff) != 0x006c) {
3333                         static const u32 set[] = {
3334                                 0x0065, 0x0066, 0x0067, 0x0068,
3335                                 0x0069, 0x006a, 0x006b, 0x006c
3336                         };
3337                         int i;
3338
3339                         rtl_writephy(tp, 0x1f, 0x0002);
3340
3341                         val &= 0xff00;
3342                         for (i = 0; i < ARRAY_SIZE(set); i++)
3343                                 rtl_writephy(tp, 0x0d, val | set[i]);
3344                 }
3345         } else {
3346                 static const struct phy_reg phy_reg_init[] = {
3347                         { 0x1f, 0x0002 },
3348                         { 0x05, 0x6662 },
3349                         { 0x1f, 0x0005 },
3350                         { 0x05, 0x8330 },
3351                         { 0x06, 0x6662 }
3352                 };
3353
3354                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3355         }
3356
3357         /* RSET couple improve */
3358         rtl_writephy(tp, 0x1f, 0x0002);
3359         rtl_patchphy(tp, 0x0d, 0x0300);
3360         rtl_patchphy(tp, 0x0f, 0x0010);
3361
3362         /* Fine tune PLL performance */
3363         rtl_writephy(tp, 0x1f, 0x0002);
3364         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3365         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3366
3367         rtl_writephy(tp, 0x1f, 0x0005);
3368         rtl_writephy(tp, 0x05, 0x001b);
3369
3370         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3371
3372         rtl_writephy(tp, 0x1f, 0x0000);
3373 }
3374
3375 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3376 {
3377         static const struct phy_reg phy_reg_init_0[] = {
3378                 /* Channel Estimation */
3379                 { 0x1f, 0x0001 },
3380                 { 0x06, 0x4064 },
3381                 { 0x07, 0x2863 },
3382                 { 0x08, 0x059c },
3383                 { 0x09, 0x26b4 },
3384                 { 0x0a, 0x6a19 },
3385                 { 0x0b, 0xdcc8 },
3386                 { 0x10, 0xf06d },
3387                 { 0x14, 0x7f68 },
3388                 { 0x18, 0x7fd9 },
3389                 { 0x1c, 0xf0ff },
3390                 { 0x1d, 0x3d9c },
3391                 { 0x1f, 0x0003 },
3392                 { 0x12, 0xf49f },
3393                 { 0x13, 0x070b },
3394                 { 0x1a, 0x05ad },
3395                 { 0x14, 0x94c0 },
3396
3397                 /*
3398                  * Tx Error Issue
3399                  * Enhance line driver power
3400                  */
3401                 { 0x1f, 0x0002 },
3402                 { 0x06, 0x5561 },
3403                 { 0x1f, 0x0005 },
3404                 { 0x05, 0x8332 },
3405                 { 0x06, 0x5561 },
3406
3407                 /*
3408                  * Can not link to 1Gbps with bad cable
3409                  * Decrease SNR threshold form 21.07dB to 19.04dB
3410                  */
3411                 { 0x1f, 0x0001 },
3412                 { 0x17, 0x0cc0 },
3413
3414                 { 0x1f, 0x0000 },
3415                 { 0x0d, 0xf880 }
3416         };
3417
3418         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3419
3420         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3421                 static const struct phy_reg phy_reg_init[] = {
3422                         { 0x1f, 0x0002 },
3423                         { 0x05, 0x669a },
3424                         { 0x1f, 0x0005 },
3425                         { 0x05, 0x8330 },
3426                         { 0x06, 0x669a },
3427
3428                         { 0x1f, 0x0002 }
3429                 };
3430                 int val;
3431
3432                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3433
3434                 val = rtl_readphy(tp, 0x0d);
3435                 if ((val & 0x00ff) != 0x006c) {
3436                         static const u32 set[] = {
3437                                 0x0065, 0x0066, 0x0067, 0x0068,
3438                                 0x0069, 0x006a, 0x006b, 0x006c
3439                         };
3440                         int i;
3441
3442                         rtl_writephy(tp, 0x1f, 0x0002);
3443
3444                         val &= 0xff00;
3445                         for (i = 0; i < ARRAY_SIZE(set); i++)
3446                                 rtl_writephy(tp, 0x0d, val | set[i]);
3447                 }
3448         } else {
3449                 static const struct phy_reg phy_reg_init[] = {
3450                         { 0x1f, 0x0002 },
3451                         { 0x05, 0x2642 },
3452                         { 0x1f, 0x0005 },
3453                         { 0x05, 0x8330 },
3454                         { 0x06, 0x2642 }
3455                 };
3456
3457                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3458         }
3459
3460         /* Fine tune PLL performance */
3461         rtl_writephy(tp, 0x1f, 0x0002);
3462         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3463         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3464
3465         /* Switching regulator Slew rate */
3466         rtl_writephy(tp, 0x1f, 0x0002);
3467         rtl_patchphy(tp, 0x0f, 0x0017);
3468
3469         rtl_writephy(tp, 0x1f, 0x0005);
3470         rtl_writephy(tp, 0x05, 0x001b);
3471
3472         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3473
3474         rtl_writephy(tp, 0x1f, 0x0000);
3475 }
3476
3477 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3478 {
3479         static const struct phy_reg phy_reg_init[] = {
3480                 { 0x1f, 0x0002 },
3481                 { 0x10, 0x0008 },
3482                 { 0x0d, 0x006c },
3483
3484                 { 0x1f, 0x0000 },
3485                 { 0x0d, 0xf880 },
3486
3487                 { 0x1f, 0x0001 },
3488                 { 0x17, 0x0cc0 },
3489
3490                 { 0x1f, 0x0001 },
3491                 { 0x0b, 0xa4d8 },
3492                 { 0x09, 0x281c },
3493                 { 0x07, 0x2883 },
3494                 { 0x0a, 0x6b35 },
3495                 { 0x1d, 0x3da4 },
3496                 { 0x1c, 0xeffd },
3497                 { 0x14, 0x7f52 },
3498                 { 0x18, 0x7fc6 },
3499                 { 0x08, 0x0601 },
3500                 { 0x06, 0x4063 },
3501                 { 0x10, 0xf074 },
3502                 { 0x1f, 0x0003 },
3503                 { 0x13, 0x0789 },
3504                 { 0x12, 0xf4bd },
3505                 { 0x1a, 0x04fd },
3506                 { 0x14, 0x84b0 },
3507                 { 0x1f, 0x0000 },
3508                 { 0x00, 0x9200 },
3509
3510                 { 0x1f, 0x0005 },
3511                 { 0x01, 0x0340 },
3512                 { 0x1f, 0x0001 },
3513                 { 0x04, 0x4000 },
3514                 { 0x03, 0x1d21 },
3515                 { 0x02, 0x0c32 },
3516                 { 0x01, 0x0200 },
3517                 { 0x00, 0x5554 },
3518                 { 0x04, 0x4800 },
3519                 { 0x04, 0x4000 },
3520                 { 0x04, 0xf000 },
3521                 { 0x03, 0xdf01 },
3522                 { 0x02, 0xdf20 },
3523                 { 0x01, 0x101a },
3524                 { 0x00, 0xa0ff },
3525                 { 0x04, 0xf800 },
3526                 { 0x04, 0xf000 },
3527                 { 0x1f, 0x0000 },
3528
3529                 { 0x1f, 0x0007 },
3530                 { 0x1e, 0x0023 },
3531                 { 0x16, 0x0000 },
3532                 { 0x1f, 0x0000 }
3533         };
3534
3535         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3536 }
3537
3538 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3539 {
3540         static const struct phy_reg phy_reg_init[] = {
3541                 { 0x1f, 0x0001 },
3542                 { 0x17, 0x0cc0 },
3543
3544                 { 0x1f, 0x0007 },
3545                 { 0x1e, 0x002d },
3546                 { 0x18, 0x0040 },
3547                 { 0x1f, 0x0000 }
3548         };
3549
3550         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3551         rtl_patchphy(tp, 0x0d, 1 << 5);
3552 }
3553
3554 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3555 {
3556         static const struct phy_reg phy_reg_init[] = {
3557                 /* Enable Delay cap */
3558                 { 0x1f, 0x0005 },
3559                 { 0x05, 0x8b80 },
3560                 { 0x06, 0xc896 },
3561                 { 0x1f, 0x0000 },
3562
3563                 /* Channel estimation fine tune */
3564                 { 0x1f, 0x0001 },
3565                 { 0x0b, 0x6c20 },
3566                 { 0x07, 0x2872 },
3567                 { 0x1c, 0xefff },
3568                 { 0x1f, 0x0003 },
3569                 { 0x14, 0x6420 },
3570                 { 0x1f, 0x0000 },
3571
3572                 /* Update PFM & 10M TX idle timer */
3573                 { 0x1f, 0x0007 },
3574                 { 0x1e, 0x002f },
3575                 { 0x15, 0x1919 },
3576                 { 0x1f, 0x0000 },
3577
3578                 { 0x1f, 0x0007 },
3579                 { 0x1e, 0x00ac },
3580                 { 0x18, 0x0006 },
3581                 { 0x1f, 0x0000 }
3582         };
3583
3584         rtl_apply_firmware(tp);
3585
3586         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3587
3588         /* DCO enable for 10M IDLE Power */
3589         rtl_writephy(tp, 0x1f, 0x0007);
3590         rtl_writephy(tp, 0x1e, 0x0023);
3591         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3592         rtl_writephy(tp, 0x1f, 0x0000);
3593
3594         /* For impedance matching */
3595         rtl_writephy(tp, 0x1f, 0x0002);
3596         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3597         rtl_writephy(tp, 0x1f, 0x0000);
3598
3599         /* PHY auto speed down */
3600         rtl_writephy(tp, 0x1f, 0x0007);
3601         rtl_writephy(tp, 0x1e, 0x002d);
3602         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3603         rtl_writephy(tp, 0x1f, 0x0000);
3604         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3605
3606         rtl_writephy(tp, 0x1f, 0x0005);
3607         rtl_writephy(tp, 0x05, 0x8b86);
3608         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3609         rtl_writephy(tp, 0x1f, 0x0000);
3610
3611         rtl_writephy(tp, 0x1f, 0x0005);
3612         rtl_writephy(tp, 0x05, 0x8b85);
3613         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3614         rtl_writephy(tp, 0x1f, 0x0007);
3615         rtl_writephy(tp, 0x1e, 0x0020);
3616         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3617         rtl_writephy(tp, 0x1f, 0x0006);
3618         rtl_writephy(tp, 0x00, 0x5a00);
3619         rtl_writephy(tp, 0x1f, 0x0000);
3620         rtl_writephy(tp, 0x0d, 0x0007);
3621         rtl_writephy(tp, 0x0e, 0x003c);
3622         rtl_writephy(tp, 0x0d, 0x4007);
3623         rtl_writephy(tp, 0x0e, 0x0000);
3624         rtl_writephy(tp, 0x0d, 0x0000);
3625 }
3626
3627 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3628 {
3629         const u16 w[] = {
3630                 addr[0] | (addr[1] << 8),
3631                 addr[2] | (addr[3] << 8),
3632                 addr[4] | (addr[5] << 8)
3633         };
3634         const struct exgmac_reg e[] = {
3635                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3636                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3637                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3638                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3639         };
3640
3641         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3642 }
3643
3644 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3645 {
3646         static const struct phy_reg phy_reg_init[] = {
3647                 /* Enable Delay cap */
3648                 { 0x1f, 0x0004 },
3649                 { 0x1f, 0x0007 },
3650                 { 0x1e, 0x00ac },
3651                 { 0x18, 0x0006 },
3652                 { 0x1f, 0x0002 },
3653                 { 0x1f, 0x0000 },
3654                 { 0x1f, 0x0000 },
3655
3656                 /* Channel estimation fine tune */
3657                 { 0x1f, 0x0003 },
3658                 { 0x09, 0xa20f },
3659                 { 0x1f, 0x0000 },
3660                 { 0x1f, 0x0000 },
3661
3662                 /* Green Setting */
3663                 { 0x1f, 0x0005 },
3664                 { 0x05, 0x8b5b },
3665                 { 0x06, 0x9222 },
3666                 { 0x05, 0x8b6d },
3667                 { 0x06, 0x8000 },
3668                 { 0x05, 0x8b76 },
3669                 { 0x06, 0x8000 },
3670                 { 0x1f, 0x0000 }
3671         };
3672
3673         rtl_apply_firmware(tp);
3674
3675         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3676
3677         /* For 4-corner performance improve */
3678         rtl_writephy(tp, 0x1f, 0x0005);
3679         rtl_writephy(tp, 0x05, 0x8b80);
3680         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3681         rtl_writephy(tp, 0x1f, 0x0000);
3682
3683         /* PHY auto speed down */
3684         rtl_writephy(tp, 0x1f, 0x0004);
3685         rtl_writephy(tp, 0x1f, 0x0007);
3686         rtl_writephy(tp, 0x1e, 0x002d);
3687         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3688         rtl_writephy(tp, 0x1f, 0x0002);
3689         rtl_writephy(tp, 0x1f, 0x0000);
3690         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3691
3692         /* improve 10M EEE waveform */
3693         rtl_writephy(tp, 0x1f, 0x0005);
3694         rtl_writephy(tp, 0x05, 0x8b86);
3695         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3696         rtl_writephy(tp, 0x1f, 0x0000);
3697
3698         /* Improve 2-pair detection performance */
3699         rtl_writephy(tp, 0x1f, 0x0005);
3700         rtl_writephy(tp, 0x05, 0x8b85);
3701         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3702         rtl_writephy(tp, 0x1f, 0x0000);
3703
3704         /* EEE setting */
3705         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3706         rtl_writephy(tp, 0x1f, 0x0005);
3707         rtl_writephy(tp, 0x05, 0x8b85);
3708         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3709         rtl_writephy(tp, 0x1f, 0x0004);
3710         rtl_writephy(tp, 0x1f, 0x0007);
3711         rtl_writephy(tp, 0x1e, 0x0020);
3712         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3713         rtl_writephy(tp, 0x1f, 0x0002);
3714         rtl_writephy(tp, 0x1f, 0x0000);
3715         rtl_writephy(tp, 0x0d, 0x0007);
3716         rtl_writephy(tp, 0x0e, 0x003c);
3717         rtl_writephy(tp, 0x0d, 0x4007);
3718         rtl_writephy(tp, 0x0e, 0x0006);
3719         rtl_writephy(tp, 0x0d, 0x0000);
3720
3721         /* Green feature */
3722         rtl_writephy(tp, 0x1f, 0x0003);
3723         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3724         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3725         rtl_writephy(tp, 0x1f, 0x0000);
3726         rtl_writephy(tp, 0x1f, 0x0005);
3727         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3728         rtl_writephy(tp, 0x1f, 0x0000);
3729
3730         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3731         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3732 }
3733
3734 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3735 {
3736         /* For 4-corner performance improve */
3737         rtl_writephy(tp, 0x1f, 0x0005);
3738         rtl_writephy(tp, 0x05, 0x8b80);
3739         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3740         rtl_writephy(tp, 0x1f, 0x0000);
3741
3742         /* PHY auto speed down */
3743         rtl_writephy(tp, 0x1f, 0x0007);
3744         rtl_writephy(tp, 0x1e, 0x002d);
3745         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3746         rtl_writephy(tp, 0x1f, 0x0000);
3747         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3748
3749         /* Improve 10M EEE waveform */
3750         rtl_writephy(tp, 0x1f, 0x0005);
3751         rtl_writephy(tp, 0x05, 0x8b86);
3752         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3753         rtl_writephy(tp, 0x1f, 0x0000);
3754 }
3755
3756 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3757 {
3758         static const struct phy_reg phy_reg_init[] = {
3759                 /* Channel estimation fine tune */
3760                 { 0x1f, 0x0003 },
3761                 { 0x09, 0xa20f },
3762                 { 0x1f, 0x0000 },
3763
3764                 /* Modify green table for giga & fnet */
3765                 { 0x1f, 0x0005 },
3766                 { 0x05, 0x8b55 },
3767                 { 0x06, 0x0000 },
3768                 { 0x05, 0x8b5e },
3769                 { 0x06, 0x0000 },
3770                 { 0x05, 0x8b67 },
3771                 { 0x06, 0x0000 },
3772                 { 0x05, 0x8b70 },
3773                 { 0x06, 0x0000 },
3774                 { 0x1f, 0x0000 },
3775                 { 0x1f, 0x0007 },
3776                 { 0x1e, 0x0078 },
3777                 { 0x17, 0x0000 },
3778                 { 0x19, 0x00fb },
3779                 { 0x1f, 0x0000 },
3780
3781                 /* Modify green table for 10M */
3782                 { 0x1f, 0x0005 },
3783                 { 0x05, 0x8b79 },
3784                 { 0x06, 0xaa00 },
3785                 { 0x1f, 0x0000 },
3786
3787                 /* Disable hiimpedance detection (RTCT) */
3788                 { 0x1f, 0x0003 },
3789                 { 0x01, 0x328a },
3790                 { 0x1f, 0x0000 }
3791         };
3792
3793         rtl_apply_firmware(tp);
3794
3795         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3796
3797         rtl8168f_hw_phy_config(tp);
3798
3799         /* Improve 2-pair detection performance */
3800         rtl_writephy(tp, 0x1f, 0x0005);
3801         rtl_writephy(tp, 0x05, 0x8b85);
3802         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3803         rtl_writephy(tp, 0x1f, 0x0000);
3804 }
3805
3806 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3807 {
3808         rtl_apply_firmware(tp);
3809
3810         rtl8168f_hw_phy_config(tp);
3811 }
3812
3813 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3814 {
3815         static const struct phy_reg phy_reg_init[] = {
3816                 /* Channel estimation fine tune */
3817                 { 0x1f, 0x0003 },
3818                 { 0x09, 0xa20f },
3819                 { 0x1f, 0x0000 },
3820
3821                 /* Modify green table for giga & fnet */
3822                 { 0x1f, 0x0005 },
3823                 { 0x05, 0x8b55 },
3824                 { 0x06, 0x0000 },
3825                 { 0x05, 0x8b5e },
3826                 { 0x06, 0x0000 },
3827                 { 0x05, 0x8b67 },
3828                 { 0x06, 0x0000 },
3829                 { 0x05, 0x8b70 },
3830                 { 0x06, 0x0000 },
3831                 { 0x1f, 0x0000 },
3832                 { 0x1f, 0x0007 },
3833                 { 0x1e, 0x0078 },
3834                 { 0x17, 0x0000 },
3835                 { 0x19, 0x00aa },
3836                 { 0x1f, 0x0000 },
3837
3838                 /* Modify green table for 10M */
3839                 { 0x1f, 0x0005 },
3840                 { 0x05, 0x8b79 },
3841                 { 0x06, 0xaa00 },
3842                 { 0x1f, 0x0000 },
3843
3844                 /* Disable hiimpedance detection (RTCT) */
3845                 { 0x1f, 0x0003 },
3846                 { 0x01, 0x328a },
3847                 { 0x1f, 0x0000 }
3848         };
3849
3850
3851         rtl_apply_firmware(tp);
3852
3853         rtl8168f_hw_phy_config(tp);
3854
3855         /* Improve 2-pair detection performance */
3856         rtl_writephy(tp, 0x1f, 0x0005);
3857         rtl_writephy(tp, 0x05, 0x8b85);
3858         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3859         rtl_writephy(tp, 0x1f, 0x0000);
3860
3861         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3862
3863         /* Modify green table for giga */
3864         rtl_writephy(tp, 0x1f, 0x0005);
3865         rtl_writephy(tp, 0x05, 0x8b54);
3866         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3867         rtl_writephy(tp, 0x05, 0x8b5d);
3868         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3869         rtl_writephy(tp, 0x05, 0x8a7c);
3870         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3871         rtl_writephy(tp, 0x05, 0x8a7f);
3872         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3873         rtl_writephy(tp, 0x05, 0x8a82);
3874         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3875         rtl_writephy(tp, 0x05, 0x8a85);
3876         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3877         rtl_writephy(tp, 0x05, 0x8a88);
3878         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3879         rtl_writephy(tp, 0x1f, 0x0000);
3880
3881         /* uc same-seed solution */
3882         rtl_writephy(tp, 0x1f, 0x0005);
3883         rtl_writephy(tp, 0x05, 0x8b85);
3884         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3885         rtl_writephy(tp, 0x1f, 0x0000);
3886
3887         /* eee setting */
3888         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3889         rtl_writephy(tp, 0x1f, 0x0005);
3890         rtl_writephy(tp, 0x05, 0x8b85);
3891         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3892         rtl_writephy(tp, 0x1f, 0x0004);
3893         rtl_writephy(tp, 0x1f, 0x0007);
3894         rtl_writephy(tp, 0x1e, 0x0020);
3895         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3896         rtl_writephy(tp, 0x1f, 0x0000);
3897         rtl_writephy(tp, 0x0d, 0x0007);
3898         rtl_writephy(tp, 0x0e, 0x003c);
3899         rtl_writephy(tp, 0x0d, 0x4007);
3900         rtl_writephy(tp, 0x0e, 0x0000);
3901         rtl_writephy(tp, 0x0d, 0x0000);
3902
3903         /* Green feature */
3904         rtl_writephy(tp, 0x1f, 0x0003);
3905         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3906         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3907         rtl_writephy(tp, 0x1f, 0x0000);
3908 }
3909
3910 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3911 {
3912         rtl_apply_firmware(tp);
3913
3914         rtl_writephy(tp, 0x1f, 0x0a46);
3915         if (rtl_readphy(tp, 0x10) & 0x0100) {
3916                 rtl_writephy(tp, 0x1f, 0x0bcc);
3917                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3918         } else {
3919                 rtl_writephy(tp, 0x1f, 0x0bcc);
3920                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3921         }
3922
3923         rtl_writephy(tp, 0x1f, 0x0a46);
3924         if (rtl_readphy(tp, 0x13) & 0x0100) {
3925                 rtl_writephy(tp, 0x1f, 0x0c41);
3926                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3927         } else {
3928                 rtl_writephy(tp, 0x1f, 0x0c41);
3929                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3930         }
3931
3932         /* Enable PHY auto speed down */
3933         rtl_writephy(tp, 0x1f, 0x0a44);
3934         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3935
3936         rtl_writephy(tp, 0x1f, 0x0bcc);
3937         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3938         rtl_writephy(tp, 0x1f, 0x0a44);
3939         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3940         rtl_writephy(tp, 0x1f, 0x0a43);
3941         rtl_writephy(tp, 0x13, 0x8084);
3942         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3943         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3944
3945         /* EEE auto-fallback function */
3946         rtl_writephy(tp, 0x1f, 0x0a4b);
3947         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3948
3949         /* Enable UC LPF tune function */
3950         rtl_writephy(tp, 0x1f, 0x0a43);
3951         rtl_writephy(tp, 0x13, 0x8012);
3952         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3953
3954         rtl_writephy(tp, 0x1f, 0x0c42);
3955         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3956
3957         /* Improve SWR Efficiency */
3958         rtl_writephy(tp, 0x1f, 0x0bcd);
3959         rtl_writephy(tp, 0x14, 0x5065);
3960         rtl_writephy(tp, 0x14, 0xd065);
3961         rtl_writephy(tp, 0x1f, 0x0bc8);
3962         rtl_writephy(tp, 0x11, 0x5655);
3963         rtl_writephy(tp, 0x1f, 0x0bcd);
3964         rtl_writephy(tp, 0x14, 0x1065);
3965         rtl_writephy(tp, 0x14, 0x9065);
3966         rtl_writephy(tp, 0x14, 0x1065);
3967
3968         /* Check ALDPS bit, disable it if enabled */
3969         rtl_writephy(tp, 0x1f, 0x0a43);
3970         if (rtl_readphy(tp, 0x10) & 0x0004)
3971                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3972
3973         rtl_writephy(tp, 0x1f, 0x0000);
3974 }
3975
3976 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3977 {
3978         rtl_apply_firmware(tp);
3979 }
3980
3981 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3982 {
3983         u16 dout_tapbin;
3984         u32 data;
3985
3986         rtl_apply_firmware(tp);
3987
3988         /* CHN EST parameters adjust - giga master */
3989         rtl_writephy(tp, 0x1f, 0x0a43);
3990         rtl_writephy(tp, 0x13, 0x809b);
3991         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3992         rtl_writephy(tp, 0x13, 0x80a2);
3993         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3994         rtl_writephy(tp, 0x13, 0x80a4);
3995         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3996         rtl_writephy(tp, 0x13, 0x809c);
3997         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3998         rtl_writephy(tp, 0x1f, 0x0000);
3999
4000         /* CHN EST parameters adjust - giga slave */
4001         rtl_writephy(tp, 0x1f, 0x0a43);
4002         rtl_writephy(tp, 0x13, 0x80ad);
4003         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
4004         rtl_writephy(tp, 0x13, 0x80b4);
4005         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
4006         rtl_writephy(tp, 0x13, 0x80ac);
4007         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
4008         rtl_writephy(tp, 0x1f, 0x0000);
4009
4010         /* CHN EST parameters adjust - fnet */
4011         rtl_writephy(tp, 0x1f, 0x0a43);
4012         rtl_writephy(tp, 0x13, 0x808e);
4013         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
4014         rtl_writephy(tp, 0x13, 0x8090);
4015         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
4016         rtl_writephy(tp, 0x13, 0x8092);
4017         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
4018         rtl_writephy(tp, 0x1f, 0x0000);
4019
4020         /* enable R-tune & PGA-retune function */
4021         dout_tapbin = 0;
4022         rtl_writephy(tp, 0x1f, 0x0a46);
4023         data = rtl_readphy(tp, 0x13);
4024         data &= 3;
4025         data <<= 2;
4026         dout_tapbin |= data;
4027         data = rtl_readphy(tp, 0x12);
4028         data &= 0xc000;
4029         data >>= 14;
4030         dout_tapbin |= data;
4031         dout_tapbin = ~(dout_tapbin^0x08);
4032         dout_tapbin <<= 12;
4033         dout_tapbin &= 0xf000;
4034         rtl_writephy(tp, 0x1f, 0x0a43);
4035         rtl_writephy(tp, 0x13, 0x827a);
4036         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4037         rtl_writephy(tp, 0x13, 0x827b);
4038         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4039         rtl_writephy(tp, 0x13, 0x827c);
4040         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4041         rtl_writephy(tp, 0x13, 0x827d);
4042         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4043
4044         rtl_writephy(tp, 0x1f, 0x0a43);
4045         rtl_writephy(tp, 0x13, 0x0811);
4046         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4047         rtl_writephy(tp, 0x1f, 0x0a42);
4048         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4049         rtl_writephy(tp, 0x1f, 0x0000);
4050
4051         /* enable GPHY 10M */
4052         rtl_writephy(tp, 0x1f, 0x0a44);
4053         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4054         rtl_writephy(tp, 0x1f, 0x0000);
4055
4056         /* SAR ADC performance */
4057         rtl_writephy(tp, 0x1f, 0x0bca);
4058         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
4059         rtl_writephy(tp, 0x1f, 0x0000);
4060
4061         rtl_writephy(tp, 0x1f, 0x0a43);
4062         rtl_writephy(tp, 0x13, 0x803f);
4063         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4064         rtl_writephy(tp, 0x13, 0x8047);
4065         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4066         rtl_writephy(tp, 0x13, 0x804f);
4067         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4068         rtl_writephy(tp, 0x13, 0x8057);
4069         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4070         rtl_writephy(tp, 0x13, 0x805f);
4071         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4072         rtl_writephy(tp, 0x13, 0x8067);
4073         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4074         rtl_writephy(tp, 0x13, 0x806f);
4075         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4076         rtl_writephy(tp, 0x1f, 0x0000);
4077
4078         /* disable phy pfm mode */
4079         rtl_writephy(tp, 0x1f, 0x0a44);
4080         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4081         rtl_writephy(tp, 0x1f, 0x0000);
4082
4083         /* Check ALDPS bit, disable it if enabled */
4084         rtl_writephy(tp, 0x1f, 0x0a43);
4085         if (rtl_readphy(tp, 0x10) & 0x0004)
4086                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4087
4088         rtl_writephy(tp, 0x1f, 0x0000);
4089 }
4090
4091 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4092 {
4093         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4094         u16 rlen;
4095         u32 data;
4096
4097         rtl_apply_firmware(tp);
4098
4099         /* CHIN EST parameter update */
4100         rtl_writephy(tp, 0x1f, 0x0a43);
4101         rtl_writephy(tp, 0x13, 0x808a);
4102         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
4103         rtl_writephy(tp, 0x1f, 0x0000);
4104
4105         /* enable R-tune & PGA-retune function */
4106         rtl_writephy(tp, 0x1f, 0x0a43);
4107         rtl_writephy(tp, 0x13, 0x0811);
4108         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4109         rtl_writephy(tp, 0x1f, 0x0a42);
4110         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4111         rtl_writephy(tp, 0x1f, 0x0000);
4112
4113         /* enable GPHY 10M */
4114         rtl_writephy(tp, 0x1f, 0x0a44);
4115         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4116         rtl_writephy(tp, 0x1f, 0x0000);
4117
4118         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4119         data = r8168_mac_ocp_read(tp, 0xdd02);
4120         ioffset_p3 = ((data & 0x80)>>7);
4121         ioffset_p3 <<= 3;
4122
4123         data = r8168_mac_ocp_read(tp, 0xdd00);
4124         ioffset_p3 |= ((data & (0xe000))>>13);
4125         ioffset_p2 = ((data & (0x1e00))>>9);
4126         ioffset_p1 = ((data & (0x01e0))>>5);
4127         ioffset_p0 = ((data & 0x0010)>>4);
4128         ioffset_p0 <<= 3;
4129         ioffset_p0 |= (data & (0x07));
4130         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4131
4132         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
4133             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
4134                 rtl_writephy(tp, 0x1f, 0x0bcf);
4135                 rtl_writephy(tp, 0x16, data);
4136                 rtl_writephy(tp, 0x1f, 0x0000);
4137         }
4138
4139         /* Modify rlen (TX LPF corner frequency) level */
4140         rtl_writephy(tp, 0x1f, 0x0bcd);
4141         data = rtl_readphy(tp, 0x16);
4142         data &= 0x000f;
4143         rlen = 0;
4144         if (data > 3)
4145                 rlen = data - 3;
4146         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4147         rtl_writephy(tp, 0x17, data);
4148         rtl_writephy(tp, 0x1f, 0x0bcd);
4149         rtl_writephy(tp, 0x1f, 0x0000);
4150
4151         /* disable phy pfm mode */
4152         rtl_writephy(tp, 0x1f, 0x0a44);
4153         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4154         rtl_writephy(tp, 0x1f, 0x0000);
4155
4156         /* Check ALDPS bit, disable it if enabled */
4157         rtl_writephy(tp, 0x1f, 0x0a43);
4158         if (rtl_readphy(tp, 0x10) & 0x0004)
4159                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4160
4161         rtl_writephy(tp, 0x1f, 0x0000);
4162 }
4163
4164 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4165 {
4166         /* Enable PHY auto speed down */
4167         rtl_writephy(tp, 0x1f, 0x0a44);
4168         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4169         rtl_writephy(tp, 0x1f, 0x0000);
4170
4171         /* patch 10M & ALDPS */
4172         rtl_writephy(tp, 0x1f, 0x0bcc);
4173         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4174         rtl_writephy(tp, 0x1f, 0x0a44);
4175         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4176         rtl_writephy(tp, 0x1f, 0x0a43);
4177         rtl_writephy(tp, 0x13, 0x8084);
4178         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4179         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4180         rtl_writephy(tp, 0x1f, 0x0000);
4181
4182         /* Enable EEE auto-fallback function */
4183         rtl_writephy(tp, 0x1f, 0x0a4b);
4184         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4185         rtl_writephy(tp, 0x1f, 0x0000);
4186
4187         /* Enable UC LPF tune function */
4188         rtl_writephy(tp, 0x1f, 0x0a43);
4189         rtl_writephy(tp, 0x13, 0x8012);
4190         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4191         rtl_writephy(tp, 0x1f, 0x0000);
4192
4193         /* set rg_sel_sdm_rate */
4194         rtl_writephy(tp, 0x1f, 0x0c42);
4195         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4196         rtl_writephy(tp, 0x1f, 0x0000);
4197
4198         /* Check ALDPS bit, disable it if enabled */
4199         rtl_writephy(tp, 0x1f, 0x0a43);
4200         if (rtl_readphy(tp, 0x10) & 0x0004)
4201                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4202
4203         rtl_writephy(tp, 0x1f, 0x0000);
4204 }
4205
4206 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4207 {
4208         /* patch 10M & ALDPS */
4209         rtl_writephy(tp, 0x1f, 0x0bcc);
4210         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4211         rtl_writephy(tp, 0x1f, 0x0a44);
4212         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4213         rtl_writephy(tp, 0x1f, 0x0a43);
4214         rtl_writephy(tp, 0x13, 0x8084);
4215         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4216         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4217         rtl_writephy(tp, 0x1f, 0x0000);
4218
4219         /* Enable UC LPF tune function */
4220         rtl_writephy(tp, 0x1f, 0x0a43);
4221         rtl_writephy(tp, 0x13, 0x8012);
4222         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4223         rtl_writephy(tp, 0x1f, 0x0000);
4224
4225         /* Set rg_sel_sdm_rate */
4226         rtl_writephy(tp, 0x1f, 0x0c42);
4227         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4228         rtl_writephy(tp, 0x1f, 0x0000);
4229
4230         /* Channel estimation parameters */
4231         rtl_writephy(tp, 0x1f, 0x0a43);
4232         rtl_writephy(tp, 0x13, 0x80f3);
4233         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4234         rtl_writephy(tp, 0x13, 0x80f0);
4235         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4236         rtl_writephy(tp, 0x13, 0x80ef);
4237         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4238         rtl_writephy(tp, 0x13, 0x80f6);
4239         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4240         rtl_writephy(tp, 0x13, 0x80ec);
4241         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4242         rtl_writephy(tp, 0x13, 0x80ed);
4243         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4244         rtl_writephy(tp, 0x13, 0x80f2);
4245         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4246         rtl_writephy(tp, 0x13, 0x80f4);
4247         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4248         rtl_writephy(tp, 0x1f, 0x0a43);
4249         rtl_writephy(tp, 0x13, 0x8110);
4250         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4251         rtl_writephy(tp, 0x13, 0x810f);
4252         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4253         rtl_writephy(tp, 0x13, 0x8111);
4254         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4255         rtl_writephy(tp, 0x13, 0x8113);
4256         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4257         rtl_writephy(tp, 0x13, 0x8115);
4258         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4259         rtl_writephy(tp, 0x13, 0x810e);
4260         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4261         rtl_writephy(tp, 0x13, 0x810c);
4262         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4263         rtl_writephy(tp, 0x13, 0x810b);
4264         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4265         rtl_writephy(tp, 0x1f, 0x0a43);
4266         rtl_writephy(tp, 0x13, 0x80d1);
4267         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4268         rtl_writephy(tp, 0x13, 0x80cd);
4269         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4270         rtl_writephy(tp, 0x13, 0x80d3);
4271         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4272         rtl_writephy(tp, 0x13, 0x80d5);
4273         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4274         rtl_writephy(tp, 0x13, 0x80d7);
4275         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4276
4277         /* Force PWM-mode */
4278         rtl_writephy(tp, 0x1f, 0x0bcd);
4279         rtl_writephy(tp, 0x14, 0x5065);
4280         rtl_writephy(tp, 0x14, 0xd065);
4281         rtl_writephy(tp, 0x1f, 0x0bc8);
4282         rtl_writephy(tp, 0x12, 0x00ed);
4283         rtl_writephy(tp, 0x1f, 0x0bcd);
4284         rtl_writephy(tp, 0x14, 0x1065);
4285         rtl_writephy(tp, 0x14, 0x9065);
4286         rtl_writephy(tp, 0x14, 0x1065);
4287         rtl_writephy(tp, 0x1f, 0x0000);
4288
4289         /* Check ALDPS bit, disable it if enabled */
4290         rtl_writephy(tp, 0x1f, 0x0a43);
4291         if (rtl_readphy(tp, 0x10) & 0x0004)
4292                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4293
4294         rtl_writephy(tp, 0x1f, 0x0000);
4295 }
4296
4297 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4298 {
4299         static const struct phy_reg phy_reg_init[] = {
4300                 { 0x1f, 0x0003 },
4301                 { 0x08, 0x441d },
4302                 { 0x01, 0x9100 },
4303                 { 0x1f, 0x0000 }
4304         };
4305
4306         rtl_writephy(tp, 0x1f, 0x0000);
4307         rtl_patchphy(tp, 0x11, 1 << 12);
4308         rtl_patchphy(tp, 0x19, 1 << 13);
4309         rtl_patchphy(tp, 0x10, 1 << 15);
4310
4311         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4312 }
4313
4314 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4315 {
4316         static const struct phy_reg phy_reg_init[] = {
4317                 { 0x1f, 0x0005 },
4318                 { 0x1a, 0x0000 },
4319                 { 0x1f, 0x0000 },
4320
4321                 { 0x1f, 0x0004 },
4322                 { 0x1c, 0x0000 },
4323                 { 0x1f, 0x0000 },
4324
4325                 { 0x1f, 0x0001 },
4326                 { 0x15, 0x7701 },
4327                 { 0x1f, 0x0000 }
4328         };
4329
4330         /* Disable ALDPS before ram code */
4331         rtl_writephy(tp, 0x1f, 0x0000);
4332         rtl_writephy(tp, 0x18, 0x0310);
4333         msleep(100);
4334
4335         rtl_apply_firmware(tp);
4336
4337         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4338 }
4339
4340 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4341 {
4342         /* Disable ALDPS before setting firmware */
4343         rtl_writephy(tp, 0x1f, 0x0000);
4344         rtl_writephy(tp, 0x18, 0x0310);
4345         msleep(20);
4346
4347         rtl_apply_firmware(tp);
4348
4349         /* EEE setting */
4350         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4351         rtl_writephy(tp, 0x1f, 0x0004);
4352         rtl_writephy(tp, 0x10, 0x401f);
4353         rtl_writephy(tp, 0x19, 0x7030);
4354         rtl_writephy(tp, 0x1f, 0x0000);
4355 }
4356
4357 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4358 {
4359         static const struct phy_reg phy_reg_init[] = {
4360                 { 0x1f, 0x0004 },
4361                 { 0x10, 0xc07f },
4362                 { 0x19, 0x7030 },
4363                 { 0x1f, 0x0000 }
4364         };
4365
4366         /* Disable ALDPS before ram code */
4367         rtl_writephy(tp, 0x1f, 0x0000);
4368         rtl_writephy(tp, 0x18, 0x0310);
4369         msleep(100);
4370
4371         rtl_apply_firmware(tp);
4372
4373         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4374         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4375
4376         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4377 }
4378
4379 static void rtl_hw_phy_config(struct net_device *dev)
4380 {
4381         struct rtl8169_private *tp = netdev_priv(dev);
4382
4383         rtl8169_print_mac_version(tp);
4384
4385         switch (tp->mac_version) {
4386         case RTL_GIGA_MAC_VER_01:
4387                 break;
4388         case RTL_GIGA_MAC_VER_02:
4389         case RTL_GIGA_MAC_VER_03:
4390                 rtl8169s_hw_phy_config(tp);
4391                 break;
4392         case RTL_GIGA_MAC_VER_04:
4393                 rtl8169sb_hw_phy_config(tp);
4394                 break;
4395         case RTL_GIGA_MAC_VER_05:
4396                 rtl8169scd_hw_phy_config(tp);
4397                 break;
4398         case RTL_GIGA_MAC_VER_06:
4399                 rtl8169sce_hw_phy_config(tp);
4400                 break;
4401         case RTL_GIGA_MAC_VER_07:
4402         case RTL_GIGA_MAC_VER_08:
4403         case RTL_GIGA_MAC_VER_09:
4404                 rtl8102e_hw_phy_config(tp);
4405                 break;
4406         case RTL_GIGA_MAC_VER_11:
4407                 rtl8168bb_hw_phy_config(tp);
4408                 break;
4409         case RTL_GIGA_MAC_VER_12:
4410                 rtl8168bef_hw_phy_config(tp);
4411                 break;
4412         case RTL_GIGA_MAC_VER_17:
4413                 rtl8168bef_hw_phy_config(tp);
4414                 break;
4415         case RTL_GIGA_MAC_VER_18:
4416                 rtl8168cp_1_hw_phy_config(tp);
4417                 break;
4418         case RTL_GIGA_MAC_VER_19:
4419                 rtl8168c_1_hw_phy_config(tp);
4420                 break;
4421         case RTL_GIGA_MAC_VER_20:
4422                 rtl8168c_2_hw_phy_config(tp);
4423                 break;
4424         case RTL_GIGA_MAC_VER_21:
4425                 rtl8168c_3_hw_phy_config(tp);
4426                 break;
4427         case RTL_GIGA_MAC_VER_22:
4428                 rtl8168c_4_hw_phy_config(tp);
4429                 break;
4430         case RTL_GIGA_MAC_VER_23:
4431         case RTL_GIGA_MAC_VER_24:
4432                 rtl8168cp_2_hw_phy_config(tp);
4433                 break;
4434         case RTL_GIGA_MAC_VER_25:
4435                 rtl8168d_1_hw_phy_config(tp);
4436                 break;
4437         case RTL_GIGA_MAC_VER_26:
4438                 rtl8168d_2_hw_phy_config(tp);
4439                 break;
4440         case RTL_GIGA_MAC_VER_27:
4441                 rtl8168d_3_hw_phy_config(tp);
4442                 break;
4443         case RTL_GIGA_MAC_VER_28:
4444                 rtl8168d_4_hw_phy_config(tp);
4445                 break;
4446         case RTL_GIGA_MAC_VER_29:
4447         case RTL_GIGA_MAC_VER_30:
4448                 rtl8105e_hw_phy_config(tp);
4449                 break;
4450         case RTL_GIGA_MAC_VER_31:
4451                 /* None. */
4452                 break;
4453         case RTL_GIGA_MAC_VER_32:
4454         case RTL_GIGA_MAC_VER_33:
4455                 rtl8168e_1_hw_phy_config(tp);
4456                 break;
4457         case RTL_GIGA_MAC_VER_34:
4458                 rtl8168e_2_hw_phy_config(tp);
4459                 break;
4460         case RTL_GIGA_MAC_VER_35:
4461                 rtl8168f_1_hw_phy_config(tp);
4462                 break;
4463         case RTL_GIGA_MAC_VER_36:
4464                 rtl8168f_2_hw_phy_config(tp);
4465                 break;
4466
4467         case RTL_GIGA_MAC_VER_37:
4468                 rtl8402_hw_phy_config(tp);
4469                 break;
4470
4471         case RTL_GIGA_MAC_VER_38:
4472                 rtl8411_hw_phy_config(tp);
4473                 break;
4474
4475         case RTL_GIGA_MAC_VER_39:
4476                 rtl8106e_hw_phy_config(tp);
4477                 break;
4478
4479         case RTL_GIGA_MAC_VER_40:
4480                 rtl8168g_1_hw_phy_config(tp);
4481                 break;
4482         case RTL_GIGA_MAC_VER_42:
4483         case RTL_GIGA_MAC_VER_43:
4484         case RTL_GIGA_MAC_VER_44:
4485                 rtl8168g_2_hw_phy_config(tp);
4486                 break;
4487         case RTL_GIGA_MAC_VER_45:
4488         case RTL_GIGA_MAC_VER_47:
4489                 rtl8168h_1_hw_phy_config(tp);
4490                 break;
4491         case RTL_GIGA_MAC_VER_46:
4492         case RTL_GIGA_MAC_VER_48:
4493                 rtl8168h_2_hw_phy_config(tp);
4494                 break;
4495
4496         case RTL_GIGA_MAC_VER_49:
4497                 rtl8168ep_1_hw_phy_config(tp);
4498                 break;
4499         case RTL_GIGA_MAC_VER_50:
4500         case RTL_GIGA_MAC_VER_51:
4501                 rtl8168ep_2_hw_phy_config(tp);
4502                 break;
4503
4504         case RTL_GIGA_MAC_VER_41:
4505         default:
4506                 break;
4507         }
4508 }
4509
4510 static void rtl_phy_work(struct rtl8169_private *tp)
4511 {
4512         struct timer_list *timer = &tp->timer;
4513         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4514
4515         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4516
4517         if (tp->phy_reset_pending(tp)) {
4518                 /*
4519                  * A busy loop could burn quite a few cycles on nowadays CPU.
4520                  * Let's delay the execution of the timer for a few ticks.
4521                  */
4522                 timeout = HZ/10;
4523                 goto out_mod_timer;
4524         }
4525
4526         if (tp->link_ok(tp))
4527                 return;
4528
4529         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4530
4531         tp->phy_reset_enable(tp);
4532
4533 out_mod_timer:
4534         mod_timer(timer, jiffies + timeout);
4535 }
4536
4537 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4538 {
4539         if (!test_and_set_bit(flag, tp->wk.flags))
4540                 schedule_work(&tp->wk.work);
4541 }
4542
4543 static void rtl8169_phy_timer(struct timer_list *t)
4544 {
4545         struct rtl8169_private *tp = from_timer(tp, t, timer);
4546
4547         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4548 }
4549
4550 DECLARE_RTL_COND(rtl_phy_reset_cond)
4551 {
4552         return tp->phy_reset_pending(tp);
4553 }
4554
4555 static void rtl8169_phy_reset(struct net_device *dev,
4556                               struct rtl8169_private *tp)
4557 {
4558         tp->phy_reset_enable(tp);
4559         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4560 }
4561
4562 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4563 {
4564         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4565             (RTL_R8(tp, PHYstatus) & TBI_Enable);
4566 }
4567
4568 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4569 {
4570         rtl_hw_phy_config(dev);
4571
4572         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4573                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4574                 RTL_W8(tp, 0x82, 0x01);
4575         }
4576
4577         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4578
4579         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4580                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4581
4582         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4583                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4584                 RTL_W8(tp, 0x82, 0x01);
4585                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4586                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4587         }
4588
4589         rtl8169_phy_reset(dev, tp);
4590
4591         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4592                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4593                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4594                           (tp->mii.supports_gmii ?
4595                            ADVERTISED_1000baseT_Half |
4596                            ADVERTISED_1000baseT_Full : 0));
4597
4598         if (rtl_tbi_enabled(tp))
4599                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4600 }
4601
4602 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4603 {
4604         rtl_lock_work(tp);
4605
4606         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4607
4608         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4609         RTL_R32(tp, MAC4);
4610
4611         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4612         RTL_R32(tp, MAC0);
4613
4614         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4615                 rtl_rar_exgmac_set(tp, addr);
4616
4617         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4618
4619         rtl_unlock_work(tp);
4620 }
4621
4622 static int rtl_set_mac_address(struct net_device *dev, void *p)
4623 {
4624         struct rtl8169_private *tp = netdev_priv(dev);
4625         struct device *d = tp_to_dev(tp);
4626         int ret;
4627
4628         ret = eth_mac_addr(dev, p);
4629         if (ret)
4630                 return ret;
4631
4632         pm_runtime_get_noresume(d);
4633
4634         if (pm_runtime_active(d))
4635                 rtl_rar_set(tp, dev->dev_addr);
4636
4637         pm_runtime_put_noidle(d);
4638
4639         return 0;
4640 }
4641
4642 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4643 {
4644         struct rtl8169_private *tp = netdev_priv(dev);
4645         struct mii_ioctl_data *data = if_mii(ifr);
4646
4647         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4648 }
4649
4650 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4651                           struct mii_ioctl_data *data, int cmd)
4652 {
4653         switch (cmd) {
4654         case SIOCGMIIPHY:
4655                 data->phy_id = 32; /* Internal PHY */
4656                 return 0;
4657
4658         case SIOCGMIIREG:
4659                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4660                 return 0;
4661
4662         case SIOCSMIIREG:
4663                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4664                 return 0;
4665         }
4666         return -EOPNOTSUPP;
4667 }
4668
4669 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4670 {
4671         return -EOPNOTSUPP;
4672 }
4673
4674 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4675 {
4676         struct mdio_ops *ops = &tp->mdio_ops;
4677
4678         switch (tp->mac_version) {
4679         case RTL_GIGA_MAC_VER_27:
4680                 ops->write      = r8168dp_1_mdio_write;
4681                 ops->read       = r8168dp_1_mdio_read;
4682                 break;
4683         case RTL_GIGA_MAC_VER_28:
4684         case RTL_GIGA_MAC_VER_31:
4685                 ops->write      = r8168dp_2_mdio_write;
4686                 ops->read       = r8168dp_2_mdio_read;
4687                 break;
4688         case RTL_GIGA_MAC_VER_40:
4689         case RTL_GIGA_MAC_VER_41:
4690         case RTL_GIGA_MAC_VER_42:
4691         case RTL_GIGA_MAC_VER_43:
4692         case RTL_GIGA_MAC_VER_44:
4693         case RTL_GIGA_MAC_VER_45:
4694         case RTL_GIGA_MAC_VER_46:
4695         case RTL_GIGA_MAC_VER_47:
4696         case RTL_GIGA_MAC_VER_48:
4697         case RTL_GIGA_MAC_VER_49:
4698         case RTL_GIGA_MAC_VER_50:
4699         case RTL_GIGA_MAC_VER_51:
4700                 ops->write      = r8168g_mdio_write;
4701                 ops->read       = r8168g_mdio_read;
4702                 break;
4703         default:
4704                 ops->write      = r8169_mdio_write;
4705                 ops->read       = r8169_mdio_read;
4706                 break;
4707         }
4708 }
4709
4710 static void rtl_speed_down(struct rtl8169_private *tp)
4711 {
4712         u32 adv;
4713         int lpa;
4714
4715         rtl_writephy(tp, 0x1f, 0x0000);
4716         lpa = rtl_readphy(tp, MII_LPA);
4717
4718         if (lpa & (LPA_10HALF | LPA_10FULL))
4719                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4720         else if (lpa & (LPA_100HALF | LPA_100FULL))
4721                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4722                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4723         else
4724                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4725                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4726                       (tp->mii.supports_gmii ?
4727                        ADVERTISED_1000baseT_Half |
4728                        ADVERTISED_1000baseT_Full : 0);
4729
4730         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4731                           adv);
4732 }
4733
4734 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4735 {
4736         switch (tp->mac_version) {
4737         case RTL_GIGA_MAC_VER_25:
4738         case RTL_GIGA_MAC_VER_26:
4739         case RTL_GIGA_MAC_VER_29:
4740         case RTL_GIGA_MAC_VER_30:
4741         case RTL_GIGA_MAC_VER_32:
4742         case RTL_GIGA_MAC_VER_33:
4743         case RTL_GIGA_MAC_VER_34:
4744         case RTL_GIGA_MAC_VER_37:
4745         case RTL_GIGA_MAC_VER_38:
4746         case RTL_GIGA_MAC_VER_39:
4747         case RTL_GIGA_MAC_VER_40:
4748         case RTL_GIGA_MAC_VER_41:
4749         case RTL_GIGA_MAC_VER_42:
4750         case RTL_GIGA_MAC_VER_43:
4751         case RTL_GIGA_MAC_VER_44:
4752         case RTL_GIGA_MAC_VER_45:
4753         case RTL_GIGA_MAC_VER_46:
4754         case RTL_GIGA_MAC_VER_47:
4755         case RTL_GIGA_MAC_VER_48:
4756         case RTL_GIGA_MAC_VER_49:
4757         case RTL_GIGA_MAC_VER_50:
4758         case RTL_GIGA_MAC_VER_51:
4759                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4760                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4761                 break;
4762         default:
4763                 break;
4764         }
4765 }
4766
4767 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4768 {
4769         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4770                 return false;
4771
4772         rtl_speed_down(tp);
4773         rtl_wol_suspend_quirk(tp);
4774
4775         return true;
4776 }
4777
4778 static void r810x_phy_power_down(struct rtl8169_private *tp)
4779 {
4780         rtl_writephy(tp, 0x1f, 0x0000);
4781         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4782 }
4783
4784 static void r810x_phy_power_up(struct rtl8169_private *tp)
4785 {
4786         rtl_writephy(tp, 0x1f, 0x0000);
4787         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4788 }
4789
4790 static void r810x_pll_power_down(struct rtl8169_private *tp)
4791 {
4792         if (rtl_wol_pll_power_down(tp))
4793                 return;
4794
4795         r810x_phy_power_down(tp);
4796
4797         switch (tp->mac_version) {
4798         case RTL_GIGA_MAC_VER_07:
4799         case RTL_GIGA_MAC_VER_08:
4800         case RTL_GIGA_MAC_VER_09:
4801         case RTL_GIGA_MAC_VER_10:
4802         case RTL_GIGA_MAC_VER_13:
4803         case RTL_GIGA_MAC_VER_16:
4804                 break;
4805         default:
4806                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4807                 break;
4808         }
4809 }
4810
4811 static void r810x_pll_power_up(struct rtl8169_private *tp)
4812 {
4813         r810x_phy_power_up(tp);
4814
4815         switch (tp->mac_version) {
4816         case RTL_GIGA_MAC_VER_07:
4817         case RTL_GIGA_MAC_VER_08:
4818         case RTL_GIGA_MAC_VER_09:
4819         case RTL_GIGA_MAC_VER_10:
4820         case RTL_GIGA_MAC_VER_13:
4821         case RTL_GIGA_MAC_VER_16:
4822                 break;
4823         case RTL_GIGA_MAC_VER_47:
4824         case RTL_GIGA_MAC_VER_48:
4825                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4826                 break;
4827         default:
4828                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4829                 break;
4830         }
4831 }
4832
4833 static void r8168_phy_power_up(struct rtl8169_private *tp)
4834 {
4835         rtl_writephy(tp, 0x1f, 0x0000);
4836         switch (tp->mac_version) {
4837         case RTL_GIGA_MAC_VER_11:
4838         case RTL_GIGA_MAC_VER_12:
4839         case RTL_GIGA_MAC_VER_17:
4840         case RTL_GIGA_MAC_VER_18:
4841         case RTL_GIGA_MAC_VER_19:
4842         case RTL_GIGA_MAC_VER_20:
4843         case RTL_GIGA_MAC_VER_21:
4844         case RTL_GIGA_MAC_VER_22:
4845         case RTL_GIGA_MAC_VER_23:
4846         case RTL_GIGA_MAC_VER_24:
4847         case RTL_GIGA_MAC_VER_25:
4848         case RTL_GIGA_MAC_VER_26:
4849         case RTL_GIGA_MAC_VER_27:
4850         case RTL_GIGA_MAC_VER_28:
4851         case RTL_GIGA_MAC_VER_31:
4852                 rtl_writephy(tp, 0x0e, 0x0000);
4853                 break;
4854         default:
4855                 break;
4856         }
4857         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4858 }
4859
4860 static void r8168_phy_power_down(struct rtl8169_private *tp)
4861 {
4862         rtl_writephy(tp, 0x1f, 0x0000);
4863         switch (tp->mac_version) {
4864         case RTL_GIGA_MAC_VER_32:
4865         case RTL_GIGA_MAC_VER_33:
4866         case RTL_GIGA_MAC_VER_40:
4867         case RTL_GIGA_MAC_VER_41:
4868                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4869                 break;
4870
4871         case RTL_GIGA_MAC_VER_11:
4872         case RTL_GIGA_MAC_VER_12:
4873         case RTL_GIGA_MAC_VER_17:
4874         case RTL_GIGA_MAC_VER_18:
4875         case RTL_GIGA_MAC_VER_19:
4876         case RTL_GIGA_MAC_VER_20:
4877         case RTL_GIGA_MAC_VER_21:
4878         case RTL_GIGA_MAC_VER_22:
4879         case RTL_GIGA_MAC_VER_23:
4880         case RTL_GIGA_MAC_VER_24:
4881         case RTL_GIGA_MAC_VER_25:
4882         case RTL_GIGA_MAC_VER_26:
4883         case RTL_GIGA_MAC_VER_27:
4884         case RTL_GIGA_MAC_VER_28:
4885         case RTL_GIGA_MAC_VER_31:
4886                 rtl_writephy(tp, 0x0e, 0x0200);
4887         default:
4888                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4889                 break;
4890         }
4891 }
4892
4893 static void r8168_pll_power_down(struct rtl8169_private *tp)
4894 {
4895         if (r8168_check_dash(tp))
4896                 return;
4897
4898         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4899              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4900             (RTL_R16(tp, CPlusCmd) & ASF)) {
4901                 return;
4902         }
4903
4904         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4905             tp->mac_version == RTL_GIGA_MAC_VER_33)
4906                 rtl_ephy_write(tp, 0x19, 0xff64);
4907
4908         if (rtl_wol_pll_power_down(tp))
4909                 return;
4910
4911         r8168_phy_power_down(tp);
4912
4913         switch (tp->mac_version) {
4914         case RTL_GIGA_MAC_VER_25:
4915         case RTL_GIGA_MAC_VER_26:
4916         case RTL_GIGA_MAC_VER_27:
4917         case RTL_GIGA_MAC_VER_28:
4918         case RTL_GIGA_MAC_VER_31:
4919         case RTL_GIGA_MAC_VER_32:
4920         case RTL_GIGA_MAC_VER_33:
4921         case RTL_GIGA_MAC_VER_44:
4922         case RTL_GIGA_MAC_VER_45:
4923         case RTL_GIGA_MAC_VER_46:
4924         case RTL_GIGA_MAC_VER_50:
4925         case RTL_GIGA_MAC_VER_51:
4926                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4927                 break;
4928         case RTL_GIGA_MAC_VER_40:
4929         case RTL_GIGA_MAC_VER_41:
4930         case RTL_GIGA_MAC_VER_49:
4931                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4932                              0xfc000000, ERIAR_EXGMAC);
4933                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4934                 break;
4935         }
4936 }
4937
4938 static void r8168_pll_power_up(struct rtl8169_private *tp)
4939 {
4940         switch (tp->mac_version) {
4941         case RTL_GIGA_MAC_VER_25:
4942         case RTL_GIGA_MAC_VER_26:
4943         case RTL_GIGA_MAC_VER_27:
4944         case RTL_GIGA_MAC_VER_28:
4945         case RTL_GIGA_MAC_VER_31:
4946         case RTL_GIGA_MAC_VER_32:
4947         case RTL_GIGA_MAC_VER_33:
4948                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4949                 break;
4950         case RTL_GIGA_MAC_VER_44:
4951         case RTL_GIGA_MAC_VER_45:
4952         case RTL_GIGA_MAC_VER_46:
4953         case RTL_GIGA_MAC_VER_50:
4954         case RTL_GIGA_MAC_VER_51:
4955                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4956                 break;
4957         case RTL_GIGA_MAC_VER_40:
4958         case RTL_GIGA_MAC_VER_41:
4959         case RTL_GIGA_MAC_VER_49:
4960                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4961                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4962                              0x00000000, ERIAR_EXGMAC);
4963                 break;
4964         }
4965
4966         r8168_phy_power_up(tp);
4967 }
4968
4969 static void rtl_generic_op(struct rtl8169_private *tp,
4970                            void (*op)(struct rtl8169_private *))
4971 {
4972         if (op)
4973                 op(tp);
4974 }
4975
4976 static void rtl_pll_power_down(struct rtl8169_private *tp)
4977 {
4978         rtl_generic_op(tp, tp->pll_power_ops.down);
4979 }
4980
4981 static void rtl_pll_power_up(struct rtl8169_private *tp)
4982 {
4983         rtl_generic_op(tp, tp->pll_power_ops.up);
4984 }
4985
4986 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4987 {
4988         struct pll_power_ops *ops = &tp->pll_power_ops;
4989
4990         switch (tp->mac_version) {
4991         case RTL_GIGA_MAC_VER_07:
4992         case RTL_GIGA_MAC_VER_08:
4993         case RTL_GIGA_MAC_VER_09:
4994         case RTL_GIGA_MAC_VER_10:
4995         case RTL_GIGA_MAC_VER_16:
4996         case RTL_GIGA_MAC_VER_29:
4997         case RTL_GIGA_MAC_VER_30:
4998         case RTL_GIGA_MAC_VER_37:
4999         case RTL_GIGA_MAC_VER_39:
5000         case RTL_GIGA_MAC_VER_43:
5001         case RTL_GIGA_MAC_VER_47:
5002         case RTL_GIGA_MAC_VER_48:
5003                 ops->down       = r810x_pll_power_down;
5004                 ops->up         = r810x_pll_power_up;
5005                 break;
5006
5007         case RTL_GIGA_MAC_VER_11:
5008         case RTL_GIGA_MAC_VER_12:
5009         case RTL_GIGA_MAC_VER_17:
5010         case RTL_GIGA_MAC_VER_18:
5011         case RTL_GIGA_MAC_VER_19:
5012         case RTL_GIGA_MAC_VER_20:
5013         case RTL_GIGA_MAC_VER_21:
5014         case RTL_GIGA_MAC_VER_22:
5015         case RTL_GIGA_MAC_VER_23:
5016         case RTL_GIGA_MAC_VER_24:
5017         case RTL_GIGA_MAC_VER_25:
5018         case RTL_GIGA_MAC_VER_26:
5019         case RTL_GIGA_MAC_VER_27:
5020         case RTL_GIGA_MAC_VER_28:
5021         case RTL_GIGA_MAC_VER_31:
5022         case RTL_GIGA_MAC_VER_32:
5023         case RTL_GIGA_MAC_VER_33:
5024         case RTL_GIGA_MAC_VER_34:
5025         case RTL_GIGA_MAC_VER_35:
5026         case RTL_GIGA_MAC_VER_36:
5027         case RTL_GIGA_MAC_VER_38:
5028         case RTL_GIGA_MAC_VER_40:
5029         case RTL_GIGA_MAC_VER_41:
5030         case RTL_GIGA_MAC_VER_42:
5031         case RTL_GIGA_MAC_VER_44:
5032         case RTL_GIGA_MAC_VER_45:
5033         case RTL_GIGA_MAC_VER_46:
5034         case RTL_GIGA_MAC_VER_49:
5035         case RTL_GIGA_MAC_VER_50:
5036         case RTL_GIGA_MAC_VER_51:
5037                 ops->down       = r8168_pll_power_down;
5038                 ops->up         = r8168_pll_power_up;
5039                 break;
5040
5041         default:
5042                 ops->down       = NULL;
5043                 ops->up         = NULL;
5044                 break;
5045         }
5046 }
5047
5048 static void rtl_init_rxcfg(struct rtl8169_private *tp)
5049 {
5050         switch (tp->mac_version) {
5051         case RTL_GIGA_MAC_VER_01:
5052         case RTL_GIGA_MAC_VER_02:
5053         case RTL_GIGA_MAC_VER_03:
5054         case RTL_GIGA_MAC_VER_04:
5055         case RTL_GIGA_MAC_VER_05:
5056         case RTL_GIGA_MAC_VER_06:
5057         case RTL_GIGA_MAC_VER_10:
5058         case RTL_GIGA_MAC_VER_11:
5059         case RTL_GIGA_MAC_VER_12:
5060         case RTL_GIGA_MAC_VER_13:
5061         case RTL_GIGA_MAC_VER_14:
5062         case RTL_GIGA_MAC_VER_15:
5063         case RTL_GIGA_MAC_VER_16:
5064         case RTL_GIGA_MAC_VER_17:
5065                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5066                 break;
5067         case RTL_GIGA_MAC_VER_18:
5068         case RTL_GIGA_MAC_VER_19:
5069         case RTL_GIGA_MAC_VER_20:
5070         case RTL_GIGA_MAC_VER_21:
5071         case RTL_GIGA_MAC_VER_22:
5072         case RTL_GIGA_MAC_VER_23:
5073         case RTL_GIGA_MAC_VER_24:
5074         case RTL_GIGA_MAC_VER_34:
5075         case RTL_GIGA_MAC_VER_35:
5076                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5077                 break;
5078         case RTL_GIGA_MAC_VER_40:
5079         case RTL_GIGA_MAC_VER_41:
5080         case RTL_GIGA_MAC_VER_42:
5081         case RTL_GIGA_MAC_VER_43:
5082         case RTL_GIGA_MAC_VER_44:
5083         case RTL_GIGA_MAC_VER_45:
5084         case RTL_GIGA_MAC_VER_46:
5085         case RTL_GIGA_MAC_VER_47:
5086         case RTL_GIGA_MAC_VER_48:
5087         case RTL_GIGA_MAC_VER_49:
5088         case RTL_GIGA_MAC_VER_50:
5089         case RTL_GIGA_MAC_VER_51:
5090                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
5091                 break;
5092         default:
5093                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
5094                 break;
5095         }
5096 }
5097
5098 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5099 {
5100         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5101 }
5102
5103 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5104 {
5105         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5106         rtl_generic_op(tp, tp->jumbo_ops.enable);
5107         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5108 }
5109
5110 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5111 {
5112         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5113         rtl_generic_op(tp, tp->jumbo_ops.disable);
5114         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5115 }
5116
5117 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5118 {
5119         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5120         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
5121         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
5122 }
5123
5124 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5125 {
5126         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5127         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
5128         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5129 }
5130
5131 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5132 {
5133         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5134 }
5135
5136 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5137 {
5138         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5139 }
5140
5141 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5142 {
5143         RTL_W8(tp, MaxTxPacketSize, 0x3f);
5144         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5145         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
5146         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
5147 }
5148
5149 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5150 {
5151         RTL_W8(tp, MaxTxPacketSize, 0x0c);
5152         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5153         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
5154         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5155 }
5156
5157 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5158 {
5159         rtl_tx_performance_tweak(tp,
5160                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5161 }
5162
5163 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5164 {
5165         rtl_tx_performance_tweak(tp,
5166                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5167 }
5168
5169 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5170 {
5171         r8168b_0_hw_jumbo_enable(tp);
5172
5173         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
5174 }
5175
5176 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5177 {
5178         r8168b_0_hw_jumbo_disable(tp);
5179
5180         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5181 }
5182
5183 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5184 {
5185         struct jumbo_ops *ops = &tp->jumbo_ops;
5186
5187         switch (tp->mac_version) {
5188         case RTL_GIGA_MAC_VER_11:
5189                 ops->disable    = r8168b_0_hw_jumbo_disable;
5190                 ops->enable     = r8168b_0_hw_jumbo_enable;
5191                 break;
5192         case RTL_GIGA_MAC_VER_12:
5193         case RTL_GIGA_MAC_VER_17:
5194                 ops->disable    = r8168b_1_hw_jumbo_disable;
5195                 ops->enable     = r8168b_1_hw_jumbo_enable;
5196                 break;
5197         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5198         case RTL_GIGA_MAC_VER_19:
5199         case RTL_GIGA_MAC_VER_20:
5200         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5201         case RTL_GIGA_MAC_VER_22:
5202         case RTL_GIGA_MAC_VER_23:
5203         case RTL_GIGA_MAC_VER_24:
5204         case RTL_GIGA_MAC_VER_25:
5205         case RTL_GIGA_MAC_VER_26:
5206                 ops->disable    = r8168c_hw_jumbo_disable;
5207                 ops->enable     = r8168c_hw_jumbo_enable;
5208                 break;
5209         case RTL_GIGA_MAC_VER_27:
5210         case RTL_GIGA_MAC_VER_28:
5211                 ops->disable    = r8168dp_hw_jumbo_disable;
5212                 ops->enable     = r8168dp_hw_jumbo_enable;
5213                 break;
5214         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5215         case RTL_GIGA_MAC_VER_32:
5216         case RTL_GIGA_MAC_VER_33:
5217         case RTL_GIGA_MAC_VER_34:
5218                 ops->disable    = r8168e_hw_jumbo_disable;
5219                 ops->enable     = r8168e_hw_jumbo_enable;
5220                 break;
5221
5222         /*
5223          * No action needed for jumbo frames with 8169.
5224          * No jumbo for 810x at all.
5225          */
5226         case RTL_GIGA_MAC_VER_40:
5227         case RTL_GIGA_MAC_VER_41:
5228         case RTL_GIGA_MAC_VER_42:
5229         case RTL_GIGA_MAC_VER_43:
5230         case RTL_GIGA_MAC_VER_44:
5231         case RTL_GIGA_MAC_VER_45:
5232         case RTL_GIGA_MAC_VER_46:
5233         case RTL_GIGA_MAC_VER_47:
5234         case RTL_GIGA_MAC_VER_48:
5235         case RTL_GIGA_MAC_VER_49:
5236         case RTL_GIGA_MAC_VER_50:
5237         case RTL_GIGA_MAC_VER_51:
5238         default:
5239                 ops->disable    = NULL;
5240                 ops->enable     = NULL;
5241                 break;
5242         }
5243 }
5244
5245 DECLARE_RTL_COND(rtl_chipcmd_cond)
5246 {
5247         return RTL_R8(tp, ChipCmd) & CmdReset;
5248 }
5249
5250 static void rtl_hw_reset(struct rtl8169_private *tp)
5251 {
5252         RTL_W8(tp, ChipCmd, CmdReset);
5253
5254         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5255 }
5256
5257 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5258 {
5259         struct rtl_fw *rtl_fw;
5260         const char *name;
5261         int rc = -ENOMEM;
5262
5263         name = rtl_lookup_firmware_name(tp);
5264         if (!name)
5265                 goto out_no_firmware;
5266
5267         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5268         if (!rtl_fw)
5269                 goto err_warn;
5270
5271         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
5272         if (rc < 0)
5273                 goto err_free;
5274
5275         rc = rtl_check_firmware(tp, rtl_fw);
5276         if (rc < 0)
5277                 goto err_release_firmware;
5278
5279         tp->rtl_fw = rtl_fw;
5280 out:
5281         return;
5282
5283 err_release_firmware:
5284         release_firmware(rtl_fw->fw);
5285 err_free:
5286         kfree(rtl_fw);
5287 err_warn:
5288         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5289                    name, rc);
5290 out_no_firmware:
5291         tp->rtl_fw = NULL;
5292         goto out;
5293 }
5294
5295 static void rtl_request_firmware(struct rtl8169_private *tp)
5296 {
5297         if (IS_ERR(tp->rtl_fw))
5298                 rtl_request_uncached_firmware(tp);
5299 }
5300
5301 static void rtl_rx_close(struct rtl8169_private *tp)
5302 {
5303         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5304 }
5305
5306 DECLARE_RTL_COND(rtl_npq_cond)
5307 {
5308         return RTL_R8(tp, TxPoll) & NPQ;
5309 }
5310
5311 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5312 {
5313         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
5314 }
5315
5316 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5317 {
5318         /* Disable interrupts */
5319         rtl8169_irq_mask_and_ack(tp);
5320
5321         rtl_rx_close(tp);
5322
5323         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5324             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5325             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5326                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5327         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5328                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5329                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5330                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5331                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5332                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5333                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5334                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5335                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5336                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5337                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5338                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5339                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5340                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5341                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5342                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5343                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5344                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5345                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5346         } else {
5347                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5348                 udelay(100);
5349         }
5350
5351         rtl_hw_reset(tp);
5352 }
5353
5354 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5355 {
5356         /* Set DMA burst size and Interframe Gap Time */
5357         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
5358                 (InterFrameGap << TxInterFrameGapShift));
5359 }
5360
5361 static void rtl_hw_start(struct net_device *dev)
5362 {
5363         struct rtl8169_private *tp = netdev_priv(dev);
5364
5365         tp->hw_start(dev);
5366
5367         rtl_irq_enable_all(tp);
5368 }
5369
5370 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
5371 {
5372         /*
5373          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5374          * register to be written before TxDescAddrLow to work.
5375          * Switching from MMIO to I/O access fixes the issue as well.
5376          */
5377         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5378         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5379         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5380         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5381 }
5382
5383 static u16 rtl_rw_cpluscmd(struct rtl8169_private *tp)
5384 {
5385         u16 cmd;
5386
5387         cmd = RTL_R16(tp, CPlusCmd);
5388         RTL_W16(tp, CPlusCmd, cmd);
5389         return cmd;
5390 }
5391
5392 static void rtl_set_rx_max_size(struct rtl8169_private *tp, unsigned int rx_buf_sz)
5393 {
5394         /* Low hurts. Let's disable the filtering. */
5395         RTL_W16(tp, RxMaxSize, rx_buf_sz + 1);
5396 }
5397
5398 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
5399 {
5400         static const struct rtl_cfg2_info {
5401                 u32 mac_version;
5402                 u32 clk;
5403                 u32 val;
5404         } cfg2_info [] = {
5405                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5406                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5407                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5408                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5409         };
5410         const struct rtl_cfg2_info *p = cfg2_info;
5411         unsigned int i;
5412         u32 clk;
5413
5414         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
5415         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5416                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5417                         RTL_W32(tp, 0x7c, p->val);
5418                         break;
5419                 }
5420         }
5421 }
5422
5423 static void rtl_set_rx_mode(struct net_device *dev)
5424 {
5425         struct rtl8169_private *tp = netdev_priv(dev);
5426         u32 mc_filter[2];       /* Multicast hash filter */
5427         int rx_mode;
5428         u32 tmp = 0;
5429
5430         if (dev->flags & IFF_PROMISC) {
5431                 /* Unconditionally log net taps. */
5432                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5433                 rx_mode =
5434                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5435                     AcceptAllPhys;
5436                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5437         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5438                    (dev->flags & IFF_ALLMULTI)) {
5439                 /* Too many to filter perfectly -- accept all multicasts. */
5440                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5441                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5442         } else {
5443                 struct netdev_hw_addr *ha;
5444
5445                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5446                 mc_filter[1] = mc_filter[0] = 0;
5447                 netdev_for_each_mc_addr(ha, dev) {
5448                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5449                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5450                         rx_mode |= AcceptMulticast;
5451                 }
5452         }
5453
5454         if (dev->features & NETIF_F_RXALL)
5455                 rx_mode |= (AcceptErr | AcceptRunt);
5456
5457         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5458
5459         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5460                 u32 data = mc_filter[0];
5461
5462                 mc_filter[0] = swab32(mc_filter[1]);
5463                 mc_filter[1] = swab32(data);
5464         }
5465
5466         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5467                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5468
5469         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
5470         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
5471
5472         RTL_W32(tp, RxConfig, tmp);
5473 }
5474
5475 static void rtl_hw_start_8169(struct net_device *dev)
5476 {
5477         struct rtl8169_private *tp = netdev_priv(dev);
5478         struct pci_dev *pdev = tp->pci_dev;
5479
5480         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5481                 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) | PCIMulRW);
5482                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5483         }
5484
5485         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5486         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5487             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5488             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5489             tp->mac_version == RTL_GIGA_MAC_VER_04)
5490                 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5491
5492         rtl_init_rxcfg(tp);
5493
5494         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5495
5496         rtl_set_rx_max_size(tp, rx_buf_sz);
5497
5498         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5499             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5500             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5501             tp->mac_version == RTL_GIGA_MAC_VER_04)
5502                 rtl_set_rx_tx_config_registers(tp);
5503
5504         tp->cp_cmd |= rtl_rw_cpluscmd(tp) | PCIMulRW;
5505
5506         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5507             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5508                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5509                         "Bit-3 and bit-14 MUST be 1\n");
5510                 tp->cp_cmd |= (1 << 14);
5511         }
5512
5513         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5514
5515         rtl8169_set_magic_reg(tp, tp->mac_version);
5516
5517         /*
5518          * Undocumented corner. Supposedly:
5519          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5520          */
5521         RTL_W16(tp, IntrMitigate, 0x0000);
5522
5523         rtl_set_rx_tx_desc_registers(tp);
5524
5525         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5526             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5527             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5528             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5529                 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5530                 rtl_set_rx_tx_config_registers(tp);
5531         }
5532
5533         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5534
5535         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5536         RTL_R8(tp, IntrMask);
5537
5538         RTL_W32(tp, RxMissed, 0);
5539
5540         rtl_set_rx_mode(dev);
5541
5542         /* no early-rx interrupts */
5543         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5544 }
5545
5546 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5547 {
5548         if (tp->csi_ops.write)
5549                 tp->csi_ops.write(tp, addr, value);
5550 }
5551
5552 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5553 {
5554         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5555 }
5556
5557 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5558 {
5559         u32 csi;
5560
5561         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5562         rtl_csi_write(tp, 0x070c, csi | bits);
5563 }
5564
5565 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5566 {
5567         rtl_csi_access_enable(tp, 0x17000000);
5568 }
5569
5570 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5571 {
5572         rtl_csi_access_enable(tp, 0x27000000);
5573 }
5574
5575 DECLARE_RTL_COND(rtl_csiar_cond)
5576 {
5577         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
5578 }
5579
5580 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5581 {
5582         RTL_W32(tp, CSIDR, value);
5583         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5584                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5585
5586         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5587 }
5588
5589 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5590 {
5591         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) |
5592                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5593
5594         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5595                 RTL_R32(tp, CSIDR) : ~0;
5596 }
5597
5598 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5599 {
5600         RTL_W32(tp, CSIDR, value);
5601         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5602                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5603                 CSIAR_FUNC_NIC);
5604
5605         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5606 }
5607
5608 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5609 {
5610         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5611                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5612
5613         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5614                 RTL_R32(tp, CSIDR) : ~0;
5615 }
5616
5617 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5618 {
5619         RTL_W32(tp, CSIDR, value);
5620         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5621                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5622                 CSIAR_FUNC_NIC2);
5623
5624         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5625 }
5626
5627 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5628 {
5629         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5630                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5631
5632         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5633                 RTL_R32(tp, CSIDR) : ~0;
5634 }
5635
5636 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5637 {
5638         struct csi_ops *ops = &tp->csi_ops;
5639
5640         switch (tp->mac_version) {
5641         case RTL_GIGA_MAC_VER_01:
5642         case RTL_GIGA_MAC_VER_02:
5643         case RTL_GIGA_MAC_VER_03:
5644         case RTL_GIGA_MAC_VER_04:
5645         case RTL_GIGA_MAC_VER_05:
5646         case RTL_GIGA_MAC_VER_06:
5647         case RTL_GIGA_MAC_VER_10:
5648         case RTL_GIGA_MAC_VER_11:
5649         case RTL_GIGA_MAC_VER_12:
5650         case RTL_GIGA_MAC_VER_13:
5651         case RTL_GIGA_MAC_VER_14:
5652         case RTL_GIGA_MAC_VER_15:
5653         case RTL_GIGA_MAC_VER_16:
5654         case RTL_GIGA_MAC_VER_17:
5655                 ops->write      = NULL;
5656                 ops->read       = NULL;
5657                 break;
5658
5659         case RTL_GIGA_MAC_VER_37:
5660         case RTL_GIGA_MAC_VER_38:
5661                 ops->write      = r8402_csi_write;
5662                 ops->read       = r8402_csi_read;
5663                 break;
5664
5665         case RTL_GIGA_MAC_VER_44:
5666                 ops->write      = r8411_csi_write;
5667                 ops->read       = r8411_csi_read;
5668                 break;
5669
5670         default:
5671                 ops->write      = r8169_csi_write;
5672                 ops->read       = r8169_csi_read;
5673                 break;
5674         }
5675 }
5676
5677 struct ephy_info {
5678         unsigned int offset;
5679         u16 mask;
5680         u16 bits;
5681 };
5682
5683 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5684                           int len)
5685 {
5686         u16 w;
5687
5688         while (len-- > 0) {
5689                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5690                 rtl_ephy_write(tp, e->offset, w);
5691                 e++;
5692         }
5693 }
5694
5695 static void rtl_disable_clock_request(struct rtl8169_private *tp)
5696 {
5697         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
5698                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5699 }
5700
5701 static void rtl_enable_clock_request(struct rtl8169_private *tp)
5702 {
5703         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
5704                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5705 }
5706
5707 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5708 {
5709         u8 data;
5710
5711         data = RTL_R8(tp, Config3);
5712
5713         if (enable)
5714                 data |= Rdy_to_L23;
5715         else
5716                 data &= ~Rdy_to_L23;
5717
5718         RTL_W8(tp, Config3, data);
5719 }
5720
5721 #define R8168_CPCMD_QUIRK_MASK (\
5722         EnableBist | \
5723         Mac_dbgo_oe | \
5724         Force_half_dup | \
5725         Force_rxflow_en | \
5726         Force_txflow_en | \
5727         Cxpl_dbg_sel | \
5728         ASF | \
5729         PktCntrDisable | \
5730         Mac_dbgo_sel)
5731
5732 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5733 {
5734         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5735
5736         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5737
5738         if (tp->dev->mtu <= ETH_DATA_LEN) {
5739                 rtl_tx_performance_tweak(tp, (0x5 << MAX_READ_REQUEST_SHIFT) |
5740                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5741         }
5742 }
5743
5744 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5745 {
5746         rtl_hw_start_8168bb(tp);
5747
5748         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5749
5750         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5751 }
5752
5753 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5754 {
5755         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
5756
5757         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5758
5759         if (tp->dev->mtu <= ETH_DATA_LEN)
5760                 rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5761
5762         rtl_disable_clock_request(tp);
5763
5764         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5765 }
5766
5767 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5768 {
5769         static const struct ephy_info e_info_8168cp[] = {
5770                 { 0x01, 0,      0x0001 },
5771                 { 0x02, 0x0800, 0x1000 },
5772                 { 0x03, 0,      0x0042 },
5773                 { 0x06, 0x0080, 0x0000 },
5774                 { 0x07, 0,      0x2000 }
5775         };
5776
5777         rtl_csi_access_enable_2(tp);
5778
5779         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5780
5781         __rtl_hw_start_8168cp(tp);
5782 }
5783
5784 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5785 {
5786         rtl_csi_access_enable_2(tp);
5787
5788         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5789
5790         if (tp->dev->mtu <= ETH_DATA_LEN)
5791                 rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5792
5793         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5794 }
5795
5796 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5797 {
5798         rtl_csi_access_enable_2(tp);
5799
5800         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5801
5802         /* Magic. */
5803         RTL_W8(tp, DBG_REG, 0x20);
5804
5805         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5806
5807         if (tp->dev->mtu <= ETH_DATA_LEN)
5808                 rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5809
5810         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5811 }
5812
5813 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5814 {
5815         static const struct ephy_info e_info_8168c_1[] = {
5816                 { 0x02, 0x0800, 0x1000 },
5817                 { 0x03, 0,      0x0002 },
5818                 { 0x06, 0x0080, 0x0000 }
5819         };
5820
5821         rtl_csi_access_enable_2(tp);
5822
5823         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5824
5825         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5826
5827         __rtl_hw_start_8168cp(tp);
5828 }
5829
5830 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5831 {
5832         static const struct ephy_info e_info_8168c_2[] = {
5833                 { 0x01, 0,      0x0001 },
5834                 { 0x03, 0x0400, 0x0220 }
5835         };
5836
5837         rtl_csi_access_enable_2(tp);
5838
5839         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5840
5841         __rtl_hw_start_8168cp(tp);
5842 }
5843
5844 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5845 {
5846         rtl_hw_start_8168c_2(tp);
5847 }
5848
5849 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5850 {
5851         rtl_csi_access_enable_2(tp);
5852
5853         __rtl_hw_start_8168cp(tp);
5854 }
5855
5856 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5857 {
5858         rtl_csi_access_enable_2(tp);
5859
5860         rtl_disable_clock_request(tp);
5861
5862         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5863
5864         if (tp->dev->mtu <= ETH_DATA_LEN)
5865                 rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5866
5867         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5868 }
5869
5870 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5871 {
5872         rtl_csi_access_enable_1(tp);
5873
5874         if (tp->dev->mtu <= ETH_DATA_LEN)
5875                 rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5876
5877         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5878
5879         rtl_disable_clock_request(tp);
5880 }
5881
5882 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5883 {
5884         static const struct ephy_info e_info_8168d_4[] = {
5885                 { 0x0b, 0x0000, 0x0048 },
5886                 { 0x19, 0x0020, 0x0050 },
5887                 { 0x0c, 0x0100, 0x0020 }
5888         };
5889
5890         rtl_csi_access_enable_1(tp);
5891
5892         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5893
5894         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5895
5896         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5897
5898         rtl_enable_clock_request(tp);
5899 }
5900
5901 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5902 {
5903         static const struct ephy_info e_info_8168e_1[] = {
5904                 { 0x00, 0x0200, 0x0100 },
5905                 { 0x00, 0x0000, 0x0004 },
5906                 { 0x06, 0x0002, 0x0001 },
5907                 { 0x06, 0x0000, 0x0030 },
5908                 { 0x07, 0x0000, 0x2000 },
5909                 { 0x00, 0x0000, 0x0020 },
5910                 { 0x03, 0x5800, 0x2000 },
5911                 { 0x03, 0x0000, 0x0001 },
5912                 { 0x01, 0x0800, 0x1000 },
5913                 { 0x07, 0x0000, 0x4000 },
5914                 { 0x1e, 0x0000, 0x2000 },
5915                 { 0x19, 0xffff, 0xfe6c },
5916                 { 0x0a, 0x0000, 0x0040 }
5917         };
5918
5919         rtl_csi_access_enable_2(tp);
5920
5921         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5922
5923         if (tp->dev->mtu <= ETH_DATA_LEN)
5924                 rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5925
5926         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5927
5928         rtl_disable_clock_request(tp);
5929
5930         /* Reset tx FIFO pointer */
5931         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5932         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5933
5934         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5935 }
5936
5937 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5938 {
5939         static const struct ephy_info e_info_8168e_2[] = {
5940                 { 0x09, 0x0000, 0x0080 },
5941                 { 0x19, 0x0000, 0x0224 }
5942         };
5943
5944         rtl_csi_access_enable_1(tp);
5945
5946         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5947
5948         if (tp->dev->mtu <= ETH_DATA_LEN)
5949                 rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5950
5951         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5952         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5953         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5954         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5955         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5956         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5957         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5958         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5959
5960         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5961
5962         rtl_disable_clock_request(tp);
5963
5964         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5965         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5966
5967         /* Adjust EEE LED frequency */
5968         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5969
5970         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5971         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5972         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5973 }
5974
5975 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5976 {
5977         rtl_csi_access_enable_2(tp);
5978
5979         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
5980
5981         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5982         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5983         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5984         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5985         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5986         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5987         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5988         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5989         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5990         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5991
5992         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5993
5994         rtl_disable_clock_request(tp);
5995
5996         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5997         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5998         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5999         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
6000         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
6001 }
6002
6003 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
6004 {
6005         static const struct ephy_info e_info_8168f_1[] = {
6006                 { 0x06, 0x00c0, 0x0020 },
6007                 { 0x08, 0x0001, 0x0002 },
6008                 { 0x09, 0x0000, 0x0080 },
6009                 { 0x19, 0x0000, 0x0224 }
6010         };
6011
6012         rtl_hw_start_8168f(tp);
6013
6014         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6015
6016         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6017
6018         /* Adjust EEE LED frequency */
6019         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6020 }
6021
6022 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6023 {
6024         static const struct ephy_info e_info_8168f_1[] = {
6025                 { 0x06, 0x00c0, 0x0020 },
6026                 { 0x0f, 0xffff, 0x5200 },
6027                 { 0x1e, 0x0000, 0x4000 },
6028                 { 0x19, 0x0000, 0x0224 }
6029         };
6030
6031         rtl_hw_start_8168f(tp);
6032         rtl_pcie_state_l2l3_enable(tp, false);
6033
6034         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6035
6036         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6037 }
6038
6039 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6040 {
6041         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6042
6043         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6044         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6045         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6046         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6047
6048         rtl_csi_access_enable_1(tp);
6049
6050         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6051
6052         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6053         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6054         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6055
6056         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6057         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6058
6059         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6060         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6061
6062         /* Adjust EEE LED frequency */
6063         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6064
6065         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6066         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6067
6068         rtl_pcie_state_l2l3_enable(tp, false);
6069 }
6070
6071 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6072 {
6073         static const struct ephy_info e_info_8168g_1[] = {
6074                 { 0x00, 0x0000, 0x0008 },
6075                 { 0x0c, 0x37d0, 0x0820 },
6076                 { 0x1e, 0x0000, 0x0001 },
6077                 { 0x19, 0x8000, 0x0000 }
6078         };
6079
6080         rtl_hw_start_8168g(tp);
6081
6082         /* disable aspm and clock request before access ephy */
6083         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6084         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6085         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6086 }
6087
6088 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6089 {
6090         static const struct ephy_info e_info_8168g_2[] = {
6091                 { 0x00, 0x0000, 0x0008 },
6092                 { 0x0c, 0x3df0, 0x0200 },
6093                 { 0x19, 0xffff, 0xfc00 },
6094                 { 0x1e, 0xffff, 0x20eb }
6095         };
6096
6097         rtl_hw_start_8168g(tp);
6098
6099         /* disable aspm and clock request before access ephy */
6100         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6101         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6102         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6103 }
6104
6105 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6106 {
6107         static const struct ephy_info e_info_8411_2[] = {
6108                 { 0x00, 0x0000, 0x0008 },
6109                 { 0x0c, 0x3df0, 0x0200 },
6110                 { 0x0f, 0xffff, 0x5200 },
6111                 { 0x19, 0x0020, 0x0000 },
6112                 { 0x1e, 0x0000, 0x2000 }
6113         };
6114
6115         rtl_hw_start_8168g(tp);
6116
6117         /* disable aspm and clock request before access ephy */
6118         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6119         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6120         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6121 }
6122
6123 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6124 {
6125         int rg_saw_cnt;
6126         u32 data;
6127         static const struct ephy_info e_info_8168h_1[] = {
6128                 { 0x1e, 0x0800, 0x0001 },
6129                 { 0x1d, 0x0000, 0x0800 },
6130                 { 0x05, 0xffff, 0x2089 },
6131                 { 0x06, 0xffff, 0x5881 },
6132                 { 0x04, 0xffff, 0x154a },
6133                 { 0x01, 0xffff, 0x068b }
6134         };
6135
6136         /* disable aspm and clock request before access ephy */
6137         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6138         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6139         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6140
6141         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6142
6143         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6144         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6145         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6146         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6147
6148         rtl_csi_access_enable_1(tp);
6149
6150         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6151
6152         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6153         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6154
6155         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6156
6157         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6158
6159         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6160
6161         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6162         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6163
6164         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6165         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6166
6167         /* Adjust EEE LED frequency */
6168         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6169
6170         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6171         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6172
6173         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6174
6175         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6176
6177         rtl_pcie_state_l2l3_enable(tp, false);
6178
6179         rtl_writephy(tp, 0x1f, 0x0c42);
6180         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6181         rtl_writephy(tp, 0x1f, 0x0000);
6182         if (rg_saw_cnt > 0) {
6183                 u16 sw_cnt_1ms_ini;
6184
6185                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6186                 sw_cnt_1ms_ini &= 0x0fff;
6187                 data = r8168_mac_ocp_read(tp, 0xd412);
6188                 data &= ~0x0fff;
6189                 data |= sw_cnt_1ms_ini;
6190                 r8168_mac_ocp_write(tp, 0xd412, data);
6191         }
6192
6193         data = r8168_mac_ocp_read(tp, 0xe056);
6194         data &= ~0xf0;
6195         data |= 0x70;
6196         r8168_mac_ocp_write(tp, 0xe056, data);
6197
6198         data = r8168_mac_ocp_read(tp, 0xe052);
6199         data &= ~0x6000;
6200         data |= 0x8008;
6201         r8168_mac_ocp_write(tp, 0xe052, data);
6202
6203         data = r8168_mac_ocp_read(tp, 0xe0d6);
6204         data &= ~0x01ff;
6205         data |= 0x017f;
6206         r8168_mac_ocp_write(tp, 0xe0d6, data);
6207
6208         data = r8168_mac_ocp_read(tp, 0xd420);
6209         data &= ~0x0fff;
6210         data |= 0x047f;
6211         r8168_mac_ocp_write(tp, 0xd420, data);
6212
6213         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6214         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6215         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6216         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6217 }
6218
6219 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6220 {
6221         rtl8168ep_stop_cmac(tp);
6222
6223         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6224
6225         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6226         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6227         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6228         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6229
6230         rtl_csi_access_enable_1(tp);
6231
6232         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6233
6234         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6235         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6236
6237         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6238
6239         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6240
6241         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6242         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6243
6244         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6245         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6246
6247         /* Adjust EEE LED frequency */
6248         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6249
6250         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6251
6252         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6253
6254         rtl_pcie_state_l2l3_enable(tp, false);
6255 }
6256
6257 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6258 {
6259         static const struct ephy_info e_info_8168ep_1[] = {
6260                 { 0x00, 0xffff, 0x10ab },
6261                 { 0x06, 0xffff, 0xf030 },
6262                 { 0x08, 0xffff, 0x2006 },
6263                 { 0x0d, 0xffff, 0x1666 },
6264                 { 0x0c, 0x3ff0, 0x0000 }
6265         };
6266
6267         /* disable aspm and clock request before access ephy */
6268         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6269         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6270         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6271
6272         rtl_hw_start_8168ep(tp);
6273 }
6274
6275 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6276 {
6277         static const struct ephy_info e_info_8168ep_2[] = {
6278                 { 0x00, 0xffff, 0x10a3 },
6279                 { 0x19, 0xffff, 0xfc00 },
6280                 { 0x1e, 0xffff, 0x20ea }
6281         };
6282
6283         /* disable aspm and clock request before access ephy */
6284         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6285         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6286         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6287
6288         rtl_hw_start_8168ep(tp);
6289
6290         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6291         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6292 }
6293
6294 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6295 {
6296         u32 data;
6297         static const struct ephy_info e_info_8168ep_3[] = {
6298                 { 0x00, 0xffff, 0x10a3 },
6299                 { 0x19, 0xffff, 0x7c00 },
6300                 { 0x1e, 0xffff, 0x20eb },
6301                 { 0x0d, 0xffff, 0x1666 }
6302         };
6303
6304         /* disable aspm and clock request before access ephy */
6305         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6306         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6307         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6308
6309         rtl_hw_start_8168ep(tp);
6310
6311         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6312         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6313
6314         data = r8168_mac_ocp_read(tp, 0xd3e2);
6315         data &= 0xf000;
6316         data |= 0x0271;
6317         r8168_mac_ocp_write(tp, 0xd3e2, data);
6318
6319         data = r8168_mac_ocp_read(tp, 0xd3e4);
6320         data &= 0xff00;
6321         r8168_mac_ocp_write(tp, 0xd3e4, data);
6322
6323         data = r8168_mac_ocp_read(tp, 0xe860);
6324         data |= 0x0080;
6325         r8168_mac_ocp_write(tp, 0xe860, data);
6326 }
6327
6328 static void rtl_hw_start_8168(struct net_device *dev)
6329 {
6330         struct rtl8169_private *tp = netdev_priv(dev);
6331
6332         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6333
6334         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
6335
6336         rtl_set_rx_max_size(tp, rx_buf_sz);
6337
6338         tp->cp_cmd |= RTL_R16(tp, CPlusCmd) | PktCntrDisable | INTT_1;
6339
6340         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6341
6342         RTL_W16(tp, IntrMitigate, 0x5151);
6343
6344         /* Work around for RxFIFO overflow. */
6345         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6346                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6347                 tp->event_slow &= ~RxOverflow;
6348         }
6349
6350         rtl_set_rx_tx_desc_registers(tp);
6351
6352         rtl_set_rx_tx_config_registers(tp);
6353
6354         RTL_R8(tp, IntrMask);
6355
6356         switch (tp->mac_version) {
6357         case RTL_GIGA_MAC_VER_11:
6358                 rtl_hw_start_8168bb(tp);
6359                 break;
6360
6361         case RTL_GIGA_MAC_VER_12:
6362         case RTL_GIGA_MAC_VER_17:
6363                 rtl_hw_start_8168bef(tp);
6364                 break;
6365
6366         case RTL_GIGA_MAC_VER_18:
6367                 rtl_hw_start_8168cp_1(tp);
6368                 break;
6369
6370         case RTL_GIGA_MAC_VER_19:
6371                 rtl_hw_start_8168c_1(tp);
6372                 break;
6373
6374         case RTL_GIGA_MAC_VER_20:
6375                 rtl_hw_start_8168c_2(tp);
6376                 break;
6377
6378         case RTL_GIGA_MAC_VER_21:
6379                 rtl_hw_start_8168c_3(tp);
6380                 break;
6381
6382         case RTL_GIGA_MAC_VER_22:
6383                 rtl_hw_start_8168c_4(tp);
6384                 break;
6385
6386         case RTL_GIGA_MAC_VER_23:
6387                 rtl_hw_start_8168cp_2(tp);
6388                 break;
6389
6390         case RTL_GIGA_MAC_VER_24:
6391                 rtl_hw_start_8168cp_3(tp);
6392                 break;
6393
6394         case RTL_GIGA_MAC_VER_25:
6395         case RTL_GIGA_MAC_VER_26:
6396         case RTL_GIGA_MAC_VER_27:
6397                 rtl_hw_start_8168d(tp);
6398                 break;
6399
6400         case RTL_GIGA_MAC_VER_28:
6401                 rtl_hw_start_8168d_4(tp);
6402                 break;
6403
6404         case RTL_GIGA_MAC_VER_31:
6405                 rtl_hw_start_8168dp(tp);
6406                 break;
6407
6408         case RTL_GIGA_MAC_VER_32:
6409         case RTL_GIGA_MAC_VER_33:
6410                 rtl_hw_start_8168e_1(tp);
6411                 break;
6412         case RTL_GIGA_MAC_VER_34:
6413                 rtl_hw_start_8168e_2(tp);
6414                 break;
6415
6416         case RTL_GIGA_MAC_VER_35:
6417         case RTL_GIGA_MAC_VER_36:
6418                 rtl_hw_start_8168f_1(tp);
6419                 break;
6420
6421         case RTL_GIGA_MAC_VER_38:
6422                 rtl_hw_start_8411(tp);
6423                 break;
6424
6425         case RTL_GIGA_MAC_VER_40:
6426         case RTL_GIGA_MAC_VER_41:
6427                 rtl_hw_start_8168g_1(tp);
6428                 break;
6429         case RTL_GIGA_MAC_VER_42:
6430                 rtl_hw_start_8168g_2(tp);
6431                 break;
6432
6433         case RTL_GIGA_MAC_VER_44:
6434                 rtl_hw_start_8411_2(tp);
6435                 break;
6436
6437         case RTL_GIGA_MAC_VER_45:
6438         case RTL_GIGA_MAC_VER_46:
6439                 rtl_hw_start_8168h_1(tp);
6440                 break;
6441
6442         case RTL_GIGA_MAC_VER_49:
6443                 rtl_hw_start_8168ep_1(tp);
6444                 break;
6445
6446         case RTL_GIGA_MAC_VER_50:
6447                 rtl_hw_start_8168ep_2(tp);
6448                 break;
6449
6450         case RTL_GIGA_MAC_VER_51:
6451                 rtl_hw_start_8168ep_3(tp);
6452                 break;
6453
6454         default:
6455                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6456                         dev->name, tp->mac_version);
6457                 break;
6458         }
6459
6460         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6461
6462         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
6463
6464         rtl_set_rx_mode(dev);
6465
6466         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
6467 }
6468
6469 #define R810X_CPCMD_QUIRK_MASK (\
6470         EnableBist | \
6471         Mac_dbgo_oe | \
6472         Force_half_dup | \
6473         Force_rxflow_en | \
6474         Force_txflow_en | \
6475         Cxpl_dbg_sel | \
6476         ASF | \
6477         PktCntrDisable | \
6478         Mac_dbgo_sel)
6479
6480 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6481 {
6482         static const struct ephy_info e_info_8102e_1[] = {
6483                 { 0x01, 0, 0x6e65 },
6484                 { 0x02, 0, 0x091f },
6485                 { 0x03, 0, 0xc2f9 },
6486                 { 0x06, 0, 0xafb5 },
6487                 { 0x07, 0, 0x0e00 },
6488                 { 0x19, 0, 0xec80 },
6489                 { 0x01, 0, 0x2e65 },
6490                 { 0x01, 0, 0x6e65 }
6491         };
6492         u8 cfg1;
6493
6494         rtl_csi_access_enable_2(tp);
6495
6496         RTL_W8(tp, DBG_REG, FIX_NAK_1);
6497
6498         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6499
6500         RTL_W8(tp, Config1,
6501                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6502         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6503
6504         cfg1 = RTL_R8(tp, Config1);
6505         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6506                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
6507
6508         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6509 }
6510
6511 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6512 {
6513         rtl_csi_access_enable_2(tp);
6514
6515         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6516
6517         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
6518         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6519 }
6520
6521 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6522 {
6523         rtl_hw_start_8102e_2(tp);
6524
6525         rtl_ephy_write(tp, 0x03, 0xc2f9);
6526 }
6527
6528 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6529 {
6530         static const struct ephy_info e_info_8105e_1[] = {
6531                 { 0x07, 0, 0x4000 },
6532                 { 0x19, 0, 0x0200 },
6533                 { 0x19, 0, 0x0020 },
6534                 { 0x1e, 0, 0x2000 },
6535                 { 0x03, 0, 0x0001 },
6536                 { 0x19, 0, 0x0100 },
6537                 { 0x19, 0, 0x0004 },
6538                 { 0x0a, 0, 0x0020 }
6539         };
6540
6541         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6542         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6543
6544         /* Disable Early Tally Counter */
6545         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
6546
6547         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6548         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
6549
6550         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6551
6552         rtl_pcie_state_l2l3_enable(tp, false);
6553 }
6554
6555 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6556 {
6557         rtl_hw_start_8105e_1(tp);
6558         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6559 }
6560
6561 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6562 {
6563         static const struct ephy_info e_info_8402[] = {
6564                 { 0x19, 0xffff, 0xff64 },
6565                 { 0x1e, 0, 0x4000 }
6566         };
6567
6568         rtl_csi_access_enable_2(tp);
6569
6570         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6571         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6572
6573         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6574         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6575
6576         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6577
6578         rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);
6579
6580         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6581         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6582         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6583         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6584         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6585         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6586         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6587
6588         rtl_pcie_state_l2l3_enable(tp, false);
6589 }
6590
6591 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6592 {
6593         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6594         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6595
6596         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6597         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6598         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6599
6600         rtl_pcie_state_l2l3_enable(tp, false);
6601 }
6602
6603 static void rtl_hw_start_8101(struct net_device *dev)
6604 {
6605         struct rtl8169_private *tp = netdev_priv(dev);
6606         struct pci_dev *pdev = tp->pci_dev;
6607
6608         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6609                 tp->event_slow &= ~RxFIFOOver;
6610
6611         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6612             tp->mac_version == RTL_GIGA_MAC_VER_16)
6613                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6614                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6615
6616         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6617
6618         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
6619
6620         rtl_set_rx_max_size(tp, rx_buf_sz);
6621
6622         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6623         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6624
6625         rtl_set_rx_tx_desc_registers(tp);
6626
6627         rtl_set_rx_tx_config_registers(tp);
6628
6629         switch (tp->mac_version) {
6630         case RTL_GIGA_MAC_VER_07:
6631                 rtl_hw_start_8102e_1(tp);
6632                 break;
6633
6634         case RTL_GIGA_MAC_VER_08:
6635                 rtl_hw_start_8102e_3(tp);
6636                 break;
6637
6638         case RTL_GIGA_MAC_VER_09:
6639                 rtl_hw_start_8102e_2(tp);
6640                 break;
6641
6642         case RTL_GIGA_MAC_VER_29:
6643                 rtl_hw_start_8105e_1(tp);
6644                 break;
6645         case RTL_GIGA_MAC_VER_30:
6646                 rtl_hw_start_8105e_2(tp);
6647                 break;
6648
6649         case RTL_GIGA_MAC_VER_37:
6650                 rtl_hw_start_8402(tp);
6651                 break;
6652
6653         case RTL_GIGA_MAC_VER_39:
6654                 rtl_hw_start_8106(tp);
6655                 break;
6656         case RTL_GIGA_MAC_VER_43:
6657                 rtl_hw_start_8168g_2(tp);
6658                 break;
6659         case RTL_GIGA_MAC_VER_47:
6660         case RTL_GIGA_MAC_VER_48:
6661                 rtl_hw_start_8168h_1(tp);
6662                 break;
6663         }
6664
6665         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6666
6667         RTL_W16(tp, IntrMitigate, 0x0000);
6668
6669         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
6670
6671         rtl_set_rx_mode(dev);
6672
6673         RTL_R8(tp, IntrMask);
6674
6675         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
6676 }
6677
6678 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6679 {
6680         struct rtl8169_private *tp = netdev_priv(dev);
6681
6682         if (new_mtu > ETH_DATA_LEN)
6683                 rtl_hw_jumbo_enable(tp);
6684         else
6685                 rtl_hw_jumbo_disable(tp);
6686
6687         dev->mtu = new_mtu;
6688         netdev_update_features(dev);
6689
6690         return 0;
6691 }
6692
6693 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6694 {
6695         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6696         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6697 }
6698
6699 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6700                                      void **data_buff, struct RxDesc *desc)
6701 {
6702         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), rx_buf_sz,
6703                          DMA_FROM_DEVICE);
6704
6705         kfree(*data_buff);
6706         *data_buff = NULL;
6707         rtl8169_make_unusable_by_asic(desc);
6708 }
6709
6710 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6711 {
6712         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6713
6714         /* Force memory writes to complete before releasing descriptor */
6715         dma_wmb();
6716
6717         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6718 }
6719
6720 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6721                                        u32 rx_buf_sz)
6722 {
6723         desc->addr = cpu_to_le64(mapping);
6724         rtl8169_mark_to_asic(desc, rx_buf_sz);
6725 }
6726
6727 static inline void *rtl8169_align(void *data)
6728 {
6729         return (void *)ALIGN((long)data, 16);
6730 }
6731
6732 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6733                                              struct RxDesc *desc)
6734 {
6735         void *data;
6736         dma_addr_t mapping;
6737         struct device *d = tp_to_dev(tp);
6738         struct net_device *dev = tp->dev;
6739         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6740
6741         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6742         if (!data)
6743                 return NULL;
6744
6745         if (rtl8169_align(data) != data) {
6746                 kfree(data);
6747                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6748                 if (!data)
6749                         return NULL;
6750         }
6751
6752         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6753                                  DMA_FROM_DEVICE);
6754         if (unlikely(dma_mapping_error(d, mapping))) {
6755                 if (net_ratelimit())
6756                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6757                 goto err_out;
6758         }
6759
6760         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6761         return data;
6762
6763 err_out:
6764         kfree(data);
6765         return NULL;
6766 }
6767
6768 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6769 {
6770         unsigned int i;
6771
6772         for (i = 0; i < NUM_RX_DESC; i++) {
6773                 if (tp->Rx_databuff[i]) {
6774                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6775                                             tp->RxDescArray + i);
6776                 }
6777         }
6778 }
6779
6780 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6781 {
6782         desc->opts1 |= cpu_to_le32(RingEnd);
6783 }
6784
6785 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6786 {
6787         unsigned int i;
6788
6789         for (i = 0; i < NUM_RX_DESC; i++) {
6790                 void *data;
6791
6792                 if (tp->Rx_databuff[i])
6793                         continue;
6794
6795                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6796                 if (!data) {
6797                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6798                         goto err_out;
6799                 }
6800                 tp->Rx_databuff[i] = data;
6801         }
6802
6803         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6804         return 0;
6805
6806 err_out:
6807         rtl8169_rx_clear(tp);
6808         return -ENOMEM;
6809 }
6810
6811 static int rtl8169_init_ring(struct net_device *dev)
6812 {
6813         struct rtl8169_private *tp = netdev_priv(dev);
6814
6815         rtl8169_init_ring_indexes(tp);
6816
6817         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6818         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6819
6820         return rtl8169_rx_fill(tp);
6821 }
6822
6823 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6824                                  struct TxDesc *desc)
6825 {
6826         unsigned int len = tx_skb->len;
6827
6828         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6829
6830         desc->opts1 = 0x00;
6831         desc->opts2 = 0x00;
6832         desc->addr = 0x00;
6833         tx_skb->len = 0;
6834 }
6835
6836 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6837                                    unsigned int n)
6838 {
6839         unsigned int i;
6840
6841         for (i = 0; i < n; i++) {
6842                 unsigned int entry = (start + i) % NUM_TX_DESC;
6843                 struct ring_info *tx_skb = tp->tx_skb + entry;
6844                 unsigned int len = tx_skb->len;
6845
6846                 if (len) {
6847                         struct sk_buff *skb = tx_skb->skb;
6848
6849                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6850                                              tp->TxDescArray + entry);
6851                         if (skb) {
6852                                 dev_consume_skb_any(skb);
6853                                 tx_skb->skb = NULL;
6854                         }
6855                 }
6856         }
6857 }
6858
6859 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6860 {
6861         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6862         tp->cur_tx = tp->dirty_tx = 0;
6863 }
6864
6865 static void rtl_reset_work(struct rtl8169_private *tp)
6866 {
6867         struct net_device *dev = tp->dev;
6868         int i;
6869
6870         napi_disable(&tp->napi);
6871         netif_stop_queue(dev);
6872         synchronize_sched();
6873
6874         rtl8169_hw_reset(tp);
6875
6876         for (i = 0; i < NUM_RX_DESC; i++)
6877                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6878
6879         rtl8169_tx_clear(tp);
6880         rtl8169_init_ring_indexes(tp);
6881
6882         napi_enable(&tp->napi);
6883         rtl_hw_start(dev);
6884         netif_wake_queue(dev);
6885         rtl8169_check_link_status(dev, tp);
6886 }
6887
6888 static void rtl8169_tx_timeout(struct net_device *dev)
6889 {
6890         struct rtl8169_private *tp = netdev_priv(dev);
6891
6892         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6893 }
6894
6895 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6896                               u32 *opts)
6897 {
6898         struct skb_shared_info *info = skb_shinfo(skb);
6899         unsigned int cur_frag, entry;
6900         struct TxDesc *uninitialized_var(txd);
6901         struct device *d = tp_to_dev(tp);
6902
6903         entry = tp->cur_tx;
6904         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6905                 const skb_frag_t *frag = info->frags + cur_frag;
6906                 dma_addr_t mapping;
6907                 u32 status, len;
6908                 void *addr;
6909
6910                 entry = (entry + 1) % NUM_TX_DESC;
6911
6912                 txd = tp->TxDescArray + entry;
6913                 len = skb_frag_size(frag);
6914                 addr = skb_frag_address(frag);
6915                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6916                 if (unlikely(dma_mapping_error(d, mapping))) {
6917                         if (net_ratelimit())
6918                                 netif_err(tp, drv, tp->dev,
6919                                           "Failed to map TX fragments DMA!\n");
6920                         goto err_out;
6921                 }
6922
6923                 /* Anti gcc 2.95.3 bugware (sic) */
6924                 status = opts[0] | len |
6925                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6926
6927                 txd->opts1 = cpu_to_le32(status);
6928                 txd->opts2 = cpu_to_le32(opts[1]);
6929                 txd->addr = cpu_to_le64(mapping);
6930
6931                 tp->tx_skb[entry].len = len;
6932         }
6933
6934         if (cur_frag) {
6935                 tp->tx_skb[entry].skb = skb;
6936                 txd->opts1 |= cpu_to_le32(LastFrag);
6937         }
6938
6939         return cur_frag;
6940
6941 err_out:
6942         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6943         return -EIO;
6944 }
6945
6946 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6947 {
6948         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6949 }
6950
6951 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6952                                       struct net_device *dev);
6953 /* r8169_csum_workaround()
6954  * The hw limites the value the transport offset. When the offset is out of the
6955  * range, calculate the checksum by sw.
6956  */
6957 static void r8169_csum_workaround(struct rtl8169_private *tp,
6958                                   struct sk_buff *skb)
6959 {
6960         if (skb_shinfo(skb)->gso_size) {
6961                 netdev_features_t features = tp->dev->features;
6962                 struct sk_buff *segs, *nskb;
6963
6964                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6965                 segs = skb_gso_segment(skb, features);
6966                 if (IS_ERR(segs) || !segs)
6967                         goto drop;
6968
6969                 do {
6970                         nskb = segs;
6971                         segs = segs->next;
6972                         nskb->next = NULL;
6973                         rtl8169_start_xmit(nskb, tp->dev);
6974                 } while (segs);
6975
6976                 dev_consume_skb_any(skb);
6977         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6978                 if (skb_checksum_help(skb) < 0)
6979                         goto drop;
6980
6981                 rtl8169_start_xmit(skb, tp->dev);
6982         } else {
6983                 struct net_device_stats *stats;
6984
6985 drop:
6986                 stats = &tp->dev->stats;
6987                 stats->tx_dropped++;
6988                 dev_kfree_skb_any(skb);
6989         }
6990 }
6991
6992 /* msdn_giant_send_check()
6993  * According to the document of microsoft, the TCP Pseudo Header excludes the
6994  * packet length for IPv6 TCP large packets.
6995  */
6996 static int msdn_giant_send_check(struct sk_buff *skb)
6997 {
6998         const struct ipv6hdr *ipv6h;
6999         struct tcphdr *th;
7000         int ret;
7001
7002         ret = skb_cow_head(skb, 0);
7003         if (ret)
7004                 return ret;
7005
7006         ipv6h = ipv6_hdr(skb);
7007         th = tcp_hdr(skb);
7008
7009         th->check = 0;
7010         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7011
7012         return ret;
7013 }
7014
7015 static inline __be16 get_protocol(struct sk_buff *skb)
7016 {
7017         __be16 protocol;
7018
7019         if (skb->protocol == htons(ETH_P_8021Q))
7020                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7021         else
7022                 protocol = skb->protocol;
7023
7024         return protocol;
7025 }
7026
7027 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7028                                 struct sk_buff *skb, u32 *opts)
7029 {
7030         u32 mss = skb_shinfo(skb)->gso_size;
7031
7032         if (mss) {
7033                 opts[0] |= TD_LSO;
7034                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7035         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7036                 const struct iphdr *ip = ip_hdr(skb);
7037
7038                 if (ip->protocol == IPPROTO_TCP)
7039                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7040                 else if (ip->protocol == IPPROTO_UDP)
7041                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7042                 else
7043                         WARN_ON_ONCE(1);
7044         }
7045
7046         return true;
7047 }
7048
7049 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7050                                 struct sk_buff *skb, u32 *opts)
7051 {
7052         u32 transport_offset = (u32)skb_transport_offset(skb);
7053         u32 mss = skb_shinfo(skb)->gso_size;
7054
7055         if (mss) {
7056                 if (transport_offset > GTTCPHO_MAX) {
7057                         netif_warn(tp, tx_err, tp->dev,
7058                                    "Invalid transport offset 0x%x for TSO\n",
7059                                    transport_offset);
7060                         return false;
7061                 }
7062
7063                 switch (get_protocol(skb)) {
7064                 case htons(ETH_P_IP):
7065                         opts[0] |= TD1_GTSENV4;
7066                         break;
7067
7068                 case htons(ETH_P_IPV6):
7069                         if (msdn_giant_send_check(skb))
7070                                 return false;
7071
7072                         opts[0] |= TD1_GTSENV6;
7073                         break;
7074
7075                 default:
7076                         WARN_ON_ONCE(1);
7077                         break;
7078                 }
7079
7080                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7081                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7082         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7083                 u8 ip_protocol;
7084
7085                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7086                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7087
7088                 if (transport_offset > TCPHO_MAX) {
7089                         netif_warn(tp, tx_err, tp->dev,
7090                                    "Invalid transport offset 0x%x\n",
7091                                    transport_offset);
7092                         return false;
7093                 }
7094
7095                 switch (get_protocol(skb)) {
7096                 case htons(ETH_P_IP):
7097                         opts[1] |= TD1_IPv4_CS;
7098                         ip_protocol = ip_hdr(skb)->protocol;
7099                         break;
7100
7101                 case htons(ETH_P_IPV6):
7102                         opts[1] |= TD1_IPv6_CS;
7103                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7104                         break;
7105
7106                 default:
7107                         ip_protocol = IPPROTO_RAW;
7108                         break;
7109                 }
7110
7111                 if (ip_protocol == IPPROTO_TCP)
7112                         opts[1] |= TD1_TCP_CS;
7113                 else if (ip_protocol == IPPROTO_UDP)
7114                         opts[1] |= TD1_UDP_CS;
7115                 else
7116                         WARN_ON_ONCE(1);
7117
7118                 opts[1] |= transport_offset << TCPHO_SHIFT;
7119         } else {
7120                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7121                         return !eth_skb_pad(skb);
7122         }
7123
7124         return true;
7125 }
7126
7127 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7128                                       struct net_device *dev)
7129 {
7130         struct rtl8169_private *tp = netdev_priv(dev);
7131         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7132         struct TxDesc *txd = tp->TxDescArray + entry;
7133         struct device *d = tp_to_dev(tp);
7134         dma_addr_t mapping;
7135         u32 status, len;
7136         u32 opts[2];
7137         int frags;
7138
7139         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7140                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7141                 goto err_stop_0;
7142         }
7143
7144         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7145                 goto err_stop_0;
7146
7147         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7148         opts[0] = DescOwn;
7149
7150         if (!tp->tso_csum(tp, skb, opts)) {
7151                 r8169_csum_workaround(tp, skb);
7152                 return NETDEV_TX_OK;
7153         }
7154
7155         len = skb_headlen(skb);
7156         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7157         if (unlikely(dma_mapping_error(d, mapping))) {
7158                 if (net_ratelimit())
7159                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7160                 goto err_dma_0;
7161         }
7162
7163         tp->tx_skb[entry].len = len;
7164         txd->addr = cpu_to_le64(mapping);
7165
7166         frags = rtl8169_xmit_frags(tp, skb, opts);
7167         if (frags < 0)
7168                 goto err_dma_1;
7169         else if (frags)
7170                 opts[0] |= FirstFrag;
7171         else {
7172                 opts[0] |= FirstFrag | LastFrag;
7173                 tp->tx_skb[entry].skb = skb;
7174         }
7175
7176         txd->opts2 = cpu_to_le32(opts[1]);
7177
7178         skb_tx_timestamp(skb);
7179
7180         /* Force memory writes to complete before releasing descriptor */
7181         dma_wmb();
7182
7183         /* Anti gcc 2.95.3 bugware (sic) */
7184         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7185         txd->opts1 = cpu_to_le32(status);
7186
7187         /* Force all memory writes to complete before notifying device */
7188         wmb();
7189
7190         tp->cur_tx += frags + 1;
7191
7192         RTL_W8(tp, TxPoll, NPQ);
7193
7194         mmiowb();
7195
7196         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7197                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7198                  * not miss a ring update when it notices a stopped queue.
7199                  */
7200                 smp_wmb();
7201                 netif_stop_queue(dev);
7202                 /* Sync with rtl_tx:
7203                  * - publish queue status and cur_tx ring index (write barrier)
7204                  * - refresh dirty_tx ring index (read barrier).
7205                  * May the current thread have a pessimistic view of the ring
7206                  * status and forget to wake up queue, a racing rtl_tx thread
7207                  * can't.
7208                  */
7209                 smp_mb();
7210                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7211                         netif_wake_queue(dev);
7212         }
7213
7214         return NETDEV_TX_OK;
7215
7216 err_dma_1:
7217         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7218 err_dma_0:
7219         dev_kfree_skb_any(skb);
7220         dev->stats.tx_dropped++;
7221         return NETDEV_TX_OK;
7222
7223 err_stop_0:
7224         netif_stop_queue(dev);
7225         dev->stats.tx_dropped++;
7226         return NETDEV_TX_BUSY;
7227 }
7228
7229 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7230 {
7231         struct rtl8169_private *tp = netdev_priv(dev);
7232         struct pci_dev *pdev = tp->pci_dev;
7233         u16 pci_status, pci_cmd;
7234
7235         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7236         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7237
7238         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7239                   pci_cmd, pci_status);
7240
7241         /*
7242          * The recovery sequence below admits a very elaborated explanation:
7243          * - it seems to work;
7244          * - I did not see what else could be done;
7245          * - it makes iop3xx happy.
7246          *
7247          * Feel free to adjust to your needs.
7248          */
7249         if (pdev->broken_parity_status)
7250                 pci_cmd &= ~PCI_COMMAND_PARITY;
7251         else
7252                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7253
7254         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7255
7256         pci_write_config_word(pdev, PCI_STATUS,
7257                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7258                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7259                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7260
7261         /* The infamous DAC f*ckup only happens at boot time */
7262         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7263                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7264                 tp->cp_cmd &= ~PCIDAC;
7265                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7266                 dev->features &= ~NETIF_F_HIGHDMA;
7267         }
7268
7269         rtl8169_hw_reset(tp);
7270
7271         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7272 }
7273
7274 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7275 {
7276         unsigned int dirty_tx, tx_left;
7277
7278         dirty_tx = tp->dirty_tx;
7279         smp_rmb();
7280         tx_left = tp->cur_tx - dirty_tx;
7281
7282         while (tx_left > 0) {
7283                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7284                 struct ring_info *tx_skb = tp->tx_skb + entry;
7285                 u32 status;
7286
7287                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7288                 if (status & DescOwn)
7289                         break;
7290
7291                 /* This barrier is needed to keep us from reading
7292                  * any other fields out of the Tx descriptor until
7293                  * we know the status of DescOwn
7294                  */
7295                 dma_rmb();
7296
7297                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
7298                                      tp->TxDescArray + entry);
7299                 if (status & LastFrag) {
7300                         u64_stats_update_begin(&tp->tx_stats.syncp);
7301                         tp->tx_stats.packets++;
7302                         tp->tx_stats.bytes += tx_skb->skb->len;
7303                         u64_stats_update_end(&tp->tx_stats.syncp);
7304                         dev_consume_skb_any(tx_skb->skb);
7305                         tx_skb->skb = NULL;
7306                 }
7307                 dirty_tx++;
7308                 tx_left--;
7309         }
7310
7311         if (tp->dirty_tx != dirty_tx) {
7312                 tp->dirty_tx = dirty_tx;
7313                 /* Sync with rtl8169_start_xmit:
7314                  * - publish dirty_tx ring index (write barrier)
7315                  * - refresh cur_tx ring index and queue status (read barrier)
7316                  * May the current thread miss the stopped queue condition,
7317                  * a racing xmit thread can only have a right view of the
7318                  * ring status.
7319                  */
7320                 smp_mb();
7321                 if (netif_queue_stopped(dev) &&
7322                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7323                         netif_wake_queue(dev);
7324                 }
7325                 /*
7326                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7327                  * too close. Let's kick an extra TxPoll request when a burst
7328                  * of start_xmit activity is detected (if it is not detected,
7329                  * it is slow enough). -- FR
7330                  */
7331                 if (tp->cur_tx != dirty_tx)
7332                         RTL_W8(tp, TxPoll, NPQ);
7333         }
7334 }
7335
7336 static inline int rtl8169_fragmented_frame(u32 status)
7337 {
7338         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7339 }
7340
7341 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7342 {
7343         u32 status = opts1 & RxProtoMask;
7344
7345         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7346             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7347                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7348         else
7349                 skb_checksum_none_assert(skb);
7350 }
7351
7352 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7353                                            struct rtl8169_private *tp,
7354                                            int pkt_size,
7355                                            dma_addr_t addr)
7356 {
7357         struct sk_buff *skb;
7358         struct device *d = tp_to_dev(tp);
7359
7360         data = rtl8169_align(data);
7361         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7362         prefetch(data);
7363         skb = napi_alloc_skb(&tp->napi, pkt_size);
7364         if (skb)
7365                 memcpy(skb->data, data, pkt_size);
7366         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7367
7368         return skb;
7369 }
7370
7371 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7372 {
7373         unsigned int cur_rx, rx_left;
7374         unsigned int count;
7375
7376         cur_rx = tp->cur_rx;
7377
7378         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7379                 unsigned int entry = cur_rx % NUM_RX_DESC;
7380                 struct RxDesc *desc = tp->RxDescArray + entry;
7381                 u32 status;
7382
7383                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7384                 if (status & DescOwn)
7385                         break;
7386
7387                 /* This barrier is needed to keep us from reading
7388                  * any other fields out of the Rx descriptor until
7389                  * we know the status of DescOwn
7390                  */
7391                 dma_rmb();
7392
7393                 if (unlikely(status & RxRES)) {
7394                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7395                                    status);
7396                         dev->stats.rx_errors++;
7397                         if (status & (RxRWT | RxRUNT))
7398                                 dev->stats.rx_length_errors++;
7399                         if (status & RxCRC)
7400                                 dev->stats.rx_crc_errors++;
7401                         if (status & RxFOVF) {
7402                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7403                                 dev->stats.rx_fifo_errors++;
7404                         }
7405                         if ((status & (RxRUNT | RxCRC)) &&
7406                             !(status & (RxRWT | RxFOVF)) &&
7407                             (dev->features & NETIF_F_RXALL))
7408                                 goto process_pkt;
7409                 } else {
7410                         struct sk_buff *skb;
7411                         dma_addr_t addr;
7412                         int pkt_size;
7413
7414 process_pkt:
7415                         addr = le64_to_cpu(desc->addr);
7416                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7417                                 pkt_size = (status & 0x00003fff) - 4;
7418                         else
7419                                 pkt_size = status & 0x00003fff;
7420
7421                         /*
7422                          * The driver does not support incoming fragmented
7423                          * frames. They are seen as a symptom of over-mtu
7424                          * sized frames.
7425                          */
7426                         if (unlikely(rtl8169_fragmented_frame(status))) {
7427                                 dev->stats.rx_dropped++;
7428                                 dev->stats.rx_length_errors++;
7429                                 goto release_descriptor;
7430                         }
7431
7432                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7433                                                   tp, pkt_size, addr);
7434                         if (!skb) {
7435                                 dev->stats.rx_dropped++;
7436                                 goto release_descriptor;
7437                         }
7438
7439                         rtl8169_rx_csum(skb, status);
7440                         skb_put(skb, pkt_size);
7441                         skb->protocol = eth_type_trans(skb, dev);
7442
7443                         rtl8169_rx_vlan_tag(desc, skb);
7444
7445                         if (skb->pkt_type == PACKET_MULTICAST)
7446                                 dev->stats.multicast++;
7447
7448                         napi_gro_receive(&tp->napi, skb);
7449
7450                         u64_stats_update_begin(&tp->rx_stats.syncp);
7451                         tp->rx_stats.packets++;
7452                         tp->rx_stats.bytes += pkt_size;
7453                         u64_stats_update_end(&tp->rx_stats.syncp);
7454                 }
7455 release_descriptor:
7456                 desc->opts2 = 0;
7457                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7458         }
7459
7460         count = cur_rx - tp->cur_rx;
7461         tp->cur_rx = cur_rx;
7462
7463         return count;
7464 }
7465
7466 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7467 {
7468         struct net_device *dev = dev_instance;
7469         struct rtl8169_private *tp = netdev_priv(dev);
7470         int handled = 0;
7471         u16 status;
7472
7473         status = rtl_get_events(tp);
7474         if (status && status != 0xffff) {
7475                 status &= RTL_EVENT_NAPI | tp->event_slow;
7476                 if (status) {
7477                         handled = 1;
7478
7479                         rtl_irq_disable(tp);
7480                         napi_schedule(&tp->napi);
7481                 }
7482         }
7483         return IRQ_RETVAL(handled);
7484 }
7485
7486 /*
7487  * Workqueue context.
7488  */
7489 static void rtl_slow_event_work(struct rtl8169_private *tp)
7490 {
7491         struct net_device *dev = tp->dev;
7492         u16 status;
7493
7494         status = rtl_get_events(tp) & tp->event_slow;
7495         rtl_ack_events(tp, status);
7496
7497         if (unlikely(status & RxFIFOOver)) {
7498                 switch (tp->mac_version) {
7499                 /* Work around for rx fifo overflow */
7500                 case RTL_GIGA_MAC_VER_11:
7501                         netif_stop_queue(dev);
7502                         /* XXX - Hack alert. See rtl_task(). */
7503                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7504                 default:
7505                         break;
7506                 }
7507         }
7508
7509         if (unlikely(status & SYSErr))
7510                 rtl8169_pcierr_interrupt(dev);
7511
7512         if (status & LinkChg)
7513                 rtl8169_check_link_status(dev, tp);
7514
7515         rtl_irq_enable_all(tp);
7516 }
7517
7518 static void rtl_task(struct work_struct *work)
7519 {
7520         static const struct {
7521                 int bitnr;
7522                 void (*action)(struct rtl8169_private *);
7523         } rtl_work[] = {
7524                 /* XXX - keep rtl_slow_event_work() as first element. */
7525                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7526                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7527                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7528         };
7529         struct rtl8169_private *tp =
7530                 container_of(work, struct rtl8169_private, wk.work);
7531         struct net_device *dev = tp->dev;
7532         int i;
7533
7534         rtl_lock_work(tp);
7535
7536         if (!netif_running(dev) ||
7537             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7538                 goto out_unlock;
7539
7540         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7541                 bool pending;
7542
7543                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7544                 if (pending)
7545                         rtl_work[i].action(tp);
7546         }
7547
7548 out_unlock:
7549         rtl_unlock_work(tp);
7550 }
7551
7552 static int rtl8169_poll(struct napi_struct *napi, int budget)
7553 {
7554         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7555         struct net_device *dev = tp->dev;
7556         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7557         int work_done= 0;
7558         u16 status;
7559
7560         status = rtl_get_events(tp);
7561         rtl_ack_events(tp, status & ~tp->event_slow);
7562
7563         if (status & RTL_EVENT_NAPI_RX)
7564                 work_done = rtl_rx(dev, tp, (u32) budget);
7565
7566         if (status & RTL_EVENT_NAPI_TX)
7567                 rtl_tx(dev, tp);
7568
7569         if (status & tp->event_slow) {
7570                 enable_mask &= ~tp->event_slow;
7571
7572                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7573         }
7574
7575         if (work_done < budget) {
7576                 napi_complete_done(napi, work_done);
7577
7578                 rtl_irq_enable(tp, enable_mask);
7579                 mmiowb();
7580         }
7581
7582         return work_done;
7583 }
7584
7585 static void rtl8169_rx_missed(struct net_device *dev)
7586 {
7587         struct rtl8169_private *tp = netdev_priv(dev);
7588
7589         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7590                 return;
7591
7592         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
7593         RTL_W32(tp, RxMissed, 0);
7594 }
7595
7596 static void rtl8169_down(struct net_device *dev)
7597 {
7598         struct rtl8169_private *tp = netdev_priv(dev);
7599
7600         del_timer_sync(&tp->timer);
7601
7602         napi_disable(&tp->napi);
7603         netif_stop_queue(dev);
7604
7605         rtl8169_hw_reset(tp);
7606         /*
7607          * At this point device interrupts can not be enabled in any function,
7608          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7609          * and napi is disabled (rtl8169_poll).
7610          */
7611         rtl8169_rx_missed(dev);
7612
7613         /* Give a racing hard_start_xmit a few cycles to complete. */
7614         synchronize_sched();
7615
7616         rtl8169_tx_clear(tp);
7617
7618         rtl8169_rx_clear(tp);
7619
7620         rtl_pll_power_down(tp);
7621 }
7622
7623 static int rtl8169_close(struct net_device *dev)
7624 {
7625         struct rtl8169_private *tp = netdev_priv(dev);
7626         struct pci_dev *pdev = tp->pci_dev;
7627
7628         pm_runtime_get_sync(&pdev->dev);
7629
7630         /* Update counters before going down */
7631         rtl8169_update_counters(dev);
7632
7633         rtl_lock_work(tp);
7634         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7635
7636         rtl8169_down(dev);
7637         rtl_unlock_work(tp);
7638
7639         cancel_work_sync(&tp->wk.work);
7640
7641         pci_free_irq(pdev, 0, dev);
7642
7643         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7644                           tp->RxPhyAddr);
7645         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7646                           tp->TxPhyAddr);
7647         tp->TxDescArray = NULL;
7648         tp->RxDescArray = NULL;
7649
7650         pm_runtime_put_sync(&pdev->dev);
7651
7652         return 0;
7653 }
7654
7655 #ifdef CONFIG_NET_POLL_CONTROLLER
7656 static void rtl8169_netpoll(struct net_device *dev)
7657 {
7658         struct rtl8169_private *tp = netdev_priv(dev);
7659
7660         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), dev);
7661 }
7662 #endif
7663
7664 static int rtl_open(struct net_device *dev)
7665 {
7666         struct rtl8169_private *tp = netdev_priv(dev);
7667         struct pci_dev *pdev = tp->pci_dev;
7668         int retval = -ENOMEM;
7669
7670         pm_runtime_get_sync(&pdev->dev);
7671
7672         /*
7673          * Rx and Tx descriptors needs 256 bytes alignment.
7674          * dma_alloc_coherent provides more.
7675          */
7676         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7677                                              &tp->TxPhyAddr, GFP_KERNEL);
7678         if (!tp->TxDescArray)
7679                 goto err_pm_runtime_put;
7680
7681         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7682                                              &tp->RxPhyAddr, GFP_KERNEL);
7683         if (!tp->RxDescArray)
7684                 goto err_free_tx_0;
7685
7686         retval = rtl8169_init_ring(dev);
7687         if (retval < 0)
7688                 goto err_free_rx_1;
7689
7690         INIT_WORK(&tp->wk.work, rtl_task);
7691
7692         smp_mb();
7693
7694         rtl_request_firmware(tp);
7695
7696         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, dev,
7697                                  dev->name);
7698         if (retval < 0)
7699                 goto err_release_fw_2;
7700
7701         rtl_lock_work(tp);
7702
7703         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7704
7705         napi_enable(&tp->napi);
7706
7707         rtl8169_init_phy(dev, tp);
7708
7709         __rtl8169_set_features(dev, dev->features);
7710
7711         rtl_pll_power_up(tp);
7712
7713         rtl_hw_start(dev);
7714
7715         if (!rtl8169_init_counter_offsets(dev))
7716                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7717
7718         netif_start_queue(dev);
7719
7720         rtl_unlock_work(tp);
7721
7722         tp->saved_wolopts = 0;
7723         pm_runtime_put_sync(&pdev->dev);
7724
7725         rtl8169_check_link_status(dev, tp);
7726 out:
7727         return retval;
7728
7729 err_release_fw_2:
7730         rtl_release_firmware(tp);
7731         rtl8169_rx_clear(tp);
7732 err_free_rx_1:
7733         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7734                           tp->RxPhyAddr);
7735         tp->RxDescArray = NULL;
7736 err_free_tx_0:
7737         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7738                           tp->TxPhyAddr);
7739         tp->TxDescArray = NULL;
7740 err_pm_runtime_put:
7741         pm_runtime_put_noidle(&pdev->dev);
7742         goto out;
7743 }
7744
7745 static void
7746 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7747 {
7748         struct rtl8169_private *tp = netdev_priv(dev);
7749         struct pci_dev *pdev = tp->pci_dev;
7750         struct rtl8169_counters *counters = tp->counters;
7751         unsigned int start;
7752
7753         pm_runtime_get_noresume(&pdev->dev);
7754
7755         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7756                 rtl8169_rx_missed(dev);
7757
7758         do {
7759                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7760                 stats->rx_packets = tp->rx_stats.packets;
7761                 stats->rx_bytes = tp->rx_stats.bytes;
7762         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7763
7764         do {
7765                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7766                 stats->tx_packets = tp->tx_stats.packets;
7767                 stats->tx_bytes = tp->tx_stats.bytes;
7768         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7769
7770         stats->rx_dropped       = dev->stats.rx_dropped;
7771         stats->tx_dropped       = dev->stats.tx_dropped;
7772         stats->rx_length_errors = dev->stats.rx_length_errors;
7773         stats->rx_errors        = dev->stats.rx_errors;
7774         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7775         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7776         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7777         stats->multicast        = dev->stats.multicast;
7778
7779         /*
7780          * Fetch additonal counter values missing in stats collected by driver
7781          * from tally counters.
7782          */
7783         if (pm_runtime_active(&pdev->dev))
7784                 rtl8169_update_counters(dev);
7785
7786         /*
7787          * Subtract values fetched during initalization.
7788          * See rtl8169_init_counter_offsets for a description why we do that.
7789          */
7790         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7791                 le64_to_cpu(tp->tc_offset.tx_errors);
7792         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7793                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7794         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7795                 le16_to_cpu(tp->tc_offset.tx_aborted);
7796
7797         pm_runtime_put_noidle(&pdev->dev);
7798 }
7799
7800 static void rtl8169_net_suspend(struct net_device *dev)
7801 {
7802         struct rtl8169_private *tp = netdev_priv(dev);
7803
7804         if (!netif_running(dev))
7805                 return;
7806
7807         netif_device_detach(dev);
7808         netif_stop_queue(dev);
7809
7810         rtl_lock_work(tp);
7811         napi_disable(&tp->napi);
7812         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7813         rtl_unlock_work(tp);
7814
7815         rtl_pll_power_down(tp);
7816 }
7817
7818 #ifdef CONFIG_PM
7819
7820 static int rtl8169_suspend(struct device *device)
7821 {
7822         struct pci_dev *pdev = to_pci_dev(device);
7823         struct net_device *dev = pci_get_drvdata(pdev);
7824
7825         rtl8169_net_suspend(dev);
7826
7827         return 0;
7828 }
7829
7830 static void __rtl8169_resume(struct net_device *dev)
7831 {
7832         struct rtl8169_private *tp = netdev_priv(dev);
7833
7834         netif_device_attach(dev);
7835
7836         rtl_pll_power_up(tp);
7837
7838         rtl_lock_work(tp);
7839         napi_enable(&tp->napi);
7840         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7841         rtl_unlock_work(tp);
7842
7843         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7844 }
7845
7846 static int rtl8169_resume(struct device *device)
7847 {
7848         struct pci_dev *pdev = to_pci_dev(device);
7849         struct net_device *dev = pci_get_drvdata(pdev);
7850         struct rtl8169_private *tp = netdev_priv(dev);
7851
7852         rtl8169_init_phy(dev, tp);
7853
7854         if (netif_running(dev))
7855                 __rtl8169_resume(dev);
7856
7857         return 0;
7858 }
7859
7860 static int rtl8169_runtime_suspend(struct device *device)
7861 {
7862         struct pci_dev *pdev = to_pci_dev(device);
7863         struct net_device *dev = pci_get_drvdata(pdev);
7864         struct rtl8169_private *tp = netdev_priv(dev);
7865
7866         if (!tp->TxDescArray) {
7867                 rtl_pll_power_down(tp);
7868                 return 0;
7869         }
7870
7871         rtl_lock_work(tp);
7872         tp->saved_wolopts = __rtl8169_get_wol(tp);
7873         __rtl8169_set_wol(tp, WAKE_ANY);
7874         rtl_unlock_work(tp);
7875
7876         rtl8169_net_suspend(dev);
7877
7878         /* Update counters before going runtime suspend */
7879         rtl8169_rx_missed(dev);
7880         rtl8169_update_counters(dev);
7881
7882         return 0;
7883 }
7884
7885 static int rtl8169_runtime_resume(struct device *device)
7886 {
7887         struct pci_dev *pdev = to_pci_dev(device);
7888         struct net_device *dev = pci_get_drvdata(pdev);
7889         struct rtl8169_private *tp = netdev_priv(dev);
7890         rtl_rar_set(tp, dev->dev_addr);
7891
7892         if (!tp->TxDescArray)
7893                 return 0;
7894
7895         rtl_lock_work(tp);
7896         __rtl8169_set_wol(tp, tp->saved_wolopts);
7897         tp->saved_wolopts = 0;
7898         rtl_unlock_work(tp);
7899
7900         rtl8169_init_phy(dev, tp);
7901
7902         __rtl8169_resume(dev);
7903
7904         return 0;
7905 }
7906
7907 static int rtl8169_runtime_idle(struct device *device)
7908 {
7909         struct pci_dev *pdev = to_pci_dev(device);
7910         struct net_device *dev = pci_get_drvdata(pdev);
7911
7912         if (!netif_running(dev) || !netif_carrier_ok(dev))
7913                 pm_schedule_suspend(device, 10000);
7914
7915         return -EBUSY;
7916 }
7917
7918 static const struct dev_pm_ops rtl8169_pm_ops = {
7919         .suspend                = rtl8169_suspend,
7920         .resume                 = rtl8169_resume,
7921         .freeze                 = rtl8169_suspend,
7922         .thaw                   = rtl8169_resume,
7923         .poweroff               = rtl8169_suspend,
7924         .restore                = rtl8169_resume,
7925         .runtime_suspend        = rtl8169_runtime_suspend,
7926         .runtime_resume         = rtl8169_runtime_resume,
7927         .runtime_idle           = rtl8169_runtime_idle,
7928 };
7929
7930 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7931
7932 #else /* !CONFIG_PM */
7933
7934 #define RTL8169_PM_OPS  NULL
7935
7936 #endif /* !CONFIG_PM */
7937
7938 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7939 {
7940         /* WoL fails with 8168b when the receiver is disabled. */
7941         switch (tp->mac_version) {
7942         case RTL_GIGA_MAC_VER_11:
7943         case RTL_GIGA_MAC_VER_12:
7944         case RTL_GIGA_MAC_VER_17:
7945                 pci_clear_master(tp->pci_dev);
7946
7947                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7948                 /* PCI commit */
7949                 RTL_R8(tp, ChipCmd);
7950                 break;
7951         default:
7952                 break;
7953         }
7954 }
7955
7956 static void rtl_shutdown(struct pci_dev *pdev)
7957 {
7958         struct net_device *dev = pci_get_drvdata(pdev);
7959         struct rtl8169_private *tp = netdev_priv(dev);
7960
7961         rtl8169_net_suspend(dev);
7962
7963         /* Restore original MAC address */
7964         rtl_rar_set(tp, dev->perm_addr);
7965
7966         rtl8169_hw_reset(tp);
7967
7968         if (system_state == SYSTEM_POWER_OFF) {
7969                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7970                         rtl_wol_suspend_quirk(tp);
7971                         rtl_wol_shutdown_quirk(tp);
7972                 }
7973
7974                 pci_wake_from_d3(pdev, true);
7975                 pci_set_power_state(pdev, PCI_D3hot);
7976         }
7977 }
7978
7979 static void rtl_remove_one(struct pci_dev *pdev)
7980 {
7981         struct net_device *dev = pci_get_drvdata(pdev);
7982         struct rtl8169_private *tp = netdev_priv(dev);
7983
7984         if (r8168_check_dash(tp))
7985                 rtl8168_driver_stop(tp);
7986
7987         netif_napi_del(&tp->napi);
7988
7989         unregister_netdev(dev);
7990
7991         rtl_release_firmware(tp);
7992
7993         if (pci_dev_run_wake(pdev))
7994                 pm_runtime_get_noresume(&pdev->dev);
7995
7996         /* restore original MAC address */
7997         rtl_rar_set(tp, dev->perm_addr);
7998 }
7999
8000 static const struct net_device_ops rtl_netdev_ops = {
8001         .ndo_open               = rtl_open,
8002         .ndo_stop               = rtl8169_close,
8003         .ndo_get_stats64        = rtl8169_get_stats64,
8004         .ndo_start_xmit         = rtl8169_start_xmit,
8005         .ndo_tx_timeout         = rtl8169_tx_timeout,
8006         .ndo_validate_addr      = eth_validate_addr,
8007         .ndo_change_mtu         = rtl8169_change_mtu,
8008         .ndo_fix_features       = rtl8169_fix_features,
8009         .ndo_set_features       = rtl8169_set_features,
8010         .ndo_set_mac_address    = rtl_set_mac_address,
8011         .ndo_do_ioctl           = rtl8169_ioctl,
8012         .ndo_set_rx_mode        = rtl_set_rx_mode,
8013 #ifdef CONFIG_NET_POLL_CONTROLLER
8014         .ndo_poll_controller    = rtl8169_netpoll,
8015 #endif
8016
8017 };
8018
8019 static const struct rtl_cfg_info {
8020         void (*hw_start)(struct net_device *);
8021         unsigned int region;
8022         unsigned int align;
8023         u16 event_slow;
8024         unsigned int has_gmii:1;
8025         const struct rtl_coalesce_info *coalesce_info;
8026         u8 default_ver;
8027 } rtl_cfg_infos [] = {
8028         [RTL_CFG_0] = {
8029                 .hw_start       = rtl_hw_start_8169,
8030                 .region         = 1,
8031                 .align          = 0,
8032                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8033                 .has_gmii       = 1,
8034                 .coalesce_info  = rtl_coalesce_info_8169,
8035                 .default_ver    = RTL_GIGA_MAC_VER_01,
8036         },
8037         [RTL_CFG_1] = {
8038                 .hw_start       = rtl_hw_start_8168,
8039                 .region         = 2,
8040                 .align          = 8,
8041                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8042                 .has_gmii       = 1,
8043                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8044                 .default_ver    = RTL_GIGA_MAC_VER_11,
8045         },
8046         [RTL_CFG_2] = {
8047                 .hw_start       = rtl_hw_start_8101,
8048                 .region         = 2,
8049                 .align          = 8,
8050                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8051                                   PCSTimeout,
8052                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8053                 .default_ver    = RTL_GIGA_MAC_VER_13,
8054         }
8055 };
8056
8057 static int rtl_alloc_irq(struct rtl8169_private *tp)
8058 {
8059         unsigned int flags;
8060
8061         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
8062                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
8063                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
8064                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
8065                 flags = PCI_IRQ_LEGACY;
8066         } else {
8067                 flags = PCI_IRQ_ALL_TYPES;
8068         }
8069
8070         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
8071 }
8072
8073 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8074 {
8075         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
8076 }
8077
8078 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8079 {
8080         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8081 }
8082
8083 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8084 {
8085         u32 data;
8086
8087         tp->ocp_base = OCP_STD_PHY_BASE;
8088
8089         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
8090
8091         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8092                 return;
8093
8094         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8095                 return;
8096
8097         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8098         msleep(1);
8099         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
8100
8101         data = r8168_mac_ocp_read(tp, 0xe8de);
8102         data &= ~(1 << 14);
8103         r8168_mac_ocp_write(tp, 0xe8de, data);
8104
8105         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8106                 return;
8107
8108         data = r8168_mac_ocp_read(tp, 0xe8de);
8109         data |= (1 << 15);
8110         r8168_mac_ocp_write(tp, 0xe8de, data);
8111
8112         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8113                 return;
8114 }
8115
8116 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8117 {
8118         rtl8168ep_stop_cmac(tp);
8119         rtl_hw_init_8168g(tp);
8120 }
8121
8122 static void rtl_hw_initialize(struct rtl8169_private *tp)
8123 {
8124         switch (tp->mac_version) {
8125         case RTL_GIGA_MAC_VER_40:
8126         case RTL_GIGA_MAC_VER_41:
8127         case RTL_GIGA_MAC_VER_42:
8128         case RTL_GIGA_MAC_VER_43:
8129         case RTL_GIGA_MAC_VER_44:
8130         case RTL_GIGA_MAC_VER_45:
8131         case RTL_GIGA_MAC_VER_46:
8132         case RTL_GIGA_MAC_VER_47:
8133         case RTL_GIGA_MAC_VER_48:
8134                 rtl_hw_init_8168g(tp);
8135                 break;
8136         case RTL_GIGA_MAC_VER_49:
8137         case RTL_GIGA_MAC_VER_50:
8138         case RTL_GIGA_MAC_VER_51:
8139                 rtl_hw_init_8168ep(tp);
8140                 break;
8141         default:
8142                 break;
8143         }
8144 }
8145
8146 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8147 {
8148         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8149         const unsigned int region = cfg->region;
8150         struct rtl8169_private *tp;
8151         struct mii_if_info *mii;
8152         struct net_device *dev;
8153         int chipset, i;
8154         int rc;
8155
8156         if (netif_msg_drv(&debug)) {
8157                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8158                        MODULENAME, RTL8169_VERSION);
8159         }
8160
8161         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8162         if (!dev)
8163                 return -ENOMEM;
8164
8165         SET_NETDEV_DEV(dev, &pdev->dev);
8166         dev->netdev_ops = &rtl_netdev_ops;
8167         tp = netdev_priv(dev);
8168         tp->dev = dev;
8169         tp->pci_dev = pdev;
8170         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8171
8172         mii = &tp->mii;
8173         mii->dev = dev;
8174         mii->mdio_read = rtl_mdio_read;
8175         mii->mdio_write = rtl_mdio_write;
8176         mii->phy_id_mask = 0x1f;
8177         mii->reg_num_mask = 0x1f;
8178         mii->supports_gmii = cfg->has_gmii;
8179
8180         /* disable ASPM completely as that cause random device stop working
8181          * problems as well as full system hangs for some PCIe devices users */
8182         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8183                                      PCIE_LINK_STATE_CLKPM);
8184
8185         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8186         rc = pcim_enable_device(pdev);
8187         if (rc < 0) {
8188                 netif_err(tp, probe, dev, "enable failure\n");
8189                 return rc;
8190         }
8191
8192         if (pcim_set_mwi(pdev) < 0)
8193                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8194
8195         /* make sure PCI base addr 1 is MMIO */
8196         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8197                 netif_err(tp, probe, dev,
8198                           "region #%d not an MMIO resource, aborting\n",
8199                           region);
8200                 return -ENODEV;
8201         }
8202
8203         /* check for weird/broken PCI region reporting */
8204         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8205                 netif_err(tp, probe, dev,
8206                           "Invalid PCI region size(s), aborting\n");
8207                 return -ENODEV;
8208         }
8209
8210         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
8211         if (rc < 0) {
8212                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8213                 return rc;
8214         }
8215
8216         tp->mmio_addr = pcim_iomap_table(pdev)[region];
8217
8218         if (!pci_is_pcie(pdev))
8219                 netif_info(tp, probe, dev, "not PCI Express\n");
8220
8221         /* Identify chip attached to board */
8222         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8223
8224         tp->cp_cmd = 0;
8225
8226         if ((sizeof(dma_addr_t) > 4) &&
8227             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8228                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8229             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8230             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8231
8232                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8233                 if (!pci_is_pcie(pdev))
8234                         tp->cp_cmd |= PCIDAC;
8235                 dev->features |= NETIF_F_HIGHDMA;
8236         } else {
8237                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8238                 if (rc < 0) {
8239                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8240                         return rc;
8241                 }
8242         }
8243
8244         rtl_init_rxcfg(tp);
8245
8246         rtl_irq_disable(tp);
8247
8248         rtl_hw_initialize(tp);
8249
8250         rtl_hw_reset(tp);
8251
8252         rtl_ack_events(tp, 0xffff);
8253
8254         pci_set_master(pdev);
8255
8256         rtl_init_mdio_ops(tp);
8257         rtl_init_pll_power_ops(tp);
8258         rtl_init_jumbo_ops(tp);
8259         rtl_init_csi_ops(tp);
8260
8261         rtl8169_print_mac_version(tp);
8262
8263         chipset = tp->mac_version;
8264         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8265
8266         rc = rtl_alloc_irq(tp);
8267         if (rc < 0) {
8268                 netif_err(tp, probe, dev, "Can't allocate interrupt\n");
8269                 return rc;
8270         }
8271
8272         /* override BIOS settings, use userspace tools to enable WOL */
8273         __rtl8169_set_wol(tp, 0);
8274
8275         if (rtl_tbi_enabled(tp)) {
8276                 tp->set_speed = rtl8169_set_speed_tbi;
8277                 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8278                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8279                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8280                 tp->link_ok = rtl8169_tbi_link_ok;
8281                 tp->do_ioctl = rtl_tbi_ioctl;
8282         } else {
8283                 tp->set_speed = rtl8169_set_speed_xmii;
8284                 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8285                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8286                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8287                 tp->link_ok = rtl8169_xmii_link_ok;
8288                 tp->do_ioctl = rtl_xmii_ioctl;
8289         }
8290
8291         mutex_init(&tp->wk.mutex);
8292         u64_stats_init(&tp->rx_stats.syncp);
8293         u64_stats_init(&tp->tx_stats.syncp);
8294
8295         /* Get MAC address */
8296         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8297             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8298             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8299             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8300             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8301             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8302             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8303             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8304             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8305             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8306             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8307             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8308             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8309             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8310             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8311             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8312                 u16 mac_addr[3];
8313
8314                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8315                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8316
8317                 if (is_valid_ether_addr((u8 *)mac_addr))
8318                         rtl_rar_set(tp, (u8 *)mac_addr);
8319         }
8320         for (i = 0; i < ETH_ALEN; i++)
8321                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
8322
8323         dev->ethtool_ops = &rtl8169_ethtool_ops;
8324         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8325
8326         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8327
8328         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8329          * properly for all devices */
8330         dev->features |= NETIF_F_RXCSUM |
8331                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8332
8333         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8334                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8335                 NETIF_F_HW_VLAN_CTAG_RX;
8336         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8337                 NETIF_F_HIGHDMA;
8338
8339         tp->cp_cmd |= RxChkSum | RxVlan;
8340
8341         /*
8342          * Pretend we are using VLANs; This bypasses a nasty bug where
8343          * Interrupts stop flowing on high load on 8110SCd controllers.
8344          */
8345         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8346                 /* Disallow toggling */
8347                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8348
8349         if (tp->txd_version == RTL_TD_0)
8350                 tp->tso_csum = rtl8169_tso_csum_v1;
8351         else if (tp->txd_version == RTL_TD_1) {
8352                 tp->tso_csum = rtl8169_tso_csum_v2;
8353                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8354         } else
8355                 WARN_ON_ONCE(1);
8356
8357         dev->hw_features |= NETIF_F_RXALL;
8358         dev->hw_features |= NETIF_F_RXFCS;
8359
8360         /* MTU range: 60 - hw-specific max */
8361         dev->min_mtu = ETH_ZLEN;
8362         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8363
8364         tp->hw_start = cfg->hw_start;
8365         tp->event_slow = cfg->event_slow;
8366         tp->coalesce_info = cfg->coalesce_info;
8367
8368         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8369                 ~(RxBOVF | RxFOVF) : ~0;
8370
8371         timer_setup(&tp->timer, rtl8169_phy_timer, 0);
8372
8373         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8374
8375         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8376                                             &tp->counters_phys_addr,
8377                                             GFP_KERNEL);
8378         if (!tp->counters)
8379                 return -ENOMEM;
8380
8381         pci_set_drvdata(pdev, dev);
8382
8383         rc = register_netdev(dev);
8384         if (rc < 0)
8385                 return rc;
8386
8387         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8388                    rtl_chip_infos[chipset].name, tp->mmio_addr, dev->dev_addr,
8389                    (u32)(RTL_R32(tp, TxConfig) & 0x9cf0f8ff),
8390                    pci_irq_vector(pdev, 0));
8391         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8392                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8393                            "tx checksumming: %s]\n",
8394                            rtl_chip_infos[chipset].jumbo_max,
8395                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8396         }
8397
8398         if (r8168_check_dash(tp))
8399                 rtl8168_driver_start(tp);
8400
8401         netif_carrier_off(dev);
8402
8403         if (pci_dev_run_wake(pdev))
8404                 pm_runtime_put_sync(&pdev->dev);
8405
8406         return 0;
8407 }
8408
8409 static struct pci_driver rtl8169_pci_driver = {
8410         .name           = MODULENAME,
8411         .id_table       = rtl8169_pci_tbl,
8412         .probe          = rtl_init_one,
8413         .remove         = rtl_remove_one,
8414         .shutdown       = rtl_shutdown,
8415         .driver.pm      = RTL8169_PM_OPS,
8416 };
8417
8418 module_pci_driver(rtl8169_pci_driver);