drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/string.h>
  41 #include <linux/etherdevice.h>
  42 #include "qed.h"
  43 #include "qed_cxt.h"
  44 #include "qed_dcbx.h"
  45 #include "qed_hsi.h"
  46 #include "qed_hw.h"
  47 #include "qed_mcp.h"
  48 #include "qed_reg_addr.h"
  49 #include "qed_sriov.h"
  50
  51 #define QED_MCP_RESP_ITER_US    10
  52
  53 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  54 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  55
  56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  57         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  58                _val)
  59
  60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  61         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  62
  63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  64         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  65                      offsetof(struct public_drv_mb, _field), _val)
  66
  67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  68         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  69                      offsetof(struct public_drv_mb, _field))
  70
  71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  72                   DRV_ID_PDA_COMP_VER_SHIFT)
  73
  74 #define MCP_BYTES_PER_MBIT_SHIFT 17
  75
  76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  77 {
  78         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  79                 return false;
  80         return true;
  81 }
  82
  83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  84 {
  85         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  86                                         PUBLIC_PORT);
  87         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  88
  89         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  90                                                    MFW_PORT(p_hwfn));
  91         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  92                    "port_addr = 0x%x, port_id 0x%02x\n",
  93                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  94 }
  95
  96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  97 {
  98         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  99         u32 tmp, i;
 100
 101         if (!p_hwfn->mcp_info->public_base)
 102                 return;
 103
 104         for (i = 0; i < length; i++) {
 105                 tmp = qed_rd(p_hwfn, p_ptt,
 106                              p_hwfn->mcp_info->mfw_mb_addr +
 107                              (i << 2) + sizeof(u32));
 108
 109                 /* The MB data is actually BE; Need to force it to cpu */
 110                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
 111                         be32_to_cpu((__force __be32)tmp);
 112         }
 113 }
 114
 115 struct qed_mcp_cmd_elem {
 116         struct list_head list;
 117         struct qed_mcp_mb_params *p_mb_params;
 118         u16 expected_seq_num;
 119         bool b_is_completed;
 120 };
 121
 122 /* Must be called while cmd_lock is acquired */
 123 static struct qed_mcp_cmd_elem *
 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
 125                      struct qed_mcp_mb_params *p_mb_params,
 126                      u16 expected_seq_num)
 127 {
 128         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 129
 130         p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
 131         if (!p_cmd_elem)
 132                 goto out;
 133
 134         p_cmd_elem->p_mb_params = p_mb_params;
 135         p_cmd_elem->expected_seq_num = expected_seq_num;
 136         list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 137 out:
 138         return p_cmd_elem;
 139 }
 140
 141 /* Must be called while cmd_lock is acquired */
 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
 143                                  struct qed_mcp_cmd_elem *p_cmd_elem)
 144 {
 145         list_del(&p_cmd_elem->list);
 146         kfree(p_cmd_elem);
 147 }
 148
 149 /* Must be called while cmd_lock is acquired */
 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
 151                                                      u16 seq_num)
 152 {
 153         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 154
 155         list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
 156                 if (p_cmd_elem->expected_seq_num == seq_num)
 157                         return p_cmd_elem;
 158         }
 159
 160         return NULL;
 161 }
 162
 163 int qed_mcp_free(struct qed_hwfn *p_hwfn)
 164 {
 165         if (p_hwfn->mcp_info) {
 166                 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
 167
 168                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
 169                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
 170
 171                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 172                 list_for_each_entry_safe(p_cmd_elem,
 173                                          p_tmp,
 174                                          &p_hwfn->mcp_info->cmd_list, list) {
 175                         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 176                 }
 177                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 178         }
 179
 180         kfree(p_hwfn->mcp_info);
 181         p_hwfn->mcp_info = NULL;
 182
 183         return 0;
 184 }
 185
 186 /* Maximum of 1 sec to wait for the SHMEM ready indication */
 187 #define QED_MCP_SHMEM_RDY_MAX_RETRIES   20
 188 #define QED_MCP_SHMEM_RDY_ITER_MS       50
 189
 190 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 191 {
 192         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 193         u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES;
 194         u8 msec = QED_MCP_SHMEM_RDY_ITER_MS;
 195         u32 drv_mb_offsize, mfw_mb_offsize;
 196         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 197
 198         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 199         if (!p_info->public_base) {
 200                 DP_NOTICE(p_hwfn,
 201                           "The address of the MCP scratch-pad is not configured\n");
 202                 return -EINVAL;
 203         }
 204
 205         p_info->public_base |= GRCBASE_MCP;
 206
 207         /* Get the MFW MB address and number of supported messages */
 208         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 209                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 210                                                      PUBLIC_MFW_MB));
 211         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 212         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt,
 213                                             p_info->mfw_mb_addr +
 214                                             offsetof(struct public_mfw_mb,
 215                                                      sup_msgs));
 216
 217         /* The driver can notify that there was an MCP reset, and might read the
 218          * SHMEM values before the MFW has completed initializing them.
 219          * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a
 220          * data ready indication.
 221          */
 222         while (!p_info->mfw_mb_length && --cnt) {
 223                 msleep(msec);
 224                 p_info->mfw_mb_length =
 225                         (u16)qed_rd(p_hwfn, p_ptt,
 226                                     p_info->mfw_mb_addr +
 227                                     offsetof(struct public_mfw_mb, sup_msgs));
 228         }
 229
 230         if (!cnt) {
 231                 DP_NOTICE(p_hwfn,
 232                           "Failed to get the SHMEM ready notification after %d msec\n",
 233                           QED_MCP_SHMEM_RDY_MAX_RETRIES * msec);
 234                 return -EBUSY;
 235         }
 236
 237         /* Calculate the driver and MFW mailbox address */
 238         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 239                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 240                                                      PUBLIC_DRV_MB));
 241         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 242         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 243                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 244                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 245
 246         /* Get the current driver mailbox sequence before sending
 247          * the first command
 248          */
 249         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 250                              DRV_MSG_SEQ_NUMBER_MASK;
 251
 252         /* Get current FW pulse sequence */
 253         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 254                                 DRV_PULSE_SEQ_MASK;
 255
 256         p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 257
 258         return 0;
 259 }
 260
 261 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 262 {
 263         struct qed_mcp_info *p_info;
 264         u32 size;
 265
 266         /* Allocate mcp_info structure */
 267         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 268         if (!p_hwfn->mcp_info)
 269                 goto err;
 270         p_info = p_hwfn->mcp_info;
 271
 272         /* Initialize the MFW spinlock */
 273         spin_lock_init(&p_info->cmd_lock);
 274         spin_lock_init(&p_info->link_lock);
 275
 276         INIT_LIST_HEAD(&p_info->cmd_list);
 277
 278         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 279                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 280                 /* Do not free mcp_info here, since public_base indicate that
 281                  * the MCP is not initialized
 282                  */
 283                 return 0;
 284         }
 285
 286         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 287         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 288         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 289         if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
 290                 goto err;
 291
 292         return 0;
 293
 294 err:
 295         qed_mcp_free(p_hwfn);
 296         return -ENOMEM;
 297 }
 298
 299 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
 300                                    struct qed_ptt *p_ptt)
 301 {
 302         u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 303
 304         /* Use MCP history register to check if MCP reset occurred between init
 305          * time and now.
 306          */
 307         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 308                 DP_VERBOSE(p_hwfn,
 309                            QED_MSG_SP,
 310                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 311                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 312
 313                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 314                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 315         }
 316 }
 317
 318 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 319 {
 320         u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0;
 321         int rc = 0;
 322
 323         if (p_hwfn->mcp_info->b_block_cmd) {
 324                 DP_NOTICE(p_hwfn,
 325                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 326                 return -EBUSY;
 327         }
 328
 329         /* Ensure that only a single thread is accessing the mailbox */
 330         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 331
 332         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 333
 334         /* Set drv command along with the updated sequence */
 335         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 336         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 337         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 338
 339         do {
 340                 /* Wait for MFW response */
 341                 udelay(delay);
 342                 /* Give the FW up to 500 second (50*1000*10usec) */
 343         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 344                                               MISCS_REG_GENERIC_POR_0)) &&
 345                  (cnt++ < QED_MCP_RESET_RETRIES));
 346
 347         if (org_mcp_reset_seq !=
 348             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 349                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 350                            "MCP was reset after %d usec\n", cnt * delay);
 351         } else {
 352                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 353                 rc = -EAGAIN;
 354         }
 355
 356         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 357
 358         return rc;
 359 }
 360
 361 /* Must be called while cmd_lock is acquired */
 362 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
 363 {
 364         struct qed_mcp_cmd_elem *p_cmd_elem;
 365
 366         /* There is at most one pending command at a certain time, and if it
 367          * exists - it is placed at the HEAD of the list.
 368          */
 369         if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
 370                 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
 371                                               struct qed_mcp_cmd_elem, list);
 372                 return !p_cmd_elem->b_is_completed;
 373         }
 374
 375         return false;
 376 }
 377
 378 /* Must be called while cmd_lock is acquired */
 379 static int
 380 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 381 {
 382         struct qed_mcp_mb_params *p_mb_params;
 383         struct qed_mcp_cmd_elem *p_cmd_elem;
 384         u32 mcp_resp;
 385         u16 seq_num;
 386
 387         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 388         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 389
 390         /* Return if no new non-handled response has been received */
 391         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 392                 return -EAGAIN;
 393
 394         p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
 395         if (!p_cmd_elem) {
 396                 DP_ERR(p_hwfn,
 397                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 398                        seq_num);
 399                 return -EINVAL;
 400         }
 401
 402         p_mb_params = p_cmd_elem->p_mb_params;
 403
 404         /* Get the MFW response along with the sequence number */
 405         p_mb_params->mcp_resp = mcp_resp;
 406
 407         /* Get the MFW param */
 408         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 409
 410         /* Get the union data */
 411         if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
 412                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 413                                       offsetof(struct public_drv_mb,
 414                                                union_data);
 415                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 416                                 union_data_addr, p_mb_params->data_dst_size);
 417         }
 418
 419         p_cmd_elem->b_is_completed = true;
 420
 421         return 0;
 422 }
 423
 424 /* Must be called while cmd_lock is acquired */
 425 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 426                                     struct qed_ptt *p_ptt,
 427                                     struct qed_mcp_mb_params *p_mb_params,
 428                                     u16 seq_num)
 429 {
 430         union drv_union_data union_data;
 431         u32 union_data_addr;
 432
 433         /* Set the union data */
 434         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 435                           offsetof(struct public_drv_mb, union_data);
 436         memset(&union_data, 0, sizeof(union_data));
 437         if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
 438                 memcpy(&union_data, p_mb_params->p_data_src,
 439                        p_mb_params->data_src_size);
 440         qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 441                       sizeof(union_data));
 442
 443         /* Set the drv param */
 444         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 445
 446         /* Set the drv command along with the sequence number */
 447         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 448
 449         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 450                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 451                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 452 }
 453
 454 static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd)
 455 {
 456         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 457
 458         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 459                 block_cmd ? "Block" : "Unblock");
 460 }
 461
 462 static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn,
 463                                    struct qed_ptt *p_ptt)
 464 {
 465         u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2;
 466         u32 delay = QED_MCP_RESP_ITER_US;
 467
 468         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
 469         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
 470         cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 471         udelay(delay);
 472         cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 473         udelay(delay);
 474         cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 475
 476         DP_NOTICE(p_hwfn,
 477                   "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n",
 478                   cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2);
 479 }
 480
 481 static int
 482 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 483                        struct qed_ptt *p_ptt,
 484                        struct qed_mcp_mb_params *p_mb_params,
 485                        u32 max_retries, u32 usecs)
 486 {
 487         u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000);
 488         struct qed_mcp_cmd_elem *p_cmd_elem;
 489         u16 seq_num;
 490         int rc = 0;
 491
 492         /* Wait until the mailbox is non-occupied */
 493         do {
 494                 /* Exit the loop if there is no pending command, or if the
 495                  * pending command is completed during this iteration.
 496                  * The spinlock stays locked until the command is sent.
 497                  */
 498
 499                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 500
 501                 if (!qed_mcp_has_pending_cmd(p_hwfn))
 502                         break;
 503
 504                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 505                 if (!rc)
 506                         break;
 507                 else if (rc != -EAGAIN)
 508                         goto err;
 509
 510                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 511
 512                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 513                         msleep(msecs);
 514                 else
 515                         udelay(usecs);
 516         } while (++cnt < max_retries);
 517
 518         if (cnt >= max_retries) {
 519                 DP_NOTICE(p_hwfn,
 520                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 521                           p_mb_params->cmd, p_mb_params->param);
 522                 return -EAGAIN;
 523         }
 524
 525         /* Send the mailbox command */
 526         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 527         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 528         p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 529         if (!p_cmd_elem) {
 530                 rc = -ENOMEM;
 531                 goto err;
 532         }
 533
 534         __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 535         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 536
 537         /* Wait for the MFW response */
 538         do {
 539                 /* Exit the loop if the command is already completed, or if the
 540                  * command is completed during this iteration.
 541                  * The spinlock stays locked until the list element is removed.
 542                  */
 543
 544                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 545                         msleep(msecs);
 546                 else
 547                         udelay(usecs);
 548
 549                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 550
 551                 if (p_cmd_elem->b_is_completed)
 552                         break;
 553
 554                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 555                 if (!rc)
 556                         break;
 557                 else if (rc != -EAGAIN)
 558                         goto err;
 559
 560                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 561         } while (++cnt < max_retries);
 562
 563         if (cnt >= max_retries) {
 564                 DP_NOTICE(p_hwfn,
 565                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 566                           p_mb_params->cmd, p_mb_params->param);
 567                 qed_mcp_print_cpu_info(p_hwfn, p_ptt);
 568
 569                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 570                 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 571                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 572
 573                 if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK))
 574                         qed_mcp_cmd_set_blocking(p_hwfn, true);
 575
 576                 return -EAGAIN;
 577         }
 578
 579         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 580         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 581
 582         DP_VERBOSE(p_hwfn,
 583                    QED_MSG_SP,
 584                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 585                    p_mb_params->mcp_resp,
 586                    p_mb_params->mcp_param,
 587                    (cnt * usecs) / 1000, (cnt * usecs) % 1000);
 588
 589         /* Clear the sequence number from the MFW response */
 590         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 591
 592         return 0;
 593
 594 err:
 595         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 596         return rc;
 597 }
 598
 599 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 600                                  struct qed_ptt *p_ptt,
 601                                  struct qed_mcp_mb_params *p_mb_params)
 602 {
 603         size_t union_data_size = sizeof(union drv_union_data);
 604         u32 max_retries = QED_DRV_MB_MAX_RETRIES;
 605         u32 usecs = QED_MCP_RESP_ITER_US;
 606
 607         /* MCP not initialized */
 608         if (!qed_mcp_is_init(p_hwfn)) {
 609                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 610                 return -EBUSY;
 611         }
 612
 613         if (p_hwfn->mcp_info->b_block_cmd) {
 614                 DP_NOTICE(p_hwfn,
 615                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 616                           p_mb_params->cmd, p_mb_params->param);
 617                 return -EBUSY;
 618         }
 619
 620         if (p_mb_params->data_src_size > union_data_size ||
 621             p_mb_params->data_dst_size > union_data_size) {
 622                 DP_ERR(p_hwfn,
 623                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 624                        p_mb_params->data_src_size,
 625                        p_mb_params->data_dst_size, union_data_size);
 626                 return -EINVAL;
 627         }
 628
 629         if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) {
 630                 max_retries = DIV_ROUND_UP(max_retries, 1000);
 631                 usecs *= 1000;
 632         }
 633
 634         return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 635                                       usecs);
 636 }
 637
 638 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 639                 struct qed_ptt *p_ptt,
 640                 u32 cmd,
 641                 u32 param,
 642                 u32 *o_mcp_resp,
 643                 u32 *o_mcp_param)
 644 {
 645         struct qed_mcp_mb_params mb_params;
 646         int rc;
 647
 648         memset(&mb_params, 0, sizeof(mb_params));
 649         mb_params.cmd = cmd;
 650         mb_params.param = param;
 651
 652         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 653         if (rc)
 654                 return rc;
 655
 656         *o_mcp_resp = mb_params.mcp_resp;
 657         *o_mcp_param = mb_params.mcp_param;
 658
 659         return 0;
 660 }
 661
 662 static int
 663 qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
 664                    struct qed_ptt *p_ptt,
 665                    u32 cmd,
 666                    u32 param,
 667                    u32 *o_mcp_resp,
 668                    u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
 669 {
 670         struct qed_mcp_mb_params mb_params;
 671         int rc;
 672
 673         memset(&mb_params, 0, sizeof(mb_params));
 674         mb_params.cmd = cmd;
 675         mb_params.param = param;
 676         mb_params.p_data_src = i_buf;
 677         mb_params.data_src_size = (u8)i_txn_size;
 678         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 679         if (rc)
 680                 return rc;
 681
 682         *o_mcp_resp = mb_params.mcp_resp;
 683         *o_mcp_param = mb_params.mcp_param;
 684
 685         /* nvm_info needs to be updated */
 686         p_hwfn->nvm_info.valid = false;
 687
 688         return 0;
 689 }
 690
 691 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 692                        struct qed_ptt *p_ptt,
 693                        u32 cmd,
 694                        u32 param,
 695                        u32 *o_mcp_resp,
 696                        u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
 697 {
 698         struct qed_mcp_mb_params mb_params;
 699         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 700         int rc;
 701
 702         memset(&mb_params, 0, sizeof(mb_params));
 703         mb_params.cmd = cmd;
 704         mb_params.param = param;
 705         mb_params.p_data_dst = raw_data;
 706
 707         /* Use the maximal value since the actual one is part of the response */
 708         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 709
 710         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 711         if (rc)
 712                 return rc;
 713
 714         *o_mcp_resp = mb_params.mcp_resp;
 715         *o_mcp_param = mb_params.mcp_param;
 716
 717         *o_txn_size = *o_mcp_param;
 718         memcpy(o_buf, raw_data, *o_txn_size);
 719
 720         return 0;
 721 }
 722
 723 static bool
 724 qed_mcp_can_force_load(u8 drv_role,
 725                        u8 exist_drv_role,
 726                        enum qed_override_force_load override_force_load)
 727 {
 728         bool can_force_load = false;
 729
 730         switch (override_force_load) {
 731         case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
 732                 can_force_load = true;
 733                 break;
 734         case QED_OVERRIDE_FORCE_LOAD_NEVER:
 735                 can_force_load = false;
 736                 break;
 737         default:
 738                 can_force_load = (drv_role == DRV_ROLE_OS &&
 739                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 740                                  (drv_role == DRV_ROLE_KDUMP &&
 741                                   exist_drv_role == DRV_ROLE_OS);
 742                 break;
 743         }
 744
 745         return can_force_load;
 746 }
 747
 748 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
 749                                    struct qed_ptt *p_ptt)
 750 {
 751         u32 resp = 0, param = 0;
 752         int rc;
 753
 754         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 755                          &resp, &param);
 756         if (rc)
 757                 DP_NOTICE(p_hwfn,
 758                           "Failed to send cancel load request, rc = %d\n", rc);
 759
 760         return rc;
 761 }
 762
 763 #define CONFIG_QEDE_BITMAP_IDX          BIT(0)
 764 #define CONFIG_QED_SRIOV_BITMAP_IDX     BIT(1)
 765 #define CONFIG_QEDR_BITMAP_IDX          BIT(2)
 766 #define CONFIG_QEDF_BITMAP_IDX          BIT(4)
 767 #define CONFIG_QEDI_BITMAP_IDX          BIT(5)
 768 #define CONFIG_QED_LL2_BITMAP_IDX       BIT(6)
 769
 770 static u32 qed_get_config_bitmap(void)
 771 {
 772         u32 config_bitmap = 0x0;
 773
 774         if (IS_ENABLED(CONFIG_QEDE))
 775                 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
 776
 777         if (IS_ENABLED(CONFIG_QED_SRIOV))
 778                 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
 779
 780         if (IS_ENABLED(CONFIG_QED_RDMA))
 781                 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
 782
 783         if (IS_ENABLED(CONFIG_QED_FCOE))
 784                 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
 785
 786         if (IS_ENABLED(CONFIG_QED_ISCSI))
 787                 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
 788
 789         if (IS_ENABLED(CONFIG_QED_LL2))
 790                 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
 791
 792         return config_bitmap;
 793 }
 794
 795 struct qed_load_req_in_params {
 796         u8 hsi_ver;
 797 #define QED_LOAD_REQ_HSI_VER_DEFAULT    0
 798 #define QED_LOAD_REQ_HSI_VER_1          1
 799         u32 drv_ver_0;
 800         u32 drv_ver_1;
 801         u32 fw_ver;
 802         u8 drv_role;
 803         u8 timeout_val;
 804         u8 force_cmd;
 805         bool avoid_eng_reset;
 806 };
 807
 808 struct qed_load_req_out_params {
 809         u32 load_code;
 810         u32 exist_drv_ver_0;
 811         u32 exist_drv_ver_1;
 812         u32 exist_fw_ver;
 813         u8 exist_drv_role;
 814         u8 mfw_hsi_ver;
 815         bool drv_exists;
 816 };
 817
 818 static int
 819 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 820                    struct qed_ptt *p_ptt,
 821                    struct qed_load_req_in_params *p_in_params,
 822                    struct qed_load_req_out_params *p_out_params)
 823 {
 824         struct qed_mcp_mb_params mb_params;
 825         struct load_req_stc load_req;
 826         struct load_rsp_stc load_rsp;
 827         u32 hsi_ver;
 828         int rc;
 829
 830         memset(&load_req, 0, sizeof(load_req));
 831         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 832         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 833         load_req.fw_ver = p_in_params->fw_ver;
 834         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 835         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 836                           p_in_params->timeout_val);
 837         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 838                           p_in_params->force_cmd);
 839         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 840                           p_in_params->avoid_eng_reset);
 841
 842         hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
 843                   DRV_ID_MCP_HSI_VER_CURRENT :
 844                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 845
 846         memset(&mb_params, 0, sizeof(mb_params));
 847         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 848         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
 849         mb_params.p_data_src = &load_req;
 850         mb_params.data_src_size = sizeof(load_req);
 851         mb_params.p_data_dst = &load_rsp;
 852         mb_params.data_dst_size = sizeof(load_rsp);
 853         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
 854
 855         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 856                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 857                    mb_params.param,
 858                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 859                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 860                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 861                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 862
 863         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
 864                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 865                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 866                            load_req.drv_ver_0,
 867                            load_req.drv_ver_1,
 868                            load_req.fw_ver,
 869                            load_req.misc0,
 870                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 871                            QED_MFW_GET_FIELD(load_req.misc0,
 872                                              LOAD_REQ_LOCK_TO),
 873                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 874                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 875         }
 876
 877         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 878         if (rc) {
 879                 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
 880                 return rc;
 881         }
 882
 883         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 884                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 885         p_out_params->load_code = mb_params.mcp_resp;
 886
 887         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 888             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 889                 DP_VERBOSE(p_hwfn,
 890                            QED_MSG_SP,
 891                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 892                            load_rsp.drv_ver_0,
 893                            load_rsp.drv_ver_1,
 894                            load_rsp.fw_ver,
 895                            load_rsp.misc0,
 896                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 897                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 898                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 899
 900                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 901                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 902                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 903                 p_out_params->exist_drv_role =
 904                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 905                 p_out_params->mfw_hsi_ver =
 906                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 907                 p_out_params->drv_exists =
 908                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 909                     LOAD_RSP_FLAGS0_DRV_EXISTS;
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
 916                                   enum qed_drv_role drv_role,
 917                                   u8 *p_mfw_drv_role)
 918 {
 919         switch (drv_role) {
 920         case QED_DRV_ROLE_OS:
 921                 *p_mfw_drv_role = DRV_ROLE_OS;
 922                 break;
 923         case QED_DRV_ROLE_KDUMP:
 924                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 925                 break;
 926         default:
 927                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 928                 return -EINVAL;
 929         }
 930
 931         return 0;
 932 }
 933
 934 enum qed_load_req_force {
 935         QED_LOAD_REQ_FORCE_NONE,
 936         QED_LOAD_REQ_FORCE_PF,
 937         QED_LOAD_REQ_FORCE_ALL,
 938 };
 939
 940 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
 941
 942                                   enum qed_load_req_force force_cmd,
 943                                   u8 *p_mfw_force_cmd)
 944 {
 945         switch (force_cmd) {
 946         case QED_LOAD_REQ_FORCE_NONE:
 947                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 948                 break;
 949         case QED_LOAD_REQ_FORCE_PF:
 950                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 951                 break;
 952         case QED_LOAD_REQ_FORCE_ALL:
 953                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 954                 break;
 955         }
 956 }
 957
 958 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 959                      struct qed_ptt *p_ptt,
 960                      struct qed_load_req_params *p_params)
 961 {
 962         struct qed_load_req_out_params out_params;
 963         struct qed_load_req_in_params in_params;
 964         u8 mfw_drv_role, mfw_force_cmd;
 965         int rc;
 966
 967         memset(&in_params, 0, sizeof(in_params));
 968         in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
 969         in_params.drv_ver_0 = QED_VERSION;
 970         in_params.drv_ver_1 = qed_get_config_bitmap();
 971         in_params.fw_ver = STORM_FW_VERSION;
 972         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 973         if (rc)
 974                 return rc;
 975
 976         in_params.drv_role = mfw_drv_role;
 977         in_params.timeout_val = p_params->timeout_val;
 978         qed_get_mfw_force_cmd(p_hwfn,
 979                               QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 980
 981         in_params.force_cmd = mfw_force_cmd;
 982         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 983
 984         memset(&out_params, 0, sizeof(out_params));
 985         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 986         if (rc)
 987                 return rc;
 988
 989         /* First handle cases where another load request should/might be sent:
 990          * - MFW expects the old interface [HSI version = 1]
 991          * - MFW responds that a force load request is required
 992          */
 993         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 994                 DP_INFO(p_hwfn,
 995                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
 996
 997                 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
 998                 memset(&out_params, 0, sizeof(out_params));
 999                 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
1000                 if (rc)
1001                         return rc;
1002         } else if (out_params.load_code ==
1003                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
1004                 if (qed_mcp_can_force_load(in_params.drv_role,
1005                                            out_params.exist_drv_role,
1006                                            p_params->override_force_load)) {
1007                         DP_INFO(p_hwfn,
1008                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
1009                                 in_params.drv_role, in_params.fw_ver,
1010                                 in_params.drv_ver_0, in_params.drv_ver_1,
1011                                 out_params.exist_drv_role,
1012                                 out_params.exist_fw_ver,
1013                                 out_params.exist_drv_ver_0,
1014                                 out_params.exist_drv_ver_1);
1015
1016                         qed_get_mfw_force_cmd(p_hwfn,
1017                                               QED_LOAD_REQ_FORCE_ALL,
1018                                               &mfw_force_cmd);
1019
1020                         in_params.force_cmd = mfw_force_cmd;
1021                         memset(&out_params, 0, sizeof(out_params));
1022                         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
1023                                                 &out_params);
1024                         if (rc)
1025                                 return rc;
1026                 } else {
1027                         DP_NOTICE(p_hwfn,
1028                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1029                                   in_params.drv_role, in_params.fw_ver,
1030                                   in_params.drv_ver_0, in_params.drv_ver_1,
1031                                   out_params.exist_drv_role,
1032                                   out_params.exist_fw_ver,
1033                                   out_params.exist_drv_ver_0,
1034                                   out_params.exist_drv_ver_1);
1035                         DP_NOTICE(p_hwfn,
1036                                   "Avoid sending a force load request to prevent disruption of active PFs\n");
1037
1038                         qed_mcp_cancel_load_req(p_hwfn, p_ptt);
1039                         return -EBUSY;
1040                 }
1041         }
1042
1043         /* Now handle the other types of responses.
1044          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1045          * expected here after the additional revised load requests were sent.
1046          */
1047         switch (out_params.load_code) {
1048         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1049         case FW_MSG_CODE_DRV_LOAD_PORT:
1050         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1051                 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
1052                     out_params.drv_exists) {
1053                         /* The role and fw/driver version match, but the PF is
1054                          * already loaded and has not been unloaded gracefully.
1055                          */
1056                         DP_NOTICE(p_hwfn,
1057                                   "PF is already loaded\n");
1058                         return -EINVAL;
1059                 }
1060                 break;
1061         default:
1062                 DP_NOTICE(p_hwfn,
1063                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1064                           out_params.load_code);
1065                 return -EBUSY;
1066         }
1067
1068         p_params->load_code = out_params.load_code;
1069
1070         return 0;
1071 }
1072
1073 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1074 {
1075         struct qed_mcp_mb_params mb_params;
1076         u32 wol_param;
1077
1078         switch (p_hwfn->cdev->wol_config) {
1079         case QED_OV_WOL_DISABLED:
1080                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
1081                 break;
1082         case QED_OV_WOL_ENABLED:
1083                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
1084                 break;
1085         default:
1086                 DP_NOTICE(p_hwfn,
1087                           "Unknown WoL configuration %02x\n",
1088                           p_hwfn->cdev->wol_config);
1089                 /* Fallthrough */
1090         case QED_OV_WOL_DEFAULT:
1091                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1092         }
1093
1094         memset(&mb_params, 0, sizeof(mb_params));
1095         mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ;
1096         mb_params.param = wol_param;
1097         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
1098
1099         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1100 }
1101
1102 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1103 {
1104         struct qed_mcp_mb_params mb_params;
1105         struct mcp_mac wol_mac;
1106
1107         memset(&mb_params, 0, sizeof(mb_params));
1108         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1109
1110         /* Set the primary MAC if WoL is enabled */
1111         if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
1112                 u8 *p_mac = p_hwfn->cdev->wol_mac;
1113
1114                 memset(&wol_mac, 0, sizeof(wol_mac));
1115                 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
1116                 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
1117                                     p_mac[4] << 8 | p_mac[5];
1118
1119                 DP_VERBOSE(p_hwfn,
1120                            (QED_MSG_SP | NETIF_MSG_IFDOWN),
1121                            "Setting WoL MAC: %pM --> [%08x,%08x]\n",
1122                            p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
1123
1124                 mb_params.p_data_src = &wol_mac;
1125                 mb_params.data_src_size = sizeof(wol_mac);
1126         }
1127
1128         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1129 }
1130
1131 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1132                                   struct qed_ptt *p_ptt)
1133 {
1134         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1135                                         PUBLIC_PATH);
1136         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1137         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1138                                      QED_PATH_ID(p_hwfn));
1139         u32 disabled_vfs[VF_MAX_STATIC / 32];
1140         int i;
1141
1142         DP_VERBOSE(p_hwfn,
1143                    QED_MSG_SP,
1144                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1145                    mfw_path_offsize, path_addr);
1146
1147         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1148                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1149                                          path_addr +
1150                                          offsetof(struct public_path,
1151                                                   mcp_vf_disabled) +
1152                                          sizeof(u32) * i);
1153                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1154                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1155                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1156         }
1157
1158         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1159                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1160 }
1161
1162 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1163                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1164 {
1165         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1166                                         PUBLIC_FUNC);
1167         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1168         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1169                                      MCP_PF_ID(p_hwfn));
1170         struct qed_mcp_mb_params mb_params;
1171         int rc;
1172         int i;
1173
1174         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1175                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1176                            "Acking VFs [%08x,...,%08x] - %08x\n",
1177                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1178
1179         memset(&mb_params, 0, sizeof(mb_params));
1180         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1181         mb_params.p_data_src = vfs_to_ack;
1182         mb_params.data_src_size = VF_MAX_STATIC / 8;
1183         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1184         if (rc) {
1185                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1186                 return -EBUSY;
1187         }
1188
1189         /* Clear the ACK bits */
1190         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1191                 qed_wr(p_hwfn, p_ptt,
1192                        func_addr +
1193                        offsetof(struct public_func, drv_ack_vf_disabled) +
1194                        i * sizeof(u32), 0);
1195
1196         return rc;
1197 }
1198
1199 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1200                                               struct qed_ptt *p_ptt)
1201 {
1202         u32 transceiver_state;
1203
1204         transceiver_state = qed_rd(p_hwfn, p_ptt,
1205                                    p_hwfn->mcp_info->port_addr +
1206                                    offsetof(struct public_port,
1207                                             transceiver_data));
1208
1209         DP_VERBOSE(p_hwfn,
1210                    (NETIF_MSG_HW | QED_MSG_SP),
1211                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1212                    transceiver_state,
1213                    (u32)(p_hwfn->mcp_info->port_addr +
1214                           offsetof(struct public_port, transceiver_data)));
1215
1216         transceiver_state = GET_FIELD(transceiver_state,
1217                                       ETH_TRANSCEIVER_STATE);
1218
1219         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1220                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1221         else
1222                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1223 }
1224
1225 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1226                                     struct qed_ptt *p_ptt,
1227                                     struct qed_mcp_link_state *p_link)
1228 {
1229         u32 eee_status, val;
1230
1231         p_link->eee_adv_caps = 0;
1232         p_link->eee_lp_adv_caps = 0;
1233         eee_status = qed_rd(p_hwfn,
1234                             p_ptt,
1235                             p_hwfn->mcp_info->port_addr +
1236                             offsetof(struct public_port, eee_status));
1237         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1238         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1239         if (val & EEE_1G_ADV)
1240                 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1241         if (val & EEE_10G_ADV)
1242                 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1243         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1244         if (val & EEE_1G_ADV)
1245                 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1246         if (val & EEE_10G_ADV)
1247                 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1248 }
1249
1250 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1251                                        struct qed_ptt *p_ptt, bool b_reset)
1252 {
1253         struct qed_mcp_link_state *p_link;
1254         u8 max_bw, min_bw;
1255         u32 status = 0;
1256
1257         /* Prevent SW/attentions from doing this at the same time */
1258         spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1259
1260         p_link = &p_hwfn->mcp_info->link_output;
1261         memset(p_link, 0, sizeof(*p_link));
1262         if (!b_reset) {
1263                 status = qed_rd(p_hwfn, p_ptt,
1264                                 p_hwfn->mcp_info->port_addr +
1265                                 offsetof(struct public_port, link_status));
1266                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1267                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1268                            status,
1269                            (u32)(p_hwfn->mcp_info->port_addr +
1270                                  offsetof(struct public_port, link_status)));
1271         } else {
1272                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1273                            "Resetting link indications\n");
1274                 goto out;
1275         }
1276
1277         if (p_hwfn->b_drv_link_init)
1278                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1279         else
1280                 p_link->link_up = false;
1281
1282         p_link->full_duplex = true;
1283         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1284         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1285                 p_link->speed = 100000;
1286                 break;
1287         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1288                 p_link->speed = 50000;
1289                 break;
1290         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1291                 p_link->speed = 40000;
1292                 break;
1293         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1294                 p_link->speed = 25000;
1295                 break;
1296         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1297                 p_link->speed = 20000;
1298                 break;
1299         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1300                 p_link->speed = 10000;
1301                 break;
1302         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1303                 p_link->full_duplex = false;
1304         /* Fall-through */
1305         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1306                 p_link->speed = 1000;
1307                 break;
1308         default:
1309                 p_link->speed = 0;
1310                 p_link->link_up = 0;
1311         }
1312
1313         if (p_link->link_up && p_link->speed)
1314                 p_link->line_speed = p_link->speed;
1315         else
1316                 p_link->line_speed = 0;
1317
1318         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1319         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1320
1321         /* Max bandwidth configuration */
1322         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1323
1324         /* Min bandwidth configuration */
1325         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1326         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1327                                             p_link->min_pf_rate);
1328
1329         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1330         p_link->an_complete = !!(status &
1331                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1332         p_link->parallel_detection = !!(status &
1333                                         LINK_STATUS_PARALLEL_DETECTION_USED);
1334         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1335
1336         p_link->partner_adv_speed |=
1337                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1338                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1339         p_link->partner_adv_speed |=
1340                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1341                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1342         p_link->partner_adv_speed |=
1343                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1344                 QED_LINK_PARTNER_SPEED_10G : 0;
1345         p_link->partner_adv_speed |=
1346                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1347                 QED_LINK_PARTNER_SPEED_20G : 0;
1348         p_link->partner_adv_speed |=
1349                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1350                 QED_LINK_PARTNER_SPEED_25G : 0;
1351         p_link->partner_adv_speed |=
1352                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1353                 QED_LINK_PARTNER_SPEED_40G : 0;
1354         p_link->partner_adv_speed |=
1355                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1356                 QED_LINK_PARTNER_SPEED_50G : 0;
1357         p_link->partner_adv_speed |=
1358                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1359                 QED_LINK_PARTNER_SPEED_100G : 0;
1360
1361         p_link->partner_tx_flow_ctrl_en =
1362                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1363         p_link->partner_rx_flow_ctrl_en =
1364                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1365
1366         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1367         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1368                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1369                 break;
1370         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1371                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1372                 break;
1373         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1374                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1375                 break;
1376         default:
1377                 p_link->partner_adv_pause = 0;
1378         }
1379
1380         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1381
1382         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1383                 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1384
1385         qed_link_update(p_hwfn);
1386 out:
1387         spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1388 }
1389
1390 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1391 {
1392         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1393         struct qed_mcp_mb_params mb_params;
1394         struct eth_phy_cfg phy_cfg;
1395         int rc = 0;
1396         u32 cmd;
1397
1398         /* Set the shmem configuration according to params */
1399         memset(&phy_cfg, 0, sizeof(phy_cfg));
1400         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1401         if (!params->speed.autoneg)
1402                 phy_cfg.speed = params->speed.forced_speed;
1403         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1404         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1405         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1406         phy_cfg.adv_speed = params->speed.advertised_speeds;
1407         phy_cfg.loopback_mode = params->loopback_mode;
1408
1409         /* There are MFWs that share this capability regardless of whether
1410          * this is feasible or not. And given that at the very least adv_caps
1411          * would be set internally by qed, we want to make sure LFA would
1412          * still work.
1413          */
1414         if ((p_hwfn->mcp_info->capabilities &
1415              FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) {
1416                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1417                 if (params->eee.tx_lpi_enable)
1418                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1419                 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1420                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1421                 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1422                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1423                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1424                                     EEE_TX_TIMER_USEC_OFFSET) &
1425                                    EEE_TX_TIMER_USEC_MASK;
1426         }
1427
1428         p_hwfn->b_drv_link_init = b_up;
1429
1430         if (b_up) {
1431                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1432                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1433                            phy_cfg.speed,
1434                            phy_cfg.pause,
1435                            phy_cfg.adv_speed,
1436                            phy_cfg.loopback_mode,
1437                            phy_cfg.feature_config_flags);
1438         } else {
1439                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1440                            "Resetting link\n");
1441         }
1442
1443         memset(&mb_params, 0, sizeof(mb_params));
1444         mb_params.cmd = cmd;
1445         mb_params.p_data_src = &phy_cfg;
1446         mb_params.data_src_size = sizeof(phy_cfg);
1447         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1448
1449         /* if mcp fails to respond we must abort */
1450         if (rc) {
1451                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1452                 return rc;
1453         }
1454
1455         /* Mimic link-change attention, done for several reasons:
1456          *  - On reset, there's no guarantee MFW would trigger
1457          *    an attention.
1458          *  - On initialization, older MFWs might not indicate link change
1459          *    during LFA, so we'll never get an UP indication.
1460          */
1461         qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1462
1463         return 0;
1464 }
1465
1466 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1467                                         struct qed_ptt *p_ptt,
1468                                         enum MFW_DRV_MSG_TYPE type)
1469 {
1470         enum qed_mcp_protocol_type stats_type;
1471         union qed_mcp_protocol_stats stats;
1472         struct qed_mcp_mb_params mb_params;
1473         u32 hsi_param;
1474
1475         switch (type) {
1476         case MFW_DRV_MSG_GET_LAN_STATS:
1477                 stats_type = QED_MCP_LAN_STATS;
1478                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1479                 break;
1480         case MFW_DRV_MSG_GET_FCOE_STATS:
1481                 stats_type = QED_MCP_FCOE_STATS;
1482                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1483                 break;
1484         case MFW_DRV_MSG_GET_ISCSI_STATS:
1485                 stats_type = QED_MCP_ISCSI_STATS;
1486                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1487                 break;
1488         case MFW_DRV_MSG_GET_RDMA_STATS:
1489                 stats_type = QED_MCP_RDMA_STATS;
1490                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1491                 break;
1492         default:
1493                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1494                 return;
1495         }
1496
1497         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1498
1499         memset(&mb_params, 0, sizeof(mb_params));
1500         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1501         mb_params.param = hsi_param;
1502         mb_params.p_data_src = &stats;
1503         mb_params.data_src_size = sizeof(stats);
1504         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1505 }
1506
1507 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1508                                   struct public_func *p_shmem_info)
1509 {
1510         struct qed_mcp_function_info *p_info;
1511
1512         p_info = &p_hwfn->mcp_info->func_info;
1513
1514         p_info->bandwidth_min = (p_shmem_info->config &
1515                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1516                                         FUNC_MF_CFG_MIN_BW_SHIFT;
1517         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1518                 DP_INFO(p_hwfn,
1519                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1520                         p_info->bandwidth_min);
1521                 p_info->bandwidth_min = 1;
1522         }
1523
1524         p_info->bandwidth_max = (p_shmem_info->config &
1525                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1526                                         FUNC_MF_CFG_MAX_BW_SHIFT;
1527         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1528                 DP_INFO(p_hwfn,
1529                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1530                         p_info->bandwidth_max);
1531                 p_info->bandwidth_max = 100;
1532         }
1533 }
1534
1535 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1536                                   struct qed_ptt *p_ptt,
1537                                   struct public_func *p_data, int pfid)
1538 {
1539         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1540                                         PUBLIC_FUNC);
1541         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1542         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1543         u32 i, size;
1544
1545         memset(p_data, 0, sizeof(*p_data));
1546
1547         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1548         for (i = 0; i < size / sizeof(u32); i++)
1549                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1550                                             func_addr + (i << 2));
1551         return size;
1552 }
1553
1554 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1555 {
1556         struct qed_mcp_function_info *p_info;
1557         struct public_func shmem_info;
1558         u32 resp = 0, param = 0;
1559
1560         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1561
1562         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1563
1564         p_info = &p_hwfn->mcp_info->func_info;
1565
1566         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1567         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1568
1569         /* Acknowledge the MFW */
1570         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1571                     &param);
1572 }
1573
1574 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1575 {
1576         struct public_func shmem_info;
1577         u32 resp = 0, param = 0;
1578
1579         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1580
1581         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1582                                                  FUNC_MF_CFG_OV_STAG_MASK;
1583         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1584         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) {
1585                 if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) {
1586                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
1587                                p_hwfn->hw_info.ovlan);
1588                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1);
1589
1590                         /* Configure DB to add external vlan to EDPM packets */
1591                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
1592                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,
1593                                p_hwfn->hw_info.ovlan);
1594                 } else {
1595                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);
1596                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0);
1597                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);
1598                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);
1599                 }
1600
1601                 qed_sp_pf_update_stag(p_hwfn);
1602         }
1603
1604         DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan  = %d hw_mode = 0x%x\n",
1605                    p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode);
1606
1607         /* Acknowledge the MFW */
1608         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1609                     &resp, &param);
1610 }
1611
1612 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1613 {
1614         struct public_func shmem_info;
1615         u32 port_cfg, val;
1616
1617         if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
1618                 return;
1619
1620         memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1621         port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1622                           offsetof(struct public_port, oem_cfg_port));
1623         val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >>
1624                 OEM_CFG_CHANNEL_TYPE_OFFSET;
1625         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1626                 DP_NOTICE(p_hwfn, "Incorrect UFP Channel type  %d\n", val);
1627
1628         val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET;
1629         if (val == OEM_CFG_SCHED_TYPE_ETS) {
1630                 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS;
1631         } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) {
1632                 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW;
1633         } else {
1634                 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN;
1635                 DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val);
1636         }
1637
1638         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1639         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >>
1640                 OEM_CFG_FUNC_TC_OFFSET;
1641         p_hwfn->ufp_info.tc = (u8)val;
1642         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >>
1643                 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET;
1644         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) {
1645                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC;
1646         } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) {
1647                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS;
1648         } else {
1649                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN;
1650                 DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val);
1651         }
1652
1653         DP_NOTICE(p_hwfn,
1654                   "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1655                   p_hwfn->ufp_info.mode,
1656                   p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type);
1657 }
1658
1659 static int
1660 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1661 {
1662         qed_mcp_read_ufp_config(p_hwfn, p_ptt);
1663
1664         if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) {
1665                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1666                 qed_hw_info_set_offload_tc(&p_hwfn->hw_info,
1667                                            p_hwfn->ufp_info.tc);
1668
1669                 qed_qm_reconf(p_hwfn, p_ptt);
1670         } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) {
1671                 /* Merge UFP TC with the dcbx TC data */
1672                 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1673                                           QED_DCBX_OPERATIONAL_MIB);
1674         } else {
1675                 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n");
1676                 return -EINVAL;
1677         }
1678
1679         /* update storm FW with negotiation results */
1680         qed_sp_pf_update_ufp(p_hwfn);
1681
1682         /* update stag pcp value */
1683         qed_sp_pf_update_stag(p_hwfn);
1684
1685         return 0;
1686 }
1687
1688 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1689                           struct qed_ptt *p_ptt)
1690 {
1691         struct qed_mcp_info *info = p_hwfn->mcp_info;
1692         int rc = 0;
1693         bool found = false;
1694         u16 i;
1695
1696         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1697
1698         /* Read Messages from MFW */
1699         qed_mcp_read_mb(p_hwfn, p_ptt);
1700
1701         /* Compare current messages to old ones */
1702         for (i = 0; i < info->mfw_mb_length; i++) {
1703                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1704                         continue;
1705
1706                 found = true;
1707
1708                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1709                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1710                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1711
1712                 switch (i) {
1713                 case MFW_DRV_MSG_LINK_CHANGE:
1714                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1715                         break;
1716                 case MFW_DRV_MSG_VF_DISABLED:
1717                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1718                         break;
1719                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1720                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1721                                                   QED_DCBX_REMOTE_LLDP_MIB);
1722                         break;
1723                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1724                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1725                                                   QED_DCBX_REMOTE_MIB);
1726                         break;
1727                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1728                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1729                                                   QED_DCBX_OPERATIONAL_MIB);
1730                         break;
1731                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1732                         qed_mcp_handle_ufp_event(p_hwfn, p_ptt);
1733                         break;
1734                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1735                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1736                         break;
1737                 case MFW_DRV_MSG_GET_LAN_STATS:
1738                 case MFW_DRV_MSG_GET_FCOE_STATS:
1739                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1740                 case MFW_DRV_MSG_GET_RDMA_STATS:
1741                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1742                         break;
1743                 case MFW_DRV_MSG_BW_UPDATE:
1744                         qed_mcp_update_bw(p_hwfn, p_ptt);
1745                         break;
1746                 case MFW_DRV_MSG_S_TAG_UPDATE:
1747                         qed_mcp_update_stag(p_hwfn, p_ptt);
1748                         break;
1749                 case MFW_DRV_MSG_GET_TLV_REQ:
1750                         qed_mfw_tlv_req(p_hwfn);
1751                         break;
1752                 default:
1753                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1754                         rc = -EINVAL;
1755                 }
1756         }
1757
1758         /* ACK everything */
1759         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1760                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1761
1762                 /* MFW expect answer in BE, so we force write in that format */
1763                 qed_wr(p_hwfn, p_ptt,
1764                        info->mfw_mb_addr + sizeof(u32) +
1765                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1766                        sizeof(u32) + i * sizeof(u32),
1767                        (__force u32)val);
1768         }
1769
1770         if (!found) {
1771                 DP_NOTICE(p_hwfn,
1772                           "Received an MFW message indication but no new message!\n");
1773                 rc = -EINVAL;
1774         }
1775
1776         /* Copy the new mfw messages into the shadow */
1777         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1778
1779         return rc;
1780 }
1781
1782 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
1783                         struct qed_ptt *p_ptt,
1784                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
1785 {
1786         u32 global_offsize;
1787
1788         if (IS_VF(p_hwfn->cdev)) {
1789                 if (p_hwfn->vf_iov_info) {
1790                         struct pfvf_acquire_resp_tlv *p_resp;
1791
1792                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1793                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1794                         return 0;
1795                 } else {
1796                         DP_VERBOSE(p_hwfn,
1797                                    QED_MSG_IOV,
1798                                    "VF requested MFW version prior to ACQUIRE\n");
1799                         return -EINVAL;
1800                 }
1801         }
1802
1803         global_offsize = qed_rd(p_hwfn, p_ptt,
1804                                 SECTION_OFFSIZE_ADDR(p_hwfn->
1805                                                      mcp_info->public_base,
1806                                                      PUBLIC_GLOBAL));
1807         *p_mfw_ver =
1808             qed_rd(p_hwfn, p_ptt,
1809                    SECTION_ADDR(global_offsize,
1810                                 0) + offsetof(struct public_global, mfw_ver));
1811
1812         if (p_running_bundle_id != NULL) {
1813                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1814                                               SECTION_ADDR(global_offsize, 0) +
1815                                               offsetof(struct public_global,
1816                                                        running_bundle_id));
1817         }
1818
1819         return 0;
1820 }
1821
1822 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
1823                         struct qed_ptt *p_ptt, u32 *p_mbi_ver)
1824 {
1825         u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
1826
1827         if (IS_VF(p_hwfn->cdev))
1828                 return -EINVAL;
1829
1830         /* Read the address of the nvm_cfg */
1831         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1832         if (!nvm_cfg_addr) {
1833                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1834                 return -EINVAL;
1835         }
1836
1837         /* Read the offset of nvm_cfg1 */
1838         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1839
1840         mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1841                        offsetof(struct nvm_cfg1, glob) +
1842                        offsetof(struct nvm_cfg1_glob, mbi_version);
1843         *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
1844                             mbi_ver_addr) &
1845                      (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
1846                       NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
1847                       NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
1848
1849         return 0;
1850 }
1851
1852 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
1853 {
1854         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1855         struct qed_ptt  *p_ptt;
1856
1857         if (IS_VF(cdev))
1858                 return -EINVAL;
1859
1860         if (!qed_mcp_is_init(p_hwfn)) {
1861                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1862                 return -EBUSY;
1863         }
1864
1865         *p_media_type = MEDIA_UNSPECIFIED;
1866
1867         p_ptt = qed_ptt_acquire(p_hwfn);
1868         if (!p_ptt)
1869                 return -EBUSY;
1870
1871         *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1872                                offsetof(struct public_port, media_type));
1873
1874         qed_ptt_release(p_hwfn, p_ptt);
1875
1876         return 0;
1877 }
1878
1879 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1880 static void
1881 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1882                                enum qed_pci_personality *p_proto)
1883 {
1884         /* There wasn't ever a legacy MFW that published iwarp.
1885          * So at this point, this is either plain l2 or RoCE.
1886          */
1887         if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1888                 *p_proto = QED_PCI_ETH_ROCE;
1889         else
1890                 *p_proto = QED_PCI_ETH;
1891
1892         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1893                    "According to Legacy capabilities, L2 personality is %08x\n",
1894                    (u32) *p_proto);
1895 }
1896
1897 static int
1898 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1899                             struct qed_ptt *p_ptt,
1900                             enum qed_pci_personality *p_proto)
1901 {
1902         u32 resp = 0, param = 0;
1903         int rc;
1904
1905         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1906                          DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
1907         if (rc)
1908                 return rc;
1909         if (resp != FW_MSG_CODE_OK) {
1910                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1911                            "MFW lacks support for command; Returns %08x\n",
1912                            resp);
1913                 return -EINVAL;
1914         }
1915
1916         switch (param) {
1917         case FW_MB_PARAM_GET_PF_RDMA_NONE:
1918                 *p_proto = QED_PCI_ETH;
1919                 break;
1920         case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1921                 *p_proto = QED_PCI_ETH_ROCE;
1922                 break;
1923         case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1924                 *p_proto = QED_PCI_ETH_IWARP;
1925                 break;
1926         case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1927                 *p_proto = QED_PCI_ETH_RDMA;
1928                 break;
1929         default:
1930                 DP_NOTICE(p_hwfn,
1931                           "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1932                           param);
1933                 return -EINVAL;
1934         }
1935
1936         DP_VERBOSE(p_hwfn,
1937                    NETIF_MSG_IFUP,
1938                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1939                    (u32) *p_proto, resp, param);
1940         return 0;
1941 }
1942
1943 static int
1944 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1945                         struct public_func *p_info,
1946                         struct qed_ptt *p_ptt,
1947                         enum qed_pci_personality *p_proto)
1948 {
1949         int rc = 0;
1950
1951         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1952         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1953                 if (!IS_ENABLED(CONFIG_QED_RDMA))
1954                         *p_proto = QED_PCI_ETH;
1955                 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1956                         qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1957                 break;
1958         case FUNC_MF_CFG_PROTOCOL_ISCSI:
1959                 *p_proto = QED_PCI_ISCSI;
1960                 break;
1961         case FUNC_MF_CFG_PROTOCOL_FCOE:
1962                 *p_proto = QED_PCI_FCOE;
1963                 break;
1964         case FUNC_MF_CFG_PROTOCOL_ROCE:
1965                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1966         /* Fallthrough */
1967         default:
1968                 rc = -EINVAL;
1969         }
1970
1971         return rc;
1972 }
1973
1974 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1975                                  struct qed_ptt *p_ptt)
1976 {
1977         struct qed_mcp_function_info *info;
1978         struct public_func shmem_info;
1979
1980         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1981         info = &p_hwfn->mcp_info->func_info;
1982
1983         info->pause_on_host = (shmem_info.config &
1984                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1985
1986         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1987                                     &info->protocol)) {
1988                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1989                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1990                 return -EINVAL;
1991         }
1992
1993         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1994
1995         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1996                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1997                 info->mac[1] = (u8)(shmem_info.mac_upper);
1998                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1999                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2000                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2001                 info->mac[5] = (u8)(shmem_info.mac_lower);
2002
2003                 /* Store primary MAC for later possible WoL */
2004                 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
2005         } else {
2006                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
2007         }
2008
2009         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
2010                          (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
2011         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
2012                          (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
2013
2014         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2015
2016         info->mtu = (u16)shmem_info.mtu_size;
2017
2018         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
2019         p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
2020         if (qed_mcp_is_init(p_hwfn)) {
2021                 u32 resp = 0, param = 0;
2022                 int rc;
2023
2024                 rc = qed_mcp_cmd(p_hwfn, p_ptt,
2025                                  DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
2026                 if (rc)
2027                         return rc;
2028                 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
2029                         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
2030         }
2031
2032         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
2033                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
2034                 info->pause_on_host, info->protocol,
2035                 info->bandwidth_min, info->bandwidth_max,
2036                 info->mac[0], info->mac[1], info->mac[2],
2037                 info->mac[3], info->mac[4], info->mac[5],
2038                 info->wwn_port, info->wwn_node,
2039                 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
2040
2041         return 0;
2042 }
2043
2044 struct qed_mcp_link_params
2045 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
2046 {
2047         if (!p_hwfn || !p_hwfn->mcp_info)
2048                 return NULL;
2049         return &p_hwfn->mcp_info->link_input;
2050 }
2051
2052 struct qed_mcp_link_state
2053 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
2054 {
2055         if (!p_hwfn || !p_hwfn->mcp_info)
2056                 return NULL;
2057         return &p_hwfn->mcp_info->link_output;
2058 }
2059
2060 struct qed_mcp_link_capabilities
2061 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
2062 {
2063         if (!p_hwfn || !p_hwfn->mcp_info)
2064                 return NULL;
2065         return &p_hwfn->mcp_info->link_capabilities;
2066 }
2067
2068 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2069 {
2070         u32 resp = 0, param = 0;
2071         int rc;
2072
2073         rc = qed_mcp_cmd(p_hwfn, p_ptt,
2074                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2075
2076         /* Wait for the drain to complete before returning */
2077         msleep(1020);
2078
2079         return rc;
2080 }
2081
2082 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
2083                            struct qed_ptt *p_ptt, u32 *p_flash_size)
2084 {
2085         u32 flash_size;
2086
2087         if (IS_VF(p_hwfn->cdev))
2088                 return -EINVAL;
2089
2090         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2091         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2092                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2093         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2094
2095         *p_flash_size = flash_size;
2096
2097         return 0;
2098 }
2099
2100 static int
2101 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
2102                           struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2103 {
2104         u32 resp = 0, param = 0, rc_param = 0;
2105         int rc;
2106
2107         /* Only Leader can configure MSIX, and need to take CMT into account */
2108         if (!IS_LEAD_HWFN(p_hwfn))
2109                 return 0;
2110         num *= p_hwfn->cdev->num_hwfns;
2111
2112         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2113                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2114         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2115                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2116
2117         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2118                          &resp, &rc_param);
2119
2120         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2121                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
2122                 rc = -EINVAL;
2123         } else {
2124                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2125                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2126                            num, vf_id);
2127         }
2128
2129         return rc;
2130 }
2131
2132 static int
2133 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
2134                           struct qed_ptt *p_ptt, u8 num)
2135 {
2136         u32 resp = 0, param = num, rc_param = 0;
2137         int rc;
2138
2139         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2140                          param, &resp, &rc_param);
2141
2142         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2143                 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
2144                 rc = -EINVAL;
2145         } else {
2146                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2147                            "Requested 0x%02x MSI-x interrupts for VFs\n", num);
2148         }
2149
2150         return rc;
2151 }
2152
2153 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
2154                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2155 {
2156         if (QED_IS_BB(p_hwfn->cdev))
2157                 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2158         else
2159                 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2160 }
2161
2162 int
2163 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
2164                          struct qed_ptt *p_ptt,
2165                          struct qed_mcp_drv_version *p_ver)
2166 {
2167         struct qed_mcp_mb_params mb_params;
2168         struct drv_version_stc drv_version;
2169         __be32 val;
2170         u32 i;
2171         int rc;
2172
2173         memset(&drv_version, 0, sizeof(drv_version));
2174         drv_version.version = p_ver->version;
2175         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
2176                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
2177                 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
2178         }
2179
2180         memset(&mb_params, 0, sizeof(mb_params));
2181         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2182         mb_params.p_data_src = &drv_version;
2183         mb_params.data_src_size = sizeof(drv_version);
2184         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2185         if (rc)
2186                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2187
2188         return rc;
2189 }
2190
2191 /* A maximal 100 msec waiting time for the MCP to halt */
2192 #define QED_MCP_HALT_SLEEP_MS           10
2193 #define QED_MCP_HALT_MAX_RETRIES        10
2194
2195 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2196 {
2197         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2198         int rc;
2199
2200         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2201                          &param);
2202         if (rc) {
2203                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2204                 return rc;
2205         }
2206
2207         do {
2208                 msleep(QED_MCP_HALT_SLEEP_MS);
2209                 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2210                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2211                         break;
2212         } while (++cnt < QED_MCP_HALT_MAX_RETRIES);
2213
2214         if (cnt == QED_MCP_HALT_MAX_RETRIES) {
2215                 DP_NOTICE(p_hwfn,
2216                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2217                           qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2218                 return -EBUSY;
2219         }
2220
2221         qed_mcp_cmd_set_blocking(p_hwfn, true);
2222
2223         return 0;
2224 }
2225
2226 #define QED_MCP_RESUME_SLEEP_MS 10
2227
2228 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2229 {
2230         u32 cpu_mode, cpu_state;
2231
2232         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2233
2234         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2235         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2236         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2237         msleep(QED_MCP_RESUME_SLEEP_MS);
2238         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2239
2240         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2241                 DP_NOTICE(p_hwfn,
2242                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2243                           cpu_mode, cpu_state);
2244                 return -EBUSY;
2245         }
2246
2247         qed_mcp_cmd_set_blocking(p_hwfn, false);
2248
2249         return 0;
2250 }
2251
2252 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
2253                                      struct qed_ptt *p_ptt,
2254                                      enum qed_ov_client client)
2255 {
2256         u32 resp = 0, param = 0;
2257         u32 drv_mb_param;
2258         int rc;
2259
2260         switch (client) {
2261         case QED_OV_CLIENT_DRV:
2262                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2263                 break;
2264         case QED_OV_CLIENT_USER:
2265                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2266                 break;
2267         case QED_OV_CLIENT_VENDOR_SPEC:
2268                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2269                 break;
2270         default:
2271                 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2272                 return -EINVAL;
2273         }
2274
2275         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2276                          drv_mb_param, &resp, &param);
2277         if (rc)
2278                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2279
2280         return rc;
2281 }
2282
2283 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2284                                    struct qed_ptt *p_ptt,
2285                                    enum qed_ov_driver_state drv_state)
2286 {
2287         u32 resp = 0, param = 0;
2288         u32 drv_mb_param;
2289         int rc;
2290
2291         switch (drv_state) {
2292         case QED_OV_DRIVER_STATE_NOT_LOADED:
2293                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2294                 break;
2295         case QED_OV_DRIVER_STATE_DISABLED:
2296                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2297                 break;
2298         case QED_OV_DRIVER_STATE_ACTIVE:
2299                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2300                 break;
2301         default:
2302                 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2303                 return -EINVAL;
2304         }
2305
2306         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2307                          drv_mb_param, &resp, &param);
2308         if (rc)
2309                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2310
2311         return rc;
2312 }
2313
2314 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2315                           struct qed_ptt *p_ptt, u16 mtu)
2316 {
2317         u32 resp = 0, param = 0;
2318         u32 drv_mb_param;
2319         int rc;
2320
2321         drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2322         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2323                          drv_mb_param, &resp, &param);
2324         if (rc)
2325                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2326
2327         return rc;
2328 }
2329
2330 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2331                           struct qed_ptt *p_ptt, u8 *mac)
2332 {
2333         struct qed_mcp_mb_params mb_params;
2334         u32 mfw_mac[2];
2335         int rc;
2336
2337         memset(&mb_params, 0, sizeof(mb_params));
2338         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2339         mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2340                           DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2341         mb_params.param |= MCP_PF_ID(p_hwfn);
2342
2343         /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
2344          * in 32-bit granularity.
2345          * So the MAC has to be set in native order [and not byte order],
2346          * otherwise it would be read incorrectly by MFW after swap.
2347          */
2348         mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2349         mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2350
2351         mb_params.p_data_src = (u8 *)mfw_mac;
2352         mb_params.data_src_size = 8;
2353         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2354         if (rc)
2355                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2356
2357         /* Store primary MAC for later possible WoL */
2358         memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2359
2360         return rc;
2361 }
2362
2363 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2364                           struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2365 {
2366         u32 resp = 0, param = 0;
2367         u32 drv_mb_param;
2368         int rc;
2369
2370         if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2371                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2372                            "Can't change WoL configuration when WoL isn't supported\n");
2373                 return -EINVAL;
2374         }
2375
2376         switch (wol) {
2377         case QED_OV_WOL_DEFAULT:
2378                 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2379                 break;
2380         case QED_OV_WOL_DISABLED:
2381                 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2382                 break;
2383         case QED_OV_WOL_ENABLED:
2384                 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2385                 break;
2386         default:
2387                 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2388                 return -EINVAL;
2389         }
2390
2391         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2392                          drv_mb_param, &resp, &param);
2393         if (rc)
2394                 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2395
2396         /* Store the WoL update for a future unload */
2397         p_hwfn->cdev->wol_config = (u8)wol;
2398
2399         return rc;
2400 }
2401
2402 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2403                               struct qed_ptt *p_ptt,
2404                               enum qed_ov_eswitch eswitch)
2405 {
2406         u32 resp = 0, param = 0;
2407         u32 drv_mb_param;
2408         int rc;
2409
2410         switch (eswitch) {
2411         case QED_OV_ESWITCH_NONE:
2412                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2413                 break;
2414         case QED_OV_ESWITCH_VEB:
2415                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2416                 break;
2417         case QED_OV_ESWITCH_VEPA:
2418                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2419                 break;
2420         default:
2421                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2422                 return -EINVAL;
2423         }
2424
2425         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2426                          drv_mb_param, &resp, &param);
2427         if (rc)
2428                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2429
2430         return rc;
2431 }
2432
2433 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2434                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
2435 {
2436         u32 resp = 0, param = 0, drv_mb_param;
2437         int rc;
2438
2439         switch (mode) {
2440         case QED_LED_MODE_ON:
2441                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2442                 break;
2443         case QED_LED_MODE_OFF:
2444                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2445                 break;
2446         case QED_LED_MODE_RESTORE:
2447                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2448                 break;
2449         default:
2450                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2451                 return -EINVAL;
2452         }
2453
2454         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2455                          drv_mb_param, &resp, &param);
2456
2457         return rc;
2458 }
2459
2460 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2461                           struct qed_ptt *p_ptt, u32 mask_parities)
2462 {
2463         u32 resp = 0, param = 0;
2464         int rc;
2465
2466         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2467                          mask_parities, &resp, &param);
2468
2469         if (rc) {
2470                 DP_ERR(p_hwfn,
2471                        "MCP response failure for mask parities, aborting\n");
2472         } else if (resp != FW_MSG_CODE_OK) {
2473                 DP_ERR(p_hwfn,
2474                        "MCP did not acknowledge mask parity request. Old MFW?\n");
2475                 rc = -EINVAL;
2476         }
2477
2478         return rc;
2479 }
2480
2481 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2482 {
2483         u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2484         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2485         u32 resp = 0, resp_param = 0;
2486         struct qed_ptt *p_ptt;
2487         int rc = 0;
2488
2489         p_ptt = qed_ptt_acquire(p_hwfn);
2490         if (!p_ptt)
2491                 return -EBUSY;
2492
2493         while (bytes_left > 0) {
2494                 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2495
2496                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2497                                         DRV_MSG_CODE_NVM_READ_NVRAM,
2498                                         addr + offset +
2499                                         (bytes_to_copy <<
2500                                          DRV_MB_PARAM_NVM_LEN_OFFSET),
2501                                         &resp, &resp_param,
2502                                         &read_len,
2503                                         (u32 *)(p_buf + offset));
2504
2505                 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2506                         DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2507                         break;
2508                 }
2509
2510                 /* This can be a lengthy process, and it's possible scheduler
2511                  * isn't preemptable. Sleep a bit to prevent CPU hogging.
2512                  */
2513                 if (bytes_left % 0x1000 <
2514                     (bytes_left - read_len) % 0x1000)
2515                         usleep_range(1000, 2000);
2516
2517                 offset += read_len;
2518                 bytes_left -= read_len;
2519         }
2520
2521         cdev->mcp_nvm_resp = resp;
2522         qed_ptt_release(p_hwfn, p_ptt);
2523
2524         return rc;
2525 }
2526
2527 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
2528 {
2529         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2530         struct qed_ptt *p_ptt;
2531
2532         p_ptt = qed_ptt_acquire(p_hwfn);
2533         if (!p_ptt)
2534                 return -EBUSY;
2535
2536         memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
2537         qed_ptt_release(p_hwfn, p_ptt);
2538
2539         return 0;
2540 }
2541
2542 int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr)
2543 {
2544         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2545         struct qed_ptt *p_ptt;
2546         u32 resp, param;
2547         int rc;
2548
2549         p_ptt = qed_ptt_acquire(p_hwfn);
2550         if (!p_ptt)
2551                 return -EBUSY;
2552         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2553                          &resp, &param);
2554         cdev->mcp_nvm_resp = resp;
2555         qed_ptt_release(p_hwfn, p_ptt);
2556
2557         return rc;
2558 }
2559
2560 int qed_mcp_nvm_write(struct qed_dev *cdev,
2561                       u32 cmd, u32 addr, u8 *p_buf, u32 len)
2562 {
2563         u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
2564         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2565         struct qed_ptt *p_ptt;
2566         int rc = -EINVAL;
2567
2568         p_ptt = qed_ptt_acquire(p_hwfn);
2569         if (!p_ptt)
2570                 return -EBUSY;
2571
2572         switch (cmd) {
2573         case QED_PUT_FILE_DATA:
2574                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2575                 break;
2576         case QED_NVM_WRITE_NVRAM:
2577                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2578                 break;
2579         default:
2580                 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
2581                 rc = -EINVAL;
2582                 goto out;
2583         }
2584
2585         while (buf_idx < len) {
2586                 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
2587                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2588                               addr) + buf_idx;
2589                 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2590                                         &resp, &param, buf_size,
2591                                         (u32 *)&p_buf[buf_idx]);
2592                 if (rc) {
2593                         DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
2594                         resp = FW_MSG_CODE_ERROR;
2595                         break;
2596                 }
2597
2598                 if (resp != FW_MSG_CODE_OK &&
2599                     resp != FW_MSG_CODE_NVM_OK &&
2600                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2601                         DP_NOTICE(cdev,
2602                                   "nvm write failed, resp = 0x%08x\n", resp);
2603                         rc = -EINVAL;
2604                         break;
2605                 }
2606
2607                 /* This can be a lengthy process, and it's possible scheduler
2608                  * isn't pre-emptable. Sleep a bit to prevent CPU hogging.
2609                  */
2610                 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
2611                         usleep_range(1000, 2000);
2612
2613                 buf_idx += buf_size;
2614         }
2615
2616         cdev->mcp_nvm_resp = resp;
2617 out:
2618         qed_ptt_release(p_hwfn, p_ptt);
2619
2620         return rc;
2621 }
2622
2623 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2624                          u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf)
2625 {
2626         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0;
2627         u32 resp, param;
2628         int rc;
2629
2630         nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) &
2631                        DRV_MB_PARAM_TRANSCEIVER_PORT_MASK;
2632         nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) &
2633                        DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK;
2634
2635         addr = offset;
2636         offset = 0;
2637         bytes_left = len;
2638         while (bytes_left > 0) {
2639                 bytes_to_copy = min_t(u32, bytes_left,
2640                                       MAX_I2C_TRANSACTION_SIZE);
2641                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2642                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2643                 nvm_offset |= ((addr + offset) <<
2644                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) &
2645                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK;
2646                 nvm_offset |= (bytes_to_copy <<
2647                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) &
2648                                DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK;
2649                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2650                                         DRV_MSG_CODE_TRANSCEIVER_READ,
2651                                         nvm_offset, &resp, &param, &buf_size,
2652                                         (u32 *)(p_buf + offset));
2653                 if (rc) {
2654                         DP_NOTICE(p_hwfn,
2655                                   "Failed to send a transceiver read command to the MFW. rc = %d.\n",
2656                                   rc);
2657                         return rc;
2658                 }
2659
2660                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
2661                         return -ENODEV;
2662                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2663                         return -EINVAL;
2664
2665                 offset += buf_size;
2666                 bytes_left -= buf_size;
2667         }
2668
2669         return 0;
2670 }
2671
2672 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2673 {
2674         u32 drv_mb_param = 0, rsp, param;
2675         int rc = 0;
2676
2677         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2678                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2679
2680         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2681                          drv_mb_param, &rsp, &param);
2682
2683         if (rc)
2684                 return rc;
2685
2686         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2687             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2688                 rc = -EAGAIN;
2689
2690         return rc;
2691 }
2692
2693 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2694 {
2695         u32 drv_mb_param, rsp, param;
2696         int rc = 0;
2697
2698         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2699                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2700
2701         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2702                          drv_mb_param, &rsp, &param);
2703
2704         if (rc)
2705                 return rc;
2706
2707         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2708             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2709                 rc = -EAGAIN;
2710
2711         return rc;
2712 }
2713
2714 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
2715                                     struct qed_ptt *p_ptt,
2716                                     u32 *num_images)
2717 {
2718         u32 drv_mb_param = 0, rsp;
2719         int rc = 0;
2720
2721         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2722                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2723
2724         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2725                          drv_mb_param, &rsp, num_images);
2726         if (rc)
2727                 return rc;
2728
2729         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2730                 rc = -EINVAL;
2731
2732         return rc;
2733 }
2734
2735 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
2736                                    struct qed_ptt *p_ptt,
2737                                    struct bist_nvm_image_att *p_image_att,
2738                                    u32 image_index)
2739 {
2740         u32 buf_size = 0, param, resp = 0, resp_param = 0;
2741         int rc;
2742
2743         param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2744                 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
2745         param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
2746
2747         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2748                                 DRV_MSG_CODE_BIST_TEST, param,
2749                                 &resp, &resp_param,
2750                                 &buf_size,
2751                                 (u32 *)p_image_att);
2752         if (rc)
2753                 return rc;
2754
2755         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2756             (p_image_att->return_code != 1))
2757                 rc = -EINVAL;
2758
2759         return rc;
2760 }
2761
2762 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
2763 {
2764         struct qed_nvm_image_info nvm_info;
2765         struct qed_ptt *p_ptt;
2766         int rc;
2767         u32 i;
2768
2769         if (p_hwfn->nvm_info.valid)
2770                 return 0;
2771
2772         p_ptt = qed_ptt_acquire(p_hwfn);
2773         if (!p_ptt) {
2774                 DP_ERR(p_hwfn, "failed to acquire ptt\n");
2775                 return -EBUSY;
2776         }
2777
2778         /* Acquire from MFW the amount of available images */
2779         nvm_info.num_images = 0;
2780         rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
2781                                              p_ptt, &nvm_info.num_images);
2782         if (rc == -EOPNOTSUPP) {
2783                 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
2784                 goto out;
2785         } else if (rc || !nvm_info.num_images) {
2786                 DP_ERR(p_hwfn, "Failed getting number of images\n");
2787                 goto err0;
2788         }
2789
2790         nvm_info.image_att = kmalloc_array(nvm_info.num_images,
2791                                            sizeof(struct bist_nvm_image_att),
2792                                            GFP_KERNEL);
2793         if (!nvm_info.image_att) {
2794                 rc = -ENOMEM;
2795                 goto err0;
2796         }
2797
2798         /* Iterate over images and get their attributes */
2799         for (i = 0; i < nvm_info.num_images; i++) {
2800                 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
2801                                                     &nvm_info.image_att[i], i);
2802                 if (rc) {
2803                         DP_ERR(p_hwfn,
2804                                "Failed getting image index %d attributes\n", i);
2805                         goto err1;
2806                 }
2807
2808                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
2809                            nvm_info.image_att[i].len);
2810         }
2811 out:
2812         /* Update hwfn's nvm_info */
2813         if (nvm_info.num_images) {
2814                 p_hwfn->nvm_info.num_images = nvm_info.num_images;
2815                 kfree(p_hwfn->nvm_info.image_att);
2816                 p_hwfn->nvm_info.image_att = nvm_info.image_att;
2817                 p_hwfn->nvm_info.valid = true;
2818         }
2819
2820         qed_ptt_release(p_hwfn, p_ptt);
2821         return 0;
2822
2823 err1:
2824         kfree(nvm_info.image_att);
2825 err0:
2826         qed_ptt_release(p_hwfn, p_ptt);
2827         return rc;
2828 }
2829
2830 int
2831 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
2832                           enum qed_nvm_images image_id,
2833                           struct qed_nvm_image_att *p_image_att)
2834 {
2835         enum nvm_image_type type;
2836         u32 i;
2837
2838         /* Translate image_id into MFW definitions */
2839         switch (image_id) {
2840         case QED_NVM_IMAGE_ISCSI_CFG:
2841                 type = NVM_TYPE_ISCSI_CFG;
2842                 break;
2843         case QED_NVM_IMAGE_FCOE_CFG:
2844                 type = NVM_TYPE_FCOE_CFG;
2845                 break;
2846         case QED_NVM_IMAGE_NVM_CFG1:
2847                 type = NVM_TYPE_NVM_CFG1;
2848                 break;
2849         case QED_NVM_IMAGE_DEFAULT_CFG:
2850                 type = NVM_TYPE_DEFAULT_CFG;
2851                 break;
2852         case QED_NVM_IMAGE_NVM_META:
2853                 type = NVM_TYPE_META;
2854                 break;
2855         default:
2856                 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
2857                           image_id);
2858                 return -EINVAL;
2859         }
2860
2861         qed_mcp_nvm_info_populate(p_hwfn);
2862         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2863                 if (type == p_hwfn->nvm_info.image_att[i].image_type)
2864                         break;
2865         if (i == p_hwfn->nvm_info.num_images) {
2866                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2867                            "Failed to find nvram image of type %08x\n",
2868                            image_id);
2869                 return -ENOENT;
2870         }
2871
2872         p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2873         p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
2874
2875         return 0;
2876 }
2877
2878 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
2879                           enum qed_nvm_images image_id,
2880                           u8 *p_buffer, u32 buffer_len)
2881 {
2882         struct qed_nvm_image_att image_att;
2883         int rc;
2884
2885         memset(p_buffer, 0, buffer_len);
2886
2887         rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
2888         if (rc)
2889                 return rc;
2890
2891         /* Validate sizes - both the image's and the supplied buffer's */
2892         if (image_att.length <= 4) {
2893                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2894                            "Image [%d] is too small - only %d bytes\n",
2895                            image_id, image_att.length);
2896                 return -EINVAL;
2897         }
2898
2899         if (image_att.length > buffer_len) {
2900                 DP_VERBOSE(p_hwfn,
2901                            QED_MSG_STORAGE,
2902                            "Image [%d] is too big - %08x bytes where only %08x are available\n",
2903                            image_id, image_att.length, buffer_len);
2904                 return -ENOMEM;
2905         }
2906
2907         return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
2908                                 p_buffer, image_att.length);
2909 }
2910
2911 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
2912 {
2913         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2914
2915         switch (res_id) {
2916         case QED_SB:
2917                 mfw_res_id = RESOURCE_NUM_SB_E;
2918                 break;
2919         case QED_L2_QUEUE:
2920                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2921                 break;
2922         case QED_VPORT:
2923                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2924                 break;
2925         case QED_RSS_ENG:
2926                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2927                 break;
2928         case QED_PQ:
2929                 mfw_res_id = RESOURCE_NUM_PQ_E;
2930                 break;
2931         case QED_RL:
2932                 mfw_res_id = RESOURCE_NUM_RL_E;
2933                 break;
2934         case QED_MAC:
2935         case QED_VLAN:
2936                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2937                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2938                 break;
2939         case QED_ILT:
2940                 mfw_res_id = RESOURCE_ILT_E;
2941                 break;
2942         case QED_LL2_QUEUE:
2943                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2944                 break;
2945         case QED_RDMA_CNQ_RAM:
2946         case QED_CMDQS_CQS:
2947                 /* CNQ/CMDQS are the same resource */
2948                 mfw_res_id = RESOURCE_CQS_E;
2949                 break;
2950         case QED_RDMA_STATS_QUEUE:
2951                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2952                 break;
2953         case QED_BDQ:
2954                 mfw_res_id = RESOURCE_BDQ_E;
2955                 break;
2956         default:
2957                 break;
2958         }
2959
2960         return mfw_res_id;
2961 }
2962
2963 #define QED_RESC_ALLOC_VERSION_MAJOR    2
2964 #define QED_RESC_ALLOC_VERSION_MINOR    0
2965 #define QED_RESC_ALLOC_VERSION                               \
2966         ((QED_RESC_ALLOC_VERSION_MAJOR <<                    \
2967           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2968          (QED_RESC_ALLOC_VERSION_MINOR <<                    \
2969           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2970
2971 struct qed_resc_alloc_in_params {
2972         u32 cmd;
2973         enum qed_resources res_id;
2974         u32 resc_max_val;
2975 };
2976
2977 struct qed_resc_alloc_out_params {
2978         u32 mcp_resp;
2979         u32 mcp_param;
2980         u32 resc_num;
2981         u32 resc_start;
2982         u32 vf_resc_num;
2983         u32 vf_resc_start;
2984         u32 flags;
2985 };
2986
2987 static int
2988 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
2989                             struct qed_ptt *p_ptt,
2990                             struct qed_resc_alloc_in_params *p_in_params,
2991                             struct qed_resc_alloc_out_params *p_out_params)
2992 {
2993         struct qed_mcp_mb_params mb_params;
2994         struct resource_info mfw_resc_info;
2995         int rc;
2996
2997         memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
2998
2999         mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
3000         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3001                 DP_ERR(p_hwfn,
3002                        "Failed to match resource %d [%s] with the MFW resources\n",
3003                        p_in_params->res_id,
3004                        qed_hw_get_resc_name(p_in_params->res_id));
3005                 return -EINVAL;
3006         }
3007
3008         switch (p_in_params->cmd) {
3009         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3010                 mfw_resc_info.size = p_in_params->resc_max_val;
3011                 /* Fallthrough */
3012         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3013                 break;
3014         default:
3015                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3016                        p_in_params->cmd);
3017                 return -EINVAL;
3018         }
3019
3020         memset(&mb_params, 0, sizeof(mb_params));
3021         mb_params.cmd = p_in_params->cmd;
3022         mb_params.param = QED_RESC_ALLOC_VERSION;
3023         mb_params.p_data_src = &mfw_resc_info;
3024         mb_params.data_src_size = sizeof(mfw_resc_info);
3025         mb_params.p_data_dst = mb_params.p_data_src;
3026         mb_params.data_dst_size = mb_params.data_src_size;
3027
3028         DP_VERBOSE(p_hwfn,
3029                    QED_MSG_SP,
3030                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3031                    p_in_params->cmd,
3032                    p_in_params->res_id,
3033                    qed_hw_get_resc_name(p_in_params->res_id),
3034                    QED_MFW_GET_FIELD(mb_params.param,
3035                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3036                    QED_MFW_GET_FIELD(mb_params.param,
3037                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3038                    p_in_params->resc_max_val);
3039
3040         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3041         if (rc)
3042                 return rc;
3043
3044         p_out_params->mcp_resp = mb_params.mcp_resp;
3045         p_out_params->mcp_param = mb_params.mcp_param;
3046         p_out_params->resc_num = mfw_resc_info.size;
3047         p_out_params->resc_start = mfw_resc_info.offset;
3048         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3049         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3050         p_out_params->flags = mfw_resc_info.flags;
3051
3052         DP_VERBOSE(p_hwfn,
3053                    QED_MSG_SP,
3054                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3055                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3056                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3057                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3058                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3059                    p_out_params->resc_num,
3060                    p_out_params->resc_start,
3061                    p_out_params->vf_resc_num,
3062                    p_out_params->vf_resc_start, p_out_params->flags);
3063
3064         return 0;
3065 }
3066
3067 int
3068 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
3069                          struct qed_ptt *p_ptt,
3070                          enum qed_resources res_id,
3071                          u32 resc_max_val, u32 *p_mcp_resp)
3072 {
3073         struct qed_resc_alloc_out_params out_params;
3074         struct qed_resc_alloc_in_params in_params;
3075         int rc;
3076
3077         memset(&in_params, 0, sizeof(in_params));
3078         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3079         in_params.res_id = res_id;
3080         in_params.resc_max_val = resc_max_val;
3081         memset(&out_params, 0, sizeof(out_params));
3082         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3083                                          &out_params);
3084         if (rc)
3085                 return rc;
3086
3087         *p_mcp_resp = out_params.mcp_resp;
3088
3089         return 0;
3090 }
3091
3092 int
3093 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
3094                       struct qed_ptt *p_ptt,
3095                       enum qed_resources res_id,
3096                       u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
3097 {
3098         struct qed_resc_alloc_out_params out_params;
3099         struct qed_resc_alloc_in_params in_params;
3100         int rc;
3101
3102         memset(&in_params, 0, sizeof(in_params));
3103         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3104         in_params.res_id = res_id;
3105         memset(&out_params, 0, sizeof(out_params));
3106         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3107                                          &out_params);
3108         if (rc)
3109                 return rc;
3110
3111         *p_mcp_resp = out_params.mcp_resp;
3112
3113         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3114                 *p_resc_num = out_params.resc_num;
3115                 *p_resc_start = out_params.resc_start;
3116         }
3117
3118         return 0;
3119 }
3120
3121 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3122 {
3123         u32 mcp_resp, mcp_param;
3124
3125         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3126                            &mcp_resp, &mcp_param);
3127 }
3128
3129 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
3130                                 struct qed_ptt *p_ptt,
3131                                 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
3132 {
3133         int rc;
3134
3135         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3136                          p_mcp_resp, p_mcp_param);
3137         if (rc)
3138                 return rc;
3139
3140         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3141                 DP_INFO(p_hwfn,
3142                         "The resource command is unsupported by the MFW\n");
3143                 return -EINVAL;
3144         }
3145
3146         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3147                 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3148
3149                 DP_NOTICE(p_hwfn,
3150                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3151                           param, opcode);
3152                 return -EINVAL;
3153         }
3154
3155         return rc;
3156 }
3157
3158 static int
3159 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3160                     struct qed_ptt *p_ptt,
3161                     struct qed_resc_lock_params *p_params)
3162 {
3163         u32 param = 0, mcp_resp, mcp_param;
3164         u8 opcode;
3165         int rc;
3166
3167         switch (p_params->timeout) {
3168         case QED_MCP_RESC_LOCK_TO_DEFAULT:
3169                 opcode = RESOURCE_OPCODE_REQ;
3170                 p_params->timeout = 0;
3171                 break;
3172         case QED_MCP_RESC_LOCK_TO_NONE:
3173                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3174                 p_params->timeout = 0;
3175                 break;
3176         default:
3177                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3178                 break;
3179         }
3180
3181         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3182         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3183         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3184
3185         DP_VERBOSE(p_hwfn,
3186                    QED_MSG_SP,
3187                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3188                    param, p_params->timeout, opcode, p_params->resource);
3189
3190         /* Attempt to acquire the resource */
3191         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3192         if (rc)
3193                 return rc;
3194
3195         /* Analyze the response */
3196         p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3197         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3198
3199         DP_VERBOSE(p_hwfn,
3200                    QED_MSG_SP,
3201                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3202                    mcp_param, opcode, p_params->owner);
3203
3204         switch (opcode) {
3205         case RESOURCE_OPCODE_GNT:
3206                 p_params->b_granted = true;
3207                 break;
3208         case RESOURCE_OPCODE_BUSY:
3209                 p_params->b_granted = false;
3210                 break;
3211         default:
3212                 DP_NOTICE(p_hwfn,
3213                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3214                           mcp_param, opcode);
3215                 return -EINVAL;
3216         }
3217
3218         return 0;
3219 }
3220
3221 int
3222 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3223                   struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
3224 {
3225         u32 retry_cnt = 0;
3226         int rc;
3227
3228         do {
3229                 /* No need for an interval before the first iteration */
3230                 if (retry_cnt) {
3231                         if (p_params->sleep_b4_retry) {
3232                                 u16 retry_interval_in_ms =
3233                                     DIV_ROUND_UP(p_params->retry_interval,
3234                                                  1000);
3235
3236                                 msleep(retry_interval_in_ms);
3237                         } else {
3238                                 udelay(p_params->retry_interval);
3239                         }
3240                 }
3241
3242                 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3243                 if (rc)
3244                         return rc;
3245
3246                 if (p_params->b_granted)
3247                         break;
3248         } while (retry_cnt++ < p_params->retry_num);
3249
3250         return 0;
3251 }
3252
3253 int
3254 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
3255                     struct qed_ptt *p_ptt,
3256                     struct qed_resc_unlock_params *p_params)
3257 {
3258         u32 param = 0, mcp_resp, mcp_param;
3259         u8 opcode;
3260         int rc;
3261
3262         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3263                                    : RESOURCE_OPCODE_RELEASE;
3264         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3265         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3266
3267         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3268                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3269                    param, opcode, p_params->resource);
3270
3271         /* Attempt to release the resource */
3272         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3273         if (rc)
3274                 return rc;
3275
3276         /* Analyze the response */
3277         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3278
3279         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3280                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3281                    mcp_param, opcode);
3282
3283         switch (opcode) {
3284         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3285                 DP_INFO(p_hwfn,
3286                         "Resource unlock request for an already released resource [%d]\n",
3287                         p_params->resource);
3288                 /* Fallthrough */
3289         case RESOURCE_OPCODE_RELEASED:
3290                 p_params->b_released = true;
3291                 break;
3292         case RESOURCE_OPCODE_WRONG_OWNER:
3293                 p_params->b_released = false;
3294                 break;
3295         default:
3296                 DP_NOTICE(p_hwfn,
3297                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3298                           mcp_param, opcode);
3299                 return -EINVAL;
3300         }
3301
3302         return 0;
3303 }
3304
3305 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
3306                                     struct qed_resc_unlock_params *p_unlock,
3307                                     enum qed_resc_lock
3308                                     resource, bool b_is_permanent)
3309 {
3310         if (p_lock) {
3311                 memset(p_lock, 0, sizeof(*p_lock));
3312
3313                 /* Permanent resources don't require aging, and there's no
3314                  * point in trying to acquire them more than once since it's
3315                  * unexpected another entity would release them.
3316                  */
3317                 if (b_is_permanent) {
3318                         p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
3319                 } else {
3320                         p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3321                         p_lock->retry_interval =
3322                             QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3323                         p_lock->sleep_b4_retry = true;
3324                 }
3325
3326                 p_lock->resource = resource;
3327         }
3328
3329         if (p_unlock) {
3330                 memset(p_unlock, 0, sizeof(*p_unlock));
3331                 p_unlock->resource = resource;
3332         }
3333 }
3334
3335 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3336 {
3337         u32 mcp_resp;
3338         int rc;
3339
3340         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3341                          0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3342         if (!rc)
3343                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
3344                            "MFW supported features: %08x\n",
3345                            p_hwfn->mcp_info->capabilities);
3346
3347         return rc;
3348 }
3349
3350 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3351 {
3352         u32 mcp_resp, mcp_param, features;
3353
3354         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3355
3356         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3357                            features, &mcp_resp, &mcp_param);
3358 }