1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
15 struct mlxsw_reg_info {
21 #define MLXSW_REG_DEFINE(_name, _id, _len) \
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
34 * This register is used for configuration of the switch capabilities.
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
42 * Link Local Broadcast (Default=0)
43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44 * packets and ignore the IGMP snooping entries.
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
57 * The SPAD register configures the switch physical MAC address.
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
65 * Base MAC address for the switch partitions.
66 * Per switch partition MAC address is equal to:
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
72 /* SMID - Switch Multicast ID
73 * --------------------------
74 * The MID record maps from a MID (Multicast ID), which is a unique identifier
75 * of the multicast group within the stacking domain, into a list of local
76 * ports into which the packet is replicated.
78 #define MLXSW_REG_SMID_ID 0x2007
79 #define MLXSW_REG_SMID_LEN 0x240
81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
84 * Switch partition ID.
87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
90 * Multicast identifier - global identifier that represents the multicast group
94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
97 * Local port memebership (1 bit per port).
100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
102 /* reg_smid_port_mask
103 * Local port mask (1 bit per port).
106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
111 MLXSW_REG_ZERO(smid, payload);
112 mlxsw_reg_smid_swid_set(payload, 0);
113 mlxsw_reg_smid_mid_set(payload, mid);
114 mlxsw_reg_smid_port_set(payload, port, set);
115 mlxsw_reg_smid_port_mask_set(payload, port, 1);
118 /* SSPR - Switch System Port Record Register
119 * -----------------------------------------
120 * Configures the system port to local port mapping.
122 #define MLXSW_REG_SSPR_ID 0x2008
123 #define MLXSW_REG_SSPR_LEN 0x8
125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
128 * Master - if set, then the record describes the master system port.
129 * This is needed in case a local port is mapped into several system ports
130 * (for multipathing). That number will be reported as the source system
131 * port when packets are forwarded to the CPU. Only one master port is allowed
134 * Note: Must be set for Spectrum.
137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
139 /* reg_sspr_local_port
144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
147 * Virtual port within the physical port.
148 * Should be set to 0 when virtual ports are not enabled on the port.
152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
154 /* reg_sspr_system_port
155 * Unique identifier within the stacking domain that represents all the ports
156 * that are available in the system (external ports).
158 * Currently, only single-ASIC configurations are supported, so we default to
159 * 1:1 mapping between system ports and local ports.
162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
173 /* SFDAT - Switch Filtering Database Aging Time
174 * --------------------------------------------
175 * Controls the Switch aging time. Aging time is able to be set per Switch
178 #define MLXSW_REG_SFDAT_ID 0x2009
179 #define MLXSW_REG_SFDAT_LEN 0x8
181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
184 * Switch partition ID.
187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
189 /* reg_sfdat_age_time
190 * Aging time in seconds
192 * Max - 1,000,000 seconds
193 * Default is 300 seconds.
196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
200 MLXSW_REG_ZERO(sfdat, payload);
201 mlxsw_reg_sfdat_swid_set(payload, 0);
202 mlxsw_reg_sfdat_age_time_set(payload, age_time);
205 /* SFD - Switch Filtering Database
206 * -------------------------------
207 * The following register defines the access to the filtering database.
208 * The register supports querying, adding, removing and modifying the database.
209 * The access is optimized for bulk updates in which case more than one
210 * FDB record is present in the same command.
212 #define MLXSW_REG_SFD_ID 0x200A
213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
222 * Switch partition ID for queries. Reserved on Write.
225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
227 enum mlxsw_reg_sfd_op {
228 /* Dump entire FDB a (process according to record_locator) */
229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230 /* Query records by {MAC, VID/FID} value */
231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232 /* Query and clear activity. Query records by {MAC, VID/FID} value */
233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234 /* Test. Response indicates if each of the records could be
237 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238 /* Add/modify. Aged-out records cannot be added. This command removes
239 * the learning notification of the {MAC, VID/FID}. Response includes
240 * the entries that were added to the FDB.
242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243 /* Remove record by {MAC, VID/FID}. This command also removes
244 * the learning notification and aged-out notifications
245 * of the {MAC, VID/FID}. The response provides current (pre-removal)
246 * entries as non-aged-out.
248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249 /* Remove learned notification by {MAC, VID/FID}. The response provides
250 * the removed learning notification.
252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
261 /* reg_sfd_record_locator
262 * Used for querying the FDB. Use record_locator=0 to initiate the
263 * query. When a record is returned, a new record_locator is
264 * returned to be used in the subsequent query.
265 * Reserved for database update.
268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
271 * Request: Number of records to read/add/modify/remove
272 * Response: Number of records read/added/replaced/removed
273 * See above description for more details.
277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
282 MLXSW_REG_ZERO(sfd, payload);
283 mlxsw_reg_sfd_op_set(payload, op);
284 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
288 * Switch partition ID.
291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 MLXSW_REG_SFD_REC_LEN, 0x00, false);
294 enum mlxsw_reg_sfd_rec_type {
295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 MLXSW_REG_SFD_REC_LEN, 0x00, false);
308 enum mlxsw_reg_sfd_rec_policy {
309 /* Replacement disabled, aging disabled. */
310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311 /* (mlag remote): Replacement enabled, aging disabled,
312 * learning notification enabled on this port.
314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315 /* (ingress device): Replacement enabled, aging enabled. */
316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
319 /* reg_sfd_rec_policy
323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 MLXSW_REG_SFD_REC_LEN, 0x00, false);
327 * Activity. Set for new static entries. Set for static entries if a frame SMAC
328 * lookup hits on the entry.
329 * To clear the a bit, use "query and clear activity" op.
332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 MLXSW_REG_SFD_REC_LEN, 0x00, false);
339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 MLXSW_REG_SFD_REC_LEN, 0x02);
342 enum mlxsw_reg_sfd_rec_action {
344 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345 /* forward and trap, trap_id is FDB_TRAP */
346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347 /* trap and do not forward, trap_id is FDB_TRAP */
348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349 /* forward to IP router */
350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
354 /* reg_sfd_rec_action
355 * Action to apply on the packet.
356 * Note: Dynamic entries can only be configured with NOP action.
359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
362 /* reg_sfd_uc_sub_port
363 * VEPA channel on local port.
364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
365 * VEPA is not enabled.
368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 MLXSW_REG_SFD_REC_LEN, 0x08, false);
371 /* reg_sfd_uc_fid_vid
372 * Filtering ID or VLAN ID
373 * For SwitchX and SwitchX-2:
374 * - Dynamic entries (policy 2,3) use FID
375 * - Static entries (policy 0) use VID
376 * - When independent learning is configured, VID=FID
377 * For Spectrum: use FID for both Dynamic and Static entries.
378 * VID should not be used.
381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 MLXSW_REG_SFD_REC_LEN, 0x08, false);
384 /* reg_sfd_uc_system_port
385 * Unique port identifier for the final destination of the packet.
388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 enum mlxsw_reg_sfd_rec_type rec_type,
394 enum mlxsw_reg_sfd_rec_action action)
396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
398 if (rec_index >= num_rec)
399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 char *mac, u16 *p_fid_vid,
424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
429 /* reg_sfd_uc_lag_sub_port
431 * Must be 0 if multichannel VEPA is not enabled.
434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 MLXSW_REG_SFD_REC_LEN, 0x08, false);
437 /* reg_sfd_uc_lag_fid_vid
438 * Filtering ID or VLAN ID
439 * For SwitchX and SwitchX-2:
440 * - Dynamic entries (policy 2,3) use FID
441 * - Static entries (policy 0) use VID
442 * - When independent learning is configured, VID=FID
443 * For Spectrum: use FID for both Dynamic and Static entries.
444 * VID should not be used.
447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 MLXSW_REG_SFD_REC_LEN, 0x08, false);
450 /* reg_sfd_uc_lag_lag_vid
451 * Indicates VID in case of vFIDs. Reserved for FIDs.
454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
457 /* reg_sfd_uc_lag_lag_id
458 * LAG Identifier - pointer into the LAG descriptor table.
461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 enum mlxsw_reg_sfd_rec_policy policy,
467 const char *mac, u16 fid_vid,
468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
471 mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 char *mac, u16 *p_vid,
485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
492 * Multicast port group index - index into the port group table.
493 * Value 0x1FFF indicates the pgi should point to the MID entry.
494 * For Spectrum this value must be set to 0x1FFF
497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 MLXSW_REG_SFD_REC_LEN, 0x08, false);
500 /* reg_sfd_mc_fid_vid
502 * Filtering ID or VLAN ID
505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 MLXSW_REG_SFD_REC_LEN, 0x08, false);
510 * Multicast identifier - global identifier that represents the multicast
511 * group across all devices.
514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 const char *mac, u16 fid_vid,
520 enum mlxsw_reg_sfd_rec_action action, u16 mid)
522 mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
529 /* reg_sfd_uc_tunnel_uip_msb
530 * When protocol is IPv4, the most significant byte of the underlay IPv4
532 * When protocol is IPv6, reserved.
535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
538 /* reg_sfd_uc_tunnel_fid
542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 MLXSW_REG_SFD_REC_LEN, 0x08, false);
545 enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
550 /* reg_sfd_uc_tunnel_protocol
554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
557 /* reg_sfd_uc_tunnel_uip_lsb
558 * When protocol is IPv4, the least significant bytes of the underlay
559 * IPv4 destination IP.
560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP
561 * which is configured by RIPS.
564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 enum mlxsw_reg_sfd_rec_policy policy,
570 const char *mac, u16 fid,
571 enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
574 mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
584 /* SFN - Switch FDB Notification Register
585 * -------------------------------------------
586 * The switch provides notifications on newly learned FDB entries and
587 * aged out entries. The notifications can be polled by software.
589 #define MLXSW_REG_SFN_ID 0x200B
590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
599 * Switch partition ID.
602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
605 * Forces the current session to end.
608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
611 * Request: Number of learned notifications and aged-out notification
613 * Response: Number of notification records returned (must be smaller
614 * than or equal to the value requested)
618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
620 static inline void mlxsw_reg_sfn_pack(char *payload)
622 MLXSW_REG_ZERO(sfn, payload);
623 mlxsw_reg_sfn_swid_set(payload, 0);
624 mlxsw_reg_sfn_end_set(payload, 1);
625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
629 * Switch partition ID.
632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
633 MLXSW_REG_SFN_REC_LEN, 0x00, false);
635 enum mlxsw_reg_sfn_rec_type {
636 /* MAC addresses learned on a regular port. */
637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
638 /* MAC addresses learned on a LAG port. */
639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
640 /* Aged-out MAC address on a regular port. */
641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
642 /* Aged-out MAC address on a LAG port. */
643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
647 * Notification record type.
650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
651 MLXSW_REG_SFN_REC_LEN, 0x00, false);
657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
658 MLXSW_REG_SFN_REC_LEN, 0x02);
660 /* reg_sfn_mac_sub_port
661 * VEPA channel on the local port.
662 * 0 if multichannel VEPA is not enabled.
665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
666 MLXSW_REG_SFN_REC_LEN, 0x08, false);
669 * Filtering identifier.
672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
673 MLXSW_REG_SFN_REC_LEN, 0x08, false);
675 /* reg_sfn_mac_system_port
676 * Unique port identifier for the final destination of the packet.
679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
680 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
682 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
683 char *mac, u16 *p_vid,
686 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
687 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
688 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
691 /* reg_sfn_mac_lag_lag_id
692 * LAG ID (pointer into the LAG descriptor table).
695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
696 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
698 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
699 char *mac, u16 *p_vid,
702 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
703 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
704 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
707 /* SPMS - Switch Port MSTP/RSTP State Register
708 * -------------------------------------------
709 * Configures the spanning tree state of a physical port.
711 #define MLXSW_REG_SPMS_ID 0x200D
712 #define MLXSW_REG_SPMS_LEN 0x404
714 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
716 /* reg_spms_local_port
720 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
722 enum mlxsw_reg_spms_state {
723 MLXSW_REG_SPMS_STATE_NO_CHANGE,
724 MLXSW_REG_SPMS_STATE_DISCARDING,
725 MLXSW_REG_SPMS_STATE_LEARNING,
726 MLXSW_REG_SPMS_STATE_FORWARDING,
730 * Spanning tree state of each VLAN ID (VID) of the local port.
731 * 0 - Do not change spanning tree state (used only when writing).
732 * 1 - Discarding. No learning or forwarding to/from this port (default).
733 * 2 - Learning. Port is learning, but not forwarding.
734 * 3 - Forwarding. Port is learning and forwarding.
737 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
739 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
741 MLXSW_REG_ZERO(spms, payload);
742 mlxsw_reg_spms_local_port_set(payload, local_port);
745 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
746 enum mlxsw_reg_spms_state state)
748 mlxsw_reg_spms_state_set(payload, vid, state);
751 /* SPVID - Switch Port VID
752 * -----------------------
753 * The switch port VID configures the default VID for a port.
755 #define MLXSW_REG_SPVID_ID 0x200E
756 #define MLXSW_REG_SPVID_LEN 0x08
758 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
760 /* reg_spvid_local_port
764 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
766 /* reg_spvid_sub_port
767 * Virtual port within the physical port.
768 * Should be set to 0 when virtual ports are not enabled on the port.
771 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
777 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
779 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
781 MLXSW_REG_ZERO(spvid, payload);
782 mlxsw_reg_spvid_local_port_set(payload, local_port);
783 mlxsw_reg_spvid_pvid_set(payload, pvid);
786 /* SPVM - Switch Port VLAN Membership
787 * ----------------------------------
788 * The Switch Port VLAN Membership register configures the VLAN membership
789 * of a port in a VLAN denoted by VID. VLAN membership is managed per
790 * virtual port. The register can be used to add and remove VID(s) from a port.
792 #define MLXSW_REG_SPVM_ID 0x200F
793 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
794 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
795 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
796 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
797 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
799 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
802 * Priority tagged. If this bit is set, packets forwarded to the port with
803 * untagged VLAN membership (u bit is set) will be tagged with priority tag
807 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
810 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
811 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
814 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
816 /* reg_spvm_local_port
820 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
823 * Virtual port within the physical port.
824 * Should be set to 0 when virtual ports are not enabled on the port.
827 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
830 * Number of records to update. Each record contains: i, e, u, vid.
833 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
836 * Ingress membership in VLAN ID.
839 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
840 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
841 MLXSW_REG_SPVM_REC_LEN, 0, false);
844 * Egress membership in VLAN ID.
847 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
848 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
849 MLXSW_REG_SPVM_REC_LEN, 0, false);
852 * Untagged - port is an untagged member - egress transmission uses untagged
856 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
857 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
858 MLXSW_REG_SPVM_REC_LEN, 0, false);
861 * Egress membership in VLAN ID.
864 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
865 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
866 MLXSW_REG_SPVM_REC_LEN, 0, false);
868 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
869 u16 vid_begin, u16 vid_end,
870 bool is_member, bool untagged)
872 int size = vid_end - vid_begin + 1;
875 MLXSW_REG_ZERO(spvm, payload);
876 mlxsw_reg_spvm_local_port_set(payload, local_port);
877 mlxsw_reg_spvm_num_rec_set(payload, size);
879 for (i = 0; i < size; i++) {
880 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
881 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
882 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
883 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
887 /* SPAFT - Switch Port Acceptable Frame Types
888 * ------------------------------------------
889 * The Switch Port Acceptable Frame Types register configures the frame
890 * admittance of the port.
892 #define MLXSW_REG_SPAFT_ID 0x2010
893 #define MLXSW_REG_SPAFT_LEN 0x08
895 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
897 /* reg_spaft_local_port
901 * Note: CPU port is not supported (all tag types are allowed).
903 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
905 /* reg_spaft_sub_port
906 * Virtual port within the physical port.
907 * Should be set to 0 when virtual ports are not enabled on the port.
910 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
912 /* reg_spaft_allow_untagged
913 * When set, untagged frames on the ingress are allowed (default).
916 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
918 /* reg_spaft_allow_prio_tagged
919 * When set, priority tagged frames on the ingress are allowed (default).
922 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
924 /* reg_spaft_allow_tagged
925 * When set, tagged frames on the ingress are allowed (default).
928 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
930 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
933 MLXSW_REG_ZERO(spaft, payload);
934 mlxsw_reg_spaft_local_port_set(payload, local_port);
935 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
936 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
937 mlxsw_reg_spaft_allow_tagged_set(payload, true);
940 /* SFGC - Switch Flooding Group Configuration
941 * ------------------------------------------
942 * The following register controls the association of flooding tables and MIDs
943 * to packet types used for flooding.
945 #define MLXSW_REG_SFGC_ID 0x2011
946 #define MLXSW_REG_SFGC_LEN 0x10
948 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
950 enum mlxsw_reg_sfgc_type {
951 MLXSW_REG_SFGC_TYPE_BROADCAST,
952 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
953 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
954 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
955 MLXSW_REG_SFGC_TYPE_RESERVED,
956 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
957 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
958 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
959 MLXSW_REG_SFGC_TYPE_MAX,
963 * The traffic type to reach the flooding table.
966 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
968 enum mlxsw_reg_sfgc_bridge_type {
969 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
970 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
973 /* reg_sfgc_bridge_type
976 * Note: SwitchX-2 only supports 802.1Q mode.
978 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
980 enum mlxsw_flood_table_type {
981 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
982 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
983 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
984 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
985 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
988 /* reg_sfgc_table_type
989 * See mlxsw_flood_table_type
992 * Note: FID offset and FID types are not supported in SwitchX-2.
994 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
996 /* reg_sfgc_flood_table
997 * Flooding table index to associate with the specific type on the specific
1001 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1004 * The multicast ID for the swid. Not supported for Spectrum
1007 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1009 /* reg_sfgc_counter_set_type
1010 * Counter Set Type for flow counters.
1013 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1015 /* reg_sfgc_counter_index
1016 * Counter Index for flow counters.
1019 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1022 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1023 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1024 enum mlxsw_flood_table_type table_type,
1025 unsigned int flood_table)
1027 MLXSW_REG_ZERO(sfgc, payload);
1028 mlxsw_reg_sfgc_type_set(payload, type);
1029 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1030 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1031 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1032 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1035 /* SFTR - Switch Flooding Table Register
1036 * -------------------------------------
1037 * The switch flooding table is used for flooding packet replication. The table
1038 * defines a bit mask of ports for packet replication.
1040 #define MLXSW_REG_SFTR_ID 0x2012
1041 #define MLXSW_REG_SFTR_LEN 0x420
1043 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1046 * Switch partition ID with which to associate the port.
1049 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1051 /* reg_sftr_flood_table
1052 * Flooding table index to associate with the specific type on the specific
1056 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1059 * Index. Used as an index into the Flooding Table in case the table is
1060 * configured to use VID / FID or FID Offset.
1063 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1065 /* reg_sftr_table_type
1066 * See mlxsw_flood_table_type
1069 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1072 * Range of entries to update
1075 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1078 * Local port membership (1 bit per port).
1081 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1083 /* reg_sftr_cpu_port_mask
1084 * CPU port mask (1 bit per port).
1087 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1089 static inline void mlxsw_reg_sftr_pack(char *payload,
1090 unsigned int flood_table,
1092 enum mlxsw_flood_table_type table_type,
1093 unsigned int range, u8 port, bool set)
1095 MLXSW_REG_ZERO(sftr, payload);
1096 mlxsw_reg_sftr_swid_set(payload, 0);
1097 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1098 mlxsw_reg_sftr_index_set(payload, index);
1099 mlxsw_reg_sftr_table_type_set(payload, table_type);
1100 mlxsw_reg_sftr_range_set(payload, range);
1101 mlxsw_reg_sftr_port_set(payload, port, set);
1102 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1105 /* SFDF - Switch Filtering DB Flush
1106 * --------------------------------
1107 * The switch filtering DB flush register is used to flush the FDB.
1108 * Note that FDB notifications are flushed as well.
1110 #define MLXSW_REG_SFDF_ID 0x2013
1111 #define MLXSW_REG_SFDF_LEN 0x14
1113 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1116 * Switch partition ID.
1119 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1121 enum mlxsw_reg_sfdf_flush_type {
1122 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1123 MLXSW_REG_SFDF_FLUSH_PER_FID,
1124 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1125 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1126 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1127 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1128 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1129 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1132 /* reg_sfdf_flush_type
1134 * 0 - All SWID dynamic entries are flushed.
1135 * 1 - All FID dynamic entries are flushed.
1136 * 2 - All dynamic entries pointing to port are flushed.
1137 * 3 - All FID dynamic entries pointing to port are flushed.
1138 * 4 - All dynamic entries pointing to LAG are flushed.
1139 * 5 - All FID dynamic entries pointing to LAG are flushed.
1140 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1142 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1146 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1148 /* reg_sfdf_flush_static
1150 * 0 - Flush only dynamic entries.
1151 * 1 - Flush both dynamic and static entries.
1154 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1156 static inline void mlxsw_reg_sfdf_pack(char *payload,
1157 enum mlxsw_reg_sfdf_flush_type type)
1159 MLXSW_REG_ZERO(sfdf, payload);
1160 mlxsw_reg_sfdf_flush_type_set(payload, type);
1161 mlxsw_reg_sfdf_flush_static_set(payload, true);
1168 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1170 /* reg_sfdf_system_port
1174 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1176 /* reg_sfdf_port_fid_system_port
1177 * Port to flush, pointed to by FID.
1180 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1186 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1188 /* reg_sfdf_lag_fid_lag_id
1189 * LAG ID to flush, pointed to by FID.
1192 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1194 /* SLDR - Switch LAG Descriptor Register
1195 * -----------------------------------------
1196 * The switch LAG descriptor register is populated by LAG descriptors.
1197 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1200 #define MLXSW_REG_SLDR_ID 0x2014
1201 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1203 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1205 enum mlxsw_reg_sldr_op {
1206 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1207 MLXSW_REG_SLDR_OP_LAG_CREATE,
1208 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1209 /* Ports that appear in the list have the Distributor enabled */
1210 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1211 /* Removes ports from the disributor list */
1212 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1219 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1222 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1225 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1227 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1229 MLXSW_REG_ZERO(sldr, payload);
1230 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1231 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1234 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1236 MLXSW_REG_ZERO(sldr, payload);
1237 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1238 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1241 /* reg_sldr_num_ports
1242 * The number of member ports of the LAG.
1243 * Reserved for Create / Destroy operations
1244 * For Add / Remove operations - indicates the number of ports in the list.
1247 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1249 /* reg_sldr_system_port
1253 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1255 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1258 MLXSW_REG_ZERO(sldr, payload);
1259 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1260 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1261 mlxsw_reg_sldr_num_ports_set(payload, 1);
1262 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1265 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1268 MLXSW_REG_ZERO(sldr, payload);
1269 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1270 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1271 mlxsw_reg_sldr_num_ports_set(payload, 1);
1272 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1275 /* SLCR - Switch LAG Configuration 2 Register
1276 * -------------------------------------------
1277 * The Switch LAG Configuration register is used for configuring the
1278 * LAG properties of the switch.
1280 #define MLXSW_REG_SLCR_ID 0x2015
1281 #define MLXSW_REG_SLCR_LEN 0x10
1283 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1285 enum mlxsw_reg_slcr_pp {
1286 /* Global Configuration (for all ports) */
1287 MLXSW_REG_SLCR_PP_GLOBAL,
1288 /* Per port configuration, based on local_port field */
1289 MLXSW_REG_SLCR_PP_PER_PORT,
1293 * Per Port Configuration
1294 * Note: Reading at Global mode results in reading port 1 configuration.
1297 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1299 /* reg_slcr_local_port
1301 * Supported from CPU port
1302 * Not supported from router port
1303 * Reserved when pp = Global Configuration
1306 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1308 enum mlxsw_reg_slcr_type {
1309 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1310 MLXSW_REG_SLCR_TYPE_XOR,
1311 MLXSW_REG_SLCR_TYPE_RANDOM,
1318 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1321 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1322 /* SMAC - for IPv4 and IPv6 packets */
1323 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1324 /* SMAC - for non-IP packets */
1325 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1326 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1327 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1328 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1329 /* DMAC - for IPv4 and IPv6 packets */
1330 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1331 /* DMAC - for non-IP packets */
1332 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1333 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1334 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1335 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1336 /* Ethertype - for IPv4 and IPv6 packets */
1337 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1338 /* Ethertype - for non-IP packets */
1339 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1340 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1341 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1342 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1343 /* VLAN ID - for IPv4 and IPv6 packets */
1344 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1345 /* VLAN ID - for non-IP packets */
1346 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1347 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1348 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1349 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1350 /* Source IP address (can be IPv4 or IPv6) */
1351 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1352 /* Destination IP address (can be IPv4 or IPv6) */
1353 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1354 /* TCP/UDP source port */
1355 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1356 /* TCP/UDP destination port*/
1357 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1358 /* IPv4 Protocol/IPv6 Next Header */
1359 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1360 /* IPv6 Flow label */
1361 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1362 /* SID - FCoE source ID */
1363 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1364 /* DID - FCoE destination ID */
1365 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1366 /* OXID - FCoE originator exchange ID */
1367 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1368 /* Destination QP number - for RoCE packets */
1369 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1371 /* reg_slcr_lag_hash
1372 * LAG hashing configuration. This is a bitmask, in which each set
1373 * bit includes the corresponding item in the LAG hash calculation.
1374 * The default lag_hash contains SMAC, DMAC, VLANID and
1375 * Ethertype (for all packet types).
1378 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1381 * LAG seed value. The seed is the same for all ports.
1384 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1386 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1388 MLXSW_REG_ZERO(slcr, payload);
1389 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1390 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1391 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1392 mlxsw_reg_slcr_seed_set(payload, seed);
1395 /* SLCOR - Switch LAG Collector Register
1396 * -------------------------------------
1397 * The Switch LAG Collector register controls the Local Port membership
1398 * in a LAG and enablement of the collector.
1400 #define MLXSW_REG_SLCOR_ID 0x2016
1401 #define MLXSW_REG_SLCOR_LEN 0x10
1403 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1405 enum mlxsw_reg_slcor_col {
1406 /* Port is added with collector disabled */
1407 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1408 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1409 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1410 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1414 * Collector configuration
1417 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1419 /* reg_slcor_local_port
1421 * Not supported for CPU port
1424 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1427 * LAG Identifier. Index into the LAG descriptor table.
1430 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1432 /* reg_slcor_port_index
1433 * Port index in the LAG list. Only valid on Add Port to LAG col.
1434 * Valid range is from 0 to cap_max_lag_members-1
1437 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1439 static inline void mlxsw_reg_slcor_pack(char *payload,
1440 u8 local_port, u16 lag_id,
1441 enum mlxsw_reg_slcor_col col)
1443 MLXSW_REG_ZERO(slcor, payload);
1444 mlxsw_reg_slcor_col_set(payload, col);
1445 mlxsw_reg_slcor_local_port_set(payload, local_port);
1446 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1449 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1450 u8 local_port, u16 lag_id,
1453 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1454 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1455 mlxsw_reg_slcor_port_index_set(payload, port_index);
1458 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1459 u8 local_port, u16 lag_id)
1461 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1462 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1465 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1466 u8 local_port, u16 lag_id)
1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1472 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1473 u8 local_port, u16 lag_id)
1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1479 /* SPMLR - Switch Port MAC Learning Register
1480 * -----------------------------------------
1481 * Controls the Switch MAC learning policy per port.
1483 #define MLXSW_REG_SPMLR_ID 0x2018
1484 #define MLXSW_REG_SPMLR_LEN 0x8
1486 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1488 /* reg_spmlr_local_port
1489 * Local port number.
1492 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1494 /* reg_spmlr_sub_port
1495 * Virtual port within the physical port.
1496 * Should be set to 0 when virtual ports are not enabled on the port.
1499 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1501 enum mlxsw_reg_spmlr_learn_mode {
1502 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1503 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1504 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1507 /* reg_spmlr_learn_mode
1508 * Learning mode on the port.
1509 * 0 - Learning disabled.
1510 * 2 - Learning enabled.
1511 * 3 - Security mode.
1513 * In security mode the switch does not learn MACs on the port, but uses the
1514 * SMAC to see if it exists on another ingress port. If so, the packet is
1515 * classified as a bad packet and is discarded unless the software registers
1516 * to receive port security error packets usign HPKT.
1518 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1520 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1521 enum mlxsw_reg_spmlr_learn_mode mode)
1523 MLXSW_REG_ZERO(spmlr, payload);
1524 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1525 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1526 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1529 /* SVFA - Switch VID to FID Allocation Register
1530 * --------------------------------------------
1531 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1532 * virtualized ports.
1534 #define MLXSW_REG_SVFA_ID 0x201C
1535 #define MLXSW_REG_SVFA_LEN 0x10
1537 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1540 * Switch partition ID.
1543 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1545 /* reg_svfa_local_port
1546 * Local port number.
1549 * Note: Reserved for 802.1Q FIDs.
1551 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1553 enum mlxsw_reg_svfa_mt {
1554 MLXSW_REG_SVFA_MT_VID_TO_FID,
1555 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1558 /* reg_svfa_mapping_table
1561 * 1 - {Port, VID} to FID
1564 * Note: Reserved for SwitchX-2.
1566 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1573 * Note: Reserved for SwitchX-2.
1575 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1581 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1587 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1589 /* reg_svfa_counter_set_type
1590 * Counter set type for flow counters.
1593 * Note: Reserved for SwitchX-2.
1595 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1597 /* reg_svfa_counter_index
1598 * Counter index for flow counters.
1601 * Note: Reserved for SwitchX-2.
1603 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1605 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1606 enum mlxsw_reg_svfa_mt mt, bool valid,
1609 MLXSW_REG_ZERO(svfa, payload);
1610 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1611 mlxsw_reg_svfa_swid_set(payload, 0);
1612 mlxsw_reg_svfa_local_port_set(payload, local_port);
1613 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1614 mlxsw_reg_svfa_v_set(payload, valid);
1615 mlxsw_reg_svfa_fid_set(payload, fid);
1616 mlxsw_reg_svfa_vid_set(payload, vid);
1619 /* SVPE - Switch Virtual-Port Enabling Register
1620 * --------------------------------------------
1621 * Enables port virtualization.
1623 #define MLXSW_REG_SVPE_ID 0x201E
1624 #define MLXSW_REG_SVPE_LEN 0x4
1626 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1628 /* reg_svpe_local_port
1632 * Note: CPU port is not supported (uses VLAN mode only).
1634 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1637 * Virtual port enable.
1638 * 0 - Disable, VLAN mode (VID to FID).
1639 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1642 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1644 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1647 MLXSW_REG_ZERO(svpe, payload);
1648 mlxsw_reg_svpe_local_port_set(payload, local_port);
1649 mlxsw_reg_svpe_vp_en_set(payload, enable);
1652 /* SFMR - Switch FID Management Register
1653 * -------------------------------------
1654 * Creates and configures FIDs.
1656 #define MLXSW_REG_SFMR_ID 0x201F
1657 #define MLXSW_REG_SFMR_LEN 0x18
1659 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1661 enum mlxsw_reg_sfmr_op {
1662 MLXSW_REG_SFMR_OP_CREATE_FID,
1663 MLXSW_REG_SFMR_OP_DESTROY_FID,
1668 * 0 - Create or edit FID.
1672 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1678 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1680 /* reg_sfmr_fid_offset
1682 * Used to point into the flooding table selected by SFGC register if
1683 * the table is of type FID-Offset. Otherwise, this field is reserved.
1686 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1689 * Valid Tunnel Flood Pointer.
1690 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1693 * Note: Reserved for 802.1Q FIDs.
1695 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1697 /* reg_sfmr_nve_tunnel_flood_ptr
1698 * Underlay Flooding and BC Pointer.
1699 * Used as a pointer to the first entry of the group based link lists of
1700 * flooding or BC entries (for NVE tunnels).
1703 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1707 * If not set, then vni is reserved.
1710 * Note: Reserved for 802.1Q FIDs.
1712 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1715 * Virtual Network Identifier.
1718 * Note: A given VNI can only be assigned to one FID.
1720 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1722 static inline void mlxsw_reg_sfmr_pack(char *payload,
1723 enum mlxsw_reg_sfmr_op op, u16 fid,
1726 MLXSW_REG_ZERO(sfmr, payload);
1727 mlxsw_reg_sfmr_op_set(payload, op);
1728 mlxsw_reg_sfmr_fid_set(payload, fid);
1729 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1730 mlxsw_reg_sfmr_vtfp_set(payload, false);
1731 mlxsw_reg_sfmr_vv_set(payload, false);
1734 /* SPVMLR - Switch Port VLAN MAC Learning Register
1735 * -----------------------------------------------
1736 * Controls the switch MAC learning policy per {Port, VID}.
1738 #define MLXSW_REG_SPVMLR_ID 0x2020
1739 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1740 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1741 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1742 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1743 MLXSW_REG_SPVMLR_REC_LEN * \
1744 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1746 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1748 /* reg_spvmlr_local_port
1749 * Local ingress port.
1752 * Note: CPU port is not supported.
1754 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1756 /* reg_spvmlr_num_rec
1757 * Number of records to update.
1760 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1762 /* reg_spvmlr_rec_learn_enable
1763 * 0 - Disable learning for {Port, VID}.
1764 * 1 - Enable learning for {Port, VID}.
1767 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1768 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1770 /* reg_spvmlr_rec_vid
1771 * VLAN ID to be added/removed from port or for querying.
1774 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1775 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1777 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1778 u16 vid_begin, u16 vid_end,
1781 int num_rec = vid_end - vid_begin + 1;
1784 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1786 MLXSW_REG_ZERO(spvmlr, payload);
1787 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1788 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1790 for (i = 0; i < num_rec; i++) {
1791 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1792 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1796 /* CWTP - Congetion WRED ECN TClass Profile
1797 * ----------------------------------------
1798 * Configures the profiles for queues of egress port and traffic class
1800 #define MLXSW_REG_CWTP_ID 0x2802
1801 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1802 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1803 #define MLXSW_REG_CWTP_LEN 0x40
1805 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1807 /* reg_cwtp_local_port
1809 * Not supported for CPU port
1812 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1814 /* reg_cwtp_traffic_class
1815 * Traffic Class to configure
1818 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1820 /* reg_cwtp_profile_min
1821 * Minimum Average Queue Size of the profile in cells.
1824 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1825 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1827 /* reg_cwtp_profile_percent
1828 * Percentage of WRED and ECN marking for maximum Average Queue size
1829 * Range is 0 to 100, units of integer percentage
1832 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1833 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1835 /* reg_cwtp_profile_max
1836 * Maximum Average Queue size of the profile in cells
1839 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1840 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1842 #define MLXSW_REG_CWTP_MIN_VALUE 64
1843 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1844 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1846 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1851 MLXSW_REG_ZERO(cwtp, payload);
1852 mlxsw_reg_cwtp_local_port_set(payload, local_port);
1853 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1855 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1856 mlxsw_reg_cwtp_profile_min_set(payload, i,
1857 MLXSW_REG_CWTP_MIN_VALUE);
1858 mlxsw_reg_cwtp_profile_max_set(payload, i,
1859 MLXSW_REG_CWTP_MIN_VALUE);
1863 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1866 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1869 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1871 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1872 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1873 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1876 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1877 * ---------------------------------------------------
1878 * The CWTPM register maps each egress port and traffic class to profile num.
1880 #define MLXSW_REG_CWTPM_ID 0x2803
1881 #define MLXSW_REG_CWTPM_LEN 0x44
1883 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1885 /* reg_cwtpm_local_port
1887 * Not supported for CPU port
1890 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1892 /* reg_cwtpm_traffic_class
1893 * Traffic Class to configure
1896 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1899 * Control enablement of WRED for traffic class:
1904 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1907 * Control enablement of ECN for traffic class:
1912 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1915 * TCP Green Profile.
1916 * Index of the profile within {port, traffic class} to use.
1917 * 0 for disabling both WRED and ECN for this type of traffic.
1920 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1923 * TCP Yellow Profile.
1924 * Index of the profile within {port, traffic class} to use.
1925 * 0 for disabling both WRED and ECN for this type of traffic.
1928 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1932 * Index of the profile within {port, traffic class} to use.
1933 * 0 for disabling both WRED and ECN for this type of traffic.
1936 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
1939 * Non-TCP Green Profile.
1940 * Index of the profile within {port, traffic class} to use.
1941 * 0 for disabling both WRED and ECN for this type of traffic.
1944 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
1947 * Non-TCP Yellow Profile.
1948 * Index of the profile within {port, traffic class} to use.
1949 * 0 for disabling both WRED and ECN for this type of traffic.
1952 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
1955 * Non-TCP Red Profile.
1956 * Index of the profile within {port, traffic class} to use.
1957 * 0 for disabling both WRED and ECN for this type of traffic.
1960 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
1962 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
1964 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
1965 u8 traffic_class, u8 profile,
1966 bool wred, bool ecn)
1968 MLXSW_REG_ZERO(cwtpm, payload);
1969 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
1970 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
1971 mlxsw_reg_cwtpm_ew_set(payload, wred);
1972 mlxsw_reg_cwtpm_ee_set(payload, ecn);
1973 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
1974 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
1975 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
1976 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
1977 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
1978 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
1981 /* PGCR - Policy-Engine General Configuration Register
1982 * ---------------------------------------------------
1983 * This register configures general Policy-Engine settings.
1985 #define MLXSW_REG_PGCR_ID 0x3001
1986 #define MLXSW_REG_PGCR_LEN 0x20
1988 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
1990 /* reg_pgcr_default_action_pointer_base
1991 * Default action pointer base. Each region has a default action pointer
1992 * which is equal to default_action_pointer_base + region_id.
1995 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
1997 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
1999 MLXSW_REG_ZERO(pgcr, payload);
2000 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2003 /* PPBT - Policy-Engine Port Binding Table
2004 * ---------------------------------------
2005 * This register is used for configuration of the Port Binding Table.
2007 #define MLXSW_REG_PPBT_ID 0x3002
2008 #define MLXSW_REG_PPBT_LEN 0x14
2010 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2012 enum mlxsw_reg_pxbt_e {
2013 MLXSW_REG_PXBT_E_IACL,
2014 MLXSW_REG_PXBT_E_EACL,
2020 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2022 enum mlxsw_reg_pxbt_op {
2023 MLXSW_REG_PXBT_OP_BIND,
2024 MLXSW_REG_PXBT_OP_UNBIND,
2030 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2032 /* reg_ppbt_local_port
2033 * Local port. Not including CPU port.
2036 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2039 * group - When set, the binding is of an ACL group. When cleared,
2040 * the binding is of an ACL.
2041 * Must be set to 1 for Spectrum.
2044 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2046 /* reg_ppbt_acl_info
2047 * ACL/ACL group identifier. If the g bit is set, this field should hold
2048 * the acl_group_id, else it should hold the acl_id.
2051 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2053 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2054 enum mlxsw_reg_pxbt_op op,
2055 u8 local_port, u16 acl_info)
2057 MLXSW_REG_ZERO(ppbt, payload);
2058 mlxsw_reg_ppbt_e_set(payload, e);
2059 mlxsw_reg_ppbt_op_set(payload, op);
2060 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2061 mlxsw_reg_ppbt_g_set(payload, true);
2062 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2065 /* PACL - Policy-Engine ACL Register
2066 * ---------------------------------
2067 * This register is used for configuration of the ACL.
2069 #define MLXSW_REG_PACL_ID 0x3004
2070 #define MLXSW_REG_PACL_LEN 0x70
2072 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2075 * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2076 * while the ACL is bounded to either a port, VLAN or ACL rule.
2079 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2082 * An identifier representing the ACL (managed by software)
2083 * Range 0 .. cap_max_acl_regions - 1
2086 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2088 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2090 /* reg_pacl_tcam_region_info
2091 * Opaque object that represents a TCAM region.
2092 * Obtained through PTAR register.
2095 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2096 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2098 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2099 bool valid, const char *tcam_region_info)
2101 MLXSW_REG_ZERO(pacl, payload);
2102 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2103 mlxsw_reg_pacl_v_set(payload, valid);
2104 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2107 /* PAGT - Policy-Engine ACL Group Table
2108 * ------------------------------------
2109 * This register is used for configuration of the ACL Group Table.
2111 #define MLXSW_REG_PAGT_ID 0x3005
2112 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2113 #define MLXSW_REG_PAGT_ACL_LEN 4
2114 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2115 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2116 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2118 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2121 * Number of ACLs in the group.
2122 * Size 0 invalidates a group.
2123 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2124 * Total number of ACLs in all groups must be lower or equal
2125 * to cap_max_acl_tot_groups
2126 * Note: a group which is binded must not be invalidated
2129 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2131 /* reg_pagt_acl_group_id
2132 * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2133 * the ACL Group identifier (managed by software).
2136 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2142 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2144 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2146 MLXSW_REG_ZERO(pagt, payload);
2147 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2150 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2153 u8 size = mlxsw_reg_pagt_size_get(payload);
2156 mlxsw_reg_pagt_size_set(payload, index + 1);
2157 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2160 /* PTAR - Policy-Engine TCAM Allocation Register
2161 * ---------------------------------------------
2162 * This register is used for allocation of regions in the TCAM.
2163 * Note: Query method is not supported on this register.
2165 #define MLXSW_REG_PTAR_ID 0x3006
2166 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2167 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2168 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2169 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2170 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2172 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2174 enum mlxsw_reg_ptar_op {
2175 /* allocate a TCAM region */
2176 MLXSW_REG_PTAR_OP_ALLOC,
2177 /* resize a TCAM region */
2178 MLXSW_REG_PTAR_OP_RESIZE,
2179 /* deallocate TCAM region */
2180 MLXSW_REG_PTAR_OP_FREE,
2181 /* test allocation */
2182 MLXSW_REG_PTAR_OP_TEST,
2188 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2190 /* reg_ptar_action_set_type
2191 * Type of action set to be used on this region.
2192 * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2195 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2197 enum mlxsw_reg_ptar_key_type {
2198 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2199 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2202 /* reg_ptar_key_type
2203 * TCAM key type for the region.
2206 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2208 /* reg_ptar_region_size
2209 * TCAM region size. When allocating/resizing this is the requested size,
2210 * the response is the actual size. Note that actual size may be
2211 * larger than requested.
2212 * Allowed range 1 .. cap_max_rules-1
2213 * Reserved during op deallocate.
2216 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2218 /* reg_ptar_region_id
2220 * Range 0 .. cap_max_regions-1
2223 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2225 /* reg_ptar_tcam_region_info
2226 * Opaque object that represents the TCAM region.
2227 * Returned when allocating a region.
2228 * Provided by software for ACL generation and region deallocation and resize.
2231 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2232 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2234 /* reg_ptar_flexible_key_id
2235 * Identifier of the Flexible Key.
2236 * Only valid if key_type == "FLEX_KEY"
2237 * The key size will be rounded up to one of the following values:
2238 * 9B, 18B, 36B, 54B.
2239 * This field is reserved for in resize operation.
2242 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2243 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2245 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2246 enum mlxsw_reg_ptar_key_type key_type,
2247 u16 region_size, u16 region_id,
2248 const char *tcam_region_info)
2250 MLXSW_REG_ZERO(ptar, payload);
2251 mlxsw_reg_ptar_op_set(payload, op);
2252 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2253 mlxsw_reg_ptar_key_type_set(payload, key_type);
2254 mlxsw_reg_ptar_region_size_set(payload, region_size);
2255 mlxsw_reg_ptar_region_id_set(payload, region_id);
2256 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2259 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2262 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2265 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2267 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2270 /* PPBS - Policy-Engine Policy Based Switching Register
2271 * ----------------------------------------------------
2272 * This register retrieves and sets Policy Based Switching Table entries.
2274 #define MLXSW_REG_PPBS_ID 0x300C
2275 #define MLXSW_REG_PPBS_LEN 0x14
2277 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2280 * Index into the PBS table.
2281 * For Spectrum, the index points to the KVD Linear.
2284 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2286 /* reg_ppbs_system_port
2287 * Unique port identifier for the final destination of the packet.
2290 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2292 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2295 MLXSW_REG_ZERO(ppbs, payload);
2296 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2297 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2300 /* PRCR - Policy-Engine Rules Copy Register
2301 * ----------------------------------------
2302 * This register is used for accessing rules within a TCAM region.
2304 #define MLXSW_REG_PRCR_ID 0x300D
2305 #define MLXSW_REG_PRCR_LEN 0x40
2307 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2309 enum mlxsw_reg_prcr_op {
2310 /* Move rules. Moves the rules from "tcam_region_info" starting
2311 * at offset "offset" to "dest_tcam_region_info"
2312 * at offset "dest_offset."
2314 MLXSW_REG_PRCR_OP_MOVE,
2315 /* Copy rules. Copies the rules from "tcam_region_info" starting
2316 * at offset "offset" to "dest_tcam_region_info"
2317 * at offset "dest_offset."
2319 MLXSW_REG_PRCR_OP_COPY,
2325 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2328 * Offset within the source region to copy/move from.
2331 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2334 * The number of rules to copy/move.
2337 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2339 /* reg_prcr_tcam_region_info
2340 * Opaque object that represents the source TCAM region.
2343 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2344 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2346 /* reg_prcr_dest_offset
2347 * Offset within the source region to copy/move to.
2350 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2352 /* reg_prcr_dest_tcam_region_info
2353 * Opaque object that represents the destination TCAM region.
2356 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2357 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2359 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2360 const char *src_tcam_region_info,
2362 const char *dest_tcam_region_info,
2363 u16 dest_offset, u16 size)
2365 MLXSW_REG_ZERO(prcr, payload);
2366 mlxsw_reg_prcr_op_set(payload, op);
2367 mlxsw_reg_prcr_offset_set(payload, src_offset);
2368 mlxsw_reg_prcr_size_set(payload, size);
2369 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2370 src_tcam_region_info);
2371 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2372 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2373 dest_tcam_region_info);
2376 /* PEFA - Policy-Engine Extended Flexible Action Register
2377 * ------------------------------------------------------
2378 * This register is used for accessing an extended flexible action entry
2379 * in the central KVD Linear Database.
2381 #define MLXSW_REG_PEFA_ID 0x300F
2382 #define MLXSW_REG_PEFA_LEN 0xB0
2384 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2387 * Index in the KVD Linear Centralized Database.
2390 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2393 * Index in the KVD Linear Centralized Database.
2395 * For a new entry: set if ca=0, clear if ca=1
2396 * Set if a packet lookup has hit on the specific entry
2399 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2403 * When write: activity is according to this field
2404 * When read: after reading the activity is cleared according to ca
2407 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2409 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2411 /* reg_pefa_flex_action_set
2412 * Action-set to perform when rule is matched.
2413 * Must be zero padded if action set is shorter.
2416 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2418 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2419 const char *flex_action_set)
2421 MLXSW_REG_ZERO(pefa, payload);
2422 mlxsw_reg_pefa_index_set(payload, index);
2423 mlxsw_reg_pefa_ca_set(payload, ca);
2424 if (flex_action_set)
2425 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2429 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2431 *p_a = mlxsw_reg_pefa_a_get(payload);
2434 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2435 * -----------------------------------------------------
2436 * This register is used for accessing rules within a TCAM region.
2437 * It is a new version of PTCE in order to support wider key,
2438 * mask and action within a TCAM region. This register is not supported
2439 * by SwitchX and SwitchX-2.
2441 #define MLXSW_REG_PTCE2_ID 0x3017
2442 #define MLXSW_REG_PTCE2_LEN 0x1D8
2444 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2450 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2453 * Activity. Set if a packet lookup has hit on the specific entry.
2454 * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2457 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2459 enum mlxsw_reg_ptce2_op {
2460 /* Read operation. */
2461 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2462 /* clear on read operation. Used to read entry
2463 * and clear Activity bit.
2465 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2466 /* Write operation. Used to write a new entry to the table.
2467 * All R/W fields are relevant for new entry. Activity bit is set
2468 * for new entries - Note write with v = 0 will delete the entry.
2470 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2471 /* Update action. Only action set will be updated. */
2472 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2473 /* Clear activity. A bit is cleared for the entry. */
2474 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2480 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2485 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2487 /* reg_ptce2_priority
2488 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2489 * Note: priority does not have to be unique per rule.
2490 * Within a region, higher priority should have lower offset (no limitation
2491 * between regions in a multi-region).
2494 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2496 /* reg_ptce2_tcam_region_info
2497 * Opaque object that represents the TCAM region.
2500 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2501 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2503 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2505 /* reg_ptce2_flex_key_blocks
2509 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2510 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2513 * mask- in the same size as key. A bit that is set directs the TCAM
2514 * to compare the corresponding bit in key. A bit that is clear directs
2515 * the TCAM to ignore the corresponding bit in key.
2518 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2519 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2521 /* reg_ptce2_flex_action_set
2525 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2526 MLXSW_REG_FLEX_ACTION_SET_LEN);
2528 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2529 enum mlxsw_reg_ptce2_op op,
2530 const char *tcam_region_info,
2531 u16 offset, u32 priority)
2533 MLXSW_REG_ZERO(ptce2, payload);
2534 mlxsw_reg_ptce2_v_set(payload, valid);
2535 mlxsw_reg_ptce2_op_set(payload, op);
2536 mlxsw_reg_ptce2_offset_set(payload, offset);
2537 mlxsw_reg_ptce2_priority_set(payload, priority);
2538 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2541 /* PERPT - Policy-Engine ERP Table Register
2542 * ----------------------------------------
2543 * This register adds and removes eRPs from the eRP table.
2545 #define MLXSW_REG_PERPT_ID 0x3021
2546 #define MLXSW_REG_PERPT_LEN 0x80
2548 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2550 /* reg_perpt_erpt_bank
2552 * Range 0 .. cap_max_erp_table_banks - 1
2555 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2557 /* reg_perpt_erpt_index
2558 * Index to eRP table within the eRP bank.
2559 * Range is 0 .. cap_max_erp_table_bank_size - 1
2562 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2564 enum mlxsw_reg_perpt_key_size {
2565 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2566 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2567 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2568 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2571 /* reg_perpt_key_size
2574 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2576 /* reg_perpt_bf_bypass
2577 * 0 - The eRP is used only if bloom filter state is set for the given
2579 * 1 - The eRP is used regardless of bloom filter state.
2580 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2583 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2586 * eRP ID for use by the rules.
2589 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2591 /* reg_perpt_erpt_base_bank
2592 * Base eRP table bank, points to head of erp_vector
2593 * Range is 0 .. cap_max_erp_table_banks - 1
2596 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2598 /* reg_perpt_erpt_base_index
2599 * Base index to eRP table within the eRP bank
2600 * Range is 0 .. cap_max_erp_table_bank_size - 1
2603 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2605 /* reg_perpt_erp_index_in_vector
2606 * eRP index in the vector.
2609 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2611 /* reg_perpt_erp_vector
2615 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2619 * 0 - A-TCAM will ignore the bit in key
2620 * 1 - A-TCAM will compare the bit in key
2623 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2625 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2626 unsigned long *erp_vector,
2631 for_each_set_bit(bit, erp_vector, size)
2632 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2636 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2637 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2638 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2641 MLXSW_REG_ZERO(perpt, payload);
2642 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2643 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2644 mlxsw_reg_perpt_key_size_set(payload, key_size);
2645 mlxsw_reg_perpt_bf_bypass_set(payload, true);
2646 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2647 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2648 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2649 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2650 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2653 /* PERAR - Policy-Engine Region Association Register
2654 * -------------------------------------------------
2655 * This register associates a hw region for region_id's. Changing on the fly
2656 * is supported by the device.
2658 #define MLXSW_REG_PERAR_ID 0x3026
2659 #define MLXSW_REG_PERAR_LEN 0x08
2661 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2663 /* reg_perar_region_id
2665 * Range 0 .. cap_max_regions-1
2668 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2670 static inline unsigned int
2671 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2673 return DIV_ROUND_UP(block_num, 4);
2676 /* reg_perar_hw_region
2678 * Range 0 .. cap_max_regions-1
2679 * Default: hw_region = region_id
2680 * For a 8 key block region, 2 consecutive regions are used
2681 * For a 12 key block region, 3 consecutive regions are used
2684 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2686 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2689 MLXSW_REG_ZERO(perar, payload);
2690 mlxsw_reg_perar_region_id_set(payload, region_id);
2691 mlxsw_reg_perar_hw_region_set(payload, hw_region);
2694 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2695 * -----------------------------------------------------
2696 * This register is a new version of PTCE-V2 in order to support the
2697 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2699 #define MLXSW_REG_PTCE3_ID 0x3027
2700 #define MLXSW_REG_PTCE3_LEN 0xF0
2702 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2708 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2710 enum mlxsw_reg_ptce3_op {
2711 /* Write operation. Used to write a new entry to the table.
2712 * All R/W fields are relevant for new entry. Activity bit is set
2713 * for new entries. Write with v = 0 will delete the entry. Must
2714 * not be used if an entry exists.
2716 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2717 /* Update operation */
2718 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2719 /* Read operation */
2720 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2726 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2728 /* reg_ptce3_priority
2729 * Priority of the rule. Higher values win.
2730 * For Spectrum-2 range is 1..cap_kvd_size - 1
2731 * Note: Priority does not have to be unique per rule.
2734 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2736 /* reg_ptce3_tcam_region_info
2737 * Opaque object that represents the TCAM region.
2740 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2741 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2743 /* reg_ptce3_flex2_key_blocks
2744 * ACL key. The key must be masked according to eRP (if exists) or
2745 * according to master mask.
2748 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2749 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2755 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2757 /* reg_ptce3_delta_start
2758 * Start point of delta_value and delta_mask, in bits. Must not exceed
2759 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2762 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2764 /* reg_ptce3_delta_mask
2766 * 0 - Ignore relevant bit in delta_value
2767 * 1 - Compare relevant bit in delta_value
2768 * Delta mask must not be set for reserved fields in the key blocks.
2769 * Note: No delta when no eRPs. Thus, for regions with
2770 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2773 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2775 /* reg_ptce3_delta_value
2777 * Bits which are masked by delta_mask must be 0.
2780 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2782 /* reg_ptce3_prune_vector
2783 * Pruning vector relative to the PERPT.erp_id.
2784 * Used for reducing lookups.
2785 * 0 - NEED: Do a lookup using the eRP.
2786 * 1 - PRUNE: Do not perform a lookup using the eRP.
2787 * Maybe be modified by PEAPBL and PEAPBM.
2788 * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2789 * all 1's or all 0's.
2792 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2794 /* reg_ptce3_prune_ctcam
2795 * Pruning on C-TCAM. Used for reducing lookups.
2796 * 0 - NEED: Do a lookup in the C-TCAM.
2797 * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2800 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2802 /* reg_ptce3_large_exists
2803 * Large entry key ID exists.
2804 * Within the region:
2805 * 0 - SINGLE: The large_entry_key_id is not currently in use.
2806 * For rule insert: The MSB of the key (blocks 6..11) will be added.
2807 * For rule delete: The MSB of the key will be removed.
2808 * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2809 * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2810 * For rule delete: The MSB of the key will not be removed.
2813 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2815 /* reg_ptce3_large_entry_key_id
2816 * Large entry key ID.
2817 * A key for 12 key blocks rules. Reserved when region has less than 12 key
2818 * blocks. Must be different for different keys which have the same common
2819 * 6 key blocks (MSB, blocks 6..11) key within a region.
2820 * Range is 0..cap_max_pe_large_key_id - 1
2823 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2825 /* reg_ptce3_action_pointer
2826 * Pointer to action.
2827 * Range is 0..cap_max_kvd_action_sets - 1
2830 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2832 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2833 enum mlxsw_reg_ptce3_op op,
2835 const char *tcam_region_info,
2836 const char *key, u8 erp_id,
2837 bool large_exists, u32 lkey_id,
2840 MLXSW_REG_ZERO(ptce3, payload);
2841 mlxsw_reg_ptce3_v_set(payload, valid);
2842 mlxsw_reg_ptce3_op_set(payload, op);
2843 mlxsw_reg_ptce3_priority_set(payload, priority);
2844 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2845 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2846 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2847 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2848 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2849 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2852 /* PERCR - Policy-Engine Region Configuration Register
2853 * ---------------------------------------------------
2854 * This register configures the region parameters. The region_id must be
2857 #define MLXSW_REG_PERCR_ID 0x302A
2858 #define MLXSW_REG_PERCR_LEN 0x80
2860 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2862 /* reg_percr_region_id
2863 * Region identifier.
2864 * Range 0..cap_max_regions-1
2867 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2869 /* reg_percr_atcam_ignore_prune
2870 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2873 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2875 /* reg_percr_ctcam_ignore_prune
2876 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2879 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2881 /* reg_percr_bf_bypass
2882 * Bloom filter bypass.
2883 * 0 - Bloom filter is used (default)
2884 * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2885 * region_id or eRP. See PERPT.bf_bypass
2888 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
2890 /* reg_percr_master_mask
2891 * Master mask. Logical OR mask of all masks of all rules of a region
2892 * (both A-TCAM and C-TCAM). When there are no eRPs
2893 * (erpt_pointer_valid = 0), then this provides the mask.
2896 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
2898 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
2900 MLXSW_REG_ZERO(percr, payload);
2901 mlxsw_reg_percr_region_id_set(payload, region_id);
2902 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
2903 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
2904 mlxsw_reg_percr_bf_bypass_set(payload, true);
2907 /* PERERP - Policy-Engine Region eRP Register
2908 * ------------------------------------------
2909 * This register configures the region eRP. The region_id must be
2912 #define MLXSW_REG_PERERP_ID 0x302B
2913 #define MLXSW_REG_PERERP_LEN 0x1C
2915 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
2917 /* reg_pererp_region_id
2918 * Region identifier.
2919 * Range 0..cap_max_regions-1
2922 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
2924 /* reg_pererp_ctcam_le
2925 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
2928 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
2930 /* reg_pererp_erpt_pointer_valid
2931 * erpt_pointer is valid.
2934 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
2936 /* reg_pererp_erpt_bank_pointer
2937 * Pointer to eRP table bank. May be modified at any time.
2938 * Range 0..cap_max_erp_table_banks-1
2939 * Reserved when erpt_pointer_valid = 0
2941 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
2943 /* reg_pererp_erpt_pointer
2944 * Pointer to eRP table within the eRP bank. Can be changed for an
2946 * Range 0..cap_max_erp_table_size-1
2947 * Reserved when erpt_pointer_valid = 0
2950 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
2952 /* reg_pererp_erpt_vector
2953 * Vector of allowed eRP indexes starting from erpt_pointer within the
2954 * erpt_bank_pointer. Next entries will be in next bank.
2955 * Note that eRP index is used and not eRP ID.
2956 * Reserved when erpt_pointer_valid = 0
2959 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
2961 /* reg_pererp_master_rp_id
2962 * Master RP ID. When there are no eRPs, then this provides the eRP ID
2963 * for the lookup. Can be changed for an existing region.
2964 * Reserved when erpt_pointer_valid = 1
2967 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
2969 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
2970 unsigned long *erp_vector,
2975 for_each_set_bit(bit, erp_vector, size)
2976 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
2979 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
2980 bool ctcam_le, bool erpt_pointer_valid,
2981 u8 erpt_bank_pointer, u8 erpt_pointer,
2984 MLXSW_REG_ZERO(pererp, payload);
2985 mlxsw_reg_pererp_region_id_set(payload, region_id);
2986 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
2987 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
2988 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
2989 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
2990 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
2993 /* IEDR - Infrastructure Entry Delete Register
2994 * ----------------------------------------------------
2995 * This register is used for deleting entries from the entry tables.
2996 * It is legitimate to attempt to delete a nonexisting entry (the device will
2997 * respond as a good flow).
2999 #define MLXSW_REG_IEDR_ID 0x3804
3000 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3001 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3002 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3003 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3004 MLXSW_REG_IEDR_REC_LEN * \
3005 MLXSW_REG_IEDR_REC_MAX_COUNT)
3007 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3010 * Number of records.
3013 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3015 /* reg_iedr_rec_type
3019 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3020 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3022 /* reg_iedr_rec_size
3023 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3026 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3027 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3029 /* reg_iedr_rec_index_start
3030 * Resource index start.
3033 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3034 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3036 static inline void mlxsw_reg_iedr_pack(char *payload)
3038 MLXSW_REG_ZERO(iedr, payload);
3041 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3042 u8 rec_type, u16 rec_size,
3043 u32 rec_index_start)
3045 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3047 if (rec_index >= num_rec)
3048 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3049 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3050 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3051 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3054 /* QPTS - QoS Priority Trust State Register
3055 * ----------------------------------------
3056 * This register controls the port policy to calculate the switch priority and
3057 * packet color based on incoming packet fields.
3059 #define MLXSW_REG_QPTS_ID 0x4002
3060 #define MLXSW_REG_QPTS_LEN 0x8
3062 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3064 /* reg_qpts_local_port
3065 * Local port number.
3068 * Note: CPU port is supported.
3070 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3072 enum mlxsw_reg_qpts_trust_state {
3073 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3074 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3077 /* reg_qpts_trust_state
3078 * Trust state for a given port.
3081 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3083 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3084 enum mlxsw_reg_qpts_trust_state ts)
3086 MLXSW_REG_ZERO(qpts, payload);
3088 mlxsw_reg_qpts_local_port_set(payload, local_port);
3089 mlxsw_reg_qpts_trust_state_set(payload, ts);
3092 /* QPCR - QoS Policer Configuration Register
3093 * -----------------------------------------
3094 * The QPCR register is used to create policers - that limit
3095 * the rate of bytes or packets via some trap group.
3097 #define MLXSW_REG_QPCR_ID 0x4004
3098 #define MLXSW_REG_QPCR_LEN 0x28
3100 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3102 enum mlxsw_reg_qpcr_g {
3103 MLXSW_REG_QPCR_G_GLOBAL = 2,
3104 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3111 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3117 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3119 /* reg_qpcr_color_aware
3120 * Is the policer aware of colors.
3121 * Must be 0 (unaware) for cpu port.
3122 * Access: RW for unbounded policer. RO for bounded policer.
3124 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3127 * Is policer limit is for bytes per sec or packets per sec.
3130 * Access: RW for unbounded policer. RO for bounded policer.
3132 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3134 enum mlxsw_reg_qpcr_ir_units {
3135 MLXSW_REG_QPCR_IR_UNITS_M,
3136 MLXSW_REG_QPCR_IR_UNITS_K,
3139 /* reg_qpcr_ir_units
3140 * Policer's units for cir and eir fields (for bytes limits only)
3145 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3147 enum mlxsw_reg_qpcr_rate_type {
3148 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3149 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3152 /* reg_qpcr_rate_type
3153 * Policer can have one limit (single rate) or 2 limits with specific operation
3154 * for packets that exceed the lower rate but not the upper one.
3155 * (For cpu port must be single rate)
3156 * Access: RW for unbounded policer. RO for bounded policer.
3158 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3161 * Policer's committed burst size.
3162 * The policer is working with time slices of 50 nano sec. By default every
3163 * slice is granted the proportionate share of the committed rate. If we want to
3164 * allow a slice to exceed that share (while still keeping the rate per sec) we
3165 * can allow burst. The burst size is between the default proportionate share
3166 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3167 * committed rate will result in exceeding the rate). The burst size must be a
3168 * log of 2 and will be determined by 2^cbs.
3171 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3174 * Policer's committed rate.
3175 * The rate used for sungle rate, the lower rate for double rate.
3176 * For bytes limits, the rate will be this value * the unit from ir_units.
3177 * (Resolution error is up to 1%).
3180 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3183 * Policer's exceed rate.
3184 * The higher rate for double rate, reserved for single rate.
3185 * Lower rate for double rate policer.
3186 * For bytes limits, the rate will be this value * the unit from ir_units.
3187 * (Resolution error is up to 1%).
3190 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3192 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3194 /* reg_qpcr_exceed_action.
3195 * What to do with packets between the 2 limits for double rate.
3196 * Access: RW for unbounded policer. RO for bounded policer.
3198 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3200 enum mlxsw_reg_qpcr_action {
3202 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3203 /* Forward and set color to red.
3204 * If the packet is intended to cpu port, it will be dropped.
3206 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3209 /* reg_qpcr_violate_action
3210 * What to do with packets that cross the cir limit (for single rate) or the eir
3211 * limit (for double rate).
3212 * Access: RW for unbounded policer. RO for bounded policer.
3214 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3216 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3217 enum mlxsw_reg_qpcr_ir_units ir_units,
3218 bool bytes, u32 cir, u16 cbs)
3220 MLXSW_REG_ZERO(qpcr, payload);
3221 mlxsw_reg_qpcr_pid_set(payload, pid);
3222 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3223 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3224 mlxsw_reg_qpcr_violate_action_set(payload,
3225 MLXSW_REG_QPCR_ACTION_DISCARD);
3226 mlxsw_reg_qpcr_cir_set(payload, cir);
3227 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3228 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3229 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3232 /* QTCT - QoS Switch Traffic Class Table
3233 * -------------------------------------
3234 * Configures the mapping between the packet switch priority and the
3235 * traffic class on the transmit port.
3237 #define MLXSW_REG_QTCT_ID 0x400A
3238 #define MLXSW_REG_QTCT_LEN 0x08
3240 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3242 /* reg_qtct_local_port
3243 * Local port number.
3246 * Note: CPU port is not supported.
3248 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3250 /* reg_qtct_sub_port
3251 * Virtual port within the physical port.
3252 * Should be set to 0 when virtual ports are not enabled on the port.
3255 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3257 /* reg_qtct_switch_prio
3261 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3266 * switch_prio 0 : tclass 1
3267 * switch_prio 1 : tclass 0
3268 * switch_prio i : tclass i, for i > 1
3271 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3273 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3274 u8 switch_prio, u8 tclass)
3276 MLXSW_REG_ZERO(qtct, payload);
3277 mlxsw_reg_qtct_local_port_set(payload, local_port);
3278 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3279 mlxsw_reg_qtct_tclass_set(payload, tclass);
3282 /* QEEC - QoS ETS Element Configuration Register
3283 * ---------------------------------------------
3284 * Configures the ETS elements.
3286 #define MLXSW_REG_QEEC_ID 0x400D
3287 #define MLXSW_REG_QEEC_LEN 0x1C
3289 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3291 /* reg_qeec_local_port
3292 * Local port number.
3295 * Note: CPU port is supported.
3297 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3299 enum mlxsw_reg_qeec_hr {
3300 MLXSW_REG_QEEC_HIERARCY_PORT,
3301 MLXSW_REG_QEEC_HIERARCY_GROUP,
3302 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3303 MLXSW_REG_QEEC_HIERARCY_TC,
3306 /* reg_qeec_element_hierarchy
3313 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3315 /* reg_qeec_element_index
3316 * The index of the element in the hierarchy.
3319 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3321 /* reg_qeec_next_element_index
3322 * The index of the next (lower) element in the hierarchy.
3325 * Note: Reserved for element_hierarchy 0.
3327 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3330 MLXSW_REG_QEEC_BYTES_MODE,
3331 MLXSW_REG_QEEC_PACKETS_MODE,
3335 * Packets or bytes mode.
3340 * Note: Used for max shaper configuration. For Spectrum, packets mode
3341 * is supported only for traffic classes of CPU port.
3343 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3346 * Max shaper configuration enable. Enables configuration of the max
3347 * shaper on this ETS element.
3352 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3354 /* A large max rate will disable the max shaper. */
3355 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
3357 /* reg_qeec_max_shaper_rate
3358 * Max shaper information rate.
3359 * For CPU port, can only be configured for port hierarchy.
3360 * When in bytes mode, value is specified in units of 1000bps.
3363 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3366 * DWRR configuration enable. Enables configuration of the dwrr and
3372 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3375 * Transmission selection algorithm to use on the link going down from
3377 * 0 - Strict priority
3381 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3383 /* reg_qeec_dwrr_weight
3384 * DWRR weight on the link going down from the ETS element. The
3385 * percentage of bandwidth guaranteed to an ETS element within
3386 * its hierarchy. The sum of all weights across all ETS elements
3387 * within one hierarchy should be equal to 100. Reserved when
3388 * transmission selection algorithm is strict priority.
3391 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3393 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3394 enum mlxsw_reg_qeec_hr hr, u8 index,
3397 MLXSW_REG_ZERO(qeec, payload);
3398 mlxsw_reg_qeec_local_port_set(payload, local_port);
3399 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3400 mlxsw_reg_qeec_element_index_set(payload, index);
3401 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3404 /* QRWE - QoS ReWrite Enable
3405 * -------------------------
3406 * This register configures the rewrite enable per receive port.
3408 #define MLXSW_REG_QRWE_ID 0x400F
3409 #define MLXSW_REG_QRWE_LEN 0x08
3411 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3413 /* reg_qrwe_local_port
3414 * Local port number.
3417 * Note: CPU port is supported. No support for router port.
3419 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3422 * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3425 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3428 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3431 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3433 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3434 bool rewrite_pcp, bool rewrite_dscp)
3436 MLXSW_REG_ZERO(qrwe, payload);
3437 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3438 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3439 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3442 /* QPDSM - QoS Priority to DSCP Mapping
3443 * ------------------------------------
3444 * QoS Priority to DSCP Mapping Register
3446 #define MLXSW_REG_QPDSM_ID 0x4011
3447 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3448 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3449 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3450 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3451 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3452 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3454 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3456 /* reg_qpdsm_local_port
3457 * Local Port. Supported for data packets from CPU port.
3460 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3462 /* reg_qpdsm_prio_entry_color0_e
3463 * Enable update of the entry for color 0 and a given port.
3466 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3467 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3468 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3470 /* reg_qpdsm_prio_entry_color0_dscp
3471 * DSCP field in the outer label of the packet for color 0 and a given port.
3472 * Reserved when e=0.
3475 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3476 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3477 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3479 /* reg_qpdsm_prio_entry_color1_e
3480 * Enable update of the entry for color 1 and a given port.
3483 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3484 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3485 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3487 /* reg_qpdsm_prio_entry_color1_dscp
3488 * DSCP field in the outer label of the packet for color 1 and a given port.
3489 * Reserved when e=0.
3492 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3493 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3494 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3496 /* reg_qpdsm_prio_entry_color2_e
3497 * Enable update of the entry for color 2 and a given port.
3500 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3501 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3502 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3504 /* reg_qpdsm_prio_entry_color2_dscp
3505 * DSCP field in the outer label of the packet for color 2 and a given port.
3506 * Reserved when e=0.
3509 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3510 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3511 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3513 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3515 MLXSW_REG_ZERO(qpdsm, payload);
3516 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3520 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3522 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3523 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3524 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3525 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3526 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3527 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3530 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3531 * --------------------------------------------------
3532 * This register controls the mapping from DSCP field to
3533 * Switch Priority for IP packets.
3535 #define MLXSW_REG_QPDPM_ID 0x4013
3536 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3537 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3538 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3539 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
3540 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
3541 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3543 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3545 /* reg_qpdpm_local_port
3546 * Local Port. Supported for data packets from CPU port.
3549 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3552 * Enable update of the specific entry. When cleared, the switch_prio and color
3553 * fields are ignored and the previous switch_prio and color values are
3557 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3558 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3560 /* reg_qpdpm_dscp_prio
3561 * The new Switch Priority value for the relevant DSCP value.
3564 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3565 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3566 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3568 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3570 MLXSW_REG_ZERO(qpdpm, payload);
3571 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3575 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3577 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3578 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3581 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3582 * ------------------------------------------------------------------
3583 * This register configures if the Switch Priority to Traffic Class mapping is
3584 * based on Multicast packet indication. If so, then multicast packets will get
3585 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3587 * By default, Switch Priority to Traffic Class mapping is not based on
3588 * Multicast packet indication.
3590 #define MLXSW_REG_QTCTM_ID 0x401A
3591 #define MLXSW_REG_QTCTM_LEN 0x08
3593 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3595 /* reg_qtctm_local_port
3596 * Local port number.
3597 * No support for CPU port.
3600 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3604 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3605 * indication (default is 0, not based on Multicast packet indication).
3607 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3610 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3612 MLXSW_REG_ZERO(qtctm, payload);
3613 mlxsw_reg_qtctm_local_port_set(payload, local_port);
3614 mlxsw_reg_qtctm_mc_set(payload, mc);
3617 /* PMLP - Ports Module to Local Port Register
3618 * ------------------------------------------
3619 * Configures the assignment of modules to local ports.
3621 #define MLXSW_REG_PMLP_ID 0x5002
3622 #define MLXSW_REG_PMLP_LEN 0x40
3624 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3627 * 0 - Tx value is used for both Tx and Rx.
3628 * 1 - Rx value is taken from a separte field.
3631 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3633 /* reg_pmlp_local_port
3634 * Local port number.
3637 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3640 * 0 - Unmap local port.
3641 * 1 - Lane 0 is used.
3642 * 2 - Lanes 0 and 1 are used.
3643 * 4 - Lanes 0, 1, 2 and 3 are used.
3646 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3652 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3655 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3658 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3661 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3665 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3667 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3669 MLXSW_REG_ZERO(pmlp, payload);
3670 mlxsw_reg_pmlp_local_port_set(payload, local_port);
3673 /* PMTU - Port MTU Register
3674 * ------------------------
3675 * Configures and reports the port MTU.
3677 #define MLXSW_REG_PMTU_ID 0x5003
3678 #define MLXSW_REG_PMTU_LEN 0x10
3680 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
3682 /* reg_pmtu_local_port
3683 * Local port number.
3686 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
3690 * When port type (e.g. Ethernet) is configured, the relevant MTU is
3691 * reported, otherwise the minimum between the max_mtu of the different
3692 * types is reported.
3695 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
3697 /* reg_pmtu_admin_mtu
3698 * MTU value to set port to. Must be smaller or equal to max_mtu.
3699 * Note: If port type is Infiniband, then port must be disabled, when its
3703 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
3705 /* reg_pmtu_oper_mtu
3706 * The actual MTU configured on the port. Packets exceeding this size
3708 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
3709 * oper_mtu might be smaller than admin_mtu.
3712 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
3714 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
3717 MLXSW_REG_ZERO(pmtu, payload);
3718 mlxsw_reg_pmtu_local_port_set(payload, local_port);
3719 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
3720 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
3721 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
3724 /* PTYS - Port Type and Speed Register
3725 * -----------------------------------
3726 * Configures and reports the port speed type.
3728 * Note: When set while the link is up, the changes will not take effect
3729 * until the port transitions from down to up state.
3731 #define MLXSW_REG_PTYS_ID 0x5004
3732 #define MLXSW_REG_PTYS_LEN 0x40
3734 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
3737 * Auto negotiation disable administrative configuration
3738 * 0 - Device doesn't support AN disable.
3739 * 1 - Device supports AN disable.
3742 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
3744 /* reg_ptys_local_port
3745 * Local port number.
3748 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
3750 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
3751 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
3753 /* reg_ptys_proto_mask
3754 * Protocol mask. Indicates which protocol is used.
3756 * 1 - Fibre Channel.
3760 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
3763 MLXSW_REG_PTYS_AN_STATUS_NA,
3764 MLXSW_REG_PTYS_AN_STATUS_OK,
3765 MLXSW_REG_PTYS_AN_STATUS_FAIL,
3768 /* reg_ptys_an_status
3769 * Autonegotiation status.
3772 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
3774 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
3775 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
3776 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
3777 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
3778 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
3779 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
3780 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
3781 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
3782 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
3783 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
3784 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
3785 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
3786 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
3787 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
3788 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
3789 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
3790 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
3791 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
3792 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
3793 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
3794 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
3795 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
3796 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
3797 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
3798 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
3799 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
3800 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
3801 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
3803 /* reg_ptys_eth_proto_cap
3804 * Ethernet port supported speeds and protocols.
3807 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
3809 /* reg_ptys_ib_link_width_cap
3810 * IB port supported widths.
3813 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
3815 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
3816 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
3817 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
3818 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
3819 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
3820 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
3822 /* reg_ptys_ib_proto_cap
3823 * IB port supported speeds and protocols.
3826 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
3828 /* reg_ptys_eth_proto_admin
3829 * Speed and protocol to set port to.
3832 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
3834 /* reg_ptys_ib_link_width_admin
3835 * IB width to set port to.
3838 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
3840 /* reg_ptys_ib_proto_admin
3841 * IB speeds and protocols to set port to.
3844 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
3846 /* reg_ptys_eth_proto_oper
3847 * The current speed and protocol configured for the port.
3850 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
3852 /* reg_ptys_ib_link_width_oper
3853 * The current IB width to set port to.
3856 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
3858 /* reg_ptys_ib_proto_oper
3859 * The current IB speed and protocol.
3862 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
3864 /* reg_ptys_eth_proto_lp_advertise
3865 * The protocols that were advertised by the link partner during
3869 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
3871 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
3872 u32 proto_admin, bool autoneg)
3874 MLXSW_REG_ZERO(ptys, payload);
3875 mlxsw_reg_ptys_local_port_set(payload, local_port);
3876 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
3877 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
3878 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
3881 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
3882 u32 *p_eth_proto_cap,
3883 u32 *p_eth_proto_adm,
3884 u32 *p_eth_proto_oper)
3886 if (p_eth_proto_cap)
3887 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
3888 if (p_eth_proto_adm)
3889 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
3890 if (p_eth_proto_oper)
3891 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
3894 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
3895 u16 proto_admin, u16 link_width)
3897 MLXSW_REG_ZERO(ptys, payload);
3898 mlxsw_reg_ptys_local_port_set(payload, local_port);
3899 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
3900 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
3901 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
3904 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
3905 u16 *p_ib_link_width_cap,
3906 u16 *p_ib_proto_oper,
3907 u16 *p_ib_link_width_oper)
3910 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
3911 if (p_ib_link_width_cap)
3912 *p_ib_link_width_cap =
3913 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
3914 if (p_ib_proto_oper)
3915 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
3916 if (p_ib_link_width_oper)
3917 *p_ib_link_width_oper =
3918 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
3921 /* PPAD - Port Physical Address Register
3922 * -------------------------------------
3923 * The PPAD register configures the per port physical MAC address.
3925 #define MLXSW_REG_PPAD_ID 0x5005
3926 #define MLXSW_REG_PPAD_LEN 0x10
3928 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
3930 /* reg_ppad_single_base_mac
3931 * 0: base_mac, local port should be 0 and mac[7:0] is
3932 * reserved. HW will set incremental
3933 * 1: single_mac - mac of the local_port
3936 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
3938 /* reg_ppad_local_port
3939 * port number, if single_base_mac = 0 then local_port is reserved
3942 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
3945 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
3946 * If single_base_mac = 1 - the per port MAC address
3949 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
3951 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
3954 MLXSW_REG_ZERO(ppad, payload);
3955 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
3956 mlxsw_reg_ppad_local_port_set(payload, local_port);
3959 /* PAOS - Ports Administrative and Operational Status Register
3960 * -----------------------------------------------------------
3961 * Configures and retrieves per port administrative and operational status.
3963 #define MLXSW_REG_PAOS_ID 0x5006
3964 #define MLXSW_REG_PAOS_LEN 0x10
3966 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
3969 * Switch partition ID with which to associate the port.
3970 * Note: while external ports uses unique local port numbers (and thus swid is
3971 * redundant), router ports use the same local port number where swid is the
3972 * only indication for the relevant port.
3975 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
3977 /* reg_paos_local_port
3978 * Local port number.
3981 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
3983 /* reg_paos_admin_status
3984 * Port administrative state (the desired state of the port):
3987 * 3 - Up once. This means that in case of link failure, the port won't go
3988 * into polling mode, but will wait to be re-enabled by software.
3989 * 4 - Disabled by system. Can only be set by hardware.
3992 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
3994 /* reg_paos_oper_status
3995 * Port operational state (the current state):
3998 * 3 - Down by port failure. This means that the device will not let the
3999 * port up again until explicitly specified by software.
4002 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4005 * Admin state update enabled.
4008 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4011 * Event update enable. If this bit is set, event generation will be
4012 * updated based on the e field.
4015 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4018 * Event generation on operational state change:
4019 * 0 - Do not generate event.
4020 * 1 - Generate Event.
4021 * 2 - Generate Single Event.
4024 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4026 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4027 enum mlxsw_port_admin_status status)
4029 MLXSW_REG_ZERO(paos, payload);
4030 mlxsw_reg_paos_swid_set(payload, 0);
4031 mlxsw_reg_paos_local_port_set(payload, local_port);
4032 mlxsw_reg_paos_admin_status_set(payload, status);
4033 mlxsw_reg_paos_oper_status_set(payload, 0);
4034 mlxsw_reg_paos_ase_set(payload, 1);
4035 mlxsw_reg_paos_ee_set(payload, 1);
4036 mlxsw_reg_paos_e_set(payload, 1);
4039 /* PFCC - Ports Flow Control Configuration Register
4040 * ------------------------------------------------
4041 * Configures and retrieves the per port flow control configuration.
4043 #define MLXSW_REG_PFCC_ID 0x5007
4044 #define MLXSW_REG_PFCC_LEN 0x20
4046 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4048 /* reg_pfcc_local_port
4049 * Local port number.
4052 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4055 * Port number access type. Determines the way local_port is interpreted:
4056 * 0 - Local port number.
4057 * 1 - IB / label port number.
4060 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4063 * Send to higher layers capabilities:
4064 * 0 - No capability of sending Pause and PFC frames to higher layers.
4065 * 1 - Device has capability of sending Pause and PFC frames to higher
4069 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4072 * Send to higher layers operation:
4073 * 0 - Pause and PFC frames are handled by the port (default).
4074 * 1 - Pause and PFC frames are handled by the port and also sent to
4075 * higher layers. Only valid if shl_cap = 1.
4078 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4081 * Pause policy auto negotiation.
4082 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4083 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4084 * based on the auto-negotiation resolution.
4087 * Note: The auto-negotiation advertisement is set according to pptx and
4088 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4090 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4092 /* reg_pfcc_prio_mask_tx
4093 * Bit per priority indicating if Tx flow control policy should be
4094 * updated based on bit pfctx.
4097 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4099 /* reg_pfcc_prio_mask_rx
4100 * Bit per priority indicating if Rx flow control policy should be
4101 * updated based on bit pfcrx.
4104 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4107 * Admin Pause policy on Tx.
4108 * 0 - Never generate Pause frames (default).
4109 * 1 - Generate Pause frames according to Rx buffer threshold.
4112 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4115 * Active (operational) Pause policy on Tx.
4116 * 0 - Never generate Pause frames.
4117 * 1 - Generate Pause frames according to Rx buffer threshold.
4120 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4123 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4124 * 0 - Never generate priority Pause frames on the specified priority
4126 * 1 - Generate priority Pause frames according to Rx buffer threshold on
4127 * the specified priority.
4130 * Note: pfctx and pptx must be mutually exclusive.
4132 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4135 * Admin Pause policy on Rx.
4136 * 0 - Ignore received Pause frames (default).
4137 * 1 - Respect received Pause frames.
4140 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4143 * Active (operational) Pause policy on Rx.
4144 * 0 - Ignore received Pause frames.
4145 * 1 - Respect received Pause frames.
4148 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4151 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4152 * 0 - Ignore incoming priority Pause frames on the specified priority
4154 * 1 - Respect incoming priority Pause frames on the specified priority.
4157 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4159 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4161 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4163 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4164 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4165 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4166 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4169 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4171 MLXSW_REG_ZERO(pfcc, payload);
4172 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4175 /* PPCNT - Ports Performance Counters Register
4176 * -------------------------------------------
4177 * The PPCNT register retrieves per port performance counters.
4179 #define MLXSW_REG_PPCNT_ID 0x5008
4180 #define MLXSW_REG_PPCNT_LEN 0x100
4181 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4183 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4186 * For HCA: must be always 0.
4187 * Switch partition ID to associate port with.
4188 * Switch partitions are numbered from 0 to 7 inclusively.
4189 * Switch partition 254 indicates stacking ports.
4190 * Switch partition 255 indicates all switch partitions.
4191 * Only valid on Set() operation with local_port=255.
4194 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4196 /* reg_ppcnt_local_port
4197 * Local port number.
4198 * 255 indicates all ports on the device, and is only allowed
4199 * for Set() operation.
4202 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4205 * Port number access type:
4206 * 0 - Local port number
4207 * 1 - IB port number
4210 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4212 enum mlxsw_reg_ppcnt_grp {
4213 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4214 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4215 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4216 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4217 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4218 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4222 * Performance counter group.
4223 * Group 63 indicates all groups. Only valid on Set() operation with
4225 * 0x0: IEEE 802.3 Counters
4226 * 0x1: RFC 2863 Counters
4227 * 0x2: RFC 2819 Counters
4228 * 0x3: RFC 3635 Counters
4229 * 0x5: Ethernet Extended Counters
4230 * 0x8: Link Level Retransmission Counters
4231 * 0x10: Per Priority Counters
4232 * 0x11: Per Traffic Class Counters
4233 * 0x12: Physical Layer Counters
4234 * 0x13: Per Traffic Class Congestion Counters
4237 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4240 * Clear counters. Setting the clr bit will reset the counter value
4241 * for all counters in the counter group. This bit can be set
4242 * for both Set() and Get() operation.
4245 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4247 /* reg_ppcnt_prio_tc
4248 * Priority for counter set that support per priority, valid values: 0-7.
4249 * Traffic class for counter set that support per traffic class,
4250 * valid values: 0- cap_max_tclass-1 .
4251 * For HCA: cap_max_tclass is always 8.
4252 * Otherwise must be 0.
4255 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4257 /* Ethernet IEEE 802.3 Counter Group */
4259 /* reg_ppcnt_a_frames_transmitted_ok
4262 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4263 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4265 /* reg_ppcnt_a_frames_received_ok
4268 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4269 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4271 /* reg_ppcnt_a_frame_check_sequence_errors
4274 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4275 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4277 /* reg_ppcnt_a_alignment_errors
4280 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4281 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4283 /* reg_ppcnt_a_octets_transmitted_ok
4286 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4287 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4289 /* reg_ppcnt_a_octets_received_ok
4292 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4293 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4295 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4298 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4299 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4301 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4304 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4305 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4307 /* reg_ppcnt_a_multicast_frames_received_ok
4310 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4311 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4313 /* reg_ppcnt_a_broadcast_frames_received_ok
4316 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4317 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4319 /* reg_ppcnt_a_in_range_length_errors
4322 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4323 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4325 /* reg_ppcnt_a_out_of_range_length_field
4328 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4329 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4331 /* reg_ppcnt_a_frame_too_long_errors
4334 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4335 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4337 /* reg_ppcnt_a_symbol_error_during_carrier
4340 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4341 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4343 /* reg_ppcnt_a_mac_control_frames_transmitted
4346 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4347 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4349 /* reg_ppcnt_a_mac_control_frames_received
4352 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4353 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4355 /* reg_ppcnt_a_unsupported_opcodes_received
4358 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4359 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4361 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4364 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4365 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4367 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4370 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4371 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4373 /* Ethernet RFC 2819 Counter Group */
4375 /* reg_ppcnt_ether_stats_pkts64octets
4378 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4379 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4381 /* reg_ppcnt_ether_stats_pkts65to127octets
4384 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4385 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4387 /* reg_ppcnt_ether_stats_pkts128to255octets
4390 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4391 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4393 /* reg_ppcnt_ether_stats_pkts256to511octets
4396 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4397 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4399 /* reg_ppcnt_ether_stats_pkts512to1023octets
4402 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4403 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4405 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4408 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4409 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4411 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4414 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4415 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4417 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4420 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4421 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4423 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4426 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4427 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4429 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4432 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4433 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4435 /* Ethernet Extended Counter Group Counters */
4437 /* reg_ppcnt_ecn_marked
4440 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4441 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4443 /* Ethernet Per Priority Group Counters */
4445 /* reg_ppcnt_rx_octets
4448 MLXSW_ITEM64(reg, ppcnt, rx_octets,
4449 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4451 /* reg_ppcnt_rx_frames
4454 MLXSW_ITEM64(reg, ppcnt, rx_frames,
4455 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4457 /* reg_ppcnt_tx_octets
4460 MLXSW_ITEM64(reg, ppcnt, tx_octets,
4461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4463 /* reg_ppcnt_tx_frames
4466 MLXSW_ITEM64(reg, ppcnt, tx_frames,
4467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4469 /* reg_ppcnt_rx_pause
4472 MLXSW_ITEM64(reg, ppcnt, rx_pause,
4473 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4475 /* reg_ppcnt_rx_pause_duration
4478 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
4479 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4481 /* reg_ppcnt_tx_pause
4484 MLXSW_ITEM64(reg, ppcnt, tx_pause,
4485 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4487 /* reg_ppcnt_tx_pause_duration
4490 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
4491 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4493 /* reg_ppcnt_rx_pause_transition
4496 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
4497 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4499 /* Ethernet Per Traffic Group Counters */
4501 /* reg_ppcnt_tc_transmit_queue
4502 * Contains the transmit queue depth in cells of traffic class
4503 * selected by prio_tc and the port selected by local_port.
4504 * The field cannot be cleared.
4507 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
4508 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4510 /* reg_ppcnt_tc_no_buffer_discard_uc
4511 * The number of unicast packets dropped due to lack of shared
4515 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
4516 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4518 /* Ethernet Per Traffic Class Congestion Group Counters */
4520 /* reg_ppcnt_wred_discard
4523 MLXSW_ITEM64(reg, ppcnt, wred_discard,
4524 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4526 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
4527 enum mlxsw_reg_ppcnt_grp grp,
4530 MLXSW_REG_ZERO(ppcnt, payload);
4531 mlxsw_reg_ppcnt_swid_set(payload, 0);
4532 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
4533 mlxsw_reg_ppcnt_pnat_set(payload, 0);
4534 mlxsw_reg_ppcnt_grp_set(payload, grp);
4535 mlxsw_reg_ppcnt_clr_set(payload, 0);
4536 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
4539 /* PLIB - Port Local to InfiniBand Port
4540 * ------------------------------------
4541 * The PLIB register performs mapping from Local Port into InfiniBand Port.
4543 #define MLXSW_REG_PLIB_ID 0x500A
4544 #define MLXSW_REG_PLIB_LEN 0x10
4546 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
4548 /* reg_plib_local_port
4549 * Local port number.
4552 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
4555 * InfiniBand port remapping for local_port.
4558 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
4560 /* PPTB - Port Prio To Buffer Register
4561 * -----------------------------------
4562 * Configures the switch priority to buffer table.
4564 #define MLXSW_REG_PPTB_ID 0x500B
4565 #define MLXSW_REG_PPTB_LEN 0x10
4567 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
4570 MLXSW_REG_PPTB_MM_UM,
4571 MLXSW_REG_PPTB_MM_UNICAST,
4572 MLXSW_REG_PPTB_MM_MULTICAST,
4577 * 0 - Map both unicast and multicast packets to the same buffer.
4578 * 1 - Map only unicast packets.
4579 * 2 - Map only multicast packets.
4582 * Note: SwitchX-2 only supports the first option.
4584 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
4586 /* reg_pptb_local_port
4587 * Local port number.
4590 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
4593 * Enables the update of the untagged_buf field.
4596 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
4599 * Enables the update of the prio_to_buff field.
4600 * Bit <i> is a flag for updating the mapping for switch priority <i>.
4603 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
4605 /* reg_pptb_prio_to_buff
4606 * Mapping of switch priority <i> to one of the allocated receive port
4610 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
4613 * Enables the update of the prio_to_buff field.
4614 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
4617 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
4619 /* reg_pptb_untagged_buff
4620 * Mapping of untagged frames to one of the allocated receive port buffers.
4623 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
4624 * Spectrum, as it maps untagged packets based on the default switch priority.
4626 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
4628 /* reg_pptb_prio_to_buff_msb
4629 * Mapping of switch priority <i+8> to one of the allocated receive port
4633 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
4635 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
4637 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
4639 MLXSW_REG_ZERO(pptb, payload);
4640 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
4641 mlxsw_reg_pptb_local_port_set(payload, local_port);
4642 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
4643 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
4646 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
4649 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
4650 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
4653 /* PBMC - Port Buffer Management Control Register
4654 * ----------------------------------------------
4655 * The PBMC register configures and retrieves the port packet buffer
4656 * allocation for different Prios, and the Pause threshold management.
4658 #define MLXSW_REG_PBMC_ID 0x500C
4659 #define MLXSW_REG_PBMC_LEN 0x6C
4661 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
4663 /* reg_pbmc_local_port
4664 * Local port number.
4667 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
4669 /* reg_pbmc_xoff_timer_value
4670 * When device generates a pause frame, it uses this value as the pause
4671 * timer (time for the peer port to pause in quota-512 bit time).
4674 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
4676 /* reg_pbmc_xoff_refresh
4677 * The time before a new pause frame should be sent to refresh the pause RW
4678 * state. Using the same units as xoff_timer_value above (in quota-512 bit
4682 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
4684 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
4686 /* reg_pbmc_buf_lossy
4687 * The field indicates if the buffer is lossy.
4692 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
4694 /* reg_pbmc_buf_epsb
4695 * Eligible for Port Shared buffer.
4696 * If epsb is set, packets assigned to buffer are allowed to insert the port
4698 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
4701 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
4703 /* reg_pbmc_buf_size
4704 * The part of the packet buffer array is allocated for the specific buffer.
4705 * Units are represented in cells.
4708 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
4710 /* reg_pbmc_buf_xoff_threshold
4711 * Once the amount of data in the buffer goes above this value, device
4712 * starts sending PFC frames for all priorities associated with the
4713 * buffer. Units are represented in cells. Reserved in case of lossy
4717 * Note: In Spectrum, reserved for buffer[9].
4719 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
4722 /* reg_pbmc_buf_xon_threshold
4723 * When the amount of data in the buffer goes below this value, device
4724 * stops sending PFC frames for the priorities associated with the
4725 * buffer. Units are represented in cells. Reserved in case of lossy
4729 * Note: In Spectrum, reserved for buffer[9].
4731 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
4734 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
4735 u16 xoff_timer_value, u16 xoff_refresh)
4737 MLXSW_REG_ZERO(pbmc, payload);
4738 mlxsw_reg_pbmc_local_port_set(payload, local_port);
4739 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
4740 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
4743 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
4747 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
4748 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
4749 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
4752 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
4753 int buf_index, u16 size,
4756 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
4757 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
4758 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
4759 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
4760 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
4763 /* PSPA - Port Switch Partition Allocation
4764 * ---------------------------------------
4765 * Controls the association of a port with a switch partition and enables
4766 * configuring ports as stacking ports.
4768 #define MLXSW_REG_PSPA_ID 0x500D
4769 #define MLXSW_REG_PSPA_LEN 0x8
4771 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
4774 * Switch partition ID.
4777 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
4779 /* reg_pspa_local_port
4780 * Local port number.
4783 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
4785 /* reg_pspa_sub_port
4786 * Virtual port within the local port. Set to 0 when virtual ports are
4787 * disabled on the local port.
4790 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
4792 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
4794 MLXSW_REG_ZERO(pspa, payload);
4795 mlxsw_reg_pspa_swid_set(payload, swid);
4796 mlxsw_reg_pspa_local_port_set(payload, local_port);
4797 mlxsw_reg_pspa_sub_port_set(payload, 0);
4800 /* HTGT - Host Trap Group Table
4801 * ----------------------------
4802 * Configures the properties for forwarding to CPU.
4804 #define MLXSW_REG_HTGT_ID 0x7002
4805 #define MLXSW_REG_HTGT_LEN 0x20
4807 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
4810 * Switch partition ID.
4813 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
4815 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
4821 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
4823 enum mlxsw_reg_htgt_trap_group {
4824 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4825 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
4826 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
4827 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
4828 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
4829 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
4830 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
4831 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
4832 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
4833 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
4834 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
4835 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
4836 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
4837 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
4838 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
4839 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
4840 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
4841 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
4842 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
4843 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
4844 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
4847 /* reg_htgt_trap_group
4848 * Trap group number. User defined number specifying which trap groups
4849 * should be forwarded to the CPU. The mapping between trap IDs and trap
4850 * groups is configured using HPKT register.
4853 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
4856 MLXSW_REG_HTGT_POLICER_DISABLE,
4857 MLXSW_REG_HTGT_POLICER_ENABLE,
4861 * Enable policer ID specified using 'pid' field.
4864 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
4866 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
4869 * Policer ID for the trap group.
4872 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
4874 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
4876 /* reg_htgt_mirror_action
4877 * Mirror action to use.
4879 * 1 - Trap to CPU and mirror to a mirroring agent.
4880 * 2 - Mirror to a mirroring agent and do not trap to CPU.
4883 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
4885 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
4887 /* reg_htgt_mirroring_agent
4891 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
4893 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
4895 /* reg_htgt_priority
4896 * Trap group priority.
4897 * In case a packet matches multiple classification rules, the packet will
4898 * only be trapped once, based on the trap ID associated with the group (via
4899 * register HPKT) with the highest priority.
4900 * Supported values are 0-7, with 7 represnting the highest priority.
4903 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
4904 * by the 'trap_group' field.
4906 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
4908 #define MLXSW_REG_HTGT_DEFAULT_TC 7
4910 /* reg_htgt_local_path_cpu_tclass
4911 * CPU ingress traffic class for the trap group.
4914 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
4916 enum mlxsw_reg_htgt_local_path_rdq {
4917 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
4918 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
4919 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
4920 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
4922 /* reg_htgt_local_path_rdq
4923 * Receive descriptor queue (RDQ) to use for the trap group.
4926 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
4928 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
4931 MLXSW_REG_ZERO(htgt, payload);
4933 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
4934 mlxsw_reg_htgt_pide_set(payload,
4935 MLXSW_REG_HTGT_POLICER_DISABLE);
4937 mlxsw_reg_htgt_pide_set(payload,
4938 MLXSW_REG_HTGT_POLICER_ENABLE);
4939 mlxsw_reg_htgt_pid_set(payload, policer_id);
4942 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
4943 mlxsw_reg_htgt_trap_group_set(payload, group);
4944 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
4945 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
4946 mlxsw_reg_htgt_priority_set(payload, priority);
4947 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
4948 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
4951 /* HPKT - Host Packet Trap
4952 * -----------------------
4953 * Configures trap IDs inside trap groups.
4955 #define MLXSW_REG_HPKT_ID 0x7003
4956 #define MLXSW_REG_HPKT_LEN 0x10
4958 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
4961 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
4962 MLXSW_REG_HPKT_ACK_REQUIRED,
4966 * Require acknowledgements from the host for events.
4967 * If set, then the device will wait for the event it sent to be acknowledged
4968 * by the host. This option is only relevant for event trap IDs.
4971 * Note: Currently not supported by firmware.
4973 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
4975 enum mlxsw_reg_hpkt_action {
4976 MLXSW_REG_HPKT_ACTION_FORWARD,
4977 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
4978 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
4979 MLXSW_REG_HPKT_ACTION_DISCARD,
4980 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
4981 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
4985 * Action to perform on packet when trapped.
4986 * 0 - No action. Forward to CPU based on switching rules.
4987 * 1 - Trap to CPU (CPU receives sole copy).
4988 * 2 - Mirror to CPU (CPU receives a replica of the packet).
4990 * 4 - Soft discard (allow other traps to act on the packet).
4991 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
4994 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
4995 * addressed to the CPU.
4997 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
4999 /* reg_hpkt_trap_group
5000 * Trap group to associate the trap with.
5003 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5009 * Note: A trap ID can only be associated with a single trap group. The device
5010 * will associate the trap ID with the last trap group configured.
5012 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5015 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5016 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5017 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5021 * Configure dedicated buffer resources for control packets.
5022 * Ignored by SwitchX-2.
5023 * 0 - Keep factory defaults.
5024 * 1 - Do not use control buffer for this trap ID.
5025 * 2 - Use control buffer for this trap ID.
5028 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5030 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5031 enum mlxsw_reg_htgt_trap_group trap_group,
5034 MLXSW_REG_ZERO(hpkt, payload);
5035 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5036 mlxsw_reg_hpkt_action_set(payload, action);
5037 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5038 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5039 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5040 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5041 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5044 /* RGCR - Router General Configuration Register
5045 * --------------------------------------------
5046 * The register is used for setting up the router configuration.
5048 #define MLXSW_REG_RGCR_ID 0x8001
5049 #define MLXSW_REG_RGCR_LEN 0x28
5051 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5054 * IPv4 router enable.
5057 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5060 * IPv6 router enable.
5063 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5065 /* reg_rgcr_max_router_interfaces
5066 * Defines the maximum number of active router interfaces for all virtual
5070 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5073 * Update switch priority and packet color.
5074 * 0 - Preserve the value of Switch Priority and packet color.
5075 * 1 - Recalculate the value of Switch Priority and packet color.
5078 * Note: Not supported by SwitchX and SwitchX-2.
5080 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5083 * Indicates how to handle the pcp_rewrite_en value:
5084 * 0 - Preserve the value of pcp_rewrite_en.
5085 * 2 - Disable PCP rewrite.
5086 * 3 - Enable PCP rewrite.
5089 * Note: Not supported by SwitchX and SwitchX-2.
5091 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5093 /* reg_rgcr_activity_dis
5095 * 0 - Activity will be set when an entry is hit (default).
5096 * 1 - Activity will not be set when an entry is hit.
5098 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5100 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5102 * Bits 2:7 are reserved.
5105 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5107 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5109 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5112 MLXSW_REG_ZERO(rgcr, payload);
5113 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5114 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5117 /* RITR - Router Interface Table Register
5118 * --------------------------------------
5119 * The register is used to configure the router interface table.
5121 #define MLXSW_REG_RITR_ID 0x8002
5122 #define MLXSW_REG_RITR_LEN 0x40
5124 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5127 * Enables routing on the router interface.
5130 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5133 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5137 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5140 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5144 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5147 * IPv4 multicast routing enable.
5150 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5153 * IPv6 multicast routing enable.
5156 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5158 enum mlxsw_reg_ritr_if_type {
5159 /* VLAN interface. */
5160 MLXSW_REG_RITR_VLAN_IF,
5161 /* FID interface. */
5162 MLXSW_REG_RITR_FID_IF,
5163 /* Sub-port interface. */
5164 MLXSW_REG_RITR_SP_IF,
5165 /* Loopback Interface. */
5166 MLXSW_REG_RITR_LOOPBACK_IF,
5170 * Router interface type as per enum mlxsw_reg_ritr_if_type.
5173 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5176 MLXSW_REG_RITR_RIF_CREATE,
5177 MLXSW_REG_RITR_RIF_DEL,
5182 * 0 - Create or edit RIF.
5184 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5185 * is not supported. An interface must be deleted and re-created in order
5186 * to update properties.
5189 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5192 * Router interface index. A pointer to the Router Interface Table.
5195 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5198 * IPv4 Forwarding Enable.
5199 * Enables routing of IPv4 traffic on the router interface. When disabled,
5200 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5201 * Not supported in SwitchX-2.
5204 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5207 * IPv6 Forwarding Enable.
5208 * Enables routing of IPv6 traffic on the router interface. When disabled,
5209 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5210 * Not supported in SwitchX-2.
5213 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5215 /* reg_ritr_ipv4_mc_fe
5216 * IPv4 Multicast Forwarding Enable.
5217 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5221 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5223 /* reg_ritr_ipv6_mc_fe
5224 * IPv6 Multicast Forwarding Enable.
5225 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5229 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5232 * Loop-back filter enable for unicast packets.
5233 * If the flag is set then loop-back filter for unicast packets is
5234 * implemented on the RIF. Multicast packets are always subject to
5235 * loop-back filtering.
5238 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5240 /* reg_ritr_virtual_router
5241 * Virtual router ID associated with the router interface.
5244 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5247 * Router interface MTU.
5250 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5253 * Switch partition ID.
5256 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5259 * Router interface MAC address.
5260 * In Spectrum, all MAC addresses must have the same 38 MSBits.
5263 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5265 /* reg_ritr_if_vrrp_id_ipv6
5267 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5270 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5272 /* reg_ritr_if_vrrp_id_ipv4
5274 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5277 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5279 /* VLAN Interface */
5281 /* reg_ritr_vlan_if_vid
5285 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5289 /* reg_ritr_fid_if_fid
5290 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5291 * the vFID range are supported.
5294 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5296 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5297 enum mlxsw_reg_ritr_if_type rif_type,
5300 if (rif_type == MLXSW_REG_RITR_FID_IF)
5301 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5303 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5306 /* Sub-port Interface */
5308 /* reg_ritr_sp_if_lag
5309 * LAG indication. When this bit is set the system_port field holds the
5313 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5315 /* reg_ritr_sp_system_port
5316 * Port unique indentifier. When lag bit is set, this field holds the
5317 * lag_id in bits 0:9.
5320 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5322 /* reg_ritr_sp_if_vid
5326 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5328 /* Loopback Interface */
5330 enum mlxsw_reg_ritr_loopback_protocol {
5331 /* IPinIP IPv4 underlay Unicast */
5332 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5333 /* IPinIP IPv6 underlay Unicast */
5334 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5337 /* reg_ritr_loopback_protocol
5340 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5342 enum mlxsw_reg_ritr_loopback_ipip_type {
5343 /* Tunnel is IPinIP. */
5344 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5345 /* Tunnel is GRE, no key. */
5346 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5347 /* Tunnel is GRE, with a key. */
5348 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5351 /* reg_ritr_loopback_ipip_type
5352 * Encapsulation type.
5355 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5357 enum mlxsw_reg_ritr_loopback_ipip_options {
5358 /* The key is defined by gre_key. */
5359 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5362 /* reg_ritr_loopback_ipip_options
5365 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5367 /* reg_ritr_loopback_ipip_uvr
5368 * Underlay Virtual Router ID.
5369 * Range is 0..cap_max_virtual_routers-1.
5370 * Reserved for Spectrum-2.
5373 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5375 /* reg_ritr_loopback_ipip_usip*
5376 * Encapsulation Underlay source IP.
5379 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5380 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5382 /* reg_ritr_loopback_ipip_gre_key
5384 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
5387 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5389 /* Shared between ingress/egress */
5390 enum mlxsw_reg_ritr_counter_set_type {
5392 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5393 /* Basic. Used for router interfaces, counting the following:
5394 * - Error and Discard counters.
5395 * - Unicast, Multicast and Broadcast counters. Sharing the
5396 * same set of counters for the different type of traffic
5397 * (IPv4, IPv6 and mpls).
5399 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
5402 /* reg_ritr_ingress_counter_index
5403 * Counter Index for flow counter.
5406 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
5408 /* reg_ritr_ingress_counter_set_type
5409 * Igress Counter Set Type for router interface counter.
5412 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
5414 /* reg_ritr_egress_counter_index
5415 * Counter Index for flow counter.
5418 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
5420 /* reg_ritr_egress_counter_set_type
5421 * Egress Counter Set Type for router interface counter.
5424 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
5426 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
5427 bool enable, bool egress)
5429 enum mlxsw_reg_ritr_counter_set_type set_type;
5432 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
5434 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
5435 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
5438 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
5440 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
5443 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
5445 MLXSW_REG_ZERO(ritr, payload);
5446 mlxsw_reg_ritr_rif_set(payload, rif);
5449 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
5450 u16 system_port, u16 vid)
5452 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
5453 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
5454 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
5457 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
5458 enum mlxsw_reg_ritr_if_type type,
5459 u16 rif, u16 vr_id, u16 mtu)
5461 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
5463 MLXSW_REG_ZERO(ritr, payload);
5464 mlxsw_reg_ritr_enable_set(payload, enable);
5465 mlxsw_reg_ritr_ipv4_set(payload, 1);
5466 mlxsw_reg_ritr_ipv6_set(payload, 1);
5467 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
5468 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
5469 mlxsw_reg_ritr_type_set(payload, type);
5470 mlxsw_reg_ritr_op_set(payload, op);
5471 mlxsw_reg_ritr_rif_set(payload, rif);
5472 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
5473 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
5474 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
5475 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
5476 mlxsw_reg_ritr_lb_en_set(payload, 1);
5477 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
5478 mlxsw_reg_ritr_mtu_set(payload, mtu);
5481 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
5483 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
5487 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
5488 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5489 enum mlxsw_reg_ritr_loopback_ipip_options options,
5490 u16 uvr_id, u32 gre_key)
5492 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
5493 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
5494 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
5495 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
5499 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
5500 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5501 enum mlxsw_reg_ritr_loopback_ipip_options options,
5502 u16 uvr_id, u32 usip, u32 gre_key)
5504 mlxsw_reg_ritr_loopback_protocol_set(payload,
5505 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
5506 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
5508 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
5511 /* RTAR - Router TCAM Allocation Register
5512 * --------------------------------------
5513 * This register is used for allocation of regions in the TCAM table.
5515 #define MLXSW_REG_RTAR_ID 0x8004
5516 #define MLXSW_REG_RTAR_LEN 0x20
5518 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
5520 enum mlxsw_reg_rtar_op {
5521 MLXSW_REG_RTAR_OP_ALLOCATE,
5522 MLXSW_REG_RTAR_OP_RESIZE,
5523 MLXSW_REG_RTAR_OP_DEALLOCATE,
5529 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
5531 enum mlxsw_reg_rtar_key_type {
5532 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
5533 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
5536 /* reg_rtar_key_type
5537 * TCAM key type for the region.
5540 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
5542 /* reg_rtar_region_size
5543 * TCAM region size. When allocating/resizing this is the requested
5544 * size, the response is the actual size.
5545 * Note: Actual size may be larger than requested.
5546 * Reserved for op = Deallocate
5549 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
5551 static inline void mlxsw_reg_rtar_pack(char *payload,
5552 enum mlxsw_reg_rtar_op op,
5553 enum mlxsw_reg_rtar_key_type key_type,
5556 MLXSW_REG_ZERO(rtar, payload);
5557 mlxsw_reg_rtar_op_set(payload, op);
5558 mlxsw_reg_rtar_key_type_set(payload, key_type);
5559 mlxsw_reg_rtar_region_size_set(payload, region_size);
5562 /* RATR - Router Adjacency Table Register
5563 * --------------------------------------
5564 * The RATR register is used to configure the Router Adjacency (next-hop)
5567 #define MLXSW_REG_RATR_ID 0x8008
5568 #define MLXSW_REG_RATR_LEN 0x2C
5570 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
5572 enum mlxsw_reg_ratr_op {
5574 MLXSW_REG_RATR_OP_QUERY_READ = 0,
5575 /* Read and clear activity */
5576 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
5577 /* Write Adjacency entry */
5578 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
5579 /* Write Adjacency entry only if the activity is cleared.
5580 * The write may not succeed if the activity is set. There is not
5581 * direct feedback if the write has succeeded or not, however
5582 * the get will reveal the actual entry (SW can compare the get
5583 * response to the set command).
5585 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
5589 * Note that Write operation may also be used for updating
5590 * counter_set_type and counter_index. In this case all other
5591 * fields must not be updated.
5594 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
5597 * Valid bit. Indicates if the adjacency entry is valid.
5598 * Note: the device may need some time before reusing an invalidated
5599 * entry. During this time the entry can not be reused. It is
5600 * recommended to use another entry before reusing an invalidated
5601 * entry (e.g. software can put it at the end of the list for
5602 * reusing). Trying to access an invalidated entry not yet cleared
5603 * by the device results with failure indicating "Try Again" status.
5604 * When valid is '0' then egress_router_interface,trap_action,
5605 * adjacency_parameters and counters are reserved
5608 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
5611 * Activity. Set for new entries. Set if a packet lookup has hit on
5612 * the specific entry. To clear the a bit, use "clear activity".
5615 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
5617 enum mlxsw_reg_ratr_type {
5619 MLXSW_REG_RATR_TYPE_ETHERNET,
5620 /* IPoIB Unicast without GRH.
5621 * Reserved for Spectrum.
5623 MLXSW_REG_RATR_TYPE_IPOIB_UC,
5624 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
5626 * Reserved for Spectrum.
5628 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
5630 * Reserved for Spectrum.
5632 MLXSW_REG_RATR_TYPE_IPOIB_MC,
5634 * Reserved for SwitchX/-2.
5636 MLXSW_REG_RATR_TYPE_MPLS,
5638 * Reserved for SwitchX/-2.
5640 MLXSW_REG_RATR_TYPE_IPIP,
5644 * Adjacency entry type.
5647 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
5649 /* reg_ratr_adjacency_index_low
5650 * Bits 15:0 of index into the adjacency table.
5651 * For SwitchX and SwitchX-2, the adjacency table is linear and
5652 * used for adjacency entries only.
5653 * For Spectrum, the index is to the KVD linear.
5656 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
5658 /* reg_ratr_egress_router_interface
5659 * Range is 0 .. cap_max_router_interfaces - 1
5662 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
5664 enum mlxsw_reg_ratr_trap_action {
5665 MLXSW_REG_RATR_TRAP_ACTION_NOP,
5666 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
5667 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
5668 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
5669 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
5672 /* reg_ratr_trap_action
5673 * see mlxsw_reg_ratr_trap_action
5676 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
5678 /* reg_ratr_adjacency_index_high
5679 * Bits 23:16 of the adjacency_index.
5682 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
5684 enum mlxsw_reg_ratr_trap_id {
5685 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
5686 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
5690 * Trap ID to be reported to CPU.
5691 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
5692 * For trap_action of NOP, MIRROR and DISCARD_ERROR
5695 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
5697 /* reg_ratr_eth_destination_mac
5698 * MAC address of the destination next-hop.
5701 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
5703 enum mlxsw_reg_ratr_ipip_type {
5704 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
5705 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
5706 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
5707 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
5710 /* reg_ratr_ipip_type
5711 * Underlay destination ip type.
5712 * Note: the type field must match the protocol of the router interface.
5715 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
5717 /* reg_ratr_ipip_ipv4_udip
5718 * Underlay ipv4 dip.
5719 * Reserved when ipip_type is IPv6.
5722 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
5724 /* reg_ratr_ipip_ipv6_ptr
5725 * Pointer to IPv6 underlay destination ip address.
5726 * For Spectrum: Pointer to KVD linear space.
5729 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
5731 enum mlxsw_reg_flow_counter_set_type {
5733 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
5734 /* Count packets and bytes */
5735 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
5736 /* Count only packets */
5737 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
5740 /* reg_ratr_counter_set_type
5741 * Counter set type for flow counters
5744 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
5746 /* reg_ratr_counter_index
5747 * Counter index for flow counters
5750 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
5753 mlxsw_reg_ratr_pack(char *payload,
5754 enum mlxsw_reg_ratr_op op, bool valid,
5755 enum mlxsw_reg_ratr_type type,
5756 u32 adjacency_index, u16 egress_rif)
5758 MLXSW_REG_ZERO(ratr, payload);
5759 mlxsw_reg_ratr_op_set(payload, op);
5760 mlxsw_reg_ratr_v_set(payload, valid);
5761 mlxsw_reg_ratr_type_set(payload, type);
5762 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
5763 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
5764 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
5767 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
5768 const char *dest_mac)
5770 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
5773 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
5775 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
5776 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
5779 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
5780 bool counter_enable)
5782 enum mlxsw_reg_flow_counter_set_type set_type;
5785 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
5787 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
5789 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
5790 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
5793 /* RDPM - Router DSCP to Priority Mapping
5794 * --------------------------------------
5795 * Controls the mapping from DSCP field to switch priority on routed packets
5797 #define MLXSW_REG_RDPM_ID 0x8009
5798 #define MLXSW_REG_RDPM_BASE_LEN 0x00
5799 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
5800 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
5801 #define MLXSW_REG_RDPM_LEN 0x40
5802 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
5803 MLXSW_REG_RDPM_LEN - \
5804 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
5806 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
5809 * Enable update of the specific entry
5812 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
5813 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
5815 /* reg_dscp_entry_prio
5819 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
5820 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
5822 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
5825 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
5826 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
5829 /* RICNT - Router Interface Counter Register
5830 * -----------------------------------------
5831 * The RICNT register retrieves per port performance counters
5833 #define MLXSW_REG_RICNT_ID 0x800B
5834 #define MLXSW_REG_RICNT_LEN 0x100
5836 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
5838 /* reg_ricnt_counter_index
5842 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
5844 enum mlxsw_reg_ricnt_counter_set_type {
5846 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
5847 /* Basic. Used for router interfaces, counting the following:
5848 * - Error and Discard counters.
5849 * - Unicast, Multicast and Broadcast counters. Sharing the
5850 * same set of counters for the different type of traffic
5851 * (IPv4, IPv6 and mpls).
5853 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
5856 /* reg_ricnt_counter_set_type
5857 * Counter Set Type for router interface counter
5860 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
5862 enum mlxsw_reg_ricnt_opcode {
5863 /* Nop. Supported only for read access*/
5864 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
5865 /* Clear. Setting the clr bit will reset the counter value for
5866 * all counters of the specified Router Interface.
5868 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
5875 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
5877 /* reg_ricnt_good_unicast_packets
5878 * good unicast packets.
5881 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
5883 /* reg_ricnt_good_multicast_packets
5884 * good multicast packets.
5887 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
5889 /* reg_ricnt_good_broadcast_packets
5890 * good broadcast packets
5893 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
5895 /* reg_ricnt_good_unicast_bytes
5896 * A count of L3 data and padding octets not including L2 headers
5897 * for good unicast frames.
5900 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
5902 /* reg_ricnt_good_multicast_bytes
5903 * A count of L3 data and padding octets not including L2 headers
5904 * for good multicast frames.
5907 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
5909 /* reg_ritr_good_broadcast_bytes
5910 * A count of L3 data and padding octets not including L2 headers
5911 * for good broadcast frames.
5914 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
5916 /* reg_ricnt_error_packets
5917 * A count of errored frames that do not pass the router checks.
5920 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
5922 /* reg_ricnt_discrad_packets
5923 * A count of non-errored frames that do not pass the router checks.
5926 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
5928 /* reg_ricnt_error_bytes
5929 * A count of L3 data and padding octets not including L2 headers
5930 * for errored frames.
5933 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
5935 /* reg_ricnt_discard_bytes
5936 * A count of L3 data and padding octets not including L2 headers
5937 * for non-errored frames that do not pass the router checks.
5940 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
5942 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
5943 enum mlxsw_reg_ricnt_opcode op)
5945 MLXSW_REG_ZERO(ricnt, payload);
5946 mlxsw_reg_ricnt_op_set(payload, op);
5947 mlxsw_reg_ricnt_counter_index_set(payload, index);
5948 mlxsw_reg_ricnt_counter_set_type_set(payload,
5949 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
5952 /* RRCR - Router Rules Copy Register Layout
5953 * ----------------------------------------
5954 * This register is used for moving and copying route entry rules.
5956 #define MLXSW_REG_RRCR_ID 0x800F
5957 #define MLXSW_REG_RRCR_LEN 0x24
5959 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
5961 enum mlxsw_reg_rrcr_op {
5963 MLXSW_REG_RRCR_OP_MOVE,
5965 MLXSW_REG_RRCR_OP_COPY,
5971 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
5974 * Offset within the region from which to copy/move.
5977 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
5980 * The number of rules to copy/move.
5983 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
5985 /* reg_rrcr_table_id
5986 * Identifier of the table on which to perform the operation. Encoding is the
5987 * same as in RTAR.key_type
5990 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
5992 /* reg_rrcr_dest_offset
5993 * Offset within the region to which to copy/move
5996 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
5998 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
5999 u16 offset, u16 size,
6000 enum mlxsw_reg_rtar_key_type table_id,
6003 MLXSW_REG_ZERO(rrcr, payload);
6004 mlxsw_reg_rrcr_op_set(payload, op);
6005 mlxsw_reg_rrcr_offset_set(payload, offset);
6006 mlxsw_reg_rrcr_size_set(payload, size);
6007 mlxsw_reg_rrcr_table_id_set(payload, table_id);
6008 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6011 /* RALTA - Router Algorithmic LPM Tree Allocation Register
6012 * -------------------------------------------------------
6013 * RALTA is used to allocate the LPM trees of the SHSPM method.
6015 #define MLXSW_REG_RALTA_ID 0x8010
6016 #define MLXSW_REG_RALTA_LEN 0x04
6018 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6021 * opcode (valid for Write, must be 0 on Read)
6022 * 0 - allocate a tree
6023 * 1 - deallocate a tree
6026 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6028 enum mlxsw_reg_ralxx_protocol {
6029 MLXSW_REG_RALXX_PROTOCOL_IPV4,
6030 MLXSW_REG_RALXX_PROTOCOL_IPV6,
6033 /* reg_ralta_protocol
6035 * Deallocation opcode: Reserved.
6038 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6040 /* reg_ralta_tree_id
6041 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
6042 * the tree identifier (managed by software).
6043 * Note that tree_id 0 is allocated for a default-route tree.
6046 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6048 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6049 enum mlxsw_reg_ralxx_protocol protocol,
6052 MLXSW_REG_ZERO(ralta, payload);
6053 mlxsw_reg_ralta_op_set(payload, !alloc);
6054 mlxsw_reg_ralta_protocol_set(payload, protocol);
6055 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6058 /* RALST - Router Algorithmic LPM Structure Tree Register
6059 * ------------------------------------------------------
6060 * RALST is used to set and query the structure of an LPM tree.
6061 * The structure of the tree must be sorted as a sorted binary tree, while
6062 * each node is a bin that is tagged as the length of the prefixes the lookup
6063 * will refer to. Therefore, bin X refers to a set of entries with prefixes
6064 * of X bits to match with the destination address. The bin 0 indicates
6065 * the default action, when there is no match of any prefix.
6067 #define MLXSW_REG_RALST_ID 0x8011
6068 #define MLXSW_REG_RALST_LEN 0x104
6070 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6072 /* reg_ralst_root_bin
6073 * The bin number of the root bin.
6074 * 0<root_bin=<(length of IP address)
6075 * For a default-route tree configure 0xff
6078 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6080 /* reg_ralst_tree_id
6081 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6084 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6086 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6087 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6088 #define MLXSW_REG_RALST_BIN_COUNT 128
6090 /* reg_ralst_left_child_bin
6091 * Holding the children of the bin according to the stored tree's structure.
6092 * For trees composed of less than 4 blocks, the bins in excess are reserved.
6093 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6096 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6098 /* reg_ralst_right_child_bin
6099 * Holding the children of the bin according to the stored tree's structure.
6100 * For trees composed of less than 4 blocks, the bins in excess are reserved.
6101 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6104 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6107 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6109 MLXSW_REG_ZERO(ralst, payload);
6111 /* Initialize all bins to have no left or right child */
6112 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6113 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6115 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6116 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6119 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6123 int bin_index = bin_number - 1;
6125 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6126 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6130 /* RALTB - Router Algorithmic LPM Tree Binding Register
6131 * ----------------------------------------------------
6132 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6134 #define MLXSW_REG_RALTB_ID 0x8012
6135 #define MLXSW_REG_RALTB_LEN 0x04
6137 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6139 /* reg_raltb_virtual_router
6141 * Range is 0..cap_max_virtual_routers-1
6144 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6146 /* reg_raltb_protocol
6150 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6152 /* reg_raltb_tree_id
6153 * Tree to be used for the {virtual_router, protocol}
6154 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6155 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6158 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6160 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6161 enum mlxsw_reg_ralxx_protocol protocol,
6164 MLXSW_REG_ZERO(raltb, payload);
6165 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6166 mlxsw_reg_raltb_protocol_set(payload, protocol);
6167 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6170 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6171 * -----------------------------------------------------
6172 * RALUE is used to configure and query LPM entries that serve
6173 * the Unicast protocols.
6175 #define MLXSW_REG_RALUE_ID 0x8013
6176 #define MLXSW_REG_RALUE_LEN 0x38
6178 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6180 /* reg_ralue_protocol
6184 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6186 enum mlxsw_reg_ralue_op {
6187 /* Read operation. If entry doesn't exist, the operation fails. */
6188 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6189 /* Clear on read operation. Used to read entry and
6190 * clear Activity bit.
6192 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6193 /* Write operation. Used to write a new entry to the table. All RW
6194 * fields are written for new entry. Activity bit is set
6197 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6198 /* Update operation. Used to update an existing route entry and
6199 * only update the RW fields that are detailed in the field
6200 * op_u_mask. If entry doesn't exist, the operation fails.
6202 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6203 /* Clear activity. The Activity bit (the field a) is cleared
6206 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6207 /* Delete operation. Used to delete an existing entry. If entry
6208 * doesn't exist, the operation fails.
6210 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6217 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6220 * Activity. Set for new entries. Set if a packet lookup has hit on the
6221 * specific entry, only if the entry is a route. To clear the a bit, use
6222 * "clear activity" op.
6223 * Enabled by activity_dis in RGCR
6226 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6228 /* reg_ralue_virtual_router
6230 * Range is 0..cap_max_virtual_routers-1
6233 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6235 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
6236 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
6237 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
6239 /* reg_ralue_op_u_mask
6240 * opcode update mask.
6241 * On read operation, this field is reserved.
6242 * This field is valid for update opcode, otherwise - reserved.
6243 * This field is a bitmask of the fields that should be updated.
6246 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6248 /* reg_ralue_prefix_len
6249 * Number of bits in the prefix of the LPM route.
6250 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6251 * two entries in the physical HW table.
6254 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6257 * The prefix of the route or of the marker that the object of the LPM
6258 * is compared with. The most significant bits of the dip are the prefix.
6259 * The least significant bits must be '0' if the prefix_len is smaller
6260 * than 128 for IPv6 or smaller than 32 for IPv4.
6261 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6264 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6265 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6267 enum mlxsw_reg_ralue_entry_type {
6268 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6269 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6270 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6273 /* reg_ralue_entry_type
6275 * Note - for Marker entries, the action_type and action fields are reserved.
6278 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6280 /* reg_ralue_bmp_len
6281 * The best match prefix length in the case that there is no match for
6283 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6284 * Note for any update operation with entry_type modification this
6285 * field must be set.
6288 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6290 enum mlxsw_reg_ralue_action_type {
6291 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6292 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6293 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6296 /* reg_ralue_action_type
6298 * Indicates how the IP address is connected.
6299 * It can be connected to a local subnet through local_erif or can be
6300 * on a remote subnet connected through a next-hop router,
6301 * or transmitted to the CPU.
6302 * Reserved when entry_type = MARKER_ENTRY
6305 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6307 enum mlxsw_reg_ralue_trap_action {
6308 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6309 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6310 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6311 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6312 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6315 /* reg_ralue_trap_action
6317 * For IP2ME action, only NOP and MIRROR are possible.
6320 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6322 /* reg_ralue_trap_id
6323 * Trap ID to be reported to CPU.
6324 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
6325 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
6328 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6330 /* reg_ralue_adjacency_index
6331 * Points to the first entry of the group-based ECMP.
6332 * Only relevant in case of REMOTE action.
6335 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6337 /* reg_ralue_ecmp_size
6338 * Amount of sequential entries starting
6339 * from the adjacency_index (the number of ECMPs).
6340 * The valid range is 1-64, 512, 1024, 2048 and 4096.
6341 * Reserved when trap_action is TRAP or DISCARD_ERROR.
6342 * Only relevant in case of REMOTE action.
6345 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6347 /* reg_ralue_local_erif
6348 * Egress Router Interface.
6349 * Only relevant in case of LOCAL action.
6352 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6354 /* reg_ralue_ip2me_v
6355 * Valid bit for the tunnel_ptr field.
6356 * If valid = 0 then trap to CPU as IP2ME trap ID.
6357 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
6358 * decapsulation then tunnel decapsulation is done.
6359 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
6360 * decapsulation then trap as IP2ME trap ID.
6361 * Only relevant in case of IP2ME action.
6364 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6366 /* reg_ralue_ip2me_tunnel_ptr
6367 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
6368 * For Spectrum, pointer to KVD Linear.
6369 * Only relevant in case of IP2ME action.
6372 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6374 static inline void mlxsw_reg_ralue_pack(char *payload,
6375 enum mlxsw_reg_ralxx_protocol protocol,
6376 enum mlxsw_reg_ralue_op op,
6377 u16 virtual_router, u8 prefix_len)
6379 MLXSW_REG_ZERO(ralue, payload);
6380 mlxsw_reg_ralue_protocol_set(payload, protocol);
6381 mlxsw_reg_ralue_op_set(payload, op);
6382 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6383 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6384 mlxsw_reg_ralue_entry_type_set(payload,
6385 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6386 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6389 static inline void mlxsw_reg_ralue_pack4(char *payload,
6390 enum mlxsw_reg_ralxx_protocol protocol,
6391 enum mlxsw_reg_ralue_op op,
6392 u16 virtual_router, u8 prefix_len,
6395 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6396 mlxsw_reg_ralue_dip4_set(payload, dip);
6399 static inline void mlxsw_reg_ralue_pack6(char *payload,
6400 enum mlxsw_reg_ralxx_protocol protocol,
6401 enum mlxsw_reg_ralue_op op,
6402 u16 virtual_router, u8 prefix_len,
6405 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6406 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
6410 mlxsw_reg_ralue_act_remote_pack(char *payload,
6411 enum mlxsw_reg_ralue_trap_action trap_action,
6412 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
6414 mlxsw_reg_ralue_action_type_set(payload,
6415 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
6416 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6417 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6418 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
6419 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
6423 mlxsw_reg_ralue_act_local_pack(char *payload,
6424 enum mlxsw_reg_ralue_trap_action trap_action,
6425 u16 trap_id, u16 local_erif)
6427 mlxsw_reg_ralue_action_type_set(payload,
6428 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
6429 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6430 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6431 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
6435 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
6437 mlxsw_reg_ralue_action_type_set(payload,
6438 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6442 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
6444 mlxsw_reg_ralue_action_type_set(payload,
6445 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6446 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
6447 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
6450 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
6451 * ----------------------------------------------------------
6452 * The RAUHT register is used to configure and query the Unicast Host table in
6453 * devices that implement the Algorithmic LPM.
6455 #define MLXSW_REG_RAUHT_ID 0x8014
6456 #define MLXSW_REG_RAUHT_LEN 0x74
6458 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
6460 enum mlxsw_reg_rauht_type {
6461 MLXSW_REG_RAUHT_TYPE_IPV4,
6462 MLXSW_REG_RAUHT_TYPE_IPV6,
6468 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
6470 enum mlxsw_reg_rauht_op {
6471 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
6472 /* Read operation */
6473 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
6474 /* Clear on read operation. Used to read entry and clear
6477 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
6478 /* Add. Used to write a new entry to the table. All R/W fields are
6479 * relevant for new entry. Activity bit is set for new entries.
6481 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
6482 /* Update action. Used to update an existing route entry and
6483 * only update the following fields:
6484 * trap_action, trap_id, mac, counter_set_type, counter_index
6486 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
6487 /* Clear activity. A bit is cleared for the entry. */
6488 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
6490 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
6491 /* Delete all host entries on a RIF. In this command, dip
6492 * field is reserved.
6499 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
6502 * Activity. Set for new entries. Set if a packet lookup has hit on
6503 * the specific entry.
6504 * To clear the a bit, use "clear activity" op.
6505 * Enabled by activity_dis in RGCR
6508 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
6514 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
6517 * Destination address.
6520 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
6521 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
6523 enum mlxsw_reg_rauht_trap_action {
6524 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
6525 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
6526 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
6527 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
6528 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
6531 /* reg_rauht_trap_action
6534 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
6536 enum mlxsw_reg_rauht_trap_id {
6537 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
6538 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
6541 /* reg_rauht_trap_id
6542 * Trap ID to be reported to CPU.
6543 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6544 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
6545 * trap_id is reserved.
6548 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
6550 /* reg_rauht_counter_set_type
6551 * Counter set type for flow counters
6554 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
6556 /* reg_rauht_counter_index
6557 * Counter index for flow counters
6560 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
6566 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
6568 static inline void mlxsw_reg_rauht_pack(char *payload,
6569 enum mlxsw_reg_rauht_op op, u16 rif,
6572 MLXSW_REG_ZERO(rauht, payload);
6573 mlxsw_reg_rauht_op_set(payload, op);
6574 mlxsw_reg_rauht_rif_set(payload, rif);
6575 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
6578 static inline void mlxsw_reg_rauht_pack4(char *payload,
6579 enum mlxsw_reg_rauht_op op, u16 rif,
6580 const char *mac, u32 dip)
6582 mlxsw_reg_rauht_pack(payload, op, rif, mac);
6583 mlxsw_reg_rauht_dip4_set(payload, dip);
6586 static inline void mlxsw_reg_rauht_pack6(char *payload,
6587 enum mlxsw_reg_rauht_op op, u16 rif,
6588 const char *mac, const char *dip)
6590 mlxsw_reg_rauht_pack(payload, op, rif, mac);
6591 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
6592 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
6595 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
6598 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
6599 mlxsw_reg_rauht_counter_set_type_set(payload,
6600 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
6603 /* RALEU - Router Algorithmic LPM ECMP Update Register
6604 * ---------------------------------------------------
6605 * The register enables updating the ECMP section in the action for multiple
6606 * LPM Unicast entries in a single operation. The update is executed to
6607 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
6609 #define MLXSW_REG_RALEU_ID 0x8015
6610 #define MLXSW_REG_RALEU_LEN 0x28
6612 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
6614 /* reg_raleu_protocol
6618 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
6620 /* reg_raleu_virtual_router
6622 * Range is 0..cap_max_virtual_routers-1
6625 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
6627 /* reg_raleu_adjacency_index
6628 * Adjacency Index used for matching on the existing entries.
6631 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
6633 /* reg_raleu_ecmp_size
6634 * ECMP Size used for matching on the existing entries.
6637 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
6639 /* reg_raleu_new_adjacency_index
6640 * New Adjacency Index.
6643 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
6645 /* reg_raleu_new_ecmp_size
6649 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
6651 static inline void mlxsw_reg_raleu_pack(char *payload,
6652 enum mlxsw_reg_ralxx_protocol protocol,
6654 u32 adjacency_index, u16 ecmp_size,
6655 u32 new_adjacency_index,
6658 MLXSW_REG_ZERO(raleu, payload);
6659 mlxsw_reg_raleu_protocol_set(payload, protocol);
6660 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
6661 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
6662 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
6663 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
6664 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
6667 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
6668 * ----------------------------------------------------------------
6669 * The RAUHTD register allows dumping entries from the Router Unicast Host
6670 * Table. For a given session an entry is dumped no more than one time. The
6671 * first RAUHTD access after reset is a new session. A session ends when the
6672 * num_rec response is smaller than num_rec request or for IPv4 when the
6673 * num_entries is smaller than 4. The clear activity affect the current session
6674 * or the last session if a new session has not started.
6676 #define MLXSW_REG_RAUHTD_ID 0x8018
6677 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
6678 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
6679 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
6680 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
6681 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
6682 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
6684 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
6686 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
6687 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
6689 /* reg_rauhtd_filter_fields
6690 * if a bit is '0' then the relevant field is ignored and dump is done
6691 * regardless of the field value
6692 * Bit0 - filter by activity: entry_a
6693 * Bit3 - filter by entry rip: entry_rif
6696 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
6698 enum mlxsw_reg_rauhtd_op {
6699 MLXSW_REG_RAUHTD_OP_DUMP,
6700 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
6706 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
6708 /* reg_rauhtd_num_rec
6709 * At request: number of records requested
6710 * At response: number of records dumped
6711 * For IPv4, each record has 4 entries at request and up to 4 entries
6713 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
6716 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
6718 /* reg_rauhtd_entry_a
6719 * Dump only if activity has value of entry_a
6720 * Reserved if filter_fields bit0 is '0'
6723 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
6725 enum mlxsw_reg_rauhtd_type {
6726 MLXSW_REG_RAUHTD_TYPE_IPV4,
6727 MLXSW_REG_RAUHTD_TYPE_IPV6,
6731 * Dump only if record type is:
6736 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
6738 /* reg_rauhtd_entry_rif
6739 * Dump only if RIF has value of entry_rif
6740 * Reserved if filter_fields bit3 is '0'
6743 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
6745 static inline void mlxsw_reg_rauhtd_pack(char *payload,
6746 enum mlxsw_reg_rauhtd_type type)
6748 MLXSW_REG_ZERO(rauhtd, payload);
6749 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
6750 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
6751 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
6752 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
6753 mlxsw_reg_rauhtd_type_set(payload, type);
6756 /* reg_rauhtd_ipv4_rec_num_entries
6757 * Number of valid entries in this record:
6759 * 1 - 2 valid entries
6760 * 2 - 3 valid entries
6761 * 3 - 4 valid entries
6764 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
6765 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
6766 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
6768 /* reg_rauhtd_rec_type
6774 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
6775 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
6777 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
6779 /* reg_rauhtd_ipv4_ent_a
6780 * Activity. Set for new entries. Set if a packet lookup has hit on the
6784 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
6785 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
6787 /* reg_rauhtd_ipv4_ent_rif
6791 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6792 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
6794 /* reg_rauhtd_ipv4_ent_dip
6795 * Destination IPv4 address.
6798 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6799 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
6801 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
6803 /* reg_rauhtd_ipv6_ent_a
6804 * Activity. Set for new entries. Set if a packet lookup has hit on the
6808 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
6809 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
6811 /* reg_rauhtd_ipv6_ent_rif
6815 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6816 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
6818 /* reg_rauhtd_ipv6_ent_dip
6819 * Destination IPv6 address.
6822 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
6823 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
6825 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
6826 int ent_index, u16 *p_rif,
6829 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
6830 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
6833 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
6834 int rec_index, u16 *p_rif,
6837 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
6838 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
6841 /* RTDP - Routing Tunnel Decap Properties Register
6842 * -----------------------------------------------
6843 * The RTDP register is used for configuring the tunnel decap properties of NVE
6846 #define MLXSW_REG_RTDP_ID 0x8020
6847 #define MLXSW_REG_RTDP_LEN 0x44
6849 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
6851 enum mlxsw_reg_rtdp_type {
6852 MLXSW_REG_RTDP_TYPE_NVE,
6853 MLXSW_REG_RTDP_TYPE_IPIP,
6857 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
6860 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
6862 /* reg_rtdp_tunnel_index
6863 * Index to the Decap entry.
6864 * For Spectrum, Index to KVD Linear.
6867 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
6871 /* reg_rtdp_ipip_irif
6872 * Ingress Router Interface for the overlay router
6875 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
6877 enum mlxsw_reg_rtdp_ipip_sip_check {
6878 /* No sip checks. */
6879 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
6880 /* Filter packet if underlay is not IPv4 or if underlay SIP does not
6883 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
6884 /* Filter packet if underlay is not IPv6 or if underlay SIP does not
6887 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
6890 /* reg_rtdp_ipip_sip_check
6891 * SIP check to perform. If decapsulation failed due to these configurations
6892 * then trap_id is IPIP_DECAP_ERROR.
6895 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
6897 /* If set, allow decapsulation of IPinIP (without GRE). */
6898 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
6899 /* If set, allow decapsulation of IPinGREinIP without a key. */
6900 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
6901 /* If set, allow decapsulation of IPinGREinIP with a key. */
6902 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
6904 /* reg_rtdp_ipip_type_check
6905 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
6906 * these configurations then trap_id is IPIP_DECAP_ERROR.
6909 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
6911 /* reg_rtdp_ipip_gre_key_check
6912 * Whether GRE key should be checked. When check is enabled:
6913 * - A packet received as IPinIP (without GRE) will always pass.
6914 * - A packet received as IPinGREinIP without a key will not pass the check.
6915 * - A packet received as IPinGREinIP with a key will pass the check only if the
6916 * key in the packet is equal to expected_gre_key.
6917 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
6920 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
6922 /* reg_rtdp_ipip_ipv4_usip
6923 * Underlay IPv4 address for ipv4 source address check.
6924 * Reserved when sip_check is not '1'.
6927 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
6929 /* reg_rtdp_ipip_ipv6_usip_ptr
6930 * This field is valid when sip_check is "sipv6 check explicitly". This is a
6931 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
6932 * is to the KVD linear.
6933 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
6936 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
6938 /* reg_rtdp_ipip_expected_gre_key
6939 * GRE key for checking.
6940 * Reserved when gre_key_check is '0'.
6943 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
6945 static inline void mlxsw_reg_rtdp_pack(char *payload,
6946 enum mlxsw_reg_rtdp_type type,
6949 MLXSW_REG_ZERO(rtdp, payload);
6950 mlxsw_reg_rtdp_type_set(payload, type);
6951 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
6955 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
6956 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
6957 unsigned int type_check, bool gre_key_check,
6958 u32 ipv4_usip, u32 expected_gre_key)
6960 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
6961 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
6962 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
6963 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
6964 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
6965 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
6968 /* RIGR-V2 - Router Interface Group Register Version 2
6969 * ---------------------------------------------------
6970 * The RIGR_V2 register is used to add, remove and query egress interface list
6971 * of a multicast forwarding entry.
6973 #define MLXSW_REG_RIGR2_ID 0x8023
6974 #define MLXSW_REG_RIGR2_LEN 0xB0
6976 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
6978 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
6980 /* reg_rigr2_rigr_index
6984 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
6987 * Next RIGR Index is valid.
6990 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
6992 /* reg_rigr2_next_rigr_index
6993 * Next RIGR Index. The index is to the KVD linear.
6994 * Reserved when vnxet = '0'.
6997 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7000 * RMID Index is valid.
7003 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7005 /* reg_rigr2_rmid_index
7007 * Range 0 .. max_mid - 1
7008 * Reserved when vrmid = '0'.
7009 * The index is to the Port Group Table (PGT)
7012 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7014 /* reg_rigr2_erif_entry_v
7015 * Egress Router Interface is valid.
7016 * Note that low-entries must be set if high-entries are set. For
7017 * example: if erif_entry[2].v is set then erif_entry[1].v and
7018 * erif_entry[0].v must be set.
7019 * Index can be from 0 to cap_mc_erif_list_entries-1
7022 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7024 /* reg_rigr2_erif_entry_erif
7025 * Egress Router Interface.
7026 * Valid range is from 0 to cap_max_router_interfaces - 1
7027 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
7030 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7032 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7033 bool vnext, u32 next_rigr_index)
7035 MLXSW_REG_ZERO(rigr2, payload);
7036 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7037 mlxsw_reg_rigr2_vnext_set(payload, vnext);
7038 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7039 mlxsw_reg_rigr2_vrmid_set(payload, 0);
7040 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7043 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7046 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7047 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7050 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7051 * ------------------------------------------------------
7053 #define MLXSW_REG_RECR2_ID 0x8025
7054 #define MLXSW_REG_RECR2_LEN 0x38
7056 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7059 * Per-port configuration
7062 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7068 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7074 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7077 /* Enable IPv4 fields if packet is not TCP and not UDP */
7078 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7079 /* Enable IPv4 fields if packet is TCP or UDP */
7080 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
7081 /* Enable IPv6 fields if packet is not TCP and not UDP */
7082 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7083 /* Enable IPv6 fields if packet is TCP or UDP */
7084 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
7085 /* Enable TCP/UDP header fields if packet is IPv4 */
7086 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
7087 /* Enable TCP/UDP header fields if packet is IPv6 */
7088 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
7091 /* reg_recr2_outer_header_enables
7092 * Bit mask where each bit enables a specific layer to be included in
7093 * the hash calculation.
7096 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7099 /* IPv4 Source IP */
7100 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
7101 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
7102 /* IPv4 Destination IP */
7103 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
7104 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
7106 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
7107 /* IPv6 Source IP */
7108 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
7109 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
7110 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
7111 /* IPv6 Destination IP */
7112 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
7113 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
7114 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
7115 /* IPv6 Next Header */
7116 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
7117 /* IPv6 Flow Label */
7118 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
7119 /* TCP/UDP Source Port */
7120 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
7121 /* TCP/UDP Destination Port */
7122 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
7125 /* reg_recr2_outer_header_fields_enable
7126 * Packet fields to enable for ECMP hash subject to outer_header_enable.
7129 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7131 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7135 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7136 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7140 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7144 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7145 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7149 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7151 int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7153 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7155 i = MLXSW_REG_RECR2_IPV6_SIP8;
7156 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7157 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7161 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7163 int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7165 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7167 i = MLXSW_REG_RECR2_IPV6_DIP8;
7168 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7169 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7173 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7175 MLXSW_REG_ZERO(recr2, payload);
7176 mlxsw_reg_recr2_pp_set(payload, false);
7177 mlxsw_reg_recr2_sh_set(payload, true);
7178 mlxsw_reg_recr2_seed_set(payload, seed);
7181 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7182 * --------------------------------------------------------------
7183 * The RMFT_V2 register is used to configure and query the multicast table.
7185 #define MLXSW_REG_RMFT2_ID 0x8027
7186 #define MLXSW_REG_RMFT2_LEN 0x174
7188 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7194 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7196 enum mlxsw_reg_rmft2_type {
7197 MLXSW_REG_RMFT2_TYPE_IPV4,
7198 MLXSW_REG_RMFT2_TYPE_IPV6
7204 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7206 enum mlxsw_sp_reg_rmft2_op {
7208 * Write operation. Used to write a new entry to the table. All RW
7209 * fields are relevant for new entry. Activity bit is set for new
7210 * entries - Note write with v (Valid) 0 will delete the entry.
7214 MLXSW_REG_RMFT2_OP_READ_WRITE,
7221 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7224 * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7228 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7231 * Offset within the multicast forwarding table to write to.
7234 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7236 /* reg_rmft2_virtual_router
7237 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7240 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7242 enum mlxsw_reg_rmft2_irif_mask {
7243 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7244 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7247 /* reg_rmft2_irif_mask
7251 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7254 * Ingress RIF index.
7257 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7259 /* reg_rmft2_dip{4,6}
7260 * Destination IPv4/6 address
7263 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7264 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7266 /* reg_rmft2_dip{4,6}_mask
7267 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7268 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7271 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7272 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7274 /* reg_rmft2_sip{4,6}
7275 * Source IPv4/6 address
7278 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7279 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7281 /* reg_rmft2_sip{4,6}_mask
7282 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7283 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7286 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7287 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7289 /* reg_rmft2_flexible_action_set
7290 * ACL action set. The only supported action types in this field and in any
7291 * action-set pointed from here are as follows:
7293 * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
7296 * 08h: ACTION_POLICING_MONITORING
7297 * 10h: ACTION_ROUTER_MC
7300 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7301 MLXSW_REG_FLEX_ACTION_SET_LEN);
7304 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7306 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7307 const char *flex_action_set)
7309 MLXSW_REG_ZERO(rmft2, payload);
7310 mlxsw_reg_rmft2_v_set(payload, v);
7311 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7312 mlxsw_reg_rmft2_offset_set(payload, offset);
7313 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7314 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7315 mlxsw_reg_rmft2_irif_set(payload, irif);
7316 if (flex_action_set)
7317 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7322 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7323 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7324 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7325 const char *flexible_action_set)
7327 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7328 irif_mask, irif, flexible_action_set);
7329 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7330 mlxsw_reg_rmft2_dip4_set(payload, dip4);
7331 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7332 mlxsw_reg_rmft2_sip4_set(payload, sip4);
7333 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7337 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7338 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7339 struct in6_addr dip6, struct in6_addr dip6_mask,
7340 struct in6_addr sip6, struct in6_addr sip6_mask,
7341 const char *flexible_action_set)
7343 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7344 irif_mask, irif, flexible_action_set);
7345 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7346 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7347 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7348 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7349 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7352 /* MFCR - Management Fan Control Register
7353 * --------------------------------------
7354 * This register controls the settings of the Fan Speed PWM mechanism.
7356 #define MLXSW_REG_MFCR_ID 0x9001
7357 #define MLXSW_REG_MFCR_LEN 0x08
7359 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7361 enum mlxsw_reg_mfcr_pwm_frequency {
7362 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7363 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7364 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7365 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7366 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7367 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7368 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7369 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7372 /* reg_mfcr_pwm_frequency
7373 * Controls the frequency of the PWM signal.
7376 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7378 #define MLXSW_MFCR_TACHOS_MAX 10
7380 /* reg_mfcr_tacho_active
7381 * Indicates which of the tachometer is active (bit per tachometer).
7384 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7386 #define MLXSW_MFCR_PWMS_MAX 5
7388 /* reg_mfcr_pwm_active
7389 * Indicates which of the PWM control is active (bit per PWM).
7392 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
7395 mlxsw_reg_mfcr_pack(char *payload,
7396 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
7398 MLXSW_REG_ZERO(mfcr, payload);
7399 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
7403 mlxsw_reg_mfcr_unpack(char *payload,
7404 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
7405 u16 *p_tacho_active, u8 *p_pwm_active)
7407 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
7408 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
7409 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
7412 /* MFSC - Management Fan Speed Control Register
7413 * --------------------------------------------
7414 * This register controls the settings of the Fan Speed PWM mechanism.
7416 #define MLXSW_REG_MFSC_ID 0x9002
7417 #define MLXSW_REG_MFSC_LEN 0x08
7419 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
7422 * Fan pwm to control / monitor.
7425 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
7427 /* reg_mfsc_pwm_duty_cycle
7428 * Controls the duty cycle of the PWM. Value range from 0..255 to
7429 * represent duty cycle of 0%...100%.
7432 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
7434 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
7437 MLXSW_REG_ZERO(mfsc, payload);
7438 mlxsw_reg_mfsc_pwm_set(payload, pwm);
7439 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
7442 /* MFSM - Management Fan Speed Measurement
7443 * ---------------------------------------
7444 * This register controls the settings of the Tacho measurements and
7445 * enables reading the Tachometer measurements.
7447 #define MLXSW_REG_MFSM_ID 0x9003
7448 #define MLXSW_REG_MFSM_LEN 0x08
7450 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
7453 * Fan tachometer index.
7456 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
7459 * Fan speed (round per minute).
7462 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
7464 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
7466 MLXSW_REG_ZERO(mfsm, payload);
7467 mlxsw_reg_mfsm_tacho_set(payload, tacho);
7470 /* MFSL - Management Fan Speed Limit Register
7471 * ------------------------------------------
7472 * The Fan Speed Limit register is used to configure the fan speed
7473 * event / interrupt notification mechanism. Fan speed threshold are
7474 * defined for both under-speed and over-speed.
7476 #define MLXSW_REG_MFSL_ID 0x9004
7477 #define MLXSW_REG_MFSL_LEN 0x0C
7479 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
7482 * Fan tachometer index.
7485 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
7487 /* reg_mfsl_tach_min
7488 * Tachometer minimum value (minimum RPM).
7491 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
7493 /* reg_mfsl_tach_max
7494 * Tachometer maximum value (maximum RPM).
7497 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
7499 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
7500 u16 tach_min, u16 tach_max)
7502 MLXSW_REG_ZERO(mfsl, payload);
7503 mlxsw_reg_mfsl_tacho_set(payload, tacho);
7504 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
7505 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
7508 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
7509 u16 *p_tach_min, u16 *p_tach_max)
7512 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
7515 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
7518 /* MTCAP - Management Temperature Capabilities
7519 * -------------------------------------------
7520 * This register exposes the capabilities of the device and
7521 * system temperature sensing.
7523 #define MLXSW_REG_MTCAP_ID 0x9009
7524 #define MLXSW_REG_MTCAP_LEN 0x08
7526 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
7528 /* reg_mtcap_sensor_count
7529 * Number of sensors supported by the device.
7530 * This includes the QSFP module sensors (if exists in the QSFP module).
7533 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
7535 /* MTMP - Management Temperature
7536 * -----------------------------
7537 * This register controls the settings of the temperature measurements
7538 * and enables reading the temperature measurements. Note that temperature
7539 * is in 0.125 degrees Celsius.
7541 #define MLXSW_REG_MTMP_ID 0x900A
7542 #define MLXSW_REG_MTMP_LEN 0x20
7544 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
7546 /* reg_mtmp_sensor_index
7547 * Sensors index to access.
7548 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
7549 * (module 0 is mapped to sensor_index 64).
7552 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
7554 /* Convert to milli degrees Celsius */
7555 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
7557 /* reg_mtmp_temperature
7558 * Temperature reading from the sensor. Reading is in 0.125 Celsius
7562 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
7565 * Max Temperature Enable - enables measuring the max temperature on a sensor.
7568 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
7571 * Max Temperature Reset - clears the value of the max temperature register.
7574 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
7576 /* reg_mtmp_max_temperature
7577 * The highest measured temperature from the sensor.
7578 * When the bit mte is cleared, the field max_temperature is reserved.
7581 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
7584 * Temperature Event Enable.
7585 * 0 - Do not generate event
7586 * 1 - Generate event
7587 * 2 - Generate single event
7590 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
7592 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */
7594 /* reg_mtmp_temperature_threshold_hi
7595 * High threshold for Temperature Warning Event. In 0.125 Celsius.
7598 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
7600 /* reg_mtmp_temperature_threshold_lo
7601 * Low threshold for Temperature Warning Event. In 0.125 Celsius.
7604 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
7606 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
7608 /* reg_mtmp_sensor_name
7612 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
7614 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
7615 bool max_temp_enable,
7616 bool max_temp_reset)
7618 MLXSW_REG_ZERO(mtmp, payload);
7619 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
7620 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
7621 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
7622 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
7623 MLXSW_REG_MTMP_THRESH_HI);
7626 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
7627 unsigned int *p_max_temp,
7633 temp = mlxsw_reg_mtmp_temperature_get(payload);
7634 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
7637 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
7638 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
7641 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
7644 /* MCIA - Management Cable Info Access
7645 * -----------------------------------
7646 * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
7649 #define MLXSW_REG_MCIA_ID 0x9014
7650 #define MLXSW_REG_MCIA_LEN 0x40
7652 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
7655 * Lock bit. Setting this bit will lock the access to the specific
7656 * cable. Used for updating a full page in a cable EPROM. Any access
7657 * other then subsequence writes will fail while the port is locked.
7660 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
7666 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
7672 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
7674 /* reg_mcia_i2c_device_address
7675 * I2C device address.
7678 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
7680 /* reg_mcia_page_number
7684 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
7686 /* reg_mcia_device_address
7690 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
7693 * Number of bytes to read/write (up to 48 bytes).
7696 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
7698 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48
7701 * Bytes to read/write.
7704 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
7706 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
7707 u8 page_number, u16 device_addr,
7708 u8 size, u8 i2c_device_addr)
7710 MLXSW_REG_ZERO(mcia, payload);
7711 mlxsw_reg_mcia_module_set(payload, module);
7712 mlxsw_reg_mcia_l_set(payload, lock);
7713 mlxsw_reg_mcia_page_number_set(payload, page_number);
7714 mlxsw_reg_mcia_device_address_set(payload, device_addr);
7715 mlxsw_reg_mcia_size_set(payload, size);
7716 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
7719 /* MPAT - Monitoring Port Analyzer Table
7720 * -------------------------------------
7721 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
7722 * For an enabled analyzer, all fields except e (enable) cannot be modified.
7724 #define MLXSW_REG_MPAT_ID 0x901A
7725 #define MLXSW_REG_MPAT_LEN 0x78
7727 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
7733 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
7735 /* reg_mpat_system_port
7736 * A unique port identifier for the final destination of the packet.
7739 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
7742 * Enable. Indicating the Port Analyzer is enabled.
7745 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
7748 * Quality Of Service Mode.
7749 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
7750 * PCP, DEI, DSCP or VL) are configured.
7751 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
7752 * same as in the original packet that has triggered the mirroring. For
7753 * SPAN also the pcp,dei are maintained.
7756 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
7759 * Best effort mode. Indicates mirroring traffic should not cause packet
7760 * drop or back pressure, but will discard the mirrored packets. Mirrored
7761 * packets will be forwarded on a best effort manner.
7762 * 0: Do not discard mirrored packets
7763 * 1: Discard mirrored packets if causing congestion
7766 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
7768 enum mlxsw_reg_mpat_span_type {
7769 /* Local SPAN Ethernet.
7770 * The original packet is not encapsulated.
7772 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
7774 /* Remote SPAN Ethernet VLAN.
7775 * The packet is forwarded to the monitoring port on the monitoring
7778 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
7780 /* Encapsulated Remote SPAN Ethernet L3 GRE.
7781 * The packet is encapsulated with GRE header.
7783 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
7786 /* reg_mpat_span_type
7790 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
7792 /* Remote SPAN - Ethernet VLAN
7793 * - - - - - - - - - - - - - -
7796 /* reg_mpat_eth_rspan_vid
7797 * Encapsulation header VLAN ID.
7800 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
7802 /* Encapsulated Remote SPAN - Ethernet L2
7803 * - - - - - - - - - - - - - - - - - - -
7806 enum mlxsw_reg_mpat_eth_rspan_version {
7807 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
7810 /* reg_mpat_eth_rspan_version
7811 * RSPAN mirror header version.
7814 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
7816 /* reg_mpat_eth_rspan_mac
7817 * Destination MAC address.
7820 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
7822 /* reg_mpat_eth_rspan_tp
7823 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
7826 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
7828 /* Encapsulated Remote SPAN - Ethernet L3
7829 * - - - - - - - - - - - - - - - - - - -
7832 enum mlxsw_reg_mpat_eth_rspan_protocol {
7833 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
7834 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
7837 /* reg_mpat_eth_rspan_protocol
7838 * SPAN encapsulation protocol.
7841 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
7843 /* reg_mpat_eth_rspan_ttl
7844 * Encapsulation header Time-to-Live/HopLimit.
7847 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
7849 /* reg_mpat_eth_rspan_smac
7850 * Source MAC address
7853 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
7855 /* reg_mpat_eth_rspan_dip*
7856 * Destination IP address. The IP version is configured by protocol.
7859 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
7860 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
7862 /* reg_mpat_eth_rspan_sip*
7863 * Source IP address. The IP version is configured by protocol.
7866 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
7867 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
7869 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
7870 u16 system_port, bool e,
7871 enum mlxsw_reg_mpat_span_type span_type)
7873 MLXSW_REG_ZERO(mpat, payload);
7874 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
7875 mlxsw_reg_mpat_system_port_set(payload, system_port);
7876 mlxsw_reg_mpat_e_set(payload, e);
7877 mlxsw_reg_mpat_qos_set(payload, 1);
7878 mlxsw_reg_mpat_be_set(payload, 1);
7879 mlxsw_reg_mpat_span_type_set(payload, span_type);
7882 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
7884 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
7888 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
7889 enum mlxsw_reg_mpat_eth_rspan_version version,
7893 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
7894 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
7895 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
7899 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
7903 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
7904 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
7905 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
7906 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
7907 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
7908 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
7912 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
7914 struct in6_addr sip, struct in6_addr dip)
7916 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
7917 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
7918 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
7919 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
7920 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
7921 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
7924 /* MPAR - Monitoring Port Analyzer Register
7925 * ----------------------------------------
7926 * MPAR register is used to query and configure the port analyzer port mirroring
7929 #define MLXSW_REG_MPAR_ID 0x901B
7930 #define MLXSW_REG_MPAR_LEN 0x08
7932 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
7934 /* reg_mpar_local_port
7935 * The local port to mirror the packets from.
7938 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
7940 enum mlxsw_reg_mpar_i_e {
7941 MLXSW_REG_MPAR_TYPE_EGRESS,
7942 MLXSW_REG_MPAR_TYPE_INGRESS,
7949 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
7953 * By default, port mirroring is disabled for all ports.
7956 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
7962 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
7964 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
7965 enum mlxsw_reg_mpar_i_e i_e,
7966 bool enable, u8 pa_id)
7968 MLXSW_REG_ZERO(mpar, payload);
7969 mlxsw_reg_mpar_local_port_set(payload, local_port);
7970 mlxsw_reg_mpar_enable_set(payload, enable);
7971 mlxsw_reg_mpar_i_e_set(payload, i_e);
7972 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
7975 /* MRSR - Management Reset and Shutdown Register
7976 * ---------------------------------------------
7977 * MRSR register is used to reset or shutdown the switch or
7978 * the entire system (when applicable).
7980 #define MLXSW_REG_MRSR_ID 0x9023
7981 #define MLXSW_REG_MRSR_LEN 0x08
7983 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
7986 * Reset/shutdown command
7988 * 1 - software reset
7991 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
7993 static inline void mlxsw_reg_mrsr_pack(char *payload)
7995 MLXSW_REG_ZERO(mrsr, payload);
7996 mlxsw_reg_mrsr_command_set(payload, 1);
7999 /* MLCR - Management LED Control Register
8000 * --------------------------------------
8001 * Controls the system LEDs.
8003 #define MLXSW_REG_MLCR_ID 0x902B
8004 #define MLXSW_REG_MLCR_LEN 0x0C
8006 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8008 /* reg_mlcr_local_port
8009 * Local port number.
8012 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8014 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8016 /* reg_mlcr_beacon_duration
8017 * Duration of the beacon to be active, in seconds.
8018 * 0x0 - Will turn off the beacon.
8019 * 0xFFFF - Will turn on the beacon until explicitly turned off.
8022 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8024 /* reg_mlcr_beacon_remain
8025 * Remaining duration of the beacon, in seconds.
8026 * 0xFFFF indicates an infinite amount of time.
8029 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8031 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8034 MLXSW_REG_ZERO(mlcr, payload);
8035 mlxsw_reg_mlcr_local_port_set(payload, local_port);
8036 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8037 MLXSW_REG_MLCR_DURATION_MAX : 0);
8040 /* MCQI - Management Component Query Information
8041 * ---------------------------------------------
8042 * This register allows querying information about firmware components.
8044 #define MLXSW_REG_MCQI_ID 0x9061
8045 #define MLXSW_REG_MCQI_BASE_LEN 0x18
8046 #define MLXSW_REG_MCQI_CAP_LEN 0x14
8047 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8049 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8051 /* reg_mcqi_component_index
8052 * Index of the accessed component.
8055 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8057 enum mlxfw_reg_mcqi_info_type {
8058 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8061 /* reg_mcqi_info_type
8062 * Component properties set.
8065 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8068 * The requested/returned data offset from the section start, given in bytes.
8069 * Must be DWORD aligned.
8072 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8074 /* reg_mcqi_data_size
8075 * The requested/returned data size, given in bytes. If data_size is not DWORD
8076 * aligned, the last bytes are zero padded.
8079 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8081 /* reg_mcqi_cap_max_component_size
8082 * Maximum size for this component, given in bytes.
8085 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8087 /* reg_mcqi_cap_log_mcda_word_size
8088 * Log 2 of the access word size in bytes. Read and write access must be aligned
8089 * to the word size. Write access must be done for an integer number of words.
8092 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8094 /* reg_mcqi_cap_mcda_max_write_size
8095 * Maximal write size for MCDA register
8098 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8100 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
8102 MLXSW_REG_ZERO(mcqi, payload);
8103 mlxsw_reg_mcqi_component_index_set(payload, component_index);
8104 mlxsw_reg_mcqi_info_type_set(payload,
8105 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
8106 mlxsw_reg_mcqi_offset_set(payload, 0);
8107 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
8110 static inline void mlxsw_reg_mcqi_unpack(char *payload,
8111 u32 *p_cap_max_component_size,
8112 u8 *p_cap_log_mcda_word_size,
8113 u16 *p_cap_mcda_max_write_size)
8115 *p_cap_max_component_size =
8116 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
8117 *p_cap_log_mcda_word_size =
8118 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
8119 *p_cap_mcda_max_write_size =
8120 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
8123 /* MCC - Management Component Control
8124 * ----------------------------------
8125 * Controls the firmware component and updates the FSM.
8127 #define MLXSW_REG_MCC_ID 0x9062
8128 #define MLXSW_REG_MCC_LEN 0x1C
8130 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
8132 enum mlxsw_reg_mcc_instruction {
8133 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
8134 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
8135 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
8136 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
8137 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
8138 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
8141 /* reg_mcc_instruction
8142 * Command to be executed by the FSM.
8143 * Applicable for write operation only.
8146 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
8148 /* reg_mcc_component_index
8149 * Index of the accessed component. Applicable only for commands that
8150 * refer to components. Otherwise, this field is reserved.
8153 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
8155 /* reg_mcc_update_handle
8156 * Token representing the current flow executed by the FSM.
8159 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
8161 /* reg_mcc_error_code
8162 * Indicates the successful completion of the instruction, or the reason it
8166 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
8168 /* reg_mcc_control_state
8172 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
8174 /* reg_mcc_component_size
8175 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
8176 * the size may shorten the update time. Value 0x0 means that size is
8180 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
8182 static inline void mlxsw_reg_mcc_pack(char *payload,
8183 enum mlxsw_reg_mcc_instruction instr,
8184 u16 component_index, u32 update_handle,
8187 MLXSW_REG_ZERO(mcc, payload);
8188 mlxsw_reg_mcc_instruction_set(payload, instr);
8189 mlxsw_reg_mcc_component_index_set(payload, component_index);
8190 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
8191 mlxsw_reg_mcc_component_size_set(payload, component_size);
8194 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
8195 u8 *p_error_code, u8 *p_control_state)
8197 if (p_update_handle)
8198 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
8200 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
8201 if (p_control_state)
8202 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
8205 /* MCDA - Management Component Data Access
8206 * ---------------------------------------
8207 * This register allows reading and writing a firmware component.
8209 #define MLXSW_REG_MCDA_ID 0x9063
8210 #define MLXSW_REG_MCDA_BASE_LEN 0x10
8211 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
8212 #define MLXSW_REG_MCDA_LEN \
8213 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
8215 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
8217 /* reg_mcda_update_handle
8218 * Token representing the current flow executed by the FSM.
8221 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
8224 * Offset of accessed address relative to component start. Accesses must be in
8225 * accordance to log_mcda_word_size in MCQI reg.
8228 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
8231 * Size of the data accessed, given in bytes.
8234 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
8237 * Data block accessed.
8240 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
8242 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
8243 u32 offset, u16 size, u8 *data)
8247 MLXSW_REG_ZERO(mcda, payload);
8248 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
8249 mlxsw_reg_mcda_offset_set(payload, offset);
8250 mlxsw_reg_mcda_size_set(payload, size);
8252 for (i = 0; i < size / 4; i++)
8253 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
8256 /* MPSC - Monitoring Packet Sampling Configuration Register
8257 * --------------------------------------------------------
8258 * MPSC Register is used to configure the Packet Sampling mechanism.
8260 #define MLXSW_REG_MPSC_ID 0x9080
8261 #define MLXSW_REG_MPSC_LEN 0x1C
8263 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
8265 /* reg_mpsc_local_port
8267 * Not supported for CPU port
8270 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
8273 * Enable sampling on port local_port
8276 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
8278 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
8281 * Sampling rate = 1 out of rate packets (with randomization around
8282 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
8285 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
8287 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
8290 MLXSW_REG_ZERO(mpsc, payload);
8291 mlxsw_reg_mpsc_local_port_set(payload, local_port);
8292 mlxsw_reg_mpsc_e_set(payload, e);
8293 mlxsw_reg_mpsc_rate_set(payload, rate);
8296 /* MGPC - Monitoring General Purpose Counter Set Register
8297 * The MGPC register retrieves and sets the General Purpose Counter Set.
8299 #define MLXSW_REG_MGPC_ID 0x9081
8300 #define MLXSW_REG_MGPC_LEN 0x18
8302 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
8304 /* reg_mgpc_counter_set_type
8308 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
8310 /* reg_mgpc_counter_index
8314 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
8316 enum mlxsw_reg_mgpc_opcode {
8318 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
8319 /* Clear counters */
8320 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
8327 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
8329 /* reg_mgpc_byte_counter
8330 * Byte counter value.
8333 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
8335 /* reg_mgpc_packet_counter
8336 * Packet counter value.
8339 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
8341 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
8342 enum mlxsw_reg_mgpc_opcode opcode,
8343 enum mlxsw_reg_flow_counter_set_type set_type)
8345 MLXSW_REG_ZERO(mgpc, payload);
8346 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
8347 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
8348 mlxsw_reg_mgpc_opcode_set(payload, opcode);
8351 /* MPRS - Monitoring Parsing State Register
8352 * ----------------------------------------
8353 * The MPRS register is used for setting up the parsing for hash,
8354 * policy-engine and routing.
8356 #define MLXSW_REG_MPRS_ID 0x9083
8357 #define MLXSW_REG_MPRS_LEN 0x14
8359 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
8361 /* reg_mprs_parsing_depth
8362 * Minimum parsing depth.
8363 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
8364 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
8367 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
8369 /* reg_mprs_parsing_en
8371 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
8372 * NVGRE. Default is enabled. Reserved when SwitchX-2.
8375 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
8377 /* reg_mprs_vxlan_udp_dport
8378 * VxLAN UDP destination port.
8379 * Used for identifying VxLAN packets and for dport field in
8380 * encapsulation. Default is 4789.
8383 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
8385 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
8386 u16 vxlan_udp_dport)
8388 MLXSW_REG_ZERO(mprs, payload);
8389 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
8390 mlxsw_reg_mprs_parsing_en_set(payload, true);
8391 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
8394 /* TNGCR - Tunneling NVE General Configuration Register
8395 * ----------------------------------------------------
8396 * The TNGCR register is used for setting up the NVE Tunneling configuration.
8398 #define MLXSW_REG_TNGCR_ID 0xA001
8399 #define MLXSW_REG_TNGCR_LEN 0x44
8401 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
8403 enum mlxsw_reg_tngcr_type {
8404 MLXSW_REG_TNGCR_TYPE_VXLAN,
8405 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
8406 MLXSW_REG_TNGCR_TYPE_GENEVE,
8407 MLXSW_REG_TNGCR_TYPE_NVGRE,
8411 * Tunnel type for encapsulation and decapsulation. The types are mutually
8413 * Note: For Spectrum the NVE parsing must be enabled in MPRS.
8416 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
8418 /* reg_tngcr_nve_valid
8419 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
8422 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
8424 /* reg_tngcr_nve_ttl_uc
8425 * The TTL for NVE tunnel encapsulation underlay unicast packets.
8428 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
8430 /* reg_tngcr_nve_ttl_mc
8431 * The TTL for NVE tunnel encapsulation underlay multicast packets.
8434 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
8437 /* Do not copy flow label. Calculate flow label using nve_flh. */
8438 MLXSW_REG_TNGCR_FL_NO_COPY,
8439 /* Copy flow label from inner packet if packet is IPv6 and
8440 * encapsulation is by IPv6. Otherwise, calculate flow label using
8443 MLXSW_REG_TNGCR_FL_COPY,
8446 /* reg_tngcr_nve_flc
8447 * For NVE tunnel encapsulation: Flow label copy from inner packet.
8450 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
8453 /* Flow label is static. In Spectrum this means '0'. Spectrum-2
8454 * uses {nve_fl_prefix, nve_fl_suffix}.
8456 MLXSW_REG_TNGCR_FL_NO_HASH,
8457 /* 8 LSBs of the flow label are calculated from ECMP hash of the
8458 * inner packet. 12 MSBs are configured by nve_fl_prefix.
8460 MLXSW_REG_TNGCR_FL_HASH,
8463 /* reg_tngcr_nve_flh
8464 * NVE flow label hash.
8467 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
8469 /* reg_tngcr_nve_fl_prefix
8470 * NVE flow label prefix. Constant 12 MSBs of the flow label.
8473 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
8475 /* reg_tngcr_nve_fl_suffix
8476 * NVE flow label suffix. Constant 8 LSBs of the flow label.
8477 * Reserved when nve_flh=1 and for Spectrum.
8480 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
8483 /* Source UDP port is fixed (default '0') */
8484 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
8485 /* Source UDP port is calculated based on hash */
8486 MLXSW_REG_TNGCR_UDP_SPORT_HASH,
8489 /* reg_tngcr_nve_udp_sport_type
8490 * NVE UDP source port type.
8491 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
8492 * When the source UDP port is calculated based on hash, then the 8 LSBs
8493 * are calculated from hash the 8 MSBs are configured by
8494 * nve_udp_sport_prefix.
8497 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
8499 /* reg_tngcr_nve_udp_sport_prefix
8500 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
8501 * Reserved when NVE type is NVGRE.
8504 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
8506 /* reg_tngcr_nve_group_size_mc
8507 * The amount of sequential linked lists of MC entries. The first linked
8508 * list is configured by SFD.underlay_mc_ptr.
8509 * Valid values: 1, 2, 4, 8, 16, 32, 64
8510 * The linked list are configured by TNUMT.
8511 * The hash is set by LAG hash.
8514 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
8516 /* reg_tngcr_nve_group_size_flood
8517 * The amount of sequential linked lists of flooding entries. The first
8518 * linked list is configured by SFMR.nve_tunnel_flood_ptr
8519 * Valid values: 1, 2, 4, 8, 16, 32, 64
8520 * The linked list are configured by TNUMT.
8521 * The hash is set by LAG hash.
8524 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
8526 /* reg_tngcr_learn_enable
8527 * During decapsulation, whether to learn from NVE port.
8528 * Reserved when Spectrum-2. See TNPC.
8531 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
8533 /* reg_tngcr_underlay_virtual_router
8534 * Underlay virtual router.
8535 * Reserved when Spectrum-2.
8538 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
8540 /* reg_tngcr_underlay_rif
8541 * Underlay ingress router interface. RIF type should be loopback generic.
8542 * Reserved when Spectrum.
8545 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
8548 * Underlay source IPv4 address of the NVE.
8551 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
8554 * Underlay source IPv6 address of the NVE. For Spectrum, must not be
8555 * modified under traffic of NVE tunneling encapsulation.
8558 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
8560 static inline void mlxsw_reg_tngcr_pack(char *payload,
8561 enum mlxsw_reg_tngcr_type type,
8564 MLXSW_REG_ZERO(tngcr, payload);
8565 mlxsw_reg_tngcr_type_set(payload, type);
8566 mlxsw_reg_tngcr_nve_valid_set(payload, valid);
8567 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
8568 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
8569 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
8570 mlxsw_reg_tngcr_nve_flh_set(payload, 0);
8571 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
8572 MLXSW_REG_TNGCR_UDP_SPORT_HASH);
8573 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
8574 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
8575 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
8578 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
8579 * -------------------------------------------------------
8580 * The TNUMT register is for building the underlay MC table. It is used
8581 * for MC, flooding and BC traffic into the NVE tunnel.
8583 #define MLXSW_REG_TNUMT_ID 0xA003
8584 #define MLXSW_REG_TNUMT_LEN 0x20
8586 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
8588 enum mlxsw_reg_tnumt_record_type {
8589 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
8590 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
8591 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
8594 /* reg_tnumt_record_type
8598 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
8600 enum mlxsw_reg_tnumt_tunnel_port {
8601 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
8602 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
8603 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
8604 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
8607 /* reg_tnumt_tunnel_port
8611 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
8613 /* reg_tnumt_underlay_mc_ptr
8614 * Index to the underlay multicast table.
8615 * For Spectrum the index is to the KVD linear.
8618 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
8621 * The next_underlay_mc_ptr is valid.
8624 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
8626 /* reg_tnumt_next_underlay_mc_ptr
8627 * The next index to the underlay multicast table.
8630 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
8632 /* reg_tnumt_record_size
8633 * Number of IP addresses in the record.
8634 * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
8637 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
8640 * The underlay IPv4 addresses. udip[i] is reserved if i >= size
8643 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
8645 /* reg_tnumt_udip_ptr
8646 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
8647 * i >= size. The IPv6 addresses are configured by RIPS.
8650 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
8652 static inline void mlxsw_reg_tnumt_pack(char *payload,
8653 enum mlxsw_reg_tnumt_record_type type,
8654 enum mlxsw_reg_tnumt_tunnel_port tport,
8655 u32 underlay_mc_ptr, bool vnext,
8656 u32 next_underlay_mc_ptr,
8659 MLXSW_REG_ZERO(tnumt, payload);
8660 mlxsw_reg_tnumt_record_type_set(payload, type);
8661 mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
8662 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
8663 mlxsw_reg_tnumt_vnext_set(payload, vnext);
8664 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
8665 mlxsw_reg_tnumt_record_size_set(payload, record_size);
8668 /* TNQCR - Tunneling NVE QoS Configuration Register
8669 * ------------------------------------------------
8670 * The TNQCR register configures how QoS is set in encapsulation into the
8673 #define MLXSW_REG_TNQCR_ID 0xA010
8674 #define MLXSW_REG_TNQCR_LEN 0x0C
8676 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
8678 /* reg_tnqcr_enc_set_dscp
8679 * For encapsulation: How to set DSCP field:
8680 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
8681 * (outer) IP header. If there is no IP header, use TNQDR.dscp
8682 * 1 - Set the DSCP field as TNQDR.dscp
8685 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
8687 static inline void mlxsw_reg_tnqcr_pack(char *payload)
8689 MLXSW_REG_ZERO(tnqcr, payload);
8690 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
8693 /* TNQDR - Tunneling NVE QoS Default Register
8694 * ------------------------------------------
8695 * The TNQDR register configures the default QoS settings for NVE
8698 #define MLXSW_REG_TNQDR_ID 0xA011
8699 #define MLXSW_REG_TNQDR_LEN 0x08
8701 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
8703 /* reg_tnqdr_local_port
8704 * Local port number (receive port). CPU port is supported.
8707 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
8710 * For encapsulation, the default DSCP.
8713 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
8715 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
8717 MLXSW_REG_ZERO(tnqdr, payload);
8718 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
8719 mlxsw_reg_tnqdr_dscp_set(payload, 0);
8722 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
8723 * --------------------------------------------------------
8724 * The TNEEM register maps ECN of the IP header at the ingress to the
8725 * encapsulation to the ECN of the underlay network.
8727 #define MLXSW_REG_TNEEM_ID 0xA012
8728 #define MLXSW_REG_TNEEM_LEN 0x0C
8730 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
8732 /* reg_tneem_overlay_ecn
8733 * ECN of the IP header in the overlay network.
8736 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
8738 /* reg_tneem_underlay_ecn
8739 * ECN of the IP header in the underlay network.
8742 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
8744 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
8747 MLXSW_REG_ZERO(tneem, payload);
8748 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
8749 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
8752 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
8753 * --------------------------------------------------------
8754 * The TNDEM register configures the actions that are done in the
8757 #define MLXSW_REG_TNDEM_ID 0xA013
8758 #define MLXSW_REG_TNDEM_LEN 0x0C
8760 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
8762 /* reg_tndem_underlay_ecn
8763 * ECN field of the IP header in the underlay network.
8766 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
8768 /* reg_tndem_overlay_ecn
8769 * ECN field of the IP header in the overlay network.
8772 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
8774 /* reg_tndem_eip_ecn
8775 * Egress IP ECN. ECN field of the IP header of the packet which goes out
8776 * from the decapsulation.
8779 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
8781 /* reg_tndem_trap_en
8783 * 0 - No trap due to decap ECN
8784 * 1 - Trap enable with trap_id
8787 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
8789 /* reg_tndem_trap_id
8790 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
8791 * Reserved when trap_en is '0'.
8794 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
8796 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
8797 u8 overlay_ecn, u8 ecn, bool trap_en,
8800 MLXSW_REG_ZERO(tndem, payload);
8801 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
8802 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
8803 mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
8804 mlxsw_reg_tndem_trap_en_set(payload, trap_en);
8805 mlxsw_reg_tndem_trap_id_set(payload, trap_id);
8808 /* TNPC - Tunnel Port Configuration Register
8809 * -----------------------------------------
8810 * The TNPC register is used for tunnel port configuration.
8811 * Reserved when Spectrum.
8813 #define MLXSW_REG_TNPC_ID 0xA020
8814 #define MLXSW_REG_TNPC_LEN 0x18
8816 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
8818 enum mlxsw_reg_tnpc_tunnel_port {
8819 MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
8820 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
8821 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
8822 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
8825 /* reg_tnpc_tunnel_port
8829 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
8831 /* reg_tnpc_learn_enable_v6
8832 * During IPv6 underlay decapsulation, whether to learn from tunnel port.
8835 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
8837 /* reg_tnpc_learn_enable_v4
8838 * During IPv4 underlay decapsulation, whether to learn from tunnel port.
8841 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
8843 static inline void mlxsw_reg_tnpc_pack(char *payload,
8844 enum mlxsw_reg_tnpc_tunnel_port tport,
8847 MLXSW_REG_ZERO(tnpc, payload);
8848 mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
8849 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
8850 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
8853 /* TIGCR - Tunneling IPinIP General Configuration Register
8854 * -------------------------------------------------------
8855 * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
8857 #define MLXSW_REG_TIGCR_ID 0xA801
8858 #define MLXSW_REG_TIGCR_LEN 0x10
8860 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
8862 /* reg_tigcr_ipip_ttlc
8863 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
8867 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
8869 /* reg_tigcr_ipip_ttl_uc
8870 * The TTL for IPinIP Tunnel encapsulation of unicast packets if
8871 * reg_tigcr_ipip_ttlc is unset.
8874 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
8876 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
8878 MLXSW_REG_ZERO(tigcr, payload);
8879 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
8880 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
8883 /* SBPR - Shared Buffer Pools Register
8884 * -----------------------------------
8885 * The SBPR configures and retrieves the shared buffer pools and configuration.
8887 #define MLXSW_REG_SBPR_ID 0xB001
8888 #define MLXSW_REG_SBPR_LEN 0x14
8890 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
8892 /* shared direstion enum for SBPR, SBCM, SBPM */
8893 enum mlxsw_reg_sbxx_dir {
8894 MLXSW_REG_SBXX_DIR_INGRESS,
8895 MLXSW_REG_SBXX_DIR_EGRESS,
8902 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
8908 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
8910 /* reg_sbpr_infi_size
8914 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
8917 * Pool size in buffer cells.
8918 * Reserved when infi_size = 1.
8921 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
8923 enum mlxsw_reg_sbpr_mode {
8924 MLXSW_REG_SBPR_MODE_STATIC,
8925 MLXSW_REG_SBPR_MODE_DYNAMIC,
8929 * Pool quota calculation mode.
8932 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
8934 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
8935 enum mlxsw_reg_sbxx_dir dir,
8936 enum mlxsw_reg_sbpr_mode mode, u32 size,
8939 MLXSW_REG_ZERO(sbpr, payload);
8940 mlxsw_reg_sbpr_pool_set(payload, pool);
8941 mlxsw_reg_sbpr_dir_set(payload, dir);
8942 mlxsw_reg_sbpr_mode_set(payload, mode);
8943 mlxsw_reg_sbpr_size_set(payload, size);
8944 mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
8947 /* SBCM - Shared Buffer Class Management Register
8948 * ----------------------------------------------
8949 * The SBCM register configures and retrieves the shared buffer allocation
8950 * and configuration according to Port-PG, including the binding to pool
8951 * and definition of the associated quota.
8953 #define MLXSW_REG_SBCM_ID 0xB002
8954 #define MLXSW_REG_SBCM_LEN 0x28
8956 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
8958 /* reg_sbcm_local_port
8959 * Local port number.
8960 * For Ingress: excludes CPU port and Router port
8961 * For Egress: excludes IP Router
8964 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
8967 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
8968 * For PG buffer: range is 0..cap_max_pg_buffers - 1
8969 * For traffic class: range is 0..cap_max_tclass - 1
8970 * Note that when traffic class is in MC aware mode then the traffic
8971 * classes which are MC aware cannot be configured.
8974 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
8980 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
8982 /* reg_sbcm_min_buff
8983 * Minimum buffer size for the limiter, in cells.
8986 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
8988 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
8989 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
8990 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
8992 /* reg_sbcm_infi_max
8993 * Max buffer is infinite.
8996 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
8998 /* reg_sbcm_max_buff
8999 * When the pool associated to the port-pg/tclass is configured to
9000 * static, Maximum buffer size for the limiter configured in cells.
9001 * When the pool associated to the port-pg/tclass is configured to
9002 * dynamic, the max_buff holds the "alpha" parameter, supporting
9003 * the following values:
9005 * i: (1/128)*2^(i-1), for i=1..14
9007 * Reserved when infi_max = 1.
9010 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
9013 * Association of the port-priority to a pool.
9016 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
9018 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
9019 enum mlxsw_reg_sbxx_dir dir,
9020 u32 min_buff, u32 max_buff,
9021 bool infi_max, u8 pool)
9023 MLXSW_REG_ZERO(sbcm, payload);
9024 mlxsw_reg_sbcm_local_port_set(payload, local_port);
9025 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
9026 mlxsw_reg_sbcm_dir_set(payload, dir);
9027 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
9028 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
9029 mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
9030 mlxsw_reg_sbcm_pool_set(payload, pool);
9033 /* SBPM - Shared Buffer Port Management Register
9034 * ---------------------------------------------
9035 * The SBPM register configures and retrieves the shared buffer allocation
9036 * and configuration according to Port-Pool, including the definition
9037 * of the associated quota.
9039 #define MLXSW_REG_SBPM_ID 0xB003
9040 #define MLXSW_REG_SBPM_LEN 0x28
9042 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
9044 /* reg_sbpm_local_port
9045 * Local port number.
9046 * For Ingress: excludes CPU port and Router port
9047 * For Egress: excludes IP Router
9050 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
9053 * The pool associated to quota counting on the local_port.
9056 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
9062 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
9064 /* reg_sbpm_buff_occupancy
9065 * Current buffer occupancy in cells.
9068 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
9071 * Clear Max Buffer Occupancy
9072 * When this bit is set, max_buff_occupancy field is cleared (and a
9073 * new max value is tracked from the time the clear was performed).
9076 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
9078 /* reg_sbpm_max_buff_occupancy
9079 * Maximum value of buffer occupancy in cells monitored. Cleared by
9080 * writing to the clr field.
9083 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
9085 /* reg_sbpm_min_buff
9086 * Minimum buffer size for the limiter, in cells.
9089 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
9091 /* reg_sbpm_max_buff
9092 * When the pool associated to the port-pg/tclass is configured to
9093 * static, Maximum buffer size for the limiter configured in cells.
9094 * When the pool associated to the port-pg/tclass is configured to
9095 * dynamic, the max_buff holds the "alpha" parameter, supporting
9096 * the following values:
9098 * i: (1/128)*2^(i-1), for i=1..14
9102 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
9104 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
9105 enum mlxsw_reg_sbxx_dir dir, bool clr,
9106 u32 min_buff, u32 max_buff)
9108 MLXSW_REG_ZERO(sbpm, payload);
9109 mlxsw_reg_sbpm_local_port_set(payload, local_port);
9110 mlxsw_reg_sbpm_pool_set(payload, pool);
9111 mlxsw_reg_sbpm_dir_set(payload, dir);
9112 mlxsw_reg_sbpm_clr_set(payload, clr);
9113 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
9114 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
9117 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
9118 u32 *p_max_buff_occupancy)
9120 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
9121 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
9124 /* SBMM - Shared Buffer Multicast Management Register
9125 * --------------------------------------------------
9126 * The SBMM register configures and retrieves the shared buffer allocation
9127 * and configuration for MC packets according to Switch-Priority, including
9128 * the binding to pool and definition of the associated quota.
9130 #define MLXSW_REG_SBMM_ID 0xB004
9131 #define MLXSW_REG_SBMM_LEN 0x28
9133 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
9139 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
9141 /* reg_sbmm_min_buff
9142 * Minimum buffer size for the limiter, in cells.
9145 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
9147 /* reg_sbmm_max_buff
9148 * When the pool associated to the port-pg/tclass is configured to
9149 * static, Maximum buffer size for the limiter configured in cells.
9150 * When the pool associated to the port-pg/tclass is configured to
9151 * dynamic, the max_buff holds the "alpha" parameter, supporting
9152 * the following values:
9154 * i: (1/128)*2^(i-1), for i=1..14
9158 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
9161 * Association of the port-priority to a pool.
9164 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
9166 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
9167 u32 max_buff, u8 pool)
9169 MLXSW_REG_ZERO(sbmm, payload);
9170 mlxsw_reg_sbmm_prio_set(payload, prio);
9171 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
9172 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
9173 mlxsw_reg_sbmm_pool_set(payload, pool);
9176 /* SBSR - Shared Buffer Status Register
9177 * ------------------------------------
9178 * The SBSR register retrieves the shared buffer occupancy according to
9179 * Port-Pool. Note that this register enables reading a large amount of data.
9180 * It is the user's responsibility to limit the amount of data to ensure the
9181 * response can match the maximum transfer unit. In case the response exceeds
9182 * the maximum transport unit, it will be truncated with no special notice.
9184 #define MLXSW_REG_SBSR_ID 0xB005
9185 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
9186 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
9187 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
9188 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
9189 MLXSW_REG_SBSR_REC_LEN * \
9190 MLXSW_REG_SBSR_REC_MAX_COUNT)
9192 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
9195 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
9196 * field is cleared (and a new max value is tracked from the time the clear
9200 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
9202 /* reg_sbsr_ingress_port_mask
9203 * Bit vector for all ingress network ports.
9204 * Indicates which of the ports (for which the relevant bit is set)
9205 * are affected by the set operation. Configuration of any other port
9209 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
9211 /* reg_sbsr_pg_buff_mask
9212 * Bit vector for all switch priority groups.
9213 * Indicates which of the priorities (for which the relevant bit is set)
9214 * are affected by the set operation. Configuration of any other priority
9216 * Range is 0..cap_max_pg_buffers - 1
9219 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
9221 /* reg_sbsr_egress_port_mask
9222 * Bit vector for all egress network ports.
9223 * Indicates which of the ports (for which the relevant bit is set)
9224 * are affected by the set operation. Configuration of any other port
9228 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
9230 /* reg_sbsr_tclass_mask
9231 * Bit vector for all traffic classes.
9232 * Indicates which of the traffic classes (for which the relevant bit is
9233 * set) are affected by the set operation. Configuration of any other
9234 * traffic class does not change.
9235 * Range is 0..cap_max_tclass - 1
9238 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
9240 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
9242 MLXSW_REG_ZERO(sbsr, payload);
9243 mlxsw_reg_sbsr_clr_set(payload, clr);
9246 /* reg_sbsr_rec_buff_occupancy
9247 * Current buffer occupancy in cells.
9250 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
9251 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
9253 /* reg_sbsr_rec_max_buff_occupancy
9254 * Maximum value of buffer occupancy in cells monitored. Cleared by
9255 * writing to the clr field.
9258 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
9259 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
9261 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
9262 u32 *p_buff_occupancy,
9263 u32 *p_max_buff_occupancy)
9266 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
9267 *p_max_buff_occupancy =
9268 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
9271 /* SBIB - Shared Buffer Internal Buffer Register
9272 * ---------------------------------------------
9273 * The SBIB register configures per port buffers for internal use. The internal
9274 * buffers consume memory on the port buffers (note that the port buffers are
9275 * used also by PBMC).
9277 * For Spectrum this is used for egress mirroring.
9279 #define MLXSW_REG_SBIB_ID 0xB006
9280 #define MLXSW_REG_SBIB_LEN 0x10
9282 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
9284 /* reg_sbib_local_port
9286 * Not supported for CPU port and router port
9289 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
9291 /* reg_sbib_buff_size
9292 * Units represented in cells
9293 * Allowed range is 0 to (cap_max_headroom_size - 1)
9297 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
9299 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
9302 MLXSW_REG_ZERO(sbib, payload);
9303 mlxsw_reg_sbib_local_port_set(payload, local_port);
9304 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
9307 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
9419 static inline const char *mlxsw_reg_id_str(u16 reg_id)
9421 const struct mlxsw_reg_info *reg_info;
9424 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
9425 reg_info = mlxsw_reg_infos[i];
9426 if (reg_info->id == reg_id)
9427 return reg_info->name;
9432 /* PUDE - Port Up / Down Event
9433 * ---------------------------
9434 * Reports the operational state change of a port.
9436 #define MLXSW_REG_PUDE_LEN 0x10
9439 * Switch partition ID with which to associate the port.
9442 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
9444 /* reg_pude_local_port
9445 * Local port number.
9448 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
9450 /* reg_pude_admin_status
9451 * Port administrative state (the desired state).
9454 * 3 - Up once. This means that in case of link failure, the port won't go
9455 * into polling mode, but will wait to be re-enabled by software.
9456 * 4 - Disabled by system. Can only be set by hardware.
9459 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
9461 /* reg_pude_oper_status
9462 * Port operatioanl state.
9465 * 3 - Down by port failure. This means that the device will not let the
9466 * port up again until explicitly specified by software.
9469 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);