drivers/net/ethernet/mellanox/mlxsw/pci.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/export.h>
  38 #include <linux/err.h>
  39 #include <linux/device.h>
  40 #include <linux/pci.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/wait.h>
  43 #include <linux/types.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/log2.h>
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #include <linux/string.h>
  50
  51 #include "pci.h"
  52 #include "core.h"
  53 #include "cmd.h"
  54 #include "port.h"
  55
  56 static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
  57
  58 static const struct pci_device_id mlxsw_pci_id_table[] = {
  59         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
  60         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
  61         {0, }
  62 };
  63
  64 static struct dentry *mlxsw_pci_dbg_root;
  65
  66 static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id)
  67 {
  68         switch (id->device) {
  69         case PCI_DEVICE_ID_MELLANOX_SWITCHX2:
  70                 return MLXSW_DEVICE_KIND_SWITCHX2;
  71         case PCI_DEVICE_ID_MELLANOX_SPECTRUM:
  72                 return MLXSW_DEVICE_KIND_SPECTRUM;
  73         default:
  74                 BUG();
  75         }
  76 }
  77
  78 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
  79         iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  80 #define mlxsw_pci_read32(mlxsw_pci, reg) \
  81         ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  82
  83 enum mlxsw_pci_queue_type {
  84         MLXSW_PCI_QUEUE_TYPE_SDQ,
  85         MLXSW_PCI_QUEUE_TYPE_RDQ,
  86         MLXSW_PCI_QUEUE_TYPE_CQ,
  87         MLXSW_PCI_QUEUE_TYPE_EQ,
  88 };
  89
  90 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type)
  91 {
  92         switch (q_type) {
  93         case MLXSW_PCI_QUEUE_TYPE_SDQ:
  94                 return "sdq";
  95         case MLXSW_PCI_QUEUE_TYPE_RDQ:
  96                 return "rdq";
  97         case MLXSW_PCI_QUEUE_TYPE_CQ:
  98                 return "cq";
  99         case MLXSW_PCI_QUEUE_TYPE_EQ:
 100                 return "eq";
 101         }
 102         BUG();
 103 }
 104
 105 #define MLXSW_PCI_QUEUE_TYPE_COUNT      4
 106
 107 static const u16 mlxsw_pci_doorbell_type_offset[] = {
 108         MLXSW_PCI_DOORBELL_SDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
 109         MLXSW_PCI_DOORBELL_RDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
 110         MLXSW_PCI_DOORBELL_CQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 111         MLXSW_PCI_DOORBELL_EQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 112 };
 113
 114 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
 115         0, /* unused */
 116         0, /* unused */
 117         MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 118         MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 119 };
 120
 121 struct mlxsw_pci_mem_item {
 122         char *buf;
 123         dma_addr_t mapaddr;
 124         size_t size;
 125 };
 126
 127 struct mlxsw_pci_queue_elem_info {
 128         char *elem; /* pointer to actual dma mapped element mem chunk */
 129         union {
 130                 struct {
 131                         struct sk_buff *skb;
 132                 } sdq;
 133                 struct {
 134                         struct sk_buff *skb;
 135                 } rdq;
 136         } u;
 137 };
 138
 139 struct mlxsw_pci_queue {
 140         spinlock_t lock; /* for queue accesses */
 141         struct mlxsw_pci_mem_item mem_item;
 142         struct mlxsw_pci_queue_elem_info *elem_info;
 143         u16 producer_counter;
 144         u16 consumer_counter;
 145         u16 count; /* number of elements in queue */
 146         u8 num; /* queue number */
 147         u8 elem_size; /* size of one element */
 148         enum mlxsw_pci_queue_type type;
 149         struct tasklet_struct tasklet; /* queue processing tasklet */
 150         struct mlxsw_pci *pci;
 151         union {
 152                 struct {
 153                         u32 comp_sdq_count;
 154                         u32 comp_rdq_count;
 155                 } cq;
 156                 struct {
 157                         u32 ev_cmd_count;
 158                         u32 ev_comp_count;
 159                         u32 ev_other_count;
 160                 } eq;
 161         } u;
 162 };
 163
 164 struct mlxsw_pci_queue_type_group {
 165         struct mlxsw_pci_queue *q;
 166         u8 count; /* number of queues in group */
 167 };
 168
 169 struct mlxsw_pci {
 170         struct pci_dev *pdev;
 171         u8 __iomem *hw_addr;
 172         struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
 173         u32 doorbell_offset;
 174         struct msix_entry msix_entry;
 175         struct mlxsw_core *core;
 176         struct {
 177                 struct mlxsw_pci_mem_item *items;
 178                 unsigned int count;
 179         } fw_area;
 180         struct {
 181                 struct mlxsw_pci_mem_item out_mbox;
 182                 struct mlxsw_pci_mem_item in_mbox;
 183                 struct mutex lock; /* Lock access to command registers */
 184                 bool nopoll;
 185                 wait_queue_head_t wait;
 186                 bool wait_done;
 187                 struct {
 188                         u8 status;
 189                         u64 out_param;
 190                 } comp;
 191         } cmd;
 192         struct mlxsw_bus_info bus_info;
 193         struct dentry *dbg_dir;
 194 };
 195
 196 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
 197 {
 198         tasklet_schedule(&q->tasklet);
 199 }
 200
 201 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
 202                                         size_t elem_size, int elem_index)
 203 {
 204         return q->mem_item.buf + (elem_size * elem_index);
 205 }
 206
 207 static struct mlxsw_pci_queue_elem_info *
 208 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
 209 {
 210         return &q->elem_info[elem_index];
 211 }
 212
 213 static struct mlxsw_pci_queue_elem_info *
 214 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
 215 {
 216         int index = q->producer_counter & (q->count - 1);
 217
 218         if ((q->producer_counter - q->consumer_counter) == q->count)
 219                 return NULL;
 220         return mlxsw_pci_queue_elem_info_get(q, index);
 221 }
 222
 223 static struct mlxsw_pci_queue_elem_info *
 224 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
 225 {
 226         int index = q->consumer_counter & (q->count - 1);
 227
 228         return mlxsw_pci_queue_elem_info_get(q, index);
 229 }
 230
 231 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
 232 {
 233         return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
 234 }
 235
 236 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
 237 {
 238         return owner_bit != !!(q->consumer_counter & q->count);
 239 }
 240
 241 static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q,
 242                                          u32 (*get_elem_owner_func)(char *))
 243 {
 244         struct mlxsw_pci_queue_elem_info *elem_info;
 245         char *elem;
 246         bool owner_bit;
 247
 248         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 249         elem = elem_info->elem;
 250         owner_bit = get_elem_owner_func(elem);
 251         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 252                 return NULL;
 253         q->consumer_counter++;
 254         rmb(); /* make sure we read owned bit before the rest of elem */
 255         return elem;
 256 }
 257
 258 static struct mlxsw_pci_queue_type_group *
 259 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
 260                                enum mlxsw_pci_queue_type q_type)
 261 {
 262         return &mlxsw_pci->queues[q_type];
 263 }
 264
 265 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
 266                                   enum mlxsw_pci_queue_type q_type)
 267 {
 268         struct mlxsw_pci_queue_type_group *queue_group;
 269
 270         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
 271         return queue_group->count;
 272 }
 273
 274 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
 275 {
 276         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
 277 }
 278
 279 static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci)
 280 {
 281         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ);
 282 }
 283
 284 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
 285 {
 286         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
 287 }
 288
 289 static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci)
 290 {
 291         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ);
 292 }
 293
 294 static struct mlxsw_pci_queue *
 295 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
 296                       enum mlxsw_pci_queue_type q_type, u8 q_num)
 297 {
 298         return &mlxsw_pci->queues[q_type].q[q_num];
 299 }
 300
 301 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
 302                                                  u8 q_num)
 303 {
 304         return __mlxsw_pci_queue_get(mlxsw_pci,
 305                                      MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
 306 }
 307
 308 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
 309                                                  u8 q_num)
 310 {
 311         return __mlxsw_pci_queue_get(mlxsw_pci,
 312                                      MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
 313 }
 314
 315 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
 316                                                 u8 q_num)
 317 {
 318         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
 319 }
 320
 321 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
 322                                                 u8 q_num)
 323 {
 324         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
 325 }
 326
 327 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
 328                                            struct mlxsw_pci_queue *q,
 329                                            u16 val)
 330 {
 331         mlxsw_pci_write32(mlxsw_pci,
 332                           DOORBELL(mlxsw_pci->doorbell_offset,
 333                                    mlxsw_pci_doorbell_type_offset[q->type],
 334                                    q->num), val);
 335 }
 336
 337 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
 338                                                struct mlxsw_pci_queue *q,
 339                                                u16 val)
 340 {
 341         mlxsw_pci_write32(mlxsw_pci,
 342                           DOORBELL(mlxsw_pci->doorbell_offset,
 343                                    mlxsw_pci_doorbell_arm_type_offset[q->type],
 344                                    q->num), val);
 345 }
 346
 347 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
 348                                                    struct mlxsw_pci_queue *q)
 349 {
 350         wmb(); /* ensure all writes are done before we ring a bell */
 351         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
 352 }
 353
 354 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 355                                                    struct mlxsw_pci_queue *q)
 356 {
 357         wmb(); /* ensure all writes are done before we ring a bell */
 358         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
 359                                        q->consumer_counter + q->count);
 360 }
 361
 362 static void
 363 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 364                                            struct mlxsw_pci_queue *q)
 365 {
 366         wmb(); /* ensure all writes are done before we ring a bell */
 367         __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
 368 }
 369
 370 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
 371                                              int page_index)
 372 {
 373         return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
 374 }
 375
 376 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 377                               struct mlxsw_pci_queue *q)
 378 {
 379         int i;
 380         int err;
 381
 382         q->producer_counter = 0;
 383         q->consumer_counter = 0;
 384
 385         /* Set CQ of same number of this SDQ. */
 386         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
 387         mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 7);
 388         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 389         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 390                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 391
 392                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 393         }
 394
 395         err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
 396         if (err)
 397                 return err;
 398         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 399         return 0;
 400 }
 401
 402 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
 403                                struct mlxsw_pci_queue *q)
 404 {
 405         mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
 406 }
 407
 408 static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data)
 409 {
 410         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 411         struct mlxsw_pci_queue *q;
 412         int i;
 413         static const char hdr[] =
 414                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 415
 416         seq_printf(file, hdr);
 417         for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) {
 418                 q = mlxsw_pci_sdq_get(mlxsw_pci, i);
 419                 spin_lock_bh(&q->lock);
 420                 seq_printf(file, "%3d %10d %10d %5d\n",
 421                            i, q->producer_counter, q->consumer_counter,
 422                            q->count);
 423                 spin_unlock_bh(&q->lock);
 424         }
 425         return 0;
 426 }
 427
 428 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
 429                                   int index, char *frag_data, size_t frag_len,
 430                                   int direction)
 431 {
 432         struct pci_dev *pdev = mlxsw_pci->pdev;
 433         dma_addr_t mapaddr;
 434
 435         mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
 436         if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
 437                 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
 438                 return -EIO;
 439         }
 440         mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
 441         mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
 442         return 0;
 443 }
 444
 445 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
 446                                      int index, int direction)
 447 {
 448         struct pci_dev *pdev = mlxsw_pci->pdev;
 449         size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
 450         dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
 451
 452         if (!frag_len)
 453                 return;
 454         pci_unmap_single(pdev, mapaddr, frag_len, direction);
 455 }
 456
 457 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
 458                                    struct mlxsw_pci_queue_elem_info *elem_info)
 459 {
 460         size_t buf_len = MLXSW_PORT_MAX_MTU;
 461         char *wqe = elem_info->elem;
 462         struct sk_buff *skb;
 463         int err;
 464
 465         elem_info->u.rdq.skb = NULL;
 466         skb = netdev_alloc_skb_ip_align(NULL, buf_len);
 467         if (!skb)
 468                 return -ENOMEM;
 469
 470         /* Assume that wqe was previously zeroed. */
 471
 472         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
 473                                      buf_len, DMA_FROM_DEVICE);
 474         if (err)
 475                 goto err_frag_map;
 476
 477         elem_info->u.rdq.skb = skb;
 478         return 0;
 479
 480 err_frag_map:
 481         dev_kfree_skb_any(skb);
 482         return err;
 483 }
 484
 485 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
 486                                    struct mlxsw_pci_queue_elem_info *elem_info)
 487 {
 488         struct sk_buff *skb;
 489         char *wqe;
 490
 491         skb = elem_info->u.rdq.skb;
 492         wqe = elem_info->elem;
 493
 494         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 495         dev_kfree_skb_any(skb);
 496 }
 497
 498 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 499                               struct mlxsw_pci_queue *q)
 500 {
 501         struct mlxsw_pci_queue_elem_info *elem_info;
 502         u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
 503         int i;
 504         int err;
 505
 506         q->producer_counter = 0;
 507         q->consumer_counter = 0;
 508
 509         /* Set CQ of same number of this RDQ with base
 510          * above SDQ count as the lower ones are assigned to SDQs.
 511          */
 512         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
 513         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 514         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 515                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 516
 517                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 518         }
 519
 520         err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
 521         if (err)
 522                 return err;
 523
 524         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 525
 526         for (i = 0; i < q->count; i++) {
 527                 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
 528                 BUG_ON(!elem_info);
 529                 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 530                 if (err)
 531                         goto rollback;
 532                 /* Everything is set up, ring doorbell to pass elem to HW */
 533                 q->producer_counter++;
 534                 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 535         }
 536
 537         return 0;
 538
 539 rollback:
 540         for (i--; i >= 0; i--) {
 541                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 542                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 543         }
 544         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 545
 546         return err;
 547 }
 548
 549 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
 550                                struct mlxsw_pci_queue *q)
 551 {
 552         struct mlxsw_pci_queue_elem_info *elem_info;
 553         int i;
 554
 555         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 556         for (i = 0; i < q->count; i++) {
 557                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 558                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 559         }
 560 }
 561
 562 static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data)
 563 {
 564         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 565         struct mlxsw_pci_queue *q;
 566         int i;
 567         static const char hdr[] =
 568                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 569
 570         seq_printf(file, hdr);
 571         for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) {
 572                 q = mlxsw_pci_rdq_get(mlxsw_pci, i);
 573                 spin_lock_bh(&q->lock);
 574                 seq_printf(file, "%3d %10d %10d %5d\n",
 575                            i, q->producer_counter, q->consumer_counter,
 576                            q->count);
 577                 spin_unlock_bh(&q->lock);
 578         }
 579         return 0;
 580 }
 581
 582 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 583                              struct mlxsw_pci_queue *q)
 584 {
 585         int i;
 586         int err;
 587
 588         q->consumer_counter = 0;
 589
 590         for (i = 0; i < q->count; i++) {
 591                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 592
 593                 mlxsw_pci_cqe_owner_set(elem, 1);
 594         }
 595
 596         mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */
 597         mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
 598         mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0);
 599         mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
 600         mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
 601         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 602                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 603
 604                 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
 605         }
 606         err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
 607         if (err)
 608                 return err;
 609         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 610         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 611         return 0;
 612 }
 613
 614 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
 615                               struct mlxsw_pci_queue *q)
 616 {
 617         mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 618 }
 619
 620 static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data)
 621 {
 622         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 623
 624         struct mlxsw_pci_queue *q;
 625         int i;
 626         static const char hdr[] =
 627                 "NUM CONS_INDEX  SDQ_COUNT  RDQ_COUNT COUNT\n";
 628
 629         seq_printf(file, hdr);
 630         for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) {
 631                 q = mlxsw_pci_cq_get(mlxsw_pci, i);
 632                 spin_lock_bh(&q->lock);
 633                 seq_printf(file, "%3d %10d %10d %10d %5d\n",
 634                            i, q->consumer_counter, q->u.cq.comp_sdq_count,
 635                            q->u.cq.comp_rdq_count, q->count);
 636                 spin_unlock_bh(&q->lock);
 637         }
 638         return 0;
 639 }
 640
 641 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
 642                                      struct mlxsw_pci_queue *q,
 643                                      u16 consumer_counter_limit,
 644                                      char *cqe)
 645 {
 646         struct pci_dev *pdev = mlxsw_pci->pdev;
 647         struct mlxsw_pci_queue_elem_info *elem_info;
 648         char *wqe;
 649         struct sk_buff *skb;
 650         int i;
 651
 652         spin_lock(&q->lock);
 653         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 654         skb = elem_info->u.sdq.skb;
 655         wqe = elem_info->elem;
 656         for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
 657                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
 658         dev_kfree_skb_any(skb);
 659         elem_info->u.sdq.skb = NULL;
 660
 661         if (q->consumer_counter++ != consumer_counter_limit)
 662                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
 663         spin_unlock(&q->lock);
 664 }
 665
 666 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
 667                                      struct mlxsw_pci_queue *q,
 668                                      u16 consumer_counter_limit,
 669                                      char *cqe)
 670 {
 671         struct pci_dev *pdev = mlxsw_pci->pdev;
 672         struct mlxsw_pci_queue_elem_info *elem_info;
 673         char *wqe;
 674         struct sk_buff *skb;
 675         struct mlxsw_rx_info rx_info;
 676         u16 byte_count;
 677         int err;
 678
 679         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 680         skb = elem_info->u.sdq.skb;
 681         if (!skb)
 682                 return;
 683         wqe = elem_info->elem;
 684         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 685
 686         if (q->consumer_counter++ != consumer_counter_limit)
 687                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
 688
 689         /* We do not support lag now */
 690         if (mlxsw_pci_cqe_lag_get(cqe))
 691                 goto drop;
 692
 693         rx_info.is_lag = false;
 694         rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
 695
 696         rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
 697
 698         byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
 699         if (mlxsw_pci_cqe_crc_get(cqe))
 700                 byte_count -= ETH_FCS_LEN;
 701         skb_put(skb, byte_count);
 702         mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
 703
 704 put_new_skb:
 705         memset(wqe, 0, q->elem_size);
 706         err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 707         if (err)
 708                 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
 709         /* Everything is set up, ring doorbell to pass elem to HW */
 710         q->producer_counter++;
 711         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 712         return;
 713
 714 drop:
 715         dev_kfree_skb_any(skb);
 716         goto put_new_skb;
 717 }
 718
 719 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
 720 {
 721         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get);
 722 }
 723
 724 static void mlxsw_pci_cq_tasklet(unsigned long data)
 725 {
 726         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 727         struct mlxsw_pci *mlxsw_pci = q->pci;
 728         char *cqe;
 729         int items = 0;
 730         int credits = q->count >> 1;
 731
 732         while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
 733                 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
 734                 u8 sendq = mlxsw_pci_cqe_sr_get(cqe);
 735                 u8 dqn = mlxsw_pci_cqe_dqn_get(cqe);
 736
 737                 if (sendq) {
 738                         struct mlxsw_pci_queue *sdq;
 739
 740                         sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
 741                         mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
 742                                                  wqe_counter, cqe);
 743                         q->u.cq.comp_sdq_count++;
 744                 } else {
 745                         struct mlxsw_pci_queue *rdq;
 746
 747                         rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
 748                         mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
 749                                                  wqe_counter, cqe);
 750                         q->u.cq.comp_rdq_count++;
 751                 }
 752                 if (++items == credits)
 753                         break;
 754         }
 755         if (items) {
 756                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 757                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 758         }
 759 }
 760
 761 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 762                              struct mlxsw_pci_queue *q)
 763 {
 764         int i;
 765         int err;
 766
 767         q->consumer_counter = 0;
 768
 769         for (i = 0; i < q->count; i++) {
 770                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 771
 772                 mlxsw_pci_eqe_owner_set(elem, 1);
 773         }
 774
 775         mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
 776         mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0);
 777         mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
 778         mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
 779         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 780                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 781
 782                 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
 783         }
 784         err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
 785         if (err)
 786                 return err;
 787         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 788         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 789         return 0;
 790 }
 791
 792 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
 793                               struct mlxsw_pci_queue *q)
 794 {
 795         mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
 796 }
 797
 798 static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data)
 799 {
 800         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 801         struct mlxsw_pci_queue *q;
 802         int i;
 803         static const char hdr[] =
 804                 "NUM CONS_COUNT     EV_CMD    EV_COMP   EV_OTHER COUNT\n";
 805
 806         seq_printf(file, hdr);
 807         for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) {
 808                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
 809                 spin_lock_bh(&q->lock);
 810                 seq_printf(file, "%3d %10d %10d %10d %10d %5d\n",
 811                            i, q->consumer_counter, q->u.eq.ev_cmd_count,
 812                            q->u.eq.ev_comp_count, q->u.eq.ev_other_count,
 813                            q->count);
 814                 spin_unlock_bh(&q->lock);
 815         }
 816         return 0;
 817 }
 818
 819 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
 820 {
 821         mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
 822         mlxsw_pci->cmd.comp.out_param =
 823                 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
 824                 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
 825         mlxsw_pci->cmd.wait_done = true;
 826         wake_up(&mlxsw_pci->cmd.wait);
 827 }
 828
 829 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
 830 {
 831         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get);
 832 }
 833
 834 static void mlxsw_pci_eq_tasklet(unsigned long data)
 835 {
 836         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 837         struct mlxsw_pci *mlxsw_pci = q->pci;
 838         u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
 839         unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
 840         char *eqe;
 841         u8 cqn;
 842         bool cq_handle = false;
 843         int items = 0;
 844         int credits = q->count >> 1;
 845
 846         memset(&active_cqns, 0, sizeof(active_cqns));
 847
 848         while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
 849                 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe);
 850
 851                 switch (event_type) {
 852                 case MLXSW_PCI_EQE_EVENT_TYPE_CMD:
 853                         mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
 854                         q->u.eq.ev_cmd_count++;
 855                         break;
 856                 case MLXSW_PCI_EQE_EVENT_TYPE_COMP:
 857                         cqn = mlxsw_pci_eqe_cqn_get(eqe);
 858                         set_bit(cqn, active_cqns);
 859                         cq_handle = true;
 860                         q->u.eq.ev_comp_count++;
 861                         break;
 862                 default:
 863                         q->u.eq.ev_other_count++;
 864                 }
 865                 if (++items == credits)
 866                         break;
 867         }
 868         if (items) {
 869                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 870                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 871         }
 872
 873         if (!cq_handle)
 874                 return;
 875         for_each_set_bit(cqn, active_cqns, cq_count) {
 876                 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
 877                 mlxsw_pci_queue_tasklet_schedule(q);
 878         }
 879 }
 880
 881 struct mlxsw_pci_queue_ops {
 882         const char *name;
 883         enum mlxsw_pci_queue_type type;
 884         int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
 885                     struct mlxsw_pci_queue *q);
 886         void (*fini)(struct mlxsw_pci *mlxsw_pci,
 887                      struct mlxsw_pci_queue *q);
 888         void (*tasklet)(unsigned long data);
 889         int (*dbg_read)(struct seq_file *s, void *data);
 890         u16 elem_count;
 891         u8 elem_size;
 892 };
 893
 894 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
 895         .type           = MLXSW_PCI_QUEUE_TYPE_SDQ,
 896         .init           = mlxsw_pci_sdq_init,
 897         .fini           = mlxsw_pci_sdq_fini,
 898         .dbg_read       = mlxsw_pci_sdq_dbg_read,
 899         .elem_count     = MLXSW_PCI_WQE_COUNT,
 900         .elem_size      = MLXSW_PCI_WQE_SIZE,
 901 };
 902
 903 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
 904         .type           = MLXSW_PCI_QUEUE_TYPE_RDQ,
 905         .init           = mlxsw_pci_rdq_init,
 906         .fini           = mlxsw_pci_rdq_fini,
 907         .dbg_read       = mlxsw_pci_rdq_dbg_read,
 908         .elem_count     = MLXSW_PCI_WQE_COUNT,
 909         .elem_size      = MLXSW_PCI_WQE_SIZE
 910 };
 911
 912 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
 913         .type           = MLXSW_PCI_QUEUE_TYPE_CQ,
 914         .init           = mlxsw_pci_cq_init,
 915         .fini           = mlxsw_pci_cq_fini,
 916         .tasklet        = mlxsw_pci_cq_tasklet,
 917         .dbg_read       = mlxsw_pci_cq_dbg_read,
 918         .elem_count     = MLXSW_PCI_CQE_COUNT,
 919         .elem_size      = MLXSW_PCI_CQE_SIZE
 920 };
 921
 922 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
 923         .type           = MLXSW_PCI_QUEUE_TYPE_EQ,
 924         .init           = mlxsw_pci_eq_init,
 925         .fini           = mlxsw_pci_eq_fini,
 926         .tasklet        = mlxsw_pci_eq_tasklet,
 927         .dbg_read       = mlxsw_pci_eq_dbg_read,
 928         .elem_count     = MLXSW_PCI_EQE_COUNT,
 929         .elem_size      = MLXSW_PCI_EQE_SIZE
 930 };
 931
 932 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 933                                 const struct mlxsw_pci_queue_ops *q_ops,
 934                                 struct mlxsw_pci_queue *q, u8 q_num)
 935 {
 936         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 937         int i;
 938         int err;
 939
 940         spin_lock_init(&q->lock);
 941         q->num = q_num;
 942         q->count = q_ops->elem_count;
 943         q->elem_size = q_ops->elem_size;
 944         q->type = q_ops->type;
 945         q->pci = mlxsw_pci;
 946
 947         if (q_ops->tasklet)
 948                 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
 949
 950         mem_item->size = MLXSW_PCI_AQ_SIZE;
 951         mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
 952                                              mem_item->size,
 953                                              &mem_item->mapaddr);
 954         if (!mem_item->buf)
 955                 return -ENOMEM;
 956         memset(mem_item->buf, 0, mem_item->size);
 957
 958         q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
 959         if (!q->elem_info) {
 960                 err = -ENOMEM;
 961                 goto err_elem_info_alloc;
 962         }
 963
 964         /* Initialize dma mapped elements info elem_info for
 965          * future easy access.
 966          */
 967         for (i = 0; i < q->count; i++) {
 968                 struct mlxsw_pci_queue_elem_info *elem_info;
 969
 970                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 971                 elem_info->elem =
 972                         __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i);
 973         }
 974
 975         mlxsw_cmd_mbox_zero(mbox);
 976         err = q_ops->init(mlxsw_pci, mbox, q);
 977         if (err)
 978                 goto err_q_ops_init;
 979         return 0;
 980
 981 err_q_ops_init:
 982         kfree(q->elem_info);
 983 err_elem_info_alloc:
 984         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 985                             mem_item->buf, mem_item->mapaddr);
 986         return err;
 987 }
 988
 989 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
 990                                  const struct mlxsw_pci_queue_ops *q_ops,
 991                                  struct mlxsw_pci_queue *q)
 992 {
 993         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 994
 995         q_ops->fini(mlxsw_pci, q);
 996         kfree(q->elem_info);
 997         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 998                             mem_item->buf, mem_item->mapaddr);
 999 }
1000
1001 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1002                                       const struct mlxsw_pci_queue_ops *q_ops,
1003                                       u8 num_qs)
1004 {
1005         struct pci_dev *pdev = mlxsw_pci->pdev;
1006         struct mlxsw_pci_queue_type_group *queue_group;
1007         char tmp[16];
1008         int i;
1009         int err;
1010
1011         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1012         queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
1013         if (!queue_group->q)
1014                 return -ENOMEM;
1015
1016         for (i = 0; i < num_qs; i++) {
1017                 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
1018                                            &queue_group->q[i], i);
1019                 if (err)
1020                         goto err_queue_init;
1021         }
1022         queue_group->count = num_qs;
1023
1024         sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type));
1025         debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir,
1026                                     q_ops->dbg_read);
1027
1028         return 0;
1029
1030 err_queue_init:
1031         for (i--; i >= 0; i--)
1032                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1033         kfree(queue_group->q);
1034         return err;
1035 }
1036
1037 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
1038                                        const struct mlxsw_pci_queue_ops *q_ops)
1039 {
1040         struct mlxsw_pci_queue_type_group *queue_group;
1041         int i;
1042
1043         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1044         for (i = 0; i < queue_group->count; i++)
1045                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1046         kfree(queue_group->q);
1047 }
1048
1049 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1050 {
1051         struct pci_dev *pdev = mlxsw_pci->pdev;
1052         u8 num_sdqs;
1053         u8 sdq_log2sz;
1054         u8 num_rdqs;
1055         u8 rdq_log2sz;
1056         u8 num_cqs;
1057         u8 cq_log2sz;
1058         u8 num_eqs;
1059         u8 eq_log2sz;
1060         int err;
1061
1062         mlxsw_cmd_mbox_zero(mbox);
1063         err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1064         if (err)
1065                 return err;
1066
1067         num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1068         sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1069         num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1070         rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1071         num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1072         cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1073         num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1074         eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1075
1076         if (num_sdqs + num_rdqs > num_cqs ||
1077             num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
1078                 dev_err(&pdev->dev, "Unsupported number of queues\n");
1079                 return -EINVAL;
1080         }
1081
1082         if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1083             (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1084             (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) ||
1085             (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
1086                 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
1087                 return -EINVAL;
1088         }
1089
1090         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1091                                          num_eqs);
1092         if (err) {
1093                 dev_err(&pdev->dev, "Failed to initialize event queues\n");
1094                 return err;
1095         }
1096
1097         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1098                                          num_cqs);
1099         if (err) {
1100                 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1101                 goto err_cqs_init;
1102         }
1103
1104         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1105                                          num_sdqs);
1106         if (err) {
1107                 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1108                 goto err_sdqs_init;
1109         }
1110
1111         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1112                                          num_rdqs);
1113         if (err) {
1114                 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1115                 goto err_rdqs_init;
1116         }
1117
1118         /* We have to poll in command interface until queues are initialized */
1119         mlxsw_pci->cmd.nopoll = true;
1120         return 0;
1121
1122 err_rdqs_init:
1123         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1124 err_sdqs_init:
1125         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1126 err_cqs_init:
1127         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1128         return err;
1129 }
1130
1131 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1132 {
1133         mlxsw_pci->cmd.nopoll = false;
1134         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1135         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1136         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1137         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1138 }
1139
1140 static void
1141 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1142                                      char *mbox, int index,
1143                                      const struct mlxsw_swid_config *swid)
1144 {
1145         u8 mask = 0;
1146
1147         if (swid->used_type) {
1148                 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1149                         mbox, index, swid->type);
1150                 mask |= 1;
1151         }
1152         if (swid->used_properties) {
1153                 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1154                         mbox, index, swid->properties);
1155                 mask |= 2;
1156         }
1157         mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1158 }
1159
1160 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1161                                     const struct mlxsw_config_profile *profile)
1162 {
1163         int i;
1164
1165         mlxsw_cmd_mbox_zero(mbox);
1166
1167         if (profile->used_max_vepa_channels) {
1168                 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1169                         mbox, 1);
1170                 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1171                         mbox, profile->max_vepa_channels);
1172         }
1173         if (profile->used_max_lag) {
1174                 mlxsw_cmd_mbox_config_profile_set_max_lag_set(
1175                         mbox, 1);
1176                 mlxsw_cmd_mbox_config_profile_max_lag_set(
1177                         mbox, profile->max_lag);
1178         }
1179         if (profile->used_max_port_per_lag) {
1180                 mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set(
1181                         mbox, 1);
1182                 mlxsw_cmd_mbox_config_profile_max_port_per_lag_set(
1183                         mbox, profile->max_port_per_lag);
1184         }
1185         if (profile->used_max_mid) {
1186                 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1187                         mbox, 1);
1188                 mlxsw_cmd_mbox_config_profile_max_mid_set(
1189                         mbox, profile->max_mid);
1190         }
1191         if (profile->used_max_pgt) {
1192                 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1193                         mbox, 1);
1194                 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1195                         mbox, profile->max_pgt);
1196         }
1197         if (profile->used_max_system_port) {
1198                 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1199                         mbox, 1);
1200                 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1201                         mbox, profile->max_system_port);
1202         }
1203         if (profile->used_max_vlan_groups) {
1204                 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1205                         mbox, 1);
1206                 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1207                         mbox, profile->max_vlan_groups);
1208         }
1209         if (profile->used_max_regions) {
1210                 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1211                         mbox, 1);
1212                 mlxsw_cmd_mbox_config_profile_max_regions_set(
1213                         mbox, profile->max_regions);
1214         }
1215         if (profile->used_flood_tables) {
1216                 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1217                         mbox, 1);
1218                 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1219                         mbox, profile->max_flood_tables);
1220                 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1221                         mbox, profile->max_vid_flood_tables);
1222                 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1223                         mbox, profile->max_fid_offset_flood_tables);
1224                 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1225                         mbox, profile->fid_offset_flood_table_size);
1226                 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1227                         mbox, profile->max_fid_flood_tables);
1228                 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1229                         mbox, profile->fid_flood_table_size);
1230         }
1231         if (profile->used_flood_mode) {
1232                 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1233                         mbox, 1);
1234                 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1235                         mbox, profile->flood_mode);
1236         }
1237         if (profile->used_max_ib_mc) {
1238                 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1239                         mbox, 1);
1240                 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1241                         mbox, profile->max_ib_mc);
1242         }
1243         if (profile->used_max_pkey) {
1244                 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1245                         mbox, 1);
1246                 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1247                         mbox, profile->max_pkey);
1248         }
1249         if (profile->used_ar_sec) {
1250                 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1251                         mbox, 1);
1252                 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1253                         mbox, profile->ar_sec);
1254         }
1255         if (profile->used_adaptive_routing_group_cap) {
1256                 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1257                         mbox, 1);
1258                 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1259                         mbox, profile->adaptive_routing_group_cap);
1260         }
1261
1262         for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1263                 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1264                                                      &profile->swid_config[i]);
1265
1266         return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1267 }
1268
1269 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1270 {
1271         struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1272         int err;
1273
1274         mlxsw_cmd_mbox_zero(mbox);
1275         err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1276         if (err)
1277                 return err;
1278         mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1279         mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1280         return 0;
1281 }
1282
1283 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1284                                   u16 num_pages)
1285 {
1286         struct mlxsw_pci_mem_item *mem_item;
1287         int nent = 0;
1288         int i;
1289         int err;
1290
1291         mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1292                                            GFP_KERNEL);
1293         if (!mlxsw_pci->fw_area.items)
1294                 return -ENOMEM;
1295         mlxsw_pci->fw_area.count = num_pages;
1296
1297         mlxsw_cmd_mbox_zero(mbox);
1298         for (i = 0; i < num_pages; i++) {
1299                 mem_item = &mlxsw_pci->fw_area.items[i];
1300
1301                 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1302                 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1303                                                      mem_item->size,
1304                                                      &mem_item->mapaddr);
1305                 if (!mem_item->buf) {
1306                         err = -ENOMEM;
1307                         goto err_alloc;
1308                 }
1309                 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1310                 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1311                 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1312                         err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1313                         if (err)
1314                                 goto err_cmd_map_fa;
1315                         nent = 0;
1316                         mlxsw_cmd_mbox_zero(mbox);
1317                 }
1318         }
1319
1320         if (nent) {
1321                 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1322                 if (err)
1323                         goto err_cmd_map_fa;
1324         }
1325
1326         return 0;
1327
1328 err_cmd_map_fa:
1329 err_alloc:
1330         for (i--; i >= 0; i--) {
1331                 mem_item = &mlxsw_pci->fw_area.items[i];
1332
1333                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1334                                     mem_item->buf, mem_item->mapaddr);
1335         }
1336         kfree(mlxsw_pci->fw_area.items);
1337         return err;
1338 }
1339
1340 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1341 {
1342         struct mlxsw_pci_mem_item *mem_item;
1343         int i;
1344
1345         mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1346
1347         for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1348                 mem_item = &mlxsw_pci->fw_area.items[i];
1349
1350                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1351                                     mem_item->buf, mem_item->mapaddr);
1352         }
1353         kfree(mlxsw_pci->fw_area.items);
1354 }
1355
1356 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1357 {
1358         struct mlxsw_pci *mlxsw_pci = dev_id;
1359         struct mlxsw_pci_queue *q;
1360         int i;
1361
1362         for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1363                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1364                 mlxsw_pci_queue_tasklet_schedule(q);
1365         }
1366         return IRQ_HANDLED;
1367 }
1368
1369 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1370                                 struct mlxsw_pci_mem_item *mbox)
1371 {
1372         struct pci_dev *pdev = mlxsw_pci->pdev;
1373         int err = 0;
1374
1375         mbox->size = MLXSW_CMD_MBOX_SIZE;
1376         mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1377                                          &mbox->mapaddr);
1378         if (!mbox->buf) {
1379                 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1380                 err = -ENOMEM;
1381         }
1382
1383         return err;
1384 }
1385
1386 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1387                                 struct mlxsw_pci_mem_item *mbox)
1388 {
1389         struct pci_dev *pdev = mlxsw_pci->pdev;
1390
1391         pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1392                             mbox->mapaddr);
1393 }
1394
1395 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1396                           const struct mlxsw_config_profile *profile)
1397 {
1398         struct mlxsw_pci *mlxsw_pci = bus_priv;
1399         struct pci_dev *pdev = mlxsw_pci->pdev;
1400         char *mbox;
1401         u16 num_pages;
1402         int err;
1403
1404         mutex_init(&mlxsw_pci->cmd.lock);
1405         init_waitqueue_head(&mlxsw_pci->cmd.wait);
1406
1407         mlxsw_pci->core = mlxsw_core;
1408
1409         mbox = mlxsw_cmd_mbox_alloc();
1410         if (!mbox)
1411                 return -ENOMEM;
1412
1413         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1414         if (err)
1415                 goto mbox_put;
1416
1417         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1418         if (err)
1419                 goto err_out_mbox_alloc;
1420
1421         err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1422         if (err)
1423                 goto err_query_fw;
1424
1425         mlxsw_pci->bus_info.fw_rev.major =
1426                 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1427         mlxsw_pci->bus_info.fw_rev.minor =
1428                 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1429         mlxsw_pci->bus_info.fw_rev.subminor =
1430                 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1431
1432         if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1433                 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1434                 err = -EINVAL;
1435                 goto err_iface_rev;
1436         }
1437         if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1438                 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1439                 err = -EINVAL;
1440                 goto err_doorbell_page_bar;
1441         }
1442
1443         mlxsw_pci->doorbell_offset =
1444                 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1445
1446         num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1447         err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1448         if (err)
1449                 goto err_fw_area_init;
1450
1451         err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1452         if (err)
1453                 goto err_boardinfo;
1454
1455         err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile);
1456         if (err)
1457                 goto err_config_profile;
1458
1459         err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1460         if (err)
1461                 goto err_aqs_init;
1462
1463         err = request_irq(mlxsw_pci->msix_entry.vector,
1464                           mlxsw_pci_eq_irq_handler, 0,
1465                           mlxsw_pci_driver_name, mlxsw_pci);
1466         if (err) {
1467                 dev_err(&pdev->dev, "IRQ request failed\n");
1468                 goto err_request_eq_irq;
1469         }
1470
1471         goto mbox_put;
1472
1473 err_request_eq_irq:
1474         mlxsw_pci_aqs_fini(mlxsw_pci);
1475 err_aqs_init:
1476 err_config_profile:
1477 err_boardinfo:
1478         mlxsw_pci_fw_area_fini(mlxsw_pci);
1479 err_fw_area_init:
1480 err_doorbell_page_bar:
1481 err_iface_rev:
1482 err_query_fw:
1483         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1484 err_out_mbox_alloc:
1485         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1486 mbox_put:
1487         mlxsw_cmd_mbox_free(mbox);
1488         return err;
1489 }
1490
1491 static void mlxsw_pci_fini(void *bus_priv)
1492 {
1493         struct mlxsw_pci *mlxsw_pci = bus_priv;
1494
1495         free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci);
1496         mlxsw_pci_aqs_fini(mlxsw_pci);
1497         mlxsw_pci_fw_area_fini(mlxsw_pci);
1498         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1499         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1500 }
1501
1502 static struct mlxsw_pci_queue *
1503 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1504                    const struct mlxsw_tx_info *tx_info)
1505 {
1506         u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1507
1508         return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1509 }
1510
1511 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1512                                         const struct mlxsw_tx_info *tx_info)
1513 {
1514         struct mlxsw_pci *mlxsw_pci = bus_priv;
1515         struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1516
1517         return !mlxsw_pci_queue_elem_info_producer_get(q);
1518 }
1519
1520 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1521                                   const struct mlxsw_tx_info *tx_info)
1522 {
1523         struct mlxsw_pci *mlxsw_pci = bus_priv;
1524         struct mlxsw_pci_queue *q;
1525         struct mlxsw_pci_queue_elem_info *elem_info;
1526         char *wqe;
1527         int i;
1528         int err;
1529
1530         if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1531                 err = skb_linearize(skb);
1532                 if (err)
1533                         return err;
1534         }
1535
1536         q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1537         spin_lock_bh(&q->lock);
1538         elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1539         if (!elem_info) {
1540                 /* queue is full */
1541                 err = -EAGAIN;
1542                 goto unlock;
1543         }
1544         elem_info->u.sdq.skb = skb;
1545
1546         wqe = elem_info->elem;
1547         mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1548         mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1549         mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1550
1551         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1552                                      skb_headlen(skb), DMA_TO_DEVICE);
1553         if (err)
1554                 goto unlock;
1555
1556         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1557                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1558
1559                 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1560                                              skb_frag_address(frag),
1561                                              skb_frag_size(frag),
1562                                              DMA_TO_DEVICE);
1563                 if (err)
1564                         goto unmap_frags;
1565         }
1566
1567         /* Set unused sq entries byte count to zero. */
1568         for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1569                 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1570
1571         /* Everything is set up, ring producer doorbell to get HW going */
1572         q->producer_counter++;
1573         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1574
1575         goto unlock;
1576
1577 unmap_frags:
1578         for (; i >= 0; i--)
1579                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1580 unlock:
1581         spin_unlock_bh(&q->lock);
1582         return err;
1583 }
1584
1585 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1586                               u32 in_mod, bool out_mbox_direct,
1587                               char *in_mbox, size_t in_mbox_size,
1588                               char *out_mbox, size_t out_mbox_size,
1589                               u8 *p_status)
1590 {
1591         struct mlxsw_pci *mlxsw_pci = bus_priv;
1592         dma_addr_t in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1593         dma_addr_t out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1594         bool evreq = mlxsw_pci->cmd.nopoll;
1595         unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1596         bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1597         int err;
1598
1599         *p_status = MLXSW_CMD_STATUS_OK;
1600
1601         err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1602         if (err)
1603                 return err;
1604
1605         if (in_mbox)
1606                 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1607         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1608         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1609
1610         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1611         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1612
1613         mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1614         mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1615
1616         *p_wait_done = false;
1617
1618         wmb(); /* all needs to be written before we write control register */
1619         mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1620                           MLXSW_PCI_CIR_CTRL_GO_BIT |
1621                           (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1622                           (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1623                           opcode);
1624
1625         if (!evreq) {
1626                 unsigned long end;
1627
1628                 end = jiffies + timeout;
1629                 do {
1630                         u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1631
1632                         if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1633                                 *p_wait_done = true;
1634                                 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1635                                 break;
1636                         }
1637                         cond_resched();
1638                 } while (time_before(jiffies, end));
1639         } else {
1640                 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1641                 *p_status = mlxsw_pci->cmd.comp.status;
1642         }
1643
1644         err = 0;
1645         if (*p_wait_done) {
1646                 if (*p_status)
1647                         err = -EIO;
1648         } else {
1649                 err = -ETIMEDOUT;
1650         }
1651
1652         if (!err && out_mbox && out_mbox_direct) {
1653                 /* Some commands don't use output param as address to mailbox
1654                  * but they store output directly into registers. In that case,
1655                  * copy registers into mbox buffer.
1656                  */
1657                 __be32 tmp;
1658
1659                 if (!evreq) {
1660                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1661                                                            CIR_OUT_PARAM_HI));
1662                         memcpy(out_mbox, &tmp, sizeof(tmp));
1663                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1664                                                            CIR_OUT_PARAM_LO));
1665                         memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1666                 }
1667         } else if (!err && out_mbox) {
1668                 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1669         }
1670
1671         mutex_unlock(&mlxsw_pci->cmd.lock);
1672
1673         return err;
1674 }
1675
1676 static const struct mlxsw_bus mlxsw_pci_bus = {
1677         .kind                   = "pci",
1678         .init                   = mlxsw_pci_init,
1679         .fini                   = mlxsw_pci_fini,
1680         .skb_transmit_busy      = mlxsw_pci_skb_transmit_busy,
1681         .skb_transmit           = mlxsw_pci_skb_transmit,
1682         .cmd_exec               = mlxsw_pci_cmd_exec,
1683 };
1684
1685 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci)
1686 {
1687         mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT);
1688         /* Current firware does not let us know when the reset is done.
1689          * So we just wait here for constant time and hope for the best.
1690          */
1691         msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1692         return 0;
1693 }
1694
1695 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1696 {
1697         struct mlxsw_pci *mlxsw_pci;
1698         int err;
1699
1700         mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1701         if (!mlxsw_pci)
1702                 return -ENOMEM;
1703
1704         err = pci_enable_device(pdev);
1705         if (err) {
1706                 dev_err(&pdev->dev, "pci_enable_device failed\n");
1707                 goto err_pci_enable_device;
1708         }
1709
1710         err = pci_request_regions(pdev, mlxsw_pci_driver_name);
1711         if (err) {
1712                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1713                 goto err_pci_request_regions;
1714         }
1715
1716         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1717         if (!err) {
1718                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1719                 if (err) {
1720                         dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1721                         goto err_pci_set_dma_mask;
1722                 }
1723         } else {
1724                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1725                 if (err) {
1726                         dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1727                         goto err_pci_set_dma_mask;
1728                 }
1729         }
1730
1731         if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1732                 dev_err(&pdev->dev, "invalid PCI region size\n");
1733                 err = -EINVAL;
1734                 goto err_pci_resource_len_check;
1735         }
1736
1737         mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1738                                      pci_resource_len(pdev, 0));
1739         if (!mlxsw_pci->hw_addr) {
1740                 dev_err(&pdev->dev, "ioremap failed\n");
1741                 err = -EIO;
1742                 goto err_ioremap;
1743         }
1744         pci_set_master(pdev);
1745
1746         mlxsw_pci->pdev = pdev;
1747         pci_set_drvdata(pdev, mlxsw_pci);
1748
1749         err = mlxsw_pci_sw_reset(mlxsw_pci);
1750         if (err) {
1751                 dev_err(&pdev->dev, "Software reset failed\n");
1752                 goto err_sw_reset;
1753         }
1754
1755         err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1);
1756         if (err) {
1757                 dev_err(&pdev->dev, "MSI-X init failed\n");
1758                 goto err_msix_init;
1759         }
1760
1761         mlxsw_pci->bus_info.device_kind = mlxsw_pci_device_kind_get(id);
1762         mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1763         mlxsw_pci->bus_info.dev = &pdev->dev;
1764
1765         mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name,
1766                                                 mlxsw_pci_dbg_root);
1767         if (!mlxsw_pci->dbg_dir) {
1768                 dev_err(&pdev->dev, "Failed to create debugfs dir\n");
1769                 err = -ENOMEM;
1770                 goto err_dbg_create_dir;
1771         }
1772
1773         err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1774                                              &mlxsw_pci_bus, mlxsw_pci);
1775         if (err) {
1776                 dev_err(&pdev->dev, "cannot register bus device\n");
1777                 goto err_bus_device_register;
1778         }
1779
1780         return 0;
1781
1782 err_bus_device_register:
1783         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1784 err_dbg_create_dir:
1785         pci_disable_msix(mlxsw_pci->pdev);
1786 err_msix_init:
1787 err_sw_reset:
1788         iounmap(mlxsw_pci->hw_addr);
1789 err_ioremap:
1790 err_pci_resource_len_check:
1791 err_pci_set_dma_mask:
1792         pci_release_regions(pdev);
1793 err_pci_request_regions:
1794         pci_disable_device(pdev);
1795 err_pci_enable_device:
1796         kfree(mlxsw_pci);
1797         return err;
1798 }
1799
1800 static void mlxsw_pci_remove(struct pci_dev *pdev)
1801 {
1802         struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1803
1804         mlxsw_core_bus_device_unregister(mlxsw_pci->core);
1805         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1806         pci_disable_msix(mlxsw_pci->pdev);
1807         iounmap(mlxsw_pci->hw_addr);
1808         pci_release_regions(mlxsw_pci->pdev);
1809         pci_disable_device(mlxsw_pci->pdev);
1810         kfree(mlxsw_pci);
1811 }
1812
1813 static struct pci_driver mlxsw_pci_driver = {
1814         .name           = mlxsw_pci_driver_name,
1815         .id_table       = mlxsw_pci_id_table,
1816         .probe          = mlxsw_pci_probe,
1817         .remove         = mlxsw_pci_remove,
1818 };
1819
1820 static int __init mlxsw_pci_module_init(void)
1821 {
1822         int err;
1823
1824         mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL);
1825         if (!mlxsw_pci_dbg_root)
1826                 return -ENOMEM;
1827         err = pci_register_driver(&mlxsw_pci_driver);
1828         if (err)
1829                 goto err_register_driver;
1830         return 0;
1831
1832 err_register_driver:
1833         debugfs_remove_recursive(mlxsw_pci_dbg_root);
1834         return err;
1835 }
1836
1837 static void __exit mlxsw_pci_module_exit(void)
1838 {
1839         pci_unregister_driver(&mlxsw_pci_driver);
1840         debugfs_remove_recursive(mlxsw_pci_dbg_root);
1841 }
1842
1843 module_init(mlxsw_pci_module_init);
1844 module_exit(mlxsw_pci_module_exit);
1845
1846 MODULE_LICENSE("Dual BSD/GPL");
1847 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1848 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
1849 MODULE_DEVICE_TABLE(pci, mlxsw_pci_id_table);