2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
56 #ifdef CONFIG_MLX5_CORE_EN
60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
61 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_VERSION(DRIVER_VERSION);
65 unsigned int mlx5_core_debug_mask;
66 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
67 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
69 #define MLX5_DEFAULT_PROF 2
70 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
71 module_param_named(prof_sel, prof_sel, uint, 0444);
72 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
75 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
76 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
79 static struct mlx5_profile profile[] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
178 #define FW_INIT_TIMEOUT_MILI 2000
179 #define FW_INIT_WAIT_MS 2
180 #define FW_PRE_INIT_TIMEOUT_MILI 10000
182 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
184 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
187 while (fw_initializing(dev)) {
188 if (time_after(jiffies, end)) {
192 msleep(FW_INIT_WAIT_MS);
198 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
200 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
202 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
203 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
204 int remaining_size = driver_ver_sz;
207 if (!MLX5_CAP_GEN(dev, driver_version))
210 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
212 strncpy(string, "Linux", remaining_size);
214 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
215 strncat(string, ",", remaining_size);
217 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
218 strncat(string, DRIVER_NAME, remaining_size);
220 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
221 strncat(string, ",", remaining_size);
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, DRIVER_VERSION, remaining_size);
227 MLX5_SET(set_driver_version_in, in, opcode,
228 MLX5_CMD_OP_SET_DRIVER_VERSION);
230 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
233 static int set_dma_caps(struct pci_dev *pdev)
237 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
239 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
240 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
242 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
247 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
250 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
251 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
254 "Can't set consistent PCI DMA mask, aborting\n");
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
265 struct pci_dev *pdev = dev->pdev;
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
274 mutex_unlock(&dev->pci_status_mutex);
279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
281 struct pci_dev *pdev = dev->pdev;
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
288 mutex_unlock(&dev->pci_status_mutex);
291 static int request_bar(struct pci_dev *pdev)
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
300 err = pci_request_regions(pdev, DRIVER_NAME);
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
307 static void release_bar(struct pci_dev *pdev)
309 pci_release_regions(pdev);
312 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
314 struct mlx5_priv *priv = &dev->priv;
315 struct mlx5_eq_table *table = &priv->eq_table;
316 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
320 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
321 MLX5_EQ_VEC_COMP_BASE;
322 nvec = min_t(int, nvec, num_eqs);
323 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
326 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
328 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
329 if (!priv->msix_arr || !priv->irq_info)
332 for (i = 0; i < nvec; i++)
333 priv->msix_arr[i].entry = i;
335 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
336 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
340 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
345 kfree(priv->irq_info);
346 kfree(priv->msix_arr);
350 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
352 struct mlx5_priv *priv = &dev->priv;
354 pci_disable_msix(dev->pdev);
355 kfree(priv->irq_info);
356 kfree(priv->msix_arr);
359 struct mlx5_reg_host_endianess {
365 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
368 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
369 MLX5_DEV_CAP_FLAG_DCT,
372 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
388 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
393 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
394 enum mlx5_cap_type cap_type,
395 enum mlx5_cap_mode cap_mode)
397 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
398 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
399 void *out, *hca_caps;
400 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
403 memset(in, 0, sizeof(in));
404 out = kzalloc(out_sz, GFP_KERNEL);
408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
409 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
410 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
413 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
414 cap_type, cap_mode, err);
418 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
421 case HCA_CAP_OPMOD_GET_MAX:
422 memcpy(dev->caps.hca_max[cap_type], hca_caps,
423 MLX5_UN_SZ_BYTES(hca_cap_union));
425 case HCA_CAP_OPMOD_GET_CUR:
426 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
427 MLX5_UN_SZ_BYTES(hca_cap_union));
431 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
441 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
445 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
448 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
451 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
453 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
455 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
456 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
457 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
460 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
464 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
468 if (MLX5_CAP_GEN(dev, atomic)) {
469 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
478 supported_atomic_req_8B_endianess_mode_1);
480 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
483 set_ctx = kzalloc(set_sz, GFP_KERNEL);
487 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
489 /* Set requestor to host endianness */
490 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
491 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
493 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
499 static int handle_hca_cap(struct mlx5_core_dev *dev)
501 void *set_ctx = NULL;
502 struct mlx5_profile *prof = dev->profile;
504 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
507 set_ctx = kzalloc(set_sz, GFP_KERNEL);
511 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
515 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
517 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
518 MLX5_ST_SZ_BYTES(cmd_hca_cap));
520 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
521 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
523 /* we limit the size of the pkey table to 128 entries for now */
524 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
525 to_fw_pkey_sz(dev, 128));
527 /* Check log_max_qp from HCA caps to set in current profile */
528 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
529 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
530 profile[prof_sel].log_max_qp,
531 MLX5_CAP_GEN_MAX(dev, log_max_qp));
532 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
534 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
535 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
538 /* disable cmdif checksum */
539 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
541 /* Enable 4K UAR only when HCA supports it and page size is bigger
544 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
545 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
547 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
549 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
550 MLX5_SET(cmd_hca_cap,
553 cache_line_size() == 128 ? 1 : 0);
555 err = set_caps(dev, set_ctx, set_sz,
556 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
563 static int set_hca_ctrl(struct mlx5_core_dev *dev)
565 struct mlx5_reg_host_endianess he_in;
566 struct mlx5_reg_host_endianess he_out;
569 if (!mlx5_core_is_pf(dev))
572 memset(&he_in, 0, sizeof(he_in));
573 he_in.he = MLX5_SET_HOST_ENDIANNESS;
574 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
575 &he_out, sizeof(he_out),
576 MLX5_REG_HOST_ENDIANNESS, 0, 1);
580 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
582 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
583 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
585 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
586 MLX5_SET(enable_hca_in, in, function_id, func_id);
587 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
590 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
592 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
593 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
595 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
596 MLX5_SET(disable_hca_in, in, function_id, func_id);
597 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
600 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
602 u32 timer_h, timer_h1, timer_l;
604 timer_h = ioread32be(&dev->iseg->internal_timer_h);
605 timer_l = ioread32be(&dev->iseg->internal_timer_l);
606 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
607 if (timer_h != timer_h1) /* wrap around */
608 timer_l = ioread32be(&dev->iseg->internal_timer_l);
610 return (u64)timer_l | (u64)timer_h1 << 32;
613 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
615 struct mlx5_priv *priv = &mdev->priv;
616 struct msix_entry *msix = priv->msix_arr;
617 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
619 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
620 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
624 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
625 priv->irq_info[i].mask);
627 if (IS_ENABLED(CONFIG_SMP) &&
628 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
629 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
634 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
636 struct mlx5_priv *priv = &mdev->priv;
637 struct msix_entry *msix = priv->msix_arr;
638 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
640 irq_set_affinity_hint(irq, NULL);
641 free_cpumask_var(priv->irq_info[i].mask);
644 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
649 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
650 err = mlx5_irq_set_affinity_hint(mdev, i);
658 for (i--; i >= 0; i--)
659 mlx5_irq_clear_affinity_hint(mdev, i);
664 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
668 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
669 mlx5_irq_clear_affinity_hint(mdev, i);
672 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
675 struct mlx5_eq_table *table = &dev->priv.eq_table;
676 struct mlx5_eq *eq, *n;
679 spin_lock(&table->lock);
680 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
681 if (eq->index == vector) {
688 spin_unlock(&table->lock);
692 EXPORT_SYMBOL(mlx5_vector2eqn);
694 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
696 struct mlx5_eq_table *table = &dev->priv.eq_table;
699 spin_lock(&table->lock);
700 list_for_each_entry(eq, &table->comp_eqs_list, list)
701 if (eq->eqn == eqn) {
702 spin_unlock(&table->lock);
706 spin_unlock(&table->lock);
708 return ERR_PTR(-ENOENT);
711 static void free_comp_eqs(struct mlx5_core_dev *dev)
713 struct mlx5_eq_table *table = &dev->priv.eq_table;
714 struct mlx5_eq *eq, *n;
716 #ifdef CONFIG_RFS_ACCEL
718 free_irq_cpu_rmap(dev->rmap);
722 spin_lock(&table->lock);
723 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
725 spin_unlock(&table->lock);
726 if (mlx5_destroy_unmap_eq(dev, eq))
727 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
730 spin_lock(&table->lock);
732 spin_unlock(&table->lock);
735 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
737 struct mlx5_eq_table *table = &dev->priv.eq_table;
738 char name[MLX5_MAX_IRQ_NAME];
745 INIT_LIST_HEAD(&table->comp_eqs_list);
746 ncomp_vec = table->num_comp_vectors;
747 nent = MLX5_COMP_EQ_SIZE;
748 #ifdef CONFIG_RFS_ACCEL
749 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
753 for (i = 0; i < ncomp_vec; i++) {
754 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
760 #ifdef CONFIG_RFS_ACCEL
761 irq_cpu_rmap_add(dev->rmap,
762 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
764 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
765 err = mlx5_create_map_eq(dev, eq,
766 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
767 name, MLX5_EQ_TYPE_COMP);
772 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
774 spin_lock(&table->lock);
775 list_add_tail(&eq->list, &table->comp_eqs_list);
776 spin_unlock(&table->lock);
786 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
788 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
789 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
793 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
794 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
795 query_out, sizeof(query_out));
800 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
801 if (!status || syndrome == MLX5_DRIVER_SYND) {
802 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
803 err, status, syndrome);
807 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
812 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
814 if (sup_issi & (1 << 1)) {
815 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
816 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
818 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
819 MLX5_SET(set_issi_in, set_in, current_issi, 1);
820 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
821 set_out, sizeof(set_out));
823 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
831 } else if (sup_issi & (1 << 0) || !sup_issi) {
839 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
841 struct pci_dev *pdev = dev->pdev;
844 pci_set_drvdata(dev->pdev, dev);
845 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
846 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
848 mutex_init(&priv->pgdir_mutex);
849 INIT_LIST_HEAD(&priv->pgdir_list);
850 spin_lock_init(&priv->mkey_lock);
852 mutex_init(&priv->alloc_mutex);
854 priv->numa_node = dev_to_node(&dev->pdev->dev);
856 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
860 err = mlx5_pci_enable_device(dev);
862 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
866 err = request_bar(pdev);
868 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
872 pci_set_master(pdev);
874 err = set_dma_caps(pdev);
876 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
880 dev->iseg_base = pci_resource_start(dev->pdev, 0);
881 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
884 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
891 pci_clear_master(dev->pdev);
892 release_bar(dev->pdev);
894 mlx5_pci_disable_device(dev);
897 debugfs_remove(priv->dbg_root);
901 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
904 pci_clear_master(dev->pdev);
905 release_bar(dev->pdev);
906 mlx5_pci_disable_device(dev);
907 debugfs_remove(priv->dbg_root);
910 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
912 struct pci_dev *pdev = dev->pdev;
915 err = mlx5_query_board_id(dev);
917 dev_err(&pdev->dev, "query board id failed\n");
921 err = mlx5_eq_init(dev);
923 dev_err(&pdev->dev, "failed to initialize eq\n");
927 err = mlx5_init_cq_table(dev);
929 dev_err(&pdev->dev, "failed to initialize cq table\n");
933 mlx5_init_qp_table(dev);
935 mlx5_init_srq_table(dev);
937 mlx5_init_mkey_table(dev);
939 err = mlx5_init_rl_table(dev);
941 dev_err(&pdev->dev, "Failed to init rate limiting\n");
942 goto err_tables_cleanup;
945 #ifdef CONFIG_MLX5_CORE_EN
946 err = mlx5_eswitch_init(dev);
948 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
953 err = mlx5_sriov_init(dev);
955 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
956 goto err_eswitch_cleanup;
962 #ifdef CONFIG_MLX5_CORE_EN
963 mlx5_eswitch_cleanup(dev->priv.eswitch);
967 mlx5_cleanup_rl_table(dev);
970 mlx5_cleanup_mkey_table(dev);
971 mlx5_cleanup_srq_table(dev);
972 mlx5_cleanup_qp_table(dev);
973 mlx5_cleanup_cq_table(dev);
976 mlx5_eq_cleanup(dev);
982 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
984 mlx5_sriov_cleanup(dev);
985 #ifdef CONFIG_MLX5_CORE_EN
986 mlx5_eswitch_cleanup(dev->priv.eswitch);
988 mlx5_cleanup_rl_table(dev);
989 mlx5_cleanup_mkey_table(dev);
990 mlx5_cleanup_srq_table(dev);
991 mlx5_cleanup_qp_table(dev);
992 mlx5_cleanup_cq_table(dev);
993 mlx5_eq_cleanup(dev);
996 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
999 struct pci_dev *pdev = dev->pdev;
1002 mutex_lock(&dev->intf_state_mutex);
1003 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1004 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1009 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1010 fw_rev_min(dev), fw_rev_sub(dev));
1012 /* on load removing any previous indication of internal error, device is
1015 dev->state = MLX5_DEVICE_STATE_UP;
1017 /* wait for firmware to accept initialization segments configurations
1019 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1021 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1022 FW_PRE_INIT_TIMEOUT_MILI);
1026 err = mlx5_cmd_init(dev);
1028 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1032 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1034 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1035 FW_INIT_TIMEOUT_MILI);
1036 goto err_cmd_cleanup;
1039 err = mlx5_core_enable_hca(dev, 0);
1041 dev_err(&pdev->dev, "enable hca failed\n");
1042 goto err_cmd_cleanup;
1045 err = mlx5_core_set_issi(dev);
1047 dev_err(&pdev->dev, "failed to set issi\n");
1048 goto err_disable_hca;
1051 err = mlx5_satisfy_startup_pages(dev, 1);
1053 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1054 goto err_disable_hca;
1057 err = set_hca_ctrl(dev);
1059 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1060 goto reclaim_boot_pages;
1063 err = handle_hca_cap(dev);
1065 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1066 goto reclaim_boot_pages;
1069 err = handle_hca_cap_atomic(dev);
1071 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1072 goto reclaim_boot_pages;
1075 err = mlx5_satisfy_startup_pages(dev, 0);
1077 dev_err(&pdev->dev, "failed to allocate init pages\n");
1078 goto reclaim_boot_pages;
1081 err = mlx5_pagealloc_start(dev);
1083 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1084 goto reclaim_boot_pages;
1087 err = mlx5_cmd_init_hca(dev);
1089 dev_err(&pdev->dev, "init hca failed\n");
1090 goto err_pagealloc_stop;
1093 mlx5_set_driver_version(dev);
1095 mlx5_start_health_poll(dev);
1097 err = mlx5_query_hca_caps(dev);
1099 dev_err(&pdev->dev, "query hca failed\n");
1103 if (boot && mlx5_init_once(dev, priv)) {
1104 dev_err(&pdev->dev, "sw objs init failed\n");
1108 err = mlx5_enable_msix(dev);
1110 dev_err(&pdev->dev, "enable msix failed\n");
1111 goto err_cleanup_once;
1114 dev->priv.uar = mlx5_get_uars_page(dev);
1115 if (!dev->priv.uar) {
1116 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1117 goto err_disable_msix;
1120 err = mlx5_start_eqs(dev);
1122 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1126 err = alloc_comp_eqs(dev);
1128 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1132 err = mlx5_irq_set_affinity_hints(dev);
1134 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1135 goto err_affinity_hints;
1138 err = mlx5_init_fs(dev);
1140 dev_err(&pdev->dev, "Failed to init flow steering\n");
1144 #ifdef CONFIG_MLX5_CORE_EN
1145 mlx5_eswitch_attach(dev->priv.eswitch);
1148 err = mlx5_sriov_attach(dev);
1150 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1154 if (mlx5_device_registered(dev)) {
1155 mlx5_attach_device(dev);
1157 err = mlx5_register_device(dev);
1159 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1164 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1165 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1167 mutex_unlock(&dev->intf_state_mutex);
1172 mlx5_sriov_detach(dev);
1175 #ifdef CONFIG_MLX5_CORE_EN
1176 mlx5_eswitch_detach(dev->priv.eswitch);
1178 mlx5_cleanup_fs(dev);
1181 mlx5_irq_clear_affinity_hints(dev);
1190 mlx5_put_uars_page(dev, priv->uar);
1193 mlx5_disable_msix(dev);
1197 mlx5_cleanup_once(dev);
1200 mlx5_stop_health_poll(dev);
1201 if (mlx5_cmd_teardown_hca(dev)) {
1202 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1207 mlx5_pagealloc_stop(dev);
1210 mlx5_reclaim_startup_pages(dev);
1213 mlx5_core_disable_hca(dev, 0);
1216 mlx5_cmd_cleanup(dev);
1219 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1220 mutex_unlock(&dev->intf_state_mutex);
1225 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1231 mlx5_drain_health_wq(dev);
1233 mutex_lock(&dev->intf_state_mutex);
1234 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1235 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1238 mlx5_cleanup_once(dev);
1242 if (mlx5_device_registered(dev))
1243 mlx5_detach_device(dev);
1245 mlx5_sriov_detach(dev);
1246 #ifdef CONFIG_MLX5_CORE_EN
1247 mlx5_eswitch_detach(dev->priv.eswitch);
1249 mlx5_cleanup_fs(dev);
1250 mlx5_irq_clear_affinity_hints(dev);
1253 mlx5_put_uars_page(dev, priv->uar);
1254 mlx5_disable_msix(dev);
1256 mlx5_cleanup_once(dev);
1257 mlx5_stop_health_poll(dev);
1258 err = mlx5_cmd_teardown_hca(dev);
1260 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1263 mlx5_pagealloc_stop(dev);
1264 mlx5_reclaim_startup_pages(dev);
1265 mlx5_core_disable_hca(dev, 0);
1266 mlx5_cmd_cleanup(dev);
1269 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1270 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1271 mutex_unlock(&dev->intf_state_mutex);
1275 struct mlx5_core_event_handler {
1276 void (*event)(struct mlx5_core_dev *dev,
1277 enum mlx5_dev_event event,
1281 static const struct devlink_ops mlx5_devlink_ops = {
1282 #ifdef CONFIG_MLX5_CORE_EN
1283 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1284 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1285 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1286 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1287 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1288 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1292 #define MLX5_IB_MOD "mlx5_ib"
1293 static int init_one(struct pci_dev *pdev,
1294 const struct pci_device_id *id)
1296 struct mlx5_core_dev *dev;
1297 struct devlink *devlink;
1298 struct mlx5_priv *priv;
1301 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1303 dev_err(&pdev->dev, "kzalloc failed\n");
1307 dev = devlink_priv(devlink);
1309 priv->pci_dev_data = id->driver_data;
1311 pci_set_drvdata(pdev, dev);
1314 dev->event = mlx5_core_event;
1315 dev->profile = &profile[prof_sel];
1317 INIT_LIST_HEAD(&priv->ctx_list);
1318 spin_lock_init(&priv->ctx_lock);
1319 mutex_init(&dev->pci_status_mutex);
1320 mutex_init(&dev->intf_state_mutex);
1322 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1323 err = init_srcu_struct(&priv->pfault_srcu);
1325 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1330 mutex_init(&priv->bfregs.reg_head.lock);
1331 mutex_init(&priv->bfregs.wc_head.lock);
1332 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1333 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1335 err = mlx5_pci_init(dev, priv);
1337 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1341 err = mlx5_health_init(dev);
1343 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1347 mlx5_pagealloc_init(dev);
1349 err = mlx5_load_one(dev, priv, true);
1351 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1355 request_module_nowait(MLX5_IB_MOD);
1357 err = devlink_register(devlink, &pdev->dev);
1361 pci_save_state(pdev);
1365 mlx5_unload_one(dev, priv, true);
1367 mlx5_pagealloc_cleanup(dev);
1368 mlx5_health_cleanup(dev);
1370 mlx5_pci_close(dev, priv);
1372 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1373 cleanup_srcu_struct(&priv->pfault_srcu);
1376 pci_set_drvdata(pdev, NULL);
1377 devlink_free(devlink);
1382 static void remove_one(struct pci_dev *pdev)
1384 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1385 struct devlink *devlink = priv_to_devlink(dev);
1386 struct mlx5_priv *priv = &dev->priv;
1388 devlink_unregister(devlink);
1389 mlx5_unregister_device(dev);
1391 if (mlx5_unload_one(dev, priv, true)) {
1392 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1393 mlx5_health_cleanup(dev);
1397 mlx5_pagealloc_cleanup(dev);
1398 mlx5_health_cleanup(dev);
1399 mlx5_pci_close(dev, priv);
1400 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1401 cleanup_srcu_struct(&priv->pfault_srcu);
1403 pci_set_drvdata(pdev, NULL);
1404 devlink_free(devlink);
1407 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1408 pci_channel_state_t state)
1410 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1411 struct mlx5_priv *priv = &dev->priv;
1413 dev_info(&pdev->dev, "%s was called\n", __func__);
1415 mlx5_enter_error_state(dev);
1416 mlx5_unload_one(dev, priv, false);
1417 /* In case of kernel call drain the health wq */
1419 mlx5_drain_health_wq(dev);
1420 mlx5_pci_disable_device(dev);
1423 return state == pci_channel_io_perm_failure ?
1424 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1427 /* wait for the device to show vital signs by waiting
1428 * for the health counter to start counting.
1430 static int wait_vital(struct pci_dev *pdev)
1432 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1433 struct mlx5_core_health *health = &dev->priv.health;
1434 const int niter = 100;
1439 for (i = 0; i < niter; i++) {
1440 count = ioread32be(health->health_counter);
1441 if (count && count != 0xffffffff) {
1442 if (last_count && last_count != count) {
1443 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1454 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1456 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1459 dev_info(&pdev->dev, "%s was called\n", __func__);
1461 err = mlx5_pci_enable_device(dev);
1463 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1465 return PCI_ERS_RESULT_DISCONNECT;
1468 pci_set_master(pdev);
1469 pci_restore_state(pdev);
1470 pci_save_state(pdev);
1472 if (wait_vital(pdev)) {
1473 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1474 return PCI_ERS_RESULT_DISCONNECT;
1477 return PCI_ERS_RESULT_RECOVERED;
1480 static void mlx5_pci_resume(struct pci_dev *pdev)
1482 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1483 struct mlx5_priv *priv = &dev->priv;
1486 dev_info(&pdev->dev, "%s was called\n", __func__);
1488 err = mlx5_load_one(dev, priv, false);
1490 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1493 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1496 static const struct pci_error_handlers mlx5_err_handler = {
1497 .error_detected = mlx5_pci_err_detected,
1498 .slot_reset = mlx5_pci_slot_reset,
1499 .resume = mlx5_pci_resume
1502 static void shutdown(struct pci_dev *pdev)
1504 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1505 struct mlx5_priv *priv = &dev->priv;
1507 dev_info(&pdev->dev, "Shutdown was called\n");
1508 /* Notify mlx5 clients that the kernel is being shut down */
1509 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1510 mlx5_unload_one(dev, priv, false);
1511 mlx5_pci_disable_device(dev);
1514 static const struct pci_device_id mlx5_core_pci_table[] = {
1515 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1516 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1517 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1518 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1519 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1520 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1521 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1522 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1523 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1524 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1525 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1526 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1530 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1532 void mlx5_disable_device(struct mlx5_core_dev *dev)
1534 mlx5_pci_err_detected(dev->pdev, 0);
1537 void mlx5_recover_device(struct mlx5_core_dev *dev)
1539 mlx5_pci_disable_device(dev);
1540 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1541 mlx5_pci_resume(dev->pdev);
1544 static struct pci_driver mlx5_core_driver = {
1545 .name = DRIVER_NAME,
1546 .id_table = mlx5_core_pci_table,
1548 .remove = remove_one,
1549 .shutdown = shutdown,
1550 .err_handler = &mlx5_err_handler,
1551 .sriov_configure = mlx5_core_sriov_configure,
1554 static void mlx5_core_verify_params(void)
1556 if (prof_sel >= ARRAY_SIZE(profile)) {
1557 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1559 ARRAY_SIZE(profile) - 1,
1561 prof_sel = MLX5_DEFAULT_PROF;
1565 static int __init init(void)
1569 mlx5_core_verify_params();
1570 mlx5_register_debugfs();
1572 err = pci_register_driver(&mlx5_core_driver);
1576 #ifdef CONFIG_MLX5_CORE_EN
1583 mlx5_unregister_debugfs();
1587 static void __exit cleanup(void)
1589 #ifdef CONFIG_MLX5_CORE_EN
1592 pci_unregister_driver(&mlx5_core_driver);
1593 mlx5_unregister_debugfs();
1597 module_exit(cleanup);