drivers/net/ethernet/mellanox/mlx5/core/fw.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/driver.h>
  34 #include <linux/mlx5/cmd.h>
  35 #include <linux/mlx5/eswitch.h>
  36 #include <linux/module.h>
  37 #include "mlx5_core.h"
  38 #include "../../mlxfw/mlxfw.h"
  39
  40 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
  41                                   int outlen)
  42 {
  43         u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0};
  44
  45         MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
  46         return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
  47 }
  48
  49 int mlx5_query_board_id(struct mlx5_core_dev *dev)
  50 {
  51         u32 *out;
  52         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  53         int err;
  54
  55         out = kzalloc(outlen, GFP_KERNEL);
  56         if (!out)
  57                 return -ENOMEM;
  58
  59         err = mlx5_cmd_query_adapter(dev, out, outlen);
  60         if (err)
  61                 goto out;
  62
  63         memcpy(dev->board_id,
  64                MLX5_ADDR_OF(query_adapter_out, out,
  65                             query_adapter_struct.vsd_contd_psid),
  66                MLX5_FLD_SZ_BYTES(query_adapter_out,
  67                                  query_adapter_struct.vsd_contd_psid));
  68
  69 out:
  70         kfree(out);
  71         return err;
  72 }
  73
  74 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
  75 {
  76         u32 *out;
  77         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  78         int err;
  79
  80         out = kzalloc(outlen, GFP_KERNEL);
  81         if (!out)
  82                 return -ENOMEM;
  83
  84         err = mlx5_cmd_query_adapter(mdev, out, outlen);
  85         if (err)
  86                 goto out;
  87
  88         *vendor_id = MLX5_GET(query_adapter_out, out,
  89                               query_adapter_struct.ieee_vendor_id);
  90 out:
  91         kfree(out);
  92         return err;
  93 }
  94 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
  95
  96 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
  97 {
  98         return mlx5_query_pcam_reg(dev, dev->caps.pcam,
  99                                    MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
 100                                    MLX5_PCAM_REGS_5000_TO_507F);
 101 }
 102
 103 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
 104 {
 105         return mlx5_query_mcam_reg(dev, dev->caps.mcam,
 106                                    MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
 107                                    MLX5_MCAM_REGS_FIRST_128);
 108 }
 109
 110 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
 111 {
 112         return mlx5_query_qcam_reg(dev, dev->caps.qcam,
 113                                    MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
 114                                    MLX5_QCAM_REGS_FIRST_128);
 115 }
 116
 117 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
 118 {
 119         int err;
 120
 121         err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
 122         if (err)
 123                 return err;
 124
 125         if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
 126                 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
 127                 if (err)
 128                         return err;
 129         }
 130
 131         if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 132                 err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS);
 133                 if (err)
 134                         return err;
 135         }
 136
 137         if (MLX5_CAP_GEN(dev, pg)) {
 138                 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
 139                 if (err)
 140                         return err;
 141         }
 142
 143         if (MLX5_CAP_GEN(dev, atomic)) {
 144                 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
 145                 if (err)
 146                         return err;
 147         }
 148
 149         if (MLX5_CAP_GEN(dev, roce)) {
 150                 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
 151                 if (err)
 152                         return err;
 153         }
 154
 155         if (MLX5_CAP_GEN(dev, nic_flow_table) ||
 156             MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 157                 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
 158                 if (err)
 159                         return err;
 160         }
 161
 162         if (MLX5_CAP_GEN(dev, vport_group_manager) &&
 163             MLX5_ESWITCH_MANAGER(dev)) {
 164                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
 165                 if (err)
 166                         return err;
 167         }
 168
 169         if (MLX5_ESWITCH_MANAGER(dev)) {
 170                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
 171                 if (err)
 172                         return err;
 173         }
 174
 175         if (MLX5_CAP_GEN(dev, vector_calc)) {
 176                 err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC);
 177                 if (err)
 178                         return err;
 179         }
 180
 181         if (MLX5_CAP_GEN(dev, qos)) {
 182                 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
 183                 if (err)
 184                         return err;
 185         }
 186
 187         if (MLX5_CAP_GEN(dev, debug))
 188                 mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
 189
 190         if (MLX5_CAP_GEN(dev, pcam_reg))
 191                 mlx5_get_pcam_reg(dev);
 192
 193         if (MLX5_CAP_GEN(dev, mcam_reg))
 194                 mlx5_get_mcam_reg(dev);
 195
 196         if (MLX5_CAP_GEN(dev, qcam_reg))
 197                 mlx5_get_qcam_reg(dev);
 198
 199         if (MLX5_CAP_GEN(dev, device_memory)) {
 200                 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_MEM);
 201                 if (err)
 202                         return err;
 203         }
 204
 205         return 0;
 206 }
 207
 208 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
 209 {
 210         u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0};
 211         u32 in[MLX5_ST_SZ_DW(init_hca_in)]   = {0};
 212         int i;
 213
 214         MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
 215
 216         if (MLX5_CAP_GEN(dev, sw_owner_id)) {
 217                 for (i = 0; i < 4; i++)
 218                         MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
 219                                        sw_owner_id[i]);
 220         }
 221
 222         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 223 }
 224
 225 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
 226 {
 227         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 228         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)]   = {0};
 229
 230         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 231         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 232 }
 233
 234 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
 235 {
 236         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 237         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 238         int force_state;
 239         int ret;
 240
 241         if (!MLX5_CAP_GEN(dev, force_teardown)) {
 242                 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
 243                 return -EOPNOTSUPP;
 244         }
 245
 246         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 247         MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
 248
 249         ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
 250         if (ret)
 251                 return ret;
 252
 253         force_state = MLX5_GET(teardown_hca_out, out, force_state);
 254         if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
 255                 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
 256                 return -EIO;
 257         }
 258
 259         return 0;
 260 }
 261
 262 enum mlxsw_reg_mcc_instruction {
 263         MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
 264         MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
 265         MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
 266         MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
 267         MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
 268         MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
 269 };
 270
 271 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
 272                             enum mlxsw_reg_mcc_instruction instr,
 273                             u16 component_index, u32 update_handle,
 274                             u32 component_size)
 275 {
 276         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 277         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 278
 279         memset(in, 0, sizeof(in));
 280
 281         MLX5_SET(mcc_reg, in, instruction, instr);
 282         MLX5_SET(mcc_reg, in, component_index, component_index);
 283         MLX5_SET(mcc_reg, in, update_handle, update_handle);
 284         MLX5_SET(mcc_reg, in, component_size, component_size);
 285
 286         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 287                                     sizeof(out), MLX5_REG_MCC, 0, 1);
 288 }
 289
 290 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
 291                               u32 *update_handle, u8 *error_code,
 292                               u8 *control_state)
 293 {
 294         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 295         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 296         int err;
 297
 298         memset(in, 0, sizeof(in));
 299         memset(out, 0, sizeof(out));
 300         MLX5_SET(mcc_reg, in, update_handle, *update_handle);
 301
 302         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 303                                    sizeof(out), MLX5_REG_MCC, 0, 0);
 304         if (err)
 305                 goto out;
 306
 307         *update_handle = MLX5_GET(mcc_reg, out, update_handle);
 308         *error_code = MLX5_GET(mcc_reg, out, error_code);
 309         *control_state = MLX5_GET(mcc_reg, out, control_state);
 310
 311 out:
 312         return err;
 313 }
 314
 315 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
 316                              u32 update_handle,
 317                              u32 offset, u16 size,
 318                              u8 *data)
 319 {
 320         int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
 321         u32 out[MLX5_ST_SZ_DW(mcda_reg)];
 322         int i, j, dw_size = size >> 2;
 323         __be32 data_element;
 324         u32 *in;
 325
 326         in = kzalloc(in_size, GFP_KERNEL);
 327         if (!in)
 328                 return -ENOMEM;
 329
 330         MLX5_SET(mcda_reg, in, update_handle, update_handle);
 331         MLX5_SET(mcda_reg, in, offset, offset);
 332         MLX5_SET(mcda_reg, in, size, size);
 333
 334         for (i = 0; i < dw_size; i++) {
 335                 j = i * 4;
 336                 data_element = htonl(*(u32 *)&data[j]);
 337                 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
 338         }
 339
 340         err = mlx5_core_access_reg(dev, in, in_size, out,
 341                                    sizeof(out), MLX5_REG_MCDA, 0, 1);
 342         kfree(in);
 343         return err;
 344 }
 345
 346 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
 347                                u16 component_index,
 348                                u32 *max_component_size,
 349                                u8 *log_mcda_word_size,
 350                                u16 *mcda_max_write_size)
 351 {
 352         u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
 353         int offset = MLX5_ST_SZ_DW(mcqi_reg);
 354         u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
 355         int err;
 356
 357         memset(in, 0, sizeof(in));
 358         memset(out, 0, sizeof(out));
 359
 360         MLX5_SET(mcqi_reg, in, component_index, component_index);
 361         MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
 362
 363         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 364                                    sizeof(out), MLX5_REG_MCQI, 0, 0);
 365         if (err)
 366                 goto out;
 367
 368         *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
 369         *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
 370         *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
 371
 372 out:
 373         return err;
 374 }
 375
 376 struct mlx5_mlxfw_dev {
 377         struct mlxfw_dev mlxfw_dev;
 378         struct mlx5_core_dev *mlx5_core_dev;
 379 };
 380
 381 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
 382                                 u16 component_index, u32 *p_max_size,
 383                                 u8 *p_align_bits, u16 *p_max_write_size)
 384 {
 385         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 386                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 387         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 388
 389         return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
 390                                    p_align_bits, p_max_write_size);
 391 }
 392
 393 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 394 {
 395         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 396                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 397         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 398         u8 control_state, error_code;
 399         int err;
 400
 401         *fwhandle = 0;
 402         err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
 403         if (err)
 404                 return err;
 405
 406         if (control_state != MLXFW_FSM_STATE_IDLE)
 407                 return -EBUSY;
 408
 409         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 410                                 0, *fwhandle, 0);
 411 }
 412
 413 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 414                                      u16 component_index, u32 component_size)
 415 {
 416         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 417                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 418         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 419
 420         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 421                                 component_index, fwhandle, component_size);
 422 }
 423
 424 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 425                                    u8 *data, u16 size, u32 offset)
 426 {
 427         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 428                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 429         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 430
 431         return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
 432 }
 433
 434 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 435                                      u16 component_index)
 436 {
 437         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 438                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 439         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 440
 441         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 442                                 component_index, fwhandle, 0);
 443 }
 444
 445 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 446 {
 447         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 448                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 449         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 450
 451         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 452                                 fwhandle, 0);
 453 }
 454
 455 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 456                                 enum mlxfw_fsm_state *fsm_state,
 457                                 enum mlxfw_fsm_state_err *fsm_state_err)
 458 {
 459         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 460                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 461         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 462         u8 control_state, error_code;
 463         int err;
 464
 465         err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
 466         if (err)
 467                 return err;
 468
 469         *fsm_state = control_state;
 470         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 471                                MLXFW_FSM_STATE_ERR_MAX);
 472         return 0;
 473 }
 474
 475 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 476 {
 477         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 478                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 479         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 480
 481         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
 482 }
 483
 484 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 485 {
 486         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 487                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 488         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 489
 490         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 491                          fwhandle, 0);
 492 }
 493
 494 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
 495         .component_query        = mlx5_component_query,
 496         .fsm_lock               = mlx5_fsm_lock,
 497         .fsm_component_update   = mlx5_fsm_component_update,
 498         .fsm_block_download     = mlx5_fsm_block_download,
 499         .fsm_component_verify   = mlx5_fsm_component_verify,
 500         .fsm_activate           = mlx5_fsm_activate,
 501         .fsm_query_state        = mlx5_fsm_query_state,
 502         .fsm_cancel             = mlx5_fsm_cancel,
 503         .fsm_release            = mlx5_fsm_release
 504 };
 505
 506 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
 507                         const struct firmware *firmware)
 508 {
 509         struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
 510                 .mlxfw_dev = {
 511                         .ops = &mlx5_mlxfw_dev_ops,
 512                         .psid = dev->board_id,
 513                         .psid_size = strlen(dev->board_id),
 514                 },
 515                 .mlx5_core_dev = dev
 516         };
 517
 518         if (!MLX5_CAP_GEN(dev, mcam_reg)  ||
 519             !MLX5_CAP_MCAM_REG(dev, mcqi) ||
 520             !MLX5_CAP_MCAM_REG(dev, mcc)  ||
 521             !MLX5_CAP_MCAM_REG(dev, mcda)) {
 522                 pr_info("%s flashing isn't supported by the running FW\n", __func__);
 523                 return -EOPNOTSUPP;
 524         }
 525
 526         return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);
 527 }