2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/mlx5_ifc.h>
36 #include <linux/mlx5/vport.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_core.h"
43 #include "lib/devcom.h"
46 /* There are two match-all miss flows, one for unicast dst mac and
49 #define MLX5_ESW_MISS_FLOWS (2)
51 #define fdb_prio_table(esw, chain, prio, level) \
52 (esw)->fdb_table.offloads.fdb_prio[(chain)][(prio)][(level)]
54 #define UPLINK_REP_INDEX 0
56 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
59 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
61 WARN_ON(idx > esw->total_vports - 1);
62 return &esw->offloads.vport_reps[idx];
65 static struct mlx5_flow_table *
66 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
68 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
70 bool mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw)
72 return (!!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED));
75 u32 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw)
77 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
83 u16 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw)
85 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
92 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
93 struct mlx5_flow_spec *spec,
94 struct mlx5_esw_flow_attr *attr)
99 /* Use metadata matching because vport is not represented by single
100 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
103 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
104 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
105 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
106 attr->in_rep->vport));
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET_TO_ONES(fte_match_set_misc2, misc2, metadata_reg_c_0);
111 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
112 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
113 if (memchr_inv(misc, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc)))
114 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
116 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
117 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
119 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
120 MLX5_SET(fte_match_set_misc, misc,
121 source_eswitch_owner_vhca_id,
122 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
124 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
125 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
126 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
127 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
128 source_eswitch_owner_vhca_id);
130 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
133 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
134 attr->in_rep->vport == MLX5_VPORT_UPLINK)
135 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
138 struct mlx5_flow_handle *
139 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
140 struct mlx5_flow_spec *spec,
141 struct mlx5_esw_flow_attr *attr)
143 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
144 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
145 bool split = !!(attr->split_count);
146 struct mlx5_flow_handle *rule;
147 struct mlx5_flow_table *fdb;
150 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
151 return ERR_PTR(-EOPNOTSUPP);
153 flow_act.action = attr->action;
154 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
155 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
156 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
157 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
158 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
159 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
160 flow_act.vlan[0].vid = attr->vlan_vid[0];
161 flow_act.vlan[0].prio = attr->vlan_prio[0];
162 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
163 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
164 flow_act.vlan[1].vid = attr->vlan_vid[1];
165 flow_act.vlan[1].prio = attr->vlan_prio[1];
169 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
170 if (attr->dest_chain) {
171 struct mlx5_flow_table *ft;
173 ft = esw_get_prio_table(esw, attr->dest_chain, 1, 0);
176 goto err_create_goto_table;
179 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
183 for (j = attr->split_count; j < attr->out_count; j++) {
184 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
185 dest[i].vport.num = attr->dests[j].rep->vport;
186 dest[i].vport.vhca_id =
187 MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
188 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
189 dest[i].vport.flags |=
190 MLX5_FLOW_DEST_VPORT_VHCA_ID;
191 if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
192 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
193 flow_act.reformat_id = attr->dests[j].encap_id;
194 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
195 dest[i].vport.reformat_id =
196 attr->dests[j].encap_id;
202 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
203 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
204 dest[i].counter_id = mlx5_fc_id(attr->counter);
208 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
210 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DECAP) {
211 if (attr->tunnel_match_level != MLX5_MATCH_NONE)
212 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
213 if (attr->match_level != MLX5_MATCH_NONE)
214 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
215 } else if (attr->match_level != MLX5_MATCH_NONE) {
216 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
219 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
220 flow_act.modify_id = attr->mod_hdr_id;
222 fdb = esw_get_prio_table(esw, attr->chain, attr->prio, !!split);
224 rule = ERR_CAST(fdb);
228 if (mlx5_eswitch_termtbl_required(esw, &flow_act, spec))
229 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, attr,
232 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
236 esw->offloads.num_flows++;
241 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
243 if (attr->dest_chain)
244 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
245 err_create_goto_table:
249 struct mlx5_flow_handle *
250 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
251 struct mlx5_flow_spec *spec,
252 struct mlx5_esw_flow_attr *attr)
254 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
255 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
256 struct mlx5_flow_table *fast_fdb;
257 struct mlx5_flow_table *fwd_fdb;
258 struct mlx5_flow_handle *rule;
261 fast_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 0);
262 if (IS_ERR(fast_fdb)) {
263 rule = ERR_CAST(fast_fdb);
267 fwd_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 1);
268 if (IS_ERR(fwd_fdb)) {
269 rule = ERR_CAST(fwd_fdb);
273 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
274 for (i = 0; i < attr->split_count; i++) {
275 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
276 dest[i].vport.num = attr->dests[i].rep->vport;
277 dest[i].vport.vhca_id =
278 MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
279 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
280 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
281 if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
282 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
283 dest[i].vport.reformat_id = attr->dests[i].encap_id;
286 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
287 dest[i].ft = fwd_fdb,
290 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
292 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
293 if (attr->match_level != MLX5_MATCH_NONE)
294 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
296 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
301 esw->offloads.num_flows++;
305 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
307 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
313 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
314 struct mlx5_flow_handle *rule,
315 struct mlx5_esw_flow_attr *attr,
318 bool split = (attr->split_count > 0);
321 mlx5_del_flow_rules(rule);
323 /* unref the term table */
324 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
325 if (attr->dests[i].termtbl)
326 mlx5_eswitch_termtbl_put(esw, attr->dests[i].termtbl);
329 esw->offloads.num_flows--;
332 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
333 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
335 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
336 if (attr->dest_chain)
337 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
342 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
343 struct mlx5_flow_handle *rule,
344 struct mlx5_esw_flow_attr *attr)
346 __mlx5_eswitch_del_rule(esw, rule, attr, false);
350 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
351 struct mlx5_flow_handle *rule,
352 struct mlx5_esw_flow_attr *attr)
354 __mlx5_eswitch_del_rule(esw, rule, attr, true);
357 static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
359 struct mlx5_eswitch_rep *rep;
362 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
363 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
364 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
367 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
376 static struct mlx5_eswitch_rep *
377 esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
379 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
381 in_rep = attr->in_rep;
382 out_rep = attr->dests[0].rep;
394 static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
395 bool push, bool pop, bool fwd)
397 struct mlx5_eswitch_rep *in_rep, *out_rep;
399 if ((push || pop) && !fwd)
402 in_rep = attr->in_rep;
403 out_rep = attr->dests[0].rep;
405 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
408 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
411 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
412 if (!push && !pop && fwd)
413 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
416 /* protects against (1) setting rules with different vlans to push and
417 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
419 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
428 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
429 struct mlx5_esw_flow_attr *attr)
431 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
432 struct mlx5_eswitch_rep *vport = NULL;
436 /* nop if we're on the vlan push/pop non emulation mode */
437 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
440 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
441 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
442 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
445 err = esw_add_vlan_action_check(attr, push, pop, fwd);
449 attr->vlan_handled = false;
451 vport = esw_vlan_action_get_vport(attr, push, pop);
453 if (!push && !pop && fwd) {
454 /* tracks VF --> wire rules without vlan push action */
455 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
456 vport->vlan_refcount++;
457 attr->vlan_handled = true;
466 if (!(offloads->vlan_push_pop_refcount)) {
467 /* it's the 1st vlan rule, apply global vlan pop policy */
468 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
472 offloads->vlan_push_pop_refcount++;
475 if (vport->vlan_refcount)
478 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
479 SET_VLAN_INSERT | SET_VLAN_STRIP);
482 vport->vlan = attr->vlan_vid[0];
484 vport->vlan_refcount++;
488 attr->vlan_handled = true;
492 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
493 struct mlx5_esw_flow_attr *attr)
495 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
496 struct mlx5_eswitch_rep *vport = NULL;
500 /* nop if we're on the vlan push/pop non emulation mode */
501 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
504 if (!attr->vlan_handled)
507 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
508 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
509 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
511 vport = esw_vlan_action_get_vport(attr, push, pop);
513 if (!push && !pop && fwd) {
514 /* tracks VF --> wire rules without vlan push action */
515 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
516 vport->vlan_refcount--;
522 vport->vlan_refcount--;
523 if (vport->vlan_refcount)
524 goto skip_unset_push;
527 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
528 0, 0, SET_VLAN_STRIP);
534 offloads->vlan_push_pop_refcount--;
535 if (offloads->vlan_push_pop_refcount)
538 /* no more vlan rules, stop global vlan pop policy */
539 err = esw_set_global_vlan_pop(esw, 0);
545 struct mlx5_flow_handle *
546 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
549 struct mlx5_flow_act flow_act = {0};
550 struct mlx5_flow_destination dest = {};
551 struct mlx5_flow_handle *flow_rule;
552 struct mlx5_flow_spec *spec;
555 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
557 flow_rule = ERR_PTR(-ENOMEM);
561 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
562 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
563 /* source vport is the esw manager */
564 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
566 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
567 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
568 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
570 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
571 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
572 dest.vport.num = vport;
573 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
575 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
576 &flow_act, &dest, 1);
577 if (IS_ERR(flow_rule))
578 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
583 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
585 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
587 mlx5_del_flow_rules(rule);
590 static int mlx5_eswitch_enable_passing_vport_metadata(struct mlx5_eswitch *esw)
592 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
593 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
594 u8 fdb_to_vport_reg_c_id;
597 err = mlx5_eswitch_query_esw_vport_context(esw, esw->manager_vport,
602 fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
603 esw_vport_context.fdb_to_vport_reg_c_id);
605 fdb_to_vport_reg_c_id |= MLX5_FDB_TO_VPORT_REG_C_0;
606 MLX5_SET(modify_esw_vport_context_in, in,
607 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);
609 MLX5_SET(modify_esw_vport_context_in, in,
610 field_select.fdb_to_vport_reg_c_id, 1);
612 return mlx5_eswitch_modify_esw_vport_context(esw, esw->manager_vport,
616 static int mlx5_eswitch_disable_passing_vport_metadata(struct mlx5_eswitch *esw)
618 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
619 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
620 u8 fdb_to_vport_reg_c_id;
623 err = mlx5_eswitch_query_esw_vport_context(esw, esw->manager_vport,
628 fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
629 esw_vport_context.fdb_to_vport_reg_c_id);
631 fdb_to_vport_reg_c_id &= ~MLX5_FDB_TO_VPORT_REG_C_0;
633 MLX5_SET(modify_esw_vport_context_in, in,
634 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);
636 MLX5_SET(modify_esw_vport_context_in, in,
637 field_select.fdb_to_vport_reg_c_id, 1);
639 return mlx5_eswitch_modify_esw_vport_context(esw, esw->manager_vport,
643 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
644 struct mlx5_core_dev *peer_dev,
645 struct mlx5_flow_spec *spec,
646 struct mlx5_flow_destination *dest)
650 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
651 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
653 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
655 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
657 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
660 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
661 MLX5_CAP_GEN(peer_dev, vhca_id));
663 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
665 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
667 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
668 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
669 source_eswitch_owner_vhca_id);
672 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
673 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
674 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
675 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
678 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
679 struct mlx5_eswitch *peer_esw,
680 struct mlx5_flow_spec *spec,
685 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
686 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
688 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
689 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
692 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
694 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
698 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
699 struct mlx5_core_dev *peer_dev)
701 struct mlx5_flow_destination dest = {};
702 struct mlx5_flow_act flow_act = {0};
703 struct mlx5_flow_handle **flows;
704 struct mlx5_flow_handle *flow;
705 struct mlx5_flow_spec *spec;
706 /* total vports is the same for both e-switches */
707 int nvports = esw->total_vports;
711 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
715 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
717 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
720 goto alloc_flows_err;
723 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
724 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
727 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
728 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
729 spec, MLX5_VPORT_PF);
731 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
732 spec, &flow_act, &dest, 1);
735 goto add_pf_flow_err;
737 flows[MLX5_VPORT_PF] = flow;
740 if (mlx5_ecpf_vport_exists(esw->dev)) {
741 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
742 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
743 spec, &flow_act, &dest, 1);
746 goto add_ecpf_flow_err;
748 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
751 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
752 esw_set_peer_miss_rule_source_port(esw,
753 peer_dev->priv.eswitch,
756 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
757 spec, &flow_act, &dest, 1);
760 goto add_vf_flow_err;
765 esw->fdb_table.offloads.peer_miss_rules = flows;
772 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
773 mlx5_del_flow_rules(flows[i]);
775 if (mlx5_ecpf_vport_exists(esw->dev))
776 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
778 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
779 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
781 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
788 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
790 struct mlx5_flow_handle **flows;
793 flows = esw->fdb_table.offloads.peer_miss_rules;
795 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
796 mlx5_core_max_vfs(esw->dev))
797 mlx5_del_flow_rules(flows[i]);
799 if (mlx5_ecpf_vport_exists(esw->dev))
800 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
802 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
803 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
808 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
810 struct mlx5_flow_act flow_act = {0};
811 struct mlx5_flow_destination dest = {};
812 struct mlx5_flow_handle *flow_rule = NULL;
813 struct mlx5_flow_spec *spec;
820 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
826 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
827 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
829 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
830 outer_headers.dmac_47_16);
833 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
834 dest.vport.num = esw->manager_vport;
835 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
837 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
838 &flow_act, &dest, 1);
839 if (IS_ERR(flow_rule)) {
840 err = PTR_ERR(flow_rule);
841 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
845 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
847 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
849 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
850 outer_headers.dmac_47_16);
852 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
853 &flow_act, &dest, 1);
854 if (IS_ERR(flow_rule)) {
855 err = PTR_ERR(flow_rule);
856 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
857 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
861 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
868 #define ESW_OFFLOADS_NUM_GROUPS 4
870 /* Firmware currently has 4 pool of 4 sizes that it supports (ESW_POOLS),
871 * and a virtual memory region of 16M (ESW_SIZE), this region is duplicated
872 * for each flow table pool. We can allocate up to 16M of each pool,
873 * and we keep track of how much we used via put/get_sz_to_pool.
874 * Firmware doesn't report any of this for now.
875 * ESW_POOL is expected to be sorted from large to small
877 #define ESW_SIZE (16 * 1024 * 1024)
878 const unsigned int ESW_POOLS[4] = { 4 * 1024 * 1024, 1 * 1024 * 1024,
879 64 * 1024, 4 * 1024 };
882 get_sz_from_pool(struct mlx5_eswitch *esw)
886 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
887 if (esw->fdb_table.offloads.fdb_left[i]) {
888 --esw->fdb_table.offloads.fdb_left[i];
898 put_sz_to_pool(struct mlx5_eswitch *esw, int sz)
902 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
903 if (sz >= ESW_POOLS[i]) {
904 ++esw->fdb_table.offloads.fdb_left[i];
910 static struct mlx5_flow_table *
911 create_next_size_table(struct mlx5_eswitch *esw,
912 struct mlx5_flow_namespace *ns,
917 struct mlx5_flow_table *fdb;
920 sz = get_sz_from_pool(esw);
922 return ERR_PTR(-ENOSPC);
924 fdb = mlx5_create_auto_grouped_flow_table(ns,
927 ESW_OFFLOADS_NUM_GROUPS,
931 esw_warn(esw->dev, "Failed to create FDB Table err %d (table prio: %d, level: %d, size: %d)\n",
932 (int)PTR_ERR(fdb), table_prio, level, sz);
933 put_sz_to_pool(esw, sz);
939 static struct mlx5_flow_table *
940 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
942 struct mlx5_core_dev *dev = esw->dev;
943 struct mlx5_flow_table *fdb = NULL;
944 struct mlx5_flow_namespace *ns;
945 int table_prio, l = 0;
948 if (chain == FDB_SLOW_PATH_CHAIN)
949 return esw->fdb_table.offloads.slow_fdb;
951 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
953 fdb = fdb_prio_table(esw, chain, prio, level).fdb;
955 /* take ref on earlier levels as well */
957 fdb_prio_table(esw, chain, prio, level--).num_rules++;
958 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
962 ns = mlx5_get_fdb_sub_ns(dev, chain);
964 esw_warn(dev, "Failed to get FDB sub namespace\n");
965 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
966 return ERR_PTR(-EOPNOTSUPP);
969 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
970 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
971 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
973 table_prio = (chain * FDB_MAX_PRIO) + prio - 1;
975 /* create earlier levels for correct fs_core lookup when
978 for (l = 0; l <= level; l++) {
979 if (fdb_prio_table(esw, chain, prio, l).fdb) {
980 fdb_prio_table(esw, chain, prio, l).num_rules++;
984 fdb = create_next_size_table(esw, ns, table_prio, l, flags);
990 fdb_prio_table(esw, chain, prio, l).fdb = fdb;
991 fdb_prio_table(esw, chain, prio, l).num_rules = 1;
994 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
998 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
1000 esw_put_prio_table(esw, chain, prio, l);
1006 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
1010 if (chain == FDB_SLOW_PATH_CHAIN)
1013 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
1015 for (l = level; l >= 0; l--) {
1016 if (--(fdb_prio_table(esw, chain, prio, l).num_rules) > 0)
1019 put_sz_to_pool(esw, fdb_prio_table(esw, chain, prio, l).fdb->max_fte);
1020 mlx5_destroy_flow_table(fdb_prio_table(esw, chain, prio, l).fdb);
1021 fdb_prio_table(esw, chain, prio, l).fdb = NULL;
1024 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
1027 static void esw_destroy_offloads_fast_fdb_tables(struct mlx5_eswitch *esw)
1029 /* If lazy creation isn't supported, deref the fast path tables */
1030 if (!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)) {
1031 esw_put_prio_table(esw, 0, 1, 1);
1032 esw_put_prio_table(esw, 0, 1, 0);
1036 #define MAX_PF_SQ 256
1037 #define MAX_SQ_NVPORTS 32
1039 static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1042 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1046 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1047 MLX5_SET(create_flow_group_in, flow_group_in,
1048 match_criteria_enable,
1049 MLX5_MATCH_MISC_PARAMETERS_2);
1051 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1052 misc_parameters_2.metadata_reg_c_0);
1054 MLX5_SET(create_flow_group_in, flow_group_in,
1055 match_criteria_enable,
1056 MLX5_MATCH_MISC_PARAMETERS);
1058 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1059 misc_parameters.source_port);
1063 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
1065 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1066 struct mlx5_flow_table_attr ft_attr = {};
1067 struct mlx5_core_dev *dev = esw->dev;
1068 u32 *flow_group_in, max_flow_counter;
1069 struct mlx5_flow_namespace *root_ns;
1070 struct mlx5_flow_table *fdb = NULL;
1071 int table_size, ix, err = 0, i;
1072 struct mlx5_flow_group *g;
1073 u32 flags = 0, fdb_max;
1074 void *match_criteria;
1077 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1078 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1082 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1084 esw_warn(dev, "Failed to get FDB flow namespace\n");
1089 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1090 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1091 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1093 esw_debug(dev, "Create offloads FDB table, min (max esw size(2^%d), max counters(%d), groups(%d), max flow table size(2^%d))\n",
1094 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size),
1095 max_flow_counter, ESW_OFFLOADS_NUM_GROUPS,
1098 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++)
1099 esw->fdb_table.offloads.fdb_left[i] =
1100 ESW_POOLS[i] <= fdb_max ? ESW_SIZE / ESW_POOLS[i] : 0;
1102 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1103 MLX5_ESW_MISS_FLOWS + esw->total_vports;
1105 /* create the slow path fdb with encap set, so further table instances
1106 * can be created at run time while VFs are probed if the FW allows that.
1108 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1109 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1110 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1112 ft_attr.flags = flags;
1113 ft_attr.max_fte = table_size;
1114 ft_attr.prio = FDB_SLOW_PATH;
1116 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1119 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1122 esw->fdb_table.offloads.slow_fdb = fdb;
1124 /* If lazy creation isn't supported, open the fast path tables now */
1125 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, multi_fdb_encap) &&
1126 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1127 esw->fdb_table.flags &= ~ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
1128 esw_warn(dev, "Lazy creation of flow tables isn't supported, ignoring priorities\n");
1129 esw_get_prio_table(esw, 0, 1, 0);
1130 esw_get_prio_table(esw, 0, 1, 1);
1132 esw_debug(dev, "Lazy creation of flow tables supported, deferring table opening\n");
1133 esw->fdb_table.flags |= ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
1136 /* create send-to-vport group */
1137 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1138 MLX5_MATCH_MISC_PARAMETERS);
1140 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1142 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1143 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1145 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
1146 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1147 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1149 g = mlx5_create_flow_group(fdb, flow_group_in);
1152 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1153 goto send_vport_err;
1155 esw->fdb_table.offloads.send_to_vport_grp = g;
1157 /* create peer esw miss group */
1158 memset(flow_group_in, 0, inlen);
1160 esw_set_flow_group_source_port(esw, flow_group_in);
1162 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1163 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1167 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1168 misc_parameters.source_eswitch_owner_vhca_id);
1170 MLX5_SET(create_flow_group_in, flow_group_in,
1171 source_eswitch_owner_vhca_id_valid, 1);
1174 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1175 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1176 ix + esw->total_vports - 1);
1177 ix += esw->total_vports;
1179 g = mlx5_create_flow_group(fdb, flow_group_in);
1182 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1185 esw->fdb_table.offloads.peer_miss_grp = g;
1187 /* create miss group */
1188 memset(flow_group_in, 0, inlen);
1189 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1190 MLX5_MATCH_OUTER_HEADERS);
1191 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1193 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1194 outer_headers.dmac_47_16);
1197 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1198 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1199 ix + MLX5_ESW_MISS_FLOWS);
1201 g = mlx5_create_flow_group(fdb, flow_group_in);
1204 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1207 esw->fdb_table.offloads.miss_grp = g;
1209 err = esw_add_fdb_miss_rule(esw);
1213 esw->nvports = nvports;
1214 kvfree(flow_group_in);
1218 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1220 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1222 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1224 esw_destroy_offloads_fast_fdb_tables(esw);
1225 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1228 kvfree(flow_group_in);
1232 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1234 if (!esw->fdb_table.offloads.slow_fdb)
1237 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1238 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1239 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1240 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1241 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1242 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1244 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1245 esw_destroy_offloads_fast_fdb_tables(esw);
1248 static int esw_create_offloads_table(struct mlx5_eswitch *esw, int nvports)
1250 struct mlx5_flow_table_attr ft_attr = {};
1251 struct mlx5_core_dev *dev = esw->dev;
1252 struct mlx5_flow_table *ft_offloads;
1253 struct mlx5_flow_namespace *ns;
1256 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1258 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1262 ft_attr.max_fte = nvports + MLX5_ESW_MISS_FLOWS;
1264 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1265 if (IS_ERR(ft_offloads)) {
1266 err = PTR_ERR(ft_offloads);
1267 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1271 esw->offloads.ft_offloads = ft_offloads;
1275 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1277 struct mlx5_esw_offload *offloads = &esw->offloads;
1279 mlx5_destroy_flow_table(offloads->ft_offloads);
1282 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw, int nvports)
1284 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1285 struct mlx5_flow_group *g;
1289 nvports = nvports + MLX5_ESW_MISS_FLOWS;
1290 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1294 /* create vport rx group */
1295 esw_set_flow_group_source_port(esw, flow_group_in);
1297 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1298 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1300 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1304 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1308 esw->offloads.vport_rx_group = g;
1310 kvfree(flow_group_in);
1314 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1316 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1319 struct mlx5_flow_handle *
1320 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1321 struct mlx5_flow_destination *dest)
1323 struct mlx5_flow_act flow_act = {0};
1324 struct mlx5_flow_handle *flow_rule;
1325 struct mlx5_flow_spec *spec;
1328 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1330 flow_rule = ERR_PTR(-ENOMEM);
1334 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1335 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1336 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1337 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
1339 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
1340 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
1342 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1344 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1345 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1347 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1348 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1350 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1353 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1354 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1355 &flow_act, dest, 1);
1356 if (IS_ERR(flow_rule)) {
1357 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1366 static int esw_offloads_start(struct mlx5_eswitch *esw,
1367 struct netlink_ext_ack *extack)
1371 if (esw->mode != MLX5_ESWITCH_LEGACY &&
1372 !mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1373 NL_SET_ERR_MSG_MOD(extack,
1374 "Can't set offloads mode, SRIOV legacy not enabled");
1378 mlx5_eswitch_disable(esw);
1379 mlx5_eswitch_update_num_of_vfs(esw, esw->dev->priv.sriov.num_vfs);
1380 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
1382 NL_SET_ERR_MSG_MOD(extack,
1383 "Failed setting eswitch to offloads");
1384 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
1386 NL_SET_ERR_MSG_MOD(extack,
1387 "Failed setting eswitch back to legacy");
1390 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1391 if (mlx5_eswitch_inline_mode_get(esw,
1392 &esw->offloads.inline_mode)) {
1393 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
1394 NL_SET_ERR_MSG_MOD(extack,
1395 "Inline mode is different between vports");
1401 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1403 kfree(esw->offloads.vport_reps);
1406 int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1408 int total_vports = esw->total_vports;
1409 struct mlx5_core_dev *dev = esw->dev;
1410 struct mlx5_eswitch_rep *rep;
1411 u8 hw_id[ETH_ALEN], rep_type;
1414 esw->offloads.vport_reps = kcalloc(total_vports,
1415 sizeof(struct mlx5_eswitch_rep),
1417 if (!esw->offloads.vport_reps)
1420 mlx5_query_mac_address(dev, hw_id);
1422 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1423 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
1424 rep->vport_index = vport_index;
1425 ether_addr_copy(rep->hw_id, hw_id);
1427 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1428 atomic_set(&rep->rep_data[rep_type].state,
1435 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1436 struct mlx5_eswitch_rep *rep, u8 rep_type)
1438 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1439 REP_LOADED, REP_REGISTERED) == REP_LOADED)
1440 esw->offloads.rep_ops[rep_type]->unload(rep);
1443 static void __unload_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1445 struct mlx5_eswitch_rep *rep;
1447 if (mlx5_ecpf_vport_exists(esw->dev)) {
1448 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1449 __esw_offloads_unload_rep(esw, rep, rep_type);
1452 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1453 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1454 __esw_offloads_unload_rep(esw, rep, rep_type);
1457 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1458 __esw_offloads_unload_rep(esw, rep, rep_type);
1461 static void __unload_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1464 struct mlx5_eswitch_rep *rep;
1467 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvports)
1468 __esw_offloads_unload_rep(esw, rep, rep_type);
1471 static void esw_offloads_unload_vf_reps(struct mlx5_eswitch *esw, int nvports)
1473 u8 rep_type = NUM_REP_TYPES;
1475 while (rep_type-- > 0)
1476 __unload_reps_vf_vport(esw, nvports, rep_type);
1479 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1481 __unload_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1483 /* Special vports must be the last to unload. */
1484 __unload_reps_special_vport(esw, rep_type);
1487 static void esw_offloads_unload_all_reps(struct mlx5_eswitch *esw)
1489 u8 rep_type = NUM_REP_TYPES;
1491 while (rep_type-- > 0)
1492 __unload_reps_all_vport(esw, rep_type);
1495 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
1496 struct mlx5_eswitch_rep *rep, u8 rep_type)
1500 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1501 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1502 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1504 atomic_set(&rep->rep_data[rep_type].state,
1511 static int __load_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1513 struct mlx5_eswitch_rep *rep;
1516 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1517 err = __esw_offloads_load_rep(esw, rep, rep_type);
1521 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1522 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1523 err = __esw_offloads_load_rep(esw, rep, rep_type);
1528 if (mlx5_ecpf_vport_exists(esw->dev)) {
1529 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1530 err = __esw_offloads_load_rep(esw, rep, rep_type);
1538 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1539 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1540 __esw_offloads_unload_rep(esw, rep, rep_type);
1544 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1545 __esw_offloads_unload_rep(esw, rep, rep_type);
1549 static int __load_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1552 struct mlx5_eswitch_rep *rep;
1555 mlx5_esw_for_each_vf_rep(esw, i, rep, nvports) {
1556 err = __esw_offloads_load_rep(esw, rep, rep_type);
1564 __unload_reps_vf_vport(esw, --i, rep_type);
1568 static int __load_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1572 /* Special vports must be loaded first, uplink rep creates mdev resource. */
1573 err = __load_reps_special_vport(esw, rep_type);
1577 err = __load_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1584 __unload_reps_special_vport(esw, rep_type);
1588 static int esw_offloads_load_vf_reps(struct mlx5_eswitch *esw, int nvports)
1593 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1594 err = __load_reps_vf_vport(esw, nvports, rep_type);
1602 while (rep_type-- > 0)
1603 __unload_reps_vf_vport(esw, nvports, rep_type);
1607 static int esw_offloads_load_all_reps(struct mlx5_eswitch *esw)
1612 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1613 err = __load_reps_all_vport(esw, rep_type);
1621 while (rep_type-- > 0)
1622 __unload_reps_all_vport(esw, rep_type);
1626 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
1627 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1629 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1630 struct mlx5_eswitch *peer_esw)
1634 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1641 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1643 mlx5e_tc_clean_fdb_peer_flows(esw);
1644 esw_del_fdb_peer_miss_rules(esw);
1647 static int mlx5_esw_offloads_devcom_event(int event,
1651 struct mlx5_eswitch *esw = my_data;
1652 struct mlx5_eswitch *peer_esw = event_data;
1653 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1657 case ESW_OFFLOADS_DEVCOM_PAIR:
1658 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1659 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1662 err = mlx5_esw_offloads_pair(esw, peer_esw);
1666 err = mlx5_esw_offloads_pair(peer_esw, esw);
1670 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1673 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1674 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1677 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1678 mlx5_esw_offloads_unpair(peer_esw);
1679 mlx5_esw_offloads_unpair(esw);
1686 mlx5_esw_offloads_unpair(esw);
1689 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1694 static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1696 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1698 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1699 mutex_init(&esw->offloads.peer_mutex);
1701 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1704 mlx5_devcom_register_component(devcom,
1705 MLX5_DEVCOM_ESW_OFFLOADS,
1706 mlx5_esw_offloads_devcom_event,
1709 mlx5_devcom_send_event(devcom,
1710 MLX5_DEVCOM_ESW_OFFLOADS,
1711 ESW_OFFLOADS_DEVCOM_PAIR, esw);
1714 static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
1716 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1718 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1721 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1722 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
1724 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1727 static int esw_vport_ingress_prio_tag_config(struct mlx5_eswitch *esw,
1728 struct mlx5_vport *vport)
1730 struct mlx5_flow_act flow_act = {0};
1731 struct mlx5_flow_spec *spec;
1734 /* For prio tag mode, there is only 1 FTEs:
1735 * 1) Untagged packets - push prio tag VLAN and modify metadata if
1737 * Unmatched traffic is allowed by default
1740 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1746 /* Untagged packets - push prio tag VLAN, allow */
1747 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1748 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 0);
1749 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1750 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
1751 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1752 flow_act.vlan[0].ethtype = ETH_P_8021Q;
1753 flow_act.vlan[0].vid = 0;
1754 flow_act.vlan[0].prio = 0;
1756 if (vport->ingress.modify_metadata_rule) {
1757 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1758 flow_act.modify_id = vport->ingress.modify_metadata_id;
1761 vport->ingress.allow_rule =
1762 mlx5_add_flow_rules(vport->ingress.acl, spec,
1763 &flow_act, NULL, 0);
1764 if (IS_ERR(vport->ingress.allow_rule)) {
1765 err = PTR_ERR(vport->ingress.allow_rule);
1767 "vport[%d] configure ingress untagged allow rule, err(%d)\n",
1769 vport->ingress.allow_rule = NULL;
1777 esw_vport_cleanup_ingress_rules(esw, vport);
1781 static int esw_vport_add_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1782 struct mlx5_vport *vport)
1784 u8 action[MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)] = {};
1785 static const struct mlx5_flow_spec spec = {};
1786 struct mlx5_flow_act flow_act = {};
1789 MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET);
1790 MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_C_0);
1791 MLX5_SET(set_action_in, action, data,
1792 mlx5_eswitch_get_vport_metadata_for_match(esw, vport->vport));
1794 err = mlx5_modify_header_alloc(esw->dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS,
1795 1, action, &vport->ingress.modify_metadata_id);
1798 "failed to alloc modify header for vport %d ingress acl (%d)\n",
1803 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1804 flow_act.modify_id = vport->ingress.modify_metadata_id;
1805 vport->ingress.modify_metadata_rule = mlx5_add_flow_rules(vport->ingress.acl,
1806 &spec, &flow_act, NULL, 0);
1807 if (IS_ERR(vport->ingress.modify_metadata_rule)) {
1808 err = PTR_ERR(vport->ingress.modify_metadata_rule);
1810 "failed to add setting metadata rule for vport %d ingress acl, err(%d)\n",
1812 vport->ingress.modify_metadata_rule = NULL;
1818 mlx5_modify_header_dealloc(esw->dev, vport->ingress.modify_metadata_id);
1822 void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1823 struct mlx5_vport *vport)
1825 if (vport->ingress.modify_metadata_rule) {
1826 mlx5_del_flow_rules(vport->ingress.modify_metadata_rule);
1827 mlx5_modify_header_dealloc(esw->dev, vport->ingress.modify_metadata_id);
1829 vport->ingress.modify_metadata_rule = NULL;
1833 static int esw_vport_egress_prio_tag_config(struct mlx5_eswitch *esw,
1834 struct mlx5_vport *vport)
1836 struct mlx5_flow_act flow_act = {0};
1837 struct mlx5_flow_spec *spec;
1840 if (!MLX5_CAP_GEN(esw->dev, prio_tag_required))
1843 /* For prio tag mode, there is only 1 FTEs:
1844 * 1) prio tag packets - pop the prio tag VLAN, allow
1845 * Unmatched traffic is allowed by default
1848 esw_vport_cleanup_egress_rules(esw, vport);
1850 err = esw_vport_enable_egress_acl(esw, vport);
1852 mlx5_core_warn(esw->dev,
1853 "failed to enable egress acl (%d) on vport[%d]\n",
1859 "vport[%d] configure prio tag egress rules\n", vport->vport);
1861 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1867 /* prio tag vlan rule - pop it so VF receives untagged packets */
1868 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1869 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag);
1870 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1871 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, 0);
1873 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1874 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
1875 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1876 vport->egress.allowed_vlan =
1877 mlx5_add_flow_rules(vport->egress.acl, spec,
1878 &flow_act, NULL, 0);
1879 if (IS_ERR(vport->egress.allowed_vlan)) {
1880 err = PTR_ERR(vport->egress.allowed_vlan);
1882 "vport[%d] configure egress pop prio tag vlan rule failed, err(%d)\n",
1884 vport->egress.allowed_vlan = NULL;
1892 esw_vport_cleanup_egress_rules(esw, vport);
1896 static int esw_vport_ingress_common_config(struct mlx5_eswitch *esw,
1897 struct mlx5_vport *vport)
1901 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1902 !MLX5_CAP_GEN(esw->dev, prio_tag_required))
1905 esw_vport_cleanup_ingress_rules(esw, vport);
1907 err = esw_vport_enable_ingress_acl(esw, vport);
1910 "failed to enable ingress acl (%d) on vport[%d]\n",
1916 "vport[%d] configure ingress rules\n", vport->vport);
1918 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1919 err = esw_vport_add_ingress_acl_modify_metadata(esw, vport);
1924 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
1925 mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
1926 err = esw_vport_ingress_prio_tag_config(esw, vport);
1933 esw_vport_disable_ingress_acl(esw, vport);
1938 esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
1940 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
1943 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1944 MLX5_FDB_TO_VPORT_REG_C_0))
1947 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
1950 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
1951 mlx5_ecpf_vport_exists(esw->dev))
1957 static int esw_create_offloads_acl_tables(struct mlx5_eswitch *esw)
1959 struct mlx5_vport *vport;
1963 if (esw_check_vport_match_metadata_supported(esw))
1964 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
1966 mlx5_esw_for_all_vports(esw, i, vport) {
1967 err = esw_vport_ingress_common_config(esw, vport);
1971 if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
1972 err = esw_vport_egress_prio_tag_config(esw, vport);
1978 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
1979 esw_info(esw->dev, "Use metadata reg_c as source vport to match\n");
1984 esw_vport_disable_ingress_acl(esw, vport);
1986 for (j = MLX5_VPORT_PF; j < i; j++) {
1987 vport = &esw->vports[j];
1988 esw_vport_disable_egress_acl(esw, vport);
1989 esw_vport_disable_ingress_acl(esw, vport);
1995 static void esw_destroy_offloads_acl_tables(struct mlx5_eswitch *esw)
1997 struct mlx5_vport *vport;
2000 mlx5_esw_for_all_vports(esw, i, vport) {
2001 esw_vport_disable_egress_acl(esw, vport);
2002 esw_vport_disable_ingress_acl(esw, vport);
2005 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2008 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
2010 int num_vfs = esw->esw_funcs.num_vfs;
2014 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
2015 total_vports = esw->total_vports;
2017 total_vports = num_vfs + MLX5_SPECIAL_VPORTS(esw->dev);
2019 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
2020 mutex_init(&esw->fdb_table.offloads.fdb_prio_lock);
2022 err = esw_create_offloads_acl_tables(esw);
2026 err = esw_create_offloads_fdb_tables(esw, total_vports);
2028 goto create_fdb_err;
2030 err = esw_create_offloads_table(esw, total_vports);
2034 err = esw_create_vport_rx_group(esw, total_vports);
2041 esw_destroy_offloads_table(esw);
2044 esw_destroy_offloads_fdb_tables(esw);
2047 esw_destroy_offloads_acl_tables(esw);
2052 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2054 esw_destroy_vport_rx_group(esw);
2055 esw_destroy_offloads_table(esw);
2056 esw_destroy_offloads_fdb_tables(esw);
2057 esw_destroy_offloads_acl_tables(esw);
2061 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
2063 bool host_pf_disabled;
2066 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2067 host_params_context.host_num_of_vfs);
2068 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2069 host_params_context.host_pf_disabled);
2071 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2074 /* Number of VFs can only change from "0 to x" or "x to 0". */
2075 if (esw->esw_funcs.num_vfs > 0) {
2076 esw_offloads_unload_vf_reps(esw, esw->esw_funcs.num_vfs);
2080 err = esw_offloads_load_vf_reps(esw, new_num_vfs);
2084 esw->esw_funcs.num_vfs = new_num_vfs;
2087 static void esw_functions_changed_event_handler(struct work_struct *work)
2089 struct mlx5_host_work *host_work;
2090 struct mlx5_eswitch *esw;
2093 host_work = container_of(work, struct mlx5_host_work, work);
2094 esw = host_work->esw;
2096 out = mlx5_esw_query_functions(esw->dev);
2100 esw_vfs_changed_event_handler(esw, out);
2106 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
2108 struct mlx5_esw_functions *esw_funcs;
2109 struct mlx5_host_work *host_work;
2110 struct mlx5_eswitch *esw;
2112 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2116 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2117 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
2119 host_work->esw = esw;
2121 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
2122 queue_work(esw->work_queue, &host_work->work);
2127 int esw_offloads_init(struct mlx5_eswitch *esw)
2131 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2132 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2133 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2135 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2137 err = esw_offloads_steering_init(esw);
2141 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2142 err = mlx5_eswitch_enable_passing_vport_metadata(esw);
2144 goto err_vport_metadata;
2147 err = esw_offloads_load_all_reps(esw);
2151 esw_offloads_devcom_init(esw);
2152 mutex_init(&esw->offloads.termtbl_mutex);
2154 mlx5_rdma_enable_roce(esw->dev);
2159 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
2160 mlx5_eswitch_disable_passing_vport_metadata(esw);
2162 esw_offloads_steering_cleanup(esw);
2166 static int esw_offloads_stop(struct mlx5_eswitch *esw,
2167 struct netlink_ext_ack *extack)
2171 mlx5_eswitch_disable(esw);
2172 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
2174 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
2175 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
2177 NL_SET_ERR_MSG_MOD(extack,
2178 "Failed setting eswitch back to offloads");
2185 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2187 mlx5_rdma_disable_roce(esw->dev);
2188 esw_offloads_devcom_cleanup(esw);
2189 esw_offloads_unload_all_reps(esw);
2190 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
2191 mlx5_eswitch_disable_passing_vport_metadata(esw);
2192 esw_offloads_steering_cleanup(esw);
2193 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2196 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
2199 case DEVLINK_ESWITCH_MODE_LEGACY:
2200 *mlx5_mode = MLX5_ESWITCH_LEGACY;
2202 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
2203 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
2212 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2214 switch (mlx5_mode) {
2215 case MLX5_ESWITCH_LEGACY:
2216 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2218 case MLX5_ESWITCH_OFFLOADS:
2219 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2228 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2231 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2232 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2234 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2235 *mlx5_mode = MLX5_INLINE_MODE_L2;
2237 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2238 *mlx5_mode = MLX5_INLINE_MODE_IP;
2240 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2241 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2250 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2252 switch (mlx5_mode) {
2253 case MLX5_INLINE_MODE_NONE:
2254 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2256 case MLX5_INLINE_MODE_L2:
2257 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2259 case MLX5_INLINE_MODE_IP:
2260 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2262 case MLX5_INLINE_MODE_TCP_UDP:
2263 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2272 static int mlx5_devlink_eswitch_check(struct devlink *devlink)
2274 struct mlx5_core_dev *dev = devlink_priv(devlink);
2276 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2279 if(!MLX5_ESWITCH_MANAGER(dev))
2282 if (dev->priv.eswitch->mode == MLX5_ESWITCH_NONE &&
2283 !mlx5_core_is_ecpf_esw_manager(dev))
2289 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2290 struct netlink_ext_ack *extack)
2292 struct mlx5_core_dev *dev = devlink_priv(devlink);
2293 u16 cur_mlx5_mode, mlx5_mode = 0;
2296 err = mlx5_devlink_eswitch_check(devlink);
2300 cur_mlx5_mode = dev->priv.eswitch->mode;
2302 if (esw_mode_from_devlink(mode, &mlx5_mode))
2305 if (cur_mlx5_mode == mlx5_mode)
2308 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
2309 return esw_offloads_start(dev->priv.eswitch, extack);
2310 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
2311 return esw_offloads_stop(dev->priv.eswitch, extack);
2316 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2318 struct mlx5_core_dev *dev = devlink_priv(devlink);
2321 err = mlx5_devlink_eswitch_check(devlink);
2325 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
2328 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2329 struct netlink_ext_ack *extack)
2331 struct mlx5_core_dev *dev = devlink_priv(devlink);
2332 struct mlx5_eswitch *esw = dev->priv.eswitch;
2333 int err, vport, num_vport;
2336 err = mlx5_devlink_eswitch_check(devlink);
2340 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2341 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2342 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
2345 case MLX5_CAP_INLINE_MODE_L2:
2346 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
2348 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2352 if (esw->offloads.num_flows > 0) {
2353 NL_SET_ERR_MSG_MOD(extack,
2354 "Can't set inline mode when flows are configured");
2358 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2362 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2363 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2365 NL_SET_ERR_MSG_MOD(extack,
2366 "Failed to set min inline on vport");
2367 goto revert_inline_mode;
2371 esw->offloads.inline_mode = mlx5_mode;
2375 num_vport = --vport;
2376 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
2377 mlx5_modify_nic_vport_min_inline(dev,
2379 esw->offloads.inline_mode);
2384 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2386 struct mlx5_core_dev *dev = devlink_priv(devlink);
2387 struct mlx5_eswitch *esw = dev->priv.eswitch;
2390 err = mlx5_devlink_eswitch_check(devlink);
2394 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2397 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2399 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2400 struct mlx5_core_dev *dev = esw->dev;
2403 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2406 if (esw->mode == MLX5_ESWITCH_NONE)
2409 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2410 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2411 mlx5_mode = MLX5_INLINE_MODE_NONE;
2413 case MLX5_CAP_INLINE_MODE_L2:
2414 mlx5_mode = MLX5_INLINE_MODE_L2;
2416 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2421 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2422 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2423 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
2424 if (prev_mlx5_mode != mlx5_mode)
2426 prev_mlx5_mode = mlx5_mode;
2434 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2435 enum devlink_eswitch_encap_mode encap,
2436 struct netlink_ext_ack *extack)
2438 struct mlx5_core_dev *dev = devlink_priv(devlink);
2439 struct mlx5_eswitch *esw = dev->priv.eswitch;
2442 err = mlx5_devlink_eswitch_check(devlink);
2446 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
2447 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
2448 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)))
2451 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC)
2454 if (esw->mode == MLX5_ESWITCH_LEGACY) {
2455 esw->offloads.encap = encap;
2459 if (esw->offloads.encap == encap)
2462 if (esw->offloads.num_flows > 0) {
2463 NL_SET_ERR_MSG_MOD(extack,
2464 "Can't set encapsulation when flows are configured");
2468 esw_destroy_offloads_fdb_tables(esw);
2470 esw->offloads.encap = encap;
2472 err = esw_create_offloads_fdb_tables(esw, esw->nvports);
2475 NL_SET_ERR_MSG_MOD(extack,
2476 "Failed re-creating fast FDB table");
2477 esw->offloads.encap = !encap;
2478 (void)esw_create_offloads_fdb_tables(esw, esw->nvports);
2484 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2485 enum devlink_eswitch_encap_mode *encap)
2487 struct mlx5_core_dev *dev = devlink_priv(devlink);
2488 struct mlx5_eswitch *esw = dev->priv.eswitch;
2491 err = mlx5_devlink_eswitch_check(devlink);
2495 *encap = esw->offloads.encap;
2499 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
2500 const struct mlx5_eswitch_rep_ops *ops,
2503 struct mlx5_eswitch_rep_data *rep_data;
2504 struct mlx5_eswitch_rep *rep;
2507 esw->offloads.rep_ops[rep_type] = ops;
2508 mlx5_esw_for_all_reps(esw, i, rep) {
2509 rep_data = &rep->rep_data[rep_type];
2510 atomic_set(&rep_data->state, REP_REGISTERED);
2513 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
2515 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
2517 struct mlx5_eswitch_rep *rep;
2520 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
2521 __unload_reps_all_vport(esw, rep_type);
2523 mlx5_esw_for_all_reps(esw, i, rep)
2524 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2526 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
2528 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
2530 struct mlx5_eswitch_rep *rep;
2532 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2533 return rep->rep_data[rep_type].priv;
2536 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
2540 struct mlx5_eswitch_rep *rep;
2542 rep = mlx5_eswitch_get_rep(esw, vport);
2544 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2545 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2546 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
2549 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
2551 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2553 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
2555 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2557 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
2560 return mlx5_eswitch_get_rep(esw, vport);
2562 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
2564 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2566 return vport_num >= MLX5_VPORT_FIRST_VF &&
2567 vport_num <= esw->dev->priv.sriov.max_vfs;
2570 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2572 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2574 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2576 u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,
2579 return ((MLX5_CAP_GEN(esw->dev, vhca_id) & 0xffff) << 16) | vport_num;
2581 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);