2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/mlx5_ifc.h>
36 #include <linux/mlx5/vport.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_core.h"
46 struct mlx5_flow_handle *
47 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
48 struct mlx5_flow_spec *spec,
49 struct mlx5_esw_flow_attr *attr)
51 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
52 struct mlx5_flow_act flow_act = {0};
53 struct mlx5_flow_table *ft = NULL;
54 struct mlx5_fc *counter = NULL;
55 struct mlx5_flow_handle *rule;
59 if (esw->mode != SRIOV_OFFLOADS)
60 return ERR_PTR(-EOPNOTSUPP);
62 if (attr->mirror_count)
63 ft = esw->fdb_table.offloads.fwd_fdb;
65 ft = esw->fdb_table.offloads.fast_fdb;
67 flow_act.action = attr->action;
68 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
69 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
70 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
71 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
72 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
73 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
74 flow_act.vlan[0].vid = attr->vlan_vid[0];
75 flow_act.vlan[0].prio = attr->vlan_prio[0];
76 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
77 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
78 flow_act.vlan[1].vid = attr->vlan_vid[1];
79 flow_act.vlan[1].prio = attr->vlan_prio[1];
83 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
84 for (j = attr->mirror_count; j < attr->out_count; j++) {
85 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
86 dest[i].vport.num = attr->out_rep[j]->vport;
87 dest[i].vport.vhca_id =
88 MLX5_CAP_GEN(attr->out_mdev[j], vhca_id);
89 dest[i].vport.vhca_id_valid = !!MLX5_CAP_ESW(esw->dev, merged_eswitch);
93 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
94 counter = mlx5_fc_create(esw->dev, true);
95 if (IS_ERR(counter)) {
96 rule = ERR_CAST(counter);
97 goto err_counter_alloc;
99 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
100 dest[i].counter = counter;
104 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
105 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
107 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
108 MLX5_SET(fte_match_set_misc, misc,
109 source_eswitch_owner_vhca_id,
110 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
112 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
113 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
114 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
115 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
116 source_eswitch_owner_vhca_id);
118 if (attr->match_level == MLX5_MATCH_NONE)
119 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
121 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS |
122 MLX5_MATCH_MISC_PARAMETERS;
124 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
125 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
127 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
128 flow_act.modify_id = attr->mod_hdr_id;
130 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
131 flow_act.encap_id = attr->encap_id;
133 rule = mlx5_add_flow_rules(ft, spec, &flow_act, dest, i);
137 esw->offloads.num_flows++;
142 mlx5_fc_destroy(esw->dev, counter);
147 struct mlx5_flow_handle *
148 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
149 struct mlx5_flow_spec *spec,
150 struct mlx5_esw_flow_attr *attr)
152 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
153 struct mlx5_flow_act flow_act = {0};
154 struct mlx5_flow_handle *rule;
158 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
159 for (i = 0; i < attr->mirror_count; i++) {
160 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
161 dest[i].vport.num = attr->out_rep[i]->vport;
162 dest[i].vport.vhca_id =
163 MLX5_CAP_GEN(attr->out_mdev[i], vhca_id);
164 dest[i].vport.vhca_id_valid = !!MLX5_CAP_ESW(esw->dev, merged_eswitch);
166 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
167 dest[i].ft = esw->fdb_table.offloads.fwd_fdb,
170 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
171 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
173 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
174 MLX5_SET(fte_match_set_misc, misc,
175 source_eswitch_owner_vhca_id,
176 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
178 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
179 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
180 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
181 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
182 source_eswitch_owner_vhca_id);
184 if (attr->match_level == MLX5_MATCH_NONE)
185 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
187 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS |
188 MLX5_MATCH_MISC_PARAMETERS;
190 rule = mlx5_add_flow_rules(esw->fdb_table.offloads.fast_fdb, spec, &flow_act, dest, i);
193 esw->offloads.num_flows++;
199 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
200 struct mlx5_flow_handle *rule,
201 struct mlx5_esw_flow_attr *attr)
203 struct mlx5_fc *counter = NULL;
205 counter = mlx5_flow_rule_counter(rule);
206 mlx5_del_flow_rules(rule);
207 mlx5_fc_destroy(esw->dev, counter);
208 esw->offloads.num_flows--;
211 static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
213 struct mlx5_eswitch_rep *rep;
214 int vf_vport, err = 0;
216 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
217 for (vf_vport = 1; vf_vport < esw->enabled_vports; vf_vport++) {
218 rep = &esw->offloads.vport_reps[vf_vport];
219 if (!rep->rep_if[REP_ETH].valid)
222 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
231 static struct mlx5_eswitch_rep *
232 esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
234 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
236 in_rep = attr->in_rep;
237 out_rep = attr->out_rep[0];
249 static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
250 bool push, bool pop, bool fwd)
252 struct mlx5_eswitch_rep *in_rep, *out_rep;
254 if ((push || pop) && !fwd)
257 in_rep = attr->in_rep;
258 out_rep = attr->out_rep[0];
260 if (push && in_rep->vport == FDB_UPLINK_VPORT)
263 if (pop && out_rep->vport == FDB_UPLINK_VPORT)
266 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
267 if (!push && !pop && fwd)
268 if (in_rep->vlan && out_rep->vport == FDB_UPLINK_VPORT)
271 /* protects against (1) setting rules with different vlans to push and
272 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
274 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
283 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
284 struct mlx5_esw_flow_attr *attr)
286 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
287 struct mlx5_eswitch_rep *vport = NULL;
291 /* nop if we're on the vlan push/pop non emulation mode */
292 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
295 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
296 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
297 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
299 err = esw_add_vlan_action_check(attr, push, pop, fwd);
303 attr->vlan_handled = false;
305 vport = esw_vlan_action_get_vport(attr, push, pop);
307 if (!push && !pop && fwd) {
308 /* tracks VF --> wire rules without vlan push action */
309 if (attr->out_rep[0]->vport == FDB_UPLINK_VPORT) {
310 vport->vlan_refcount++;
311 attr->vlan_handled = true;
320 if (!(offloads->vlan_push_pop_refcount)) {
321 /* it's the 1st vlan rule, apply global vlan pop policy */
322 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
326 offloads->vlan_push_pop_refcount++;
329 if (vport->vlan_refcount)
332 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
333 SET_VLAN_INSERT | SET_VLAN_STRIP);
336 vport->vlan = attr->vlan_vid[0];
338 vport->vlan_refcount++;
342 attr->vlan_handled = true;
346 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
347 struct mlx5_esw_flow_attr *attr)
349 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
350 struct mlx5_eswitch_rep *vport = NULL;
354 /* nop if we're on the vlan push/pop non emulation mode */
355 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
358 if (!attr->vlan_handled)
361 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
362 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
363 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
365 vport = esw_vlan_action_get_vport(attr, push, pop);
367 if (!push && !pop && fwd) {
368 /* tracks VF --> wire rules without vlan push action */
369 if (attr->out_rep[0]->vport == FDB_UPLINK_VPORT)
370 vport->vlan_refcount--;
376 vport->vlan_refcount--;
377 if (vport->vlan_refcount)
378 goto skip_unset_push;
381 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
382 0, 0, SET_VLAN_STRIP);
388 offloads->vlan_push_pop_refcount--;
389 if (offloads->vlan_push_pop_refcount)
392 /* no more vlan rules, stop global vlan pop policy */
393 err = esw_set_global_vlan_pop(esw, 0);
399 struct mlx5_flow_handle *
400 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport, u32 sqn)
402 struct mlx5_flow_act flow_act = {0};
403 struct mlx5_flow_destination dest = {};
404 struct mlx5_flow_handle *flow_rule;
405 struct mlx5_flow_spec *spec;
408 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
410 flow_rule = ERR_PTR(-ENOMEM);
414 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
415 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
416 MLX5_SET(fte_match_set_misc, misc, source_port, 0x0); /* source vport is 0 */
418 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
419 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
420 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
422 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
423 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
424 dest.vport.num = vport;
425 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
427 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
428 &flow_act, &dest, 1);
429 if (IS_ERR(flow_rule))
430 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
435 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
437 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
439 mlx5_del_flow_rules(rule);
442 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
444 struct mlx5_flow_act flow_act = {0};
445 struct mlx5_flow_destination dest = {};
446 struct mlx5_flow_handle *flow_rule = NULL;
447 struct mlx5_flow_spec *spec;
454 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
460 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
461 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
463 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
464 outer_headers.dmac_47_16);
467 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
469 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
471 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
472 &flow_act, &dest, 1);
473 if (IS_ERR(flow_rule)) {
474 err = PTR_ERR(flow_rule);
475 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
479 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
481 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
483 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
484 outer_headers.dmac_47_16);
486 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
487 &flow_act, &dest, 1);
488 if (IS_ERR(flow_rule)) {
489 err = PTR_ERR(flow_rule);
490 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
491 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
495 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
502 #define ESW_OFFLOADS_NUM_GROUPS 4
504 static int esw_create_offloads_fast_fdb_table(struct mlx5_eswitch *esw)
506 struct mlx5_core_dev *dev = esw->dev;
507 struct mlx5_flow_namespace *root_ns;
508 struct mlx5_flow_table *fdb = NULL;
509 int esw_size, err = 0;
511 u32 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
512 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
514 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
516 esw_warn(dev, "Failed to get FDB flow namespace\n");
521 esw_debug(dev, "Create offloads FDB table, min (max esw size(2^%d), max counters(%d)*groups(%d))\n",
522 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size),
523 max_flow_counter, ESW_OFFLOADS_NUM_GROUPS);
525 esw_size = min_t(int, max_flow_counter * ESW_OFFLOADS_NUM_GROUPS,
526 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
528 if (mlx5_esw_has_fwd_fdb(dev))
531 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
532 flags |= MLX5_FLOW_TABLE_TUNNEL_EN;
534 fdb = mlx5_create_auto_grouped_flow_table(root_ns, FDB_FAST_PATH,
536 ESW_OFFLOADS_NUM_GROUPS, 0,
540 esw_warn(dev, "Failed to create Fast path FDB Table err %d\n", err);
543 esw->fdb_table.offloads.fast_fdb = fdb;
545 if (!mlx5_esw_has_fwd_fdb(dev))
548 fdb = mlx5_create_auto_grouped_flow_table(root_ns, FDB_FAST_PATH,
550 ESW_OFFLOADS_NUM_GROUPS, 1,
554 esw_warn(dev, "Failed to create fwd table err %d\n", err);
557 esw->fdb_table.offloads.fwd_fdb = fdb;
562 mlx5_destroy_flow_table(esw->fdb_table.offloads.fast_fdb);
567 static void esw_destroy_offloads_fast_fdb_table(struct mlx5_eswitch *esw)
569 if (mlx5_esw_has_fwd_fdb(esw->dev))
570 mlx5_destroy_flow_table(esw->fdb_table.offloads.fwd_fdb);
571 mlx5_destroy_flow_table(esw->fdb_table.offloads.fast_fdb);
574 #define MAX_PF_SQ 256
575 #define MAX_SQ_NVPORTS 32
577 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
579 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
580 struct mlx5_flow_table_attr ft_attr = {};
581 struct mlx5_core_dev *dev = esw->dev;
582 struct mlx5_flow_namespace *root_ns;
583 struct mlx5_flow_table *fdb = NULL;
584 int table_size, ix, err = 0;
585 struct mlx5_flow_group *g;
586 void *match_criteria;
590 esw_debug(esw->dev, "Create offloads FDB Tables\n");
591 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
595 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
597 esw_warn(dev, "Failed to get FDB flow namespace\n");
602 err = esw_create_offloads_fast_fdb_table(esw);
606 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ + 2;
608 ft_attr.max_fte = table_size;
609 ft_attr.prio = FDB_SLOW_PATH;
611 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
614 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
617 esw->fdb_table.offloads.slow_fdb = fdb;
619 /* create send-to-vport group */
620 memset(flow_group_in, 0, inlen);
621 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
622 MLX5_MATCH_MISC_PARAMETERS);
624 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
626 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
627 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
629 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
630 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
631 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
633 g = mlx5_create_flow_group(fdb, flow_group_in);
636 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
639 esw->fdb_table.offloads.send_to_vport_grp = g;
641 /* create miss group */
642 memset(flow_group_in, 0, inlen);
643 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
644 MLX5_MATCH_OUTER_HEADERS);
645 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
647 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
648 outer_headers.dmac_47_16);
651 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
652 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix + 2);
654 g = mlx5_create_flow_group(fdb, flow_group_in);
657 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
660 esw->fdb_table.offloads.miss_grp = g;
662 err = esw_add_fdb_miss_rule(esw);
666 kvfree(flow_group_in);
670 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
672 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
674 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
676 esw_destroy_offloads_fast_fdb_table(esw);
679 kvfree(flow_group_in);
683 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
685 if (!esw->fdb_table.offloads.fast_fdb)
688 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
689 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
690 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
691 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
692 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
694 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
695 esw_destroy_offloads_fast_fdb_table(esw);
698 static int esw_create_offloads_table(struct mlx5_eswitch *esw)
700 struct mlx5_flow_table_attr ft_attr = {};
701 struct mlx5_core_dev *dev = esw->dev;
702 struct mlx5_flow_table *ft_offloads;
703 struct mlx5_flow_namespace *ns;
706 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
708 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
712 ft_attr.max_fte = dev->priv.sriov.num_vfs + 2;
714 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
715 if (IS_ERR(ft_offloads)) {
716 err = PTR_ERR(ft_offloads);
717 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
721 esw->offloads.ft_offloads = ft_offloads;
725 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
727 struct mlx5_esw_offload *offloads = &esw->offloads;
729 mlx5_destroy_flow_table(offloads->ft_offloads);
732 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
734 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
735 struct mlx5_flow_group *g;
736 struct mlx5_priv *priv = &esw->dev->priv;
738 void *match_criteria, *misc;
740 int nvports = priv->sriov.num_vfs + 2;
742 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
746 /* create vport rx group */
747 memset(flow_group_in, 0, inlen);
748 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
749 MLX5_MATCH_MISC_PARAMETERS);
751 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
752 misc = MLX5_ADDR_OF(fte_match_param, match_criteria, misc_parameters);
753 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
755 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
756 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
758 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
762 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
766 esw->offloads.vport_rx_group = g;
768 kvfree(flow_group_in);
772 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
774 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
777 struct mlx5_flow_handle *
778 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
779 struct mlx5_flow_destination *dest)
781 struct mlx5_flow_act flow_act = {0};
782 struct mlx5_flow_handle *flow_rule;
783 struct mlx5_flow_spec *spec;
786 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
788 flow_rule = ERR_PTR(-ENOMEM);
792 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
793 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
795 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
796 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
798 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
800 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
801 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
803 if (IS_ERR(flow_rule)) {
804 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
813 static int esw_offloads_start(struct mlx5_eswitch *esw)
815 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
817 if (esw->mode != SRIOV_LEGACY) {
818 esw_warn(esw->dev, "Can't set offloads mode, SRIOV legacy not enabled\n");
822 mlx5_eswitch_disable_sriov(esw);
823 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
825 esw_warn(esw->dev, "Failed setting eswitch to offloads, err %d\n", err);
826 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
828 esw_warn(esw->dev, "Failed setting eswitch back to legacy, err %d\n", err1);
830 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
831 if (mlx5_eswitch_inline_mode_get(esw,
833 &esw->offloads.inline_mode)) {
834 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
835 esw_warn(esw->dev, "Inline mode is different between vports\n");
841 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
843 kfree(esw->offloads.vport_reps);
846 int esw_offloads_init_reps(struct mlx5_eswitch *esw)
848 int total_vfs = MLX5_TOTAL_VPORTS(esw->dev);
849 struct mlx5_core_dev *dev = esw->dev;
850 struct mlx5_esw_offload *offloads;
851 struct mlx5_eswitch_rep *rep;
855 esw->offloads.vport_reps = kcalloc(total_vfs,
856 sizeof(struct mlx5_eswitch_rep),
858 if (!esw->offloads.vport_reps)
861 offloads = &esw->offloads;
862 mlx5_query_nic_vport_mac_address(dev, 0, hw_id);
864 for (vport = 0; vport < total_vfs; vport++) {
865 rep = &offloads->vport_reps[vport];
868 ether_addr_copy(rep->hw_id, hw_id);
871 offloads->vport_reps[0].vport = FDB_UPLINK_VPORT;
876 static void esw_offloads_unload_reps_type(struct mlx5_eswitch *esw, int nvports,
879 struct mlx5_eswitch_rep *rep;
882 for (vport = nvports - 1; vport >= 0; vport--) {
883 rep = &esw->offloads.vport_reps[vport];
884 if (!rep->rep_if[rep_type].valid)
887 rep->rep_if[rep_type].unload(rep);
891 static void esw_offloads_unload_reps(struct mlx5_eswitch *esw, int nvports)
893 u8 rep_type = NUM_REP_TYPES;
895 while (rep_type-- > 0)
896 esw_offloads_unload_reps_type(esw, nvports, rep_type);
899 static int esw_offloads_load_reps_type(struct mlx5_eswitch *esw, int nvports,
902 struct mlx5_eswitch_rep *rep;
906 for (vport = 0; vport < nvports; vport++) {
907 rep = &esw->offloads.vport_reps[vport];
908 if (!rep->rep_if[rep_type].valid)
911 err = rep->rep_if[rep_type].load(esw->dev, rep);
919 esw_offloads_unload_reps_type(esw, vport, rep_type);
923 static int esw_offloads_load_reps(struct mlx5_eswitch *esw, int nvports)
928 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
929 err = esw_offloads_load_reps_type(esw, nvports, rep_type);
937 while (rep_type-- > 0)
938 esw_offloads_unload_reps_type(esw, nvports, rep_type);
942 int esw_offloads_init(struct mlx5_eswitch *esw, int nvports)
946 err = esw_create_offloads_fdb_tables(esw, nvports);
950 err = esw_create_offloads_table(esw);
954 err = esw_create_vport_rx_group(esw);
958 err = esw_offloads_load_reps(esw, nvports);
965 esw_destroy_vport_rx_group(esw);
968 esw_destroy_offloads_table(esw);
971 esw_destroy_offloads_fdb_tables(esw);
976 static int esw_offloads_stop(struct mlx5_eswitch *esw)
978 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
980 mlx5_eswitch_disable_sriov(esw);
981 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
983 esw_warn(esw->dev, "Failed setting eswitch to legacy, err %d\n", err);
984 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
986 esw_warn(esw->dev, "Failed setting eswitch back to offloads, err %d\n", err);
989 /* enable back PF RoCE */
990 mlx5_reload_interface(esw->dev, MLX5_INTERFACE_PROTOCOL_IB);
995 void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports)
997 esw_offloads_unload_reps(esw, nvports);
998 esw_destroy_vport_rx_group(esw);
999 esw_destroy_offloads_table(esw);
1000 esw_destroy_offloads_fdb_tables(esw);
1003 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
1006 case DEVLINK_ESWITCH_MODE_LEGACY:
1007 *mlx5_mode = SRIOV_LEGACY;
1009 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
1010 *mlx5_mode = SRIOV_OFFLOADS;
1019 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
1021 switch (mlx5_mode) {
1023 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
1025 case SRIOV_OFFLOADS:
1026 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
1035 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
1038 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
1039 *mlx5_mode = MLX5_INLINE_MODE_NONE;
1041 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
1042 *mlx5_mode = MLX5_INLINE_MODE_L2;
1044 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
1045 *mlx5_mode = MLX5_INLINE_MODE_IP;
1047 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
1048 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
1057 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
1059 switch (mlx5_mode) {
1060 case MLX5_INLINE_MODE_NONE:
1061 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
1063 case MLX5_INLINE_MODE_L2:
1064 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
1066 case MLX5_INLINE_MODE_IP:
1067 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
1069 case MLX5_INLINE_MODE_TCP_UDP:
1070 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
1079 static int mlx5_devlink_eswitch_check(struct devlink *devlink)
1081 struct mlx5_core_dev *dev = devlink_priv(devlink);
1083 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1086 if(!MLX5_ESWITCH_MANAGER(dev))
1089 if (dev->priv.eswitch->mode == SRIOV_NONE)
1095 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode)
1097 struct mlx5_core_dev *dev = devlink_priv(devlink);
1098 u16 cur_mlx5_mode, mlx5_mode = 0;
1101 err = mlx5_devlink_eswitch_check(devlink);
1105 cur_mlx5_mode = dev->priv.eswitch->mode;
1107 if (esw_mode_from_devlink(mode, &mlx5_mode))
1110 if (cur_mlx5_mode == mlx5_mode)
1113 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
1114 return esw_offloads_start(dev->priv.eswitch);
1115 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
1116 return esw_offloads_stop(dev->priv.eswitch);
1121 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
1123 struct mlx5_core_dev *dev = devlink_priv(devlink);
1126 err = mlx5_devlink_eswitch_check(devlink);
1130 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
1133 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode)
1135 struct mlx5_core_dev *dev = devlink_priv(devlink);
1136 struct mlx5_eswitch *esw = dev->priv.eswitch;
1140 err = mlx5_devlink_eswitch_check(devlink);
1144 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1145 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1146 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
1149 case MLX5_CAP_INLINE_MODE_L2:
1150 esw_warn(dev, "Inline mode can't be set\n");
1152 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1156 if (esw->offloads.num_flows > 0) {
1157 esw_warn(dev, "Can't set inline mode when flows are configured\n");
1161 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
1165 for (vport = 1; vport < esw->enabled_vports; vport++) {
1166 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
1168 esw_warn(dev, "Failed to set min inline on vport %d\n",
1170 goto revert_inline_mode;
1174 esw->offloads.inline_mode = mlx5_mode;
1179 mlx5_modify_nic_vport_min_inline(dev,
1181 esw->offloads.inline_mode);
1186 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
1188 struct mlx5_core_dev *dev = devlink_priv(devlink);
1189 struct mlx5_eswitch *esw = dev->priv.eswitch;
1192 err = mlx5_devlink_eswitch_check(devlink);
1196 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
1199 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode)
1201 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1202 struct mlx5_core_dev *dev = esw->dev;
1205 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1208 if (esw->mode == SRIOV_NONE)
1211 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1212 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1213 mlx5_mode = MLX5_INLINE_MODE_NONE;
1215 case MLX5_CAP_INLINE_MODE_L2:
1216 mlx5_mode = MLX5_INLINE_MODE_L2;
1218 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1223 for (vport = 1; vport <= nvfs; vport++) {
1224 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
1225 if (vport > 1 && prev_mlx5_mode != mlx5_mode)
1227 prev_mlx5_mode = mlx5_mode;
1235 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap)
1237 struct mlx5_core_dev *dev = devlink_priv(devlink);
1238 struct mlx5_eswitch *esw = dev->priv.eswitch;
1241 err = mlx5_devlink_eswitch_check(devlink);
1245 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
1246 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, encap) ||
1247 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)))
1250 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC)
1253 if (esw->mode == SRIOV_LEGACY) {
1254 esw->offloads.encap = encap;
1258 if (esw->offloads.encap == encap)
1261 if (esw->offloads.num_flows > 0) {
1262 esw_warn(dev, "Can't set encapsulation when flows are configured\n");
1266 esw_destroy_offloads_fast_fdb_table(esw);
1268 esw->offloads.encap = encap;
1269 err = esw_create_offloads_fast_fdb_table(esw);
1271 esw_warn(esw->dev, "Failed re-creating fast FDB table, err %d\n", err);
1272 esw->offloads.encap = !encap;
1273 (void)esw_create_offloads_fast_fdb_table(esw);
1278 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap)
1280 struct mlx5_core_dev *dev = devlink_priv(devlink);
1281 struct mlx5_eswitch *esw = dev->priv.eswitch;
1284 err = mlx5_devlink_eswitch_check(devlink);
1288 *encap = esw->offloads.encap;
1292 void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
1294 struct mlx5_eswitch_rep_if *__rep_if,
1297 struct mlx5_esw_offload *offloads = &esw->offloads;
1298 struct mlx5_eswitch_rep_if *rep_if;
1300 rep_if = &offloads->vport_reps[vport_index].rep_if[rep_type];
1302 rep_if->load = __rep_if->load;
1303 rep_if->unload = __rep_if->unload;
1304 rep_if->get_proto_dev = __rep_if->get_proto_dev;
1305 rep_if->priv = __rep_if->priv;
1307 rep_if->valid = true;
1309 EXPORT_SYMBOL(mlx5_eswitch_register_vport_rep);
1311 void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
1312 int vport_index, u8 rep_type)
1314 struct mlx5_esw_offload *offloads = &esw->offloads;
1315 struct mlx5_eswitch_rep *rep;
1317 rep = &offloads->vport_reps[vport_index];
1319 if (esw->mode == SRIOV_OFFLOADS && esw->vports[vport_index].enabled)
1320 rep->rep_if[rep_type].unload(rep);
1322 rep->rep_if[rep_type].valid = false;
1324 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_rep);
1326 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
1328 #define UPLINK_REP_INDEX 0
1329 struct mlx5_esw_offload *offloads = &esw->offloads;
1330 struct mlx5_eswitch_rep *rep;
1332 rep = &offloads->vport_reps[UPLINK_REP_INDEX];
1333 return rep->rep_if[rep_type].priv;
1336 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
1340 struct mlx5_esw_offload *offloads = &esw->offloads;
1341 struct mlx5_eswitch_rep *rep;
1343 if (vport == FDB_UPLINK_VPORT)
1344 vport = UPLINK_REP_INDEX;
1346 rep = &offloads->vport_reps[vport];
1348 if (rep->rep_if[rep_type].valid &&
1349 rep->rep_if[rep_type].get_proto_dev)
1350 return rep->rep_if[rep_type].get_proto_dev(rep);
1353 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
1355 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
1357 return mlx5_eswitch_get_proto_dev(esw, UPLINK_REP_INDEX, rep_type);
1359 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
1361 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
1364 return &esw->offloads.vport_reps[vport];
1366 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);