2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/flow_dissector.h>
34 #include <net/sch_generic.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_skbedit.h>
38 #include <linux/mlx5/fs.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/rhashtable.h>
41 #include <net/switchdev.h>
42 #include <net/tc_act/tc_mirred.h>
43 #include <net/tc_act/tc_vlan.h>
44 #include <net/tc_act/tc_tunnel_key.h>
45 #include <net/tc_act/tc_pedit.h>
46 #include <net/tc_act/tc_csum.h>
47 #include <net/vxlan.h>
53 #include "lib/vxlan.h"
57 struct mlx5_nic_flow_attr {
63 struct mlx5_flow_table *hairpin_ft;
66 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
69 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
70 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
71 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
72 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
73 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
74 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
75 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
78 #define MLX5E_TC_MAX_SPLITS 1
80 struct mlx5e_tc_flow {
81 struct rhash_head node;
82 struct mlx5e_priv *priv;
85 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
86 struct list_head encap; /* flows sharing the same encap ID */
87 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
88 struct list_head hairpin; /* flows sharing the same hairpin */
90 struct mlx5_esw_flow_attr esw_attr[0];
91 struct mlx5_nic_flow_attr nic_attr[0];
95 struct mlx5e_tc_flow_parse_attr {
96 struct ip_tunnel_info tun_info;
97 struct mlx5_flow_spec spec;
98 int num_mod_hdr_actions;
99 void *mod_hdr_actions;
104 MLX5_HEADER_TYPE_VXLAN = 0x0,
105 MLX5_HEADER_TYPE_NVGRE = 0x1,
108 #define MLX5E_TC_TABLE_NUM_GROUPS 4
109 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
111 struct mlx5e_hairpin {
112 struct mlx5_hairpin *pair;
114 struct mlx5_core_dev *func_mdev;
115 struct mlx5e_priv *func_priv;
120 struct mlx5e_rqt indir_rqt;
121 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
122 struct mlx5e_ttc_table ttc;
125 struct mlx5e_hairpin_entry {
126 /* a node of a hash table which keeps all the hairpin entries */
127 struct hlist_node hairpin_hlist;
129 /* flows sharing the same hairpin */
130 struct list_head flows;
134 struct mlx5e_hairpin *hp;
142 struct mlx5e_mod_hdr_entry {
143 /* a node of a hash table which keeps all the mod_hdr entries */
144 struct hlist_node mod_hdr_hlist;
146 /* flows sharing the same mod_hdr entry */
147 struct list_head flows;
149 struct mod_hdr_key key;
154 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
156 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
158 return jhash(key->actions,
159 key->num_actions * MLX5_MH_ACT_SZ, 0);
162 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
163 struct mod_hdr_key *b)
165 if (a->num_actions != b->num_actions)
168 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
171 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
172 struct mlx5e_tc_flow *flow,
173 struct mlx5e_tc_flow_parse_attr *parse_attr)
175 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
176 int num_actions, actions_size, namespace, err;
177 struct mlx5e_mod_hdr_entry *mh;
178 struct mod_hdr_key key;
182 num_actions = parse_attr->num_mod_hdr_actions;
183 actions_size = MLX5_MH_ACT_SZ * num_actions;
185 key.actions = parse_attr->mod_hdr_actions;
186 key.num_actions = num_actions;
188 hash_key = hash_mod_hdr_info(&key);
190 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
191 namespace = MLX5_FLOW_NAMESPACE_FDB;
192 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
193 mod_hdr_hlist, hash_key) {
194 if (!cmp_mod_hdr_info(&mh->key, &key)) {
200 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
201 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
202 mod_hdr_hlist, hash_key) {
203 if (!cmp_mod_hdr_info(&mh->key, &key)) {
213 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
217 mh->key.actions = (void *)mh + sizeof(*mh);
218 memcpy(mh->key.actions, key.actions, actions_size);
219 mh->key.num_actions = num_actions;
220 INIT_LIST_HEAD(&mh->flows);
222 err = mlx5_modify_header_alloc(priv->mdev, namespace,
229 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
230 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
232 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
235 list_add(&flow->mod_hdr, &mh->flows);
236 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
237 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
239 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
248 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
249 struct mlx5e_tc_flow *flow)
251 struct list_head *next = flow->mod_hdr.next;
253 list_del(&flow->mod_hdr);
255 if (list_empty(next)) {
256 struct mlx5e_mod_hdr_entry *mh;
258 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
260 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
261 hash_del(&mh->mod_hdr_hlist);
267 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
269 struct net_device *netdev;
270 struct mlx5e_priv *priv;
272 netdev = __dev_get_by_index(net, ifindex);
273 priv = netdev_priv(netdev);
277 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
279 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
283 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
287 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
289 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
290 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
291 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
293 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
300 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
305 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
307 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
308 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
311 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
313 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
314 struct mlx5e_priv *priv = hp->func_priv;
315 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
317 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
320 for (i = 0; i < sz; i++) {
322 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
323 ix = mlx5e_bits_invert(i, ilog2(sz));
324 ix = indirection_rqt[ix];
325 rqn = hp->pair->rqn[ix];
326 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
330 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
332 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
333 struct mlx5e_priv *priv = hp->func_priv;
334 struct mlx5_core_dev *mdev = priv->mdev;
338 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
339 in = kvzalloc(inlen, GFP_KERNEL);
343 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
345 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
346 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
348 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
350 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
352 hp->indir_rqt.enabled = true;
358 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
360 struct mlx5e_priv *priv = hp->func_priv;
361 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
365 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
366 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
367 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
369 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
370 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
371 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
372 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
374 err = mlx5_core_create_tir(hp->func_mdev, in,
375 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
377 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
378 goto err_destroy_tirs;
384 for (i = 0; i < tt; i++)
385 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
389 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
393 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
394 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
397 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
398 struct ttc_params *ttc_params)
400 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
403 memset(ttc_params, 0, sizeof(*ttc_params));
405 ttc_params->any_tt_tirn = hp->tirn;
407 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
408 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
410 ft_attr->max_fte = MLX5E_NUM_TT;
411 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
412 ft_attr->prio = MLX5E_TC_PRIO;
415 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
417 struct mlx5e_priv *priv = hp->func_priv;
418 struct ttc_params ttc_params;
421 err = mlx5e_hairpin_create_indirect_rqt(hp);
425 err = mlx5e_hairpin_create_indirect_tirs(hp);
427 goto err_create_indirect_tirs;
429 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
430 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
432 goto err_create_ttc_table;
434 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
435 hp->num_channels, hp->ttc.ft.t->id);
439 err_create_ttc_table:
440 mlx5e_hairpin_destroy_indirect_tirs(hp);
441 err_create_indirect_tirs:
442 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
447 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
449 struct mlx5e_priv *priv = hp->func_priv;
451 mlx5e_destroy_ttc_table(priv, &hp->ttc);
452 mlx5e_hairpin_destroy_indirect_tirs(hp);
453 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
456 static struct mlx5e_hairpin *
457 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
460 struct mlx5_core_dev *func_mdev, *peer_mdev;
461 struct mlx5e_hairpin *hp;
462 struct mlx5_hairpin *pair;
465 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
467 return ERR_PTR(-ENOMEM);
469 func_mdev = priv->mdev;
470 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
472 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
475 goto create_pair_err;
478 hp->func_mdev = func_mdev;
479 hp->func_priv = priv;
480 hp->num_channels = params->num_channels;
482 err = mlx5e_hairpin_create_transport(hp);
484 goto create_transport_err;
486 if (hp->num_channels > 1) {
487 err = mlx5e_hairpin_rss_init(hp);
495 mlx5e_hairpin_destroy_transport(hp);
496 create_transport_err:
497 mlx5_core_hairpin_destroy(hp->pair);
503 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
505 if (hp->num_channels > 1)
506 mlx5e_hairpin_rss_cleanup(hp);
507 mlx5e_hairpin_destroy_transport(hp);
508 mlx5_core_hairpin_destroy(hp->pair);
512 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
514 return (peer_vhca_id << 16 | prio);
517 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
518 u16 peer_vhca_id, u8 prio)
520 struct mlx5e_hairpin_entry *hpe;
521 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
523 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
524 hairpin_hlist, hash_key) {
525 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
532 #define UNKNOWN_MATCH_PRIO 8
534 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
535 struct mlx5_flow_spec *spec, u8 *match_prio)
537 void *headers_c, *headers_v;
538 u8 prio_val, prio_mask = 0;
541 #ifdef CONFIG_MLX5_CORE_EN_DCB
542 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
543 netdev_warn(priv->netdev,
544 "only PCP trust state supported for hairpin\n");
548 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
549 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
551 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
553 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
554 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
557 if (!vlan_present || !prio_mask) {
558 prio_val = UNKNOWN_MATCH_PRIO;
559 } else if (prio_mask != 0x7) {
560 netdev_warn(priv->netdev,
561 "masked priority match not supported for hairpin\n");
565 *match_prio = prio_val;
569 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
570 struct mlx5e_tc_flow *flow,
571 struct mlx5e_tc_flow_parse_attr *parse_attr)
573 int peer_ifindex = parse_attr->mirred_ifindex;
574 struct mlx5_hairpin_params params;
575 struct mlx5_core_dev *peer_mdev;
576 struct mlx5e_hairpin_entry *hpe;
577 struct mlx5e_hairpin *hp;
584 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
585 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
586 netdev_warn(priv->netdev, "hairpin is not supported\n");
590 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
591 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
594 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
598 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
602 INIT_LIST_HEAD(&hpe->flows);
603 hpe->peer_vhca_id = peer_id;
604 hpe->prio = match_prio;
606 params.log_data_size = 15;
607 params.log_data_size = min_t(u8, params.log_data_size,
608 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
609 params.log_data_size = max_t(u8, params.log_data_size,
610 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
612 params.log_num_packets = params.log_data_size -
613 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
614 params.log_num_packets = min_t(u8, params.log_num_packets,
615 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
617 params.q_counter = priv->q_counter;
618 /* set hairpin pair per each 50Gbs share of the link */
619 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
620 link_speed = max_t(u32, link_speed, 50000);
621 link_speed64 = link_speed;
622 do_div(link_speed64, 50000);
623 params.num_channels = link_speed64;
625 hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex);
628 goto create_hairpin_err;
631 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
632 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
633 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
636 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
637 hash_hairpin_info(peer_id, match_prio));
640 if (hpe->hp->num_channels > 1) {
641 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
642 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
644 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
646 list_add(&flow->hairpin, &hpe->flows);
655 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
656 struct mlx5e_tc_flow *flow)
658 struct list_head *next = flow->hairpin.next;
660 list_del(&flow->hairpin);
662 /* no more hairpin flows for us, release the hairpin pair */
663 if (list_empty(next)) {
664 struct mlx5e_hairpin_entry *hpe;
666 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
668 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
669 hpe->hp->pair->peer_mdev->priv.name);
671 mlx5e_hairpin_destroy(hpe->hp);
672 hash_del(&hpe->hairpin_hlist);
677 static struct mlx5_flow_handle *
678 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
679 struct mlx5e_tc_flow_parse_attr *parse_attr,
680 struct mlx5e_tc_flow *flow)
682 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
683 struct mlx5_core_dev *dev = priv->mdev;
684 struct mlx5_flow_destination dest[2] = {};
685 struct mlx5_flow_act flow_act = {
686 .action = attr->action,
687 .has_flow_tag = true,
688 .flow_tag = attr->flow_tag,
691 struct mlx5_fc *counter = NULL;
692 struct mlx5_flow_handle *rule;
693 bool table_created = false;
694 int err, dest_ix = 0;
696 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
697 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
700 goto err_add_hairpin_flow;
702 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
703 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
704 dest[dest_ix].ft = attr->hairpin_ft;
706 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
707 dest[dest_ix].tir_num = attr->hairpin_tirn;
710 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
711 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
712 dest[dest_ix].ft = priv->fs.vlan.ft.t;
716 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
717 counter = mlx5_fc_create(dev, true);
718 if (IS_ERR(counter)) {
719 rule = ERR_CAST(counter);
722 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
723 dest[dest_ix].counter = counter;
727 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
728 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
729 flow_act.modify_id = attr->mod_hdr_id;
730 kfree(parse_attr->mod_hdr_actions);
733 goto err_create_mod_hdr_id;
737 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
738 int tc_grp_size, tc_tbl_size;
739 u32 max_flow_counter;
741 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
742 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
744 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
746 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
747 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
750 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
753 MLX5E_TC_TABLE_NUM_GROUPS,
754 MLX5E_TC_FT_LEVEL, 0);
755 if (IS_ERR(priv->fs.tc.t)) {
756 netdev_err(priv->netdev,
757 "Failed to create tc offload table\n");
758 rule = ERR_CAST(priv->fs.tc.t);
762 table_created = true;
765 if (attr->match_level != MLX5_MATCH_NONE)
766 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
768 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
769 &flow_act, dest, dest_ix);
778 mlx5_destroy_flow_table(priv->fs.tc.t);
779 priv->fs.tc.t = NULL;
782 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
783 mlx5e_detach_mod_hdr(priv, flow);
784 err_create_mod_hdr_id:
785 mlx5_fc_destroy(dev, counter);
787 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
788 mlx5e_hairpin_flow_del(priv, flow);
789 err_add_hairpin_flow:
793 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
794 struct mlx5e_tc_flow *flow)
796 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
797 struct mlx5_fc *counter = NULL;
799 counter = mlx5_flow_rule_counter(flow->rule[0]);
800 mlx5_del_flow_rules(flow->rule[0]);
801 mlx5_fc_destroy(priv->mdev, counter);
803 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
804 mlx5_destroy_flow_table(priv->fs.tc.t);
805 priv->fs.tc.t = NULL;
808 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
809 mlx5e_detach_mod_hdr(priv, flow);
811 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
812 mlx5e_hairpin_flow_del(priv, flow);
815 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
816 struct mlx5e_tc_flow *flow);
818 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
819 struct ip_tunnel_info *tun_info,
820 struct net_device *mirred_dev,
821 struct net_device **encap_dev,
822 struct mlx5e_tc_flow *flow);
824 static struct mlx5_flow_handle *
825 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
826 struct mlx5e_tc_flow_parse_attr *parse_attr,
827 struct mlx5e_tc_flow *flow)
829 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
830 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
831 struct net_device *out_dev, *encap_dev = NULL;
832 struct mlx5_flow_handle *rule = NULL;
833 struct mlx5e_rep_priv *rpriv;
834 struct mlx5e_priv *out_priv;
837 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
838 out_dev = __dev_get_by_index(dev_net(priv->netdev),
839 attr->parse_attr->mirred_ifindex);
840 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
841 out_dev, &encap_dev, flow);
845 goto err_attach_encap;
847 out_priv = netdev_priv(encap_dev);
848 rpriv = out_priv->ppriv;
849 attr->out_rep[attr->out_count] = rpriv->rep;
850 attr->out_mdev[attr->out_count++] = out_priv->mdev;
853 err = mlx5_eswitch_add_vlan_action(esw, attr);
859 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
860 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
861 kfree(parse_attr->mod_hdr_actions);
868 /* we get here if (1) there's no error (rule being null) or when
869 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
871 if (rule != ERR_PTR(-EAGAIN)) {
872 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
876 if (attr->mirror_count) {
877 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &parse_attr->spec, attr);
878 if (IS_ERR(flow->rule[1]))
885 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
886 rule = flow->rule[1];
888 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
889 mlx5e_detach_mod_hdr(priv, flow);
891 mlx5_eswitch_del_vlan_action(esw, attr);
893 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
894 mlx5e_detach_encap(priv, flow);
899 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
900 struct mlx5e_tc_flow *flow)
902 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
903 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
905 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
906 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
907 if (attr->mirror_count)
908 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
909 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
912 mlx5_eswitch_del_vlan_action(esw, attr);
914 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
915 mlx5e_detach_encap(priv, flow);
916 kvfree(attr->parse_attr);
919 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
920 mlx5e_detach_mod_hdr(priv, flow);
923 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
924 struct mlx5e_encap_entry *e)
926 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
927 struct mlx5_esw_flow_attr *esw_attr;
928 struct mlx5e_tc_flow *flow;
931 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
932 e->encap_size, e->encap_header,
935 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
939 e->flags |= MLX5_ENCAP_ENTRY_VALID;
940 mlx5e_rep_queue_neigh_stats_work(priv);
942 list_for_each_entry(flow, &e->flows, encap) {
943 esw_attr = flow->esw_attr;
944 esw_attr->encap_id = e->encap_id;
945 flow->rule[0] = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
946 if (IS_ERR(flow->rule[0])) {
947 err = PTR_ERR(flow->rule[0]);
948 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
953 if (esw_attr->mirror_count) {
954 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
955 if (IS_ERR(flow->rule[1])) {
956 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], esw_attr);
957 err = PTR_ERR(flow->rule[1]);
958 mlx5_core_warn(priv->mdev, "Failed to update cached mirror flow, %d\n",
964 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
968 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
969 struct mlx5e_encap_entry *e)
971 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
972 struct mlx5e_tc_flow *flow;
974 list_for_each_entry(flow, &e->flows, encap) {
975 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
976 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
978 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
979 if (attr->mirror_count)
980 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
981 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
985 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
986 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
987 mlx5_encap_dealloc(priv->mdev, e->encap_id);
991 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
993 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
994 u64 bytes, packets, lastuse = 0;
995 struct mlx5e_tc_flow *flow;
996 struct mlx5e_encap_entry *e;
997 struct mlx5_fc *counter;
998 struct neigh_table *tbl;
999 bool neigh_used = false;
1000 struct neighbour *n;
1002 if (m_neigh->family == AF_INET)
1004 #if IS_ENABLED(CONFIG_IPV6)
1005 else if (m_neigh->family == AF_INET6)
1011 list_for_each_entry(e, &nhe->encap_list, encap_list) {
1012 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1014 list_for_each_entry(flow, &e->flows, encap) {
1015 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1016 counter = mlx5_flow_rule_counter(flow->rule[0]);
1017 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1018 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1029 nhe->reported_lastuse = jiffies;
1031 /* find the relevant neigh according to the cached device and
1034 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1038 neigh_event_send(n, NULL);
1043 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1044 struct mlx5e_tc_flow *flow)
1046 struct list_head *next = flow->encap.next;
1048 list_del(&flow->encap);
1049 if (list_empty(next)) {
1050 struct mlx5e_encap_entry *e;
1052 e = list_entry(next, struct mlx5e_encap_entry, flows);
1053 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1055 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1056 mlx5_encap_dealloc(priv->mdev, e->encap_id);
1058 hash_del_rcu(&e->encap_hlist);
1059 kfree(e->encap_header);
1064 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1065 struct mlx5e_tc_flow *flow)
1067 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1068 mlx5e_tc_del_fdb_flow(priv, flow);
1070 mlx5e_tc_del_nic_flow(priv, flow);
1073 static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1074 struct tc_cls_flower_offload *f)
1076 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1078 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1080 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1082 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1085 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1086 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1088 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1089 struct flow_dissector_key_keyid *key =
1090 skb_flow_dissector_target(f->dissector,
1091 FLOW_DISSECTOR_KEY_ENC_KEYID,
1093 struct flow_dissector_key_keyid *mask =
1094 skb_flow_dissector_target(f->dissector,
1095 FLOW_DISSECTOR_KEY_ENC_KEYID,
1097 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1098 be32_to_cpu(mask->keyid));
1099 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1100 be32_to_cpu(key->keyid));
1104 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1105 struct mlx5_flow_spec *spec,
1106 struct tc_cls_flower_offload *f)
1108 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1110 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1113 struct flow_dissector_key_control *enc_control =
1114 skb_flow_dissector_target(f->dissector,
1115 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1118 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1119 struct flow_dissector_key_ports *key =
1120 skb_flow_dissector_target(f->dissector,
1121 FLOW_DISSECTOR_KEY_ENC_PORTS,
1123 struct flow_dissector_key_ports *mask =
1124 skb_flow_dissector_target(f->dissector,
1125 FLOW_DISSECTOR_KEY_ENC_PORTS,
1128 /* Full udp dst port must be given */
1129 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
1130 goto vxlan_match_offload_err;
1132 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->dst)) &&
1133 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1134 parse_vxlan_attr(spec, f);
1136 netdev_warn(priv->netdev,
1137 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
1141 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1142 udp_dport, ntohs(mask->dst));
1143 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1144 udp_dport, ntohs(key->dst));
1146 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1147 udp_sport, ntohs(mask->src));
1148 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1149 udp_sport, ntohs(key->src));
1150 } else { /* udp dst port must be given */
1151 vxlan_match_offload_err:
1152 netdev_warn(priv->netdev,
1153 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1157 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1158 struct flow_dissector_key_ipv4_addrs *key =
1159 skb_flow_dissector_target(f->dissector,
1160 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1162 struct flow_dissector_key_ipv4_addrs *mask =
1163 skb_flow_dissector_target(f->dissector,
1164 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1166 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1167 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1169 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1170 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1173 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1174 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1176 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1177 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1180 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
1182 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1183 struct flow_dissector_key_ipv6_addrs *key =
1184 skb_flow_dissector_target(f->dissector,
1185 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1187 struct flow_dissector_key_ipv6_addrs *mask =
1188 skb_flow_dissector_target(f->dissector,
1189 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1192 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1193 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1194 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1195 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1196 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1197 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1199 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1200 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1201 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1202 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1203 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1204 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1206 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1207 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
1210 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1211 struct flow_dissector_key_ip *key =
1212 skb_flow_dissector_target(f->dissector,
1213 FLOW_DISSECTOR_KEY_ENC_IP,
1215 struct flow_dissector_key_ip *mask =
1216 skb_flow_dissector_target(f->dissector,
1217 FLOW_DISSECTOR_KEY_ENC_IP,
1220 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1221 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1223 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1224 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1226 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1227 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1230 /* Enforce DMAC when offloading incoming tunneled flows.
1231 * Flow counters require a match on the DMAC.
1233 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1234 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1235 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1236 dmac_47_16), priv->netdev->dev_addr);
1238 /* let software handle IP fragments */
1239 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1240 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1245 static int __parse_cls_flower(struct mlx5e_priv *priv,
1246 struct mlx5_flow_spec *spec,
1247 struct tc_cls_flower_offload *f,
1250 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1252 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1254 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1256 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1261 *match_level = MLX5_MATCH_NONE;
1263 if (f->dissector->used_keys &
1264 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1265 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1266 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1267 BIT(FLOW_DISSECTOR_KEY_VLAN) |
1268 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1269 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1270 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1271 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1272 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1273 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1274 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1275 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1276 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1277 BIT(FLOW_DISSECTOR_KEY_TCP) |
1278 BIT(FLOW_DISSECTOR_KEY_IP) |
1279 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
1280 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1281 f->dissector->used_keys);
1285 if ((dissector_uses_key(f->dissector,
1286 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1287 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1288 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1289 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1290 struct flow_dissector_key_control *key =
1291 skb_flow_dissector_target(f->dissector,
1292 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1294 switch (key->addr_type) {
1295 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
1296 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
1297 if (parse_tunnel_attr(priv, spec, f))
1304 /* In decap flow, header pointers should point to the inner
1305 * headers, outer header were already set by parse_tunnel_attr
1307 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1309 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1313 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1314 struct flow_dissector_key_eth_addrs *key =
1315 skb_flow_dissector_target(f->dissector,
1316 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1318 struct flow_dissector_key_eth_addrs *mask =
1319 skb_flow_dissector_target(f->dissector,
1320 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1323 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1326 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1330 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1333 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1337 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
1338 *match_level = MLX5_MATCH_L2;
1341 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1342 struct flow_dissector_key_vlan *key =
1343 skb_flow_dissector_target(f->dissector,
1344 FLOW_DISSECTOR_KEY_VLAN,
1346 struct flow_dissector_key_vlan *mask =
1347 skb_flow_dissector_target(f->dissector,
1348 FLOW_DISSECTOR_KEY_VLAN,
1350 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1351 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1352 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1354 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1357 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1359 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1363 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1364 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
1366 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1367 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
1369 *match_level = MLX5_MATCH_L2;
1373 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1374 struct flow_dissector_key_vlan *key =
1375 skb_flow_dissector_target(f->dissector,
1376 FLOW_DISSECTOR_KEY_CVLAN,
1378 struct flow_dissector_key_vlan *mask =
1379 skb_flow_dissector_target(f->dissector,
1380 FLOW_DISSECTOR_KEY_CVLAN,
1382 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1383 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1384 MLX5_SET(fte_match_set_misc, misc_c,
1385 outer_second_svlan_tag, 1);
1386 MLX5_SET(fte_match_set_misc, misc_v,
1387 outer_second_svlan_tag, 1);
1389 MLX5_SET(fte_match_set_misc, misc_c,
1390 outer_second_cvlan_tag, 1);
1391 MLX5_SET(fte_match_set_misc, misc_v,
1392 outer_second_cvlan_tag, 1);
1395 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1397 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1399 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1400 mask->vlan_priority);
1401 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1402 key->vlan_priority);
1404 *match_level = MLX5_MATCH_L2;
1408 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1409 struct flow_dissector_key_basic *key =
1410 skb_flow_dissector_target(f->dissector,
1411 FLOW_DISSECTOR_KEY_BASIC,
1413 struct flow_dissector_key_basic *mask =
1414 skb_flow_dissector_target(f->dissector,
1415 FLOW_DISSECTOR_KEY_BASIC,
1417 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1418 ntohs(mask->n_proto));
1419 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1420 ntohs(key->n_proto));
1423 *match_level = MLX5_MATCH_L2;
1426 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1427 struct flow_dissector_key_control *key =
1428 skb_flow_dissector_target(f->dissector,
1429 FLOW_DISSECTOR_KEY_CONTROL,
1432 struct flow_dissector_key_control *mask =
1433 skb_flow_dissector_target(f->dissector,
1434 FLOW_DISSECTOR_KEY_CONTROL,
1436 addr_type = key->addr_type;
1438 /* the HW doesn't support frag first/later */
1439 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1442 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1443 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1444 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1445 key->flags & FLOW_DIS_IS_FRAGMENT);
1447 /* the HW doesn't need L3 inline to match on frag=no */
1448 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
1449 *match_level = MLX5_INLINE_MODE_L2;
1450 /* *** L2 attributes parsing up to here *** */
1452 *match_level = MLX5_INLINE_MODE_IP;
1456 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1457 struct flow_dissector_key_basic *key =
1458 skb_flow_dissector_target(f->dissector,
1459 FLOW_DISSECTOR_KEY_BASIC,
1461 struct flow_dissector_key_basic *mask =
1462 skb_flow_dissector_target(f->dissector,
1463 FLOW_DISSECTOR_KEY_BASIC,
1465 ip_proto = key->ip_proto;
1467 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1469 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1473 *match_level = MLX5_MATCH_L3;
1476 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1477 struct flow_dissector_key_ipv4_addrs *key =
1478 skb_flow_dissector_target(f->dissector,
1479 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1481 struct flow_dissector_key_ipv4_addrs *mask =
1482 skb_flow_dissector_target(f->dissector,
1483 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1486 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1487 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1488 &mask->src, sizeof(mask->src));
1489 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1490 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1491 &key->src, sizeof(key->src));
1492 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1493 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1494 &mask->dst, sizeof(mask->dst));
1495 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1496 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1497 &key->dst, sizeof(key->dst));
1499 if (mask->src || mask->dst)
1500 *match_level = MLX5_MATCH_L3;
1503 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1504 struct flow_dissector_key_ipv6_addrs *key =
1505 skb_flow_dissector_target(f->dissector,
1506 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1508 struct flow_dissector_key_ipv6_addrs *mask =
1509 skb_flow_dissector_target(f->dissector,
1510 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1513 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1514 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1515 &mask->src, sizeof(mask->src));
1516 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1517 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1518 &key->src, sizeof(key->src));
1520 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1521 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1522 &mask->dst, sizeof(mask->dst));
1523 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1524 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1525 &key->dst, sizeof(key->dst));
1527 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1528 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
1529 *match_level = MLX5_MATCH_L3;
1532 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1533 struct flow_dissector_key_ip *key =
1534 skb_flow_dissector_target(f->dissector,
1535 FLOW_DISSECTOR_KEY_IP,
1537 struct flow_dissector_key_ip *mask =
1538 skb_flow_dissector_target(f->dissector,
1539 FLOW_DISSECTOR_KEY_IP,
1542 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1543 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1545 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1546 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1548 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1549 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1552 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1553 ft_field_support.outer_ipv4_ttl))
1556 if (mask->tos || mask->ttl)
1557 *match_level = MLX5_MATCH_L3;
1560 /* *** L3 attributes parsing up to here *** */
1562 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1563 struct flow_dissector_key_ports *key =
1564 skb_flow_dissector_target(f->dissector,
1565 FLOW_DISSECTOR_KEY_PORTS,
1567 struct flow_dissector_key_ports *mask =
1568 skb_flow_dissector_target(f->dissector,
1569 FLOW_DISSECTOR_KEY_PORTS,
1573 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1574 tcp_sport, ntohs(mask->src));
1575 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1576 tcp_sport, ntohs(key->src));
1578 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1579 tcp_dport, ntohs(mask->dst));
1580 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1581 tcp_dport, ntohs(key->dst));
1585 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1586 udp_sport, ntohs(mask->src));
1587 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1588 udp_sport, ntohs(key->src));
1590 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1591 udp_dport, ntohs(mask->dst));
1592 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1593 udp_dport, ntohs(key->dst));
1596 netdev_err(priv->netdev,
1597 "Only UDP and TCP transport are supported\n");
1601 if (mask->src || mask->dst)
1602 *match_level = MLX5_MATCH_L4;
1605 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1606 struct flow_dissector_key_tcp *key =
1607 skb_flow_dissector_target(f->dissector,
1608 FLOW_DISSECTOR_KEY_TCP,
1610 struct flow_dissector_key_tcp *mask =
1611 skb_flow_dissector_target(f->dissector,
1612 FLOW_DISSECTOR_KEY_TCP,
1615 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1616 ntohs(mask->flags));
1617 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1621 *match_level = MLX5_MATCH_L4;
1627 static int parse_cls_flower(struct mlx5e_priv *priv,
1628 struct mlx5e_tc_flow *flow,
1629 struct mlx5_flow_spec *spec,
1630 struct tc_cls_flower_offload *f)
1632 struct mlx5_core_dev *dev = priv->mdev;
1633 struct mlx5_eswitch *esw = dev->priv.eswitch;
1634 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1635 struct mlx5_eswitch_rep *rep;
1639 err = __parse_cls_flower(priv, spec, f, &match_level);
1641 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1643 if (rep->vport != FDB_UPLINK_VPORT &&
1644 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1645 esw->offloads.inline_mode < match_level)) {
1646 netdev_warn(priv->netdev,
1647 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1648 match_level, esw->offloads.inline_mode);
1653 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1654 flow->esw_attr->match_level = match_level;
1656 flow->nic_attr->match_level = match_level;
1661 struct pedit_headers {
1669 static int pedit_header_offsets[] = {
1670 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1671 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1672 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1673 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1674 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1677 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1679 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1680 struct pedit_headers *masks,
1681 struct pedit_headers *vals)
1683 u32 *curr_pmask, *curr_pval;
1685 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1688 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1689 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1691 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1694 *curr_pmask |= mask;
1695 *curr_pval |= (val & mask);
1703 struct mlx5_fields {
1709 #define OFFLOAD(fw_field, size, field, off) \
1710 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1712 static struct mlx5_fields fields[] = {
1713 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1714 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1715 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1716 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1717 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1719 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1720 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1721 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1723 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1724 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1725 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1726 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1727 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1728 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1729 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1730 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
1731 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
1733 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1734 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1735 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1737 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1738 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
1741 /* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1742 * max from the SW pedit action. On success, it says how many HW actions were
1745 static int offload_pedit_fields(struct pedit_headers *masks,
1746 struct pedit_headers *vals,
1747 struct mlx5e_tc_flow_parse_attr *parse_attr)
1749 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
1750 int i, action_size, nactions, max_actions, first, last, next_z;
1751 void *s_masks_p, *a_masks_p, *vals_p;
1752 struct mlx5_fields *f;
1753 u8 cmd, field_bsize;
1760 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1761 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1762 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1763 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1765 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1766 action = parse_attr->mod_hdr_actions;
1767 max_actions = parse_attr->num_mod_hdr_actions;
1770 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1772 /* avoid seeing bits set from previous iterations */
1776 s_masks_p = (void *)set_masks + f->offset;
1777 a_masks_p = (void *)add_masks + f->offset;
1779 memcpy(&s_mask, s_masks_p, f->size);
1780 memcpy(&a_mask, a_masks_p, f->size);
1782 if (!s_mask && !a_mask) /* nothing to offload here */
1785 if (s_mask && a_mask) {
1786 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1790 if (nactions == max_actions) {
1791 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1796 cmd = MLX5_ACTION_TYPE_SET;
1798 vals_p = (void *)set_vals + f->offset;
1799 /* clear to denote we consumed this field */
1800 memset(s_masks_p, 0, f->size);
1802 cmd = MLX5_ACTION_TYPE_ADD;
1804 vals_p = (void *)add_vals + f->offset;
1805 /* clear to denote we consumed this field */
1806 memset(a_masks_p, 0, f->size);
1809 field_bsize = f->size * BITS_PER_BYTE;
1811 if (field_bsize == 32) {
1812 mask_be32 = *(__be32 *)&mask;
1813 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1814 } else if (field_bsize == 16) {
1815 mask_be16 = *(__be16 *)&mask;
1816 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1819 first = find_first_bit(&mask, field_bsize);
1820 next_z = find_next_zero_bit(&mask, field_bsize, first);
1821 last = find_last_bit(&mask, field_bsize);
1822 if (first < next_z && next_z < last) {
1823 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
1828 MLX5_SET(set_action_in, action, action_type, cmd);
1829 MLX5_SET(set_action_in, action, field, f->field);
1831 if (cmd == MLX5_ACTION_TYPE_SET) {
1832 MLX5_SET(set_action_in, action, offset, first);
1833 /* length is num of bits to be written, zero means length of 32 */
1834 MLX5_SET(set_action_in, action, length, (last - first + 1));
1837 if (field_bsize == 32)
1838 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
1839 else if (field_bsize == 16)
1840 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
1841 else if (field_bsize == 8)
1842 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
1844 action += action_size;
1848 parse_attr->num_mod_hdr_actions = nactions;
1852 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1853 const struct tc_action *a, int namespace,
1854 struct mlx5e_tc_flow_parse_attr *parse_attr)
1856 int nkeys, action_size, max_actions;
1858 nkeys = tcf_pedit_nkeys(a);
1859 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1861 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1862 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1863 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1864 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1866 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1867 max_actions = min(max_actions, nkeys * 16);
1869 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1870 if (!parse_attr->mod_hdr_actions)
1873 parse_attr->num_mod_hdr_actions = max_actions;
1877 static const struct pedit_headers zero_masks = {};
1879 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1880 const struct tc_action *a, int namespace,
1881 struct mlx5e_tc_flow_parse_attr *parse_attr)
1883 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1884 int nkeys, i, err = -EOPNOTSUPP;
1885 u32 mask, val, offset;
1888 nkeys = tcf_pedit_nkeys(a);
1890 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1891 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1893 for (i = 0; i < nkeys; i++) {
1894 htype = tcf_pedit_htype(a, i);
1895 cmd = tcf_pedit_cmd(a, i);
1896 err = -EOPNOTSUPP; /* can't be all optimistic */
1898 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1899 netdev_warn(priv->netdev, "legacy pedit isn't offloaded\n");
1903 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1904 netdev_warn(priv->netdev, "pedit cmd %d isn't offloaded\n", cmd);
1908 mask = tcf_pedit_mask(a, i);
1909 val = tcf_pedit_val(a, i);
1910 offset = tcf_pedit_offset(a, i);
1912 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1917 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1921 err = offload_pedit_fields(masks, vals, parse_attr);
1923 goto out_dealloc_parsed_actions;
1925 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1926 cmd_masks = &masks[cmd];
1927 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1928 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
1929 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1930 16, 1, cmd_masks, sizeof(zero_masks), true);
1932 goto out_dealloc_parsed_actions;
1938 out_dealloc_parsed_actions:
1939 kfree(parse_attr->mod_hdr_actions);
1944 static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1946 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1947 TCA_CSUM_UPDATE_FLAG_UDP;
1949 /* The HW recalcs checksums only if re-writing headers */
1950 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1951 netdev_warn(priv->netdev,
1952 "TC csum action is only offloaded with pedit\n");
1956 if (update_flags & ~prot_flags) {
1957 netdev_warn(priv->netdev,
1958 "can't offload TC csum action for some header/s - flags %#x\n",
1966 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1967 struct tcf_exts *exts)
1969 const struct tc_action *a;
1970 bool modify_ip_header;
1977 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1978 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1980 /* for non-IP we only re-write MACs, so we're okay */
1981 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1984 modify_ip_header = false;
1985 tcf_exts_for_each_action(i, a, exts) {
1988 if (!is_tcf_pedit(a))
1991 nkeys = tcf_pedit_nkeys(a);
1992 for (k = 0; k < nkeys; k++) {
1993 htype = tcf_pedit_htype(a, k);
1994 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1995 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1996 modify_ip_header = true;
2002 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2003 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2004 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2005 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2013 static bool actions_match_supported(struct mlx5e_priv *priv,
2014 struct tcf_exts *exts,
2015 struct mlx5e_tc_flow_parse_attr *parse_attr,
2016 struct mlx5e_tc_flow *flow)
2020 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2021 actions = flow->esw_attr->action;
2023 actions = flow->nic_attr->action;
2025 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2026 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2029 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2030 return modify_header_match_supported(&parse_attr->spec, exts);
2035 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2037 struct mlx5_core_dev *fmdev, *pmdev;
2038 u64 fsystem_guid, psystem_guid;
2041 pmdev = peer_priv->mdev;
2043 mlx5_query_nic_vport_system_image_guid(fmdev, &fsystem_guid);
2044 mlx5_query_nic_vport_system_image_guid(pmdev, &psystem_guid);
2046 return (fsystem_guid == psystem_guid);
2049 static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
2050 struct mlx5e_tc_flow_parse_attr *parse_attr,
2051 struct mlx5e_tc_flow *flow)
2053 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2054 const struct tc_action *a;
2059 if (!tcf_exts_has_actions(exts))
2062 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2064 tcf_exts_for_each_action(i, a, exts) {
2065 if (is_tcf_gact_shot(a)) {
2066 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2067 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2068 flow_table_properties_nic_receive.flow_counter))
2069 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2073 if (is_tcf_pedit(a)) {
2074 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
2079 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2080 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2084 if (is_tcf_csum(a)) {
2085 if (csum_offload_supported(priv, action,
2086 tcf_csum_update_flags(a)))
2092 if (is_tcf_mirred_egress_redirect(a)) {
2093 struct net_device *peer_dev = tcf_mirred_dev(a);
2095 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2096 same_hw_devs(priv, netdev_priv(peer_dev))) {
2097 parse_attr->mirred_ifindex = peer_dev->ifindex;
2098 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
2099 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2100 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2102 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2109 if (is_tcf_skbedit_mark(a)) {
2110 u32 mark = tcf_skbedit_mark(a);
2112 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2113 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
2118 attr->flow_tag = mark;
2119 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2126 attr->action = action;
2127 if (!actions_match_supported(priv, exts, parse_attr, flow))
2133 static inline int cmp_encap_info(struct ip_tunnel_key *a,
2134 struct ip_tunnel_key *b)
2136 return memcmp(a, b, sizeof(*a));
2139 static inline int hash_encap_info(struct ip_tunnel_key *key)
2141 return jhash(key, sizeof(*key), 0);
2144 static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2145 struct net_device *mirred_dev,
2146 struct net_device **out_dev,
2148 struct neighbour **out_n,
2151 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2152 struct mlx5e_rep_priv *uplink_rpriv;
2154 struct neighbour *n = NULL;
2156 #if IS_ENABLED(CONFIG_INET)
2159 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
2160 ret = PTR_ERR_OR_ZERO(rt);
2166 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2167 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2168 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
2169 *out_dev = uplink_rpriv->netdev;
2171 *out_dev = rt->dst.dev;
2174 *out_ttl = ip4_dst_hoplimit(&rt->dst);
2175 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2184 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2185 struct net_device *peer_netdev)
2187 struct mlx5e_priv *peer_priv;
2189 peer_priv = netdev_priv(peer_netdev);
2191 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2192 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2193 same_hw_devs(priv, peer_priv) &&
2194 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2195 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2198 static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2199 struct net_device *mirred_dev,
2200 struct net_device **out_dev,
2202 struct neighbour **out_n,
2205 struct neighbour *n = NULL;
2206 struct dst_entry *dst;
2208 #if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
2209 struct mlx5e_rep_priv *uplink_rpriv;
2210 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2213 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2219 *out_ttl = ip6_dst_hoplimit(dst);
2221 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2222 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2223 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
2224 *out_dev = uplink_rpriv->netdev;
2226 *out_dev = dst->dev;
2231 n = dst_neigh_lookup(dst, &fl6->daddr);
2240 static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2241 char buf[], int encap_size,
2242 unsigned char h_dest[ETH_ALEN],
2246 __be16 udp_dst_port,
2249 struct ethhdr *eth = (struct ethhdr *)buf;
2250 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2251 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2252 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2254 memset(buf, 0, encap_size);
2256 ether_addr_copy(eth->h_dest, h_dest);
2257 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2258 eth->h_proto = htons(ETH_P_IP);
2265 ip->protocol = IPPROTO_UDP;
2269 udp->dest = udp_dst_port;
2270 vxh->vx_flags = VXLAN_HF_VNI;
2271 vxh->vx_vni = vxlan_vni_field(vx_vni);
2274 static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2275 char buf[], int encap_size,
2276 unsigned char h_dest[ETH_ALEN],
2278 struct in6_addr *daddr,
2279 struct in6_addr *saddr,
2280 __be16 udp_dst_port,
2283 struct ethhdr *eth = (struct ethhdr *)buf;
2284 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2285 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2286 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2288 memset(buf, 0, encap_size);
2290 ether_addr_copy(eth->h_dest, h_dest);
2291 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2292 eth->h_proto = htons(ETH_P_IPV6);
2294 ip6_flow_hdr(ip6h, tos, 0);
2295 /* the HW fills up ipv6 payload len */
2296 ip6h->nexthdr = IPPROTO_UDP;
2297 ip6h->hop_limit = ttl;
2298 ip6h->daddr = *daddr;
2299 ip6h->saddr = *saddr;
2301 udp->dest = udp_dst_port;
2302 vxh->vx_flags = VXLAN_HF_VNI;
2303 vxh->vx_vni = vxlan_vni_field(vx_vni);
2306 static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2307 struct net_device *mirred_dev,
2308 struct mlx5e_encap_entry *e)
2310 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2311 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
2312 struct ip_tunnel_key *tun_key = &e->tun_info.key;
2313 struct net_device *out_dev;
2314 struct neighbour *n = NULL;
2315 struct flowi4 fl4 = {};
2316 u8 nud_state, tos, ttl;
2320 if (max_encap_size < ipv4_encap_size) {
2321 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2322 ipv4_encap_size, max_encap_size);
2326 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
2330 switch (e->tunnel_type) {
2331 case MLX5_HEADER_TYPE_VXLAN:
2332 fl4.flowi4_proto = IPPROTO_UDP;
2333 fl4.fl4_dport = tun_key->tp_dst;
2343 fl4.flowi4_tos = tun_key->tos;
2344 fl4.daddr = tun_key->u.ipv4.dst;
2345 fl4.saddr = tun_key->u.ipv4.src;
2347 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
2352 /* used by mlx5e_detach_encap to lookup a neigh hash table
2353 * entry in the neigh hash table when a user deletes a rule
2355 e->m_neigh.dev = n->dev;
2356 e->m_neigh.family = n->ops->family;
2357 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2358 e->out_dev = out_dev;
2360 /* It's importent to add the neigh to the hash table before checking
2361 * the neigh validity state. So if we'll get a notification, in case the
2362 * neigh changes it's validity state, we would find the relevant neigh
2365 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2369 read_lock_bh(&n->lock);
2370 nud_state = n->nud_state;
2371 ether_addr_copy(e->h_dest, n->ha);
2372 read_unlock_bh(&n->lock);
2374 switch (e->tunnel_type) {
2375 case MLX5_HEADER_TYPE_VXLAN:
2376 gen_vxlan_header_ipv4(out_dev, encap_header,
2377 ipv4_encap_size, e->h_dest, tos, ttl,
2379 fl4.saddr, tun_key->tp_dst,
2380 tunnel_id_to_key32(tun_key->tun_id));
2384 goto destroy_neigh_entry;
2386 e->encap_size = ipv4_encap_size;
2387 e->encap_header = encap_header;
2389 if (!(nud_state & NUD_VALID)) {
2390 neigh_event_send(n, NULL);
2395 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
2396 ipv4_encap_size, encap_header, &e->encap_id);
2398 goto destroy_neigh_entry;
2400 e->flags |= MLX5_ENCAP_ENTRY_VALID;
2401 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2405 destroy_neigh_entry:
2406 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2408 kfree(encap_header);
2415 static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2416 struct net_device *mirred_dev,
2417 struct mlx5e_encap_entry *e)
2419 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
2420 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
2421 struct ip_tunnel_key *tun_key = &e->tun_info.key;
2422 struct net_device *out_dev;
2423 struct neighbour *n = NULL;
2424 struct flowi6 fl6 = {};
2425 u8 nud_state, tos, ttl;
2429 if (max_encap_size < ipv6_encap_size) {
2430 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2431 ipv6_encap_size, max_encap_size);
2435 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
2439 switch (e->tunnel_type) {
2440 case MLX5_HEADER_TYPE_VXLAN:
2441 fl6.flowi6_proto = IPPROTO_UDP;
2442 fl6.fl6_dport = tun_key->tp_dst;
2452 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2453 fl6.daddr = tun_key->u.ipv6.dst;
2454 fl6.saddr = tun_key->u.ipv6.src;
2456 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
2461 /* used by mlx5e_detach_encap to lookup a neigh hash table
2462 * entry in the neigh hash table when a user deletes a rule
2464 e->m_neigh.dev = n->dev;
2465 e->m_neigh.family = n->ops->family;
2466 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2467 e->out_dev = out_dev;
2469 /* It's importent to add the neigh to the hash table before checking
2470 * the neigh validity state. So if we'll get a notification, in case the
2471 * neigh changes it's validity state, we would find the relevant neigh
2474 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2478 read_lock_bh(&n->lock);
2479 nud_state = n->nud_state;
2480 ether_addr_copy(e->h_dest, n->ha);
2481 read_unlock_bh(&n->lock);
2483 switch (e->tunnel_type) {
2484 case MLX5_HEADER_TYPE_VXLAN:
2485 gen_vxlan_header_ipv6(out_dev, encap_header,
2486 ipv6_encap_size, e->h_dest, tos, ttl,
2488 &fl6.saddr, tun_key->tp_dst,
2489 tunnel_id_to_key32(tun_key->tun_id));
2493 goto destroy_neigh_entry;
2496 e->encap_size = ipv6_encap_size;
2497 e->encap_header = encap_header;
2499 if (!(nud_state & NUD_VALID)) {
2500 neigh_event_send(n, NULL);
2505 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
2506 ipv6_encap_size, encap_header, &e->encap_id);
2508 goto destroy_neigh_entry;
2510 e->flags |= MLX5_ENCAP_ENTRY_VALID;
2511 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
2515 destroy_neigh_entry:
2516 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
2518 kfree(encap_header);
2525 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2526 struct ip_tunnel_info *tun_info,
2527 struct net_device *mirred_dev,
2528 struct net_device **encap_dev,
2529 struct mlx5e_tc_flow *flow)
2531 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2532 unsigned short family = ip_tunnel_info_af(tun_info);
2533 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2534 struct ip_tunnel_key *key = &tun_info->key;
2535 struct mlx5e_encap_entry *e;
2536 int tunnel_type, err = 0;
2540 /* udp dst port must be set */
2541 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2542 goto vxlan_encap_offload_err;
2544 /* setting udp src port isn't supported */
2545 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2546 vxlan_encap_offload_err:
2547 netdev_warn(priv->netdev,
2548 "must set udp dst port and not set udp src port\n");
2552 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->tp_dst)) &&
2553 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
2554 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2556 netdev_warn(priv->netdev,
2557 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
2561 hash_key = hash_encap_info(key);
2563 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2564 encap_hlist, hash_key) {
2565 if (!cmp_encap_info(&e->tun_info.key, key)) {
2571 /* must verify if encap is valid or not */
2575 e = kzalloc(sizeof(*e), GFP_KERNEL);
2579 e->tun_info = *tun_info;
2580 e->tunnel_type = tunnel_type;
2581 INIT_LIST_HEAD(&e->flows);
2583 if (family == AF_INET)
2584 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
2585 else if (family == AF_INET6)
2586 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
2588 if (err && err != -EAGAIN)
2591 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2594 list_add(&flow->encap, &e->flows);
2595 *encap_dev = e->out_dev;
2596 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2597 attr->encap_id = e->encap_id;
2608 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2609 const struct tc_action *a,
2610 struct mlx5_esw_flow_attr *attr,
2613 u8 vlan_idx = attr->total_vlan;
2615 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2618 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
2620 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2621 MLX5_FS_VLAN_DEPTH))
2624 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2626 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2628 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
2629 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2630 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2631 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2632 if (!attr->vlan_proto[vlan_idx])
2633 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2636 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2637 MLX5_FS_VLAN_DEPTH))
2640 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2642 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2643 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2644 tcf_vlan_push_prio(a)))
2647 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
2649 } else { /* action is TCA_VLAN_ACT_MODIFY */
2653 attr->total_vlan = vlan_idx + 1;
2658 static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
2659 struct mlx5e_tc_flow_parse_attr *parse_attr,
2660 struct mlx5e_tc_flow *flow)
2662 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2663 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2664 struct ip_tunnel_info *info = NULL;
2665 const struct tc_action *a;
2671 if (!tcf_exts_has_actions(exts))
2674 attr->in_rep = rpriv->rep;
2675 attr->in_mdev = priv->mdev;
2677 tcf_exts_for_each_action(i, a, exts) {
2678 if (is_tcf_gact_shot(a)) {
2679 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2680 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2684 if (is_tcf_pedit(a)) {
2685 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2690 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2691 attr->mirror_count = attr->out_count;
2695 if (is_tcf_csum(a)) {
2696 if (csum_offload_supported(priv, action,
2697 tcf_csum_update_flags(a)))
2703 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
2704 struct mlx5e_priv *out_priv;
2705 struct net_device *out_dev;
2707 out_dev = tcf_mirred_dev(a);
2709 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
2710 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2715 if (switchdev_port_same_parent_id(priv->netdev,
2717 is_merged_eswitch_dev(priv, out_dev)) {
2718 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2719 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2720 out_priv = netdev_priv(out_dev);
2721 rpriv = out_priv->ppriv;
2722 attr->out_rep[attr->out_count] = rpriv->rep;
2723 attr->out_mdev[attr->out_count++] = out_priv->mdev;
2725 parse_attr->mirred_ifindex = out_dev->ifindex;
2726 parse_attr->tun_info = *info;
2727 attr->parse_attr = parse_attr;
2728 action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2729 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2730 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2731 /* attr->out_rep is resolved when we handle encap */
2733 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2734 priv->netdev->name, out_dev->name);
2740 if (is_tcf_tunnel_set(a)) {
2741 info = tcf_tunnel_info(a);
2746 attr->mirror_count = attr->out_count;
2750 if (is_tcf_vlan(a)) {
2751 err = parse_tc_vlan_action(priv, a, attr, &action);
2756 attr->mirror_count = attr->out_count;
2760 if (is_tcf_tunnel_release(a)) {
2761 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2768 attr->action = action;
2769 if (!actions_match_supported(priv, exts, parse_attr, flow))
2772 if (attr->out_count > 1 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
2773 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2780 static void get_flags(int flags, u8 *flow_flags)
2782 u8 __flow_flags = 0;
2784 if (flags & MLX5E_TC_INGRESS)
2785 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2786 if (flags & MLX5E_TC_EGRESS)
2787 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2789 *flow_flags = __flow_flags;
2792 static const struct rhashtable_params tc_ht_params = {
2793 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2794 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2795 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2796 .automatic_shrinking = true,
2799 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
2801 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2802 struct mlx5e_rep_priv *uplink_rpriv;
2804 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
2805 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2806 return &uplink_rpriv->tc_ht;
2808 return &priv->fs.tc.ht;
2811 int mlx5e_configure_flower(struct mlx5e_priv *priv,
2812 struct tc_cls_flower_offload *f, int flags)
2814 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2815 struct mlx5e_tc_flow_parse_attr *parse_attr;
2816 struct rhashtable *tc_ht = get_tc_ht(priv);
2817 struct mlx5e_tc_flow *flow;
2818 int attr_size, err = 0;
2821 get_flags(flags, &flow_flags);
2823 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2825 netdev_warn_once(priv->netdev, "flow cookie %lx already exists, ignoring\n", f->cookie);
2829 if (esw && esw->mode == SRIOV_OFFLOADS) {
2830 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2831 attr_size = sizeof(struct mlx5_esw_flow_attr);
2833 flow_flags |= MLX5E_TC_FLOW_NIC;
2834 attr_size = sizeof(struct mlx5_nic_flow_attr);
2837 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
2838 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
2839 if (!parse_attr || !flow) {
2844 flow->cookie = f->cookie;
2845 flow->flags = flow_flags;
2848 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
2852 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
2853 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
2856 flow->rule[0] = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
2858 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
2861 flow->rule[0] = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
2864 if (IS_ERR(flow->rule[0])) {
2865 err = PTR_ERR(flow->rule[0]);
2871 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2873 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
2874 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2877 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
2879 mlx5e_tc_del_flow(priv, flow);
2891 #define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2892 #define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2894 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2896 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2902 int mlx5e_delete_flower(struct mlx5e_priv *priv,
2903 struct tc_cls_flower_offload *f, int flags)
2905 struct rhashtable *tc_ht = get_tc_ht(priv);
2906 struct mlx5e_tc_flow *flow;
2908 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2909 if (!flow || !same_flow_direction(flow, flags))
2912 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
2914 mlx5e_tc_del_flow(priv, flow);
2921 int mlx5e_stats_flower(struct mlx5e_priv *priv,
2922 struct tc_cls_flower_offload *f, int flags)
2924 struct rhashtable *tc_ht = get_tc_ht(priv);
2925 struct mlx5e_tc_flow *flow;
2926 struct mlx5_fc *counter;
2931 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2932 if (!flow || !same_flow_direction(flow, flags))
2935 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2938 counter = mlx5_flow_rule_counter(flow->rule[0]);
2942 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2944 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
2949 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
2951 struct mlx5e_tc_table *tc = &priv->fs.tc;
2953 hash_init(tc->mod_hdr_tbl);
2954 hash_init(tc->hairpin_tbl);
2956 return rhashtable_init(&tc->ht, &tc_ht_params);
2959 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2961 struct mlx5e_tc_flow *flow = ptr;
2962 struct mlx5e_priv *priv = flow->priv;
2964 mlx5e_tc_del_flow(priv, flow);
2968 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
2970 struct mlx5e_tc_table *tc = &priv->fs.tc;
2972 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
2974 if (!IS_ERR_OR_NULL(tc->t)) {
2975 mlx5_destroy_flow_table(tc->t);
2980 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
2982 return rhashtable_init(tc_ht, &tc_ht_params);
2985 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
2987 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
2990 int mlx5e_tc_num_filters(struct mlx5e_priv *priv)
2992 struct rhashtable *tc_ht = get_tc_ht(priv);
2994 return atomic_read(&tc_ht->nelems);