2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
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6 * General Public License (GPL) Version 2, available from the file
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32 #ifndef __MLX5_EN_STATS_H__
33 #define __MLX5_EN_STATS_H__
35 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
44 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
45 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
50 char format[ETH_GSTRING_LEN];
51 size_t offset; /* Byte offset */
54 struct mlx5e_sw_stats {
61 u64 tx_tso_inner_packets;
62 u64 tx_tso_inner_bytes;
63 u64 tx_added_vlan_packets;
66 u64 rx_removed_vlan_packets;
67 u64 rx_csum_unnecessary;
70 u64 rx_csum_unnecessary_inner;
76 u64 tx_csum_partial_inner;
85 u64 rx_buff_alloc_err;
86 u64 rx_cqe_compress_blks;
87 u64 rx_cqe_compress_pkts;
96 /* Special handling counters */
97 u64 link_down_events_phy;
100 struct mlx5e_qcounter_stats {
101 u32 rx_out_of_buffer;
102 u32 rx_if_down_packets;
105 struct mlx5e_vnic_env_stats {
106 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
109 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
110 vstats->query_vport_out, c)
112 struct mlx5e_vport_stats {
113 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
116 #define PPORT_802_3_GET(pstats, c) \
117 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
118 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
119 #define PPORT_2863_GET(pstats, c) \
120 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
121 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
122 #define PPORT_2819_GET(pstats, c) \
123 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
124 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
125 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
126 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
127 counter_set.phys_layer_statistical_cntrs.c##_high)
128 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
129 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
130 counter_set.eth_per_prio_grp_data_layout.c##_high)
131 #define NUM_PPORT_PRIO 8
132 #define PPORT_ETH_EXT_GET(pstats, c) \
133 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
134 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
136 struct mlx5e_pport_stats {
137 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
138 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
139 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
140 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
141 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
142 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
143 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
146 #define PCIE_PERF_GET(pcie_stats, c) \
147 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
148 counter_set.pcie_perf_cntrs_grp_data_layout.c)
150 #define PCIE_PERF_GET64(pcie_stats, c) \
151 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
152 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
154 struct mlx5e_pcie_stats {
155 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
158 struct mlx5e_rq_stats {
162 u64 csum_unnecessary;
163 u64 csum_unnecessary_inner;
167 u64 removed_vlan_packets;
174 u64 cqe_compress_blks;
175 u64 cqe_compress_pkts;
184 struct mlx5e_sq_stats {
185 /* commonly accessed in data path */
191 u64 tso_inner_packets;
194 u64 csum_partial_inner;
195 u64 added_vlan_packets;
197 /* less likely accessed in data path */
206 struct mlx5e_ch_stats {
211 struct mlx5e_sw_stats sw;
212 struct mlx5e_qcounter_stats qcnt;
213 struct mlx5e_vnic_env_stats vnic;
214 struct mlx5e_vport_stats vport;
215 struct mlx5e_pport_stats pport;
216 struct rtnl_link_stats64 vf_vport;
217 struct mlx5e_pcie_stats pcie;
221 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
225 struct mlx5e_stats_grp {
226 u16 update_stats_mask;
227 int (*get_num_stats)(struct mlx5e_priv *priv);
228 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
229 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
230 void (*update_stats)(struct mlx5e_priv *priv);
233 extern const struct mlx5e_stats_grp mlx5e_stats_grps[];
234 extern const int mlx5e_num_stats_grps;
236 #endif /* __MLX5_EN_STATS_H__ */