drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "eswitch.h"
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "en_rep.h"
  42 #include "en_accel/ipsec.h"
  43 #include "en_accel/ipsec_rxtx.h"
  44 #include "accel/ipsec.h"
  45 #include "vxlan.h"
  46
  47 struct mlx5e_rq_param {
  48         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  49         struct mlx5_wq_param    wq;
  50 };
  51
  52 struct mlx5e_sq_param {
  53         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  54         struct mlx5_wq_param       wq;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)
  75 {
  76         return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);
  77 }
  78
  79 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  80 {
  81         return MLX5_CAP_GEN(mdev, striding_rq) &&
  82                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  83                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  84 }
  85
  86 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
  87                               struct mlx5e_params *params, u8 rq_type)
  88 {
  89         params->rq_wq_type = rq_type;
  90         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
  91         switch (params->rq_wq_type) {
  92         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  93                 params->log_rq_size = is_kdump_kernel() ?
  94                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
  95                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  96                 params->mpwqe_log_stride_sz =
  97                         MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
  98                         MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
  99                         MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
 100                 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
 101                         params->mpwqe_log_stride_sz;
 102                 break;
 103         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 104                 params->log_rq_size = is_kdump_kernel() ?
 105                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 106                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 107                 params->rq_headroom = params->xdp_prog ?
 108                         XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 109                 params->rq_headroom += NET_IP_ALIGN;
 110
 111                 /* Extra room needed for build_skb */
 112                 params->lro_wqe_sz -= params->rq_headroom +
 113                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 114         }
 115
 116         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 117                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 118                        BIT(params->log_rq_size),
 119                        BIT(params->mpwqe_log_stride_sz),
 120                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 121 }
 122
 123 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 124 {
 125         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 126                     !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
 127                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 128                     MLX5_WQ_TYPE_LINKED_LIST;
 129         mlx5e_set_rq_type_params(mdev, params, rq_type);
 130 }
 131
 132 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 static void mlx5e_tx_timeout_work(struct work_struct *work)
 163 {
 164         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 165                                                tx_timeout_work);
 166         int err;
 167
 168         rtnl_lock();
 169         mutex_lock(&priv->state_lock);
 170         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 171                 goto unlock;
 172         mlx5e_close_locked(priv->netdev);
 173         err = mlx5e_open_locked(priv->netdev);
 174         if (err)
 175                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 176                            err);
 177 unlock:
 178         mutex_unlock(&priv->state_lock);
 179         rtnl_unlock();
 180 }
 181
 182 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 183 {
 184         struct mlx5e_sw_stats temp, *s = &temp;
 185         struct mlx5e_rq_stats *rq_stats;
 186         struct mlx5e_sq_stats *sq_stats;
 187         int i, j;
 188
 189         memset(s, 0, sizeof(*s));
 190         for (i = 0; i < priv->channels.num; i++) {
 191                 struct mlx5e_channel *c = priv->channels.c[i];
 192
 193                 rq_stats = &c->rq.stats;
 194
 195                 s->rx_packets   += rq_stats->packets;
 196                 s->rx_bytes     += rq_stats->bytes;
 197                 s->rx_lro_packets += rq_stats->lro_packets;
 198                 s->rx_lro_bytes += rq_stats->lro_bytes;
 199                 s->rx_csum_none += rq_stats->csum_none;
 200                 s->rx_csum_complete += rq_stats->csum_complete;
 201                 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
 202                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 203                 s->rx_xdp_drop += rq_stats->xdp_drop;
 204                 s->rx_xdp_tx += rq_stats->xdp_tx;
 205                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 206                 s->rx_wqe_err   += rq_stats->wqe_err;
 207                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 208                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 209                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 210                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 211                 s->rx_page_reuse  += rq_stats->page_reuse;
 212                 s->rx_cache_reuse += rq_stats->cache_reuse;
 213                 s->rx_cache_full  += rq_stats->cache_full;
 214                 s->rx_cache_empty += rq_stats->cache_empty;
 215                 s->rx_cache_busy  += rq_stats->cache_busy;
 216                 s->rx_cache_waive += rq_stats->cache_waive;
 217
 218                 for (j = 0; j < priv->channels.params.num_tc; j++) {
 219                         sq_stats = &c->sq[j].stats;
 220
 221                         s->tx_packets           += sq_stats->packets;
 222                         s->tx_bytes             += sq_stats->bytes;
 223                         s->tx_tso_packets       += sq_stats->tso_packets;
 224                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 225                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 226                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 227                         s->tx_queue_stopped     += sq_stats->stopped;
 228                         s->tx_queue_wake        += sq_stats->wake;
 229                         s->tx_queue_dropped     += sq_stats->dropped;
 230                         s->tx_xmit_more         += sq_stats->xmit_more;
 231                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 232                         s->tx_csum_none         += sq_stats->csum_none;
 233                         s->tx_csum_partial      += sq_stats->csum_partial;
 234                 }
 235         }
 236
 237         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 238                                 priv->stats.pport.phy_counters,
 239                                 counter_set.phys_layer_cntrs.link_down_events);
 240         memcpy(&priv->stats.sw, s, sizeof(*s));
 241 }
 242
 243 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 244 {
 245         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 246         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 247         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 248         struct mlx5_core_dev *mdev = priv->mdev;
 249
 250         MLX5_SET(query_vport_counter_in, in, opcode,
 251                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 252         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 253         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 254
 255         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 256 }
 257
 258 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
 259 {
 260         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 261         struct mlx5_core_dev *mdev = priv->mdev;
 262         u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
 263         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 264         int prio;
 265         void *out;
 266
 267         MLX5_SET(ppcnt_reg, in, local_port, 1);
 268
 269         out = pstats->IEEE_802_3_counters;
 270         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 271         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 272
 273         if (!full)
 274                 return;
 275
 276         out = pstats->RFC_2863_counters;
 277         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 278         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 279
 280         out = pstats->RFC_2819_counters;
 281         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 282         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 283
 284         out = pstats->phy_counters;
 285         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 286         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 287
 288         if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
 289                 out = pstats->phy_statistical_counters;
 290                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 291                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 292         }
 293
 294         if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
 295                 out = pstats->eth_ext_counters;
 296                 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 297                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 298         }
 299
 300         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 301         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 302                 out = pstats->per_prio_counters[prio];
 303                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 304                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 305                                      MLX5_REG_PPCNT, 0, 0);
 306         }
 307 }
 308
 309 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 310 {
 311         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 312         u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
 313         int err;
 314
 315         if (!priv->q_counter)
 316                 return;
 317
 318         err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
 319         if (err)
 320                 return;
 321
 322         qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
 323 }
 324
 325 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 326 {
 327         struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
 328         struct mlx5_core_dev *mdev = priv->mdev;
 329         u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
 330         int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 331         void *out;
 332
 333         if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
 334                 return;
 335
 336         out = pcie_stats->pcie_perf_counters;
 337         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 338         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 339 }
 340
 341 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
 342 {
 343         if (full) {
 344                 mlx5e_update_pcie_counters(priv);
 345                 mlx5e_ipsec_update_stats(priv);
 346         }
 347         mlx5e_update_pport_counters(priv, full);
 348         mlx5e_update_vport_counters(priv);
 349         mlx5e_update_q_counter(priv);
 350         mlx5e_update_sw_counters(priv);
 351 }
 352
 353 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 354 {
 355         mlx5e_update_stats(priv, false);
 356 }
 357
 358 void mlx5e_update_stats_work(struct work_struct *work)
 359 {
 360         struct delayed_work *dwork = to_delayed_work(work);
 361         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 362                                                update_stats_work);
 363         mutex_lock(&priv->state_lock);
 364         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 365                 priv->profile->update_stats(priv);
 366                 queue_delayed_work(priv->wq, dwork,
 367                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 368         }
 369         mutex_unlock(&priv->state_lock);
 370 }
 371
 372 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 373                               enum mlx5_dev_event event, unsigned long param)
 374 {
 375         struct mlx5e_priv *priv = vpriv;
 376         struct ptp_clock_event ptp_event;
 377         struct mlx5_eqe *eqe = NULL;
 378
 379         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 380                 return;
 381
 382         switch (event) {
 383         case MLX5_DEV_EVENT_PORT_UP:
 384         case MLX5_DEV_EVENT_PORT_DOWN:
 385                 queue_work(priv->wq, &priv->update_carrier_work);
 386                 break;
 387         case MLX5_DEV_EVENT_PPS:
 388                 eqe = (struct mlx5_eqe *)param;
 389                 ptp_event.index = eqe->data.pps.pin;
 390                 ptp_event.timestamp =
 391                         timecounter_cyc2time(&priv->tstamp.clock,
 392                                              be64_to_cpu(eqe->data.pps.time_stamp));
 393                 mlx5e_pps_event_handler(vpriv, &ptp_event);
 394                 break;
 395         default:
 396                 break;
 397         }
 398 }
 399
 400 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 401 {
 402         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 403 }
 404
 405 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 406 {
 407         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 408         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 409 }
 410
 411 static inline int mlx5e_get_wqe_mtt_sz(void)
 412 {
 413         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 414          * To avoid copying garbage after the mtt array, we allocate
 415          * a little more.
 416          */
 417         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 418                      MLX5_UMR_MTT_ALIGNMENT);
 419 }
 420
 421 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 422                                        struct mlx5e_icosq *sq,
 423                                        struct mlx5e_umr_wqe *wqe,
 424                                        u16 ix)
 425 {
 426         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 427         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 428         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 429         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 430         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 431         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 432
 433         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 434                                       ds_cnt);
 435         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 436         cseg->imm       = rq->mkey_be;
 437
 438         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 439         ucseg->xlt_octowords =
 440                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 441         ucseg->bsf_octowords =
 442                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 443         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 444
 445         dseg->lkey = sq->mkey_be;
 446         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 447 }
 448
 449 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 450                                      struct mlx5e_channel *c)
 451 {
 452         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 453         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 454         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 455         int node = mlx5e_get_node(c->priv, c->ix);
 456         int i;
 457
 458         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 459                                         GFP_KERNEL, node);
 460         if (!rq->mpwqe.info)
 461                 goto err_out;
 462
 463         /* We allocate more than mtt_sz as we will align the pointer */
 464         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,
 465                                         GFP_KERNEL, node);
 466         if (unlikely(!rq->mpwqe.mtt_no_align))
 467                 goto err_free_wqe_info;
 468
 469         for (i = 0; i < wq_sz; i++) {
 470                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 471
 472                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 473                                         MLX5_UMR_ALIGN);
 474                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 475                                                   PCI_DMA_TODEVICE);
 476                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 477                         goto err_unmap_mtts;
 478
 479                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 480         }
 481
 482         return 0;
 483
 484 err_unmap_mtts:
 485         while (--i >= 0) {
 486                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 487
 488                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 489                                  PCI_DMA_TODEVICE);
 490         }
 491         kfree(rq->mpwqe.mtt_no_align);
 492 err_free_wqe_info:
 493         kfree(rq->mpwqe.info);
 494
 495 err_out:
 496         return -ENOMEM;
 497 }
 498
 499 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 500 {
 501         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 502         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 503         int i;
 504
 505         for (i = 0; i < wq_sz; i++) {
 506                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 507
 508                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 509                                  PCI_DMA_TODEVICE);
 510         }
 511         kfree(rq->mpwqe.mtt_no_align);
 512         kfree(rq->mpwqe.info);
 513 }
 514
 515 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 516                                  u64 npages, u8 page_shift,
 517                                  struct mlx5_core_mkey *umr_mkey)
 518 {
 519         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 520         void *mkc;
 521         u32 *in;
 522         int err;
 523
 524         if (!MLX5E_VALID_NUM_MTTS(npages))
 525                 return -EINVAL;
 526
 527         in = kvzalloc(inlen, GFP_KERNEL);
 528         if (!in)
 529                 return -ENOMEM;
 530
 531         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 532
 533         MLX5_SET(mkc, mkc, free, 1);
 534         MLX5_SET(mkc, mkc, umr_en, 1);
 535         MLX5_SET(mkc, mkc, lw, 1);
 536         MLX5_SET(mkc, mkc, lr, 1);
 537         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 538
 539         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 540         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 541         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 542         MLX5_SET(mkc, mkc, translations_octword_size,
 543                  MLX5_MTT_OCTW(npages));
 544         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 545
 546         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 547
 548         kvfree(in);
 549         return err;
 550 }
 551
 552 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 553 {
 554         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 555
 556         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 557 }
 558
 559 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 560                           struct mlx5e_params *params,
 561                           struct mlx5e_rq_param *rqp,
 562                           struct mlx5e_rq *rq)
 563 {
 564         struct mlx5_core_dev *mdev = c->mdev;
 565         void *rqc = rqp->rqc;
 566         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 567         u32 byte_count;
 568         int npages;
 569         int wq_sz;
 570         int err;
 571         int i;
 572
 573         rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
 574
 575         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 576                                 &rq->wq_ctrl);
 577         if (err)
 578                 return err;
 579
 580         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 581
 582         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 583
 584         rq->wq_type = params->rq_wq_type;
 585         rq->pdev    = c->pdev;
 586         rq->netdev  = c->netdev;
 587         rq->tstamp  = c->tstamp;
 588         rq->channel = c;
 589         rq->ix      = c->ix;
 590         rq->mdev    = mdev;
 591
 592         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 593         if (IS_ERR(rq->xdp_prog)) {
 594                 err = PTR_ERR(rq->xdp_prog);
 595                 rq->xdp_prog = NULL;
 596                 goto err_rq_wq_destroy;
 597         }
 598
 599         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 600         rq->buff.headroom = params->rq_headroom;
 601
 602         switch (rq->wq_type) {
 603         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 604
 605                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 606                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 607
 608                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 609 #ifdef CONFIG_MLX5_EN_IPSEC
 610                 if (MLX5_IPSEC_DEV(mdev)) {
 611                         err = -EINVAL;
 612                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 613                         goto err_rq_wq_destroy;
 614                 }
 615 #endif
 616                 if (!rq->handle_rx_cqe) {
 617                         err = -EINVAL;
 618                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 619                         goto err_rq_wq_destroy;
 620                 }
 621
 622                 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
 623                 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
 624
 625                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 626
 627                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 628                 if (err)
 629                         goto err_rq_wq_destroy;
 630                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 631
 632                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 633                 if (err)
 634                         goto err_destroy_umr_mkey;
 635                 break;
 636         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 637                 rq->wqe.frag_info =
 638                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 639                                      GFP_KERNEL,
 640                                      mlx5e_get_node(c->priv, c->ix));
 641                 if (!rq->wqe.frag_info) {
 642                         err = -ENOMEM;
 643                         goto err_rq_wq_destroy;
 644                 }
 645                 rq->post_wqes = mlx5e_post_rx_wqes;
 646                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 647
 648 #ifdef CONFIG_MLX5_EN_IPSEC
 649                 if (c->priv->ipsec)
 650                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 651                 else
 652 #endif
 653                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 654                 if (!rq->handle_rx_cqe) {
 655                         kfree(rq->wqe.frag_info);
 656                         err = -EINVAL;
 657                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 658                         goto err_rq_wq_destroy;
 659                 }
 660
 661                 byte_count = params->lro_en  ?
 662                                 params->lro_wqe_sz :
 663                                 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
 664 #ifdef CONFIG_MLX5_EN_IPSEC
 665                 if (MLX5_IPSEC_DEV(mdev))
 666                         byte_count += MLX5E_METADATA_ETHER_LEN;
 667 #endif
 668                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 669
 670                 /* calc the required page order */
 671                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
 672                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 673                 rq->buff.page_order = order_base_2(npages);
 674
 675                 byte_count |= MLX5_HW_START_PADDING;
 676                 rq->mkey_be = c->mkey_be;
 677         }
 678
 679         for (i = 0; i < wq_sz; i++) {
 680                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 681
 682                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 683                         u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
 684
 685                         wqe->data.addr = cpu_to_be64(dma_offset);
 686                 }
 687
 688                 wqe->data.byte_count = cpu_to_be32(byte_count);
 689                 wqe->data.lkey = rq->mkey_be;
 690         }
 691
 692         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 693         rq->am.mode = params->rx_cq_period_mode;
 694         rq->page_cache.head = 0;
 695         rq->page_cache.tail = 0;
 696
 697         return 0;
 698
 699 err_destroy_umr_mkey:
 700         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 701
 702 err_rq_wq_destroy:
 703         if (rq->xdp_prog)
 704                 bpf_prog_put(rq->xdp_prog);
 705         mlx5_wq_destroy(&rq->wq_ctrl);
 706
 707         return err;
 708 }
 709
 710 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 711 {
 712         int i;
 713
 714         if (rq->xdp_prog)
 715                 bpf_prog_put(rq->xdp_prog);
 716
 717         switch (rq->wq_type) {
 718         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 719                 mlx5e_rq_free_mpwqe_info(rq);
 720                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 721                 break;
 722         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 723                 kfree(rq->wqe.frag_info);
 724         }
 725
 726         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 727              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 728                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 729
 730                 mlx5e_page_release(rq, dma_info, false);
 731         }
 732         mlx5_wq_destroy(&rq->wq_ctrl);
 733 }
 734
 735 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 736                            struct mlx5e_rq_param *param)
 737 {
 738         struct mlx5_core_dev *mdev = rq->mdev;
 739
 740         void *in;
 741         void *rqc;
 742         void *wq;
 743         int inlen;
 744         int err;
 745
 746         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 747                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 748         in = kvzalloc(inlen, GFP_KERNEL);
 749         if (!in)
 750                 return -ENOMEM;
 751
 752         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 753         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 754
 755         memcpy(rqc, param->rqc, sizeof(param->rqc));
 756
 757         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 758         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 759         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 760                                                 MLX5_ADAPTER_PAGE_SHIFT);
 761         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 762
 763         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 764                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 765
 766         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 767
 768         kvfree(in);
 769
 770         return err;
 771 }
 772
 773 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 774                                  int next_state)
 775 {
 776         struct mlx5e_channel *c = rq->channel;
 777         struct mlx5_core_dev *mdev = c->mdev;
 778
 779         void *in;
 780         void *rqc;
 781         int inlen;
 782         int err;
 783
 784         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 785         in = kvzalloc(inlen, GFP_KERNEL);
 786         if (!in)
 787                 return -ENOMEM;
 788
 789         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 790
 791         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 792         MLX5_SET(rqc, rqc, state, next_state);
 793
 794         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 795
 796         kvfree(in);
 797
 798         return err;
 799 }
 800
 801 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 802 {
 803         struct mlx5e_channel *c = rq->channel;
 804         struct mlx5e_priv *priv = c->priv;
 805         struct mlx5_core_dev *mdev = priv->mdev;
 806
 807         void *in;
 808         void *rqc;
 809         int inlen;
 810         int err;
 811
 812         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 813         in = kvzalloc(inlen, GFP_KERNEL);
 814         if (!in)
 815                 return -ENOMEM;
 816
 817         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 818
 819         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 820         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 821                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 822         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 823         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 824
 825         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 826
 827         kvfree(in);
 828
 829         return err;
 830 }
 831
 832 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 833 {
 834         struct mlx5e_channel *c = rq->channel;
 835         struct mlx5_core_dev *mdev = c->mdev;
 836         void *in;
 837         void *rqc;
 838         int inlen;
 839         int err;
 840
 841         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 842         in = kvzalloc(inlen, GFP_KERNEL);
 843         if (!in)
 844                 return -ENOMEM;
 845
 846         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 847
 848         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 849         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 850                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 851         MLX5_SET(rqc, rqc, vsd, vsd);
 852         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 853
 854         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 855
 856         kvfree(in);
 857
 858         return err;
 859 }
 860
 861 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 862 {
 863         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 864 }
 865
 866 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 867 {
 868         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 869         struct mlx5e_channel *c = rq->channel;
 870
 871         struct mlx5_wq_ll *wq = &rq->wq;
 872         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 873
 874         while (time_before(jiffies, exp_time)) {
 875                 if (wq->cur_sz >= min_wqes)
 876                         return 0;
 877
 878                 msleep(20);
 879         }
 880
 881         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 882                     rq->rqn, wq->cur_sz, min_wqes);
 883         return -ETIMEDOUT;
 884 }
 885
 886 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 887 {
 888         struct mlx5_wq_ll *wq = &rq->wq;
 889         struct mlx5e_rx_wqe *wqe;
 890         __be16 wqe_ix_be;
 891         u16 wqe_ix;
 892
 893         /* UMR WQE (if in progress) is always at wq->head */
 894         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 895             rq->mpwqe.umr_in_progress)
 896                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 897
 898         while (!mlx5_wq_ll_is_empty(wq)) {
 899                 wqe_ix_be = *wq->tail_next;
 900                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 901                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 902                 rq->dealloc_wqe(rq, wqe_ix);
 903                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 904                                &wqe->next.next_wqe_index);
 905         }
 906
 907         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 908                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 909                  * but yet to be re-posted.
 910                  */
 911                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 912
 913                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 914                         rq->dealloc_wqe(rq, wqe_ix);
 915         }
 916 }
 917
 918 static int mlx5e_open_rq(struct mlx5e_channel *c,
 919                          struct mlx5e_params *params,
 920                          struct mlx5e_rq_param *param,
 921                          struct mlx5e_rq *rq)
 922 {
 923         int err;
 924
 925         err = mlx5e_alloc_rq(c, params, param, rq);
 926         if (err)
 927                 return err;
 928
 929         err = mlx5e_create_rq(rq, param);
 930         if (err)
 931                 goto err_free_rq;
 932
 933         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 934         if (err)
 935                 goto err_destroy_rq;
 936
 937         if (params->rx_am_enabled)
 938                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
 939
 940         return 0;
 941
 942 err_destroy_rq:
 943         mlx5e_destroy_rq(rq);
 944 err_free_rq:
 945         mlx5e_free_rq(rq);
 946
 947         return err;
 948 }
 949
 950 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 951 {
 952         struct mlx5e_icosq *sq = &rq->channel->icosq;
 953         u16 pi = sq->pc & sq->wq.sz_m1;
 954         struct mlx5e_tx_wqe *nopwqe;
 955
 956         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 957         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 958         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 959         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 960 }
 961
 962 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 963 {
 964         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 965         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 966 }
 967
 968 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 969 {
 970         cancel_work_sync(&rq->am.work);
 971         mlx5e_destroy_rq(rq);
 972         mlx5e_free_rx_descs(rq);
 973         mlx5e_free_rq(rq);
 974 }
 975
 976 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 977 {
 978         kfree(sq->db.di);
 979 }
 980
 981 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 982 {
 983         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 984
 985         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 986                                      GFP_KERNEL, numa);
 987         if (!sq->db.di) {
 988                 mlx5e_free_xdpsq_db(sq);
 989                 return -ENOMEM;
 990         }
 991
 992         return 0;
 993 }
 994
 995 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 996                              struct mlx5e_params *params,
 997                              struct mlx5e_sq_param *param,
 998                              struct mlx5e_xdpsq *sq)
 999 {
1000         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1001         struct mlx5_core_dev *mdev = c->mdev;
1002         int err;
1003
1004         sq->pdev      = c->pdev;
1005         sq->mkey_be   = c->mkey_be;
1006         sq->channel   = c;
1007         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1008         sq->min_inline_mode = params->tx_min_inline_mode;
1009
1010         param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1011         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1012         if (err)
1013                 return err;
1014         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1015
1016         err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1017         if (err)
1018                 goto err_sq_wq_destroy;
1019
1020         return 0;
1021
1022 err_sq_wq_destroy:
1023         mlx5_wq_destroy(&sq->wq_ctrl);
1024
1025         return err;
1026 }
1027
1028 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1029 {
1030         mlx5e_free_xdpsq_db(sq);
1031         mlx5_wq_destroy(&sq->wq_ctrl);
1032 }
1033
1034 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1035 {
1036         kfree(sq->db.ico_wqe);
1037 }
1038
1039 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1040 {
1041         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1042
1043         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1044                                       GFP_KERNEL, numa);
1045         if (!sq->db.ico_wqe)
1046                 return -ENOMEM;
1047
1048         return 0;
1049 }
1050
1051 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1052                              struct mlx5e_sq_param *param,
1053                              struct mlx5e_icosq *sq)
1054 {
1055         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1056         struct mlx5_core_dev *mdev = c->mdev;
1057         int err;
1058
1059         sq->mkey_be   = c->mkey_be;
1060         sq->channel   = c;
1061         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1062
1063         param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1064         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1065         if (err)
1066                 return err;
1067         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1068
1069         err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));
1070         if (err)
1071                 goto err_sq_wq_destroy;
1072
1073         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1074
1075         return 0;
1076
1077 err_sq_wq_destroy:
1078         mlx5_wq_destroy(&sq->wq_ctrl);
1079
1080         return err;
1081 }
1082
1083 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1084 {
1085         mlx5e_free_icosq_db(sq);
1086         mlx5_wq_destroy(&sq->wq_ctrl);
1087 }
1088
1089 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1090 {
1091         kfree(sq->db.wqe_info);
1092         kfree(sq->db.dma_fifo);
1093 }
1094
1095 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1096 {
1097         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1098         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1099
1100         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1101                                            GFP_KERNEL, numa);
1102         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1103                                            GFP_KERNEL, numa);
1104         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1105                 mlx5e_free_txqsq_db(sq);
1106                 return -ENOMEM;
1107         }
1108
1109         sq->dma_fifo_mask = df_sz - 1;
1110
1111         return 0;
1112 }
1113
1114 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1115                              int txq_ix,
1116                              struct mlx5e_params *params,
1117                              struct mlx5e_sq_param *param,
1118                              struct mlx5e_txqsq *sq)
1119 {
1120         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1121         struct mlx5_core_dev *mdev = c->mdev;
1122         int err;
1123
1124         sq->pdev      = c->pdev;
1125         sq->tstamp    = c->tstamp;
1126         sq->mkey_be   = c->mkey_be;
1127         sq->channel   = c;
1128         sq->txq_ix    = txq_ix;
1129         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1130         sq->max_inline      = params->tx_max_inline;
1131         sq->min_inline_mode = params->tx_min_inline_mode;
1132         if (MLX5_IPSEC_DEV(c->priv->mdev))
1133                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1134
1135         param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1136         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1137         if (err)
1138                 return err;
1139         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
1140
1141         err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1142         if (err)
1143                 goto err_sq_wq_destroy;
1144
1145         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1146
1147         return 0;
1148
1149 err_sq_wq_destroy:
1150         mlx5_wq_destroy(&sq->wq_ctrl);
1151
1152         return err;
1153 }
1154
1155 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1156 {
1157         mlx5e_free_txqsq_db(sq);
1158         mlx5_wq_destroy(&sq->wq_ctrl);
1159 }
1160
1161 struct mlx5e_create_sq_param {
1162         struct mlx5_wq_ctrl        *wq_ctrl;
1163         u32                         cqn;
1164         u32                         tisn;
1165         u8                          tis_lst_sz;
1166         u8                          min_inline_mode;
1167 };
1168
1169 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1170                            struct mlx5e_sq_param *param,
1171                            struct mlx5e_create_sq_param *csp,
1172                            u32 *sqn)
1173 {
1174         void *in;
1175         void *sqc;
1176         void *wq;
1177         int inlen;
1178         int err;
1179
1180         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1181                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1182         in = kvzalloc(inlen, GFP_KERNEL);
1183         if (!in)
1184                 return -ENOMEM;
1185
1186         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1187         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1188
1189         memcpy(sqc, param->sqc, sizeof(param->sqc));
1190         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1191         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1192         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1193
1194         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1195                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1196
1197         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1198
1199         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1200         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1201         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1202                                           MLX5_ADAPTER_PAGE_SHIFT);
1203         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1204
1205         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1206
1207         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1208
1209         kvfree(in);
1210
1211         return err;
1212 }
1213
1214 struct mlx5e_modify_sq_param {
1215         int curr_state;
1216         int next_state;
1217         bool rl_update;
1218         int rl_index;
1219 };
1220
1221 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1222                            struct mlx5e_modify_sq_param *p)
1223 {
1224         void *in;
1225         void *sqc;
1226         int inlen;
1227         int err;
1228
1229         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1230         in = kvzalloc(inlen, GFP_KERNEL);
1231         if (!in)
1232                 return -ENOMEM;
1233
1234         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1235
1236         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1237         MLX5_SET(sqc, sqc, state, p->next_state);
1238         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1239                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1240                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1241         }
1242
1243         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1244
1245         kvfree(in);
1246
1247         return err;
1248 }
1249
1250 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1251 {
1252         mlx5_core_destroy_sq(mdev, sqn);
1253 }
1254
1255 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1256                                struct mlx5e_sq_param *param,
1257                                struct mlx5e_create_sq_param *csp,
1258                                u32 *sqn)
1259 {
1260         struct mlx5e_modify_sq_param msp = {0};
1261         int err;
1262
1263         err = mlx5e_create_sq(mdev, param, csp, sqn);
1264         if (err)
1265                 return err;
1266
1267         msp.curr_state = MLX5_SQC_STATE_RST;
1268         msp.next_state = MLX5_SQC_STATE_RDY;
1269         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1270         if (err)
1271                 mlx5e_destroy_sq(mdev, *sqn);
1272
1273         return err;
1274 }
1275
1276 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1277                                 struct mlx5e_txqsq *sq, u32 rate);
1278
1279 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1280                             u32 tisn,
1281                             int txq_ix,
1282                             struct mlx5e_params *params,
1283                             struct mlx5e_sq_param *param,
1284                             struct mlx5e_txqsq *sq)
1285 {
1286         struct mlx5e_create_sq_param csp = {};
1287         u32 tx_rate;
1288         int err;
1289
1290         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1291         if (err)
1292                 return err;
1293
1294         csp.tisn            = tisn;
1295         csp.tis_lst_sz      = 1;
1296         csp.cqn             = sq->cq.mcq.cqn;
1297         csp.wq_ctrl         = &sq->wq_ctrl;
1298         csp.min_inline_mode = sq->min_inline_mode;
1299         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1300         if (err)
1301                 goto err_free_txqsq;
1302
1303         tx_rate = c->priv->tx_rates[sq->txq_ix];
1304         if (tx_rate)
1305                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1306
1307         return 0;
1308
1309 err_free_txqsq:
1310         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1311         mlx5e_free_txqsq(sq);
1312
1313         return err;
1314 }
1315
1316 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1317 {
1318         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1319         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1320         netdev_tx_reset_queue(sq->txq);
1321         netif_tx_start_queue(sq->txq);
1322 }
1323
1324 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1325 {
1326         __netif_tx_lock_bh(txq);
1327         netif_tx_stop_queue(txq);
1328         __netif_tx_unlock_bh(txq);
1329 }
1330
1331 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1332 {
1333         struct mlx5e_channel *c = sq->channel;
1334
1335         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1336         /* prevent netif_tx_wake_queue */
1337         napi_synchronize(&c->napi);
1338
1339         netif_tx_disable_queue(sq->txq);
1340
1341         /* last doorbell out, godspeed .. */
1342         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1343                 struct mlx5e_tx_wqe *nop;
1344
1345                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1346                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1347                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1348         }
1349 }
1350
1351 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1352 {
1353         struct mlx5e_channel *c = sq->channel;
1354         struct mlx5_core_dev *mdev = c->mdev;
1355
1356         mlx5e_destroy_sq(mdev, sq->sqn);
1357         if (sq->rate_limit)
1358                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1359         mlx5e_free_txqsq_descs(sq);
1360         mlx5e_free_txqsq(sq);
1361 }
1362
1363 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1364                             struct mlx5e_params *params,
1365                             struct mlx5e_sq_param *param,
1366                             struct mlx5e_icosq *sq)
1367 {
1368         struct mlx5e_create_sq_param csp = {};
1369         int err;
1370
1371         err = mlx5e_alloc_icosq(c, param, sq);
1372         if (err)
1373                 return err;
1374
1375         csp.cqn             = sq->cq.mcq.cqn;
1376         csp.wq_ctrl         = &sq->wq_ctrl;
1377         csp.min_inline_mode = params->tx_min_inline_mode;
1378         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1379         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1380         if (err)
1381                 goto err_free_icosq;
1382
1383         return 0;
1384
1385 err_free_icosq:
1386         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1387         mlx5e_free_icosq(sq);
1388
1389         return err;
1390 }
1391
1392 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1393 {
1394         struct mlx5e_channel *c = sq->channel;
1395
1396         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1397         napi_synchronize(&c->napi);
1398
1399         mlx5e_destroy_sq(c->mdev, sq->sqn);
1400         mlx5e_free_icosq(sq);
1401 }
1402
1403 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1404                             struct mlx5e_params *params,
1405                             struct mlx5e_sq_param *param,
1406                             struct mlx5e_xdpsq *sq)
1407 {
1408         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1409         struct mlx5e_create_sq_param csp = {};
1410         unsigned int inline_hdr_sz = 0;
1411         int err;
1412         int i;
1413
1414         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1415         if (err)
1416                 return err;
1417
1418         csp.tis_lst_sz      = 1;
1419         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1420         csp.cqn             = sq->cq.mcq.cqn;
1421         csp.wq_ctrl         = &sq->wq_ctrl;
1422         csp.min_inline_mode = sq->min_inline_mode;
1423         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1424         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1425         if (err)
1426                 goto err_free_xdpsq;
1427
1428         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1429                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1430                 ds_cnt++;
1431         }
1432
1433         /* Pre initialize fixed WQE fields */
1434         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1435                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1436                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1437                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1438                 struct mlx5_wqe_data_seg *dseg;
1439
1440                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1441                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1442
1443                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1444                 dseg->lkey = sq->mkey_be;
1445         }
1446
1447         return 0;
1448
1449 err_free_xdpsq:
1450         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1451         mlx5e_free_xdpsq(sq);
1452
1453         return err;
1454 }
1455
1456 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1457 {
1458         struct mlx5e_channel *c = sq->channel;
1459
1460         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1461         napi_synchronize(&c->napi);
1462
1463         mlx5e_destroy_sq(c->mdev, sq->sqn);
1464         mlx5e_free_xdpsq_descs(sq);
1465         mlx5e_free_xdpsq(sq);
1466 }
1467
1468 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1469                                  struct mlx5e_cq_param *param,
1470                                  struct mlx5e_cq *cq)
1471 {
1472         struct mlx5_core_cq *mcq = &cq->mcq;
1473         int eqn_not_used;
1474         unsigned int irqn;
1475         int err;
1476         u32 i;
1477
1478         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1479                                &cq->wq_ctrl);
1480         if (err)
1481                 return err;
1482
1483         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1484
1485         mcq->cqe_sz     = 64;
1486         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1487         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1488         *mcq->set_ci_db = 0;
1489         *mcq->arm_db    = 0;
1490         mcq->vector     = param->eq_ix;
1491         mcq->comp       = mlx5e_completion_event;
1492         mcq->event      = mlx5e_cq_error_event;
1493         mcq->irqn       = irqn;
1494
1495         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1496                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1497
1498                 cqe->op_own = 0xf1;
1499         }
1500
1501         cq->mdev = mdev;
1502
1503         return 0;
1504 }
1505
1506 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1507                           struct mlx5e_cq_param *param,
1508                           struct mlx5e_cq *cq)
1509 {
1510         struct mlx5_core_dev *mdev = c->priv->mdev;
1511         int err;
1512
1513         param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);
1514         param->wq.db_numa_node  = mlx5e_get_node(c->priv, c->ix);
1515         param->eq_ix   = c->ix;
1516
1517         err = mlx5e_alloc_cq_common(mdev, param, cq);
1518
1519         cq->napi    = &c->napi;
1520         cq->channel = c;
1521
1522         return err;
1523 }
1524
1525 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1526 {
1527         mlx5_cqwq_destroy(&cq->wq_ctrl);
1528 }
1529
1530 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1531 {
1532         struct mlx5_core_dev *mdev = cq->mdev;
1533         struct mlx5_core_cq *mcq = &cq->mcq;
1534
1535         void *in;
1536         void *cqc;
1537         int inlen;
1538         unsigned int irqn_not_used;
1539         int eqn;
1540         int err;
1541
1542         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1543                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1544         in = kvzalloc(inlen, GFP_KERNEL);
1545         if (!in)
1546                 return -ENOMEM;
1547
1548         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1549
1550         memcpy(cqc, param->cqc, sizeof(param->cqc));
1551
1552         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1553                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1554
1555         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1556
1557         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1558         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1559         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1560         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1561                                             MLX5_ADAPTER_PAGE_SHIFT);
1562         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1563
1564         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1565
1566         kvfree(in);
1567
1568         if (err)
1569                 return err;
1570
1571         mlx5e_cq_arm(cq);
1572
1573         return 0;
1574 }
1575
1576 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1577 {
1578         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1579 }
1580
1581 static int mlx5e_open_cq(struct mlx5e_channel *c,
1582                          struct mlx5e_cq_moder moder,
1583                          struct mlx5e_cq_param *param,
1584                          struct mlx5e_cq *cq)
1585 {
1586         struct mlx5_core_dev *mdev = c->mdev;
1587         int err;
1588
1589         err = mlx5e_alloc_cq(c, param, cq);
1590         if (err)
1591                 return err;
1592
1593         err = mlx5e_create_cq(cq, param);
1594         if (err)
1595                 goto err_free_cq;
1596
1597         if (MLX5_CAP_GEN(mdev, cq_moderation))
1598                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1599         return 0;
1600
1601 err_free_cq:
1602         mlx5e_free_cq(cq);
1603
1604         return err;
1605 }
1606
1607 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1608 {
1609         mlx5e_destroy_cq(cq);
1610         mlx5e_free_cq(cq);
1611 }
1612
1613 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1614                              struct mlx5e_params *params,
1615                              struct mlx5e_channel_param *cparam)
1616 {
1617         int err;
1618         int tc;
1619
1620         for (tc = 0; tc < c->num_tc; tc++) {
1621                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1622                                     &cparam->tx_cq, &c->sq[tc].cq);
1623                 if (err)
1624                         goto err_close_tx_cqs;
1625         }
1626
1627         return 0;
1628
1629 err_close_tx_cqs:
1630         for (tc--; tc >= 0; tc--)
1631                 mlx5e_close_cq(&c->sq[tc].cq);
1632
1633         return err;
1634 }
1635
1636 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1637 {
1638         int tc;
1639
1640         for (tc = 0; tc < c->num_tc; tc++)
1641                 mlx5e_close_cq(&c->sq[tc].cq);
1642 }
1643
1644 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1645                           struct mlx5e_params *params,
1646                           struct mlx5e_channel_param *cparam)
1647 {
1648         int err;
1649         int tc;
1650
1651         for (tc = 0; tc < params->num_tc; tc++) {
1652                 int txq_ix = c->ix + tc * params->num_channels;
1653
1654                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1655                                        params, &cparam->sq, &c->sq[tc]);
1656                 if (err)
1657                         goto err_close_sqs;
1658         }
1659
1660         return 0;
1661
1662 err_close_sqs:
1663         for (tc--; tc >= 0; tc--)
1664                 mlx5e_close_txqsq(&c->sq[tc]);
1665
1666         return err;
1667 }
1668
1669 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1670 {
1671         int tc;
1672
1673         for (tc = 0; tc < c->num_tc; tc++)
1674                 mlx5e_close_txqsq(&c->sq[tc]);
1675 }
1676
1677 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1678                                 struct mlx5e_txqsq *sq, u32 rate)
1679 {
1680         struct mlx5e_priv *priv = netdev_priv(dev);
1681         struct mlx5_core_dev *mdev = priv->mdev;
1682         struct mlx5e_modify_sq_param msp = {0};
1683         u16 rl_index = 0;
1684         int err;
1685
1686         if (rate == sq->rate_limit)
1687                 /* nothing to do */
1688                 return 0;
1689
1690         if (sq->rate_limit)
1691                 /* remove current rl index to free space to next ones */
1692                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1693
1694         sq->rate_limit = 0;
1695
1696         if (rate) {
1697                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1698                 if (err) {
1699                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1700                                    rate, err);
1701                         return err;
1702                 }
1703         }
1704
1705         msp.curr_state = MLX5_SQC_STATE_RDY;
1706         msp.next_state = MLX5_SQC_STATE_RDY;
1707         msp.rl_index   = rl_index;
1708         msp.rl_update  = true;
1709         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1710         if (err) {
1711                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1712                            rate, err);
1713                 /* remove the rate from the table */
1714                 if (rate)
1715                         mlx5_rl_remove_rate(mdev, rate);
1716                 return err;
1717         }
1718
1719         sq->rate_limit = rate;
1720         return 0;
1721 }
1722
1723 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1724 {
1725         struct mlx5e_priv *priv = netdev_priv(dev);
1726         struct mlx5_core_dev *mdev = priv->mdev;
1727         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1728         int err = 0;
1729
1730         if (!mlx5_rl_is_supported(mdev)) {
1731                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1732                 return -EINVAL;
1733         }
1734
1735         /* rate is given in Mb/sec, HW config is in Kb/sec */
1736         rate = rate << 10;
1737
1738         /* Check whether rate in valid range, 0 is always valid */
1739         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1740                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1741                 return -ERANGE;
1742         }
1743
1744         mutex_lock(&priv->state_lock);
1745         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1746                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1747         if (!err)
1748                 priv->tx_rates[index] = rate;
1749         mutex_unlock(&priv->state_lock);
1750
1751         return err;
1752 }
1753
1754 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1755                               struct mlx5e_params *params,
1756                               struct mlx5e_channel_param *cparam,
1757                               struct mlx5e_channel **cp)
1758 {
1759         struct mlx5e_cq_moder icocq_moder = {0, 0};
1760         struct net_device *netdev = priv->netdev;
1761         struct mlx5e_channel *c;
1762         unsigned int irq;
1763         int err;
1764         int eqn;
1765
1766         c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));
1767         if (!c)
1768                 return -ENOMEM;
1769
1770         c->priv     = priv;
1771         c->mdev     = priv->mdev;
1772         c->tstamp   = &priv->tstamp;
1773         c->ix       = ix;
1774         c->pdev     = &priv->mdev->pdev->dev;
1775         c->netdev   = priv->netdev;
1776         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1777         c->num_tc   = params->num_tc;
1778         c->xdp      = !!params->xdp_prog;
1779
1780         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1781         c->irq_desc = irq_to_desc(irq);
1782
1783         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1784
1785         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1786         if (err)
1787                 goto err_napi_del;
1788
1789         err = mlx5e_open_tx_cqs(c, params, cparam);
1790         if (err)
1791                 goto err_close_icosq_cq;
1792
1793         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1794         if (err)
1795                 goto err_close_tx_cqs;
1796
1797         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1798         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1799                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1800         if (err)
1801                 goto err_close_rx_cq;
1802
1803         napi_enable(&c->napi);
1804
1805         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1806         if (err)
1807                 goto err_disable_napi;
1808
1809         err = mlx5e_open_sqs(c, params, cparam);
1810         if (err)
1811                 goto err_close_icosq;
1812
1813         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1814         if (err)
1815                 goto err_close_sqs;
1816
1817         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1818         if (err)
1819                 goto err_close_xdp_sq;
1820
1821         *cp = c;
1822
1823         return 0;
1824 err_close_xdp_sq:
1825         if (c->xdp)
1826                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1827
1828 err_close_sqs:
1829         mlx5e_close_sqs(c);
1830
1831 err_close_icosq:
1832         mlx5e_close_icosq(&c->icosq);
1833
1834 err_disable_napi:
1835         napi_disable(&c->napi);
1836         if (c->xdp)
1837                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1838
1839 err_close_rx_cq:
1840         mlx5e_close_cq(&c->rq.cq);
1841
1842 err_close_tx_cqs:
1843         mlx5e_close_tx_cqs(c);
1844
1845 err_close_icosq_cq:
1846         mlx5e_close_cq(&c->icosq.cq);
1847
1848 err_napi_del:
1849         netif_napi_del(&c->napi);
1850         kfree(c);
1851
1852         return err;
1853 }
1854
1855 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1856 {
1857         int tc;
1858
1859         for (tc = 0; tc < c->num_tc; tc++)
1860                 mlx5e_activate_txqsq(&c->sq[tc]);
1861         mlx5e_activate_rq(&c->rq);
1862         netif_set_xps_queue(c->netdev,
1863                 mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);
1864 }
1865
1866 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1867 {
1868         int tc;
1869
1870         mlx5e_deactivate_rq(&c->rq);
1871         for (tc = 0; tc < c->num_tc; tc++)
1872                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1873 }
1874
1875 static void mlx5e_close_channel(struct mlx5e_channel *c)
1876 {
1877         mlx5e_close_rq(&c->rq);
1878         if (c->xdp)
1879                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1880         mlx5e_close_sqs(c);
1881         mlx5e_close_icosq(&c->icosq);
1882         napi_disable(&c->napi);
1883         if (c->xdp)
1884                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1885         mlx5e_close_cq(&c->rq.cq);
1886         mlx5e_close_tx_cqs(c);
1887         mlx5e_close_cq(&c->icosq.cq);
1888         netif_napi_del(&c->napi);
1889
1890         kfree(c);
1891 }
1892
1893 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1894                                  struct mlx5e_params *params,
1895                                  struct mlx5e_rq_param *param)
1896 {
1897         void *rqc = param->rqc;
1898         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1899
1900         switch (params->rq_wq_type) {
1901         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1902                 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1903                 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1904                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1905                 break;
1906         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1907                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1908         }
1909
1910         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1911         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1912         MLX5_SET(wq, wq, log_wq_sz,        params->log_rq_size);
1913         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1914         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1915         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1916         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1917
1918         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1919         param->wq.linear = 1;
1920 }
1921
1922 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1923 {
1924         void *rqc = param->rqc;
1925         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1926
1927         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1928         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1929 }
1930
1931 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1932                                         struct mlx5e_sq_param *param)
1933 {
1934         void *sqc = param->sqc;
1935         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1936
1937         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1938         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1939
1940         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1941 }
1942
1943 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1944                                  struct mlx5e_params *params,
1945                                  struct mlx5e_sq_param *param)
1946 {
1947         void *sqc = param->sqc;
1948         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1949
1950         mlx5e_build_sq_param_common(priv, param);
1951         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1952         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1953 }
1954
1955 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1956                                         struct mlx5e_cq_param *param)
1957 {
1958         void *cqc = param->cqc;
1959
1960         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1961 }
1962
1963 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1964                                     struct mlx5e_params *params,
1965                                     struct mlx5e_cq_param *param)
1966 {
1967         void *cqc = param->cqc;
1968         u8 log_cq_size;
1969
1970         switch (params->rq_wq_type) {
1971         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1972                 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1973                 break;
1974         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1975                 log_cq_size = params->log_rq_size;
1976         }
1977
1978         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1979         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1980                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1981                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1982         }
1983
1984         mlx5e_build_common_cq_param(priv, param);
1985         param->cq_period_mode = params->rx_cq_period_mode;
1986 }
1987
1988 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1989                                     struct mlx5e_params *params,
1990                                     struct mlx5e_cq_param *param)
1991 {
1992         void *cqc = param->cqc;
1993
1994         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1995
1996         mlx5e_build_common_cq_param(priv, param);
1997
1998         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1999 }
2000
2001 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2002                                      u8 log_wq_size,
2003                                      struct mlx5e_cq_param *param)
2004 {
2005         void *cqc = param->cqc;
2006
2007         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2008
2009         mlx5e_build_common_cq_param(priv, param);
2010
2011         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2012 }
2013
2014 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2015                                     u8 log_wq_size,
2016                                     struct mlx5e_sq_param *param)
2017 {
2018         void *sqc = param->sqc;
2019         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2020
2021         mlx5e_build_sq_param_common(priv, param);
2022
2023         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2024         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2025 }
2026
2027 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2028                                     struct mlx5e_params *params,
2029                                     struct mlx5e_sq_param *param)
2030 {
2031         void *sqc = param->sqc;
2032         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2033
2034         mlx5e_build_sq_param_common(priv, param);
2035         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2036 }
2037
2038 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2039                                       struct mlx5e_params *params,
2040                                       struct mlx5e_channel_param *cparam)
2041 {
2042         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2043
2044         mlx5e_build_rq_param(priv, params, &cparam->rq);
2045         mlx5e_build_sq_param(priv, params, &cparam->sq);
2046         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2047         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2048         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2049         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2050         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2051 }
2052
2053 int mlx5e_open_channels(struct mlx5e_priv *priv,
2054                         struct mlx5e_channels *chs)
2055 {
2056         struct mlx5e_channel_param *cparam;
2057         int err = -ENOMEM;
2058         int i;
2059
2060         chs->num = chs->params.num_channels;
2061
2062         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2063         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2064         if (!chs->c || !cparam)
2065                 goto err_free;
2066
2067         mlx5e_build_channel_param(priv, &chs->params, cparam);
2068         for (i = 0; i < chs->num; i++) {
2069                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2070                 if (err)
2071                         goto err_close_channels;
2072         }
2073
2074         kfree(cparam);
2075         return 0;
2076
2077 err_close_channels:
2078         for (i--; i >= 0; i--)
2079                 mlx5e_close_channel(chs->c[i]);
2080
2081 err_free:
2082         kfree(chs->c);
2083         kfree(cparam);
2084         chs->num = 0;
2085         return err;
2086 }
2087
2088 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2089 {
2090         int i;
2091
2092         for (i = 0; i < chs->num; i++)
2093                 mlx5e_activate_channel(chs->c[i]);
2094 }
2095
2096 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2097 {
2098         int err = 0;
2099         int i;
2100
2101         for (i = 0; i < chs->num; i++) {
2102                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2103                 if (err)
2104                         break;
2105         }
2106
2107         return err;
2108 }
2109
2110 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2111 {
2112         int i;
2113
2114         for (i = 0; i < chs->num; i++)
2115                 mlx5e_deactivate_channel(chs->c[i]);
2116 }
2117
2118 void mlx5e_close_channels(struct mlx5e_channels *chs)
2119 {
2120         int i;
2121
2122         for (i = 0; i < chs->num; i++)
2123                 mlx5e_close_channel(chs->c[i]);
2124
2125         kfree(chs->c);
2126         chs->num = 0;
2127 }
2128
2129 static int
2130 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2131 {
2132         struct mlx5_core_dev *mdev = priv->mdev;
2133         void *rqtc;
2134         int inlen;
2135         int err;
2136         u32 *in;
2137         int i;
2138
2139         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2140         in = kvzalloc(inlen, GFP_KERNEL);
2141         if (!in)
2142                 return -ENOMEM;
2143
2144         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2145
2146         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2147         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2148
2149         for (i = 0; i < sz; i++)
2150                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2151
2152         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2153         if (!err)
2154                 rqt->enabled = true;
2155
2156         kvfree(in);
2157         return err;
2158 }
2159
2160 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2161 {
2162         rqt->enabled = false;
2163         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2164 }
2165
2166 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2167 {
2168         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2169         int err;
2170
2171         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2172         if (err)
2173                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2174         return err;
2175 }
2176
2177 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2178 {
2179         struct mlx5e_rqt *rqt;
2180         int err;
2181         int ix;
2182
2183         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2184                 rqt = &priv->direct_tir[ix].rqt;
2185                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2186                 if (err)
2187                         goto err_destroy_rqts;
2188         }
2189
2190         return 0;
2191
2192 err_destroy_rqts:
2193         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2194         for (ix--; ix >= 0; ix--)
2195                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2196
2197         return err;
2198 }
2199
2200 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2201 {
2202         int i;
2203
2204         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2205                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2206 }
2207
2208 static int mlx5e_rx_hash_fn(int hfunc)
2209 {
2210         return (hfunc == ETH_RSS_HASH_TOP) ?
2211                MLX5_RX_HASH_FN_TOEPLITZ :
2212                MLX5_RX_HASH_FN_INVERTED_XOR8;
2213 }
2214
2215 static int mlx5e_bits_invert(unsigned long a, int size)
2216 {
2217         int inv = 0;
2218         int i;
2219
2220         for (i = 0; i < size; i++)
2221                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2222
2223         return inv;
2224 }
2225
2226 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2227                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2228 {
2229         int i;
2230
2231         for (i = 0; i < sz; i++) {
2232                 u32 rqn;
2233
2234                 if (rrp.is_rss) {
2235                         int ix = i;
2236
2237                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2238                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2239
2240                         ix = priv->channels.params.indirection_rqt[ix];
2241                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2242                 } else {
2243                         rqn = rrp.rqn;
2244                 }
2245                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2246         }
2247 }
2248
2249 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2250                        struct mlx5e_redirect_rqt_param rrp)
2251 {
2252         struct mlx5_core_dev *mdev = priv->mdev;
2253         void *rqtc;
2254         int inlen;
2255         u32 *in;
2256         int err;
2257
2258         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2259         in = kvzalloc(inlen, GFP_KERNEL);
2260         if (!in)
2261                 return -ENOMEM;
2262
2263         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2264
2265         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2266         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2267         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2268         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2269
2270         kvfree(in);
2271         return err;
2272 }
2273
2274 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2275                                 struct mlx5e_redirect_rqt_param rrp)
2276 {
2277         if (!rrp.is_rss)
2278                 return rrp.rqn;
2279
2280         if (ix >= rrp.rss.channels->num)
2281                 return priv->drop_rq.rqn;
2282
2283         return rrp.rss.channels->c[ix]->rq.rqn;
2284 }
2285
2286 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2287                                 struct mlx5e_redirect_rqt_param rrp)
2288 {
2289         u32 rqtn;
2290         int ix;
2291
2292         if (priv->indir_rqt.enabled) {
2293                 /* RSS RQ table */
2294                 rqtn = priv->indir_rqt.rqtn;
2295                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2296         }
2297
2298         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2299                 struct mlx5e_redirect_rqt_param direct_rrp = {
2300                         .is_rss = false,
2301                         {
2302                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2303                         },
2304                 };
2305
2306                 /* Direct RQ Tables */
2307                 if (!priv->direct_tir[ix].rqt.enabled)
2308                         continue;
2309
2310                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2311                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2312         }
2313 }
2314
2315 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2316                                             struct mlx5e_channels *chs)
2317 {
2318         struct mlx5e_redirect_rqt_param rrp = {
2319                 .is_rss        = true,
2320                 {
2321                         .rss = {
2322                                 .channels  = chs,
2323                                 .hfunc     = chs->params.rss_hfunc,
2324                         }
2325                 },
2326         };
2327
2328         mlx5e_redirect_rqts(priv, rrp);
2329 }
2330
2331 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2332 {
2333         struct mlx5e_redirect_rqt_param drop_rrp = {
2334                 .is_rss = false,
2335                 {
2336                         .rqn = priv->drop_rq.rqn,
2337                 },
2338         };
2339
2340         mlx5e_redirect_rqts(priv, drop_rrp);
2341 }
2342
2343 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2344 {
2345         if (!params->lro_en)
2346                 return;
2347
2348 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2349
2350         MLX5_SET(tirc, tirc, lro_enable_mask,
2351                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2352                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2353         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2354                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2355         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2356 }
2357
2358 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2359                                     enum mlx5e_traffic_types tt,
2360                                     void *tirc, bool inner)
2361 {
2362         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2363                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2364
2365 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2366                                  MLX5_HASH_FIELD_SEL_DST_IP)
2367
2368 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2369                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2370                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2371                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2372
2373 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2374                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2375                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2376
2377         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2378         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2379                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2380                                              rx_hash_toeplitz_key);
2381                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2382                                                rx_hash_toeplitz_key);
2383
2384                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2385                 memcpy(rss_key, params->toeplitz_hash_key, len);
2386         }
2387
2388         switch (tt) {
2389         case MLX5E_TT_IPV4_TCP:
2390                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2391                          MLX5_L3_PROT_TYPE_IPV4);
2392                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2393                          MLX5_L4_PROT_TYPE_TCP);
2394                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2395                          MLX5_HASH_IP_L4PORTS);
2396                 break;
2397
2398         case MLX5E_TT_IPV6_TCP:
2399                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400                          MLX5_L3_PROT_TYPE_IPV6);
2401                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2402                          MLX5_L4_PROT_TYPE_TCP);
2403                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2404                          MLX5_HASH_IP_L4PORTS);
2405                 break;
2406
2407         case MLX5E_TT_IPV4_UDP:
2408                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2409                          MLX5_L3_PROT_TYPE_IPV4);
2410                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2411                          MLX5_L4_PROT_TYPE_UDP);
2412                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2413                          MLX5_HASH_IP_L4PORTS);
2414                 break;
2415
2416         case MLX5E_TT_IPV6_UDP:
2417                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2418                          MLX5_L3_PROT_TYPE_IPV6);
2419                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2420                          MLX5_L4_PROT_TYPE_UDP);
2421                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2422                          MLX5_HASH_IP_L4PORTS);
2423                 break;
2424
2425         case MLX5E_TT_IPV4_IPSEC_AH:
2426                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2427                          MLX5_L3_PROT_TYPE_IPV4);
2428                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429                          MLX5_HASH_IP_IPSEC_SPI);
2430                 break;
2431
2432         case MLX5E_TT_IPV6_IPSEC_AH:
2433                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434                          MLX5_L3_PROT_TYPE_IPV6);
2435                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436                          MLX5_HASH_IP_IPSEC_SPI);
2437                 break;
2438
2439         case MLX5E_TT_IPV4_IPSEC_ESP:
2440                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441                          MLX5_L3_PROT_TYPE_IPV4);
2442                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443                          MLX5_HASH_IP_IPSEC_SPI);
2444                 break;
2445
2446         case MLX5E_TT_IPV6_IPSEC_ESP:
2447                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448                          MLX5_L3_PROT_TYPE_IPV6);
2449                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450                          MLX5_HASH_IP_IPSEC_SPI);
2451                 break;
2452
2453         case MLX5E_TT_IPV4:
2454                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2455                          MLX5_L3_PROT_TYPE_IPV4);
2456                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457                          MLX5_HASH_IP);
2458                 break;
2459
2460         case MLX5E_TT_IPV6:
2461                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2462                          MLX5_L3_PROT_TYPE_IPV6);
2463                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2464                          MLX5_HASH_IP);
2465                 break;
2466         default:
2467                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2468         }
2469 }
2470
2471 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2472 {
2473         struct mlx5_core_dev *mdev = priv->mdev;
2474
2475         void *in;
2476         void *tirc;
2477         int inlen;
2478         int err;
2479         int tt;
2480         int ix;
2481
2482         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2483         in = kvzalloc(inlen, GFP_KERNEL);
2484         if (!in)
2485                 return -ENOMEM;
2486
2487         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2488         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2489
2490         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2491
2492         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2493                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2494                                            inlen);
2495                 if (err)
2496                         goto free_in;
2497         }
2498
2499         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2500                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2501                                            in, inlen);
2502                 if (err)
2503                         goto free_in;
2504         }
2505
2506 free_in:
2507         kvfree(in);
2508
2509         return err;
2510 }
2511
2512 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2513                                             enum mlx5e_traffic_types tt,
2514                                             u32 *tirc)
2515 {
2516         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2517
2518         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2519
2520         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2521         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2522         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2523
2524         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2525 }
2526
2527 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2528 {
2529         struct mlx5_core_dev *mdev = priv->mdev;
2530         u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2531         int err;
2532
2533         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2534         if (err)
2535                 return err;
2536
2537         /* Update vport context MTU */
2538         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2539         return 0;
2540 }
2541
2542 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2543 {
2544         struct mlx5_core_dev *mdev = priv->mdev;
2545         u16 hw_mtu = 0;
2546         int err;
2547
2548         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2549         if (err || !hw_mtu) /* fallback to port oper mtu */
2550                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2551
2552         *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2553 }
2554
2555 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2556 {
2557         struct net_device *netdev = priv->netdev;
2558         u16 mtu;
2559         int err;
2560
2561         err = mlx5e_set_mtu(priv, netdev->mtu);
2562         if (err)
2563                 return err;
2564
2565         mlx5e_query_mtu(priv, &mtu);
2566         if (mtu != netdev->mtu)
2567                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2568                             __func__, mtu, netdev->mtu);
2569
2570         netdev->mtu = mtu;
2571         return 0;
2572 }
2573
2574 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2575 {
2576         struct mlx5e_priv *priv = netdev_priv(netdev);
2577         int nch = priv->channels.params.num_channels;
2578         int ntc = priv->channels.params.num_tc;
2579         int tc;
2580
2581         netdev_reset_tc(netdev);
2582
2583         if (ntc == 1)
2584                 return;
2585
2586         netdev_set_num_tc(netdev, ntc);
2587
2588         /* Map netdev TCs to offset 0
2589          * We have our own UP to TXQ mapping for QoS
2590          */
2591         for (tc = 0; tc < ntc; tc++)
2592                 netdev_set_tc_queue(netdev, tc, nch, 0);
2593 }
2594
2595 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2596 {
2597         struct mlx5e_channel *c;
2598         struct mlx5e_txqsq *sq;
2599         int i, tc;
2600
2601         for (i = 0; i < priv->channels.num; i++)
2602                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2603                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2604
2605         for (i = 0; i < priv->channels.num; i++) {
2606                 c = priv->channels.c[i];
2607                 for (tc = 0; tc < c->num_tc; tc++) {
2608                         sq = &c->sq[tc];
2609                         priv->txq2sq[sq->txq_ix] = sq;
2610                 }
2611         }
2612 }
2613
2614 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2615 {
2616         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2617         struct net_device *netdev = priv->netdev;
2618
2619         mlx5e_netdev_set_tcs(netdev);
2620         netif_set_real_num_tx_queues(netdev, num_txqs);
2621         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2622
2623         mlx5e_build_channels_tx_maps(priv);
2624         mlx5e_activate_channels(&priv->channels);
2625         netif_tx_start_all_queues(priv->netdev);
2626
2627         if (MLX5_VPORT_MANAGER(priv->mdev))
2628                 mlx5e_add_sqs_fwd_rules(priv);
2629
2630         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2631         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2632 }
2633
2634 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2635 {
2636         mlx5e_redirect_rqts_to_drop(priv);
2637
2638         if (MLX5_VPORT_MANAGER(priv->mdev))
2639                 mlx5e_remove_sqs_fwd_rules(priv);
2640
2641         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2642          * polling for inactive tx queues.
2643          */
2644         netif_tx_stop_all_queues(priv->netdev);
2645         netif_tx_disable(priv->netdev);
2646         mlx5e_deactivate_channels(&priv->channels);
2647 }
2648
2649 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2650                                 struct mlx5e_channels *new_chs,
2651                                 mlx5e_fp_hw_modify hw_modify)
2652 {
2653         struct net_device *netdev = priv->netdev;
2654         int new_num_txqs;
2655         int carrier_ok;
2656         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2657
2658         carrier_ok = netif_carrier_ok(netdev);
2659         netif_carrier_off(netdev);
2660
2661         if (new_num_txqs < netdev->real_num_tx_queues)
2662                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2663
2664         mlx5e_deactivate_priv_channels(priv);
2665         mlx5e_close_channels(&priv->channels);
2666
2667         priv->channels = *new_chs;
2668
2669         /* New channels are ready to roll, modify HW settings if needed */
2670         if (hw_modify)
2671                 hw_modify(priv);
2672
2673         mlx5e_refresh_tirs(priv, false);
2674         mlx5e_activate_priv_channels(priv);
2675
2676         /* return carrier back if needed */
2677         if (carrier_ok)
2678                 netif_carrier_on(netdev);
2679 }
2680
2681 int mlx5e_open_locked(struct net_device *netdev)
2682 {
2683         struct mlx5e_priv *priv = netdev_priv(netdev);
2684         int err;
2685
2686         set_bit(MLX5E_STATE_OPENED, &priv->state);
2687
2688         err = mlx5e_open_channels(priv, &priv->channels);
2689         if (err)
2690                 goto err_clear_state_opened_flag;
2691
2692         mlx5e_refresh_tirs(priv, false);
2693         mlx5e_activate_priv_channels(priv);
2694         if (priv->profile->update_carrier)
2695                 priv->profile->update_carrier(priv);
2696         mlx5e_timestamp_init(priv);
2697
2698         if (priv->profile->update_stats)
2699                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2700
2701         return 0;
2702
2703 err_clear_state_opened_flag:
2704         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2705         return err;
2706 }
2707
2708 int mlx5e_open(struct net_device *netdev)
2709 {
2710         struct mlx5e_priv *priv = netdev_priv(netdev);
2711         int err;
2712
2713         mutex_lock(&priv->state_lock);
2714         err = mlx5e_open_locked(netdev);
2715         if (!err)
2716                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2717         mutex_unlock(&priv->state_lock);
2718
2719         return err;
2720 }
2721
2722 int mlx5e_close_locked(struct net_device *netdev)
2723 {
2724         struct mlx5e_priv *priv = netdev_priv(netdev);
2725
2726         /* May already be CLOSED in case a previous configuration operation
2727          * (e.g RX/TX queue size change) that involves close&open failed.
2728          */
2729         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2730                 return 0;
2731
2732         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2733
2734         mlx5e_timestamp_cleanup(priv);
2735         netif_carrier_off(priv->netdev);
2736         mlx5e_deactivate_priv_channels(priv);
2737         mlx5e_close_channels(&priv->channels);
2738
2739         return 0;
2740 }
2741
2742 int mlx5e_close(struct net_device *netdev)
2743 {
2744         struct mlx5e_priv *priv = netdev_priv(netdev);
2745         int err;
2746
2747         if (!netif_device_present(netdev))
2748                 return -ENODEV;
2749
2750         mutex_lock(&priv->state_lock);
2751         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2752         err = mlx5e_close_locked(netdev);
2753         mutex_unlock(&priv->state_lock);
2754
2755         return err;
2756 }
2757
2758 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2759                                struct mlx5e_rq *rq,
2760                                struct mlx5e_rq_param *param)
2761 {
2762         void *rqc = param->rqc;
2763         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2764         int err;
2765
2766         param->wq.db_numa_node = param->wq.buf_numa_node;
2767
2768         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2769                                 &rq->wq_ctrl);
2770         if (err)
2771                 return err;
2772
2773         rq->mdev = mdev;
2774
2775         return 0;
2776 }
2777
2778 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2779                                struct mlx5e_cq *cq,
2780                                struct mlx5e_cq_param *param)
2781 {
2782         return mlx5e_alloc_cq_common(mdev, param, cq);
2783 }
2784
2785 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2786                               struct mlx5e_rq *drop_rq)
2787 {
2788         struct mlx5e_cq_param cq_param = {};
2789         struct mlx5e_rq_param rq_param = {};
2790         struct mlx5e_cq *cq = &drop_rq->cq;
2791         int err;
2792
2793         mlx5e_build_drop_rq_param(&rq_param);
2794
2795         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2796         if (err)
2797                 return err;
2798
2799         err = mlx5e_create_cq(cq, &cq_param);
2800         if (err)
2801                 goto err_free_cq;
2802
2803         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2804         if (err)
2805                 goto err_destroy_cq;
2806
2807         err = mlx5e_create_rq(drop_rq, &rq_param);
2808         if (err)
2809                 goto err_free_rq;
2810
2811         return 0;
2812
2813 err_free_rq:
2814         mlx5e_free_rq(drop_rq);
2815
2816 err_destroy_cq:
2817         mlx5e_destroy_cq(cq);
2818
2819 err_free_cq:
2820         mlx5e_free_cq(cq);
2821
2822         return err;
2823 }
2824
2825 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2826 {
2827         mlx5e_destroy_rq(drop_rq);
2828         mlx5e_free_rq(drop_rq);
2829         mlx5e_destroy_cq(&drop_rq->cq);
2830         mlx5e_free_cq(&drop_rq->cq);
2831 }
2832
2833 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2834                      u32 underlay_qpn, u32 *tisn)
2835 {
2836         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2837         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2838
2839         MLX5_SET(tisc, tisc, prio, tc << 1);
2840         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2841         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2842
2843         if (mlx5_lag_is_lacp_owner(mdev))
2844                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2845
2846         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2847 }
2848
2849 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2850 {
2851         mlx5_core_destroy_tis(mdev, tisn);
2852 }
2853
2854 int mlx5e_create_tises(struct mlx5e_priv *priv)
2855 {
2856         int err;
2857         int tc;
2858
2859         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2860                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2861                 if (err)
2862                         goto err_close_tises;
2863         }
2864
2865         return 0;
2866
2867 err_close_tises:
2868         for (tc--; tc >= 0; tc--)
2869                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2870
2871         return err;
2872 }
2873
2874 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2875 {
2876         int tc;
2877
2878         for (tc = 0; tc < priv->profile->max_tc; tc++)
2879                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2880 }
2881
2882 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2883                                       enum mlx5e_traffic_types tt,
2884                                       u32 *tirc)
2885 {
2886         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2887
2888         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2889
2890         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2891         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2892         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2893 }
2894
2895 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2896 {
2897         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2898
2899         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2900
2901         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2902         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2903         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2904 }
2905
2906 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2907 {
2908         struct mlx5e_tir *tir;
2909         void *tirc;
2910         int inlen;
2911         int i = 0;
2912         int err;
2913         u32 *in;
2914         int tt;
2915
2916         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2917         in = kvzalloc(inlen, GFP_KERNEL);
2918         if (!in)
2919                 return -ENOMEM;
2920
2921         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2922                 memset(in, 0, inlen);
2923                 tir = &priv->indir_tir[tt];
2924                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2925                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2926                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2927                 if (err) {
2928                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2929                         goto err_destroy_inner_tirs;
2930                 }
2931         }
2932
2933         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2934                 goto out;
2935
2936         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2937                 memset(in, 0, inlen);
2938                 tir = &priv->inner_indir_tir[i];
2939                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2940                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2941                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2942                 if (err) {
2943                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2944                         goto err_destroy_inner_tirs;
2945                 }
2946         }
2947
2948 out:
2949         kvfree(in);
2950
2951         return 0;
2952
2953 err_destroy_inner_tirs:
2954         for (i--; i >= 0; i--)
2955                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2956
2957         for (tt--; tt >= 0; tt--)
2958                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2959
2960         kvfree(in);
2961
2962         return err;
2963 }
2964
2965 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2966 {
2967         int nch = priv->profile->max_nch(priv->mdev);
2968         struct mlx5e_tir *tir;
2969         void *tirc;
2970         int inlen;
2971         int err;
2972         u32 *in;
2973         int ix;
2974
2975         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2976         in = kvzalloc(inlen, GFP_KERNEL);
2977         if (!in)
2978                 return -ENOMEM;
2979
2980         for (ix = 0; ix < nch; ix++) {
2981                 memset(in, 0, inlen);
2982                 tir = &priv->direct_tir[ix];
2983                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2984                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2985                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2986                 if (err)
2987                         goto err_destroy_ch_tirs;
2988         }
2989
2990         kvfree(in);
2991
2992         return 0;
2993
2994 err_destroy_ch_tirs:
2995         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2996         for (ix--; ix >= 0; ix--)
2997                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2998
2999         kvfree(in);
3000
3001         return err;
3002 }
3003
3004 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3005 {
3006         int i;
3007
3008         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3009                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3010
3011         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3012                 return;
3013
3014         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3015                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3016 }
3017
3018 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3019 {
3020         int nch = priv->profile->max_nch(priv->mdev);
3021         int i;
3022
3023         for (i = 0; i < nch; i++)
3024                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3025 }
3026
3027 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3028 {
3029         int err = 0;
3030         int i;
3031
3032         for (i = 0; i < chs->num; i++) {
3033                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3034                 if (err)
3035                         return err;
3036         }
3037
3038         return 0;
3039 }
3040
3041 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3042 {
3043         int err = 0;
3044         int i;
3045
3046         for (i = 0; i < chs->num; i++) {
3047                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3048                 if (err)
3049                         return err;
3050         }
3051
3052         return 0;
3053 }
3054
3055 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3056                                  struct tc_mqprio_qopt *mqprio)
3057 {
3058         struct mlx5e_priv *priv = netdev_priv(netdev);
3059         struct mlx5e_channels new_channels = {};
3060         u8 tc = mqprio->num_tc;
3061         int err = 0;
3062
3063         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3064
3065         if (tc && tc != MLX5E_MAX_NUM_TC)
3066                 return -EINVAL;
3067
3068         mutex_lock(&priv->state_lock);
3069
3070         new_channels.params = priv->channels.params;
3071         new_channels.params.num_tc = tc ? tc : 1;
3072
3073         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3074                 priv->channels.params = new_channels.params;
3075                 goto out;
3076         }
3077
3078         err = mlx5e_open_channels(priv, &new_channels);
3079         if (err)
3080                 goto out;
3081
3082         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3083 out:
3084         mutex_unlock(&priv->state_lock);
3085         return err;
3086 }
3087
3088 #ifdef CONFIG_MLX5_ESWITCH
3089 static int mlx5e_setup_tc_cls_flower(struct net_device *dev,
3090                                      struct tc_cls_flower_offload *cls_flower)
3091 {
3092         struct mlx5e_priv *priv = netdev_priv(dev);
3093
3094         if (!is_classid_clsact_ingress(cls_flower->common.classid) ||
3095             cls_flower->common.chain_index)
3096                 return -EOPNOTSUPP;
3097
3098         switch (cls_flower->command) {
3099         case TC_CLSFLOWER_REPLACE:
3100                 return mlx5e_configure_flower(priv, cls_flower);
3101         case TC_CLSFLOWER_DESTROY:
3102                 return mlx5e_delete_flower(priv, cls_flower);
3103         case TC_CLSFLOWER_STATS:
3104                 return mlx5e_stats_flower(priv, cls_flower);
3105         default:
3106                 return -EOPNOTSUPP;
3107         }
3108 }
3109 #endif
3110
3111 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3112                           void *type_data)
3113 {
3114         switch (type) {
3115 #ifdef CONFIG_MLX5_ESWITCH
3116         case TC_SETUP_CLSFLOWER:
3117                 return mlx5e_setup_tc_cls_flower(dev, type_data);
3118 #endif
3119         case TC_SETUP_MQPRIO:
3120                 return mlx5e_setup_tc_mqprio(dev, type_data);
3121         default:
3122                 return -EOPNOTSUPP;
3123         }
3124 }
3125
3126 static void
3127 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3128 {
3129         struct mlx5e_priv *priv = netdev_priv(dev);
3130         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3131         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3132         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3133
3134         if (mlx5e_is_uplink_rep(priv)) {
3135                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3136                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3137                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3138                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3139         } else {
3140                 stats->rx_packets = sstats->rx_packets;
3141                 stats->rx_bytes   = sstats->rx_bytes;
3142                 stats->tx_packets = sstats->tx_packets;
3143                 stats->tx_bytes   = sstats->tx_bytes;
3144                 stats->tx_dropped = sstats->tx_queue_dropped;
3145         }
3146
3147         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3148
3149         stats->rx_length_errors =
3150                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3151                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3152                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3153         stats->rx_crc_errors =
3154                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3155         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3156         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3157         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3158                            stats->rx_frame_errors;
3159         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3160
3161         /* vport multicast also counts packets that are dropped due to steering
3162          * or rx out of buffer
3163          */
3164         stats->multicast =
3165                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3166 }
3167
3168 static void mlx5e_set_rx_mode(struct net_device *dev)
3169 {
3170         struct mlx5e_priv *priv = netdev_priv(dev);
3171
3172         queue_work(priv->wq, &priv->set_rx_mode_work);
3173 }
3174
3175 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3176 {
3177         struct mlx5e_priv *priv = netdev_priv(netdev);
3178         struct sockaddr *saddr = addr;
3179
3180         if (!is_valid_ether_addr(saddr->sa_data))
3181                 return -EADDRNOTAVAIL;
3182
3183         netif_addr_lock_bh(netdev);
3184         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3185         netif_addr_unlock_bh(netdev);
3186
3187         queue_work(priv->wq, &priv->set_rx_mode_work);
3188
3189         return 0;
3190 }
3191
3192 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
3193         do {                                            \
3194                 if (enable)                             \
3195                         netdev->features |= feature;    \
3196                 else                                    \
3197                         netdev->features &= ~feature;   \
3198         } while (0)
3199
3200 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3201
3202 static int set_feature_lro(struct net_device *netdev, bool enable)
3203 {
3204         struct mlx5e_priv *priv = netdev_priv(netdev);
3205         struct mlx5e_channels new_channels = {};
3206         int err = 0;
3207         bool reset;
3208
3209         mutex_lock(&priv->state_lock);
3210
3211         reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3212         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3213
3214         new_channels.params = priv->channels.params;
3215         new_channels.params.lro_en = enable;
3216
3217         if (!reset) {
3218                 priv->channels.params = new_channels.params;
3219                 err = mlx5e_modify_tirs_lro(priv);
3220                 goto out;
3221         }
3222
3223         err = mlx5e_open_channels(priv, &new_channels);
3224         if (err)
3225                 goto out;
3226
3227         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3228 out:
3229         mutex_unlock(&priv->state_lock);
3230         return err;
3231 }
3232
3233 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3234 {
3235         struct mlx5e_priv *priv = netdev_priv(netdev);
3236
3237         if (enable)
3238                 mlx5e_enable_vlan_filter(priv);
3239         else
3240                 mlx5e_disable_vlan_filter(priv);
3241
3242         return 0;
3243 }
3244
3245 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3246 {
3247         struct mlx5e_priv *priv = netdev_priv(netdev);
3248
3249         if (!enable && mlx5e_tc_num_filters(priv)) {
3250                 netdev_err(netdev,
3251                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3252                 return -EINVAL;
3253         }
3254
3255         return 0;
3256 }
3257
3258 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3259 {
3260         struct mlx5e_priv *priv = netdev_priv(netdev);
3261         struct mlx5_core_dev *mdev = priv->mdev;
3262
3263         return mlx5_set_port_fcs(mdev, !enable);
3264 }
3265
3266 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3267 {
3268         struct mlx5e_priv *priv = netdev_priv(netdev);
3269         int err;
3270
3271         mutex_lock(&priv->state_lock);
3272
3273         priv->channels.params.scatter_fcs_en = enable;
3274         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3275         if (err)
3276                 priv->channels.params.scatter_fcs_en = !enable;
3277
3278         mutex_unlock(&priv->state_lock);
3279
3280         return err;
3281 }
3282
3283 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3284 {
3285         struct mlx5e_priv *priv = netdev_priv(netdev);
3286         int err = 0;
3287
3288         mutex_lock(&priv->state_lock);
3289
3290         priv->channels.params.vlan_strip_disable = !enable;
3291         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3292                 goto unlock;
3293
3294         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3295         if (err)
3296                 priv->channels.params.vlan_strip_disable = enable;
3297
3298 unlock:
3299         mutex_unlock(&priv->state_lock);
3300
3301         return err;
3302 }
3303
3304 #ifdef CONFIG_RFS_ACCEL
3305 static int set_feature_arfs(struct net_device *netdev, bool enable)
3306 {
3307         struct mlx5e_priv *priv = netdev_priv(netdev);
3308         int err;
3309
3310         if (enable)
3311                 err = mlx5e_arfs_enable(priv);
3312         else
3313                 err = mlx5e_arfs_disable(priv);
3314
3315         return err;
3316 }
3317 #endif
3318
3319 static int mlx5e_handle_feature(struct net_device *netdev,
3320                                 netdev_features_t wanted_features,
3321                                 netdev_features_t feature,
3322                                 mlx5e_feature_handler feature_handler)
3323 {
3324         netdev_features_t changes = wanted_features ^ netdev->features;
3325         bool enable = !!(wanted_features & feature);
3326         int err;
3327
3328         if (!(changes & feature))
3329                 return 0;
3330
3331         err = feature_handler(netdev, enable);
3332         if (err) {
3333                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3334                            enable ? "Enable" : "Disable", &feature, err);
3335                 return err;
3336         }
3337
3338         MLX5E_SET_FEATURE(netdev, feature, enable);
3339         return 0;
3340 }
3341
3342 static int mlx5e_set_features(struct net_device *netdev,
3343                               netdev_features_t features)
3344 {
3345         int err;
3346
3347         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3348                                     set_feature_lro);
3349         err |= mlx5e_handle_feature(netdev, features,
3350                                     NETIF_F_HW_VLAN_CTAG_FILTER,
3351                                     set_feature_vlan_filter);
3352         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3353                                     set_feature_tc_num_filters);
3354         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3355                                     set_feature_rx_all);
3356         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3357                                     set_feature_rx_fcs);
3358         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3359                                     set_feature_rx_vlan);
3360 #ifdef CONFIG_RFS_ACCEL
3361         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3362                                     set_feature_arfs);
3363 #endif
3364
3365         return err ? -EINVAL : 0;
3366 }
3367
3368 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3369 {
3370         struct mlx5e_priv *priv = netdev_priv(netdev);
3371         struct mlx5e_channels new_channels = {};
3372         int curr_mtu;
3373         int err = 0;
3374         bool reset;
3375
3376         mutex_lock(&priv->state_lock);
3377
3378         reset = !priv->channels.params.lro_en &&
3379                 (priv->channels.params.rq_wq_type !=
3380                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3381
3382         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3383
3384         curr_mtu    = netdev->mtu;
3385         netdev->mtu = new_mtu;
3386
3387         if (!reset) {
3388                 mlx5e_set_dev_port_mtu(priv);
3389                 goto out;
3390         }
3391
3392         new_channels.params = priv->channels.params;
3393         err = mlx5e_open_channels(priv, &new_channels);
3394         if (err) {
3395                 netdev->mtu = curr_mtu;
3396                 goto out;
3397         }
3398
3399         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3400
3401 out:
3402         mutex_unlock(&priv->state_lock);
3403         return err;
3404 }
3405
3406 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3407 {
3408         struct mlx5e_priv *priv = netdev_priv(dev);
3409
3410         switch (cmd) {
3411         case SIOCSHWTSTAMP:
3412                 return mlx5e_hwstamp_set(priv, ifr);
3413         case SIOCGHWTSTAMP:
3414                 return mlx5e_hwstamp_get(priv, ifr);
3415         default:
3416                 return -EOPNOTSUPP;
3417         }
3418 }
3419
3420 #ifdef CONFIG_MLX5_ESWITCH
3421 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3422 {
3423         struct mlx5e_priv *priv = netdev_priv(dev);
3424         struct mlx5_core_dev *mdev = priv->mdev;
3425
3426         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3427 }
3428
3429 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3430                              __be16 vlan_proto)
3431 {
3432         struct mlx5e_priv *priv = netdev_priv(dev);
3433         struct mlx5_core_dev *mdev = priv->mdev;
3434
3435         if (vlan_proto != htons(ETH_P_8021Q))
3436                 return -EPROTONOSUPPORT;
3437
3438         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3439                                            vlan, qos);
3440 }
3441
3442 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3443 {
3444         struct mlx5e_priv *priv = netdev_priv(dev);
3445         struct mlx5_core_dev *mdev = priv->mdev;
3446
3447         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3448 }
3449
3450 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3451 {
3452         struct mlx5e_priv *priv = netdev_priv(dev);
3453         struct mlx5_core_dev *mdev = priv->mdev;
3454
3455         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3456 }
3457
3458 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3459                              int max_tx_rate)
3460 {
3461         struct mlx5e_priv *priv = netdev_priv(dev);
3462         struct mlx5_core_dev *mdev = priv->mdev;
3463
3464         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3465                                            max_tx_rate, min_tx_rate);
3466 }
3467
3468 static int mlx5_vport_link2ifla(u8 esw_link)
3469 {
3470         switch (esw_link) {
3471         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3472                 return IFLA_VF_LINK_STATE_DISABLE;
3473         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3474                 return IFLA_VF_LINK_STATE_ENABLE;
3475         }
3476         return IFLA_VF_LINK_STATE_AUTO;
3477 }
3478
3479 static int mlx5_ifla_link2vport(u8 ifla_link)
3480 {
3481         switch (ifla_link) {
3482         case IFLA_VF_LINK_STATE_DISABLE:
3483                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3484         case IFLA_VF_LINK_STATE_ENABLE:
3485                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3486         }
3487         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3488 }
3489
3490 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3491                                    int link_state)
3492 {
3493         struct mlx5e_priv *priv = netdev_priv(dev);
3494         struct mlx5_core_dev *mdev = priv->mdev;
3495
3496         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3497                                             mlx5_ifla_link2vport(link_state));
3498 }
3499
3500 static int mlx5e_get_vf_config(struct net_device *dev,
3501                                int vf, struct ifla_vf_info *ivi)
3502 {
3503         struct mlx5e_priv *priv = netdev_priv(dev);
3504         struct mlx5_core_dev *mdev = priv->mdev;
3505         int err;
3506
3507         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3508         if (err)
3509                 return err;
3510         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3511         return 0;
3512 }
3513
3514 static int mlx5e_get_vf_stats(struct net_device *dev,
3515                               int vf, struct ifla_vf_stats *vf_stats)
3516 {
3517         struct mlx5e_priv *priv = netdev_priv(dev);
3518         struct mlx5_core_dev *mdev = priv->mdev;
3519
3520         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3521                                             vf_stats);
3522 }
3523 #endif
3524
3525 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3526                                  struct udp_tunnel_info *ti)
3527 {
3528         struct mlx5e_priv *priv = netdev_priv(netdev);
3529
3530         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3531                 return;
3532
3533         if (!mlx5e_vxlan_allowed(priv->mdev))
3534                 return;
3535
3536         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3537 }
3538
3539 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3540                                  struct udp_tunnel_info *ti)
3541 {
3542         struct mlx5e_priv *priv = netdev_priv(netdev);
3543
3544         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3545                 return;
3546
3547         if (!mlx5e_vxlan_allowed(priv->mdev))
3548                 return;
3549
3550         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3551 }
3552
3553 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3554                                                      struct sk_buff *skb,
3555                                                      netdev_features_t features)
3556 {
3557         struct udphdr *udph;
3558         u8 proto;
3559         u16 port;
3560
3561         switch (vlan_get_protocol(skb)) {
3562         case htons(ETH_P_IP):
3563                 proto = ip_hdr(skb)->protocol;
3564                 break;
3565         case htons(ETH_P_IPV6):
3566                 proto = ipv6_hdr(skb)->nexthdr;
3567                 break;
3568         default:
3569                 goto out;
3570         }
3571
3572         switch (proto) {
3573         case IPPROTO_GRE:
3574                 return features;
3575         case IPPROTO_UDP:
3576                 udph = udp_hdr(skb);
3577                 port = be16_to_cpu(udph->dest);
3578
3579                 /* Verify if UDP port is being offloaded by HW */
3580                 if (mlx5e_vxlan_lookup_port(priv, port))
3581                         return features;
3582         }
3583
3584 out:
3585         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3586         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3587 }
3588
3589 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3590                                               struct net_device *netdev,
3591                                               netdev_features_t features)
3592 {
3593         struct mlx5e_priv *priv = netdev_priv(netdev);
3594
3595         features = vlan_features_check(skb, features);
3596         features = vxlan_features_check(skb, features);
3597
3598 #ifdef CONFIG_MLX5_EN_IPSEC
3599         if (mlx5e_ipsec_feature_check(skb, netdev, features))
3600                 return features;
3601 #endif
3602
3603         /* Validate if the tunneled packet is being offloaded by HW */
3604         if (skb->encapsulation &&
3605             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3606                 return mlx5e_tunnel_features_check(priv, skb, features);
3607
3608         return features;
3609 }
3610
3611 static void mlx5e_tx_timeout(struct net_device *dev)
3612 {
3613         struct mlx5e_priv *priv = netdev_priv(dev);
3614         bool sched_work = false;
3615         int i;
3616
3617         netdev_err(dev, "TX timeout detected\n");
3618
3619         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3620                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3621
3622                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3623                         continue;
3624                 sched_work = true;
3625                 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3626                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3627                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3628         }
3629
3630         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3631                 schedule_work(&priv->tx_timeout_work);
3632 }
3633
3634 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3635 {
3636         struct mlx5e_priv *priv = netdev_priv(netdev);
3637         struct bpf_prog *old_prog;
3638         int err = 0;
3639         bool reset, was_opened;
3640         int i;
3641
3642         mutex_lock(&priv->state_lock);
3643
3644         if ((netdev->features & NETIF_F_LRO) && prog) {
3645                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3646                 err = -EINVAL;
3647                 goto unlock;
3648         }
3649
3650         if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3651                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3652                 err = -EINVAL;
3653                 goto unlock;
3654         }
3655
3656         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3657         /* no need for full reset when exchanging programs */
3658         reset = (!priv->channels.params.xdp_prog || !prog);
3659
3660         if (was_opened && reset)
3661                 mlx5e_close_locked(netdev);
3662         if (was_opened && !reset) {
3663                 /* num_channels is invariant here, so we can take the
3664                  * batched reference right upfront.
3665                  */
3666                 prog = bpf_prog_add(prog, priv->channels.num);
3667                 if (IS_ERR(prog)) {
3668                         err = PTR_ERR(prog);
3669                         goto unlock;
3670                 }
3671         }
3672
3673         /* exchange programs, extra prog reference we got from caller
3674          * as long as we don't fail from this point onwards.
3675          */
3676         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3677         if (old_prog)
3678                 bpf_prog_put(old_prog);
3679
3680         if (reset) /* change RQ type according to priv->xdp_prog */
3681                 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3682
3683         if (was_opened && reset)
3684                 mlx5e_open_locked(netdev);
3685
3686         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3687                 goto unlock;
3688
3689         /* exchanging programs w/o reset, we update ref counts on behalf
3690          * of the channels RQs here.
3691          */
3692         for (i = 0; i < priv->channels.num; i++) {
3693                 struct mlx5e_channel *c = priv->channels.c[i];
3694
3695                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3696                 napi_synchronize(&c->napi);
3697                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3698
3699                 old_prog = xchg(&c->rq.xdp_prog, prog);
3700
3701                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3702                 /* napi_schedule in case we have missed anything */
3703                 napi_schedule(&c->napi);
3704
3705                 if (old_prog)
3706                         bpf_prog_put(old_prog);
3707         }
3708
3709 unlock:
3710         mutex_unlock(&priv->state_lock);
3711         return err;
3712 }
3713
3714 static u32 mlx5e_xdp_query(struct net_device *dev)
3715 {
3716         struct mlx5e_priv *priv = netdev_priv(dev);
3717         const struct bpf_prog *xdp_prog;
3718         u32 prog_id = 0;
3719
3720         mutex_lock(&priv->state_lock);
3721         xdp_prog = priv->channels.params.xdp_prog;
3722         if (xdp_prog)
3723                 prog_id = xdp_prog->aux->id;
3724         mutex_unlock(&priv->state_lock);
3725
3726         return prog_id;
3727 }
3728
3729 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3730 {
3731         switch (xdp->command) {
3732         case XDP_SETUP_PROG:
3733                 return mlx5e_xdp_set(dev, xdp->prog);
3734         case XDP_QUERY_PROG:
3735                 xdp->prog_id = mlx5e_xdp_query(dev);
3736                 xdp->prog_attached = !!xdp->prog_id;
3737                 return 0;
3738         default:
3739                 return -EINVAL;
3740         }
3741 }
3742
3743 #ifdef CONFIG_NET_POLL_CONTROLLER
3744 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3745  * reenabling interrupts.
3746  */
3747 static void mlx5e_netpoll(struct net_device *dev)
3748 {
3749         struct mlx5e_priv *priv = netdev_priv(dev);
3750         struct mlx5e_channels *chs = &priv->channels;
3751
3752         int i;
3753
3754         for (i = 0; i < chs->num; i++)
3755                 napi_schedule(&chs->c[i]->napi);
3756 }
3757 #endif
3758
3759 static const struct net_device_ops mlx5e_netdev_ops = {
3760         .ndo_open                = mlx5e_open,
3761         .ndo_stop                = mlx5e_close,
3762         .ndo_start_xmit          = mlx5e_xmit,
3763         .ndo_setup_tc            = mlx5e_setup_tc,
3764         .ndo_select_queue        = mlx5e_select_queue,
3765         .ndo_get_stats64         = mlx5e_get_stats,
3766         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3767         .ndo_set_mac_address     = mlx5e_set_mac,
3768         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3769         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3770         .ndo_set_features        = mlx5e_set_features,
3771         .ndo_change_mtu          = mlx5e_change_mtu,
3772         .ndo_do_ioctl            = mlx5e_ioctl,
3773         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3774         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3775         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3776         .ndo_features_check      = mlx5e_features_check,
3777 #ifdef CONFIG_RFS_ACCEL
3778         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3779 #endif
3780         .ndo_tx_timeout          = mlx5e_tx_timeout,
3781         .ndo_xdp                 = mlx5e_xdp,
3782 #ifdef CONFIG_NET_POLL_CONTROLLER
3783         .ndo_poll_controller     = mlx5e_netpoll,
3784 #endif
3785 #ifdef CONFIG_MLX5_ESWITCH
3786         /* SRIOV E-Switch NDOs */
3787         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3788         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3789         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3790         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3791         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
3792         .ndo_get_vf_config       = mlx5e_get_vf_config,
3793         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3794         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3795         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
3796         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
3797 #endif
3798 };
3799
3800 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3801 {
3802         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3803                 return -EOPNOTSUPP;
3804         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3805             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3806             !MLX5_CAP_ETH(mdev, csum_cap) ||
3807             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3808             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3809             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3810             MLX5_CAP_FLOWTABLE(mdev,
3811                                flow_table_properties_nic_receive.max_ft_level)
3812                                < 3) {
3813                 mlx5_core_warn(mdev,
3814                                "Not creating net device, some required device capabilities are missing\n");
3815                 return -EOPNOTSUPP;
3816         }
3817         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3818                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3819         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3820                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3821
3822         return 0;
3823 }
3824
3825 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3826 {
3827         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3828
3829         return bf_buf_size -
3830                sizeof(struct mlx5e_tx_wqe) +
3831                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3832 }
3833
3834 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
3835                                    int num_channels)
3836 {
3837         int i;
3838
3839         for (i = 0; i < len; i++)
3840                 indirection_rqt[i] = i % num_channels;
3841 }
3842
3843 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3844 {
3845         enum pcie_link_width width;
3846         enum pci_bus_speed speed;
3847         int err = 0;
3848
3849         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3850         if (err)
3851                 return err;
3852
3853         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3854                 return -EINVAL;
3855
3856         switch (speed) {
3857         case PCIE_SPEED_2_5GT:
3858                 *pci_bw = 2500 * width;
3859                 break;
3860         case PCIE_SPEED_5_0GT:
3861                 *pci_bw = 5000 * width;
3862                 break;
3863         case PCIE_SPEED_8_0GT:
3864                 *pci_bw = 8000 * width;
3865                 break;
3866         default:
3867                 return -EINVAL;
3868         }
3869
3870         return 0;
3871 }
3872
3873 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3874 {
3875         return (link_speed && pci_bw &&
3876                 (pci_bw < 40000) && (pci_bw < link_speed));
3877 }
3878
3879 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3880 {
3881         return !(link_speed && pci_bw &&
3882                  (pci_bw <= 16000) && (pci_bw < link_speed));
3883 }
3884
3885 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3886 {
3887         params->rx_cq_period_mode = cq_period_mode;
3888
3889         params->rx_cq_moderation.pkts =
3890                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3891         params->rx_cq_moderation.usec =
3892                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3893
3894         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3895                 params->rx_cq_moderation.usec =
3896                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3897
3898         if (params->rx_am_enabled)
3899                 params->rx_cq_moderation =
3900                         mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3901
3902         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3903                         params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3904 }
3905
3906 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3907 {
3908         int i;
3909
3910         /* The supported periods are organized in ascending order */
3911         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3912                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3913                         break;
3914
3915         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3916 }
3917
3918 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3919                             struct mlx5e_params *params,
3920                             u16 max_channels)
3921 {
3922         u8 cq_period_mode = 0;
3923         u32 link_speed = 0;
3924         u32 pci_bw = 0;
3925
3926         params->num_channels = max_channels;
3927         params->num_tc       = 1;
3928
3929         mlx5e_get_max_linkspeed(mdev, &link_speed);
3930         mlx5e_get_pci_bw(mdev, &pci_bw);
3931         mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3932                       link_speed, pci_bw);
3933
3934         /* SQ */
3935         params->log_sq_size = is_kdump_kernel() ?
3936                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3937                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3938
3939         /* set CQE compression */
3940         params->rx_cqe_compress_def = false;
3941         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3942             MLX5_CAP_GEN(mdev, vport_group_manager))
3943                 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
3944
3945         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3946
3947         /* RQ */
3948         mlx5e_set_rq_params(mdev, params);
3949
3950         /* HW LRO */
3951
3952         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3953         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3954                 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
3955         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3956
3957         /* CQ moderation params */
3958         cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3959                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3960                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3961         params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3962         mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
3963
3964         params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3965         params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3966
3967         /* TX inline */
3968         params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3969         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3970         if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3971             !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3972                 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3973
3974         /* RSS */
3975         params->rss_hfunc = ETH_RSS_HASH_XOR;
3976         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3977         mlx5e_build_default_indir_rqt(params->indirection_rqt,
3978                                       MLX5E_INDIR_RQT_SIZE, max_channels);
3979 }
3980
3981 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3982                                         struct net_device *netdev,
3983                                         const struct mlx5e_profile *profile,
3984                                         void *ppriv)
3985 {
3986         struct mlx5e_priv *priv = netdev_priv(netdev);
3987
3988         priv->mdev        = mdev;
3989         priv->netdev      = netdev;
3990         priv->profile     = profile;
3991         priv->ppriv       = ppriv;
3992         priv->hard_mtu = MLX5E_ETH_HARD_MTU;
3993
3994         mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
3995
3996         mutex_init(&priv->state_lock);
3997
3998         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3999         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4000         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4001         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4002 }
4003
4004 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4005 {
4006         struct mlx5e_priv *priv = netdev_priv(netdev);
4007
4008         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4009         if (is_zero_ether_addr(netdev->dev_addr) &&
4010             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4011                 eth_hw_addr_random(netdev);
4012                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4013         }
4014 }
4015
4016 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4017 static const struct switchdev_ops mlx5e_switchdev_ops = {
4018         .switchdev_port_attr_get        = mlx5e_attr_get,
4019 };
4020 #endif
4021
4022 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4023 {
4024         struct mlx5e_priv *priv = netdev_priv(netdev);
4025         struct mlx5_core_dev *mdev = priv->mdev;
4026         bool fcs_supported;
4027         bool fcs_enabled;
4028
4029         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4030
4031         netdev->netdev_ops = &mlx5e_netdev_ops;
4032
4033 #ifdef CONFIG_MLX5_CORE_EN_DCB
4034         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4035                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4036 #endif
4037
4038         netdev->watchdog_timeo    = 15 * HZ;
4039
4040         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4041
4042         netdev->vlan_features    |= NETIF_F_SG;
4043         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4044         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4045         netdev->vlan_features    |= NETIF_F_GRO;
4046         netdev->vlan_features    |= NETIF_F_TSO;
4047         netdev->vlan_features    |= NETIF_F_TSO6;
4048         netdev->vlan_features    |= NETIF_F_RXCSUM;
4049         netdev->vlan_features    |= NETIF_F_RXHASH;
4050
4051         if (!!MLX5_CAP_ETH(mdev, lro_cap))
4052                 netdev->vlan_features    |= NETIF_F_LRO;
4053
4054         netdev->hw_features       = netdev->vlan_features;
4055         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4056         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4057         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4058
4059         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4060                 netdev->hw_features     |= NETIF_F_GSO_PARTIAL;
4061                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4062                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4063                 netdev->hw_enc_features |= NETIF_F_TSO;
4064                 netdev->hw_enc_features |= NETIF_F_TSO6;
4065                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4066         }
4067
4068         if (mlx5e_vxlan_allowed(mdev)) {
4069                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4070                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4071                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4072                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4073                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4074         }
4075
4076         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4077                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4078                                            NETIF_F_GSO_GRE_CSUM;
4079                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4080                                            NETIF_F_GSO_GRE_CSUM;
4081                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4082                                                 NETIF_F_GSO_GRE_CSUM;
4083         }
4084
4085         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4086
4087         if (fcs_supported)
4088                 netdev->hw_features |= NETIF_F_RXALL;
4089
4090         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4091                 netdev->hw_features |= NETIF_F_RXFCS;
4092
4093         netdev->features          = netdev->hw_features;
4094         if (!priv->channels.params.lro_en)
4095                 netdev->features  &= ~NETIF_F_LRO;
4096
4097         if (fcs_enabled)
4098                 netdev->features  &= ~NETIF_F_RXALL;
4099
4100         if (!priv->channels.params.scatter_fcs_en)
4101                 netdev->features  &= ~NETIF_F_RXFCS;
4102
4103 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4104         if (FT_CAP(flow_modify_en) &&
4105             FT_CAP(modify_root) &&
4106             FT_CAP(identified_miss_table_mode) &&
4107             FT_CAP(flow_table_modify)) {
4108                 netdev->hw_features      |= NETIF_F_HW_TC;
4109 #ifdef CONFIG_RFS_ACCEL
4110                 netdev->hw_features      |= NETIF_F_NTUPLE;
4111 #endif
4112         }
4113
4114         netdev->features         |= NETIF_F_HIGHDMA;
4115
4116         netdev->priv_flags       |= IFF_UNICAST_FLT;
4117
4118         mlx5e_set_netdev_dev_addr(netdev);
4119
4120 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4121         if (MLX5_VPORT_MANAGER(mdev))
4122                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4123 #endif
4124
4125         mlx5e_ipsec_build_netdev(priv);
4126 }
4127
4128 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4129 {
4130         struct mlx5_core_dev *mdev = priv->mdev;
4131         int err;
4132
4133         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4134         if (err) {
4135                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4136                 priv->q_counter = 0;
4137         }
4138 }
4139
4140 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4141 {
4142         if (!priv->q_counter)
4143                 return;
4144
4145         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4146 }
4147
4148 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4149                            struct net_device *netdev,
4150                            const struct mlx5e_profile *profile,
4151                            void *ppriv)
4152 {
4153         struct mlx5e_priv *priv = netdev_priv(netdev);
4154         int err;
4155
4156         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4157         err = mlx5e_ipsec_init(priv);
4158         if (err)
4159                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4160         mlx5e_build_nic_netdev(netdev);
4161         mlx5e_vxlan_init(priv);
4162 }
4163
4164 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4165 {
4166         mlx5e_ipsec_cleanup(priv);
4167         mlx5e_vxlan_cleanup(priv);
4168
4169         if (priv->channels.params.xdp_prog)
4170                 bpf_prog_put(priv->channels.params.xdp_prog);
4171 }
4172
4173 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4174 {
4175         struct mlx5_core_dev *mdev = priv->mdev;
4176         int err;
4177
4178         err = mlx5e_create_indirect_rqt(priv);
4179         if (err)
4180                 return err;
4181
4182         err = mlx5e_create_direct_rqts(priv);
4183         if (err)
4184                 goto err_destroy_indirect_rqts;
4185
4186         err = mlx5e_create_indirect_tirs(priv);
4187         if (err)
4188                 goto err_destroy_direct_rqts;
4189
4190         err = mlx5e_create_direct_tirs(priv);
4191         if (err)
4192                 goto err_destroy_indirect_tirs;
4193
4194         err = mlx5e_create_flow_steering(priv);
4195         if (err) {
4196                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4197                 goto err_destroy_direct_tirs;
4198         }
4199
4200         err = mlx5e_tc_init(priv);
4201         if (err)
4202                 goto err_destroy_flow_steering;
4203
4204         return 0;
4205
4206 err_destroy_flow_steering:
4207         mlx5e_destroy_flow_steering(priv);
4208 err_destroy_direct_tirs:
4209         mlx5e_destroy_direct_tirs(priv);
4210 err_destroy_indirect_tirs:
4211         mlx5e_destroy_indirect_tirs(priv);
4212 err_destroy_direct_rqts:
4213         mlx5e_destroy_direct_rqts(priv);
4214 err_destroy_indirect_rqts:
4215         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4216         return err;
4217 }
4218
4219 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4220 {
4221         mlx5e_tc_cleanup(priv);
4222         mlx5e_destroy_flow_steering(priv);
4223         mlx5e_destroy_direct_tirs(priv);
4224         mlx5e_destroy_indirect_tirs(priv);
4225         mlx5e_destroy_direct_rqts(priv);
4226         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4227 }
4228
4229 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4230 {
4231         int err;
4232
4233         err = mlx5e_create_tises(priv);
4234         if (err) {
4235                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4236                 return err;
4237         }
4238
4239 #ifdef CONFIG_MLX5_CORE_EN_DCB
4240         mlx5e_dcbnl_initialize(priv);
4241 #endif
4242         return 0;
4243 }
4244
4245 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4246 {
4247         struct net_device *netdev = priv->netdev;
4248         struct mlx5_core_dev *mdev = priv->mdev;
4249         u16 max_mtu;
4250
4251         mlx5e_init_l2_addr(priv);
4252
4253         /* Marking the link as currently not needed by the Driver */
4254         if (!netif_running(netdev))
4255                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4256
4257         /* MTU range: 68 - hw-specific max */
4258         netdev->min_mtu = ETH_MIN_MTU;
4259         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4260         netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4261         mlx5e_set_dev_port_mtu(priv);
4262
4263         mlx5_lag_add(mdev, netdev);
4264
4265         mlx5e_enable_async_events(priv);
4266
4267         if (MLX5_VPORT_MANAGER(priv->mdev))
4268                 mlx5e_register_vport_reps(priv);
4269
4270         if (netdev->reg_state != NETREG_REGISTERED)
4271                 return;
4272
4273         /* Device already registered: sync netdev system state */
4274         if (mlx5e_vxlan_allowed(mdev)) {
4275                 rtnl_lock();
4276                 udp_tunnel_get_rx_info(netdev);
4277                 rtnl_unlock();
4278         }
4279
4280         queue_work(priv->wq, &priv->set_rx_mode_work);
4281
4282         rtnl_lock();
4283         if (netif_running(netdev))
4284                 mlx5e_open(netdev);
4285         netif_device_attach(netdev);
4286         rtnl_unlock();
4287 }
4288
4289 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4290 {
4291         struct mlx5_core_dev *mdev = priv->mdev;
4292
4293         rtnl_lock();
4294         if (netif_running(priv->netdev))
4295                 mlx5e_close(priv->netdev);
4296         netif_device_detach(priv->netdev);
4297         rtnl_unlock();
4298
4299         queue_work(priv->wq, &priv->set_rx_mode_work);
4300
4301         if (MLX5_VPORT_MANAGER(priv->mdev))
4302                 mlx5e_unregister_vport_reps(priv);
4303
4304         mlx5e_disable_async_events(priv);
4305         mlx5_lag_remove(mdev);
4306 }
4307
4308 static const struct mlx5e_profile mlx5e_nic_profile = {
4309         .init              = mlx5e_nic_init,
4310         .cleanup           = mlx5e_nic_cleanup,
4311         .init_rx           = mlx5e_init_nic_rx,
4312         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4313         .init_tx           = mlx5e_init_nic_tx,
4314         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4315         .enable            = mlx5e_nic_enable,
4316         .disable           = mlx5e_nic_disable,
4317         .update_stats      = mlx5e_update_ndo_stats,
4318         .max_nch           = mlx5e_get_max_num_channels,
4319         .update_carrier    = mlx5e_update_carrier,
4320         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4321         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4322         .max_tc            = MLX5E_MAX_NUM_TC,
4323 };
4324
4325 /* mlx5e generic netdev management API (move to en_common.c) */
4326
4327 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4328                                        const struct mlx5e_profile *profile,
4329                                        void *ppriv)
4330 {
4331         int nch = profile->max_nch(mdev);
4332         struct net_device *netdev;
4333         struct mlx5e_priv *priv;
4334
4335         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4336                                     nch * profile->max_tc,
4337                                     nch);
4338         if (!netdev) {
4339                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4340                 return NULL;
4341         }
4342
4343 #ifdef CONFIG_RFS_ACCEL
4344         netdev->rx_cpu_rmap = mdev->rmap;
4345 #endif
4346
4347         profile->init(mdev, netdev, profile, ppriv);
4348
4349         netif_carrier_off(netdev);
4350
4351         priv = netdev_priv(netdev);
4352
4353         priv->wq = create_singlethread_workqueue("mlx5e");
4354         if (!priv->wq)
4355                 goto err_cleanup_nic;
4356
4357         return netdev;
4358
4359 err_cleanup_nic:
4360         if (profile->cleanup)
4361                 profile->cleanup(priv);
4362         free_netdev(netdev);
4363
4364         return NULL;
4365 }
4366
4367 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4368 {
4369         struct mlx5_core_dev *mdev = priv->mdev;
4370         const struct mlx5e_profile *profile;
4371         int err;
4372
4373         profile = priv->profile;
4374         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4375
4376         err = profile->init_tx(priv);
4377         if (err)
4378                 goto out;
4379
4380         err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4381         if (err) {
4382                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4383                 goto err_cleanup_tx;
4384         }
4385
4386         err = profile->init_rx(priv);
4387         if (err)
4388                 goto err_close_drop_rq;
4389
4390         mlx5e_create_q_counter(priv);
4391
4392         if (profile->enable)
4393                 profile->enable(priv);
4394
4395         return 0;
4396
4397 err_close_drop_rq:
4398         mlx5e_close_drop_rq(&priv->drop_rq);
4399
4400 err_cleanup_tx:
4401         profile->cleanup_tx(priv);
4402
4403 out:
4404         return err;
4405 }
4406
4407 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4408 {
4409         const struct mlx5e_profile *profile = priv->profile;
4410
4411         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4412
4413         if (profile->disable)
4414                 profile->disable(priv);
4415         flush_workqueue(priv->wq);
4416
4417         mlx5e_destroy_q_counter(priv);
4418         profile->cleanup_rx(priv);
4419         mlx5e_close_drop_rq(&priv->drop_rq);
4420         profile->cleanup_tx(priv);
4421         cancel_delayed_work_sync(&priv->update_stats_work);
4422 }
4423
4424 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4425 {
4426         const struct mlx5e_profile *profile = priv->profile;
4427         struct net_device *netdev = priv->netdev;
4428
4429         destroy_workqueue(priv->wq);
4430         if (profile->cleanup)
4431                 profile->cleanup(priv);
4432         free_netdev(netdev);
4433 }
4434
4435 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4436  * hardware contexts and to connect it to the current netdev.
4437  */
4438 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4439 {
4440         struct mlx5e_priv *priv = vpriv;
4441         struct net_device *netdev = priv->netdev;
4442         int err;
4443
4444         if (netif_device_present(netdev))
4445                 return 0;
4446
4447         err = mlx5e_create_mdev_resources(mdev);
4448         if (err)
4449                 return err;
4450
4451         err = mlx5e_attach_netdev(priv);
4452         if (err) {
4453                 mlx5e_destroy_mdev_resources(mdev);
4454                 return err;
4455         }
4456
4457         return 0;
4458 }
4459
4460 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4461 {
4462         struct mlx5e_priv *priv = vpriv;
4463         struct net_device *netdev = priv->netdev;
4464
4465         if (!netif_device_present(netdev))
4466                 return;
4467
4468         mlx5e_detach_netdev(priv);
4469         mlx5e_destroy_mdev_resources(mdev);
4470 }
4471
4472 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4473 {
4474         struct net_device *netdev;
4475         void *rpriv = NULL;
4476         void *priv;
4477         int err;
4478
4479         err = mlx5e_check_required_hca_cap(mdev);
4480         if (err)
4481                 return NULL;
4482
4483 #ifdef CONFIG_MLX5_ESWITCH
4484         if (MLX5_VPORT_MANAGER(mdev)) {
4485                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4486                 if (!rpriv) {
4487                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4488                         return NULL;
4489                 }
4490         }
4491 #endif
4492
4493         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4494         if (!netdev) {
4495                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4496                 goto err_free_rpriv;
4497         }
4498
4499         priv = netdev_priv(netdev);
4500
4501         err = mlx5e_attach(mdev, priv);
4502         if (err) {
4503                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4504                 goto err_destroy_netdev;
4505         }
4506
4507         err = register_netdev(netdev);
4508         if (err) {
4509                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4510                 goto err_detach;
4511         }
4512
4513         return priv;
4514
4515 err_detach:
4516         mlx5e_detach(mdev, priv);
4517 err_destroy_netdev:
4518         mlx5e_destroy_netdev(priv);
4519 err_free_rpriv:
4520         kfree(rpriv);
4521         return NULL;
4522 }
4523
4524 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4525 {
4526         struct mlx5e_priv *priv = vpriv;
4527         void *ppriv = priv->ppriv;
4528
4529         unregister_netdev(priv->netdev);
4530         mlx5e_detach(mdev, vpriv);
4531         mlx5e_destroy_netdev(priv);
4532         kfree(ppriv);
4533 }
4534
4535 static void *mlx5e_get_netdev(void *vpriv)
4536 {
4537         struct mlx5e_priv *priv = vpriv;
4538
4539         return priv->netdev;
4540 }
4541
4542 static struct mlx5_interface mlx5e_interface = {
4543         .add       = mlx5e_add,
4544         .remove    = mlx5e_remove,
4545         .attach    = mlx5e_attach,
4546         .detach    = mlx5e_detach,
4547         .event     = mlx5e_async_event,
4548         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4549         .get_dev   = mlx5e_get_netdev,
4550 };
4551
4552 void mlx5e_init(void)
4553 {
4554         mlx5e_ipsec_build_inverse_table();
4555         mlx5e_build_ptys2ethtool_map();
4556         mlx5_register_interface(&mlx5e_interface);
4557 }
4558
4559 void mlx5e_cleanup(void)
4560 {
4561         mlx5_unregister_interface(&mlx5e_interface);
4562 }