drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <linux/crash_dump.h>
  35 #include <net/pkt_cls.h>
  36 #include <linux/mlx5/fs.h>
  37 #include <net/vxlan.h>
  38 #include <linux/bpf.h>
  39 #include "en.h"
  40 #include "en_tc.h"
  41 #include "eswitch.h"
  42 #include "vxlan.h"
  43
  44 struct mlx5e_rq_param {
  45         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  46         struct mlx5_wq_param    wq;
  47         bool                    am_enabled;
  48 };
  49
  50 struct mlx5e_sq_param {
  51         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  52         struct mlx5_wq_param       wq;
  53         u16                        max_inline;
  54         u8                         min_inline_mode;
  55         enum mlx5e_sq_type         type;
  56 };
  57
  58 struct mlx5e_cq_param {
  59         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  60         struct mlx5_wq_param       wq;
  61         u16                        eq_ix;
  62         u8                         cq_period_mode;
  63 };
  64
  65 struct mlx5e_channel_param {
  66         struct mlx5e_rq_param      rq;
  67         struct mlx5e_sq_param      sq;
  68         struct mlx5e_sq_param      xdp_sq;
  69         struct mlx5e_sq_param      icosq;
  70         struct mlx5e_cq_param      rx_cq;
  71         struct mlx5e_cq_param      tx_cq;
  72         struct mlx5e_cq_param      icosq_cq;
  73 };
  74
  75 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  76 {
  77         return MLX5_CAP_GEN(mdev, striding_rq) &&
  78                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  79                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  80 }
  81
  82 void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  83 {
  84         priv->params.rq_wq_type = rq_type;
  85         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
  86         switch (priv->params.rq_wq_type) {
  87         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  88                 priv->params.log_rq_size = is_kdump_kernel() ?
  89                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
  90                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  91                 priv->params.mpwqe_log_stride_sz =
  92                         MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
  93                         MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(priv->mdev) :
  94                         MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(priv->mdev);
  95                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  96                         priv->params.mpwqe_log_stride_sz;
  97                 break;
  98         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  99                 priv->params.log_rq_size = is_kdump_kernel() ?
 100                         MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 101                         MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 102
 103                 /* Extra room needed for build_skb */
 104                 priv->params.lro_wqe_sz -= MLX5_RX_HEADROOM +
 105                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 106         }
 107         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
 108                                                BIT(priv->params.log_rq_size));
 109
 110         mlx5_core_info(priv->mdev,
 111                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 112                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 113                        BIT(priv->params.log_rq_size),
 114                        BIT(priv->params.mpwqe_log_stride_sz),
 115                        MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
 116 }
 117
 118 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 119 {
 120         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 121                     !priv->xdp_prog ?
 122                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 123                     MLX5_WQ_TYPE_LINKED_LIST;
 124         mlx5e_set_rq_type_params(priv, rq_type);
 125 }
 126
 127 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 128 {
 129         struct mlx5_core_dev *mdev = priv->mdev;
 130         u8 port_state;
 131
 132         port_state = mlx5_query_vport_state(mdev,
 133                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 134
 135         if (port_state == VPORT_STATE_UP) {
 136                 netdev_info(priv->netdev, "Link up\n");
 137                 netif_carrier_on(priv->netdev);
 138         } else {
 139                 netdev_info(priv->netdev, "Link down\n");
 140                 netif_carrier_off(priv->netdev);
 141         }
 142 }
 143
 144 static void mlx5e_update_carrier_work(struct work_struct *work)
 145 {
 146         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 147                                                update_carrier_work);
 148
 149         mutex_lock(&priv->state_lock);
 150         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 151                 mlx5e_update_carrier(priv);
 152         mutex_unlock(&priv->state_lock);
 153 }
 154
 155 static void mlx5e_tx_timeout_work(struct work_struct *work)
 156 {
 157         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 158                                                tx_timeout_work);
 159         int err;
 160
 161         rtnl_lock();
 162         mutex_lock(&priv->state_lock);
 163         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 164                 goto unlock;
 165         mlx5e_close_locked(priv->netdev);
 166         err = mlx5e_open_locked(priv->netdev);
 167         if (err)
 168                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 169                            err);
 170 unlock:
 171         mutex_unlock(&priv->state_lock);
 172         rtnl_unlock();
 173 }
 174
 175 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 176 {
 177         struct mlx5e_sw_stats *s = &priv->stats.sw;
 178         struct mlx5e_rq_stats *rq_stats;
 179         struct mlx5e_sq_stats *sq_stats;
 180         u64 tx_offload_none = 0;
 181         int i, j;
 182
 183         memset(s, 0, sizeof(*s));
 184         for (i = 0; i < priv->params.num_channels; i++) {
 185                 rq_stats = &priv->channel[i]->rq.stats;
 186
 187                 s->rx_packets   += rq_stats->packets;
 188                 s->rx_bytes     += rq_stats->bytes;
 189                 s->rx_lro_packets += rq_stats->lro_packets;
 190                 s->rx_lro_bytes += rq_stats->lro_bytes;
 191                 s->rx_csum_none += rq_stats->csum_none;
 192                 s->rx_csum_complete += rq_stats->csum_complete;
 193                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 194                 s->rx_xdp_drop += rq_stats->xdp_drop;
 195                 s->rx_xdp_tx += rq_stats->xdp_tx;
 196                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 197                 s->rx_wqe_err   += rq_stats->wqe_err;
 198                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 199                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 200                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 201                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 202                 s->rx_cache_reuse += rq_stats->cache_reuse;
 203                 s->rx_cache_full  += rq_stats->cache_full;
 204                 s->rx_cache_empty += rq_stats->cache_empty;
 205                 s->rx_cache_busy  += rq_stats->cache_busy;
 206
 207                 for (j = 0; j < priv->params.num_tc; j++) {
 208                         sq_stats = &priv->channel[i]->sq[j].stats;
 209
 210                         s->tx_packets           += sq_stats->packets;
 211                         s->tx_bytes             += sq_stats->bytes;
 212                         s->tx_tso_packets       += sq_stats->tso_packets;
 213                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 214                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 215                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 216                         s->tx_queue_stopped     += sq_stats->stopped;
 217                         s->tx_queue_wake        += sq_stats->wake;
 218                         s->tx_queue_dropped     += sq_stats->dropped;
 219                         s->tx_xmit_more         += sq_stats->xmit_more;
 220                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 221                         tx_offload_none         += sq_stats->csum_none;
 222                 }
 223         }
 224
 225         /* Update calculated offload counters */
 226         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 227         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 228
 229         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 230                                 priv->stats.pport.phy_counters,
 231                                 counter_set.phys_layer_cntrs.link_down_events);
 232 }
 233
 234 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 235 {
 236         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 237         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 238         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 239         struct mlx5_core_dev *mdev = priv->mdev;
 240
 241         MLX5_SET(query_vport_counter_in, in, opcode,
 242                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 243         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 244         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 245
 246         memset(out, 0, outlen);
 247         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 248 }
 249
 250 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 251 {
 252         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 253         struct mlx5_core_dev *mdev = priv->mdev;
 254         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 255         int prio;
 256         void *out;
 257         u32 *in;
 258
 259         in = mlx5_vzalloc(sz);
 260         if (!in)
 261                 goto free_out;
 262
 263         MLX5_SET(ppcnt_reg, in, local_port, 1);
 264
 265         out = pstats->IEEE_802_3_counters;
 266         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 267         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 268
 269         out = pstats->RFC_2863_counters;
 270         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 271         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 272
 273         out = pstats->RFC_2819_counters;
 274         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 275         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 276
 277         out = pstats->phy_counters;
 278         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 279         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 280
 281         if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
 282                 out = pstats->phy_statistical_counters;
 283                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 284                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 285         }
 286
 287         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 288         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 289                 out = pstats->per_prio_counters[prio];
 290                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 291                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 292                                      MLX5_REG_PPCNT, 0, 0);
 293         }
 294
 295 free_out:
 296         kvfree(in);
 297 }
 298
 299 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 300 {
 301         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 302
 303         if (!priv->q_counter)
 304                 return;
 305
 306         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 307                                       &qcnt->rx_out_of_buffer);
 308 }
 309
 310 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 311 {
 312         struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
 313         struct mlx5_core_dev *mdev = priv->mdev;
 314         int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 315         void *out;
 316         u32 *in;
 317
 318         if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
 319                 return;
 320
 321         in = mlx5_vzalloc(sz);
 322         if (!in)
 323                 return;
 324
 325         out = pcie_stats->pcie_perf_counters;
 326         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 327         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 328
 329         kvfree(in);
 330 }
 331
 332 void mlx5e_update_stats(struct mlx5e_priv *priv)
 333 {
 334         mlx5e_update_pcie_counters(priv);
 335         mlx5e_update_pport_counters(priv);
 336         mlx5e_update_vport_counters(priv);
 337         mlx5e_update_q_counter(priv);
 338         mlx5e_update_sw_counters(priv);
 339 }
 340
 341 void mlx5e_update_stats_work(struct work_struct *work)
 342 {
 343         struct delayed_work *dwork = to_delayed_work(work);
 344         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 345                                                update_stats_work);
 346         mutex_lock(&priv->state_lock);
 347         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 348                 priv->profile->update_stats(priv);
 349                 queue_delayed_work(priv->wq, dwork,
 350                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 351         }
 352         mutex_unlock(&priv->state_lock);
 353 }
 354
 355 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 356                               enum mlx5_dev_event event, unsigned long param)
 357 {
 358         struct mlx5e_priv *priv = vpriv;
 359         struct ptp_clock_event ptp_event;
 360         struct mlx5_eqe *eqe = NULL;
 361
 362         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 363                 return;
 364
 365         switch (event) {
 366         case MLX5_DEV_EVENT_PORT_UP:
 367         case MLX5_DEV_EVENT_PORT_DOWN:
 368                 queue_work(priv->wq, &priv->update_carrier_work);
 369                 break;
 370         case MLX5_DEV_EVENT_PPS:
 371                 eqe = (struct mlx5_eqe *)param;
 372                 ptp_event.type = PTP_CLOCK_EXTTS;
 373                 ptp_event.index = eqe->data.pps.pin;
 374                 ptp_event.timestamp =
 375                         timecounter_cyc2time(&priv->tstamp.clock,
 376                                              be64_to_cpu(eqe->data.pps.time_stamp));
 377                 mlx5e_pps_event_handler(vpriv, &ptp_event);
 378                 break;
 379         default:
 380                 break;
 381         }
 382 }
 383
 384 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 385 {
 386         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 387 }
 388
 389 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 390 {
 391         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 392         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 393 }
 394
 395 static inline int mlx5e_get_wqe_mtt_sz(void)
 396 {
 397         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 398          * To avoid copying garbage after the mtt array, we allocate
 399          * a little more.
 400          */
 401         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 402                      MLX5_UMR_MTT_ALIGNMENT);
 403 }
 404
 405 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 406                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 407 {
 408         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 409         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 410         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 411         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 412         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 413         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 414
 415         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 416                                       ds_cnt);
 417         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 418         cseg->imm       = rq->mkey_be;
 419
 420         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 421         ucseg->xlt_octowords =
 422                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 423         ucseg->bsf_octowords =
 424                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 425         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 426
 427         dseg->lkey = sq->mkey_be;
 428         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 429 }
 430
 431 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 432                                      struct mlx5e_channel *c)
 433 {
 434         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 435         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 436         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 437         int i;
 438
 439         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 440                                       GFP_KERNEL, cpu_to_node(c->cpu));
 441         if (!rq->mpwqe.info)
 442                 goto err_out;
 443
 444         /* We allocate more than mtt_sz as we will align the pointer */
 445         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 446                                         cpu_to_node(c->cpu));
 447         if (unlikely(!rq->mpwqe.mtt_no_align))
 448                 goto err_free_wqe_info;
 449
 450         for (i = 0; i < wq_sz; i++) {
 451                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 452
 453                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 454                                         MLX5_UMR_ALIGN);
 455                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 456                                                   PCI_DMA_TODEVICE);
 457                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 458                         goto err_unmap_mtts;
 459
 460                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 461         }
 462
 463         return 0;
 464
 465 err_unmap_mtts:
 466         while (--i >= 0) {
 467                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 468
 469                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 470                                  PCI_DMA_TODEVICE);
 471         }
 472         kfree(rq->mpwqe.mtt_no_align);
 473 err_free_wqe_info:
 474         kfree(rq->mpwqe.info);
 475
 476 err_out:
 477         return -ENOMEM;
 478 }
 479
 480 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 481 {
 482         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 483         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 484         int i;
 485
 486         for (i = 0; i < wq_sz; i++) {
 487                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 488
 489                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 490                                  PCI_DMA_TODEVICE);
 491         }
 492         kfree(rq->mpwqe.mtt_no_align);
 493         kfree(rq->mpwqe.info);
 494 }
 495
 496 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
 497                                  u64 npages, u8 page_shift,
 498                                  struct mlx5_core_mkey *umr_mkey)
 499 {
 500         struct mlx5_core_dev *mdev = priv->mdev;
 501         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 502         void *mkc;
 503         u32 *in;
 504         int err;
 505
 506         if (!MLX5E_VALID_NUM_MTTS(npages))
 507                 return -EINVAL;
 508
 509         in = mlx5_vzalloc(inlen);
 510         if (!in)
 511                 return -ENOMEM;
 512
 513         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 514
 515         MLX5_SET(mkc, mkc, free, 1);
 516         MLX5_SET(mkc, mkc, umr_en, 1);
 517         MLX5_SET(mkc, mkc, lw, 1);
 518         MLX5_SET(mkc, mkc, lr, 1);
 519         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
 520
 521         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 522         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 523         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 524         MLX5_SET(mkc, mkc, translations_octword_size,
 525                  MLX5_MTT_OCTW(npages));
 526         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 527
 528         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 529
 530         kvfree(in);
 531         return err;
 532 }
 533
 534 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
 535 {
 536         struct mlx5e_priv *priv = rq->priv;
 537         u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
 538
 539         return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 540 }
 541
 542 static int mlx5e_create_rq(struct mlx5e_channel *c,
 543                            struct mlx5e_rq_param *param,
 544                            struct mlx5e_rq *rq)
 545 {
 546         struct mlx5e_priv *priv = c->priv;
 547         struct mlx5_core_dev *mdev = priv->mdev;
 548         void *rqc = param->rqc;
 549         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 550         u32 byte_count;
 551         u32 frag_sz;
 552         int npages;
 553         int wq_sz;
 554         int err;
 555         int i;
 556
 557         param->wq.db_numa_node = cpu_to_node(c->cpu);
 558
 559         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 560                                 &rq->wq_ctrl);
 561         if (err)
 562                 return err;
 563
 564         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 565
 566         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 567
 568         rq->wq_type = priv->params.rq_wq_type;
 569         rq->pdev    = c->pdev;
 570         rq->netdev  = c->netdev;
 571         rq->tstamp  = &priv->tstamp;
 572         rq->channel = c;
 573         rq->ix      = c->ix;
 574         rq->priv    = c->priv;
 575
 576         rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
 577         if (IS_ERR(rq->xdp_prog)) {
 578                 err = PTR_ERR(rq->xdp_prog);
 579                 rq->xdp_prog = NULL;
 580                 goto err_rq_wq_destroy;
 581         }
 582
 583         if (rq->xdp_prog) {
 584                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
 585                 rq->rx_headroom = XDP_PACKET_HEADROOM;
 586         } else {
 587                 rq->buff.map_dir = DMA_FROM_DEVICE;
 588                 rq->rx_headroom = MLX5_RX_HEADROOM;
 589         }
 590
 591         switch (priv->params.rq_wq_type) {
 592         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 593                 if (mlx5e_is_vf_vport_rep(priv)) {
 594                         err = -EINVAL;
 595                         goto err_rq_wq_destroy;
 596                 }
 597
 598                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 599                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 600                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 601
 602                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 603                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 604
 605                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 606                 byte_count = rq->buff.wqe_sz;
 607
 608                 err = mlx5e_create_rq_umr_mkey(rq);
 609                 if (err)
 610                         goto err_rq_wq_destroy;
 611                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 612
 613                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 614                 if (err)
 615                         goto err_destroy_umr_mkey;
 616                 break;
 617         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 618                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 619                                             GFP_KERNEL, cpu_to_node(c->cpu));
 620                 if (!rq->dma_info) {
 621                         err = -ENOMEM;
 622                         goto err_rq_wq_destroy;
 623                 }
 624
 625                 if (mlx5e_is_vf_vport_rep(priv))
 626                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
 627                 else
 628                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 629
 630                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 631                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 632
 633                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 634                                 priv->params.lro_wqe_sz :
 635                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 636                 byte_count = rq->buff.wqe_sz;
 637
 638                 /* calc the required page order */
 639                 frag_sz = rq->rx_headroom +
 640                           byte_count /* packet data */ +
 641                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 642                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 643
 644                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 645                 rq->buff.page_order = order_base_2(npages);
 646
 647                 byte_count |= MLX5_HW_START_PADDING;
 648                 rq->mkey_be = c->mkey_be;
 649         }
 650
 651         for (i = 0; i < wq_sz; i++) {
 652                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 653
 654                 wqe->data.byte_count = cpu_to_be32(byte_count);
 655                 wqe->data.lkey = rq->mkey_be;
 656         }
 657
 658         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 659         rq->am.mode = priv->params.rx_cq_period_mode;
 660
 661         rq->page_cache.head = 0;
 662         rq->page_cache.tail = 0;
 663
 664         return 0;
 665
 666 err_destroy_umr_mkey:
 667         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 668
 669 err_rq_wq_destroy:
 670         if (rq->xdp_prog)
 671                 bpf_prog_put(rq->xdp_prog);
 672         mlx5_wq_destroy(&rq->wq_ctrl);
 673
 674         return err;
 675 }
 676
 677 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 678 {
 679         int i;
 680
 681         if (rq->xdp_prog)
 682                 bpf_prog_put(rq->xdp_prog);
 683
 684         switch (rq->wq_type) {
 685         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 686                 mlx5e_rq_free_mpwqe_info(rq);
 687                 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
 688                 break;
 689         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 690                 kfree(rq->dma_info);
 691         }
 692
 693         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 694              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 695                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 696
 697                 mlx5e_page_release(rq, dma_info, false);
 698         }
 699         mlx5_wq_destroy(&rq->wq_ctrl);
 700 }
 701
 702 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 703 {
 704         struct mlx5e_priv *priv = rq->priv;
 705         struct mlx5_core_dev *mdev = priv->mdev;
 706
 707         void *in;
 708         void *rqc;
 709         void *wq;
 710         int inlen;
 711         int err;
 712
 713         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 714                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 715         in = mlx5_vzalloc(inlen);
 716         if (!in)
 717                 return -ENOMEM;
 718
 719         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 720         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 721
 722         memcpy(rqc, param->rqc, sizeof(param->rqc));
 723
 724         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 725         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 726         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 727         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 728                                                 MLX5_ADAPTER_PAGE_SHIFT);
 729         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 730
 731         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 732                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 733
 734         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 735
 736         kvfree(in);
 737
 738         return err;
 739 }
 740
 741 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 742                                  int next_state)
 743 {
 744         struct mlx5e_channel *c = rq->channel;
 745         struct mlx5e_priv *priv = c->priv;
 746         struct mlx5_core_dev *mdev = priv->mdev;
 747
 748         void *in;
 749         void *rqc;
 750         int inlen;
 751         int err;
 752
 753         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 754         in = mlx5_vzalloc(inlen);
 755         if (!in)
 756                 return -ENOMEM;
 757
 758         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 759
 760         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 761         MLX5_SET(rqc, rqc, state, next_state);
 762
 763         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 764
 765         kvfree(in);
 766
 767         return err;
 768 }
 769
 770 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 771 {
 772         struct mlx5e_channel *c = rq->channel;
 773         struct mlx5e_priv *priv = c->priv;
 774         struct mlx5_core_dev *mdev = priv->mdev;
 775
 776         void *in;
 777         void *rqc;
 778         int inlen;
 779         int err;
 780
 781         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 782         in = mlx5_vzalloc(inlen);
 783         if (!in)
 784                 return -ENOMEM;
 785
 786         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 787
 788         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 789         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 790                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 791         MLX5_SET(rqc, rqc, vsd, vsd);
 792         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 793
 794         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 795
 796         kvfree(in);
 797
 798         return err;
 799 }
 800
 801 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 802 {
 803         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 804 }
 805
 806 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 807 {
 808         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 809         struct mlx5e_channel *c = rq->channel;
 810         struct mlx5e_priv *priv = c->priv;
 811         struct mlx5_wq_ll *wq = &rq->wq;
 812
 813         while (time_before(jiffies, exp_time)) {
 814                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 815                         return 0;
 816
 817                 msleep(20);
 818         }
 819
 820         return -ETIMEDOUT;
 821 }
 822
 823 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 824 {
 825         struct mlx5_wq_ll *wq = &rq->wq;
 826         struct mlx5e_rx_wqe *wqe;
 827         __be16 wqe_ix_be;
 828         u16 wqe_ix;
 829
 830         /* UMR WQE (if in progress) is always at wq->head */
 831         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 832                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 833
 834         while (!mlx5_wq_ll_is_empty(wq)) {
 835                 wqe_ix_be = *wq->tail_next;
 836                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 837                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 838                 rq->dealloc_wqe(rq, wqe_ix);
 839                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 840                                &wqe->next.next_wqe_index);
 841         }
 842 }
 843
 844 static int mlx5e_open_rq(struct mlx5e_channel *c,
 845                          struct mlx5e_rq_param *param,
 846                          struct mlx5e_rq *rq)
 847 {
 848         struct mlx5e_sq *sq = &c->icosq;
 849         u16 pi = sq->pc & sq->wq.sz_m1;
 850         int err;
 851
 852         err = mlx5e_create_rq(c, param, rq);
 853         if (err)
 854                 return err;
 855
 856         err = mlx5e_enable_rq(rq, param);
 857         if (err)
 858                 goto err_destroy_rq;
 859
 860         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 861         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 862         if (err)
 863                 goto err_disable_rq;
 864
 865         if (param->am_enabled)
 866                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 867
 868         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 869         sq->db.ico_wqe[pi].num_wqebbs = 1;
 870         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 871
 872         return 0;
 873
 874 err_disable_rq:
 875         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 876         mlx5e_disable_rq(rq);
 877 err_destroy_rq:
 878         mlx5e_destroy_rq(rq);
 879
 880         return err;
 881 }
 882
 883 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 884 {
 885         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 886         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 887         cancel_work_sync(&rq->am.work);
 888
 889         mlx5e_disable_rq(rq);
 890         mlx5e_free_rx_descs(rq);
 891         mlx5e_destroy_rq(rq);
 892 }
 893
 894 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
 895 {
 896         kfree(sq->db.xdp.di);
 897         kfree(sq->db.xdp.wqe_info);
 898 }
 899
 900 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
 901 {
 902         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 903
 904         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
 905                                      GFP_KERNEL, numa);
 906         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
 907                                            GFP_KERNEL, numa);
 908         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
 909                 mlx5e_free_sq_xdp_db(sq);
 910                 return -ENOMEM;
 911         }
 912
 913         return 0;
 914 }
 915
 916 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 917 {
 918         kfree(sq->db.ico_wqe);
 919 }
 920
 921 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 922 {
 923         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 924
 925         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 926                                       GFP_KERNEL, numa);
 927         if (!sq->db.ico_wqe)
 928                 return -ENOMEM;
 929
 930         return 0;
 931 }
 932
 933 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 934 {
 935         kfree(sq->db.txq.wqe_info);
 936         kfree(sq->db.txq.dma_fifo);
 937         kfree(sq->db.txq.skb);
 938 }
 939
 940 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 941 {
 942         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 943         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 944
 945         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 946                                       GFP_KERNEL, numa);
 947         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 948                                            GFP_KERNEL, numa);
 949         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 950                                            GFP_KERNEL, numa);
 951         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 952                 mlx5e_free_sq_txq_db(sq);
 953                 return -ENOMEM;
 954         }
 955
 956         sq->dma_fifo_mask = df_sz - 1;
 957
 958         return 0;
 959 }
 960
 961 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 962 {
 963         switch (sq->type) {
 964         case MLX5E_SQ_TXQ:
 965                 mlx5e_free_sq_txq_db(sq);
 966                 break;
 967         case MLX5E_SQ_ICO:
 968                 mlx5e_free_sq_ico_db(sq);
 969                 break;
 970         case MLX5E_SQ_XDP:
 971                 mlx5e_free_sq_xdp_db(sq);
 972                 break;
 973         }
 974 }
 975
 976 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 977 {
 978         switch (sq->type) {
 979         case MLX5E_SQ_TXQ:
 980                 return mlx5e_alloc_sq_txq_db(sq, numa);
 981         case MLX5E_SQ_ICO:
 982                 return mlx5e_alloc_sq_ico_db(sq, numa);
 983         case MLX5E_SQ_XDP:
 984                 return mlx5e_alloc_sq_xdp_db(sq, numa);
 985         }
 986
 987         return 0;
 988 }
 989
 990 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
 991 {
 992         switch (sq_type) {
 993         case MLX5E_SQ_ICO:
 994                 return MLX5E_ICOSQ_MAX_WQEBBS;
 995         case MLX5E_SQ_XDP:
 996                 return MLX5E_XDP_TX_WQEBBS;
 997         }
 998         return MLX5_SEND_WQE_MAX_WQEBBS;
 999 }
1000
1001 static int mlx5e_create_sq(struct mlx5e_channel *c,
1002                            int tc,
1003                            struct mlx5e_sq_param *param,
1004                            struct mlx5e_sq *sq)
1005 {
1006         struct mlx5e_priv *priv = c->priv;
1007         struct mlx5_core_dev *mdev = priv->mdev;
1008
1009         void *sqc = param->sqc;
1010         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1011         int err;
1012
1013         sq->type      = param->type;
1014         sq->pdev      = c->pdev;
1015         sq->tstamp    = &priv->tstamp;
1016         sq->mkey_be   = c->mkey_be;
1017         sq->channel   = c;
1018         sq->tc        = tc;
1019
1020         err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
1021         if (err)
1022                 return err;
1023
1024         sq->uar_map = sq->bfreg.map;
1025         param->wq.db_numa_node = cpu_to_node(c->cpu);
1026
1027         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1028                                  &sq->wq_ctrl);
1029         if (err)
1030                 goto err_unmap_free_uar;
1031
1032         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
1033         if (sq->bfreg.wc)
1034                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
1035
1036         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1037         sq->max_inline  = param->max_inline;
1038         sq->min_inline_mode = param->min_inline_mode;
1039
1040         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1041         if (err)
1042                 goto err_sq_wq_destroy;
1043
1044         if (sq->type == MLX5E_SQ_TXQ) {
1045                 int txq_ix;
1046
1047                 txq_ix = c->ix + tc * priv->params.num_channels;
1048                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1049                 priv->txq_to_sq_map[txq_ix] = sq;
1050         }
1051
1052         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
1053         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
1054
1055         return 0;
1056
1057 err_sq_wq_destroy:
1058         mlx5_wq_destroy(&sq->wq_ctrl);
1059
1060 err_unmap_free_uar:
1061         mlx5_free_bfreg(mdev, &sq->bfreg);
1062
1063         return err;
1064 }
1065
1066 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1067 {
1068         struct mlx5e_channel *c = sq->channel;
1069         struct mlx5e_priv *priv = c->priv;
1070
1071         mlx5e_free_sq_db(sq);
1072         mlx5_wq_destroy(&sq->wq_ctrl);
1073         mlx5_free_bfreg(priv->mdev, &sq->bfreg);
1074 }
1075
1076 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1077 {
1078         struct mlx5e_channel *c = sq->channel;
1079         struct mlx5e_priv *priv = c->priv;
1080         struct mlx5_core_dev *mdev = priv->mdev;
1081
1082         void *in;
1083         void *sqc;
1084         void *wq;
1085         int inlen;
1086         int err;
1087
1088         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1089                 sizeof(u64) * sq->wq_ctrl.buf.npages;
1090         in = mlx5_vzalloc(inlen);
1091         if (!in)
1092                 return -ENOMEM;
1093
1094         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1095         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1096
1097         memcpy(sqc, param->sqc, sizeof(param->sqc));
1098
1099         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1100                                        0 : priv->tisn[sq->tc]);
1101         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1102
1103         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1104                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1105
1106         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1107         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1108
1109         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1110         MLX5_SET(wq,   wq, uar_page,      sq->bfreg.index);
1111         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1112                                           MLX5_ADAPTER_PAGE_SHIFT);
1113         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1114
1115         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1116                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1117
1118         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1119
1120         kvfree(in);
1121
1122         return err;
1123 }
1124
1125 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1126                            int next_state, bool update_rl, int rl_index)
1127 {
1128         struct mlx5e_channel *c = sq->channel;
1129         struct mlx5e_priv *priv = c->priv;
1130         struct mlx5_core_dev *mdev = priv->mdev;
1131
1132         void *in;
1133         void *sqc;
1134         int inlen;
1135         int err;
1136
1137         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1138         in = mlx5_vzalloc(inlen);
1139         if (!in)
1140                 return -ENOMEM;
1141
1142         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1143
1144         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1145         MLX5_SET(sqc, sqc, state, next_state);
1146         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1147                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1148                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1149         }
1150
1151         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1152
1153         kvfree(in);
1154
1155         return err;
1156 }
1157
1158 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1159 {
1160         struct mlx5e_channel *c = sq->channel;
1161         struct mlx5e_priv *priv = c->priv;
1162         struct mlx5_core_dev *mdev = priv->mdev;
1163
1164         mlx5_core_destroy_sq(mdev, sq->sqn);
1165         if (sq->rate_limit)
1166                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1167 }
1168
1169 static int mlx5e_open_sq(struct mlx5e_channel *c,
1170                          int tc,
1171                          struct mlx5e_sq_param *param,
1172                          struct mlx5e_sq *sq)
1173 {
1174         int err;
1175
1176         err = mlx5e_create_sq(c, tc, param, sq);
1177         if (err)
1178                 return err;
1179
1180         err = mlx5e_enable_sq(sq, param);
1181         if (err)
1182                 goto err_destroy_sq;
1183
1184         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1185         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1186                               false, 0);
1187         if (err)
1188                 goto err_disable_sq;
1189
1190         if (sq->txq) {
1191                 netdev_tx_reset_queue(sq->txq);
1192                 netif_tx_start_queue(sq->txq);
1193         }
1194
1195         return 0;
1196
1197 err_disable_sq:
1198         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1199         mlx5e_disable_sq(sq);
1200 err_destroy_sq:
1201         mlx5e_destroy_sq(sq);
1202
1203         return err;
1204 }
1205
1206 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1207 {
1208         __netif_tx_lock_bh(txq);
1209         netif_tx_stop_queue(txq);
1210         __netif_tx_unlock_bh(txq);
1211 }
1212
1213 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1214 {
1215         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1216         /* prevent netif_tx_wake_queue */
1217         napi_synchronize(&sq->channel->napi);
1218
1219         if (sq->txq) {
1220                 netif_tx_disable_queue(sq->txq);
1221
1222                 /* last doorbell out, godspeed .. */
1223                 if (mlx5e_sq_has_room_for(sq, 1)) {
1224                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1225                         mlx5e_send_nop(sq, true);
1226                 }
1227         }
1228
1229         mlx5e_disable_sq(sq);
1230         mlx5e_free_sq_descs(sq);
1231         mlx5e_destroy_sq(sq);
1232 }
1233
1234 static int mlx5e_create_cq(struct mlx5e_channel *c,
1235                            struct mlx5e_cq_param *param,
1236                            struct mlx5e_cq *cq)
1237 {
1238         struct mlx5e_priv *priv = c->priv;
1239         struct mlx5_core_dev *mdev = priv->mdev;
1240         struct mlx5_core_cq *mcq = &cq->mcq;
1241         int eqn_not_used;
1242         unsigned int irqn;
1243         int err;
1244         u32 i;
1245
1246         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1247         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1248         param->eq_ix   = c->ix;
1249
1250         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1251                                &cq->wq_ctrl);
1252         if (err)
1253                 return err;
1254
1255         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1256
1257         cq->napi        = &c->napi;
1258
1259         mcq->cqe_sz     = 64;
1260         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1261         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1262         *mcq->set_ci_db = 0;
1263         *mcq->arm_db    = 0;
1264         mcq->vector     = param->eq_ix;
1265         mcq->comp       = mlx5e_completion_event;
1266         mcq->event      = mlx5e_cq_error_event;
1267         mcq->irqn       = irqn;
1268
1269         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1270                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1271
1272                 cqe->op_own = 0xf1;
1273         }
1274
1275         cq->channel = c;
1276         cq->priv = priv;
1277
1278         return 0;
1279 }
1280
1281 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1282 {
1283         mlx5_cqwq_destroy(&cq->wq_ctrl);
1284 }
1285
1286 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1287 {
1288         struct mlx5e_priv *priv = cq->priv;
1289         struct mlx5_core_dev *mdev = priv->mdev;
1290         struct mlx5_core_cq *mcq = &cq->mcq;
1291
1292         void *in;
1293         void *cqc;
1294         int inlen;
1295         unsigned int irqn_not_used;
1296         int eqn;
1297         int err;
1298
1299         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1300                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1301         in = mlx5_vzalloc(inlen);
1302         if (!in)
1303                 return -ENOMEM;
1304
1305         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1306
1307         memcpy(cqc, param->cqc, sizeof(param->cqc));
1308
1309         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1310                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1311
1312         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1313
1314         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1315         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1316         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1317         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1318                                             MLX5_ADAPTER_PAGE_SHIFT);
1319         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1320
1321         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1322
1323         kvfree(in);
1324
1325         if (err)
1326                 return err;
1327
1328         mlx5e_cq_arm(cq);
1329
1330         return 0;
1331 }
1332
1333 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1334 {
1335         struct mlx5e_priv *priv = cq->priv;
1336         struct mlx5_core_dev *mdev = priv->mdev;
1337
1338         mlx5_core_destroy_cq(mdev, &cq->mcq);
1339 }
1340
1341 static int mlx5e_open_cq(struct mlx5e_channel *c,
1342                          struct mlx5e_cq_param *param,
1343                          struct mlx5e_cq *cq,
1344                          struct mlx5e_cq_moder moderation)
1345 {
1346         int err;
1347         struct mlx5e_priv *priv = c->priv;
1348         struct mlx5_core_dev *mdev = priv->mdev;
1349
1350         err = mlx5e_create_cq(c, param, cq);
1351         if (err)
1352                 return err;
1353
1354         err = mlx5e_enable_cq(cq, param);
1355         if (err)
1356                 goto err_destroy_cq;
1357
1358         if (MLX5_CAP_GEN(mdev, cq_moderation))
1359                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1360                                                moderation.usec,
1361                                                moderation.pkts);
1362         return 0;
1363
1364 err_destroy_cq:
1365         mlx5e_destroy_cq(cq);
1366
1367         return err;
1368 }
1369
1370 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1371 {
1372         mlx5e_disable_cq(cq);
1373         mlx5e_destroy_cq(cq);
1374 }
1375
1376 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1377 {
1378         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1379 }
1380
1381 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1382                              struct mlx5e_channel_param *cparam)
1383 {
1384         struct mlx5e_priv *priv = c->priv;
1385         int err;
1386         int tc;
1387
1388         for (tc = 0; tc < c->num_tc; tc++) {
1389                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1390                                     priv->params.tx_cq_moderation);
1391                 if (err)
1392                         goto err_close_tx_cqs;
1393         }
1394
1395         return 0;
1396
1397 err_close_tx_cqs:
1398         for (tc--; tc >= 0; tc--)
1399                 mlx5e_close_cq(&c->sq[tc].cq);
1400
1401         return err;
1402 }
1403
1404 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1405 {
1406         int tc;
1407
1408         for (tc = 0; tc < c->num_tc; tc++)
1409                 mlx5e_close_cq(&c->sq[tc].cq);
1410 }
1411
1412 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1413                           struct mlx5e_channel_param *cparam)
1414 {
1415         int err;
1416         int tc;
1417
1418         for (tc = 0; tc < c->num_tc; tc++) {
1419                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1420                 if (err)
1421                         goto err_close_sqs;
1422         }
1423
1424         return 0;
1425
1426 err_close_sqs:
1427         for (tc--; tc >= 0; tc--)
1428                 mlx5e_close_sq(&c->sq[tc]);
1429
1430         return err;
1431 }
1432
1433 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1434 {
1435         int tc;
1436
1437         for (tc = 0; tc < c->num_tc; tc++)
1438                 mlx5e_close_sq(&c->sq[tc]);
1439 }
1440
1441 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1442 {
1443         int i;
1444
1445         for (i = 0; i < priv->profile->max_tc; i++)
1446                 priv->channeltc_to_txq_map[ix][i] =
1447                         ix + i * priv->params.num_channels;
1448 }
1449
1450 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1451                                 struct mlx5e_sq *sq, u32 rate)
1452 {
1453         struct mlx5e_priv *priv = netdev_priv(dev);
1454         struct mlx5_core_dev *mdev = priv->mdev;
1455         u16 rl_index = 0;
1456         int err;
1457
1458         if (rate == sq->rate_limit)
1459                 /* nothing to do */
1460                 return 0;
1461
1462         if (sq->rate_limit)
1463                 /* remove current rl index to free space to next ones */
1464                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1465
1466         sq->rate_limit = 0;
1467
1468         if (rate) {
1469                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1470                 if (err) {
1471                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1472                                    rate, err);
1473                         return err;
1474                 }
1475         }
1476
1477         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1478                               MLX5_SQC_STATE_RDY, true, rl_index);
1479         if (err) {
1480                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1481                            rate, err);
1482                 /* remove the rate from the table */
1483                 if (rate)
1484                         mlx5_rl_remove_rate(mdev, rate);
1485                 return err;
1486         }
1487
1488         sq->rate_limit = rate;
1489         return 0;
1490 }
1491
1492 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1493 {
1494         struct mlx5e_priv *priv = netdev_priv(dev);
1495         struct mlx5_core_dev *mdev = priv->mdev;
1496         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1497         int err = 0;
1498
1499         if (!mlx5_rl_is_supported(mdev)) {
1500                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1501                 return -EINVAL;
1502         }
1503
1504         /* rate is given in Mb/sec, HW config is in Kb/sec */
1505         rate = rate << 10;
1506
1507         /* Check whether rate in valid range, 0 is always valid */
1508         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1509                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1510                 return -ERANGE;
1511         }
1512
1513         mutex_lock(&priv->state_lock);
1514         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1515                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1516         if (!err)
1517                 priv->tx_rates[index] = rate;
1518         mutex_unlock(&priv->state_lock);
1519
1520         return err;
1521 }
1522
1523 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
1524 {
1525         return is_kdump_kernel() ?
1526                 MLX5E_MIN_NUM_CHANNELS :
1527                 min_t(int, mdev->priv.eq_table.num_comp_vectors,
1528                       MLX5E_MAX_NUM_CHANNELS);
1529 }
1530
1531 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1532                               struct mlx5e_channel_param *cparam,
1533                               struct mlx5e_channel **cp)
1534 {
1535         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1536         struct net_device *netdev = priv->netdev;
1537         struct mlx5e_cq_moder rx_cq_profile;
1538         int cpu = mlx5e_get_cpu(priv, ix);
1539         struct mlx5e_channel *c;
1540         struct mlx5e_sq *sq;
1541         int err;
1542         int i;
1543
1544         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1545         if (!c)
1546                 return -ENOMEM;
1547
1548         c->priv     = priv;
1549         c->ix       = ix;
1550         c->cpu      = cpu;
1551         c->pdev     = &priv->mdev->pdev->dev;
1552         c->netdev   = priv->netdev;
1553         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1554         c->num_tc   = priv->params.num_tc;
1555         c->xdp      = !!priv->xdp_prog;
1556
1557         if (priv->params.rx_am_enabled)
1558                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1559         else
1560                 rx_cq_profile = priv->params.rx_cq_moderation;
1561
1562         mlx5e_build_channeltc_to_txq_map(priv, ix);
1563
1564         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1565
1566         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1567         if (err)
1568                 goto err_napi_del;
1569
1570         err = mlx5e_open_tx_cqs(c, cparam);
1571         if (err)
1572                 goto err_close_icosq_cq;
1573
1574         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1575                             rx_cq_profile);
1576         if (err)
1577                 goto err_close_tx_cqs;
1578
1579         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1580         err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1581                                      priv->params.tx_cq_moderation) : 0;
1582         if (err)
1583                 goto err_close_rx_cq;
1584
1585         napi_enable(&c->napi);
1586
1587         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1588         if (err)
1589                 goto err_disable_napi;
1590
1591         err = mlx5e_open_sqs(c, cparam);
1592         if (err)
1593                 goto err_close_icosq;
1594
1595         for (i = 0; i < priv->params.num_tc; i++) {
1596                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1597
1598                 if (priv->tx_rates[txq_ix]) {
1599                         sq = priv->txq_to_sq_map[txq_ix];
1600                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1601                                              priv->tx_rates[txq_ix]);
1602                 }
1603         }
1604
1605         err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1606         if (err)
1607                 goto err_close_sqs;
1608
1609         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1610         if (err)
1611                 goto err_close_xdp_sq;
1612
1613         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1614         *cp = c;
1615
1616         return 0;
1617 err_close_xdp_sq:
1618         if (c->xdp)
1619                 mlx5e_close_sq(&c->xdp_sq);
1620
1621 err_close_sqs:
1622         mlx5e_close_sqs(c);
1623
1624 err_close_icosq:
1625         mlx5e_close_sq(&c->icosq);
1626
1627 err_disable_napi:
1628         napi_disable(&c->napi);
1629         if (c->xdp)
1630                 mlx5e_close_cq(&c->xdp_sq.cq);
1631
1632 err_close_rx_cq:
1633         mlx5e_close_cq(&c->rq.cq);
1634
1635 err_close_tx_cqs:
1636         mlx5e_close_tx_cqs(c);
1637
1638 err_close_icosq_cq:
1639         mlx5e_close_cq(&c->icosq.cq);
1640
1641 err_napi_del:
1642         netif_napi_del(&c->napi);
1643         kfree(c);
1644
1645         return err;
1646 }
1647
1648 static void mlx5e_close_channel(struct mlx5e_channel *c)
1649 {
1650         mlx5e_close_rq(&c->rq);
1651         if (c->xdp)
1652                 mlx5e_close_sq(&c->xdp_sq);
1653         mlx5e_close_sqs(c);
1654         mlx5e_close_sq(&c->icosq);
1655         napi_disable(&c->napi);
1656         if (c->xdp)
1657                 mlx5e_close_cq(&c->xdp_sq.cq);
1658         mlx5e_close_cq(&c->rq.cq);
1659         mlx5e_close_tx_cqs(c);
1660         mlx5e_close_cq(&c->icosq.cq);
1661         netif_napi_del(&c->napi);
1662
1663         kfree(c);
1664 }
1665
1666 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1667                                  struct mlx5e_rq_param *param)
1668 {
1669         void *rqc = param->rqc;
1670         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1671
1672         switch (priv->params.rq_wq_type) {
1673         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1674                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1675                          priv->params.mpwqe_log_num_strides - 9);
1676                 MLX5_SET(wq, wq, log_wqe_stride_size,
1677                          priv->params.mpwqe_log_stride_sz - 6);
1678                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1679                 break;
1680         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1681                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1682         }
1683
1684         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1685         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1686         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1687         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1688         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1689
1690         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1691         param->wq.linear = 1;
1692
1693         param->am_enabled = priv->params.rx_am_enabled;
1694 }
1695
1696 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1697 {
1698         void *rqc = param->rqc;
1699         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1700
1701         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1702         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1703 }
1704
1705 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1706                                         struct mlx5e_sq_param *param)
1707 {
1708         void *sqc = param->sqc;
1709         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1710
1711         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1712         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1713
1714         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1715 }
1716
1717 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1718                                  struct mlx5e_sq_param *param)
1719 {
1720         void *sqc = param->sqc;
1721         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1722
1723         mlx5e_build_sq_param_common(priv, param);
1724         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1725
1726         param->max_inline = priv->params.tx_max_inline;
1727         param->min_inline_mode = priv->params.tx_min_inline_mode;
1728         param->type = MLX5E_SQ_TXQ;
1729 }
1730
1731 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1732                                         struct mlx5e_cq_param *param)
1733 {
1734         void *cqc = param->cqc;
1735
1736         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1737 }
1738
1739 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1740                                     struct mlx5e_cq_param *param)
1741 {
1742         void *cqc = param->cqc;
1743         u8 log_cq_size;
1744
1745         switch (priv->params.rq_wq_type) {
1746         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1747                 log_cq_size = priv->params.log_rq_size +
1748                         priv->params.mpwqe_log_num_strides;
1749                 break;
1750         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1751                 log_cq_size = priv->params.log_rq_size;
1752         }
1753
1754         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1755         if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1756                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1757                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1758         }
1759
1760         mlx5e_build_common_cq_param(priv, param);
1761
1762         param->cq_period_mode = priv->params.rx_cq_period_mode;
1763 }
1764
1765 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1766                                     struct mlx5e_cq_param *param)
1767 {
1768         void *cqc = param->cqc;
1769
1770         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1771
1772         mlx5e_build_common_cq_param(priv, param);
1773
1774         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1775 }
1776
1777 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1778                                      struct mlx5e_cq_param *param,
1779                                      u8 log_wq_size)
1780 {
1781         void *cqc = param->cqc;
1782
1783         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1784
1785         mlx5e_build_common_cq_param(priv, param);
1786
1787         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1788 }
1789
1790 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1791                                     struct mlx5e_sq_param *param,
1792                                     u8 log_wq_size)
1793 {
1794         void *sqc = param->sqc;
1795         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1796
1797         mlx5e_build_sq_param_common(priv, param);
1798
1799         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1800         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1801
1802         param->type = MLX5E_SQ_ICO;
1803 }
1804
1805 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1806                                     struct mlx5e_sq_param *param)
1807 {
1808         void *sqc = param->sqc;
1809         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1810
1811         mlx5e_build_sq_param_common(priv, param);
1812         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1813
1814         param->max_inline = priv->params.tx_max_inline;
1815         param->min_inline_mode = priv->params.tx_min_inline_mode;
1816         param->type = MLX5E_SQ_XDP;
1817 }
1818
1819 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1820 {
1821         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1822
1823         mlx5e_build_rq_param(priv, &cparam->rq);
1824         mlx5e_build_sq_param(priv, &cparam->sq);
1825         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1826         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1827         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1828         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1829         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1830 }
1831
1832 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1833 {
1834         struct mlx5e_channel_param *cparam;
1835         int nch = priv->params.num_channels;
1836         int err = -ENOMEM;
1837         int i;
1838         int j;
1839
1840         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1841                                 GFP_KERNEL);
1842
1843         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1844                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1845
1846         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1847
1848         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1849                 goto err_free_txq_to_sq_map;
1850
1851         mlx5e_build_channel_param(priv, cparam);
1852
1853         for (i = 0; i < nch; i++) {
1854                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1855                 if (err)
1856                         goto err_close_channels;
1857         }
1858
1859         for (j = 0; j < nch; j++) {
1860                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1861                 if (err)
1862                         goto err_close_channels;
1863         }
1864
1865         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1866          * polling for inactive tx queues.
1867          */
1868         netif_tx_start_all_queues(priv->netdev);
1869
1870         kfree(cparam);
1871         return 0;
1872
1873 err_close_channels:
1874         for (i--; i >= 0; i--)
1875                 mlx5e_close_channel(priv->channel[i]);
1876
1877 err_free_txq_to_sq_map:
1878         kfree(priv->txq_to_sq_map);
1879         kfree(priv->channel);
1880         kfree(cparam);
1881
1882         return err;
1883 }
1884
1885 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1886 {
1887         int i;
1888
1889         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1890          * polling for inactive tx queues.
1891          */
1892         netif_tx_stop_all_queues(priv->netdev);
1893         netif_tx_disable(priv->netdev);
1894
1895         for (i = 0; i < priv->params.num_channels; i++)
1896                 mlx5e_close_channel(priv->channel[i]);
1897
1898         kfree(priv->txq_to_sq_map);
1899         kfree(priv->channel);
1900 }
1901
1902 static int mlx5e_rx_hash_fn(int hfunc)
1903 {
1904         return (hfunc == ETH_RSS_HASH_TOP) ?
1905                MLX5_RX_HASH_FN_TOEPLITZ :
1906                MLX5_RX_HASH_FN_INVERTED_XOR8;
1907 }
1908
1909 static int mlx5e_bits_invert(unsigned long a, int size)
1910 {
1911         int inv = 0;
1912         int i;
1913
1914         for (i = 0; i < size; i++)
1915                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1916
1917         return inv;
1918 }
1919
1920 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1921 {
1922         int i;
1923
1924         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1925                 int ix = i;
1926                 u32 rqn;
1927
1928                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1929                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1930
1931                 ix = priv->params.indirection_rqt[ix];
1932                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1933                                 priv->channel[ix]->rq.rqn :
1934                                 priv->drop_rq.rqn;
1935                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1936         }
1937 }
1938
1939 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1940                                       int ix)
1941 {
1942         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1943                         priv->channel[ix]->rq.rqn :
1944                         priv->drop_rq.rqn;
1945
1946         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1947 }
1948
1949 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1950                             int ix, struct mlx5e_rqt *rqt)
1951 {
1952         struct mlx5_core_dev *mdev = priv->mdev;
1953         void *rqtc;
1954         int inlen;
1955         int err;
1956         u32 *in;
1957
1958         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1959         in = mlx5_vzalloc(inlen);
1960         if (!in)
1961                 return -ENOMEM;
1962
1963         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1964
1965         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1966         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1967
1968         if (sz > 1) /* RSS */
1969                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1970         else
1971                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1972
1973         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1974         if (!err)
1975                 rqt->enabled = true;
1976
1977         kvfree(in);
1978         return err;
1979 }
1980
1981 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1982 {
1983         rqt->enabled = false;
1984         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1985 }
1986
1987 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1988 {
1989         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1990
1991         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1992 }
1993
1994 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1995 {
1996         struct mlx5e_rqt *rqt;
1997         int err;
1998         int ix;
1999
2000         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2001                 rqt = &priv->direct_tir[ix].rqt;
2002                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
2003                 if (err)
2004                         goto err_destroy_rqts;
2005         }
2006
2007         return 0;
2008
2009 err_destroy_rqts:
2010         for (ix--; ix >= 0; ix--)
2011                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2012
2013         return err;
2014 }
2015
2016 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
2017 {
2018         struct mlx5_core_dev *mdev = priv->mdev;
2019         void *rqtc;
2020         int inlen;
2021         u32 *in;
2022         int err;
2023
2024         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2025         in = mlx5_vzalloc(inlen);
2026         if (!in)
2027                 return -ENOMEM;
2028
2029         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2030
2031         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2032         if (sz > 1) /* RSS */
2033                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2034         else
2035                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2036
2037         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2038
2039         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2040
2041         kvfree(in);
2042
2043         return err;
2044 }
2045
2046 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2047 {
2048         u32 rqtn;
2049         int ix;
2050
2051         if (priv->indir_rqt.enabled) {
2052                 rqtn = priv->indir_rqt.rqtn;
2053                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2054         }
2055
2056         for (ix = 0; ix < priv->params.num_channels; ix++) {
2057                 if (!priv->direct_tir[ix].rqt.enabled)
2058                         continue;
2059                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2060                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2061         }
2062 }
2063
2064 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2065 {
2066         if (!priv->params.lro_en)
2067                 return;
2068
2069 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2070
2071         MLX5_SET(tirc, tirc, lro_enable_mask,
2072                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2073                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2074         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2075                  (priv->params.lro_wqe_sz -
2076                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2077         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
2078 }
2079
2080 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
2081                                     enum mlx5e_traffic_types tt)
2082 {
2083         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2084
2085 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2086                                  MLX5_HASH_FIELD_SEL_DST_IP)
2087
2088 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2089                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2090                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2091                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2092
2093 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2094                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2095                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2096
2097         MLX5_SET(tirc, tirc, rx_hash_fn,
2098                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2099         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2100                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2101                                              rx_hash_toeplitz_key);
2102                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2103                                                rx_hash_toeplitz_key);
2104
2105                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2106                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2107         }
2108
2109         switch (tt) {
2110         case MLX5E_TT_IPV4_TCP:
2111                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2112                          MLX5_L3_PROT_TYPE_IPV4);
2113                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2114                          MLX5_L4_PROT_TYPE_TCP);
2115                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2116                          MLX5_HASH_IP_L4PORTS);
2117                 break;
2118
2119         case MLX5E_TT_IPV6_TCP:
2120                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2121                          MLX5_L3_PROT_TYPE_IPV6);
2122                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2123                          MLX5_L4_PROT_TYPE_TCP);
2124                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2125                          MLX5_HASH_IP_L4PORTS);
2126                 break;
2127
2128         case MLX5E_TT_IPV4_UDP:
2129                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2130                          MLX5_L3_PROT_TYPE_IPV4);
2131                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2132                          MLX5_L4_PROT_TYPE_UDP);
2133                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2134                          MLX5_HASH_IP_L4PORTS);
2135                 break;
2136
2137         case MLX5E_TT_IPV6_UDP:
2138                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2139                          MLX5_L3_PROT_TYPE_IPV6);
2140                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2141                          MLX5_L4_PROT_TYPE_UDP);
2142                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2143                          MLX5_HASH_IP_L4PORTS);
2144                 break;
2145
2146         case MLX5E_TT_IPV4_IPSEC_AH:
2147                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2148                          MLX5_L3_PROT_TYPE_IPV4);
2149                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2150                          MLX5_HASH_IP_IPSEC_SPI);
2151                 break;
2152
2153         case MLX5E_TT_IPV6_IPSEC_AH:
2154                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2155                          MLX5_L3_PROT_TYPE_IPV6);
2156                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2157                          MLX5_HASH_IP_IPSEC_SPI);
2158                 break;
2159
2160         case MLX5E_TT_IPV4_IPSEC_ESP:
2161                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2162                          MLX5_L3_PROT_TYPE_IPV4);
2163                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2164                          MLX5_HASH_IP_IPSEC_SPI);
2165                 break;
2166
2167         case MLX5E_TT_IPV6_IPSEC_ESP:
2168                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2169                          MLX5_L3_PROT_TYPE_IPV6);
2170                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2171                          MLX5_HASH_IP_IPSEC_SPI);
2172                 break;
2173
2174         case MLX5E_TT_IPV4:
2175                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2176                          MLX5_L3_PROT_TYPE_IPV4);
2177                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2178                          MLX5_HASH_IP);
2179                 break;
2180
2181         case MLX5E_TT_IPV6:
2182                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2183                          MLX5_L3_PROT_TYPE_IPV6);
2184                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2185                          MLX5_HASH_IP);
2186                 break;
2187         default:
2188                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2189         }
2190 }
2191
2192 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2193 {
2194         struct mlx5_core_dev *mdev = priv->mdev;
2195
2196         void *in;
2197         void *tirc;
2198         int inlen;
2199         int err;
2200         int tt;
2201         int ix;
2202
2203         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2204         in = mlx5_vzalloc(inlen);
2205         if (!in)
2206                 return -ENOMEM;
2207
2208         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2209         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2210
2211         mlx5e_build_tir_ctx_lro(tirc, priv);
2212
2213         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2214                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2215                                            inlen);
2216                 if (err)
2217                         goto free_in;
2218         }
2219
2220         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2221                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2222                                            in, inlen);
2223                 if (err)
2224                         goto free_in;
2225         }
2226
2227 free_in:
2228         kvfree(in);
2229
2230         return err;
2231 }
2232
2233 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2234 {
2235         struct mlx5_core_dev *mdev = priv->mdev;
2236         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2237         int err;
2238
2239         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2240         if (err)
2241                 return err;
2242
2243         /* Update vport context MTU */
2244         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2245         return 0;
2246 }
2247
2248 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2249 {
2250         struct mlx5_core_dev *mdev = priv->mdev;
2251         u16 hw_mtu = 0;
2252         int err;
2253
2254         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2255         if (err || !hw_mtu) /* fallback to port oper mtu */
2256                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2257
2258         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2259 }
2260
2261 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2262 {
2263         struct mlx5e_priv *priv = netdev_priv(netdev);
2264         u16 mtu;
2265         int err;
2266
2267         err = mlx5e_set_mtu(priv, netdev->mtu);
2268         if (err)
2269                 return err;
2270
2271         mlx5e_query_mtu(priv, &mtu);
2272         if (mtu != netdev->mtu)
2273                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2274                             __func__, mtu, netdev->mtu);
2275
2276         netdev->mtu = mtu;
2277         return 0;
2278 }
2279
2280 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2281 {
2282         struct mlx5e_priv *priv = netdev_priv(netdev);
2283         int nch = priv->params.num_channels;
2284         int ntc = priv->params.num_tc;
2285         int tc;
2286
2287         netdev_reset_tc(netdev);
2288
2289         if (ntc == 1)
2290                 return;
2291
2292         netdev_set_num_tc(netdev, ntc);
2293
2294         /* Map netdev TCs to offset 0
2295          * We have our own UP to TXQ mapping for QoS
2296          */
2297         for (tc = 0; tc < ntc; tc++)
2298                 netdev_set_tc_queue(netdev, tc, nch, 0);
2299 }
2300
2301 int mlx5e_open_locked(struct net_device *netdev)
2302 {
2303         struct mlx5e_priv *priv = netdev_priv(netdev);
2304         struct mlx5_core_dev *mdev = priv->mdev;
2305         int num_txqs;
2306         int err;
2307
2308         set_bit(MLX5E_STATE_OPENED, &priv->state);
2309
2310         mlx5e_netdev_set_tcs(netdev);
2311
2312         num_txqs = priv->params.num_channels * priv->params.num_tc;
2313         netif_set_real_num_tx_queues(netdev, num_txqs);
2314         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2315
2316         err = mlx5e_open_channels(priv);
2317         if (err) {
2318                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2319                            __func__, err);
2320                 goto err_clear_state_opened_flag;
2321         }
2322
2323         err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
2324         if (err) {
2325                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2326                            __func__, err);
2327                 goto err_close_channels;
2328         }
2329
2330         mlx5e_redirect_rqts(priv);
2331         mlx5e_update_carrier(priv);
2332         mlx5e_timestamp_init(priv);
2333 #ifdef CONFIG_RFS_ACCEL
2334         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2335 #endif
2336         if (priv->profile->update_stats)
2337                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2338
2339         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2340                 err = mlx5e_add_sqs_fwd_rules(priv);
2341                 if (err)
2342                         goto err_close_channels;
2343         }
2344         return 0;
2345
2346 err_close_channels:
2347         mlx5e_close_channels(priv);
2348 err_clear_state_opened_flag:
2349         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2350         return err;
2351 }
2352
2353 int mlx5e_open(struct net_device *netdev)
2354 {
2355         struct mlx5e_priv *priv = netdev_priv(netdev);
2356         int err;
2357
2358         mutex_lock(&priv->state_lock);
2359         err = mlx5e_open_locked(netdev);
2360         mutex_unlock(&priv->state_lock);
2361
2362         return err;
2363 }
2364
2365 int mlx5e_close_locked(struct net_device *netdev)
2366 {
2367         struct mlx5e_priv *priv = netdev_priv(netdev);
2368         struct mlx5_core_dev *mdev = priv->mdev;
2369
2370         /* May already be CLOSED in case a previous configuration operation
2371          * (e.g RX/TX queue size change) that involves close&open failed.
2372          */
2373         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2374                 return 0;
2375
2376         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2377
2378         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2379                 mlx5e_remove_sqs_fwd_rules(priv);
2380
2381         mlx5e_timestamp_cleanup(priv);
2382         netif_carrier_off(priv->netdev);
2383         mlx5e_redirect_rqts(priv);
2384         mlx5e_close_channels(priv);
2385
2386         return 0;
2387 }
2388
2389 int mlx5e_close(struct net_device *netdev)
2390 {
2391         struct mlx5e_priv *priv = netdev_priv(netdev);
2392         int err;
2393
2394         if (!netif_device_present(netdev))
2395                 return -ENODEV;
2396
2397         mutex_lock(&priv->state_lock);
2398         err = mlx5e_close_locked(netdev);
2399         mutex_unlock(&priv->state_lock);
2400
2401         return err;
2402 }
2403
2404 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2405                                 struct mlx5e_rq *rq,
2406                                 struct mlx5e_rq_param *param)
2407 {
2408         struct mlx5_core_dev *mdev = priv->mdev;
2409         void *rqc = param->rqc;
2410         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2411         int err;
2412
2413         param->wq.db_numa_node = param->wq.buf_numa_node;
2414
2415         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2416                                 &rq->wq_ctrl);
2417         if (err)
2418                 return err;
2419
2420         rq->priv = priv;
2421
2422         return 0;
2423 }
2424
2425 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2426                                 struct mlx5e_cq *cq,
2427                                 struct mlx5e_cq_param *param)
2428 {
2429         struct mlx5_core_dev *mdev = priv->mdev;
2430         struct mlx5_core_cq *mcq = &cq->mcq;
2431         int eqn_not_used;
2432         unsigned int irqn;
2433         int err;
2434
2435         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2436                                &cq->wq_ctrl);
2437         if (err)
2438                 return err;
2439
2440         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2441
2442         mcq->cqe_sz     = 64;
2443         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2444         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2445         *mcq->set_ci_db = 0;
2446         *mcq->arm_db    = 0;
2447         mcq->vector     = param->eq_ix;
2448         mcq->comp       = mlx5e_completion_event;
2449         mcq->event      = mlx5e_cq_error_event;
2450         mcq->irqn       = irqn;
2451
2452         cq->priv = priv;
2453
2454         return 0;
2455 }
2456
2457 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2458 {
2459         struct mlx5e_cq_param cq_param;
2460         struct mlx5e_rq_param rq_param;
2461         struct mlx5e_rq *rq = &priv->drop_rq;
2462         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2463         int err;
2464
2465         memset(&cq_param, 0, sizeof(cq_param));
2466         memset(&rq_param, 0, sizeof(rq_param));
2467         mlx5e_build_drop_rq_param(&rq_param);
2468
2469         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2470         if (err)
2471                 return err;
2472
2473         err = mlx5e_enable_cq(cq, &cq_param);
2474         if (err)
2475                 goto err_destroy_cq;
2476
2477         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2478         if (err)
2479                 goto err_disable_cq;
2480
2481         err = mlx5e_enable_rq(rq, &rq_param);
2482         if (err)
2483                 goto err_destroy_rq;
2484
2485         return 0;
2486
2487 err_destroy_rq:
2488         mlx5e_destroy_rq(&priv->drop_rq);
2489
2490 err_disable_cq:
2491         mlx5e_disable_cq(&priv->drop_rq.cq);
2492
2493 err_destroy_cq:
2494         mlx5e_destroy_cq(&priv->drop_rq.cq);
2495
2496         return err;
2497 }
2498
2499 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2500 {
2501         mlx5e_disable_rq(&priv->drop_rq);
2502         mlx5e_destroy_rq(&priv->drop_rq);
2503         mlx5e_disable_cq(&priv->drop_rq.cq);
2504         mlx5e_destroy_cq(&priv->drop_rq.cq);
2505 }
2506
2507 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2508 {
2509         struct mlx5_core_dev *mdev = priv->mdev;
2510         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2511         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2512
2513         MLX5_SET(tisc, tisc, prio, tc << 1);
2514         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2515
2516         if (mlx5_lag_is_lacp_owner(mdev))
2517                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2518
2519         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2520 }
2521
2522 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2523 {
2524         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2525 }
2526
2527 int mlx5e_create_tises(struct mlx5e_priv *priv)
2528 {
2529         int err;
2530         int tc;
2531
2532         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2533                 err = mlx5e_create_tis(priv, tc);
2534                 if (err)
2535                         goto err_close_tises;
2536         }
2537
2538         return 0;
2539
2540 err_close_tises:
2541         for (tc--; tc >= 0; tc--)
2542                 mlx5e_destroy_tis(priv, tc);
2543
2544         return err;
2545 }
2546
2547 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2548 {
2549         int tc;
2550
2551         for (tc = 0; tc < priv->profile->max_tc; tc++)
2552                 mlx5e_destroy_tis(priv, tc);
2553 }
2554
2555 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2556                                       enum mlx5e_traffic_types tt)
2557 {
2558         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2559
2560         mlx5e_build_tir_ctx_lro(tirc, priv);
2561
2562         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2563         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2564         mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
2565 }
2566
2567 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2568                                        u32 rqtn)
2569 {
2570         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2571
2572         mlx5e_build_tir_ctx_lro(tirc, priv);
2573
2574         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2575         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2576         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2577 }
2578
2579 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2580 {
2581         struct mlx5e_tir *tir;
2582         void *tirc;
2583         int inlen;
2584         int err;
2585         u32 *in;
2586         int tt;
2587
2588         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2589         in = mlx5_vzalloc(inlen);
2590         if (!in)
2591                 return -ENOMEM;
2592
2593         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2594                 memset(in, 0, inlen);
2595                 tir = &priv->indir_tir[tt];
2596                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2597                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2598                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2599                 if (err)
2600                         goto err_destroy_tirs;
2601         }
2602
2603         kvfree(in);
2604
2605         return 0;
2606
2607 err_destroy_tirs:
2608         for (tt--; tt >= 0; tt--)
2609                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2610
2611         kvfree(in);
2612
2613         return err;
2614 }
2615
2616 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2617 {
2618         int nch = priv->profile->max_nch(priv->mdev);
2619         struct mlx5e_tir *tir;
2620         void *tirc;
2621         int inlen;
2622         int err;
2623         u32 *in;
2624         int ix;
2625
2626         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2627         in = mlx5_vzalloc(inlen);
2628         if (!in)
2629                 return -ENOMEM;
2630
2631         for (ix = 0; ix < nch; ix++) {
2632                 memset(in, 0, inlen);
2633                 tir = &priv->direct_tir[ix];
2634                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2635                 mlx5e_build_direct_tir_ctx(priv, tirc,
2636                                            priv->direct_tir[ix].rqt.rqtn);
2637                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2638                 if (err)
2639                         goto err_destroy_ch_tirs;
2640         }
2641
2642         kvfree(in);
2643
2644         return 0;
2645
2646 err_destroy_ch_tirs:
2647         for (ix--; ix >= 0; ix--)
2648                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2649
2650         kvfree(in);
2651
2652         return err;
2653 }
2654
2655 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2656 {
2657         int i;
2658
2659         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2660                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2661 }
2662
2663 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2664 {
2665         int nch = priv->profile->max_nch(priv->mdev);
2666         int i;
2667
2668         for (i = 0; i < nch; i++)
2669                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2670 }
2671
2672 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2673 {
2674         int err = 0;
2675         int i;
2676
2677         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2678                 return 0;
2679
2680         for (i = 0; i < priv->params.num_channels; i++) {
2681                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2682                 if (err)
2683                         return err;
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2690 {
2691         struct mlx5e_priv *priv = netdev_priv(netdev);
2692         bool was_opened;
2693         int err = 0;
2694
2695         if (tc && tc != MLX5E_MAX_NUM_TC)
2696                 return -EINVAL;
2697
2698         mutex_lock(&priv->state_lock);
2699
2700         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2701         if (was_opened)
2702                 mlx5e_close_locked(priv->netdev);
2703
2704         priv->params.num_tc = tc ? tc : 1;
2705
2706         if (was_opened)
2707                 err = mlx5e_open_locked(priv->netdev);
2708
2709         mutex_unlock(&priv->state_lock);
2710
2711         return err;
2712 }
2713
2714 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2715                               __be16 proto, struct tc_to_netdev *tc)
2716 {
2717         struct mlx5e_priv *priv = netdev_priv(dev);
2718
2719         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2720                 goto mqprio;
2721
2722         switch (tc->type) {
2723         case TC_SETUP_CLSFLOWER:
2724                 switch (tc->cls_flower->command) {
2725                 case TC_CLSFLOWER_REPLACE:
2726                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2727                 case TC_CLSFLOWER_DESTROY:
2728                         return mlx5e_delete_flower(priv, tc->cls_flower);
2729                 case TC_CLSFLOWER_STATS:
2730                         return mlx5e_stats_flower(priv, tc->cls_flower);
2731                 }
2732         default:
2733                 return -EOPNOTSUPP;
2734         }
2735
2736 mqprio:
2737         if (tc->type != TC_SETUP_MQPRIO)
2738                 return -EINVAL;
2739
2740         return mlx5e_setup_tc(dev, tc->tc);
2741 }
2742
2743 static void
2744 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2745 {
2746         struct mlx5e_priv *priv = netdev_priv(dev);
2747         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2748         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2749         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2750
2751         if (mlx5e_is_uplink_rep(priv)) {
2752                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2753                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
2754                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2755                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2756         } else {
2757                 stats->rx_packets = sstats->rx_packets;
2758                 stats->rx_bytes   = sstats->rx_bytes;
2759                 stats->tx_packets = sstats->tx_packets;
2760                 stats->tx_bytes   = sstats->tx_bytes;
2761                 stats->tx_dropped = sstats->tx_queue_dropped;
2762         }
2763
2764         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2765
2766         stats->rx_length_errors =
2767                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2768                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2769                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2770         stats->rx_crc_errors =
2771                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2772         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2773         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2774         stats->tx_carrier_errors =
2775                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2776         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2777                            stats->rx_frame_errors;
2778         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2779
2780         /* vport multicast also counts packets that are dropped due to steering
2781          * or rx out of buffer
2782          */
2783         stats->multicast =
2784                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2785
2786 }
2787
2788 static void mlx5e_set_rx_mode(struct net_device *dev)
2789 {
2790         struct mlx5e_priv *priv = netdev_priv(dev);
2791
2792         queue_work(priv->wq, &priv->set_rx_mode_work);
2793 }
2794
2795 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2796 {
2797         struct mlx5e_priv *priv = netdev_priv(netdev);
2798         struct sockaddr *saddr = addr;
2799
2800         if (!is_valid_ether_addr(saddr->sa_data))
2801                 return -EADDRNOTAVAIL;
2802
2803         netif_addr_lock_bh(netdev);
2804         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2805         netif_addr_unlock_bh(netdev);
2806
2807         queue_work(priv->wq, &priv->set_rx_mode_work);
2808
2809         return 0;
2810 }
2811
2812 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2813         do {                                            \
2814                 if (enable)                             \
2815                         netdev->features |= feature;    \
2816                 else                                    \
2817                         netdev->features &= ~feature;   \
2818         } while (0)
2819
2820 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2821
2822 static int set_feature_lro(struct net_device *netdev, bool enable)
2823 {
2824         struct mlx5e_priv *priv = netdev_priv(netdev);
2825         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2826         int err;
2827
2828         mutex_lock(&priv->state_lock);
2829
2830         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2831                 mlx5e_close_locked(priv->netdev);
2832
2833         priv->params.lro_en = enable;
2834         err = mlx5e_modify_tirs_lro(priv);
2835         if (err) {
2836                 netdev_err(netdev, "lro modify failed, %d\n", err);
2837                 priv->params.lro_en = !enable;
2838         }
2839
2840         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2841                 mlx5e_open_locked(priv->netdev);
2842
2843         mutex_unlock(&priv->state_lock);
2844
2845         return err;
2846 }
2847
2848 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2849 {
2850         struct mlx5e_priv *priv = netdev_priv(netdev);
2851
2852         if (enable)
2853                 mlx5e_enable_vlan_filter(priv);
2854         else
2855                 mlx5e_disable_vlan_filter(priv);
2856
2857         return 0;
2858 }
2859
2860 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2861 {
2862         struct mlx5e_priv *priv = netdev_priv(netdev);
2863
2864         if (!enable && mlx5e_tc_num_filters(priv)) {
2865                 netdev_err(netdev,
2866                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2867                 return -EINVAL;
2868         }
2869
2870         return 0;
2871 }
2872
2873 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2874 {
2875         struct mlx5e_priv *priv = netdev_priv(netdev);
2876         struct mlx5_core_dev *mdev = priv->mdev;
2877
2878         return mlx5_set_port_fcs(mdev, !enable);
2879 }
2880
2881 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2882 {
2883         struct mlx5e_priv *priv = netdev_priv(netdev);
2884         int err;
2885
2886         mutex_lock(&priv->state_lock);
2887
2888         priv->params.vlan_strip_disable = !enable;
2889         err = mlx5e_modify_rqs_vsd(priv, !enable);
2890         if (err)
2891                 priv->params.vlan_strip_disable = enable;
2892
2893         mutex_unlock(&priv->state_lock);
2894
2895         return err;
2896 }
2897
2898 #ifdef CONFIG_RFS_ACCEL
2899 static int set_feature_arfs(struct net_device *netdev, bool enable)
2900 {
2901         struct mlx5e_priv *priv = netdev_priv(netdev);
2902         int err;
2903
2904         if (enable)
2905                 err = mlx5e_arfs_enable(priv);
2906         else
2907                 err = mlx5e_arfs_disable(priv);
2908
2909         return err;
2910 }
2911 #endif
2912
2913 static int mlx5e_handle_feature(struct net_device *netdev,
2914                                 netdev_features_t wanted_features,
2915                                 netdev_features_t feature,
2916                                 mlx5e_feature_handler feature_handler)
2917 {
2918         netdev_features_t changes = wanted_features ^ netdev->features;
2919         bool enable = !!(wanted_features & feature);
2920         int err;
2921
2922         if (!(changes & feature))
2923                 return 0;
2924
2925         err = feature_handler(netdev, enable);
2926         if (err) {
2927                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2928                            enable ? "Enable" : "Disable", feature, err);
2929                 return err;
2930         }
2931
2932         MLX5E_SET_FEATURE(netdev, feature, enable);
2933         return 0;
2934 }
2935
2936 static int mlx5e_set_features(struct net_device *netdev,
2937                               netdev_features_t features)
2938 {
2939         int err;
2940
2941         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2942                                     set_feature_lro);
2943         err |= mlx5e_handle_feature(netdev, features,
2944                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2945                                     set_feature_vlan_filter);
2946         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2947                                     set_feature_tc_num_filters);
2948         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2949                                     set_feature_rx_all);
2950         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2951                                     set_feature_rx_vlan);
2952 #ifdef CONFIG_RFS_ACCEL
2953         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2954                                     set_feature_arfs);
2955 #endif
2956
2957         return err ? -EINVAL : 0;
2958 }
2959
2960 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2961 {
2962         struct mlx5e_priv *priv = netdev_priv(netdev);
2963         bool was_opened;
2964         int err = 0;
2965         bool reset;
2966
2967         mutex_lock(&priv->state_lock);
2968
2969         reset = !priv->params.lro_en &&
2970                 (priv->params.rq_wq_type !=
2971                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2972
2973         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2974         if (was_opened && reset)
2975                 mlx5e_close_locked(netdev);
2976
2977         netdev->mtu = new_mtu;
2978         mlx5e_set_dev_port_mtu(netdev);
2979
2980         if (was_opened && reset)
2981                 err = mlx5e_open_locked(netdev);
2982
2983         mutex_unlock(&priv->state_lock);
2984
2985         return err;
2986 }
2987
2988 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2989 {
2990         switch (cmd) {
2991         case SIOCSHWTSTAMP:
2992                 return mlx5e_hwstamp_set(dev, ifr);
2993         case SIOCGHWTSTAMP:
2994                 return mlx5e_hwstamp_get(dev, ifr);
2995         default:
2996                 return -EOPNOTSUPP;
2997         }
2998 }
2999
3000 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3001 {
3002         struct mlx5e_priv *priv = netdev_priv(dev);
3003         struct mlx5_core_dev *mdev = priv->mdev;
3004
3005         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3006 }
3007
3008 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3009                              __be16 vlan_proto)
3010 {
3011         struct mlx5e_priv *priv = netdev_priv(dev);
3012         struct mlx5_core_dev *mdev = priv->mdev;
3013
3014         if (vlan_proto != htons(ETH_P_8021Q))
3015                 return -EPROTONOSUPPORT;
3016
3017         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3018                                            vlan, qos);
3019 }
3020
3021 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3022 {
3023         struct mlx5e_priv *priv = netdev_priv(dev);
3024         struct mlx5_core_dev *mdev = priv->mdev;
3025
3026         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3027 }
3028
3029 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3030 {
3031         struct mlx5e_priv *priv = netdev_priv(dev);
3032         struct mlx5_core_dev *mdev = priv->mdev;
3033
3034         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3035 }
3036
3037 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3038                              int max_tx_rate)
3039 {
3040         struct mlx5e_priv *priv = netdev_priv(dev);
3041         struct mlx5_core_dev *mdev = priv->mdev;
3042
3043         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3044                                            max_tx_rate, min_tx_rate);
3045 }
3046
3047 static int mlx5_vport_link2ifla(u8 esw_link)
3048 {
3049         switch (esw_link) {
3050         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3051                 return IFLA_VF_LINK_STATE_DISABLE;
3052         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3053                 return IFLA_VF_LINK_STATE_ENABLE;
3054         }
3055         return IFLA_VF_LINK_STATE_AUTO;
3056 }
3057
3058 static int mlx5_ifla_link2vport(u8 ifla_link)
3059 {
3060         switch (ifla_link) {
3061         case IFLA_VF_LINK_STATE_DISABLE:
3062                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3063         case IFLA_VF_LINK_STATE_ENABLE:
3064                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3065         }
3066         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3067 }
3068
3069 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3070                                    int link_state)
3071 {
3072         struct mlx5e_priv *priv = netdev_priv(dev);
3073         struct mlx5_core_dev *mdev = priv->mdev;
3074
3075         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3076                                             mlx5_ifla_link2vport(link_state));
3077 }
3078
3079 static int mlx5e_get_vf_config(struct net_device *dev,
3080                                int vf, struct ifla_vf_info *ivi)
3081 {
3082         struct mlx5e_priv *priv = netdev_priv(dev);
3083         struct mlx5_core_dev *mdev = priv->mdev;
3084         int err;
3085
3086         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3087         if (err)
3088                 return err;
3089         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3090         return 0;
3091 }
3092
3093 static int mlx5e_get_vf_stats(struct net_device *dev,
3094                               int vf, struct ifla_vf_stats *vf_stats)
3095 {
3096         struct mlx5e_priv *priv = netdev_priv(dev);
3097         struct mlx5_core_dev *mdev = priv->mdev;
3098
3099         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3100                                             vf_stats);
3101 }
3102
3103 void mlx5e_add_vxlan_port(struct net_device *netdev,
3104                           struct udp_tunnel_info *ti)
3105 {
3106         struct mlx5e_priv *priv = netdev_priv(netdev);
3107
3108         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3109                 return;
3110
3111         if (!mlx5e_vxlan_allowed(priv->mdev))
3112                 return;
3113
3114         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3115 }
3116
3117 void mlx5e_del_vxlan_port(struct net_device *netdev,
3118                           struct udp_tunnel_info *ti)
3119 {
3120         struct mlx5e_priv *priv = netdev_priv(netdev);
3121
3122         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3123                 return;
3124
3125         if (!mlx5e_vxlan_allowed(priv->mdev))
3126                 return;
3127
3128         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3129 }
3130
3131 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3132                                                     struct sk_buff *skb,
3133                                                     netdev_features_t features)
3134 {
3135         struct udphdr *udph;
3136         u16 proto;
3137         u16 port = 0;
3138
3139         switch (vlan_get_protocol(skb)) {
3140         case htons(ETH_P_IP):
3141                 proto = ip_hdr(skb)->protocol;
3142                 break;
3143         case htons(ETH_P_IPV6):
3144                 proto = ipv6_hdr(skb)->nexthdr;
3145                 break;
3146         default:
3147                 goto out;
3148         }
3149
3150         if (proto == IPPROTO_UDP) {
3151                 udph = udp_hdr(skb);
3152                 port = be16_to_cpu(udph->dest);
3153         }
3154
3155         /* Verify if UDP port is being offloaded by HW */
3156         if (port && mlx5e_vxlan_lookup_port(priv, port))
3157                 return features;
3158
3159 out:
3160         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3161         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3162 }
3163
3164 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3165                                               struct net_device *netdev,
3166                                               netdev_features_t features)
3167 {
3168         struct mlx5e_priv *priv = netdev_priv(netdev);
3169
3170         features = vlan_features_check(skb, features);
3171         features = vxlan_features_check(skb, features);
3172
3173         /* Validate if the tunneled packet is being offloaded by HW */
3174         if (skb->encapsulation &&
3175             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3176                 return mlx5e_vxlan_features_check(priv, skb, features);
3177
3178         return features;
3179 }
3180
3181 static void mlx5e_tx_timeout(struct net_device *dev)
3182 {
3183         struct mlx5e_priv *priv = netdev_priv(dev);
3184         bool sched_work = false;
3185         int i;
3186
3187         netdev_err(dev, "TX timeout detected\n");
3188
3189         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3190                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3191
3192                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3193                         continue;
3194                 sched_work = true;
3195                 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3196                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3197                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3198         }
3199
3200         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3201                 schedule_work(&priv->tx_timeout_work);
3202 }
3203
3204 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3205 {
3206         struct mlx5e_priv *priv = netdev_priv(netdev);
3207         struct bpf_prog *old_prog;
3208         int err = 0;
3209         bool reset, was_opened;
3210         int i;
3211
3212         mutex_lock(&priv->state_lock);
3213
3214         if ((netdev->features & NETIF_F_LRO) && prog) {
3215                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3216                 err = -EINVAL;
3217                 goto unlock;
3218         }
3219
3220         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3221         /* no need for full reset when exchanging programs */
3222         reset = (!priv->xdp_prog || !prog);
3223
3224         if (was_opened && reset)
3225                 mlx5e_close_locked(netdev);
3226         if (was_opened && !reset) {
3227                 /* num_channels is invariant here, so we can take the
3228                  * batched reference right upfront.
3229                  */
3230                 prog = bpf_prog_add(prog, priv->params.num_channels);
3231                 if (IS_ERR(prog)) {
3232                         err = PTR_ERR(prog);
3233                         goto unlock;
3234                 }
3235         }
3236
3237         /* exchange programs, extra prog reference we got from caller
3238          * as long as we don't fail from this point onwards.
3239          */
3240         old_prog = xchg(&priv->xdp_prog, prog);
3241         if (old_prog)
3242                 bpf_prog_put(old_prog);
3243
3244         if (reset) /* change RQ type according to priv->xdp_prog */
3245                 mlx5e_set_rq_priv_params(priv);
3246
3247         if (was_opened && reset)
3248                 mlx5e_open_locked(netdev);
3249
3250         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3251                 goto unlock;
3252
3253         /* exchanging programs w/o reset, we update ref counts on behalf
3254          * of the channels RQs here.
3255          */
3256         for (i = 0; i < priv->params.num_channels; i++) {
3257                 struct mlx5e_channel *c = priv->channel[i];
3258
3259                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3260                 napi_synchronize(&c->napi);
3261                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3262
3263                 old_prog = xchg(&c->rq.xdp_prog, prog);
3264
3265                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3266                 /* napi_schedule in case we have missed anything */
3267                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3268                 napi_schedule(&c->napi);
3269
3270                 if (old_prog)
3271                         bpf_prog_put(old_prog);
3272         }
3273
3274 unlock:
3275         mutex_unlock(&priv->state_lock);
3276         return err;
3277 }
3278
3279 static bool mlx5e_xdp_attached(struct net_device *dev)
3280 {
3281         struct mlx5e_priv *priv = netdev_priv(dev);
3282
3283         return !!priv->xdp_prog;
3284 }
3285
3286 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3287 {
3288         switch (xdp->command) {
3289         case XDP_SETUP_PROG:
3290                 return mlx5e_xdp_set(dev, xdp->prog);
3291         case XDP_QUERY_PROG:
3292                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3293                 return 0;
3294         default:
3295                 return -EINVAL;
3296         }
3297 }
3298
3299 #ifdef CONFIG_NET_POLL_CONTROLLER
3300 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3301  * reenabling interrupts.
3302  */
3303 static void mlx5e_netpoll(struct net_device *dev)
3304 {
3305         struct mlx5e_priv *priv = netdev_priv(dev);
3306         int i;
3307
3308         for (i = 0; i < priv->params.num_channels; i++)
3309                 napi_schedule(&priv->channel[i]->napi);
3310 }
3311 #endif
3312
3313 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3314         .ndo_open                = mlx5e_open,
3315         .ndo_stop                = mlx5e_close,
3316         .ndo_start_xmit          = mlx5e_xmit,
3317         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3318         .ndo_select_queue        = mlx5e_select_queue,
3319         .ndo_get_stats64         = mlx5e_get_stats,
3320         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3321         .ndo_set_mac_address     = mlx5e_set_mac,
3322         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3323         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3324         .ndo_set_features        = mlx5e_set_features,
3325         .ndo_change_mtu          = mlx5e_change_mtu,
3326         .ndo_do_ioctl            = mlx5e_ioctl,
3327         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3328 #ifdef CONFIG_RFS_ACCEL
3329         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3330 #endif
3331         .ndo_tx_timeout          = mlx5e_tx_timeout,
3332         .ndo_xdp                 = mlx5e_xdp,
3333 #ifdef CONFIG_NET_POLL_CONTROLLER
3334         .ndo_poll_controller     = mlx5e_netpoll,
3335 #endif
3336 };
3337
3338 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3339         .ndo_open                = mlx5e_open,
3340         .ndo_stop                = mlx5e_close,
3341         .ndo_start_xmit          = mlx5e_xmit,
3342         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3343         .ndo_select_queue        = mlx5e_select_queue,
3344         .ndo_get_stats64         = mlx5e_get_stats,
3345         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3346         .ndo_set_mac_address     = mlx5e_set_mac,
3347         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3348         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3349         .ndo_set_features        = mlx5e_set_features,
3350         .ndo_change_mtu          = mlx5e_change_mtu,
3351         .ndo_do_ioctl            = mlx5e_ioctl,
3352         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3353         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3354         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3355         .ndo_features_check      = mlx5e_features_check,
3356 #ifdef CONFIG_RFS_ACCEL
3357         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3358 #endif
3359         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3360         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3361         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3362         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3363         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
3364         .ndo_get_vf_config       = mlx5e_get_vf_config,
3365         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3366         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3367         .ndo_tx_timeout          = mlx5e_tx_timeout,
3368         .ndo_xdp                 = mlx5e_xdp,
3369 #ifdef CONFIG_NET_POLL_CONTROLLER
3370         .ndo_poll_controller     = mlx5e_netpoll,
3371 #endif
3372         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
3373         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
3374 };
3375
3376 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3377 {
3378         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3379                 return -EOPNOTSUPP;
3380         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3381             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3382             !MLX5_CAP_ETH(mdev, csum_cap) ||
3383             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3384             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3385             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3386             MLX5_CAP_FLOWTABLE(mdev,
3387                                flow_table_properties_nic_receive.max_ft_level)
3388                                < 3) {
3389                 mlx5_core_warn(mdev,
3390                                "Not creating net device, some required device capabilities are missing\n");
3391                 return -EOPNOTSUPP;
3392         }
3393         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3394                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3395         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3396                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3397
3398         return 0;
3399 }
3400
3401 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3402 {
3403         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3404
3405         return bf_buf_size -
3406                sizeof(struct mlx5e_tx_wqe) +
3407                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3408 }
3409
3410 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3411                                    u32 *indirection_rqt, int len,
3412                                    int num_channels)
3413 {
3414         int node = mdev->priv.numa_node;
3415         int node_num_of_cores;
3416         int i;
3417
3418         if (node == -1)
3419                 node = first_online_node;
3420
3421         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3422
3423         if (node_num_of_cores)
3424                 num_channels = min_t(int, num_channels, node_num_of_cores);
3425
3426         for (i = 0; i < len; i++)
3427                 indirection_rqt[i] = i % num_channels;
3428 }
3429
3430 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3431 {
3432         enum pcie_link_width width;
3433         enum pci_bus_speed speed;
3434         int err = 0;
3435
3436         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3437         if (err)
3438                 return err;
3439
3440         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3441                 return -EINVAL;
3442
3443         switch (speed) {
3444         case PCIE_SPEED_2_5GT:
3445                 *pci_bw = 2500 * width;
3446                 break;
3447         case PCIE_SPEED_5_0GT:
3448                 *pci_bw = 5000 * width;
3449                 break;
3450         case PCIE_SPEED_8_0GT:
3451                 *pci_bw = 8000 * width;
3452                 break;
3453         default:
3454                 return -EINVAL;
3455         }
3456
3457         return 0;
3458 }
3459
3460 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3461 {
3462         return (link_speed && pci_bw &&
3463                 (pci_bw < 40000) && (pci_bw < link_speed));
3464 }
3465
3466 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3467 {
3468         params->rx_cq_period_mode = cq_period_mode;
3469
3470         params->rx_cq_moderation.pkts =
3471                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3472         params->rx_cq_moderation.usec =
3473                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3474
3475         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3476                 params->rx_cq_moderation.usec =
3477                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3478 }
3479
3480 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3481 {
3482         int i;
3483
3484         /* The supported periods are organized in ascending order */
3485         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3486                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3487                         break;
3488
3489         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3490 }
3491
3492 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3493                                         struct net_device *netdev,
3494                                         const struct mlx5e_profile *profile,
3495                                         void *ppriv)
3496 {
3497         struct mlx5e_priv *priv = netdev_priv(netdev);
3498         u32 link_speed = 0;
3499         u32 pci_bw = 0;
3500         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3501                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3502                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3503
3504         priv->mdev                         = mdev;
3505         priv->netdev                       = netdev;
3506         priv->params.num_channels          = profile->max_nch(mdev);
3507         priv->profile                      = profile;
3508         priv->ppriv                        = ppriv;
3509
3510         priv->params.lro_timeout =
3511                 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3512
3513         priv->params.log_sq_size = is_kdump_kernel() ?
3514                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3515                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3516
3517         /* set CQE compression */
3518         priv->params.rx_cqe_compress_def = false;
3519         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3520             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3521                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3522                 mlx5e_get_pci_bw(mdev, &pci_bw);
3523                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3524                               link_speed, pci_bw);
3525                 priv->params.rx_cqe_compress_def =
3526                         cqe_compress_heuristic(link_speed, pci_bw);
3527         }
3528
3529         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS,
3530                         priv->params.rx_cqe_compress_def);
3531
3532         mlx5e_set_rq_priv_params(priv);
3533         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3534                 priv->params.lro_en = true;
3535
3536         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3537         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3538
3539         priv->params.tx_cq_moderation.usec =
3540                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3541         priv->params.tx_cq_moderation.pkts =
3542                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3543         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3544         mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3545         if (priv->params.tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3546             !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3547                 priv->params.tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3548
3549         priv->params.num_tc                = 1;
3550         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3551
3552         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3553                             sizeof(priv->params.toeplitz_hash_key));
3554
3555         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3556                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3557
3558         /* Initialize pflags */
3559         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3560                         priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3561
3562         mutex_init(&priv->state_lock);
3563
3564         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3565         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3566         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3567         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3568 }
3569
3570 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3571 {
3572         struct mlx5e_priv *priv = netdev_priv(netdev);
3573
3574         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3575         if (is_zero_ether_addr(netdev->dev_addr) &&
3576             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3577                 eth_hw_addr_random(netdev);
3578                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3579         }
3580 }
3581
3582 static const struct switchdev_ops mlx5e_switchdev_ops = {
3583         .switchdev_port_attr_get        = mlx5e_attr_get,
3584 };
3585
3586 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3587 {
3588         struct mlx5e_priv *priv = netdev_priv(netdev);
3589         struct mlx5_core_dev *mdev = priv->mdev;
3590         bool fcs_supported;
3591         bool fcs_enabled;
3592
3593         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3594
3595         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3596                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3597 #ifdef CONFIG_MLX5_CORE_EN_DCB
3598                 if (MLX5_CAP_GEN(mdev, qos))
3599                         netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3600 #endif
3601         } else {
3602                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3603         }
3604
3605         netdev->watchdog_timeo    = 15 * HZ;
3606
3607         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3608
3609         netdev->vlan_features    |= NETIF_F_SG;
3610         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3611         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3612         netdev->vlan_features    |= NETIF_F_GRO;
3613         netdev->vlan_features    |= NETIF_F_TSO;
3614         netdev->vlan_features    |= NETIF_F_TSO6;
3615         netdev->vlan_features    |= NETIF_F_RXCSUM;
3616         netdev->vlan_features    |= NETIF_F_RXHASH;
3617
3618         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3619                 netdev->vlan_features    |= NETIF_F_LRO;
3620
3621         netdev->hw_features       = netdev->vlan_features;
3622         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3623         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3624         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3625
3626         if (mlx5e_vxlan_allowed(mdev)) {
3627                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3628                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3629                                            NETIF_F_GSO_PARTIAL;
3630                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3631                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3632                 netdev->hw_enc_features |= NETIF_F_TSO;
3633                 netdev->hw_enc_features |= NETIF_F_TSO6;
3634                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3635                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3636                                            NETIF_F_GSO_PARTIAL;
3637                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3638         }
3639
3640         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3641
3642         if (fcs_supported)
3643                 netdev->hw_features |= NETIF_F_RXALL;
3644
3645         netdev->features          = netdev->hw_features;
3646         if (!priv->params.lro_en)
3647                 netdev->features  &= ~NETIF_F_LRO;
3648
3649         if (fcs_enabled)
3650                 netdev->features  &= ~NETIF_F_RXALL;
3651
3652 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3653         if (FT_CAP(flow_modify_en) &&
3654             FT_CAP(modify_root) &&
3655             FT_CAP(identified_miss_table_mode) &&
3656             FT_CAP(flow_table_modify)) {
3657                 netdev->hw_features      |= NETIF_F_HW_TC;
3658 #ifdef CONFIG_RFS_ACCEL
3659                 netdev->hw_features      |= NETIF_F_NTUPLE;
3660 #endif
3661         }
3662
3663         netdev->features         |= NETIF_F_HIGHDMA;
3664
3665         netdev->priv_flags       |= IFF_UNICAST_FLT;
3666
3667         mlx5e_set_netdev_dev_addr(netdev);
3668
3669 #ifdef CONFIG_NET_SWITCHDEV
3670         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3671                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3672 #endif
3673 }
3674
3675 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3676 {
3677         struct mlx5_core_dev *mdev = priv->mdev;
3678         int err;
3679
3680         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3681         if (err) {
3682                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3683                 priv->q_counter = 0;
3684         }
3685 }
3686
3687 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3688 {
3689         if (!priv->q_counter)
3690                 return;
3691
3692         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3693 }
3694
3695 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3696                            struct net_device *netdev,
3697                            const struct mlx5e_profile *profile,
3698                            void *ppriv)
3699 {
3700         struct mlx5e_priv *priv = netdev_priv(netdev);
3701
3702         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3703         mlx5e_build_nic_netdev(netdev);
3704         mlx5e_vxlan_init(priv);
3705 }
3706
3707 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3708 {
3709         mlx5e_vxlan_cleanup(priv);
3710
3711         if (priv->xdp_prog)
3712                 bpf_prog_put(priv->xdp_prog);
3713 }
3714
3715 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3716 {
3717         struct mlx5_core_dev *mdev = priv->mdev;
3718         int err;
3719         int i;
3720
3721         err = mlx5e_create_indirect_rqts(priv);
3722         if (err) {
3723                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3724                 return err;
3725         }
3726
3727         err = mlx5e_create_direct_rqts(priv);
3728         if (err) {
3729                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3730                 goto err_destroy_indirect_rqts;
3731         }
3732
3733         err = mlx5e_create_indirect_tirs(priv);
3734         if (err) {
3735                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3736                 goto err_destroy_direct_rqts;
3737         }
3738
3739         err = mlx5e_create_direct_tirs(priv);
3740         if (err) {
3741                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3742                 goto err_destroy_indirect_tirs;
3743         }
3744
3745         err = mlx5e_create_flow_steering(priv);
3746         if (err) {
3747                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3748                 goto err_destroy_direct_tirs;
3749         }
3750
3751         err = mlx5e_tc_init(priv);
3752         if (err)
3753                 goto err_destroy_flow_steering;
3754
3755         return 0;
3756
3757 err_destroy_flow_steering:
3758         mlx5e_destroy_flow_steering(priv);
3759 err_destroy_direct_tirs:
3760         mlx5e_destroy_direct_tirs(priv);
3761 err_destroy_indirect_tirs:
3762         mlx5e_destroy_indirect_tirs(priv);
3763 err_destroy_direct_rqts:
3764         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3765                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3766 err_destroy_indirect_rqts:
3767         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3768         return err;
3769 }
3770
3771 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3772 {
3773         int i;
3774
3775         mlx5e_tc_cleanup(priv);
3776         mlx5e_destroy_flow_steering(priv);
3777         mlx5e_destroy_direct_tirs(priv);
3778         mlx5e_destroy_indirect_tirs(priv);
3779         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3780                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3781         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3782 }
3783
3784 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3785 {
3786         int err;
3787
3788         err = mlx5e_create_tises(priv);
3789         if (err) {
3790                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3791                 return err;
3792         }
3793
3794 #ifdef CONFIG_MLX5_CORE_EN_DCB
3795         mlx5e_dcbnl_initialize(priv);
3796 #endif
3797         return 0;
3798 }
3799
3800 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3801 {
3802         struct net_device *netdev = priv->netdev;
3803         struct mlx5_core_dev *mdev = priv->mdev;
3804         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3805         struct mlx5_eswitch_rep rep;
3806
3807         mlx5_lag_add(mdev, netdev);
3808
3809         mlx5e_enable_async_events(priv);
3810
3811         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3812                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3813                 rep.load = mlx5e_nic_rep_load;
3814                 rep.unload = mlx5e_nic_rep_unload;
3815                 rep.vport = FDB_UPLINK_VPORT;
3816                 rep.netdev = netdev;
3817                 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3818         }
3819
3820         if (netdev->reg_state != NETREG_REGISTERED)
3821                 return;
3822
3823         /* Device already registered: sync netdev system state */
3824         if (mlx5e_vxlan_allowed(mdev)) {
3825                 rtnl_lock();
3826                 udp_tunnel_get_rx_info(netdev);
3827                 rtnl_unlock();
3828         }
3829
3830         queue_work(priv->wq, &priv->set_rx_mode_work);
3831 }
3832
3833 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3834 {
3835         struct mlx5_core_dev *mdev = priv->mdev;
3836         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3837
3838         queue_work(priv->wq, &priv->set_rx_mode_work);
3839         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3840                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3841         mlx5e_disable_async_events(priv);
3842         mlx5_lag_remove(mdev);
3843 }
3844
3845 static const struct mlx5e_profile mlx5e_nic_profile = {
3846         .init              = mlx5e_nic_init,
3847         .cleanup           = mlx5e_nic_cleanup,
3848         .init_rx           = mlx5e_init_nic_rx,
3849         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3850         .init_tx           = mlx5e_init_nic_tx,
3851         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3852         .enable            = mlx5e_nic_enable,
3853         .disable           = mlx5e_nic_disable,
3854         .update_stats      = mlx5e_update_stats,
3855         .max_nch           = mlx5e_get_max_num_channels,
3856         .max_tc            = MLX5E_MAX_NUM_TC,
3857 };
3858
3859 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3860                                        const struct mlx5e_profile *profile,
3861                                        void *ppriv)
3862 {
3863         int nch = profile->max_nch(mdev);
3864         struct net_device *netdev;
3865         struct mlx5e_priv *priv;
3866
3867         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3868                                     nch * profile->max_tc,
3869                                     nch);
3870         if (!netdev) {
3871                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3872                 return NULL;
3873         }
3874
3875         profile->init(mdev, netdev, profile, ppriv);
3876
3877         netif_carrier_off(netdev);
3878
3879         priv = netdev_priv(netdev);
3880
3881         priv->wq = create_singlethread_workqueue("mlx5e");
3882         if (!priv->wq)
3883                 goto err_cleanup_nic;
3884
3885         return netdev;
3886
3887 err_cleanup_nic:
3888         profile->cleanup(priv);
3889         free_netdev(netdev);
3890
3891         return NULL;
3892 }
3893
3894 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3895 {
3896         const struct mlx5e_profile *profile;
3897         struct mlx5e_priv *priv;
3898         u16 max_mtu;
3899         int err;
3900
3901         priv = netdev_priv(netdev);
3902         profile = priv->profile;
3903         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3904
3905         err = profile->init_tx(priv);
3906         if (err)
3907                 goto out;
3908
3909         err = mlx5e_open_drop_rq(priv);
3910         if (err) {
3911                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3912                 goto err_cleanup_tx;
3913         }
3914
3915         err = profile->init_rx(priv);
3916         if (err)
3917                 goto err_close_drop_rq;
3918
3919         mlx5e_create_q_counter(priv);
3920
3921         mlx5e_init_l2_addr(priv);
3922
3923         /* MTU range: 68 - hw-specific max */
3924         netdev->min_mtu = ETH_MIN_MTU;
3925         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3926         netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3927
3928         mlx5e_set_dev_port_mtu(netdev);
3929
3930         if (profile->enable)
3931                 profile->enable(priv);
3932
3933         rtnl_lock();
3934         if (netif_running(netdev))
3935                 mlx5e_open(netdev);
3936         netif_device_attach(netdev);
3937         rtnl_unlock();
3938
3939         return 0;
3940
3941 err_close_drop_rq:
3942         mlx5e_close_drop_rq(priv);
3943
3944 err_cleanup_tx:
3945         profile->cleanup_tx(priv);
3946
3947 out:
3948         return err;
3949 }
3950
3951 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3952 {
3953         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3954         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3955         int vport;
3956         u8 mac[ETH_ALEN];
3957
3958         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3959                 return;
3960
3961         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3962
3963         for (vport = 1; vport < total_vfs; vport++) {
3964                 struct mlx5_eswitch_rep rep;
3965
3966                 rep.load = mlx5e_vport_rep_load;
3967                 rep.unload = mlx5e_vport_rep_unload;
3968                 rep.vport = vport;
3969                 ether_addr_copy(rep.hw_id, mac);
3970                 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3971         }
3972 }
3973
3974 static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev)
3975 {
3976         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3977         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3978         int vport;
3979
3980         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3981                 return;
3982
3983         for (vport = 1; vport < total_vfs; vport++)
3984                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3985 }
3986
3987 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3988 {
3989         struct mlx5e_priv *priv = netdev_priv(netdev);
3990         const struct mlx5e_profile *profile = priv->profile;
3991
3992         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3993
3994         rtnl_lock();
3995         if (netif_running(netdev))
3996                 mlx5e_close(netdev);
3997         netif_device_detach(netdev);
3998         rtnl_unlock();
3999
4000         if (profile->disable)
4001                 profile->disable(priv);
4002         flush_workqueue(priv->wq);
4003
4004         mlx5e_destroy_q_counter(priv);
4005         profile->cleanup_rx(priv);
4006         mlx5e_close_drop_rq(priv);
4007         profile->cleanup_tx(priv);
4008         cancel_delayed_work_sync(&priv->update_stats_work);
4009 }
4010
4011 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4012  * hardware contexts and to connect it to the current netdev.
4013  */
4014 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4015 {
4016         struct mlx5e_priv *priv = vpriv;
4017         struct net_device *netdev = priv->netdev;
4018         int err;
4019
4020         if (netif_device_present(netdev))
4021                 return 0;
4022
4023         err = mlx5e_create_mdev_resources(mdev);
4024         if (err)
4025                 return err;
4026
4027         err = mlx5e_attach_netdev(mdev, netdev);
4028         if (err) {
4029                 mlx5e_destroy_mdev_resources(mdev);
4030                 return err;
4031         }
4032
4033         mlx5e_register_vport_rep(mdev);
4034         return 0;
4035 }
4036
4037 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4038 {
4039         struct mlx5e_priv *priv = vpriv;
4040         struct net_device *netdev = priv->netdev;
4041
4042         if (!netif_device_present(netdev))
4043                 return;
4044
4045         mlx5e_unregister_vport_rep(mdev);
4046         mlx5e_detach_netdev(mdev, netdev);
4047         mlx5e_destroy_mdev_resources(mdev);
4048 }
4049
4050 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4051 {
4052         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4053         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4054         void *ppriv = NULL;
4055         void *priv;
4056         int vport;
4057         int err;
4058         struct net_device *netdev;
4059
4060         err = mlx5e_check_required_hca_cap(mdev);
4061         if (err)
4062                 return NULL;
4063
4064         if (MLX5_CAP_GEN(mdev, vport_group_manager))
4065                 ppriv = &esw->offloads.vport_reps[0];
4066
4067         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4068         if (!netdev) {
4069                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4070                 goto err_unregister_reps;
4071         }
4072
4073         priv = netdev_priv(netdev);
4074
4075         err = mlx5e_attach(mdev, priv);
4076         if (err) {
4077                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4078                 goto err_destroy_netdev;
4079         }
4080
4081         err = register_netdev(netdev);
4082         if (err) {
4083                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4084                 goto err_detach;
4085         }
4086
4087         return priv;
4088
4089 err_detach:
4090         mlx5e_detach(mdev, priv);
4091
4092 err_destroy_netdev:
4093         mlx5e_destroy_netdev(mdev, priv);
4094
4095 err_unregister_reps:
4096         for (vport = 1; vport < total_vfs; vport++)
4097                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4098
4099         return NULL;
4100 }
4101
4102 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4103 {
4104         const struct mlx5e_profile *profile = priv->profile;
4105         struct net_device *netdev = priv->netdev;
4106
4107         destroy_workqueue(priv->wq);
4108         if (profile->cleanup)
4109                 profile->cleanup(priv);
4110         free_netdev(netdev);
4111 }
4112
4113 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4114 {
4115         struct mlx5e_priv *priv = vpriv;
4116
4117         unregister_netdev(priv->netdev);
4118         mlx5e_detach(mdev, vpriv);
4119         mlx5e_destroy_netdev(mdev, priv);
4120 }
4121
4122 static void *mlx5e_get_netdev(void *vpriv)
4123 {
4124         struct mlx5e_priv *priv = vpriv;
4125
4126         return priv->netdev;
4127 }
4128
4129 static struct mlx5_interface mlx5e_interface = {
4130         .add       = mlx5e_add,
4131         .remove    = mlx5e_remove,
4132         .attach    = mlx5e_attach,
4133         .detach    = mlx5e_detach,
4134         .event     = mlx5e_async_event,
4135         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4136         .get_dev   = mlx5e_get_netdev,
4137 };
4138
4139 void mlx5e_init(void)
4140 {
4141         mlx5e_build_ptys2ethtool_map();
4142         mlx5_register_interface(&mlx5e_interface);
4143 }
4144
4145 void mlx5e_cleanup(void)
4146 {
4147         mlx5_unregister_interface(&mlx5e_interface);
4148 }