2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
58 extern const struct net_device_ops mlx5e_netdev_ops;
61 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
62 #define MLX5E_METADATA_ETHER_LEN 8
64 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
66 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
68 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
69 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
71 #define MLX5E_MAX_PRIORITY 8
72 #define MLX5E_MAX_DSCP 64
73 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5E_RX_MAX_HEAD (256)
81 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
82 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
83 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
84 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
85 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
86 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
88 #define MLX5_MPWRQ_LOG_WQE_SZ 18
89 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
90 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
91 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
94 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
95 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
96 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
97 #define MLX5E_MAX_RQ_NUM_MTTS \
98 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
99 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
100 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
101 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
102 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
103 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
104 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
106 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
107 #define MLX5E_LOG_MAX_RX_WQE_BULK \
108 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
110 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
111 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
112 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
114 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
115 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
116 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
117 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
119 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
121 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
122 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
123 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
128 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
131 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
135 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
136 #define MLX5E_MIN_NUM_CHANNELS 0x1
137 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
138 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
139 #define MLX5E_TX_CQ_POLL_BUDGET 128
140 #define MLX5E_TX_XSK_POLL_BUDGET 64
141 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
143 #define MLX5E_UMR_WQE_INLINE_SZ \
144 (sizeof(struct mlx5e_umr_wqe) + \
145 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
146 MLX5_UMR_MTT_ALIGNMENT))
147 #define MLX5E_UMR_WQEBBS \
148 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
150 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
152 #define mlx5e_dbg(mlevel, priv, format, ...) \
154 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
155 netdev_warn(priv->netdev, format, \
159 enum mlx5e_rq_group {
160 MLX5E_RQ_GROUP_REGULAR,
162 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
165 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
168 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
169 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
172 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
177 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
178 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
180 return is_kdump_kernel() ?
181 MLX5E_MIN_NUM_CHANNELS :
182 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
185 struct mlx5e_tx_wqe {
186 struct mlx5_wqe_ctrl_seg ctrl;
187 struct mlx5_wqe_eth_seg eth;
188 struct mlx5_wqe_data_seg data[0];
191 struct mlx5e_rx_wqe_ll {
192 struct mlx5_wqe_srq_next_seg next;
193 struct mlx5_wqe_data_seg data[0];
196 struct mlx5e_rx_wqe_cyc {
197 struct mlx5_wqe_data_seg data[0];
200 struct mlx5e_umr_wqe {
201 struct mlx5_wqe_ctrl_seg ctrl;
202 struct mlx5_wqe_umr_ctrl_seg uctrl;
203 struct mlx5_mkey_seg mkc;
205 struct mlx5_mtt inline_mtts[0];
206 u8 tls_static_params_ctx[0];
210 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
212 enum mlx5e_priv_flag {
213 MLX5E_PFLAG_RX_CQE_BASED_MODER,
214 MLX5E_PFLAG_TX_CQE_BASED_MODER,
215 MLX5E_PFLAG_RX_CQE_COMPRESS,
216 MLX5E_PFLAG_RX_STRIDING_RQ,
217 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
218 MLX5E_PFLAG_XDP_TX_MPWQE,
219 MLX5E_NUM_PFLAGS, /* Keep last */
222 #define MLX5E_SET_PFLAG(params, pflag, enable) \
225 (params)->pflags |= BIT(pflag); \
227 (params)->pflags &= ~(BIT(pflag)); \
230 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
232 #ifdef CONFIG_MLX5_CORE_EN_DCB
233 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
236 struct mlx5e_params {
239 u8 log_rq_mtu_frames;
242 bool rx_cqe_compress_def;
243 bool tunneled_offload_en;
244 struct dim_cq_moder rx_cq_moderation;
245 struct dim_cq_moder tx_cq_moderation;
247 u8 tx_min_inline_mode;
248 bool vlan_strip_disable;
254 struct bpf_prog *xdp_prog;
255 struct mlx5e_xsk *xsk;
260 #ifdef CONFIG_MLX5_CORE_EN_DCB
261 struct mlx5e_cee_config {
262 /* bw pct for priority group */
263 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
264 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
265 bool pfc_setting[CEE_DCBX_MAX_PRIO];
272 MLX5_DCB_CHG_NO_RESET,
276 enum mlx5_dcbx_oper_mode mode;
277 struct mlx5e_cee_config cee_cfg; /* pending configuration */
280 /* The only setting that cannot be read from FW */
281 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
284 /* Buffer configuration */
290 struct mlx5e_dcbx_dp {
291 u8 dscp2prio[MLX5E_MAX_DSCP];
297 MLX5E_RQ_STATE_ENABLED,
299 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
300 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
304 /* data path - accessed per cqe */
307 /* data path - accessed per napi poll */
309 struct napi_struct *napi;
310 struct mlx5_core_cq mcq;
311 struct mlx5e_channel *channel;
314 struct mlx5_core_dev *mdev;
315 struct mlx5_wq_ctrl wq_ctrl;
316 } ____cacheline_aligned_in_smp;
318 struct mlx5e_cq_decomp {
319 /* cqe decompression */
320 struct mlx5_cqe64 title;
321 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
325 } ____cacheline_aligned_in_smp;
327 struct mlx5e_tx_wqe_info {
332 #ifdef CONFIG_MLX5_EN_TLS
333 skb_frag_t *resync_dump_frag;
337 enum mlx5e_dma_map_type {
338 MLX5E_DMA_MAP_SINGLE,
342 struct mlx5e_sq_dma {
345 enum mlx5e_dma_map_type type;
349 MLX5E_SQ_STATE_ENABLED,
350 MLX5E_SQ_STATE_RECOVERING,
351 MLX5E_SQ_STATE_IPSEC,
356 struct mlx5e_sq_wqe_info {
359 /* Auxiliary data for different opcodes. */
370 /* dirtied @completion */
373 struct dim dim; /* Adaptive Moderation */
376 u16 pc ____cacheline_aligned_in_smp;
382 struct mlx5_wq_cyc wq;
384 struct mlx5e_sq_stats *stats;
386 struct mlx5e_sq_dma *dma_fifo;
387 struct mlx5e_tx_wqe_info *wqe_info;
389 void __iomem *uar_map;
390 struct netdev_queue *txq;
397 struct hwtstamp_config *tstamp;
398 struct mlx5_clock *clock;
401 struct mlx5_wq_ctrl wq_ctrl;
402 struct mlx5e_channel *channel;
406 struct work_struct recover_work;
407 } ____cacheline_aligned_in_smp;
409 struct mlx5e_dma_info {
420 /* XDP packets can be transmitted in different ways. On completion, we need to
421 * distinguish between them to clean up things in a proper way.
423 enum mlx5e_xdp_xmit_mode {
424 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
425 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
428 MLX5E_XDP_XMIT_MODE_FRAME,
430 /* The xdp_frame was created in place as a result of XDP_TX from a
431 * regular RQ. No DMA remapping happened, and the page belongs to us.
433 MLX5E_XDP_XMIT_MODE_PAGE,
435 /* No xdp_frame was created at all, the transmit happened from a UMEM
436 * page. The UMEM Completion Ring producer pointer has to be increased.
438 MLX5E_XDP_XMIT_MODE_XSK,
441 struct mlx5e_xdp_info {
442 enum mlx5e_xdp_xmit_mode mode;
445 struct xdp_frame *xdpf;
450 struct mlx5e_dma_info di;
455 struct mlx5e_xdp_xmit_data {
461 struct mlx5e_xdp_info_fifo {
462 struct mlx5e_xdp_info *xi;
468 struct mlx5e_xdp_wqe_info {
473 struct mlx5e_xdp_mpwqe {
474 /* Current MPWQE session */
475 struct mlx5e_tx_wqe *wqe;
484 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
485 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
486 struct mlx5e_xdp_xmit_data *,
487 struct mlx5e_xdp_info *,
493 /* dirtied @completion */
498 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
500 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
501 struct mlx5e_xdp_mpwqe mpwqe;
506 struct xdp_umem *umem;
507 struct mlx5_wq_cyc wq;
508 struct mlx5e_xdpsq_stats *stats;
509 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
510 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
512 struct mlx5e_xdp_wqe_info *wqe_info;
513 struct mlx5e_xdp_info_fifo xdpi_fifo;
515 void __iomem *uar_map;
524 struct mlx5_wq_ctrl wq_ctrl;
525 struct mlx5e_channel *channel;
526 } ____cacheline_aligned_in_smp;
533 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
536 /* write@xmit, read@completion */
538 struct mlx5e_sq_wqe_info *ico_wqe;
542 struct mlx5_wq_cyc wq;
543 void __iomem *uar_map;
548 struct mlx5_wq_ctrl wq_ctrl;
549 struct mlx5e_channel *channel;
550 } ____cacheline_aligned_in_smp;
552 struct mlx5e_wqe_frag_info {
553 struct mlx5e_dma_info *di;
558 struct mlx5e_umr_dma_info {
559 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
562 struct mlx5e_mpw_info {
563 struct mlx5e_umr_dma_info umr;
564 u16 consumed_strides;
565 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
568 #define MLX5E_MAX_RX_FRAGS 4
570 /* a single cache unit is capable to serve one napi call (for non-striding rq)
571 * or a MPWQE (for striding rq).
573 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
574 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
575 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
576 struct mlx5e_page_cache {
579 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
583 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
584 typedef struct sk_buff *
585 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
586 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
587 typedef struct sk_buff *
588 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
589 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
590 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
591 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
594 MLX5E_RQ_FLAG_XDP_XMIT,
595 MLX5E_RQ_FLAG_XDP_REDIRECT,
598 struct mlx5e_rq_frag_info {
603 struct mlx5e_rq_frags_info {
604 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
614 struct mlx5_wq_cyc wq;
615 struct mlx5e_wqe_frag_info *frags;
616 struct mlx5e_dma_info *di;
617 struct mlx5e_rq_frags_info info;
618 mlx5e_fp_skb_from_cqe skb_from_cqe;
621 struct mlx5_wq_ll wq;
622 struct mlx5e_umr_wqe umr_wqe;
623 struct mlx5e_mpw_info *info;
624 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
636 u8 map_dir; /* dma map direction */
639 struct mlx5e_channel *channel;
641 struct net_device *netdev;
642 struct mlx5e_rq_stats *stats;
644 struct mlx5e_cq_decomp cqd;
645 struct mlx5e_page_cache page_cache;
646 struct hwtstamp_config *tstamp;
647 struct mlx5_clock *clock;
649 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
650 mlx5e_fp_post_rx_wqes post_wqes;
651 mlx5e_fp_dealloc_wqe dealloc_wqe;
657 struct dim dim; /* Dynamic Interrupt Moderation */
660 struct bpf_prog *xdp_prog;
661 struct mlx5e_xdpsq *xdpsq;
662 DECLARE_BITMAP(flags, 8);
663 struct page_pool *page_pool;
665 /* AF_XDP zero-copy */
666 struct zero_copy_allocator zca;
667 struct xdp_umem *umem;
670 struct mlx5_wq_ctrl wq_ctrl;
674 struct mlx5_core_dev *mdev;
675 struct mlx5_core_mkey umr_mkey;
677 /* XDP read-mostly */
678 struct xdp_rxq_info xdp_rxq;
679 } ____cacheline_aligned_in_smp;
681 enum mlx5e_channel_state {
682 MLX5E_CHANNEL_STATE_XSK,
683 MLX5E_CHANNEL_NUM_STATES
686 struct mlx5e_channel {
689 struct mlx5e_xdpsq rq_xdpsq;
690 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
691 struct mlx5e_icosq icosq; /* internal control operations */
693 struct napi_struct napi;
695 struct net_device *netdev;
700 struct mlx5e_xdpsq xdpsq;
702 /* AF_XDP zero-copy */
703 struct mlx5e_rq xskrq;
704 struct mlx5e_xdpsq xsksq;
705 struct mlx5e_icosq xskicosq;
706 /* xskicosq can be accessed from any CPU - the spinlock protects it. */
707 spinlock_t xskicosq_lock;
709 /* data path - accessed per napi poll */
710 struct irq_desc *irq_desc;
711 struct mlx5e_ch_stats *stats;
714 struct mlx5e_priv *priv;
715 struct mlx5_core_dev *mdev;
716 struct hwtstamp_config *tstamp;
717 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
720 cpumask_var_t xps_cpumask;
723 struct mlx5e_channels {
724 struct mlx5e_channel **c;
726 struct mlx5e_params params;
729 struct mlx5e_channel_stats {
730 struct mlx5e_ch_stats ch;
731 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
732 struct mlx5e_rq_stats rq;
733 struct mlx5e_rq_stats xskrq;
734 struct mlx5e_xdpsq_stats rq_xdpsq;
735 struct mlx5e_xdpsq_stats xdpsq;
736 struct mlx5e_xdpsq_stats xsksq;
737 } ____cacheline_aligned_in_smp;
741 MLX5E_STATE_DESTROYING,
742 MLX5E_STATE_XDP_TX_ENABLED,
743 MLX5E_STATE_XDP_OPEN,
753 struct mlx5e_rqt rqt;
754 struct list_head list;
762 struct mlx5e_rss_params {
763 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
764 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
765 u8 toeplitz_hash_key[40];
769 struct mlx5e_modify_sq_param {
777 /* UMEMs are stored separately from channels, because we don't want to
778 * lose them when channels are recreated. The kernel also stores UMEMs,
779 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
780 * so rely on our mechanism.
782 struct xdp_umem **umems;
788 /* priv data path fields - start */
789 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
790 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
791 #ifdef CONFIG_MLX5_CORE_EN_DCB
792 struct mlx5e_dcbx_dp dcbx_dp;
794 /* priv data path fields - end */
798 struct mutex state_lock; /* Protects Interface state */
799 struct mlx5e_rq drop_rq;
801 struct mlx5e_channels channels;
802 u32 tisn[MLX5E_MAX_NUM_TC];
803 struct mlx5e_rqt indir_rqt;
804 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
805 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
806 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
807 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
808 struct mlx5e_rss_params rss_params;
809 u32 tx_rates[MLX5E_MAX_NUM_SQS];
811 struct mlx5e_flow_steering fs;
813 struct workqueue_struct *wq;
814 struct work_struct update_carrier_work;
815 struct work_struct set_rx_mode_work;
816 struct work_struct tx_timeout_work;
817 struct work_struct update_stats_work;
818 struct work_struct monitor_counters_work;
819 struct mlx5_nb monitor_counters_nb;
821 struct mlx5_core_dev *mdev;
822 struct net_device *netdev;
823 struct mlx5e_stats stats;
824 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
827 struct hwtstamp_config tstamp;
829 u16 drop_rq_q_counter;
830 struct notifier_block events_nb;
832 #ifdef CONFIG_MLX5_CORE_EN_DCB
833 struct mlx5e_dcbx dcbx;
836 const struct mlx5e_profile *profile;
838 #ifdef CONFIG_MLX5_EN_IPSEC
839 struct mlx5e_ipsec *ipsec;
841 #ifdef CONFIG_MLX5_EN_TLS
842 struct mlx5e_tls *tls;
844 struct devlink_health_reporter *tx_reporter;
845 struct mlx5e_xsk xsk;
848 struct mlx5e_profile {
849 int (*init)(struct mlx5_core_dev *mdev,
850 struct net_device *netdev,
851 const struct mlx5e_profile *profile, void *ppriv);
852 void (*cleanup)(struct mlx5e_priv *priv);
853 int (*init_rx)(struct mlx5e_priv *priv);
854 void (*cleanup_rx)(struct mlx5e_priv *priv);
855 int (*init_tx)(struct mlx5e_priv *priv);
856 void (*cleanup_tx)(struct mlx5e_priv *priv);
857 void (*enable)(struct mlx5e_priv *priv);
858 void (*disable)(struct mlx5e_priv *priv);
859 int (*update_rx)(struct mlx5e_priv *priv);
860 void (*update_stats)(struct mlx5e_priv *priv);
861 void (*update_carrier)(struct mlx5e_priv *priv);
863 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
864 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
870 void mlx5e_build_ptys2ethtool_map(void);
872 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
873 struct net_device *sb_dev);
874 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
875 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
876 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more);
878 void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
879 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
880 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
881 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
882 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
883 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
884 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
886 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
887 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
888 struct mlx5e_params *params);
890 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
891 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
892 struct mlx5e_dma_info *dma_info,
894 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
895 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
896 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
897 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
898 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
899 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
900 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
902 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
903 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
905 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
906 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
908 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
909 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
911 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
912 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
914 void mlx5e_update_stats(struct mlx5e_priv *priv);
915 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
916 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
918 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
919 int mlx5e_self_test_num(struct mlx5e_priv *priv);
920 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
922 void mlx5e_set_rx_mode_work(struct work_struct *work);
924 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
925 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
926 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
928 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
930 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
932 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
934 struct mlx5e_redirect_rqt_param {
937 u32 rqn; /* Direct RQN (Non-RSS) */
940 struct mlx5e_channels *channels;
941 } rss; /* RSS data */
945 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
946 struct mlx5e_redirect_rqt_param rrp);
947 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
948 const struct mlx5e_tirc_config *ttconfig,
949 void *tirc, bool inner);
950 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
951 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
953 struct mlx5e_xsk_param;
955 struct mlx5e_rq_param;
956 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
957 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
958 struct xdp_umem *umem, struct mlx5e_rq *rq);
959 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
960 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
961 void mlx5e_close_rq(struct mlx5e_rq *rq);
963 struct mlx5e_sq_param;
964 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
965 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
966 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
967 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
968 struct mlx5e_sq_param *param, struct xdp_umem *umem,
969 struct mlx5e_xdpsq *sq, bool is_redirect);
970 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
972 struct mlx5e_cq_param;
973 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
974 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
975 void mlx5e_close_cq(struct mlx5e_cq *cq);
977 int mlx5e_open_locked(struct net_device *netdev);
978 int mlx5e_close_locked(struct net_device *netdev);
980 int mlx5e_open_channels(struct mlx5e_priv *priv,
981 struct mlx5e_channels *chs);
982 void mlx5e_close_channels(struct mlx5e_channels *chs);
984 /* Function pointer to be used to modify WH settings while
987 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
988 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
989 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
990 struct mlx5e_channels *new_chs,
991 mlx5e_fp_hw_modify hw_modify);
992 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
993 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
995 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
997 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
999 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
1001 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
1002 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
1003 struct mlx5e_params *params);
1005 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1006 struct mlx5e_modify_sq_param *p);
1007 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1008 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1010 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
1012 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
1013 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
1016 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1018 return MLX5_CAP_ETH(mdev, swp) &&
1019 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1022 extern const struct ethtool_ops mlx5e_ethtool_ops;
1023 #ifdef CONFIG_MLX5_CORE_EN_DCB
1024 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1025 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1026 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1027 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1028 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1031 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1032 struct mlx5e_tir *tir, u32 *in, int inlen);
1033 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1034 struct mlx5e_tir *tir);
1035 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1036 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1037 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1039 /* common netdev helpers */
1040 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1041 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1042 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1043 struct mlx5e_rq *drop_rq);
1044 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1046 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1048 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1049 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1051 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1052 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1053 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1054 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1055 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1057 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1058 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1060 int mlx5e_create_tises(struct mlx5e_priv *priv);
1061 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1062 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1063 int mlx5e_close(struct net_device *netdev);
1064 int mlx5e_open(struct net_device *netdev);
1065 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
1067 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1068 int mlx5e_bits_invert(unsigned long a, int size);
1070 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
1071 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1072 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1073 change_hw_mtu_cb set_mtu_cb);
1075 /* ethtool helpers */
1076 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1077 struct ethtool_drvinfo *drvinfo);
1078 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1079 uint32_t stringset, uint8_t *data);
1080 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1081 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1082 struct ethtool_stats *stats, u64 *data);
1083 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1084 struct ethtool_ringparam *param);
1085 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1086 struct ethtool_ringparam *param);
1087 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1088 struct ethtool_channels *ch);
1089 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1090 struct ethtool_channels *ch);
1091 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1092 struct ethtool_coalesce *coal);
1093 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1094 struct ethtool_coalesce *coal);
1095 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1096 struct ethtool_link_ksettings *link_ksettings);
1097 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1098 const struct ethtool_link_ksettings *link_ksettings);
1099 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1100 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1101 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1102 struct ethtool_ts_info *info);
1103 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1104 struct ethtool_pauseparam *pauseparam);
1105 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1106 struct ethtool_pauseparam *pauseparam);
1108 /* mlx5e generic netdev management API */
1109 int mlx5e_netdev_init(struct net_device *netdev,
1110 struct mlx5e_priv *priv,
1111 struct mlx5_core_dev *mdev,
1112 const struct mlx5e_profile *profile,
1114 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1116 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1117 int nch, void *ppriv);
1118 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1119 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1120 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1121 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1122 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1123 struct mlx5e_xsk *xsk,
1124 struct mlx5e_rss_params *rss_params,
1125 struct mlx5e_params *params,
1126 u16 max_channels, u16 mtu);
1127 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1128 struct mlx5e_params *params);
1129 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1131 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1132 void mlx5e_rx_dim_work(struct work_struct *work);
1133 void mlx5e_tx_dim_work(struct work_struct *work);
1135 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1136 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1137 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1138 struct net_device *netdev,
1139 netdev_features_t features);
1140 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1141 #ifdef CONFIG_MLX5_ESWITCH
1142 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1143 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1144 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1145 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1147 #endif /* __MLX5_EN_H__ */