2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/rhashtable.h>
48 #include <net/switchdev.h>
51 #include "mlx5_core.h"
54 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
56 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
58 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu))
59 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu))
61 #define MLX5E_MAX_DSCP 64
62 #define MLX5E_MAX_NUM_TC 8
64 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
65 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
66 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
68 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
69 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
70 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
72 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
73 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
74 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
76 #define MLX5_RX_HEADROOM NET_SKB_PAD
77 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
78 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
81 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
82 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
83 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
84 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
85 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
86 #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \
87 (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \
88 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))
90 #define MLX5_MPWRQ_LOG_WQE_SZ 18
91 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
92 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
93 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
95 MLX5_MPWRQ_WQE_PAGE_ORDER)
97 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
98 #define MLX5E_REQUIRED_MTTS(wqes) \
99 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
100 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
102 #define MLX5_UMR_ALIGN (2048)
103 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256)
105 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
106 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
107 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
109 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
110 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
111 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
112 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
113 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
114 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
115 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
116 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
118 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
119 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
120 #define MLX5E_MIN_NUM_CHANNELS 0x1
121 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
122 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
123 #define MLX5E_TX_CQ_POLL_BUDGET 128
124 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
126 #define MLX5E_ICOSQ_MAX_WQEBBS \
127 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
129 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
130 #define MLX5E_XDP_TX_DS_COUNT \
131 ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
133 #define MLX5E_NUM_MAIN_GROUPS 9
135 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
137 #define mlx5e_dbg(mlevel, priv, format, ...) \
139 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
140 netdev_warn(priv->netdev, format, \
145 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
148 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
149 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
152 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
157 static inline int mlx5_min_log_rq_size(int wq_type)
160 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
161 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
163 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
167 static inline int mlx5_max_log_rq_size(int wq_type)
170 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
171 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
173 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
177 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
179 return is_kdump_kernel() ?
180 MLX5E_MIN_NUM_CHANNELS :
181 min_t(int, mdev->priv.eq_table.num_comp_vectors,
182 MLX5E_MAX_NUM_CHANNELS);
185 struct mlx5e_tx_wqe {
186 struct mlx5_wqe_ctrl_seg ctrl;
187 struct mlx5_wqe_eth_seg eth;
190 struct mlx5e_rx_wqe {
191 struct mlx5_wqe_srq_next_seg next;
192 struct mlx5_wqe_data_seg data;
195 struct mlx5e_umr_wqe {
196 struct mlx5_wqe_ctrl_seg ctrl;
197 struct mlx5_wqe_umr_ctrl_seg uctrl;
198 struct mlx5_mkey_seg mkc;
199 struct mlx5_wqe_data_seg data;
202 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
204 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
210 enum mlx5e_priv_flag {
211 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
212 MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),
213 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),
216 #define MLX5E_SET_PFLAG(params, pflag, enable) \
219 (params)->pflags |= (pflag); \
221 (params)->pflags &= ~(pflag); \
224 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
226 #ifdef CONFIG_MLX5_CORE_EN_DCB
227 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
230 struct mlx5e_cq_moder {
236 struct mlx5e_params {
240 u8 mpwqe_log_stride_sz;
241 u8 mpwqe_log_num_strides;
245 bool rx_cqe_compress_def;
246 struct mlx5e_cq_moder rx_cq_moderation;
247 struct mlx5e_cq_moder tx_cq_moderation;
251 u8 tx_min_inline_mode;
253 u8 toeplitz_hash_key[40];
254 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
255 bool vlan_strip_disable;
260 struct bpf_prog *xdp_prog;
263 #ifdef CONFIG_MLX5_CORE_EN_DCB
264 struct mlx5e_cee_config {
265 /* bw pct for priority group */
266 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
267 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
268 bool pfc_setting[CEE_DCBX_MAX_PRIO];
275 MLX5_DCB_CHG_NO_RESET,
279 enum mlx5_dcbx_oper_mode mode;
280 struct mlx5e_cee_config cee_cfg; /* pending configuration */
283 /* The only setting that cannot be read from FW */
284 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
288 struct mlx5e_dcbx_dp {
289 u8 dscp2prio[MLX5E_MAX_DSCP];
295 MLX5E_RQ_STATE_ENABLED,
299 #define MLX5E_TEST_BIT(state, nr) (state & BIT(nr))
302 /* data path - accessed per cqe */
305 /* data path - accessed per napi poll */
307 struct napi_struct *napi;
308 struct mlx5_core_cq mcq;
309 struct mlx5e_channel *channel;
311 /* cqe decompression */
312 struct mlx5_cqe64 title;
313 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
316 u16 decmprs_wqe_counter;
319 struct mlx5_core_dev *mdev;
320 struct mlx5_frag_wq_ctrl wq_ctrl;
321 } ____cacheline_aligned_in_smp;
323 struct mlx5e_tx_wqe_info {
330 enum mlx5e_dma_map_type {
331 MLX5E_DMA_MAP_SINGLE,
335 struct mlx5e_sq_dma {
338 enum mlx5e_dma_map_type type;
342 MLX5E_SQ_STATE_ENABLED,
343 MLX5E_SQ_STATE_IPSEC,
346 struct mlx5e_sq_wqe_info {
353 /* dirtied @completion */
358 u16 pc ____cacheline_aligned_in_smp;
360 struct mlx5e_sq_stats stats;
364 /* write@xmit, read@completion */
366 struct mlx5e_sq_dma *dma_fifo;
367 struct mlx5e_tx_wqe_info *wqe_info;
371 struct mlx5_wq_cyc wq;
373 void __iomem *uar_map;
374 struct netdev_queue *txq;
382 struct hwtstamp_config *tstamp;
383 struct mlx5_clock *clock;
386 struct mlx5_wq_ctrl wq_ctrl;
387 struct mlx5e_channel *channel;
390 } ____cacheline_aligned_in_smp;
395 /* dirtied @rx completion */
401 /* write@xmit, read@completion */
403 struct mlx5e_dma_info *di;
408 struct mlx5_wq_cyc wq;
409 void __iomem *uar_map;
417 struct mlx5_wq_ctrl wq_ctrl;
418 struct mlx5e_channel *channel;
419 } ____cacheline_aligned_in_smp;
425 u16 pc ____cacheline_aligned_in_smp;
429 /* write@xmit, read@completion */
431 struct mlx5e_sq_wqe_info *ico_wqe;
435 struct mlx5_wq_cyc wq;
436 void __iomem *uar_map;
443 struct mlx5_wq_ctrl wq_ctrl;
444 struct mlx5e_channel *channel;
445 } ____cacheline_aligned_in_smp;
448 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
450 return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc));
453 struct mlx5e_dma_info {
458 struct mlx5e_wqe_frag_info {
459 struct mlx5e_dma_info di;
463 struct mlx5e_umr_dma_info {
466 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
467 struct mlx5e_umr_wqe wqe;
470 struct mlx5e_mpw_info {
471 struct mlx5e_umr_dma_info umr;
472 u16 consumed_strides;
473 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
476 struct mlx5e_rx_am_stats {
477 int ppms; /* packets per msec */
478 int bpms; /* bytes per msec */
479 int epms; /* events per msec */
482 struct mlx5e_rx_am_sample {
489 struct mlx5e_rx_am { /* Adaptive Moderation */
491 struct mlx5e_rx_am_stats prev_stats;
492 struct mlx5e_rx_am_sample start_sample;
493 struct work_struct work;
502 /* a single cache unit is capable to serve one napi call (for non-striding rq)
503 * or a MPWQE (for striding rq).
505 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
506 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
507 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
508 struct mlx5e_page_cache {
511 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
515 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
516 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
517 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
521 struct mlx5_wq_ll wq;
525 struct mlx5e_wqe_frag_info *frag_info;
526 u32 frag_sz; /* max possible skb frag_sz */
533 struct mlx5e_mpw_info *info;
537 bool umr_in_progress;
543 u8 map_dir; /* dma map direction */
546 struct mlx5e_channel *channel;
548 struct net_device *netdev;
549 struct mlx5e_rq_stats stats;
551 struct mlx5e_page_cache page_cache;
552 struct hwtstamp_config *tstamp;
553 struct mlx5_clock *clock;
555 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
556 mlx5e_fp_post_rx_wqes post_wqes;
557 mlx5e_fp_dealloc_wqe dealloc_wqe;
562 struct mlx5e_rx_am am; /* Adaptive Moderation */
565 struct bpf_prog *xdp_prog;
566 struct mlx5e_xdpsq xdpsq;
569 struct mlx5_wq_ctrl wq_ctrl;
573 struct mlx5_core_dev *mdev;
574 struct mlx5_core_mkey umr_mkey;
576 /* XDP read-mostly */
577 struct xdp_rxq_info xdp_rxq;
578 } ____cacheline_aligned_in_smp;
580 struct mlx5e_channel {
583 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
584 struct mlx5e_icosq icosq; /* internal control operations */
586 struct napi_struct napi;
588 struct net_device *netdev;
592 /* data path - accessed per napi poll */
593 struct irq_desc *irq_desc;
596 struct mlx5e_priv *priv;
597 struct mlx5_core_dev *mdev;
598 struct hwtstamp_config *tstamp;
603 struct mlx5e_channels {
604 struct mlx5e_channel **c;
606 struct mlx5e_params params;
609 enum mlx5e_traffic_types {
614 MLX5E_TT_IPV4_IPSEC_AH,
615 MLX5E_TT_IPV6_IPSEC_AH,
616 MLX5E_TT_IPV4_IPSEC_ESP,
617 MLX5E_TT_IPV6_IPSEC_ESP,
622 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
625 enum mlx5e_tunnel_types {
632 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
634 MLX5E_STATE_DESTROYING,
637 struct mlx5e_vxlan_db {
638 spinlock_t lock; /* protect vxlan table */
639 struct radix_tree_root tree;
642 struct mlx5e_l2_rule {
643 u8 addr[ETH_ALEN + 2];
644 struct mlx5_flow_handle *rule;
647 struct mlx5e_flow_table {
649 struct mlx5_flow_table *t;
650 struct mlx5_flow_group **g;
653 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
655 struct mlx5e_tc_table {
656 struct mlx5_flow_table *t;
658 struct rhashtable_params ht_params;
659 struct rhashtable ht;
661 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
662 DECLARE_HASHTABLE(hairpin_tbl, 8);
665 struct mlx5e_vlan_table {
666 struct mlx5e_flow_table ft;
667 DECLARE_BITMAP(active_cvlans, VLAN_N_VID);
668 DECLARE_BITMAP(active_svlans, VLAN_N_VID);
669 struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID];
670 struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID];
671 struct mlx5_flow_handle *untagged_rule;
672 struct mlx5_flow_handle *any_cvlan_rule;
673 struct mlx5_flow_handle *any_svlan_rule;
674 bool cvlan_filter_disabled;
677 struct mlx5e_l2_table {
678 struct mlx5e_flow_table ft;
679 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
680 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
681 struct mlx5e_l2_rule broadcast;
682 struct mlx5e_l2_rule allmulti;
683 struct mlx5e_l2_rule promisc;
684 bool broadcast_enabled;
685 bool allmulti_enabled;
686 bool promisc_enabled;
689 /* L3/L4 traffic type classifier */
690 struct mlx5e_ttc_table {
691 struct mlx5e_flow_table ft;
692 struct mlx5_flow_handle *rules[MLX5E_NUM_TT];
693 struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT];
696 #define ARFS_HASH_SHIFT BITS_PER_BYTE
697 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
699 struct mlx5e_flow_table ft;
700 struct mlx5_flow_handle *default_rule;
701 struct hlist_head rules_hash[ARFS_HASH_SIZE];
712 struct mlx5e_arfs_tables {
713 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
714 /* Protect aRFS rules list */
715 spinlock_t arfs_lock;
716 struct list_head rules;
718 struct workqueue_struct *wq;
723 MLX5E_VLAN_FT_LEVEL = 0,
726 MLX5E_INNER_TTC_FT_LEVEL,
730 struct mlx5e_ethtool_table {
731 struct mlx5_flow_table *ft;
735 #define ETHTOOL_NUM_L3_L4_FTS 7
736 #define ETHTOOL_NUM_L2_FTS 4
738 struct mlx5e_ethtool_steering {
739 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
740 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
741 struct list_head rules;
745 struct mlx5e_flow_steering {
746 struct mlx5_flow_namespace *ns;
747 struct mlx5e_ethtool_steering ethtool;
748 struct mlx5e_tc_table tc;
749 struct mlx5e_vlan_table vlan;
750 struct mlx5e_l2_table l2;
751 struct mlx5e_ttc_table ttc;
752 struct mlx5e_ttc_table inner_ttc;
753 struct mlx5e_arfs_tables arfs;
763 struct mlx5e_rqt rqt;
764 struct list_head list;
773 /* priv data path fields - start */
774 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
775 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
776 #ifdef CONFIG_MLX5_CORE_EN_DCB
777 struct mlx5e_dcbx_dp dcbx_dp;
779 /* priv data path fields - end */
783 struct mutex state_lock; /* Protects Interface state */
784 struct mlx5e_rq drop_rq;
786 struct mlx5e_channels channels;
787 u32 tisn[MLX5E_MAX_NUM_TC];
788 struct mlx5e_rqt indir_rqt;
789 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
790 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
791 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
792 u32 tx_rates[MLX5E_MAX_NUM_SQS];
795 struct mlx5e_flow_steering fs;
796 struct mlx5e_vxlan_db vxlan;
798 struct workqueue_struct *wq;
799 struct work_struct update_carrier_work;
800 struct work_struct set_rx_mode_work;
801 struct work_struct tx_timeout_work;
802 struct delayed_work update_stats_work;
804 struct mlx5_core_dev *mdev;
805 struct net_device *netdev;
806 struct mlx5e_stats stats;
807 struct hwtstamp_config tstamp;
809 #ifdef CONFIG_MLX5_CORE_EN_DCB
810 struct mlx5e_dcbx dcbx;
813 const struct mlx5e_profile *profile;
815 #ifdef CONFIG_MLX5_EN_IPSEC
816 struct mlx5e_ipsec *ipsec;
820 struct mlx5e_profile {
821 void (*init)(struct mlx5_core_dev *mdev,
822 struct net_device *netdev,
823 const struct mlx5e_profile *profile, void *ppriv);
824 void (*cleanup)(struct mlx5e_priv *priv);
825 int (*init_rx)(struct mlx5e_priv *priv);
826 void (*cleanup_rx)(struct mlx5e_priv *priv);
827 int (*init_tx)(struct mlx5e_priv *priv);
828 void (*cleanup_tx)(struct mlx5e_priv *priv);
829 void (*enable)(struct mlx5e_priv *priv);
830 void (*disable)(struct mlx5e_priv *priv);
831 void (*update_stats)(struct mlx5e_priv *priv);
832 void (*update_carrier)(struct mlx5e_priv *priv);
833 int (*max_nch)(struct mlx5_core_dev *mdev);
835 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
836 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
838 void (*netdev_registered_init)(struct mlx5e_priv *priv);
839 void (*netdev_registered_remove)(struct mlx5e_priv *priv);
843 void mlx5e_build_ptys2ethtool_map(void);
845 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
846 void *accel_priv, select_queue_fallback_t fallback);
847 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
849 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
850 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
851 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
852 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
853 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
854 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
855 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
856 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
858 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
860 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
861 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
862 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
863 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
864 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
865 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
866 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
868 void mlx5e_rx_am(struct mlx5e_rq *rq);
869 void mlx5e_rx_am_work(struct work_struct *work);
870 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
872 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full);
874 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
875 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
876 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
877 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
878 int mlx5e_self_test_num(struct mlx5e_priv *priv);
879 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
881 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
883 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
884 struct ethtool_rxnfc *info, u32 *rule_locs);
885 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
886 struct ethtool_rx_flow_spec *fs);
887 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
889 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
890 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
891 void mlx5e_set_rx_mode_work(struct work_struct *work);
893 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
894 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
895 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
897 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
899 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
901 void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv);
902 void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv);
903 void mlx5e_timestamp_set(struct mlx5e_priv *priv);
905 struct mlx5e_redirect_rqt_param {
908 u32 rqn; /* Direct RQN (Non-RSS) */
911 struct mlx5e_channels *channels;
912 } rss; /* RSS data */
916 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
917 struct mlx5e_redirect_rqt_param rrp);
918 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
919 enum mlx5e_traffic_types tt,
920 void *tirc, bool inner);
922 int mlx5e_open_locked(struct net_device *netdev);
923 int mlx5e_close_locked(struct net_device *netdev);
925 int mlx5e_open_channels(struct mlx5e_priv *priv,
926 struct mlx5e_channels *chs);
927 void mlx5e_close_channels(struct mlx5e_channels *chs);
929 /* Function pointer to be used to modify WH settings while
932 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
933 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
934 struct mlx5e_channels *new_chs,
935 mlx5e_fp_hw_modify hw_modify);
936 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
937 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
939 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
941 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
943 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
945 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
947 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
948 struct mlx5e_params *params,
951 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
953 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
954 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
958 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
960 u16 pi = *pc & wq->sz_m1;
961 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
962 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
964 memset(cseg, 0, sizeof(*cseg));
966 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
967 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
975 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
976 void __iomem *uar_map,
977 struct mlx5_wqe_ctrl_seg *ctrl)
979 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
980 /* ensure wqe is visible to device before updating doorbell record */
983 *wq->db = cpu_to_be32(pc);
985 /* ensure doorbell record is visible to device before ringing the
990 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
993 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
995 struct mlx5_core_cq *mcq;
998 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
1001 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
1003 return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
1006 extern const struct ethtool_ops mlx5e_ethtool_ops;
1007 #ifdef CONFIG_MLX5_CORE_EN_DCB
1008 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1009 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1010 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1011 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1012 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1015 #ifndef CONFIG_RFS_ACCEL
1016 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
1021 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
1023 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
1028 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
1033 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
1034 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
1035 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
1036 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
1037 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1038 u16 rxq_index, u32 flow_id);
1041 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
1042 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1043 struct mlx5e_tir *tir, u32 *in, int inlen);
1044 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1045 struct mlx5e_tir *tir);
1046 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1047 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1048 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1050 /* common netdev helpers */
1051 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1053 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
1054 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1056 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
1057 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
1058 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
1059 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
1060 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1062 int mlx5e_create_ttc_table(struct mlx5e_priv *priv);
1063 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
1065 int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv);
1066 void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv);
1068 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
1069 u32 underlay_qpn, u32 *tisn);
1070 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1072 int mlx5e_create_tises(struct mlx5e_priv *priv);
1073 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
1074 int mlx5e_close(struct net_device *netdev);
1075 int mlx5e_open(struct net_device *netdev);
1076 void mlx5e_update_stats_work(struct work_struct *work);
1077 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
1079 /* ethtool helpers */
1080 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1081 struct ethtool_drvinfo *drvinfo);
1082 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1083 uint32_t stringset, uint8_t *data);
1084 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1085 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1086 struct ethtool_stats *stats, u64 *data);
1087 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1088 struct ethtool_ringparam *param);
1089 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1090 struct ethtool_ringparam *param);
1091 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1092 struct ethtool_channels *ch);
1093 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1094 struct ethtool_channels *ch);
1095 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1096 struct ethtool_coalesce *coal);
1097 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1098 struct ethtool_coalesce *coal);
1099 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1100 struct ethtool_ts_info *info);
1101 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1102 struct ethtool_flash *flash);
1104 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1107 /* mlx5e generic netdev management API */
1109 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1111 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1112 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1113 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1114 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1115 struct mlx5e_params *params,
1117 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1118 #endif /* __MLX5_EN_H__ */