drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  68 };
  69
  70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  71                                            struct mlx5_cmd_msg *in,
  72                                            struct mlx5_cmd_msg *out,
  73                                            void *uout, int uout_size,
  74                                            mlx5_cmd_cbk_t cbk,
  75                                            void *context, int page_queue)
  76 {
  77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  78         struct mlx5_cmd_work_ent *ent;
  79
  80         ent = kzalloc(sizeof(*ent), alloc_flags);
  81         if (!ent)
  82                 return ERR_PTR(-ENOMEM);
  83
  84         ent->in         = in;
  85         ent->out        = out;
  86         ent->uout       = uout;
  87         ent->uout_size  = uout_size;
  88         ent->callback   = cbk;
  89         ent->context    = context;
  90         ent->cmd        = cmd;
  91         ent->page_queue = page_queue;
  92
  93         return ent;
  94 }
  95
  96 static u8 alloc_token(struct mlx5_cmd *cmd)
  97 {
  98         u8 token;
  99
 100         spin_lock(&cmd->token_lock);
 101         cmd->token++;
 102         if (cmd->token == 0)
 103                 cmd->token++;
 104         token = cmd->token;
 105         spin_unlock(&cmd->token_lock);
 106
 107         return token;
 108 }
 109
 110 static int alloc_ent(struct mlx5_cmd *cmd)
 111 {
 112         unsigned long flags;
 113         int ret;
 114
 115         spin_lock_irqsave(&cmd->alloc_lock, flags);
 116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 117         if (ret < cmd->max_reg_cmds)
 118                 clear_bit(ret, &cmd->bitmask);
 119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 120
 121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 122 }
 123
 124 static void free_ent(struct mlx5_cmd *cmd, int idx)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&cmd->alloc_lock, flags);
 129         set_bit(idx, &cmd->bitmask);
 130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 131 }
 132
 133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 134 {
 135         return cmd->cmd_buf + (idx << cmd->log_stride);
 136 }
 137
 138 static u8 xor8_buf(void *buf, size_t offset, int len)
 139 {
 140         u8 *ptr = buf;
 141         u8 sum = 0;
 142         int i;
 143         int end = len + offset;
 144
 145         for (i = offset; i < end; i++)
 146                 sum ^= ptr[i];
 147
 148         return sum;
 149 }
 150
 151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 152 {
 153         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 154         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 155
 156         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 157                 return -EINVAL;
 158
 159         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 160                 return -EINVAL;
 161
 162         return 0;
 163 }
 164
 165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 166 {
 167         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 168         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 169
 170         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 171         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 172 }
 173
 174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 175 {
 176         struct mlx5_cmd_mailbox *next = msg->next;
 177         int size = msg->len;
 178         int blen = size - min_t(int, sizeof(msg->first.data), size);
 179         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 180                 / MLX5_CMD_DATA_BLOCK_SIZE;
 181         int i = 0;
 182
 183         for (i = 0; i < n && next; i++)  {
 184                 calc_block_sig(next->buf);
 185                 next = next->next;
 186         }
 187 }
 188
 189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 190 {
 191         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 192         if (csum) {
 193                 calc_chain_sig(ent->in);
 194                 calc_chain_sig(ent->out);
 195         }
 196 }
 197
 198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 199 {
 200         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 201         u8 own;
 202
 203         do {
 204                 own = ent->lay->status_own;
 205                 if (!(own & CMD_OWNER_HW)) {
 206                         ent->ret = 0;
 207                         return;
 208                 }
 209                 usleep_range(5000, 10000);
 210         } while (time_before(jiffies, poll_end));
 211
 212         ent->ret = -ETIMEDOUT;
 213 }
 214
 215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 216 {
 217         kfree(ent);
 218 }
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225         int size = ent->out->len;
 226         int blen = size - min_t(int, sizeof(ent->out->first.data), size);
 227         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 228                 / MLX5_CMD_DATA_BLOCK_SIZE;
 229         int i = 0;
 230
 231         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 232         if (sig != 0xff)
 233                 return -EINVAL;
 234
 235         for (i = 0; i < n && next; i++) {
 236                 err = verify_block_sig(next->buf);
 237                 if (err)
 238                         return err;
 239
 240                 next = next->next;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static void dump_buf(void *buf, int size, int data_only, int offset)
 247 {
 248         __be32 *p = buf;
 249         int i;
 250
 251         for (i = 0; i < size; i += 16) {
 252                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 253                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 254                          be32_to_cpu(p[3]));
 255                 p += 4;
 256                 offset += 16;
 257         }
 258         if (!data_only)
 259                 pr_debug("\n");
 260 }
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 282         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 283         case MLX5_CMD_OP_DEALLOC_PD:
 284         case MLX5_CMD_OP_DEALLOC_UAR:
 285         case MLX5_CMD_OP_DETACH_FROM_MCG:
 286         case MLX5_CMD_OP_DEALLOC_XRCD:
 287         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 288         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 289         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 290         case MLX5_CMD_OP_DESTROY_LAG:
 291         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 292         case MLX5_CMD_OP_DESTROY_TIR:
 293         case MLX5_CMD_OP_DESTROY_SQ:
 294         case MLX5_CMD_OP_DESTROY_RQ:
 295         case MLX5_CMD_OP_DESTROY_RMP:
 296         case MLX5_CMD_OP_DESTROY_TIS:
 297         case MLX5_CMD_OP_DESTROY_RQT:
 298         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 299         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 300         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 301         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 302         case MLX5_CMD_OP_2ERR_QP:
 303         case MLX5_CMD_OP_2RST_QP:
 304         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 305         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 306         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 307         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 308         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 309         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 310         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 311                 return MLX5_CMD_STAT_OK;
 312
 313         case MLX5_CMD_OP_QUERY_HCA_CAP:
 314         case MLX5_CMD_OP_QUERY_ADAPTER:
 315         case MLX5_CMD_OP_INIT_HCA:
 316         case MLX5_CMD_OP_ENABLE_HCA:
 317         case MLX5_CMD_OP_QUERY_PAGES:
 318         case MLX5_CMD_OP_SET_HCA_CAP:
 319         case MLX5_CMD_OP_QUERY_ISSI:
 320         case MLX5_CMD_OP_SET_ISSI:
 321         case MLX5_CMD_OP_CREATE_MKEY:
 322         case MLX5_CMD_OP_QUERY_MKEY:
 323         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 324         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 325         case MLX5_CMD_OP_CREATE_EQ:
 326         case MLX5_CMD_OP_QUERY_EQ:
 327         case MLX5_CMD_OP_GEN_EQE:
 328         case MLX5_CMD_OP_CREATE_CQ:
 329         case MLX5_CMD_OP_QUERY_CQ:
 330         case MLX5_CMD_OP_MODIFY_CQ:
 331         case MLX5_CMD_OP_CREATE_QP:
 332         case MLX5_CMD_OP_RST2INIT_QP:
 333         case MLX5_CMD_OP_INIT2RTR_QP:
 334         case MLX5_CMD_OP_RTR2RTS_QP:
 335         case MLX5_CMD_OP_RTS2RTS_QP:
 336         case MLX5_CMD_OP_SQERR2RTS_QP:
 337         case MLX5_CMD_OP_QUERY_QP:
 338         case MLX5_CMD_OP_SQD_RTS_QP:
 339         case MLX5_CMD_OP_INIT2INIT_QP:
 340         case MLX5_CMD_OP_CREATE_PSV:
 341         case MLX5_CMD_OP_CREATE_SRQ:
 342         case MLX5_CMD_OP_QUERY_SRQ:
 343         case MLX5_CMD_OP_ARM_RQ:
 344         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 345         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 346         case MLX5_CMD_OP_ARM_XRC_SRQ:
 347         case MLX5_CMD_OP_CREATE_DCT:
 348         case MLX5_CMD_OP_DRAIN_DCT:
 349         case MLX5_CMD_OP_QUERY_DCT:
 350         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 351         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 352         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 353         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 354         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 355         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 356         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 357         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 358         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 359         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 360         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 361         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 362         case MLX5_CMD_OP_QUERY_VNIC_ENV:
 363         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 364         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 365         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 366         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
 367         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 368         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 369         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 370         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 371         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 372         case MLX5_CMD_OP_ALLOC_PD:
 373         case MLX5_CMD_OP_ALLOC_UAR:
 374         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 375         case MLX5_CMD_OP_ACCESS_REG:
 376         case MLX5_CMD_OP_ATTACH_TO_MCG:
 377         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 378         case MLX5_CMD_OP_MAD_IFC:
 379         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 380         case MLX5_CMD_OP_SET_MAD_DEMUX:
 381         case MLX5_CMD_OP_NOP:
 382         case MLX5_CMD_OP_ALLOC_XRCD:
 383         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 384         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 385         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 386         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 387         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 388         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 389         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 390         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 391         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 392         case MLX5_CMD_OP_CREATE_LAG:
 393         case MLX5_CMD_OP_MODIFY_LAG:
 394         case MLX5_CMD_OP_QUERY_LAG:
 395         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 396         case MLX5_CMD_OP_CREATE_TIR:
 397         case MLX5_CMD_OP_MODIFY_TIR:
 398         case MLX5_CMD_OP_QUERY_TIR:
 399         case MLX5_CMD_OP_CREATE_SQ:
 400         case MLX5_CMD_OP_MODIFY_SQ:
 401         case MLX5_CMD_OP_QUERY_SQ:
 402         case MLX5_CMD_OP_CREATE_RQ:
 403         case MLX5_CMD_OP_MODIFY_RQ:
 404         case MLX5_CMD_OP_QUERY_RQ:
 405         case MLX5_CMD_OP_CREATE_RMP:
 406         case MLX5_CMD_OP_MODIFY_RMP:
 407         case MLX5_CMD_OP_QUERY_RMP:
 408         case MLX5_CMD_OP_CREATE_TIS:
 409         case MLX5_CMD_OP_MODIFY_TIS:
 410         case MLX5_CMD_OP_QUERY_TIS:
 411         case MLX5_CMD_OP_CREATE_RQT:
 412         case MLX5_CMD_OP_MODIFY_RQT:
 413         case MLX5_CMD_OP_QUERY_RQT:
 414
 415         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 416         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 417         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 418         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 419         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 420         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 421         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 422         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 423         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 424         case MLX5_CMD_OP_FPGA_CREATE_QP:
 425         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 426         case MLX5_CMD_OP_FPGA_QUERY_QP:
 427         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 428                 *status = MLX5_DRIVER_STATUS_ABORTED;
 429                 *synd = MLX5_DRIVER_SYND;
 430                 return -EIO;
 431         default:
 432                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 433                 return -EINVAL;
 434         }
 435 }
 436
 437 const char *mlx5_command_str(int command)
 438 {
 439 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 440
 441         switch (command) {
 442         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 443         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 444         MLX5_COMMAND_STR_CASE(INIT_HCA);
 445         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 446         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 447         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 448         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 449         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 450         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 451         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 452         MLX5_COMMAND_STR_CASE(SET_ISSI);
 453         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 454         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 455         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 456         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 457         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 458         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 459         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 460         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 461         MLX5_COMMAND_STR_CASE(GEN_EQE);
 462         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 463         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 464         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 465         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 466         MLX5_COMMAND_STR_CASE(CREATE_QP);
 467         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 468         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 469         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 470         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 471         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 472         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 473         MLX5_COMMAND_STR_CASE(2ERR_QP);
 474         MLX5_COMMAND_STR_CASE(2RST_QP);
 475         MLX5_COMMAND_STR_CASE(QUERY_QP);
 476         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 477         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 478         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 479         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 480         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 481         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 482         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 483         MLX5_COMMAND_STR_CASE(ARM_RQ);
 484         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 485         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 486         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 487         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 488         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 489         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 490         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 491         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 492         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 493         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 494         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 495         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 496         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 497         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 498         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 499         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 500         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 501         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 502         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 503         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 504         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 505         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
 506         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 507         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 508         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 509         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 510         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
 511         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 512         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 513         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 514         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 515         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 516         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 517         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 518         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 519         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 520         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 521         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 522         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 523         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 524         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 525         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 526         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 527         MLX5_COMMAND_STR_CASE(MAD_IFC);
 528         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 529         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 530         MLX5_COMMAND_STR_CASE(NOP);
 531         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 532         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 533         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 534         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 535         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 536         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 537         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 538         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 539         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 540         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 541         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 542         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 543         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 544         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 545         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 546         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 547         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 548         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 549         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 550         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 551         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 552         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 553         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 554         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 555         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 556         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 557         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 558         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 559         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 560         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 561         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 562         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 563         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 564         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 565         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 566         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 567         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 568         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 569         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 570         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 571         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 572         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 573         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 574         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 575         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 576         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 577         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 578         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 579         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 580         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 581         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 582         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 583         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 584         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 585         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 586         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 587         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 588         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 589         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 590         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 591         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
 592         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
 593         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 594         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 595         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 596         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 597         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 598         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 599         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 600         default: return "unknown command opcode";
 601         }
 602 }
 603
 604 static const char *cmd_status_str(u8 status)
 605 {
 606         switch (status) {
 607         case MLX5_CMD_STAT_OK:
 608                 return "OK";
 609         case MLX5_CMD_STAT_INT_ERR:
 610                 return "internal error";
 611         case MLX5_CMD_STAT_BAD_OP_ERR:
 612                 return "bad operation";
 613         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 614                 return "bad parameter";
 615         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 616                 return "bad system state";
 617         case MLX5_CMD_STAT_BAD_RES_ERR:
 618                 return "bad resource";
 619         case MLX5_CMD_STAT_RES_BUSY:
 620                 return "resource busy";
 621         case MLX5_CMD_STAT_LIM_ERR:
 622                 return "limits exceeded";
 623         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 624                 return "bad resource state";
 625         case MLX5_CMD_STAT_IX_ERR:
 626                 return "bad index";
 627         case MLX5_CMD_STAT_NO_RES_ERR:
 628                 return "no resources";
 629         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 630                 return "bad input length";
 631         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 632                 return "bad output length";
 633         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 634                 return "bad QP state";
 635         case MLX5_CMD_STAT_BAD_PKT_ERR:
 636                 return "bad packet (discarded)";
 637         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 638                 return "bad size too many outstanding CQEs";
 639         default:
 640                 return "unknown status";
 641         }
 642 }
 643
 644 static int cmd_status_to_err(u8 status)
 645 {
 646         switch (status) {
 647         case MLX5_CMD_STAT_OK:                          return 0;
 648         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 649         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 650         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 651         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 652         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 653         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 654         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 655         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 656         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 657         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 658         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 659         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 660         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 661         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 662         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 663         default:                                        return -EIO;
 664         }
 665 }
 666
 667 struct mlx5_ifc_mbox_out_bits {
 668         u8         status[0x8];
 669         u8         reserved_at_8[0x18];
 670
 671         u8         syndrome[0x20];
 672
 673         u8         reserved_at_40[0x40];
 674 };
 675
 676 struct mlx5_ifc_mbox_in_bits {
 677         u8         opcode[0x10];
 678         u8         reserved_at_10[0x10];
 679
 680         u8         reserved_at_20[0x10];
 681         u8         op_mod[0x10];
 682
 683         u8         reserved_at_40[0x40];
 684 };
 685
 686 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 687 {
 688         *status = MLX5_GET(mbox_out, out, status);
 689         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 690 }
 691
 692 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 693 {
 694         u32 syndrome;
 695         u8  status;
 696         u16 opcode;
 697         u16 op_mod;
 698
 699         mlx5_cmd_mbox_status(out, &status, &syndrome);
 700         if (!status)
 701                 return 0;
 702
 703         opcode = MLX5_GET(mbox_in, in, opcode);
 704         op_mod = MLX5_GET(mbox_in, in, op_mod);
 705
 706         mlx5_core_err(dev,
 707                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 708                       mlx5_command_str(opcode),
 709                       opcode, op_mod,
 710                       cmd_status_str(status),
 711                       status,
 712                       syndrome);
 713
 714         return cmd_status_to_err(status);
 715 }
 716
 717 static void dump_command(struct mlx5_core_dev *dev,
 718                          struct mlx5_cmd_work_ent *ent, int input)
 719 {
 720         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 721         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 722         struct mlx5_cmd_mailbox *next = msg->next;
 723         int data_only;
 724         u32 offset = 0;
 725         int dump_len;
 726
 727         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 728
 729         if (data_only)
 730                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 731                                    "dump command data %s(0x%x) %s\n",
 732                                    mlx5_command_str(op), op,
 733                                    input ? "INPUT" : "OUTPUT");
 734         else
 735                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 736                               mlx5_command_str(op), op,
 737                               input ? "INPUT" : "OUTPUT");
 738
 739         if (data_only) {
 740                 if (input) {
 741                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 742                         offset += sizeof(ent->lay->in);
 743                 } else {
 744                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 745                         offset += sizeof(ent->lay->out);
 746                 }
 747         } else {
 748                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 749                 offset += sizeof(*ent->lay);
 750         }
 751
 752         while (next && offset < msg->len) {
 753                 if (data_only) {
 754                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 755                         dump_buf(next->buf, dump_len, 1, offset);
 756                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 757                 } else {
 758                         mlx5_core_dbg(dev, "command block:\n");
 759                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 760                         offset += sizeof(struct mlx5_cmd_prot_block);
 761                 }
 762                 next = next->next;
 763         }
 764
 765         if (data_only)
 766                 pr_debug("\n");
 767 }
 768
 769 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 770 {
 771         return MLX5_GET(mbox_in, in->first.data, opcode);
 772 }
 773
 774 static void cb_timeout_handler(struct work_struct *work)
 775 {
 776         struct delayed_work *dwork = container_of(work, struct delayed_work,
 777                                                   work);
 778         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 779                                                      struct mlx5_cmd_work_ent,
 780                                                      cb_timeout_work);
 781         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 782                                                  cmd);
 783
 784         ent->ret = -ETIMEDOUT;
 785         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 786                        mlx5_command_str(msg_to_opcode(ent->in)),
 787                        msg_to_opcode(ent->in));
 788         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 789 }
 790
 791 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 792 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 793                               struct mlx5_cmd_msg *msg);
 794
 795 static void cmd_work_handler(struct work_struct *work)
 796 {
 797         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 798         struct mlx5_cmd *cmd = ent->cmd;
 799         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 800         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 801         struct mlx5_cmd_layout *lay;
 802         struct semaphore *sem;
 803         unsigned long flags;
 804         bool poll_cmd = ent->polling;
 805         int alloc_ret;
 806
 807         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 808         down(sem);
 809         if (!ent->page_queue) {
 810                 alloc_ret = alloc_ent(cmd);
 811                 if (alloc_ret < 0) {
 812                         mlx5_core_err(dev, "failed to allocate command entry\n");
 813                         if (ent->callback) {
 814                                 ent->callback(-EAGAIN, ent->context);
 815                                 mlx5_free_cmd_msg(dev, ent->out);
 816                                 free_msg(dev, ent->in);
 817                                 free_cmd(ent);
 818                         } else {
 819                                 ent->ret = -EAGAIN;
 820                                 complete(&ent->done);
 821                         }
 822                         up(sem);
 823                         return;
 824                 }
 825                 ent->idx = alloc_ret;
 826         } else {
 827                 ent->idx = cmd->max_reg_cmds;
 828                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 829                 clear_bit(ent->idx, &cmd->bitmask);
 830                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 831         }
 832
 833         cmd->ent_arr[ent->idx] = ent;
 834         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 835         lay = get_inst(cmd, ent->idx);
 836         ent->lay = lay;
 837         memset(lay, 0, sizeof(*lay));
 838         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 839         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 840         if (ent->in->next)
 841                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 842         lay->inlen = cpu_to_be32(ent->in->len);
 843         if (ent->out->next)
 844                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 845         lay->outlen = cpu_to_be32(ent->out->len);
 846         lay->type = MLX5_PCI_CMD_XPORT;
 847         lay->token = ent->token;
 848         lay->status_own = CMD_OWNER_HW;
 849         set_signature(ent, !cmd->checksum_disabled);
 850         dump_command(dev, ent, 1);
 851         ent->ts1 = ktime_get_ns();
 852
 853         if (ent->callback)
 854                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 855
 856         /* Skip sending command to fw if internal error */
 857         if (pci_channel_offline(dev->pdev) ||
 858             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 859                 u8 status = 0;
 860                 u32 drv_synd;
 861
 862                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 863                 MLX5_SET(mbox_out, ent->out, status, status);
 864                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 865
 866                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 867                 return;
 868         }
 869
 870         /* ring doorbell after the descriptor is valid */
 871         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 872         wmb();
 873         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 874         mmiowb();
 875         /* if not in polling don't use ent after this point */
 876         if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
 877                 poll_timeout(ent);
 878                 /* make sure we read the descriptor after ownership is SW */
 879                 rmb();
 880                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 881         }
 882 }
 883
 884 static const char *deliv_status_to_str(u8 status)
 885 {
 886         switch (status) {
 887         case MLX5_CMD_DELIVERY_STAT_OK:
 888                 return "no errors";
 889         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 890                 return "signature error";
 891         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 892                 return "token error";
 893         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 894                 return "bad block number";
 895         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 896                 return "output pointer not aligned to block size";
 897         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 898                 return "input pointer not aligned to block size";
 899         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 900                 return "firmware internal error";
 901         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 902                 return "command input length error";
 903         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 904                 return "command output length error";
 905         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 906                 return "reserved fields not cleared";
 907         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 908                 return "bad command descriptor type";
 909         default:
 910                 return "unknown status code";
 911         }
 912 }
 913
 914 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 915 {
 916         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 917         struct mlx5_cmd *cmd = &dev->cmd;
 918         int err;
 919
 920         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 921                 wait_for_completion(&ent->done);
 922         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 923                 ent->ret = -ETIMEDOUT;
 924                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 925         }
 926
 927         err = ent->ret;
 928
 929         if (err == -ETIMEDOUT) {
 930                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 931                                mlx5_command_str(msg_to_opcode(ent->in)),
 932                                msg_to_opcode(ent->in));
 933         }
 934         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 935                       err, deliv_status_to_str(ent->status), ent->status);
 936
 937         return err;
 938 }
 939
 940 /*  Notes:
 941  *    1. Callback functions may not sleep
 942  *    2. page queue commands do not support asynchrous completion
 943  */
 944 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 945                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 946                            mlx5_cmd_cbk_t callback,
 947                            void *context, int page_queue, u8 *status,
 948                            u8 token, bool force_polling)
 949 {
 950         struct mlx5_cmd *cmd = &dev->cmd;
 951         struct mlx5_cmd_work_ent *ent;
 952         struct mlx5_cmd_stats *stats;
 953         int err = 0;
 954         s64 ds;
 955         u16 op;
 956
 957         if (callback && page_queue)
 958                 return -EINVAL;
 959
 960         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 961                         page_queue);
 962         if (IS_ERR(ent))
 963                 return PTR_ERR(ent);
 964
 965         ent->token = token;
 966         ent->polling = force_polling;
 967
 968         if (!callback)
 969                 init_completion(&ent->done);
 970
 971         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
 972         INIT_WORK(&ent->work, cmd_work_handler);
 973         if (page_queue) {
 974                 cmd_work_handler(&ent->work);
 975         } else if (!queue_work(cmd->wq, &ent->work)) {
 976                 mlx5_core_warn(dev, "failed to queue work\n");
 977                 err = -ENOMEM;
 978                 goto out_free;
 979         }
 980
 981         if (callback)
 982                 goto out;
 983
 984         err = wait_func(dev, ent);
 985         if (err == -ETIMEDOUT)
 986                 goto out;
 987
 988         ds = ent->ts2 - ent->ts1;
 989         op = MLX5_GET(mbox_in, in->first.data, opcode);
 990         if (op < ARRAY_SIZE(cmd->stats)) {
 991                 stats = &cmd->stats[op];
 992                 spin_lock_irq(&stats->lock);
 993                 stats->sum += ds;
 994                 ++stats->n;
 995                 spin_unlock_irq(&stats->lock);
 996         }
 997         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 998                            "fw exec time for %s is %lld nsec\n",
 999                            mlx5_command_str(op), ds);
1000         *status = ent->status;
1001
1002 out_free:
1003         free_cmd(ent);
1004 out:
1005         return err;
1006 }
1007
1008 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1009                          size_t count, loff_t *pos)
1010 {
1011         struct mlx5_core_dev *dev = filp->private_data;
1012         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1013         char lbuf[3];
1014         int err;
1015
1016         if (!dbg->in_msg || !dbg->out_msg)
1017                 return -ENOMEM;
1018
1019         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
1020                 return -EFAULT;
1021
1022         lbuf[sizeof(lbuf) - 1] = 0;
1023
1024         if (strcmp(lbuf, "go"))
1025                 return -EINVAL;
1026
1027         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1028
1029         return err ? err : count;
1030 }
1031
1032 static const struct file_operations fops = {
1033         .owner  = THIS_MODULE,
1034         .open   = simple_open,
1035         .write  = dbg_write,
1036 };
1037
1038 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1039                             u8 token)
1040 {
1041         struct mlx5_cmd_prot_block *block;
1042         struct mlx5_cmd_mailbox *next;
1043         int copy;
1044
1045         if (!to || !from)
1046                 return -ENOMEM;
1047
1048         copy = min_t(int, size, sizeof(to->first.data));
1049         memcpy(to->first.data, from, copy);
1050         size -= copy;
1051         from += copy;
1052
1053         next = to->next;
1054         while (size) {
1055                 if (!next) {
1056                         /* this is a BUG */
1057                         return -ENOMEM;
1058                 }
1059
1060                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1061                 block = next->buf;
1062                 memcpy(block->data, from, copy);
1063                 from += copy;
1064                 size -= copy;
1065                 block->token = token;
1066                 next = next->next;
1067         }
1068
1069         return 0;
1070 }
1071
1072 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1073 {
1074         struct mlx5_cmd_prot_block *block;
1075         struct mlx5_cmd_mailbox *next;
1076         int copy;
1077
1078         if (!to || !from)
1079                 return -ENOMEM;
1080
1081         copy = min_t(int, size, sizeof(from->first.data));
1082         memcpy(to, from->first.data, copy);
1083         size -= copy;
1084         to += copy;
1085
1086         next = from->next;
1087         while (size) {
1088                 if (!next) {
1089                         /* this is a BUG */
1090                         return -ENOMEM;
1091                 }
1092
1093                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1094                 block = next->buf;
1095
1096                 memcpy(to, block->data, copy);
1097                 to += copy;
1098                 size -= copy;
1099                 next = next->next;
1100         }
1101
1102         return 0;
1103 }
1104
1105 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1106                                               gfp_t flags)
1107 {
1108         struct mlx5_cmd_mailbox *mailbox;
1109
1110         mailbox = kmalloc(sizeof(*mailbox), flags);
1111         if (!mailbox)
1112                 return ERR_PTR(-ENOMEM);
1113
1114         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1115                                        &mailbox->dma);
1116         if (!mailbox->buf) {
1117                 mlx5_core_dbg(dev, "failed allocation\n");
1118                 kfree(mailbox);
1119                 return ERR_PTR(-ENOMEM);
1120         }
1121         mailbox->next = NULL;
1122
1123         return mailbox;
1124 }
1125
1126 static void free_cmd_box(struct mlx5_core_dev *dev,
1127                          struct mlx5_cmd_mailbox *mailbox)
1128 {
1129         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1130         kfree(mailbox);
1131 }
1132
1133 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1134                                                gfp_t flags, int size,
1135                                                u8 token)
1136 {
1137         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1138         struct mlx5_cmd_prot_block *block;
1139         struct mlx5_cmd_msg *msg;
1140         int blen;
1141         int err;
1142         int n;
1143         int i;
1144
1145         msg = kzalloc(sizeof(*msg), flags);
1146         if (!msg)
1147                 return ERR_PTR(-ENOMEM);
1148
1149         blen = size - min_t(int, sizeof(msg->first.data), size);
1150         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1151
1152         for (i = 0; i < n; i++) {
1153                 tmp = alloc_cmd_box(dev, flags);
1154                 if (IS_ERR(tmp)) {
1155                         mlx5_core_warn(dev, "failed allocating block\n");
1156                         err = PTR_ERR(tmp);
1157                         goto err_alloc;
1158                 }
1159
1160                 block = tmp->buf;
1161                 tmp->next = head;
1162                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1163                 block->block_num = cpu_to_be32(n - i - 1);
1164                 block->token = token;
1165                 head = tmp;
1166         }
1167         msg->next = head;
1168         msg->len = size;
1169         return msg;
1170
1171 err_alloc:
1172         while (head) {
1173                 tmp = head->next;
1174                 free_cmd_box(dev, head);
1175                 head = tmp;
1176         }
1177         kfree(msg);
1178
1179         return ERR_PTR(err);
1180 }
1181
1182 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1183                               struct mlx5_cmd_msg *msg)
1184 {
1185         struct mlx5_cmd_mailbox *head = msg->next;
1186         struct mlx5_cmd_mailbox *next;
1187
1188         while (head) {
1189                 next = head->next;
1190                 free_cmd_box(dev, head);
1191                 head = next;
1192         }
1193         kfree(msg);
1194 }
1195
1196 static ssize_t data_write(struct file *filp, const char __user *buf,
1197                           size_t count, loff_t *pos)
1198 {
1199         struct mlx5_core_dev *dev = filp->private_data;
1200         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1201         void *ptr;
1202
1203         if (*pos != 0)
1204                 return -EINVAL;
1205
1206         kfree(dbg->in_msg);
1207         dbg->in_msg = NULL;
1208         dbg->inlen = 0;
1209         ptr = memdup_user(buf, count);
1210         if (IS_ERR(ptr))
1211                 return PTR_ERR(ptr);
1212         dbg->in_msg = ptr;
1213         dbg->inlen = count;
1214
1215         *pos = count;
1216
1217         return count;
1218 }
1219
1220 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1221                          loff_t *pos)
1222 {
1223         struct mlx5_core_dev *dev = filp->private_data;
1224         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1225         int copy;
1226
1227         if (*pos)
1228                 return 0;
1229
1230         if (!dbg->out_msg)
1231                 return -ENOMEM;
1232
1233         copy = min_t(int, count, dbg->outlen);
1234         if (copy_to_user(buf, dbg->out_msg, copy))
1235                 return -EFAULT;
1236
1237         *pos += copy;
1238
1239         return copy;
1240 }
1241
1242 static const struct file_operations dfops = {
1243         .owner  = THIS_MODULE,
1244         .open   = simple_open,
1245         .write  = data_write,
1246         .read   = data_read,
1247 };
1248
1249 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1250                            loff_t *pos)
1251 {
1252         struct mlx5_core_dev *dev = filp->private_data;
1253         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1254         char outlen[8];
1255         int err;
1256
1257         if (*pos)
1258                 return 0;
1259
1260         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1261         if (err < 0)
1262                 return err;
1263
1264         if (copy_to_user(buf, &outlen, err))
1265                 return -EFAULT;
1266
1267         *pos += err;
1268
1269         return err;
1270 }
1271
1272 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1273                             size_t count, loff_t *pos)
1274 {
1275         struct mlx5_core_dev *dev = filp->private_data;
1276         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1277         char outlen_str[8];
1278         int outlen;
1279         void *ptr;
1280         int err;
1281
1282         if (*pos != 0 || count > 6)
1283                 return -EINVAL;
1284
1285         kfree(dbg->out_msg);
1286         dbg->out_msg = NULL;
1287         dbg->outlen = 0;
1288
1289         if (copy_from_user(outlen_str, buf, count))
1290                 return -EFAULT;
1291
1292         outlen_str[7] = 0;
1293
1294         err = sscanf(outlen_str, "%d", &outlen);
1295         if (err < 0)
1296                 return err;
1297
1298         ptr = kzalloc(outlen, GFP_KERNEL);
1299         if (!ptr)
1300                 return -ENOMEM;
1301
1302         dbg->out_msg = ptr;
1303         dbg->outlen = outlen;
1304
1305         *pos = count;
1306
1307         return count;
1308 }
1309
1310 static const struct file_operations olfops = {
1311         .owner  = THIS_MODULE,
1312         .open   = simple_open,
1313         .write  = outlen_write,
1314         .read   = outlen_read,
1315 };
1316
1317 static void set_wqname(struct mlx5_core_dev *dev)
1318 {
1319         struct mlx5_cmd *cmd = &dev->cmd;
1320
1321         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1322                  dev_name(&dev->pdev->dev));
1323 }
1324
1325 static void clean_debug_files(struct mlx5_core_dev *dev)
1326 {
1327         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1328
1329         if (!mlx5_debugfs_root)
1330                 return;
1331
1332         mlx5_cmdif_debugfs_cleanup(dev);
1333         debugfs_remove_recursive(dbg->dbg_root);
1334 }
1335
1336 static int create_debugfs_files(struct mlx5_core_dev *dev)
1337 {
1338         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1339         int err = -ENOMEM;
1340
1341         if (!mlx5_debugfs_root)
1342                 return 0;
1343
1344         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1345         if (!dbg->dbg_root)
1346                 return err;
1347
1348         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1349                                           dev, &dfops);
1350         if (!dbg->dbg_in)
1351                 goto err_dbg;
1352
1353         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1354                                            dev, &dfops);
1355         if (!dbg->dbg_out)
1356                 goto err_dbg;
1357
1358         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1359                                               dev, &olfops);
1360         if (!dbg->dbg_outlen)
1361                 goto err_dbg;
1362
1363         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1364                                             &dbg->status);
1365         if (!dbg->dbg_status)
1366                 goto err_dbg;
1367
1368         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1369         if (!dbg->dbg_run)
1370                 goto err_dbg;
1371
1372         mlx5_cmdif_debugfs_init(dev);
1373
1374         return 0;
1375
1376 err_dbg:
1377         clean_debug_files(dev);
1378         return err;
1379 }
1380
1381 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1382 {
1383         struct mlx5_cmd *cmd = &dev->cmd;
1384         int i;
1385
1386         for (i = 0; i < cmd->max_reg_cmds; i++)
1387                 down(&cmd->sem);
1388         down(&cmd->pages_sem);
1389
1390         cmd->mode = mode;
1391
1392         up(&cmd->pages_sem);
1393         for (i = 0; i < cmd->max_reg_cmds; i++)
1394                 up(&cmd->sem);
1395 }
1396
1397 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1398 {
1399         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1400 }
1401
1402 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1403 {
1404         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1405 }
1406
1407 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1408 {
1409         unsigned long flags;
1410
1411         if (msg->parent) {
1412                 spin_lock_irqsave(&msg->parent->lock, flags);
1413                 list_add_tail(&msg->list, &msg->parent->head);
1414                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1415         } else {
1416                 mlx5_free_cmd_msg(dev, msg);
1417         }
1418 }
1419
1420 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1421 {
1422         struct mlx5_cmd *cmd = &dev->cmd;
1423         struct mlx5_cmd_work_ent *ent;
1424         mlx5_cmd_cbk_t callback;
1425         void *context;
1426         int err;
1427         int i;
1428         s64 ds;
1429         struct mlx5_cmd_stats *stats;
1430         unsigned long flags;
1431         unsigned long vector;
1432
1433         /* there can be at most 32 command queues */
1434         vector = vec & 0xffffffff;
1435         for (i = 0; i < (1 << cmd->log_sz); i++) {
1436                 if (test_bit(i, &vector)) {
1437                         struct semaphore *sem;
1438
1439                         ent = cmd->ent_arr[i];
1440
1441                         /* if we already completed the command, ignore it */
1442                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1443                                                 &ent->state)) {
1444                                 /* only real completion can free the cmd slot */
1445                                 if (!forced) {
1446                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1447                                                       ent->idx);
1448                                         free_ent(cmd, ent->idx);
1449                                         free_cmd(ent);
1450                                 }
1451                                 continue;
1452                         }
1453
1454                         if (ent->callback)
1455                                 cancel_delayed_work(&ent->cb_timeout_work);
1456                         if (ent->page_queue)
1457                                 sem = &cmd->pages_sem;
1458                         else
1459                                 sem = &cmd->sem;
1460                         ent->ts2 = ktime_get_ns();
1461                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1462                         dump_command(dev, ent, 0);
1463                         if (!ent->ret) {
1464                                 if (!cmd->checksum_disabled)
1465                                         ent->ret = verify_signature(ent);
1466                                 else
1467                                         ent->ret = 0;
1468                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1469                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1470                                 else
1471                                         ent->status = ent->lay->status_own >> 1;
1472
1473                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1474                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1475                         }
1476
1477                         /* only real completion will free the entry slot */
1478                         if (!forced)
1479                                 free_ent(cmd, ent->idx);
1480
1481                         if (ent->callback) {
1482                                 ds = ent->ts2 - ent->ts1;
1483                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1484                                         stats = &cmd->stats[ent->op];
1485                                         spin_lock_irqsave(&stats->lock, flags);
1486                                         stats->sum += ds;
1487                                         ++stats->n;
1488                                         spin_unlock_irqrestore(&stats->lock, flags);
1489                                 }
1490
1491                                 callback = ent->callback;
1492                                 context = ent->context;
1493                                 err = ent->ret;
1494                                 if (!err) {
1495                                         err = mlx5_copy_from_msg(ent->uout,
1496                                                                  ent->out,
1497                                                                  ent->uout_size);
1498
1499                                         err = err ? err : mlx5_cmd_check(dev,
1500                                                                         ent->in->first.data,
1501                                                                         ent->uout);
1502                                 }
1503
1504                                 mlx5_free_cmd_msg(dev, ent->out);
1505                                 free_msg(dev, ent->in);
1506
1507                                 err = err ? err : ent->status;
1508                                 if (!forced)
1509                                         free_cmd(ent);
1510                                 callback(err, context);
1511                         } else {
1512                                 complete(&ent->done);
1513                         }
1514                         up(sem);
1515                 }
1516         }
1517 }
1518 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1519
1520 static int status_to_err(u8 status)
1521 {
1522         return status ? -1 : 0; /* TBD more meaningful codes */
1523 }
1524
1525 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1526                                       gfp_t gfp)
1527 {
1528         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1529         struct cmd_msg_cache *ch = NULL;
1530         struct mlx5_cmd *cmd = &dev->cmd;
1531         int i;
1532
1533         if (in_size <= 16)
1534                 goto cache_miss;
1535
1536         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1537                 ch = &cmd->cache[i];
1538                 if (in_size > ch->max_inbox_size)
1539                         continue;
1540                 spin_lock_irq(&ch->lock);
1541                 if (list_empty(&ch->head)) {
1542                         spin_unlock_irq(&ch->lock);
1543                         continue;
1544                 }
1545                 msg = list_entry(ch->head.next, typeof(*msg), list);
1546                 /* For cached lists, we must explicitly state what is
1547                  * the real size
1548                  */
1549                 msg->len = in_size;
1550                 list_del(&msg->list);
1551                 spin_unlock_irq(&ch->lock);
1552                 break;
1553         }
1554
1555         if (!IS_ERR(msg))
1556                 return msg;
1557
1558 cache_miss:
1559         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1560         return msg;
1561 }
1562
1563 static int is_manage_pages(void *in)
1564 {
1565         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1566 }
1567
1568 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1569                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1570                     bool force_polling)
1571 {
1572         struct mlx5_cmd_msg *inb;
1573         struct mlx5_cmd_msg *outb;
1574         int pages_queue;
1575         gfp_t gfp;
1576         int err;
1577         u8 status = 0;
1578         u32 drv_synd;
1579         u8 token;
1580
1581         if (pci_channel_offline(dev->pdev) ||
1582             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1583                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1584
1585                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1586                 MLX5_SET(mbox_out, out, status, status);
1587                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1588                 return err;
1589         }
1590
1591         pages_queue = is_manage_pages(in);
1592         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1593
1594         inb = alloc_msg(dev, in_size, gfp);
1595         if (IS_ERR(inb)) {
1596                 err = PTR_ERR(inb);
1597                 return err;
1598         }
1599
1600         token = alloc_token(&dev->cmd);
1601
1602         err = mlx5_copy_to_msg(inb, in, in_size, token);
1603         if (err) {
1604                 mlx5_core_warn(dev, "err %d\n", err);
1605                 goto out_in;
1606         }
1607
1608         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1609         if (IS_ERR(outb)) {
1610                 err = PTR_ERR(outb);
1611                 goto out_in;
1612         }
1613
1614         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1615                               pages_queue, &status, token, force_polling);
1616         if (err)
1617                 goto out_out;
1618
1619         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1620         if (status) {
1621                 err = status_to_err(status);
1622                 goto out_out;
1623         }
1624
1625         if (!callback)
1626                 err = mlx5_copy_from_msg(out, outb, out_size);
1627
1628 out_out:
1629         if (!callback)
1630                 mlx5_free_cmd_msg(dev, outb);
1631
1632 out_in:
1633         if (!callback)
1634                 free_msg(dev, inb);
1635         return err;
1636 }
1637
1638 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1639                   int out_size)
1640 {
1641         int err;
1642
1643         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1644         return err ? : mlx5_cmd_check(dev, in, out);
1645 }
1646 EXPORT_SYMBOL(mlx5_cmd_exec);
1647
1648 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1649                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1650                      void *context)
1651 {
1652         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1653                         false);
1654 }
1655 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1656
1657 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1658                           void *out, int out_size)
1659 {
1660         int err;
1661
1662         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1663
1664         return err ? : mlx5_cmd_check(dev, in, out);
1665 }
1666 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1667
1668 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1669 {
1670         struct cmd_msg_cache *ch;
1671         struct mlx5_cmd_msg *msg;
1672         struct mlx5_cmd_msg *n;
1673         int i;
1674
1675         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1676                 ch = &dev->cmd.cache[i];
1677                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1678                         list_del(&msg->list);
1679                         mlx5_free_cmd_msg(dev, msg);
1680                 }
1681         }
1682 }
1683
1684 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1685         512, 32, 16, 8, 2
1686 };
1687
1688 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1689         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1690         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1691         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1692         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1693         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1694 };
1695
1696 static void create_msg_cache(struct mlx5_core_dev *dev)
1697 {
1698         struct mlx5_cmd *cmd = &dev->cmd;
1699         struct cmd_msg_cache *ch;
1700         struct mlx5_cmd_msg *msg;
1701         int i;
1702         int k;
1703
1704         /* Initialize and fill the caches with initial entries */
1705         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1706                 ch = &cmd->cache[k];
1707                 spin_lock_init(&ch->lock);
1708                 INIT_LIST_HEAD(&ch->head);
1709                 ch->num_ent = cmd_cache_num_ent[k];
1710                 ch->max_inbox_size = cmd_cache_ent_size[k];
1711                 for (i = 0; i < ch->num_ent; i++) {
1712                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1713                                                  ch->max_inbox_size, 0);
1714                         if (IS_ERR(msg))
1715                                 break;
1716                         msg->parent = ch;
1717                         list_add_tail(&msg->list, &ch->head);
1718                 }
1719         }
1720 }
1721
1722 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1723 {
1724         struct device *ddev = &dev->pdev->dev;
1725
1726         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1727                                                  &cmd->alloc_dma, GFP_KERNEL);
1728         if (!cmd->cmd_alloc_buf)
1729                 return -ENOMEM;
1730
1731         /* make sure it is aligned to 4K */
1732         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1733                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1734                 cmd->dma = cmd->alloc_dma;
1735                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1736                 return 0;
1737         }
1738
1739         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1740                           cmd->alloc_dma);
1741         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1742                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1743                                                  &cmd->alloc_dma, GFP_KERNEL);
1744         if (!cmd->cmd_alloc_buf)
1745                 return -ENOMEM;
1746
1747         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1748         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1749         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1750         return 0;
1751 }
1752
1753 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1754 {
1755         struct device *ddev = &dev->pdev->dev;
1756
1757         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1758                           cmd->alloc_dma);
1759 }
1760
1761 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1762 {
1763         int size = sizeof(struct mlx5_cmd_prot_block);
1764         int align = roundup_pow_of_two(size);
1765         struct mlx5_cmd *cmd = &dev->cmd;
1766         u32 cmd_h, cmd_l;
1767         u16 cmd_if_rev;
1768         int err;
1769         int i;
1770
1771         memset(cmd, 0, sizeof(*cmd));
1772         cmd_if_rev = cmdif_rev(dev);
1773         if (cmd_if_rev != CMD_IF_REV) {
1774                 dev_err(&dev->pdev->dev,
1775                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1776                         CMD_IF_REV, cmd_if_rev);
1777                 return -EINVAL;
1778         }
1779
1780         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1781                                     0);
1782         if (!cmd->pool)
1783                 return -ENOMEM;
1784
1785         err = alloc_cmd_page(dev, cmd);
1786         if (err)
1787                 goto err_free_pool;
1788
1789         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1790         cmd->log_sz = cmd_l >> 4 & 0xf;
1791         cmd->log_stride = cmd_l & 0xf;
1792         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1793                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1794                         1 << cmd->log_sz);
1795                 err = -EINVAL;
1796                 goto err_free_page;
1797         }
1798
1799         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1800                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1801                 err = -EINVAL;
1802                 goto err_free_page;
1803         }
1804
1805         cmd->checksum_disabled = 1;
1806         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1807         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1808
1809         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1810         if (cmd->cmdif_rev > CMD_IF_REV) {
1811                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1812                         CMD_IF_REV, cmd->cmdif_rev);
1813                 err = -EOPNOTSUPP;
1814                 goto err_free_page;
1815         }
1816
1817         spin_lock_init(&cmd->alloc_lock);
1818         spin_lock_init(&cmd->token_lock);
1819         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1820                 spin_lock_init(&cmd->stats[i].lock);
1821
1822         sema_init(&cmd->sem, cmd->max_reg_cmds);
1823         sema_init(&cmd->pages_sem, 1);
1824
1825         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1826         cmd_l = (u32)(cmd->dma);
1827         if (cmd_l & 0xfff) {
1828                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1829                 err = -ENOMEM;
1830                 goto err_free_page;
1831         }
1832
1833         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1834         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1835
1836         /* Make sure firmware sees the complete address before we proceed */
1837         wmb();
1838
1839         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1840
1841         cmd->mode = CMD_MODE_POLLING;
1842
1843         create_msg_cache(dev);
1844
1845         set_wqname(dev);
1846         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1847         if (!cmd->wq) {
1848                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1849                 err = -ENOMEM;
1850                 goto err_cache;
1851         }
1852
1853         err = create_debugfs_files(dev);
1854         if (err) {
1855                 err = -ENOMEM;
1856                 goto err_wq;
1857         }
1858
1859         return 0;
1860
1861 err_wq:
1862         destroy_workqueue(cmd->wq);
1863
1864 err_cache:
1865         destroy_msg_cache(dev);
1866
1867 err_free_page:
1868         free_cmd_page(dev, cmd);
1869
1870 err_free_pool:
1871         dma_pool_destroy(cmd->pool);
1872
1873         return err;
1874 }
1875 EXPORT_SYMBOL(mlx5_cmd_init);
1876
1877 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1878 {
1879         struct mlx5_cmd *cmd = &dev->cmd;
1880
1881         clean_debug_files(dev);
1882         destroy_workqueue(cmd->wq);
1883         destroy_msg_cache(dev);
1884         free_cmd_page(dev, cmd);
1885         dma_pool_destroy(cmd->pool);
1886 }
1887 EXPORT_SYMBOL(mlx5_cmd_cleanup);