drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/mlx5/eq.h>
  44 #include <linux/debugfs.h>
  45
  46 #include "mlx5_core.h"
  47 #include "lib/eq.h"
  48
  49 enum {
  50         CMD_IF_REV = 5,
  51 };
  52
  53 enum {
  54         CMD_MODE_POLLING,
  55         CMD_MODE_EVENTS
  56 };
  57
  58 enum {
  59         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  60         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  61         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  62         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  63         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  64         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  65         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  66         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  67         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  68         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  69         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  70 };
  71
  72 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  73                                            struct mlx5_cmd_msg *in,
  74                                            struct mlx5_cmd_msg *out,
  75                                            void *uout, int uout_size,
  76                                            mlx5_cmd_cbk_t cbk,
  77                                            void *context, int page_queue)
  78 {
  79         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  80         struct mlx5_cmd_work_ent *ent;
  81
  82         ent = kzalloc(sizeof(*ent), alloc_flags);
  83         if (!ent)
  84                 return ERR_PTR(-ENOMEM);
  85
  86         ent->in         = in;
  87         ent->out        = out;
  88         ent->uout       = uout;
  89         ent->uout_size  = uout_size;
  90         ent->callback   = cbk;
  91         ent->context    = context;
  92         ent->cmd        = cmd;
  93         ent->page_queue = page_queue;
  94
  95         return ent;
  96 }
  97
  98 static u8 alloc_token(struct mlx5_cmd *cmd)
  99 {
 100         u8 token;
 101
 102         spin_lock(&cmd->token_lock);
 103         cmd->token++;
 104         if (cmd->token == 0)
 105                 cmd->token++;
 106         token = cmd->token;
 107         spin_unlock(&cmd->token_lock);
 108
 109         return token;
 110 }
 111
 112 static int alloc_ent(struct mlx5_cmd *cmd)
 113 {
 114         unsigned long flags;
 115         int ret;
 116
 117         spin_lock_irqsave(&cmd->alloc_lock, flags);
 118         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 119         if (ret < cmd->max_reg_cmds)
 120                 clear_bit(ret, &cmd->bitmask);
 121         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 122
 123         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 124 }
 125
 126 static void free_ent(struct mlx5_cmd *cmd, int idx)
 127 {
 128         unsigned long flags;
 129
 130         spin_lock_irqsave(&cmd->alloc_lock, flags);
 131         set_bit(idx, &cmd->bitmask);
 132         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 133 }
 134
 135 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 136 {
 137         return cmd->cmd_buf + (idx << cmd->log_stride);
 138 }
 139
 140 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
 141 {
 142         int size = msg->len;
 143         int blen = size - min_t(int, sizeof(msg->first.data), size);
 144
 145         return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
 146 }
 147
 148 static u8 xor8_buf(void *buf, size_t offset, int len)
 149 {
 150         u8 *ptr = buf;
 151         u8 sum = 0;
 152         int i;
 153         int end = len + offset;
 154
 155         for (i = offset; i < end; i++)
 156                 sum ^= ptr[i];
 157
 158         return sum;
 159 }
 160
 161 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 162 {
 163         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 164         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 165
 166         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 167                 return -EINVAL;
 168
 169         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 170                 return -EINVAL;
 171
 172         return 0;
 173 }
 174
 175 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 176 {
 177         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 178         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 179
 180         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 181         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 182 }
 183
 184 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 185 {
 186         struct mlx5_cmd_mailbox *next = msg->next;
 187         int n = mlx5_calc_cmd_blocks(msg);
 188         int i = 0;
 189
 190         for (i = 0; i < n && next; i++)  {
 191                 calc_block_sig(next->buf);
 192                 next = next->next;
 193         }
 194 }
 195
 196 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 197 {
 198         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 199         if (csum) {
 200                 calc_chain_sig(ent->in);
 201                 calc_chain_sig(ent->out);
 202         }
 203 }
 204
 205 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 206 {
 207         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 208         u8 own;
 209
 210         do {
 211                 own = READ_ONCE(ent->lay->status_own);
 212                 if (!(own & CMD_OWNER_HW)) {
 213                         ent->ret = 0;
 214                         return;
 215                 }
 216                 cond_resched();
 217         } while (time_before(jiffies, poll_end));
 218
 219         ent->ret = -ETIMEDOUT;
 220 }
 221
 222 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 223 {
 224         kfree(ent);
 225 }
 226
 227 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 228 {
 229         struct mlx5_cmd_mailbox *next = ent->out->next;
 230         int n = mlx5_calc_cmd_blocks(ent->out);
 231         int err;
 232         u8 sig;
 233         int i = 0;
 234
 235         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 236         if (sig != 0xff)
 237                 return -EINVAL;
 238
 239         for (i = 0; i < n && next; i++) {
 240                 err = verify_block_sig(next->buf);
 241                 if (err)
 242                         return err;
 243
 244                 next = next->next;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static void dump_buf(void *buf, int size, int data_only, int offset)
 251 {
 252         __be32 *p = buf;
 253         int i;
 254
 255         for (i = 0; i < size; i += 16) {
 256                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 257                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 258                          be32_to_cpu(p[3]));
 259                 p += 4;
 260                 offset += 16;
 261         }
 262         if (!data_only)
 263                 pr_debug("\n");
 264 }
 265
 266 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 267                                        u32 *synd, u8 *status)
 268 {
 269         *synd = 0;
 270         *status = 0;
 271
 272         switch (op) {
 273         case MLX5_CMD_OP_TEARDOWN_HCA:
 274         case MLX5_CMD_OP_DISABLE_HCA:
 275         case MLX5_CMD_OP_MANAGE_PAGES:
 276         case MLX5_CMD_OP_DESTROY_MKEY:
 277         case MLX5_CMD_OP_DESTROY_EQ:
 278         case MLX5_CMD_OP_DESTROY_CQ:
 279         case MLX5_CMD_OP_DESTROY_QP:
 280         case MLX5_CMD_OP_DESTROY_PSV:
 281         case MLX5_CMD_OP_DESTROY_SRQ:
 282         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 283         case MLX5_CMD_OP_DESTROY_XRQ:
 284         case MLX5_CMD_OP_DESTROY_DCT:
 285         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 286         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 287         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 288         case MLX5_CMD_OP_DEALLOC_PD:
 289         case MLX5_CMD_OP_DEALLOC_UAR:
 290         case MLX5_CMD_OP_DETACH_FROM_MCG:
 291         case MLX5_CMD_OP_DEALLOC_XRCD:
 292         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 293         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 294         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 295         case MLX5_CMD_OP_DESTROY_LAG:
 296         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 297         case MLX5_CMD_OP_DESTROY_TIR:
 298         case MLX5_CMD_OP_DESTROY_SQ:
 299         case MLX5_CMD_OP_DESTROY_RQ:
 300         case MLX5_CMD_OP_DESTROY_RMP:
 301         case MLX5_CMD_OP_DESTROY_TIS:
 302         case MLX5_CMD_OP_DESTROY_RQT:
 303         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 304         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 305         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 306         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 307         case MLX5_CMD_OP_2ERR_QP:
 308         case MLX5_CMD_OP_2RST_QP:
 309         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 310         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 311         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 312         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 313         case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
 314         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 315         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 316         case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
 317         case MLX5_CMD_OP_DEALLOC_MEMIC:
 318         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 319         case MLX5_CMD_OP_QUERY_HOST_PARAMS:
 320                 return MLX5_CMD_STAT_OK;
 321
 322         case MLX5_CMD_OP_QUERY_HCA_CAP:
 323         case MLX5_CMD_OP_QUERY_ADAPTER:
 324         case MLX5_CMD_OP_INIT_HCA:
 325         case MLX5_CMD_OP_ENABLE_HCA:
 326         case MLX5_CMD_OP_QUERY_PAGES:
 327         case MLX5_CMD_OP_SET_HCA_CAP:
 328         case MLX5_CMD_OP_QUERY_ISSI:
 329         case MLX5_CMD_OP_SET_ISSI:
 330         case MLX5_CMD_OP_CREATE_MKEY:
 331         case MLX5_CMD_OP_QUERY_MKEY:
 332         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 333         case MLX5_CMD_OP_CREATE_EQ:
 334         case MLX5_CMD_OP_QUERY_EQ:
 335         case MLX5_CMD_OP_GEN_EQE:
 336         case MLX5_CMD_OP_CREATE_CQ:
 337         case MLX5_CMD_OP_QUERY_CQ:
 338         case MLX5_CMD_OP_MODIFY_CQ:
 339         case MLX5_CMD_OP_CREATE_QP:
 340         case MLX5_CMD_OP_RST2INIT_QP:
 341         case MLX5_CMD_OP_INIT2RTR_QP:
 342         case MLX5_CMD_OP_RTR2RTS_QP:
 343         case MLX5_CMD_OP_RTS2RTS_QP:
 344         case MLX5_CMD_OP_SQERR2RTS_QP:
 345         case MLX5_CMD_OP_QUERY_QP:
 346         case MLX5_CMD_OP_SQD_RTS_QP:
 347         case MLX5_CMD_OP_INIT2INIT_QP:
 348         case MLX5_CMD_OP_CREATE_PSV:
 349         case MLX5_CMD_OP_CREATE_SRQ:
 350         case MLX5_CMD_OP_QUERY_SRQ:
 351         case MLX5_CMD_OP_ARM_RQ:
 352         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 353         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 354         case MLX5_CMD_OP_ARM_XRC_SRQ:
 355         case MLX5_CMD_OP_CREATE_XRQ:
 356         case MLX5_CMD_OP_QUERY_XRQ:
 357         case MLX5_CMD_OP_ARM_XRQ:
 358         case MLX5_CMD_OP_CREATE_DCT:
 359         case MLX5_CMD_OP_DRAIN_DCT:
 360         case MLX5_CMD_OP_QUERY_DCT:
 361         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 362         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 363         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 364         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 365         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 366         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 367         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 368         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 369         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 370         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 371         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 372         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 373         case MLX5_CMD_OP_QUERY_VNIC_ENV:
 374         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 375         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 376         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 377         case MLX5_CMD_OP_SET_MONITOR_COUNTER:
 378         case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
 379         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
 380         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 381         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 382         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 383         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 384         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 385         case MLX5_CMD_OP_ALLOC_PD:
 386         case MLX5_CMD_OP_ALLOC_UAR:
 387         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 388         case MLX5_CMD_OP_ACCESS_REG:
 389         case MLX5_CMD_OP_ATTACH_TO_MCG:
 390         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 391         case MLX5_CMD_OP_MAD_IFC:
 392         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 393         case MLX5_CMD_OP_SET_MAD_DEMUX:
 394         case MLX5_CMD_OP_NOP:
 395         case MLX5_CMD_OP_ALLOC_XRCD:
 396         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 397         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 398         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 399         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 400         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 401         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 402         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 403         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 404         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 405         case MLX5_CMD_OP_CREATE_LAG:
 406         case MLX5_CMD_OP_MODIFY_LAG:
 407         case MLX5_CMD_OP_QUERY_LAG:
 408         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 409         case MLX5_CMD_OP_CREATE_TIR:
 410         case MLX5_CMD_OP_MODIFY_TIR:
 411         case MLX5_CMD_OP_QUERY_TIR:
 412         case MLX5_CMD_OP_CREATE_SQ:
 413         case MLX5_CMD_OP_MODIFY_SQ:
 414         case MLX5_CMD_OP_QUERY_SQ:
 415         case MLX5_CMD_OP_CREATE_RQ:
 416         case MLX5_CMD_OP_MODIFY_RQ:
 417         case MLX5_CMD_OP_QUERY_RQ:
 418         case MLX5_CMD_OP_CREATE_RMP:
 419         case MLX5_CMD_OP_MODIFY_RMP:
 420         case MLX5_CMD_OP_QUERY_RMP:
 421         case MLX5_CMD_OP_CREATE_TIS:
 422         case MLX5_CMD_OP_MODIFY_TIS:
 423         case MLX5_CMD_OP_QUERY_TIS:
 424         case MLX5_CMD_OP_CREATE_RQT:
 425         case MLX5_CMD_OP_MODIFY_RQT:
 426         case MLX5_CMD_OP_QUERY_RQT:
 427
 428         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 429         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 430         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 431         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 432         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 433         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 434         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 435         case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
 436         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 437         case MLX5_CMD_OP_FPGA_CREATE_QP:
 438         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 439         case MLX5_CMD_OP_FPGA_QUERY_QP:
 440         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 441         case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
 442         case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
 443         case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
 444         case MLX5_CMD_OP_ALLOC_MEMIC:
 445                 *status = MLX5_DRIVER_STATUS_ABORTED;
 446                 *synd = MLX5_DRIVER_SYND;
 447                 return -EIO;
 448         default:
 449                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 450                 return -EINVAL;
 451         }
 452 }
 453
 454 const char *mlx5_command_str(int command)
 455 {
 456 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 457
 458         switch (command) {
 459         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 460         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 461         MLX5_COMMAND_STR_CASE(INIT_HCA);
 462         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 463         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 464         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 465         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 466         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 467         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 468         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 469         MLX5_COMMAND_STR_CASE(SET_ISSI);
 470         MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
 471         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 472         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 473         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 474         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 475         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 476         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 477         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 478         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 479         MLX5_COMMAND_STR_CASE(GEN_EQE);
 480         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 481         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 482         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 483         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 484         MLX5_COMMAND_STR_CASE(CREATE_QP);
 485         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 486         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 487         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 488         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 489         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 490         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 491         MLX5_COMMAND_STR_CASE(2ERR_QP);
 492         MLX5_COMMAND_STR_CASE(2RST_QP);
 493         MLX5_COMMAND_STR_CASE(QUERY_QP);
 494         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 495         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 496         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 497         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 498         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 499         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 500         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 501         MLX5_COMMAND_STR_CASE(ARM_RQ);
 502         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 503         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 504         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 505         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 506         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 507         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 508         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 509         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 510         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 511         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 512         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 513         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 514         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 515         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 516         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 517         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 518         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 519         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 520         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 521         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 522         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 523         MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
 524         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 525         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 526         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 527         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 528         MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
 529         MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
 530         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
 531         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 532         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 533         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 534         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 535         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 536         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 537         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 538         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 539         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 540         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 541         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 542         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 543         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 544         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 545         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 546         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 547         MLX5_COMMAND_STR_CASE(MAD_IFC);
 548         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 549         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 550         MLX5_COMMAND_STR_CASE(NOP);
 551         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 552         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 553         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 554         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 555         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 556         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 557         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 558         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 559         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 560         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 561         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 562         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 563         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 564         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 565         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 566         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 567         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 568         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 569         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 570         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 571         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 572         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 573         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 574         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 575         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 576         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 577         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 578         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 579         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 580         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 581         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 582         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 583         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 584         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 585         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 586         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 587         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 588         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 589         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 590         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 591         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 592         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 593         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 594         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 595         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 596         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 597         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 598         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 599         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 600         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 601         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 602         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 603         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 604         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 605         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 606         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 607         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 608         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 609         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 610         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 611         MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
 612         MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
 613         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 614         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 615         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 616         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 617         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 618         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 619         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 620         MLX5_COMMAND_STR_CASE(CREATE_XRQ);
 621         MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
 622         MLX5_COMMAND_STR_CASE(QUERY_XRQ);
 623         MLX5_COMMAND_STR_CASE(ARM_XRQ);
 624         MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
 625         MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
 626         MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
 627         MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
 628         MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
 629         MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
 630         MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
 631         MLX5_COMMAND_STR_CASE(QUERY_HOST_PARAMS);
 632         default: return "unknown command opcode";
 633         }
 634 }
 635
 636 static const char *cmd_status_str(u8 status)
 637 {
 638         switch (status) {
 639         case MLX5_CMD_STAT_OK:
 640                 return "OK";
 641         case MLX5_CMD_STAT_INT_ERR:
 642                 return "internal error";
 643         case MLX5_CMD_STAT_BAD_OP_ERR:
 644                 return "bad operation";
 645         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 646                 return "bad parameter";
 647         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 648                 return "bad system state";
 649         case MLX5_CMD_STAT_BAD_RES_ERR:
 650                 return "bad resource";
 651         case MLX5_CMD_STAT_RES_BUSY:
 652                 return "resource busy";
 653         case MLX5_CMD_STAT_LIM_ERR:
 654                 return "limits exceeded";
 655         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 656                 return "bad resource state";
 657         case MLX5_CMD_STAT_IX_ERR:
 658                 return "bad index";
 659         case MLX5_CMD_STAT_NO_RES_ERR:
 660                 return "no resources";
 661         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 662                 return "bad input length";
 663         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 664                 return "bad output length";
 665         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 666                 return "bad QP state";
 667         case MLX5_CMD_STAT_BAD_PKT_ERR:
 668                 return "bad packet (discarded)";
 669         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 670                 return "bad size too many outstanding CQEs";
 671         default:
 672                 return "unknown status";
 673         }
 674 }
 675
 676 static int cmd_status_to_err(u8 status)
 677 {
 678         switch (status) {
 679         case MLX5_CMD_STAT_OK:                          return 0;
 680         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 681         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 682         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 683         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 684         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 685         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 686         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 687         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 688         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 689         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 690         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 691         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 692         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 693         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 694         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 695         default:                                        return -EIO;
 696         }
 697 }
 698
 699 struct mlx5_ifc_mbox_out_bits {
 700         u8         status[0x8];
 701         u8         reserved_at_8[0x18];
 702
 703         u8         syndrome[0x20];
 704
 705         u8         reserved_at_40[0x40];
 706 };
 707
 708 struct mlx5_ifc_mbox_in_bits {
 709         u8         opcode[0x10];
 710         u8         uid[0x10];
 711
 712         u8         reserved_at_20[0x10];
 713         u8         op_mod[0x10];
 714
 715         u8         reserved_at_40[0x40];
 716 };
 717
 718 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 719 {
 720         *status = MLX5_GET(mbox_out, out, status);
 721         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 722 }
 723
 724 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 725 {
 726         u32 syndrome;
 727         u8  status;
 728         u16 opcode;
 729         u16 op_mod;
 730         u16 uid;
 731
 732         mlx5_cmd_mbox_status(out, &status, &syndrome);
 733         if (!status)
 734                 return 0;
 735
 736         opcode = MLX5_GET(mbox_in, in, opcode);
 737         op_mod = MLX5_GET(mbox_in, in, op_mod);
 738         uid    = MLX5_GET(mbox_in, in, uid);
 739
 740         if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
 741                 mlx5_core_err_rl(dev,
 742                         "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 743                         mlx5_command_str(opcode), opcode, op_mod,
 744                         cmd_status_str(status), status, syndrome);
 745         else
 746                 mlx5_core_dbg(dev,
 747                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 748                       mlx5_command_str(opcode),
 749                       opcode, op_mod,
 750                       cmd_status_str(status),
 751                       status,
 752                       syndrome);
 753
 754         return cmd_status_to_err(status);
 755 }
 756
 757 static void dump_command(struct mlx5_core_dev *dev,
 758                          struct mlx5_cmd_work_ent *ent, int input)
 759 {
 760         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 761         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 762         struct mlx5_cmd_mailbox *next = msg->next;
 763         int n = mlx5_calc_cmd_blocks(msg);
 764         int data_only;
 765         u32 offset = 0;
 766         int dump_len;
 767         int i;
 768
 769         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 770
 771         if (data_only)
 772                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 773                                    "dump command data %s(0x%x) %s\n",
 774                                    mlx5_command_str(op), op,
 775                                    input ? "INPUT" : "OUTPUT");
 776         else
 777                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 778                               mlx5_command_str(op), op,
 779                               input ? "INPUT" : "OUTPUT");
 780
 781         if (data_only) {
 782                 if (input) {
 783                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 784                         offset += sizeof(ent->lay->in);
 785                 } else {
 786                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 787                         offset += sizeof(ent->lay->out);
 788                 }
 789         } else {
 790                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 791                 offset += sizeof(*ent->lay);
 792         }
 793
 794         for (i = 0; i < n && next; i++)  {
 795                 if (data_only) {
 796                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 797                         dump_buf(next->buf, dump_len, 1, offset);
 798                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 799                 } else {
 800                         mlx5_core_dbg(dev, "command block:\n");
 801                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 802                         offset += sizeof(struct mlx5_cmd_prot_block);
 803                 }
 804                 next = next->next;
 805         }
 806
 807         if (data_only)
 808                 pr_debug("\n");
 809 }
 810
 811 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 812 {
 813         return MLX5_GET(mbox_in, in->first.data, opcode);
 814 }
 815
 816 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
 817
 818 static void cb_timeout_handler(struct work_struct *work)
 819 {
 820         struct delayed_work *dwork = container_of(work, struct delayed_work,
 821                                                   work);
 822         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 823                                                      struct mlx5_cmd_work_ent,
 824                                                      cb_timeout_work);
 825         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 826                                                  cmd);
 827
 828         ent->ret = -ETIMEDOUT;
 829         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 830                        mlx5_command_str(msg_to_opcode(ent->in)),
 831                        msg_to_opcode(ent->in));
 832         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 833 }
 834
 835 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 836 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 837                               struct mlx5_cmd_msg *msg);
 838
 839 static void cmd_work_handler(struct work_struct *work)
 840 {
 841         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 842         struct mlx5_cmd *cmd = ent->cmd;
 843         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 844         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 845         struct mlx5_cmd_layout *lay;
 846         struct semaphore *sem;
 847         unsigned long flags;
 848         bool poll_cmd = ent->polling;
 849         int alloc_ret;
 850         int cmd_mode;
 851
 852         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 853         down(sem);
 854         if (!ent->page_queue) {
 855                 alloc_ret = alloc_ent(cmd);
 856                 if (alloc_ret < 0) {
 857                         mlx5_core_err(dev, "failed to allocate command entry\n");
 858                         if (ent->callback) {
 859                                 ent->callback(-EAGAIN, ent->context);
 860                                 mlx5_free_cmd_msg(dev, ent->out);
 861                                 free_msg(dev, ent->in);
 862                                 free_cmd(ent);
 863                         } else {
 864                                 ent->ret = -EAGAIN;
 865                                 complete(&ent->done);
 866                         }
 867                         up(sem);
 868                         return;
 869                 }
 870                 ent->idx = alloc_ret;
 871         } else {
 872                 ent->idx = cmd->max_reg_cmds;
 873                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 874                 clear_bit(ent->idx, &cmd->bitmask);
 875                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 876         }
 877
 878         cmd->ent_arr[ent->idx] = ent;
 879         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 880         lay = get_inst(cmd, ent->idx);
 881         ent->lay = lay;
 882         memset(lay, 0, sizeof(*lay));
 883         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 884         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 885         if (ent->in->next)
 886                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 887         lay->inlen = cpu_to_be32(ent->in->len);
 888         if (ent->out->next)
 889                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 890         lay->outlen = cpu_to_be32(ent->out->len);
 891         lay->type = MLX5_PCI_CMD_XPORT;
 892         lay->token = ent->token;
 893         lay->status_own = CMD_OWNER_HW;
 894         set_signature(ent, !cmd->checksum_disabled);
 895         dump_command(dev, ent, 1);
 896         ent->ts1 = ktime_get_ns();
 897         cmd_mode = cmd->mode;
 898
 899         if (ent->callback)
 900                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 901
 902         /* Skip sending command to fw if internal error */
 903         if (pci_channel_offline(dev->pdev) ||
 904             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 905                 u8 status = 0;
 906                 u32 drv_synd;
 907
 908                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 909                 MLX5_SET(mbox_out, ent->out, status, status);
 910                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 911
 912                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 913                 return;
 914         }
 915
 916         /* ring doorbell after the descriptor is valid */
 917         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 918         wmb();
 919         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 920         mmiowb();
 921         /* if not in polling don't use ent after this point */
 922         if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
 923                 poll_timeout(ent);
 924                 /* make sure we read the descriptor after ownership is SW */
 925                 rmb();
 926                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 927         }
 928 }
 929
 930 static const char *deliv_status_to_str(u8 status)
 931 {
 932         switch (status) {
 933         case MLX5_CMD_DELIVERY_STAT_OK:
 934                 return "no errors";
 935         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 936                 return "signature error";
 937         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 938                 return "token error";
 939         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 940                 return "bad block number";
 941         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 942                 return "output pointer not aligned to block size";
 943         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 944                 return "input pointer not aligned to block size";
 945         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 946                 return "firmware internal error";
 947         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 948                 return "command input length error";
 949         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 950                 return "command output length error";
 951         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 952                 return "reserved fields not cleared";
 953         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 954                 return "bad command descriptor type";
 955         default:
 956                 return "unknown status code";
 957         }
 958 }
 959
 960 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 961 {
 962         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 963         struct mlx5_cmd *cmd = &dev->cmd;
 964         int err;
 965
 966         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 967                 wait_for_completion(&ent->done);
 968         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 969                 ent->ret = -ETIMEDOUT;
 970                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 971         }
 972
 973         err = ent->ret;
 974
 975         if (err == -ETIMEDOUT) {
 976                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 977                                mlx5_command_str(msg_to_opcode(ent->in)),
 978                                msg_to_opcode(ent->in));
 979         }
 980         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 981                       err, deliv_status_to_str(ent->status), ent->status);
 982
 983         return err;
 984 }
 985
 986 /*  Notes:
 987  *    1. Callback functions may not sleep
 988  *    2. page queue commands do not support asynchrous completion
 989  */
 990 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 991                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 992                            mlx5_cmd_cbk_t callback,
 993                            void *context, int page_queue, u8 *status,
 994                            u8 token, bool force_polling)
 995 {
 996         struct mlx5_cmd *cmd = &dev->cmd;
 997         struct mlx5_cmd_work_ent *ent;
 998         struct mlx5_cmd_stats *stats;
 999         int err = 0;
1000         s64 ds;
1001         u16 op;
1002
1003         if (callback && page_queue)
1004                 return -EINVAL;
1005
1006         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
1007                         page_queue);
1008         if (IS_ERR(ent))
1009                 return PTR_ERR(ent);
1010
1011         ent->token = token;
1012         ent->polling = force_polling;
1013
1014         if (!callback)
1015                 init_completion(&ent->done);
1016
1017         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1018         INIT_WORK(&ent->work, cmd_work_handler);
1019         if (page_queue) {
1020                 cmd_work_handler(&ent->work);
1021         } else if (!queue_work(cmd->wq, &ent->work)) {
1022                 mlx5_core_warn(dev, "failed to queue work\n");
1023                 err = -ENOMEM;
1024                 goto out_free;
1025         }
1026
1027         if (callback)
1028                 goto out;
1029
1030         err = wait_func(dev, ent);
1031         if (err == -ETIMEDOUT)
1032                 goto out;
1033
1034         ds = ent->ts2 - ent->ts1;
1035         op = MLX5_GET(mbox_in, in->first.data, opcode);
1036         if (op < ARRAY_SIZE(cmd->stats)) {
1037                 stats = &cmd->stats[op];
1038                 spin_lock_irq(&stats->lock);
1039                 stats->sum += ds;
1040                 ++stats->n;
1041                 spin_unlock_irq(&stats->lock);
1042         }
1043         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1044                            "fw exec time for %s is %lld nsec\n",
1045                            mlx5_command_str(op), ds);
1046         *status = ent->status;
1047
1048 out_free:
1049         free_cmd(ent);
1050 out:
1051         return err;
1052 }
1053
1054 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1055                          size_t count, loff_t *pos)
1056 {
1057         struct mlx5_core_dev *dev = filp->private_data;
1058         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1059         char lbuf[3];
1060         int err;
1061
1062         if (!dbg->in_msg || !dbg->out_msg)
1063                 return -ENOMEM;
1064
1065         if (count < sizeof(lbuf) - 1)
1066                 return -EINVAL;
1067
1068         if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1069                 return -EFAULT;
1070
1071         lbuf[sizeof(lbuf) - 1] = 0;
1072
1073         if (strcmp(lbuf, "go"))
1074                 return -EINVAL;
1075
1076         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1077
1078         return err ? err : count;
1079 }
1080
1081 static const struct file_operations fops = {
1082         .owner  = THIS_MODULE,
1083         .open   = simple_open,
1084         .write  = dbg_write,
1085 };
1086
1087 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1088                             u8 token)
1089 {
1090         struct mlx5_cmd_prot_block *block;
1091         struct mlx5_cmd_mailbox *next;
1092         int copy;
1093
1094         if (!to || !from)
1095                 return -ENOMEM;
1096
1097         copy = min_t(int, size, sizeof(to->first.data));
1098         memcpy(to->first.data, from, copy);
1099         size -= copy;
1100         from += copy;
1101
1102         next = to->next;
1103         while (size) {
1104                 if (!next) {
1105                         /* this is a BUG */
1106                         return -ENOMEM;
1107                 }
1108
1109                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1110                 block = next->buf;
1111                 memcpy(block->data, from, copy);
1112                 from += copy;
1113                 size -= copy;
1114                 block->token = token;
1115                 next = next->next;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1122 {
1123         struct mlx5_cmd_prot_block *block;
1124         struct mlx5_cmd_mailbox *next;
1125         int copy;
1126
1127         if (!to || !from)
1128                 return -ENOMEM;
1129
1130         copy = min_t(int, size, sizeof(from->first.data));
1131         memcpy(to, from->first.data, copy);
1132         size -= copy;
1133         to += copy;
1134
1135         next = from->next;
1136         while (size) {
1137                 if (!next) {
1138                         /* this is a BUG */
1139                         return -ENOMEM;
1140                 }
1141
1142                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1143                 block = next->buf;
1144
1145                 memcpy(to, block->data, copy);
1146                 to += copy;
1147                 size -= copy;
1148                 next = next->next;
1149         }
1150
1151         return 0;
1152 }
1153
1154 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1155                                               gfp_t flags)
1156 {
1157         struct mlx5_cmd_mailbox *mailbox;
1158
1159         mailbox = kmalloc(sizeof(*mailbox), flags);
1160         if (!mailbox)
1161                 return ERR_PTR(-ENOMEM);
1162
1163         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1164                                        &mailbox->dma);
1165         if (!mailbox->buf) {
1166                 mlx5_core_dbg(dev, "failed allocation\n");
1167                 kfree(mailbox);
1168                 return ERR_PTR(-ENOMEM);
1169         }
1170         mailbox->next = NULL;
1171
1172         return mailbox;
1173 }
1174
1175 static void free_cmd_box(struct mlx5_core_dev *dev,
1176                          struct mlx5_cmd_mailbox *mailbox)
1177 {
1178         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1179         kfree(mailbox);
1180 }
1181
1182 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1183                                                gfp_t flags, int size,
1184                                                u8 token)
1185 {
1186         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1187         struct mlx5_cmd_prot_block *block;
1188         struct mlx5_cmd_msg *msg;
1189         int err;
1190         int n;
1191         int i;
1192
1193         msg = kzalloc(sizeof(*msg), flags);
1194         if (!msg)
1195                 return ERR_PTR(-ENOMEM);
1196
1197         msg->len = size;
1198         n = mlx5_calc_cmd_blocks(msg);
1199
1200         for (i = 0; i < n; i++) {
1201                 tmp = alloc_cmd_box(dev, flags);
1202                 if (IS_ERR(tmp)) {
1203                         mlx5_core_warn(dev, "failed allocating block\n");
1204                         err = PTR_ERR(tmp);
1205                         goto err_alloc;
1206                 }
1207
1208                 block = tmp->buf;
1209                 tmp->next = head;
1210                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1211                 block->block_num = cpu_to_be32(n - i - 1);
1212                 block->token = token;
1213                 head = tmp;
1214         }
1215         msg->next = head;
1216         return msg;
1217
1218 err_alloc:
1219         while (head) {
1220                 tmp = head->next;
1221                 free_cmd_box(dev, head);
1222                 head = tmp;
1223         }
1224         kfree(msg);
1225
1226         return ERR_PTR(err);
1227 }
1228
1229 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1230                               struct mlx5_cmd_msg *msg)
1231 {
1232         struct mlx5_cmd_mailbox *head = msg->next;
1233         struct mlx5_cmd_mailbox *next;
1234
1235         while (head) {
1236                 next = head->next;
1237                 free_cmd_box(dev, head);
1238                 head = next;
1239         }
1240         kfree(msg);
1241 }
1242
1243 static ssize_t data_write(struct file *filp, const char __user *buf,
1244                           size_t count, loff_t *pos)
1245 {
1246         struct mlx5_core_dev *dev = filp->private_data;
1247         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1248         void *ptr;
1249
1250         if (*pos != 0)
1251                 return -EINVAL;
1252
1253         kfree(dbg->in_msg);
1254         dbg->in_msg = NULL;
1255         dbg->inlen = 0;
1256         ptr = memdup_user(buf, count);
1257         if (IS_ERR(ptr))
1258                 return PTR_ERR(ptr);
1259         dbg->in_msg = ptr;
1260         dbg->inlen = count;
1261
1262         *pos = count;
1263
1264         return count;
1265 }
1266
1267 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1268                          loff_t *pos)
1269 {
1270         struct mlx5_core_dev *dev = filp->private_data;
1271         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1272
1273         if (!dbg->out_msg)
1274                 return -ENOMEM;
1275
1276         return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1277                                        dbg->outlen);
1278 }
1279
1280 static const struct file_operations dfops = {
1281         .owner  = THIS_MODULE,
1282         .open   = simple_open,
1283         .write  = data_write,
1284         .read   = data_read,
1285 };
1286
1287 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1288                            loff_t *pos)
1289 {
1290         struct mlx5_core_dev *dev = filp->private_data;
1291         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1292         char outlen[8];
1293         int err;
1294
1295         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1296         if (err < 0)
1297                 return err;
1298
1299         return simple_read_from_buffer(buf, count, pos, outlen, err);
1300 }
1301
1302 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1303                             size_t count, loff_t *pos)
1304 {
1305         struct mlx5_core_dev *dev = filp->private_data;
1306         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1307         char outlen_str[8] = {0};
1308         int outlen;
1309         void *ptr;
1310         int err;
1311
1312         if (*pos != 0 || count > 6)
1313                 return -EINVAL;
1314
1315         kfree(dbg->out_msg);
1316         dbg->out_msg = NULL;
1317         dbg->outlen = 0;
1318
1319         if (copy_from_user(outlen_str, buf, count))
1320                 return -EFAULT;
1321
1322         err = sscanf(outlen_str, "%d", &outlen);
1323         if (err < 0)
1324                 return err;
1325
1326         ptr = kzalloc(outlen, GFP_KERNEL);
1327         if (!ptr)
1328                 return -ENOMEM;
1329
1330         dbg->out_msg = ptr;
1331         dbg->outlen = outlen;
1332
1333         *pos = count;
1334
1335         return count;
1336 }
1337
1338 static const struct file_operations olfops = {
1339         .owner  = THIS_MODULE,
1340         .open   = simple_open,
1341         .write  = outlen_write,
1342         .read   = outlen_read,
1343 };
1344
1345 static void set_wqname(struct mlx5_core_dev *dev)
1346 {
1347         struct mlx5_cmd *cmd = &dev->cmd;
1348
1349         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1350                  dev_name(&dev->pdev->dev));
1351 }
1352
1353 static void clean_debug_files(struct mlx5_core_dev *dev)
1354 {
1355         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1356
1357         if (!mlx5_debugfs_root)
1358                 return;
1359
1360         mlx5_cmdif_debugfs_cleanup(dev);
1361         debugfs_remove_recursive(dbg->dbg_root);
1362 }
1363
1364 static int create_debugfs_files(struct mlx5_core_dev *dev)
1365 {
1366         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1367         int err = -ENOMEM;
1368
1369         if (!mlx5_debugfs_root)
1370                 return 0;
1371
1372         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1373         if (!dbg->dbg_root)
1374                 return err;
1375
1376         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1377                                           dev, &dfops);
1378         if (!dbg->dbg_in)
1379                 goto err_dbg;
1380
1381         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1382                                            dev, &dfops);
1383         if (!dbg->dbg_out)
1384                 goto err_dbg;
1385
1386         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1387                                               dev, &olfops);
1388         if (!dbg->dbg_outlen)
1389                 goto err_dbg;
1390
1391         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1392                                             &dbg->status);
1393         if (!dbg->dbg_status)
1394                 goto err_dbg;
1395
1396         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1397         if (!dbg->dbg_run)
1398                 goto err_dbg;
1399
1400         mlx5_cmdif_debugfs_init(dev);
1401
1402         return 0;
1403
1404 err_dbg:
1405         clean_debug_files(dev);
1406         return err;
1407 }
1408
1409 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1410 {
1411         struct mlx5_cmd *cmd = &dev->cmd;
1412         int i;
1413
1414         for (i = 0; i < cmd->max_reg_cmds; i++)
1415                 down(&cmd->sem);
1416         down(&cmd->pages_sem);
1417
1418         cmd->mode = mode;
1419
1420         up(&cmd->pages_sem);
1421         for (i = 0; i < cmd->max_reg_cmds; i++)
1422                 up(&cmd->sem);
1423 }
1424
1425 static int cmd_comp_notifier(struct notifier_block *nb,
1426                              unsigned long type, void *data)
1427 {
1428         struct mlx5_core_dev *dev;
1429         struct mlx5_cmd *cmd;
1430         struct mlx5_eqe *eqe;
1431
1432         cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1433         dev = container_of(cmd, struct mlx5_core_dev, cmd);
1434         eqe = data;
1435
1436         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1437
1438         return NOTIFY_OK;
1439 }
1440 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1441 {
1442         MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1443         mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1444         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1445 }
1446
1447 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1448 {
1449         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1450         mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1451 }
1452
1453 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1454 {
1455         unsigned long flags;
1456
1457         if (msg->parent) {
1458                 spin_lock_irqsave(&msg->parent->lock, flags);
1459                 list_add_tail(&msg->list, &msg->parent->head);
1460                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1461         } else {
1462                 mlx5_free_cmd_msg(dev, msg);
1463         }
1464 }
1465
1466 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1467 {
1468         struct mlx5_cmd *cmd = &dev->cmd;
1469         struct mlx5_cmd_work_ent *ent;
1470         mlx5_cmd_cbk_t callback;
1471         void *context;
1472         int err;
1473         int i;
1474         s64 ds;
1475         struct mlx5_cmd_stats *stats;
1476         unsigned long flags;
1477         unsigned long vector;
1478
1479         /* there can be at most 32 command queues */
1480         vector = vec & 0xffffffff;
1481         for (i = 0; i < (1 << cmd->log_sz); i++) {
1482                 if (test_bit(i, &vector)) {
1483                         struct semaphore *sem;
1484
1485                         ent = cmd->ent_arr[i];
1486
1487                         /* if we already completed the command, ignore it */
1488                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1489                                                 &ent->state)) {
1490                                 /* only real completion can free the cmd slot */
1491                                 if (!forced) {
1492                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1493                                                       ent->idx);
1494                                         free_ent(cmd, ent->idx);
1495                                         free_cmd(ent);
1496                                 }
1497                                 continue;
1498                         }
1499
1500                         if (ent->callback)
1501                                 cancel_delayed_work(&ent->cb_timeout_work);
1502                         if (ent->page_queue)
1503                                 sem = &cmd->pages_sem;
1504                         else
1505                                 sem = &cmd->sem;
1506                         ent->ts2 = ktime_get_ns();
1507                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1508                         dump_command(dev, ent, 0);
1509                         if (!ent->ret) {
1510                                 if (!cmd->checksum_disabled)
1511                                         ent->ret = verify_signature(ent);
1512                                 else
1513                                         ent->ret = 0;
1514                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1515                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1516                                 else
1517                                         ent->status = ent->lay->status_own >> 1;
1518
1519                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1520                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1521                         }
1522
1523                         /* only real completion will free the entry slot */
1524                         if (!forced)
1525                                 free_ent(cmd, ent->idx);
1526
1527                         if (ent->callback) {
1528                                 ds = ent->ts2 - ent->ts1;
1529                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1530                                         stats = &cmd->stats[ent->op];
1531                                         spin_lock_irqsave(&stats->lock, flags);
1532                                         stats->sum += ds;
1533                                         ++stats->n;
1534                                         spin_unlock_irqrestore(&stats->lock, flags);
1535                                 }
1536
1537                                 callback = ent->callback;
1538                                 context = ent->context;
1539                                 err = ent->ret;
1540                                 if (!err) {
1541                                         err = mlx5_copy_from_msg(ent->uout,
1542                                                                  ent->out,
1543                                                                  ent->uout_size);
1544
1545                                         err = err ? err : mlx5_cmd_check(dev,
1546                                                                         ent->in->first.data,
1547                                                                         ent->uout);
1548                                 }
1549
1550                                 mlx5_free_cmd_msg(dev, ent->out);
1551                                 free_msg(dev, ent->in);
1552
1553                                 err = err ? err : ent->status;
1554                                 if (!forced)
1555                                         free_cmd(ent);
1556                                 callback(err, context);
1557                         } else {
1558                                 complete(&ent->done);
1559                         }
1560                         up(sem);
1561                 }
1562         }
1563 }
1564
1565 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1566 {
1567         unsigned long flags;
1568         u64 vector;
1569
1570         /* wait for pending handlers to complete */
1571         mlx5_eq_synchronize_cmd_irq(dev);
1572         spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1573         vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1574         if (!vector)
1575                 goto no_trig;
1576
1577         vector |= MLX5_TRIGGERED_CMD_COMP;
1578         spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1579
1580         mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1581         mlx5_cmd_comp_handler(dev, vector, true);
1582         return;
1583
1584 no_trig:
1585         spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1586 }
1587
1588 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1589 {
1590         struct mlx5_cmd *cmd = &dev->cmd;
1591         int i;
1592
1593         for (i = 0; i < cmd->max_reg_cmds; i++)
1594                 while (down_trylock(&cmd->sem))
1595                         mlx5_cmd_trigger_completions(dev);
1596
1597         while (down_trylock(&cmd->pages_sem))
1598                 mlx5_cmd_trigger_completions(dev);
1599
1600         /* Unlock cmdif */
1601         up(&cmd->pages_sem);
1602         for (i = 0; i < cmd->max_reg_cmds; i++)
1603                 up(&cmd->sem);
1604 }
1605
1606 static int status_to_err(u8 status)
1607 {
1608         return status ? -1 : 0; /* TBD more meaningful codes */
1609 }
1610
1611 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1612                                       gfp_t gfp)
1613 {
1614         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1615         struct cmd_msg_cache *ch = NULL;
1616         struct mlx5_cmd *cmd = &dev->cmd;
1617         int i;
1618
1619         if (in_size <= 16)
1620                 goto cache_miss;
1621
1622         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1623                 ch = &cmd->cache[i];
1624                 if (in_size > ch->max_inbox_size)
1625                         continue;
1626                 spin_lock_irq(&ch->lock);
1627                 if (list_empty(&ch->head)) {
1628                         spin_unlock_irq(&ch->lock);
1629                         continue;
1630                 }
1631                 msg = list_entry(ch->head.next, typeof(*msg), list);
1632                 /* For cached lists, we must explicitly state what is
1633                  * the real size
1634                  */
1635                 msg->len = in_size;
1636                 list_del(&msg->list);
1637                 spin_unlock_irq(&ch->lock);
1638                 break;
1639         }
1640
1641         if (!IS_ERR(msg))
1642                 return msg;
1643
1644 cache_miss:
1645         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1646         return msg;
1647 }
1648
1649 static int is_manage_pages(void *in)
1650 {
1651         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1652 }
1653
1654 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1655                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1656                     bool force_polling)
1657 {
1658         struct mlx5_cmd_msg *inb;
1659         struct mlx5_cmd_msg *outb;
1660         int pages_queue;
1661         gfp_t gfp;
1662         int err;
1663         u8 status = 0;
1664         u32 drv_synd;
1665         u8 token;
1666
1667         if (pci_channel_offline(dev->pdev) ||
1668             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1669                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1670
1671                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1672                 MLX5_SET(mbox_out, out, status, status);
1673                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1674                 return err;
1675         }
1676
1677         pages_queue = is_manage_pages(in);
1678         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1679
1680         inb = alloc_msg(dev, in_size, gfp);
1681         if (IS_ERR(inb)) {
1682                 err = PTR_ERR(inb);
1683                 return err;
1684         }
1685
1686         token = alloc_token(&dev->cmd);
1687
1688         err = mlx5_copy_to_msg(inb, in, in_size, token);
1689         if (err) {
1690                 mlx5_core_warn(dev, "err %d\n", err);
1691                 goto out_in;
1692         }
1693
1694         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1695         if (IS_ERR(outb)) {
1696                 err = PTR_ERR(outb);
1697                 goto out_in;
1698         }
1699
1700         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1701                               pages_queue, &status, token, force_polling);
1702         if (err)
1703                 goto out_out;
1704
1705         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1706         if (status) {
1707                 err = status_to_err(status);
1708                 goto out_out;
1709         }
1710
1711         if (!callback)
1712                 err = mlx5_copy_from_msg(out, outb, out_size);
1713
1714 out_out:
1715         if (!callback)
1716                 mlx5_free_cmd_msg(dev, outb);
1717
1718 out_in:
1719         if (!callback)
1720                 free_msg(dev, inb);
1721         return err;
1722 }
1723
1724 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1725                   int out_size)
1726 {
1727         int err;
1728
1729         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1730         return err ? : mlx5_cmd_check(dev, in, out);
1731 }
1732 EXPORT_SYMBOL(mlx5_cmd_exec);
1733
1734 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1735                              struct mlx5_async_ctx *ctx)
1736 {
1737         ctx->dev = dev;
1738         /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
1739         atomic_set(&ctx->num_inflight, 1);
1740         init_waitqueue_head(&ctx->wait);
1741 }
1742 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
1743
1744 /**
1745  * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
1746  * @ctx: The ctx to clean
1747  *
1748  * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
1749  * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
1750  * the call mlx5_cleanup_async_ctx().
1751  */
1752 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
1753 {
1754         atomic_dec(&ctx->num_inflight);
1755         wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0);
1756 }
1757 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
1758
1759 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
1760 {
1761         struct mlx5_async_work *work = _work;
1762         struct mlx5_async_ctx *ctx = work->ctx;
1763
1764         work->user_callback(status, work);
1765         if (atomic_dec_and_test(&ctx->num_inflight))
1766                 wake_up(&ctx->wait);
1767 }
1768
1769 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1770                      void *out, int out_size, mlx5_async_cbk_t callback,
1771                      struct mlx5_async_work *work)
1772 {
1773         int ret;
1774
1775         work->ctx = ctx;
1776         work->user_callback = callback;
1777         if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
1778                 return -EIO;
1779         ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
1780                        mlx5_cmd_exec_cb_handler, work, false);
1781         if (ret && atomic_dec_and_test(&ctx->num_inflight))
1782                 wake_up(&ctx->wait);
1783
1784         return ret;
1785 }
1786 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1787
1788 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1789                           void *out, int out_size)
1790 {
1791         int err;
1792
1793         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1794
1795         return err ? : mlx5_cmd_check(dev, in, out);
1796 }
1797 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1798
1799 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1800 {
1801         struct cmd_msg_cache *ch;
1802         struct mlx5_cmd_msg *msg;
1803         struct mlx5_cmd_msg *n;
1804         int i;
1805
1806         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1807                 ch = &dev->cmd.cache[i];
1808                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1809                         list_del(&msg->list);
1810                         mlx5_free_cmd_msg(dev, msg);
1811                 }
1812         }
1813 }
1814
1815 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1816         512, 32, 16, 8, 2
1817 };
1818
1819 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1820         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1821         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1822         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1823         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1824         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1825 };
1826
1827 static void create_msg_cache(struct mlx5_core_dev *dev)
1828 {
1829         struct mlx5_cmd *cmd = &dev->cmd;
1830         struct cmd_msg_cache *ch;
1831         struct mlx5_cmd_msg *msg;
1832         int i;
1833         int k;
1834
1835         /* Initialize and fill the caches with initial entries */
1836         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1837                 ch = &cmd->cache[k];
1838                 spin_lock_init(&ch->lock);
1839                 INIT_LIST_HEAD(&ch->head);
1840                 ch->num_ent = cmd_cache_num_ent[k];
1841                 ch->max_inbox_size = cmd_cache_ent_size[k];
1842                 for (i = 0; i < ch->num_ent; i++) {
1843                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1844                                                  ch->max_inbox_size, 0);
1845                         if (IS_ERR(msg))
1846                                 break;
1847                         msg->parent = ch;
1848                         list_add_tail(&msg->list, &ch->head);
1849                 }
1850         }
1851 }
1852
1853 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1854 {
1855         struct device *ddev = &dev->pdev->dev;
1856
1857         cmd->cmd_alloc_buf = dma_alloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1858                                                 &cmd->alloc_dma, GFP_KERNEL);
1859         if (!cmd->cmd_alloc_buf)
1860                 return -ENOMEM;
1861
1862         /* make sure it is aligned to 4K */
1863         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1864                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1865                 cmd->dma = cmd->alloc_dma;
1866                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1867                 return 0;
1868         }
1869
1870         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1871                           cmd->alloc_dma);
1872         cmd->cmd_alloc_buf = dma_alloc_coherent(ddev,
1873                                                 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1874                                                 &cmd->alloc_dma, GFP_KERNEL);
1875         if (!cmd->cmd_alloc_buf)
1876                 return -ENOMEM;
1877
1878         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1879         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1880         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1881         return 0;
1882 }
1883
1884 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1885 {
1886         struct device *ddev = &dev->pdev->dev;
1887
1888         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1889                           cmd->alloc_dma);
1890 }
1891
1892 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1893 {
1894         int size = sizeof(struct mlx5_cmd_prot_block);
1895         int align = roundup_pow_of_two(size);
1896         struct mlx5_cmd *cmd = &dev->cmd;
1897         u32 cmd_h, cmd_l;
1898         u16 cmd_if_rev;
1899         int err;
1900         int i;
1901
1902         memset(cmd, 0, sizeof(*cmd));
1903         cmd_if_rev = cmdif_rev(dev);
1904         if (cmd_if_rev != CMD_IF_REV) {
1905                 dev_err(&dev->pdev->dev,
1906                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1907                         CMD_IF_REV, cmd_if_rev);
1908                 return -EINVAL;
1909         }
1910
1911         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1912                                     0);
1913         if (!cmd->pool)
1914                 return -ENOMEM;
1915
1916         err = alloc_cmd_page(dev, cmd);
1917         if (err)
1918                 goto err_free_pool;
1919
1920         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1921         cmd->log_sz = cmd_l >> 4 & 0xf;
1922         cmd->log_stride = cmd_l & 0xf;
1923         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1924                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1925                         1 << cmd->log_sz);
1926                 err = -EINVAL;
1927                 goto err_free_page;
1928         }
1929
1930         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1931                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1932                 err = -EINVAL;
1933                 goto err_free_page;
1934         }
1935
1936         cmd->checksum_disabled = 1;
1937         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1938         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1939
1940         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1941         if (cmd->cmdif_rev > CMD_IF_REV) {
1942                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1943                         CMD_IF_REV, cmd->cmdif_rev);
1944                 err = -EOPNOTSUPP;
1945                 goto err_free_page;
1946         }
1947
1948         spin_lock_init(&cmd->alloc_lock);
1949         spin_lock_init(&cmd->token_lock);
1950         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1951                 spin_lock_init(&cmd->stats[i].lock);
1952
1953         sema_init(&cmd->sem, cmd->max_reg_cmds);
1954         sema_init(&cmd->pages_sem, 1);
1955
1956         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1957         cmd_l = (u32)(cmd->dma);
1958         if (cmd_l & 0xfff) {
1959                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1960                 err = -ENOMEM;
1961                 goto err_free_page;
1962         }
1963
1964         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1965         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1966
1967         /* Make sure firmware sees the complete address before we proceed */
1968         wmb();
1969
1970         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1971
1972         cmd->mode = CMD_MODE_POLLING;
1973
1974         create_msg_cache(dev);
1975
1976         set_wqname(dev);
1977         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1978         if (!cmd->wq) {
1979                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1980                 err = -ENOMEM;
1981                 goto err_cache;
1982         }
1983
1984         err = create_debugfs_files(dev);
1985         if (err) {
1986                 err = -ENOMEM;
1987                 goto err_wq;
1988         }
1989
1990         return 0;
1991
1992 err_wq:
1993         destroy_workqueue(cmd->wq);
1994
1995 err_cache:
1996         destroy_msg_cache(dev);
1997
1998 err_free_page:
1999         free_cmd_page(dev, cmd);
2000
2001 err_free_pool:
2002         dma_pool_destroy(cmd->pool);
2003
2004         return err;
2005 }
2006 EXPORT_SYMBOL(mlx5_cmd_init);
2007
2008 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2009 {
2010         struct mlx5_cmd *cmd = &dev->cmd;
2011
2012         clean_debug_files(dev);
2013         destroy_workqueue(cmd->wq);
2014         destroy_msg_cache(dev);
2015         free_cmd_page(dev, cmd);
2016         dma_pool_destroy(cmd->pool);
2017 }
2018 EXPORT_SYMBOL(mlx5_cmd_cleanup);