drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <asm-generic/kmap_types.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 enum {
  79         MLX5_CMD_STAT_OK                        = 0x0,
  80         MLX5_CMD_STAT_INT_ERR                   = 0x1,
  81         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
  82         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
  83         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
  84         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
  85         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
  86         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
  87         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
  88         MLX5_CMD_STAT_IX_ERR                    = 0xa,
  89         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
  90         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
  91         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
  92         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
  93         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
  94         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
  95 };
  96
  97 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  98                                            struct mlx5_cmd_msg *in,
  99                                            struct mlx5_cmd_msg *out,
 100                                            void *uout, int uout_size,
 101                                            mlx5_cmd_cbk_t cbk,
 102                                            void *context, int page_queue)
 103 {
 104         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
 105         struct mlx5_cmd_work_ent *ent;
 106
 107         ent = kzalloc(sizeof(*ent), alloc_flags);
 108         if (!ent)
 109                 return ERR_PTR(-ENOMEM);
 110
 111         ent->in         = in;
 112         ent->out        = out;
 113         ent->uout       = uout;
 114         ent->uout_size  = uout_size;
 115         ent->callback   = cbk;
 116         ent->context    = context;
 117         ent->cmd        = cmd;
 118         ent->page_queue = page_queue;
 119
 120         return ent;
 121 }
 122
 123 static u8 alloc_token(struct mlx5_cmd *cmd)
 124 {
 125         u8 token;
 126
 127         spin_lock(&cmd->token_lock);
 128         token = cmd->token++ % 255 + 1;
 129         spin_unlock(&cmd->token_lock);
 130
 131         return token;
 132 }
 133
 134 static int alloc_ent(struct mlx5_cmd *cmd)
 135 {
 136         unsigned long flags;
 137         int ret;
 138
 139         spin_lock_irqsave(&cmd->alloc_lock, flags);
 140         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 141         if (ret < cmd->max_reg_cmds)
 142                 clear_bit(ret, &cmd->bitmask);
 143         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 144
 145         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 146 }
 147
 148 static void free_ent(struct mlx5_cmd *cmd, int idx)
 149 {
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&cmd->alloc_lock, flags);
 153         set_bit(idx, &cmd->bitmask);
 154         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 155 }
 156
 157 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 158 {
 159         return cmd->cmd_buf + (idx << cmd->log_stride);
 160 }
 161
 162 static u8 xor8_buf(void *buf, int len)
 163 {
 164         u8 *ptr = buf;
 165         u8 sum = 0;
 166         int i;
 167
 168         for (i = 0; i < len; i++)
 169                 sum ^= ptr[i];
 170
 171         return sum;
 172 }
 173
 174 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 175 {
 176         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 177                 return -EINVAL;
 178
 179         if (xor8_buf(block, sizeof(*block)) != 0xff)
 180                 return -EINVAL;
 181
 182         return 0;
 183 }
 184
 185 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 186                            int csum)
 187 {
 188         block->token = token;
 189         if (csum) {
 190                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 191                                             sizeof(block->data) - 2);
 192                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 193         }
 194 }
 195
 196 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 197 {
 198         struct mlx5_cmd_mailbox *next = msg->next;
 199
 200         while (next) {
 201                 calc_block_sig(next->buf, token, csum);
 202                 next = next->next;
 203         }
 204 }
 205
 206 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 207 {
 208         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 209         calc_chain_sig(ent->in, ent->token, csum);
 210         calc_chain_sig(ent->out, ent->token, csum);
 211 }
 212
 213 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 214 {
 215         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 216         u8 own;
 217
 218         do {
 219                 own = ent->lay->status_own;
 220                 if (!(own & CMD_OWNER_HW)) {
 221                         ent->ret = 0;
 222                         return;
 223                 }
 224                 usleep_range(5000, 10000);
 225         } while (time_before(jiffies, poll_end));
 226
 227         ent->ret = -ETIMEDOUT;
 228 }
 229
 230 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 231 {
 232         kfree(ent);
 233 }
 234
 235
 236 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 237 {
 238         struct mlx5_cmd_mailbox *next = ent->out->next;
 239         int err;
 240         u8 sig;
 241
 242         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 243         if (sig != 0xff)
 244                 return -EINVAL;
 245
 246         while (next) {
 247                 err = verify_block_sig(next->buf);
 248                 if (err)
 249                         return err;
 250
 251                 next = next->next;
 252         }
 253
 254         return 0;
 255 }
 256
 257 static void dump_buf(void *buf, int size, int data_only, int offset)
 258 {
 259         __be32 *p = buf;
 260         int i;
 261
 262         for (i = 0; i < size; i += 16) {
 263                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 264                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 265                          be32_to_cpu(p[3]));
 266                 p += 4;
 267                 offset += 16;
 268         }
 269         if (!data_only)
 270                 pr_debug("\n");
 271 }
 272
 273 const char *mlx5_command_str(int command)
 274 {
 275         switch (command) {
 276         case MLX5_CMD_OP_QUERY_HCA_CAP:
 277                 return "QUERY_HCA_CAP";
 278
 279         case MLX5_CMD_OP_SET_HCA_CAP:
 280                 return "SET_HCA_CAP";
 281
 282         case MLX5_CMD_OP_QUERY_ADAPTER:
 283                 return "QUERY_ADAPTER";
 284
 285         case MLX5_CMD_OP_INIT_HCA:
 286                 return "INIT_HCA";
 287
 288         case MLX5_CMD_OP_TEARDOWN_HCA:
 289                 return "TEARDOWN_HCA";
 290
 291         case MLX5_CMD_OP_ENABLE_HCA:
 292                 return "MLX5_CMD_OP_ENABLE_HCA";
 293
 294         case MLX5_CMD_OP_DISABLE_HCA:
 295                 return "MLX5_CMD_OP_DISABLE_HCA";
 296
 297         case MLX5_CMD_OP_QUERY_PAGES:
 298                 return "QUERY_PAGES";
 299
 300         case MLX5_CMD_OP_MANAGE_PAGES:
 301                 return "MANAGE_PAGES";
 302
 303         case MLX5_CMD_OP_CREATE_MKEY:
 304                 return "CREATE_MKEY";
 305
 306         case MLX5_CMD_OP_QUERY_MKEY:
 307                 return "QUERY_MKEY";
 308
 309         case MLX5_CMD_OP_DESTROY_MKEY:
 310                 return "DESTROY_MKEY";
 311
 312         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 313                 return "QUERY_SPECIAL_CONTEXTS";
 314
 315         case MLX5_CMD_OP_CREATE_EQ:
 316                 return "CREATE_EQ";
 317
 318         case MLX5_CMD_OP_DESTROY_EQ:
 319                 return "DESTROY_EQ";
 320
 321         case MLX5_CMD_OP_QUERY_EQ:
 322                 return "QUERY_EQ";
 323
 324         case MLX5_CMD_OP_CREATE_CQ:
 325                 return "CREATE_CQ";
 326
 327         case MLX5_CMD_OP_DESTROY_CQ:
 328                 return "DESTROY_CQ";
 329
 330         case MLX5_CMD_OP_QUERY_CQ:
 331                 return "QUERY_CQ";
 332
 333         case MLX5_CMD_OP_MODIFY_CQ:
 334                 return "MODIFY_CQ";
 335
 336         case MLX5_CMD_OP_CREATE_QP:
 337                 return "CREATE_QP";
 338
 339         case MLX5_CMD_OP_DESTROY_QP:
 340                 return "DESTROY_QP";
 341
 342         case MLX5_CMD_OP_RST2INIT_QP:
 343                 return "RST2INIT_QP";
 344
 345         case MLX5_CMD_OP_INIT2RTR_QP:
 346                 return "INIT2RTR_QP";
 347
 348         case MLX5_CMD_OP_RTR2RTS_QP:
 349                 return "RTR2RTS_QP";
 350
 351         case MLX5_CMD_OP_RTS2RTS_QP:
 352                 return "RTS2RTS_QP";
 353
 354         case MLX5_CMD_OP_SQERR2RTS_QP:
 355                 return "SQERR2RTS_QP";
 356
 357         case MLX5_CMD_OP_2ERR_QP:
 358                 return "2ERR_QP";
 359
 360         case MLX5_CMD_OP_RTS2SQD_QP:
 361                 return "RTS2SQD_QP";
 362
 363         case MLX5_CMD_OP_SQD2RTS_QP:
 364                 return "SQD2RTS_QP";
 365
 366         case MLX5_CMD_OP_2RST_QP:
 367                 return "2RST_QP";
 368
 369         case MLX5_CMD_OP_QUERY_QP:
 370                 return "QUERY_QP";
 371
 372         case MLX5_CMD_OP_CONF_SQP:
 373                 return "CONF_SQP";
 374
 375         case MLX5_CMD_OP_MAD_IFC:
 376                 return "MAD_IFC";
 377
 378         case MLX5_CMD_OP_INIT2INIT_QP:
 379                 return "INIT2INIT_QP";
 380
 381         case MLX5_CMD_OP_SUSPEND_QP:
 382                 return "SUSPEND_QP";
 383
 384         case MLX5_CMD_OP_UNSUSPEND_QP:
 385                 return "UNSUSPEND_QP";
 386
 387         case MLX5_CMD_OP_SQD2SQD_QP:
 388                 return "SQD2SQD_QP";
 389
 390         case MLX5_CMD_OP_ALLOC_QP_COUNTER_SET:
 391                 return "ALLOC_QP_COUNTER_SET";
 392
 393         case MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET:
 394                 return "DEALLOC_QP_COUNTER_SET";
 395
 396         case MLX5_CMD_OP_QUERY_QP_COUNTER_SET:
 397                 return "QUERY_QP_COUNTER_SET";
 398
 399         case MLX5_CMD_OP_CREATE_PSV:
 400                 return "CREATE_PSV";
 401
 402         case MLX5_CMD_OP_DESTROY_PSV:
 403                 return "DESTROY_PSV";
 404
 405         case MLX5_CMD_OP_QUERY_PSV:
 406                 return "QUERY_PSV";
 407
 408         case MLX5_CMD_OP_QUERY_SIG_RULE_TABLE:
 409                 return "QUERY_SIG_RULE_TABLE";
 410
 411         case MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE:
 412                 return "QUERY_BLOCK_SIZE_TABLE";
 413
 414         case MLX5_CMD_OP_CREATE_SRQ:
 415                 return "CREATE_SRQ";
 416
 417         case MLX5_CMD_OP_DESTROY_SRQ:
 418                 return "DESTROY_SRQ";
 419
 420         case MLX5_CMD_OP_QUERY_SRQ:
 421                 return "QUERY_SRQ";
 422
 423         case MLX5_CMD_OP_ARM_RQ:
 424                 return "ARM_RQ";
 425
 426         case MLX5_CMD_OP_RESIZE_SRQ:
 427                 return "RESIZE_SRQ";
 428
 429         case MLX5_CMD_OP_ALLOC_PD:
 430                 return "ALLOC_PD";
 431
 432         case MLX5_CMD_OP_DEALLOC_PD:
 433                 return "DEALLOC_PD";
 434
 435         case MLX5_CMD_OP_ALLOC_UAR:
 436                 return "ALLOC_UAR";
 437
 438         case MLX5_CMD_OP_DEALLOC_UAR:
 439                 return "DEALLOC_UAR";
 440
 441         case MLX5_CMD_OP_ATTACH_TO_MCG:
 442                 return "ATTACH_TO_MCG";
 443
 444         case MLX5_CMD_OP_DETACH_FROM_MCG:
 445                 return "DETACH_FROM_MCG";
 446
 447         case MLX5_CMD_OP_ALLOC_XRCD:
 448                 return "ALLOC_XRCD";
 449
 450         case MLX5_CMD_OP_DEALLOC_XRCD:
 451                 return "DEALLOC_XRCD";
 452
 453         case MLX5_CMD_OP_ACCESS_REG:
 454                 return "MLX5_CMD_OP_ACCESS_REG";
 455
 456         default: return "unknown command opcode";
 457         }
 458 }
 459
 460 static void dump_command(struct mlx5_core_dev *dev,
 461                          struct mlx5_cmd_work_ent *ent, int input)
 462 {
 463         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 464         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 465         struct mlx5_cmd_mailbox *next = msg->next;
 466         int data_only;
 467         int offset = 0;
 468         int dump_len;
 469
 470         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 471
 472         if (data_only)
 473                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 474                                    "dump command data %s(0x%x) %s\n",
 475                                    mlx5_command_str(op), op,
 476                                    input ? "INPUT" : "OUTPUT");
 477         else
 478                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 479                               mlx5_command_str(op), op,
 480                               input ? "INPUT" : "OUTPUT");
 481
 482         if (data_only) {
 483                 if (input) {
 484                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 485                         offset += sizeof(ent->lay->in);
 486                 } else {
 487                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 488                         offset += sizeof(ent->lay->out);
 489                 }
 490         } else {
 491                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 492                 offset += sizeof(*ent->lay);
 493         }
 494
 495         while (next && offset < msg->len) {
 496                 if (data_only) {
 497                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 498                         dump_buf(next->buf, dump_len, 1, offset);
 499                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 500                 } else {
 501                         mlx5_core_dbg(dev, "command block:\n");
 502                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 503                         offset += sizeof(struct mlx5_cmd_prot_block);
 504                 }
 505                 next = next->next;
 506         }
 507
 508         if (data_only)
 509                 pr_debug("\n");
 510 }
 511
 512 static void cmd_work_handler(struct work_struct *work)
 513 {
 514         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 515         struct mlx5_cmd *cmd = ent->cmd;
 516         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 517         struct mlx5_cmd_layout *lay;
 518         struct semaphore *sem;
 519
 520         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 521         down(sem);
 522         if (!ent->page_queue) {
 523                 ent->idx = alloc_ent(cmd);
 524                 if (ent->idx < 0) {
 525                         mlx5_core_err(dev, "failed to allocate command entry\n");
 526                         up(sem);
 527                         return;
 528                 }
 529         } else {
 530                 ent->idx = cmd->max_reg_cmds;
 531         }
 532
 533         ent->token = alloc_token(cmd);
 534         cmd->ent_arr[ent->idx] = ent;
 535         lay = get_inst(cmd, ent->idx);
 536         ent->lay = lay;
 537         memset(lay, 0, sizeof(*lay));
 538         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 539         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 540         if (ent->in->next)
 541                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 542         lay->inlen = cpu_to_be32(ent->in->len);
 543         if (ent->out->next)
 544                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 545         lay->outlen = cpu_to_be32(ent->out->len);
 546         lay->type = MLX5_PCI_CMD_XPORT;
 547         lay->token = ent->token;
 548         lay->status_own = CMD_OWNER_HW;
 549         set_signature(ent, !cmd->checksum_disabled);
 550         dump_command(dev, ent, 1);
 551         ktime_get_ts(&ent->ts1);
 552
 553         /* ring doorbell after the descriptor is valid */
 554         wmb();
 555         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 556         mlx5_core_dbg(dev, "write 0x%x to command doorbell\n", 1 << ent->idx);
 557         mmiowb();
 558         if (cmd->mode == CMD_MODE_POLLING) {
 559                 poll_timeout(ent);
 560                 /* make sure we read the descriptor after ownership is SW */
 561                 rmb();
 562                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 563         }
 564 }
 565
 566 static const char *deliv_status_to_str(u8 status)
 567 {
 568         switch (status) {
 569         case MLX5_CMD_DELIVERY_STAT_OK:
 570                 return "no errors";
 571         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 572                 return "signature error";
 573         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 574                 return "token error";
 575         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 576                 return "bad block number";
 577         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 578                 return "output pointer not aligned to block size";
 579         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 580                 return "input pointer not aligned to block size";
 581         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 582                 return "firmware internal error";
 583         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 584                 return "command input length error";
 585         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 586                 return "command ouput length error";
 587         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 588                 return "reserved fields not cleared";
 589         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 590                 return "bad command descriptor type";
 591         default:
 592                 return "unknown status code";
 593         }
 594 }
 595
 596 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 597 {
 598         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 599
 600         return be16_to_cpu(hdr->opcode);
 601 }
 602
 603 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 604 {
 605         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 606         struct mlx5_cmd *cmd = &dev->cmd;
 607         int err;
 608
 609         if (cmd->mode == CMD_MODE_POLLING) {
 610                 wait_for_completion(&ent->done);
 611                 err = ent->ret;
 612         } else {
 613                 if (!wait_for_completion_timeout(&ent->done, timeout))
 614                         err = -ETIMEDOUT;
 615                 else
 616                         err = 0;
 617         }
 618         if (err == -ETIMEDOUT) {
 619                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 620                                mlx5_command_str(msg_to_opcode(ent->in)),
 621                                msg_to_opcode(ent->in));
 622         }
 623         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n", err,
 624                       deliv_status_to_str(ent->status), ent->status);
 625
 626         return err;
 627 }
 628
 629 /*  Notes:
 630  *    1. Callback functions may not sleep
 631  *    2. page queue commands do not support asynchrous completion
 632  */
 633 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 634                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 635                            mlx5_cmd_cbk_t callback,
 636                            void *context, int page_queue, u8 *status)
 637 {
 638         struct mlx5_cmd *cmd = &dev->cmd;
 639         struct mlx5_cmd_work_ent *ent;
 640         ktime_t t1, t2, delta;
 641         struct mlx5_cmd_stats *stats;
 642         int err = 0;
 643         s64 ds;
 644         u16 op;
 645
 646         if (callback && page_queue)
 647                 return -EINVAL;
 648
 649         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 650                         page_queue);
 651         if (IS_ERR(ent))
 652                 return PTR_ERR(ent);
 653
 654         if (!callback)
 655                 init_completion(&ent->done);
 656
 657         INIT_WORK(&ent->work, cmd_work_handler);
 658         if (page_queue) {
 659                 cmd_work_handler(&ent->work);
 660         } else if (!queue_work(cmd->wq, &ent->work)) {
 661                 mlx5_core_warn(dev, "failed to queue work\n");
 662                 err = -ENOMEM;
 663                 goto out_free;
 664         }
 665
 666         if (!callback) {
 667                 err = wait_func(dev, ent);
 668                 if (err == -ETIMEDOUT)
 669                         goto out;
 670
 671                 t1 = timespec_to_ktime(ent->ts1);
 672                 t2 = timespec_to_ktime(ent->ts2);
 673                 delta = ktime_sub(t2, t1);
 674                 ds = ktime_to_ns(delta);
 675                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 676                 if (op < ARRAY_SIZE(cmd->stats)) {
 677                         stats = &cmd->stats[op];
 678                         spin_lock_irq(&stats->lock);
 679                         stats->sum += ds;
 680                         ++stats->n;
 681                         spin_unlock_irq(&stats->lock);
 682                 }
 683                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 684                                    "fw exec time for %s is %lld nsec\n",
 685                                    mlx5_command_str(op), ds);
 686                 *status = ent->status;
 687                 free_cmd(ent);
 688         }
 689
 690         return err;
 691
 692 out_free:
 693         free_cmd(ent);
 694 out:
 695         return err;
 696 }
 697
 698 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 699                          size_t count, loff_t *pos)
 700 {
 701         struct mlx5_core_dev *dev = filp->private_data;
 702         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 703         char lbuf[3];
 704         int err;
 705
 706         if (!dbg->in_msg || !dbg->out_msg)
 707                 return -ENOMEM;
 708
 709         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 710                 return -EFAULT;
 711
 712         lbuf[sizeof(lbuf) - 1] = 0;
 713
 714         if (strcmp(lbuf, "go"))
 715                 return -EINVAL;
 716
 717         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 718
 719         return err ? err : count;
 720 }
 721
 722
 723 static const struct file_operations fops = {
 724         .owner  = THIS_MODULE,
 725         .open   = simple_open,
 726         .write  = dbg_write,
 727 };
 728
 729 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
 730 {
 731         struct mlx5_cmd_prot_block *block;
 732         struct mlx5_cmd_mailbox *next;
 733         int copy;
 734
 735         if (!to || !from)
 736                 return -ENOMEM;
 737
 738         copy = min_t(int, size, sizeof(to->first.data));
 739         memcpy(to->first.data, from, copy);
 740         size -= copy;
 741         from += copy;
 742
 743         next = to->next;
 744         while (size) {
 745                 if (!next) {
 746                         /* this is a BUG */
 747                         return -ENOMEM;
 748                 }
 749
 750                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 751                 block = next->buf;
 752                 memcpy(block->data, from, copy);
 753                 from += copy;
 754                 size -= copy;
 755                 next = next->next;
 756         }
 757
 758         return 0;
 759 }
 760
 761 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 762 {
 763         struct mlx5_cmd_prot_block *block;
 764         struct mlx5_cmd_mailbox *next;
 765         int copy;
 766
 767         if (!to || !from)
 768                 return -ENOMEM;
 769
 770         copy = min_t(int, size, sizeof(from->first.data));
 771         memcpy(to, from->first.data, copy);
 772         size -= copy;
 773         to += copy;
 774
 775         next = from->next;
 776         while (size) {
 777                 if (!next) {
 778                         /* this is a BUG */
 779                         return -ENOMEM;
 780                 }
 781
 782                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 783                 block = next->buf;
 784
 785                 memcpy(to, block->data, copy);
 786                 to += copy;
 787                 size -= copy;
 788                 next = next->next;
 789         }
 790
 791         return 0;
 792 }
 793
 794 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 795                                               gfp_t flags)
 796 {
 797         struct mlx5_cmd_mailbox *mailbox;
 798
 799         mailbox = kmalloc(sizeof(*mailbox), flags);
 800         if (!mailbox)
 801                 return ERR_PTR(-ENOMEM);
 802
 803         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 804                                       &mailbox->dma);
 805         if (!mailbox->buf) {
 806                 mlx5_core_dbg(dev, "failed allocation\n");
 807                 kfree(mailbox);
 808                 return ERR_PTR(-ENOMEM);
 809         }
 810         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 811         mailbox->next = NULL;
 812
 813         return mailbox;
 814 }
 815
 816 static void free_cmd_box(struct mlx5_core_dev *dev,
 817                          struct mlx5_cmd_mailbox *mailbox)
 818 {
 819         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 820         kfree(mailbox);
 821 }
 822
 823 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 824                                                gfp_t flags, int size)
 825 {
 826         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 827         struct mlx5_cmd_prot_block *block;
 828         struct mlx5_cmd_msg *msg;
 829         int blen;
 830         int err;
 831         int n;
 832         int i;
 833
 834         msg = kzalloc(sizeof(*msg), flags);
 835         if (!msg)
 836                 return ERR_PTR(-ENOMEM);
 837
 838         blen = size - min_t(int, sizeof(msg->first.data), size);
 839         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 840
 841         for (i = 0; i < n; i++) {
 842                 tmp = alloc_cmd_box(dev, flags);
 843                 if (IS_ERR(tmp)) {
 844                         mlx5_core_warn(dev, "failed allocating block\n");
 845                         err = PTR_ERR(tmp);
 846                         goto err_alloc;
 847                 }
 848
 849                 block = tmp->buf;
 850                 tmp->next = head;
 851                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 852                 block->block_num = cpu_to_be32(n - i - 1);
 853                 head = tmp;
 854         }
 855         msg->next = head;
 856         msg->len = size;
 857         return msg;
 858
 859 err_alloc:
 860         while (head) {
 861                 tmp = head->next;
 862                 free_cmd_box(dev, head);
 863                 head = tmp;
 864         }
 865         kfree(msg);
 866
 867         return ERR_PTR(err);
 868 }
 869
 870 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 871                                   struct mlx5_cmd_msg *msg)
 872 {
 873         struct mlx5_cmd_mailbox *head = msg->next;
 874         struct mlx5_cmd_mailbox *next;
 875
 876         while (head) {
 877                 next = head->next;
 878                 free_cmd_box(dev, head);
 879                 head = next;
 880         }
 881         kfree(msg);
 882 }
 883
 884 static ssize_t data_write(struct file *filp, const char __user *buf,
 885                           size_t count, loff_t *pos)
 886 {
 887         struct mlx5_core_dev *dev = filp->private_data;
 888         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 889         void *ptr;
 890         int err;
 891
 892         if (*pos != 0)
 893                 return -EINVAL;
 894
 895         kfree(dbg->in_msg);
 896         dbg->in_msg = NULL;
 897         dbg->inlen = 0;
 898
 899         ptr = kzalloc(count, GFP_KERNEL);
 900         if (!ptr)
 901                 return -ENOMEM;
 902
 903         if (copy_from_user(ptr, buf, count)) {
 904                 err = -EFAULT;
 905                 goto out;
 906         }
 907         dbg->in_msg = ptr;
 908         dbg->inlen = count;
 909
 910         *pos = count;
 911
 912         return count;
 913
 914 out:
 915         kfree(ptr);
 916         return err;
 917 }
 918
 919 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
 920                          loff_t *pos)
 921 {
 922         struct mlx5_core_dev *dev = filp->private_data;
 923         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 924         int copy;
 925
 926         if (*pos)
 927                 return 0;
 928
 929         if (!dbg->out_msg)
 930                 return -ENOMEM;
 931
 932         copy = min_t(int, count, dbg->outlen);
 933         if (copy_to_user(buf, dbg->out_msg, copy))
 934                 return -EFAULT;
 935
 936         *pos += copy;
 937
 938         return copy;
 939 }
 940
 941 static const struct file_operations dfops = {
 942         .owner  = THIS_MODULE,
 943         .open   = simple_open,
 944         .write  = data_write,
 945         .read   = data_read,
 946 };
 947
 948 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
 949                            loff_t *pos)
 950 {
 951         struct mlx5_core_dev *dev = filp->private_data;
 952         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 953         char outlen[8];
 954         int err;
 955
 956         if (*pos)
 957                 return 0;
 958
 959         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
 960         if (err < 0)
 961                 return err;
 962
 963         if (copy_to_user(buf, &outlen, err))
 964                 return -EFAULT;
 965
 966         *pos += err;
 967
 968         return err;
 969 }
 970
 971 static ssize_t outlen_write(struct file *filp, const char __user *buf,
 972                             size_t count, loff_t *pos)
 973 {
 974         struct mlx5_core_dev *dev = filp->private_data;
 975         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 976         char outlen_str[8];
 977         int outlen;
 978         void *ptr;
 979         int err;
 980
 981         if (*pos != 0 || count > 6)
 982                 return -EINVAL;
 983
 984         kfree(dbg->out_msg);
 985         dbg->out_msg = NULL;
 986         dbg->outlen = 0;
 987
 988         if (copy_from_user(outlen_str, buf, count))
 989                 return -EFAULT;
 990
 991         outlen_str[7] = 0;
 992
 993         err = sscanf(outlen_str, "%d", &outlen);
 994         if (err < 0)
 995                 return err;
 996
 997         ptr = kzalloc(outlen, GFP_KERNEL);
 998         if (!ptr)
 999                 return -ENOMEM;
1000
1001         dbg->out_msg = ptr;
1002         dbg->outlen = outlen;
1003
1004         *pos = count;
1005
1006         return count;
1007 }
1008
1009 static const struct file_operations olfops = {
1010         .owner  = THIS_MODULE,
1011         .open   = simple_open,
1012         .write  = outlen_write,
1013         .read   = outlen_read,
1014 };
1015
1016 static void set_wqname(struct mlx5_core_dev *dev)
1017 {
1018         struct mlx5_cmd *cmd = &dev->cmd;
1019
1020         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1021                  dev_name(&dev->pdev->dev));
1022 }
1023
1024 static void clean_debug_files(struct mlx5_core_dev *dev)
1025 {
1026         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1027
1028         if (!mlx5_debugfs_root)
1029                 return;
1030
1031         mlx5_cmdif_debugfs_cleanup(dev);
1032         debugfs_remove_recursive(dbg->dbg_root);
1033 }
1034
1035 static int create_debugfs_files(struct mlx5_core_dev *dev)
1036 {
1037         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1038         int err = -ENOMEM;
1039
1040         if (!mlx5_debugfs_root)
1041                 return 0;
1042
1043         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1044         if (!dbg->dbg_root)
1045                 return err;
1046
1047         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1048                                           dev, &dfops);
1049         if (!dbg->dbg_in)
1050                 goto err_dbg;
1051
1052         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1053                                            dev, &dfops);
1054         if (!dbg->dbg_out)
1055                 goto err_dbg;
1056
1057         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1058                                               dev, &olfops);
1059         if (!dbg->dbg_outlen)
1060                 goto err_dbg;
1061
1062         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1063                                             &dbg->status);
1064         if (!dbg->dbg_status)
1065                 goto err_dbg;
1066
1067         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1068         if (!dbg->dbg_run)
1069                 goto err_dbg;
1070
1071         mlx5_cmdif_debugfs_init(dev);
1072
1073         return 0;
1074
1075 err_dbg:
1076         clean_debug_files(dev);
1077         return err;
1078 }
1079
1080 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1081 {
1082         struct mlx5_cmd *cmd = &dev->cmd;
1083         int i;
1084
1085         for (i = 0; i < cmd->max_reg_cmds; i++)
1086                 down(&cmd->sem);
1087
1088         down(&cmd->pages_sem);
1089
1090         flush_workqueue(cmd->wq);
1091
1092         cmd->mode = CMD_MODE_EVENTS;
1093
1094         up(&cmd->pages_sem);
1095         for (i = 0; i < cmd->max_reg_cmds; i++)
1096                 up(&cmd->sem);
1097 }
1098
1099 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1100 {
1101         struct mlx5_cmd *cmd = &dev->cmd;
1102         int i;
1103
1104         for (i = 0; i < cmd->max_reg_cmds; i++)
1105                 down(&cmd->sem);
1106
1107         down(&cmd->pages_sem);
1108
1109         flush_workqueue(cmd->wq);
1110         cmd->mode = CMD_MODE_POLLING;
1111
1112         up(&cmd->pages_sem);
1113         for (i = 0; i < cmd->max_reg_cmds; i++)
1114                 up(&cmd->sem);
1115 }
1116
1117 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1118 {
1119         unsigned long flags;
1120
1121         if (msg->cache) {
1122                 spin_lock_irqsave(&msg->cache->lock, flags);
1123                 list_add_tail(&msg->list, &msg->cache->head);
1124                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1125         } else {
1126                 mlx5_free_cmd_msg(dev, msg);
1127         }
1128 }
1129
1130 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector)
1131 {
1132         struct mlx5_cmd *cmd = &dev->cmd;
1133         struct mlx5_cmd_work_ent *ent;
1134         mlx5_cmd_cbk_t callback;
1135         void *context;
1136         int err;
1137         int i;
1138         ktime_t t1, t2, delta;
1139         s64 ds;
1140         struct mlx5_cmd_stats *stats;
1141         unsigned long flags;
1142
1143         for (i = 0; i < (1 << cmd->log_sz); i++) {
1144                 if (test_bit(i, &vector)) {
1145                         struct semaphore *sem;
1146
1147                         ent = cmd->ent_arr[i];
1148                         if (ent->page_queue)
1149                                 sem = &cmd->pages_sem;
1150                         else
1151                                 sem = &cmd->sem;
1152                         ktime_get_ts(&ent->ts2);
1153                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1154                         dump_command(dev, ent, 0);
1155                         if (!ent->ret) {
1156                                 if (!cmd->checksum_disabled)
1157                                         ent->ret = verify_signature(ent);
1158                                 else
1159                                         ent->ret = 0;
1160                                 ent->status = ent->lay->status_own >> 1;
1161                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1162                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1163                         }
1164                         free_ent(cmd, ent->idx);
1165                         if (ent->callback) {
1166                                 t1 = timespec_to_ktime(ent->ts1);
1167                                 t2 = timespec_to_ktime(ent->ts2);
1168                                 delta = ktime_sub(t2, t1);
1169                                 ds = ktime_to_ns(delta);
1170                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1171                                         stats = &cmd->stats[ent->op];
1172                                         spin_lock_irqsave(&stats->lock, flags);
1173                                         stats->sum += ds;
1174                                         ++stats->n;
1175                                         spin_unlock_irqrestore(&stats->lock, flags);
1176                                 }
1177
1178                                 callback = ent->callback;
1179                                 context = ent->context;
1180                                 err = ent->ret;
1181                                 if (!err)
1182                                         err = mlx5_copy_from_msg(ent->uout,
1183                                                                  ent->out,
1184                                                                  ent->uout_size);
1185
1186                                 mlx5_free_cmd_msg(dev, ent->out);
1187                                 free_msg(dev, ent->in);
1188
1189                                 free_cmd(ent);
1190                                 callback(err, context);
1191                         } else {
1192                                 complete(&ent->done);
1193                         }
1194                         up(sem);
1195                 }
1196         }
1197 }
1198 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1199
1200 static int status_to_err(u8 status)
1201 {
1202         return status ? -1 : 0; /* TBD more meaningful codes */
1203 }
1204
1205 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1206                                       gfp_t gfp)
1207 {
1208         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1209         struct mlx5_cmd *cmd = &dev->cmd;
1210         struct cache_ent *ent = NULL;
1211
1212         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1213                 ent = &cmd->cache.large;
1214         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1215                 ent = &cmd->cache.med;
1216
1217         if (ent) {
1218                 spin_lock_irq(&ent->lock);
1219                 if (!list_empty(&ent->head)) {
1220                         msg = list_entry(ent->head.next, typeof(*msg), list);
1221                         /* For cached lists, we must explicitly state what is
1222                          * the real size
1223                          */
1224                         msg->len = in_size;
1225                         list_del(&msg->list);
1226                 }
1227                 spin_unlock_irq(&ent->lock);
1228         }
1229
1230         if (IS_ERR(msg))
1231                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1232
1233         return msg;
1234 }
1235
1236 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1237 {
1238         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1239 }
1240
1241 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1242                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1243 {
1244         struct mlx5_cmd_msg *inb;
1245         struct mlx5_cmd_msg *outb;
1246         int pages_queue;
1247         gfp_t gfp;
1248         int err;
1249         u8 status = 0;
1250
1251         pages_queue = is_manage_pages(in);
1252         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1253
1254         inb = alloc_msg(dev, in_size, gfp);
1255         if (IS_ERR(inb)) {
1256                 err = PTR_ERR(inb);
1257                 return err;
1258         }
1259
1260         err = mlx5_copy_to_msg(inb, in, in_size);
1261         if (err) {
1262                 mlx5_core_warn(dev, "err %d\n", err);
1263                 goto out_in;
1264         }
1265
1266         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1267         if (IS_ERR(outb)) {
1268                 err = PTR_ERR(outb);
1269                 goto out_in;
1270         }
1271
1272         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1273                               pages_queue, &status);
1274         if (err)
1275                 goto out_out;
1276
1277         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1278         if (status) {
1279                 err = status_to_err(status);
1280                 goto out_out;
1281         }
1282
1283         err = mlx5_copy_from_msg(out, outb, out_size);
1284
1285 out_out:
1286         if (!callback)
1287                 mlx5_free_cmd_msg(dev, outb);
1288
1289 out_in:
1290         if (!callback)
1291                 free_msg(dev, inb);
1292         return err;
1293 }
1294
1295 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1296                   int out_size)
1297 {
1298         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1299 }
1300 EXPORT_SYMBOL(mlx5_cmd_exec);
1301
1302 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1303                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1304                      void *context)
1305 {
1306         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1307 }
1308 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1309
1310 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1311 {
1312         struct mlx5_cmd *cmd = &dev->cmd;
1313         struct mlx5_cmd_msg *msg;
1314         struct mlx5_cmd_msg *n;
1315
1316         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1317                 list_del(&msg->list);
1318                 mlx5_free_cmd_msg(dev, msg);
1319         }
1320
1321         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1322                 list_del(&msg->list);
1323                 mlx5_free_cmd_msg(dev, msg);
1324         }
1325 }
1326
1327 static int create_msg_cache(struct mlx5_core_dev *dev)
1328 {
1329         struct mlx5_cmd *cmd = &dev->cmd;
1330         struct mlx5_cmd_msg *msg;
1331         int err;
1332         int i;
1333
1334         spin_lock_init(&cmd->cache.large.lock);
1335         INIT_LIST_HEAD(&cmd->cache.large.head);
1336         spin_lock_init(&cmd->cache.med.lock);
1337         INIT_LIST_HEAD(&cmd->cache.med.head);
1338
1339         for (i = 0; i < NUM_LONG_LISTS; i++) {
1340                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1341                 if (IS_ERR(msg)) {
1342                         err = PTR_ERR(msg);
1343                         goto ex_err;
1344                 }
1345                 msg->cache = &cmd->cache.large;
1346                 list_add_tail(&msg->list, &cmd->cache.large.head);
1347         }
1348
1349         for (i = 0; i < NUM_MED_LISTS; i++) {
1350                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1351                 if (IS_ERR(msg)) {
1352                         err = PTR_ERR(msg);
1353                         goto ex_err;
1354                 }
1355                 msg->cache = &cmd->cache.med;
1356                 list_add_tail(&msg->list, &cmd->cache.med.head);
1357         }
1358
1359         return 0;
1360
1361 ex_err:
1362         destroy_msg_cache(dev);
1363         return err;
1364 }
1365
1366 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1367 {
1368         int size = sizeof(struct mlx5_cmd_prot_block);
1369         int align = roundup_pow_of_two(size);
1370         struct mlx5_cmd *cmd = &dev->cmd;
1371         u32 cmd_h, cmd_l;
1372         u16 cmd_if_rev;
1373         int err;
1374         int i;
1375
1376         cmd_if_rev = cmdif_rev(dev);
1377         if (cmd_if_rev != CMD_IF_REV) {
1378                 dev_err(&dev->pdev->dev,
1379                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1380                         CMD_IF_REV, cmd_if_rev);
1381                 return -EINVAL;
1382         }
1383
1384         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1385         if (!cmd->pool)
1386                 return -ENOMEM;
1387
1388         cmd->cmd_buf = (void *)__get_free_pages(GFP_ATOMIC, 0);
1389         if (!cmd->cmd_buf) {
1390                 err = -ENOMEM;
1391                 goto err_free_pool;
1392         }
1393         cmd->dma = dma_map_single(&dev->pdev->dev, cmd->cmd_buf, PAGE_SIZE,
1394                                   DMA_BIDIRECTIONAL);
1395         if (dma_mapping_error(&dev->pdev->dev, cmd->dma)) {
1396                 err = -ENOMEM;
1397                 goto err_free;
1398         }
1399
1400         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1401         cmd->log_sz = cmd_l >> 4 & 0xf;
1402         cmd->log_stride = cmd_l & 0xf;
1403         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1404                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1405                         1 << cmd->log_sz);
1406                 err = -EINVAL;
1407                 goto err_map;
1408         }
1409
1410         if (cmd->log_sz + cmd->log_stride > PAGE_SHIFT) {
1411                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1412                 err = -EINVAL;
1413                 goto err_map;
1414         }
1415
1416         cmd->checksum_disabled = 1;
1417         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1418         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1419
1420         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1421         if (cmd->cmdif_rev > CMD_IF_REV) {
1422                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1423                         CMD_IF_REV, cmd->cmdif_rev);
1424                 err = -ENOTSUPP;
1425                 goto err_map;
1426         }
1427
1428         spin_lock_init(&cmd->alloc_lock);
1429         spin_lock_init(&cmd->token_lock);
1430         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1431                 spin_lock_init(&cmd->stats[i].lock);
1432
1433         sema_init(&cmd->sem, cmd->max_reg_cmds);
1434         sema_init(&cmd->pages_sem, 1);
1435
1436         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1437         cmd_l = (u32)(cmd->dma);
1438         if (cmd_l & 0xfff) {
1439                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1440                 err = -ENOMEM;
1441                 goto err_map;
1442         }
1443
1444         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1445         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1446
1447         /* Make sure firmware sees the complete address before we proceed */
1448         wmb();
1449
1450         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1451
1452         cmd->mode = CMD_MODE_POLLING;
1453
1454         err = create_msg_cache(dev);
1455         if (err) {
1456                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1457                 goto err_map;
1458         }
1459
1460         set_wqname(dev);
1461         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1462         if (!cmd->wq) {
1463                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1464                 err = -ENOMEM;
1465                 goto err_cache;
1466         }
1467
1468         err = create_debugfs_files(dev);
1469         if (err) {
1470                 err = -ENOMEM;
1471                 goto err_wq;
1472         }
1473
1474         return 0;
1475
1476 err_wq:
1477         destroy_workqueue(cmd->wq);
1478
1479 err_cache:
1480         destroy_msg_cache(dev);
1481
1482 err_map:
1483         dma_unmap_single(&dev->pdev->dev, cmd->dma, PAGE_SIZE,
1484                          DMA_BIDIRECTIONAL);
1485 err_free:
1486         free_pages((unsigned long)cmd->cmd_buf, 0);
1487
1488 err_free_pool:
1489         pci_pool_destroy(cmd->pool);
1490
1491         return err;
1492 }
1493 EXPORT_SYMBOL(mlx5_cmd_init);
1494
1495 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1496 {
1497         struct mlx5_cmd *cmd = &dev->cmd;
1498
1499         clean_debug_files(dev);
1500         destroy_workqueue(cmd->wq);
1501         destroy_msg_cache(dev);
1502         dma_unmap_single(&dev->pdev->dev, cmd->dma, PAGE_SIZE,
1503                          DMA_BIDIRECTIONAL);
1504         free_pages((unsigned long)cmd->cmd_buf, 0);
1505         pci_pool_destroy(cmd->pool);
1506 }
1507 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1508
1509 static const char *cmd_status_str(u8 status)
1510 {
1511         switch (status) {
1512         case MLX5_CMD_STAT_OK:
1513                 return "OK";
1514         case MLX5_CMD_STAT_INT_ERR:
1515                 return "internal error";
1516         case MLX5_CMD_STAT_BAD_OP_ERR:
1517                 return "bad operation";
1518         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1519                 return "bad parameter";
1520         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1521                 return "bad system state";
1522         case MLX5_CMD_STAT_BAD_RES_ERR:
1523                 return "bad resource";
1524         case MLX5_CMD_STAT_RES_BUSY:
1525                 return "resource busy";
1526         case MLX5_CMD_STAT_LIM_ERR:
1527                 return "limits exceeded";
1528         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1529                 return "bad resource state";
1530         case MLX5_CMD_STAT_IX_ERR:
1531                 return "bad index";
1532         case MLX5_CMD_STAT_NO_RES_ERR:
1533                 return "no resources";
1534         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1535                 return "bad input length";
1536         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1537                 return "bad output length";
1538         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1539                 return "bad QP state";
1540         case MLX5_CMD_STAT_BAD_PKT_ERR:
1541                 return "bad packet (discarded)";
1542         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1543                 return "bad size too many outstanding CQEs";
1544         default:
1545                 return "unknown status";
1546         }
1547 }
1548
1549 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1550 {
1551         if (!hdr->status)
1552                 return 0;
1553
1554         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1555                 cmd_status_str(hdr->status), hdr->status,
1556                 be32_to_cpu(hdr->syndrome));
1557
1558         switch (hdr->status) {
1559         case MLX5_CMD_STAT_OK:                          return 0;
1560         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1561         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1562         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1563         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1564         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1565         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1566         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1567         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1568         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1569         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1570         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1571         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1572         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1573         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1574         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1575         default:                                        return -EIO;
1576         }
1577 }