drivers/net/ethernet/mellanox/mlx4/resource_tracker.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
   4  * All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/sched.h>
  37 #include <linux/pci.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/io.h>
  41 #include <linux/slab.h>
  42 #include <linux/mlx4/cmd.h>
  43 #include <linux/mlx4/qp.h>
  44 #include <linux/if_ether.h>
  45 #include <linux/etherdevice.h>
  46
  47 #include "mlx4.h"
  48 #include "fw.h"
  49 #include "mlx4_stats.h"
  50
  51 #define MLX4_MAC_VALID          (1ull << 63)
  52 #define MLX4_PF_COUNTERS_PER_PORT       2
  53 #define MLX4_VF_COUNTERS_PER_PORT       1
  54
  55 struct mac_res {
  56         struct list_head list;
  57         u64 mac;
  58         int ref_count;
  59         u8 smac_index;
  60         u8 port;
  61 };
  62
  63 struct vlan_res {
  64         struct list_head list;
  65         u16 vlan;
  66         int ref_count;
  67         int vlan_index;
  68         u8 port;
  69 };
  70
  71 struct res_common {
  72         struct list_head        list;
  73         struct rb_node          node;
  74         u64                     res_id;
  75         int                     owner;
  76         int                     state;
  77         int                     from_state;
  78         int                     to_state;
  79         int                     removing;
  80 };
  81
  82 enum {
  83         RES_ANY_BUSY = 1
  84 };
  85
  86 struct res_gid {
  87         struct list_head        list;
  88         u8                      gid[16];
  89         enum mlx4_protocol      prot;
  90         enum mlx4_steer_type    steer;
  91         u64                     reg_id;
  92 };
  93
  94 enum res_qp_states {
  95         RES_QP_BUSY = RES_ANY_BUSY,
  96
  97         /* QP number was allocated */
  98         RES_QP_RESERVED,
  99
 100         /* ICM memory for QP context was mapped */
 101         RES_QP_MAPPED,
 102
 103         /* QP is in hw ownership */
 104         RES_QP_HW
 105 };
 106
 107 struct res_qp {
 108         struct res_common       com;
 109         struct res_mtt         *mtt;
 110         struct res_cq          *rcq;
 111         struct res_cq          *scq;
 112         struct res_srq         *srq;
 113         struct list_head        mcg_list;
 114         spinlock_t              mcg_spl;
 115         int                     local_qpn;
 116         atomic_t                ref_count;
 117         u32                     qpc_flags;
 118         /* saved qp params before VST enforcement in order to restore on VGT */
 119         u8                      sched_queue;
 120         __be32                  param3;
 121         u8                      vlan_control;
 122         u8                      fvl_rx;
 123         u8                      pri_path_fl;
 124         u8                      vlan_index;
 125         u8                      feup;
 126 };
 127
 128 enum res_mtt_states {
 129         RES_MTT_BUSY = RES_ANY_BUSY,
 130         RES_MTT_ALLOCATED,
 131 };
 132
 133 static inline const char *mtt_states_str(enum res_mtt_states state)
 134 {
 135         switch (state) {
 136         case RES_MTT_BUSY: return "RES_MTT_BUSY";
 137         case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
 138         default: return "Unknown";
 139         }
 140 }
 141
 142 struct res_mtt {
 143         struct res_common       com;
 144         int                     order;
 145         atomic_t                ref_count;
 146 };
 147
 148 enum res_mpt_states {
 149         RES_MPT_BUSY = RES_ANY_BUSY,
 150         RES_MPT_RESERVED,
 151         RES_MPT_MAPPED,
 152         RES_MPT_HW,
 153 };
 154
 155 struct res_mpt {
 156         struct res_common       com;
 157         struct res_mtt         *mtt;
 158         int                     key;
 159 };
 160
 161 enum res_eq_states {
 162         RES_EQ_BUSY = RES_ANY_BUSY,
 163         RES_EQ_RESERVED,
 164         RES_EQ_HW,
 165 };
 166
 167 struct res_eq {
 168         struct res_common       com;
 169         struct res_mtt         *mtt;
 170 };
 171
 172 enum res_cq_states {
 173         RES_CQ_BUSY = RES_ANY_BUSY,
 174         RES_CQ_ALLOCATED,
 175         RES_CQ_HW,
 176 };
 177
 178 struct res_cq {
 179         struct res_common       com;
 180         struct res_mtt         *mtt;
 181         atomic_t                ref_count;
 182 };
 183
 184 enum res_srq_states {
 185         RES_SRQ_BUSY = RES_ANY_BUSY,
 186         RES_SRQ_ALLOCATED,
 187         RES_SRQ_HW,
 188 };
 189
 190 struct res_srq {
 191         struct res_common       com;
 192         struct res_mtt         *mtt;
 193         struct res_cq          *cq;
 194         atomic_t                ref_count;
 195 };
 196
 197 enum res_counter_states {
 198         RES_COUNTER_BUSY = RES_ANY_BUSY,
 199         RES_COUNTER_ALLOCATED,
 200 };
 201
 202 struct res_counter {
 203         struct res_common       com;
 204         int                     port;
 205 };
 206
 207 enum res_xrcdn_states {
 208         RES_XRCD_BUSY = RES_ANY_BUSY,
 209         RES_XRCD_ALLOCATED,
 210 };
 211
 212 struct res_xrcdn {
 213         struct res_common       com;
 214         int                     port;
 215 };
 216
 217 enum res_fs_rule_states {
 218         RES_FS_RULE_BUSY = RES_ANY_BUSY,
 219         RES_FS_RULE_ALLOCATED,
 220 };
 221
 222 struct res_fs_rule {
 223         struct res_common       com;
 224         int                     qpn;
 225         /* VF DMFS mbox with port flipped */
 226         void                    *mirr_mbox;
 227         /* > 0 --> apply mirror when getting into HA mode      */
 228         /* = 0 --> un-apply mirror when getting out of HA mode */
 229         u32                     mirr_mbox_size;
 230         struct list_head        mirr_list;
 231         u64                     mirr_rule_id;
 232 };
 233
 234 static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
 235 {
 236         struct rb_node *node = root->rb_node;
 237
 238         while (node) {
 239                 struct res_common *res = container_of(node, struct res_common,
 240                                                       node);
 241
 242                 if (res_id < res->res_id)
 243                         node = node->rb_left;
 244                 else if (res_id > res->res_id)
 245                         node = node->rb_right;
 246                 else
 247                         return res;
 248         }
 249         return NULL;
 250 }
 251
 252 static int res_tracker_insert(struct rb_root *root, struct res_common *res)
 253 {
 254         struct rb_node **new = &(root->rb_node), *parent = NULL;
 255
 256         /* Figure out where to put new node */
 257         while (*new) {
 258                 struct res_common *this = container_of(*new, struct res_common,
 259                                                        node);
 260
 261                 parent = *new;
 262                 if (res->res_id < this->res_id)
 263                         new = &((*new)->rb_left);
 264                 else if (res->res_id > this->res_id)
 265                         new = &((*new)->rb_right);
 266                 else
 267                         return -EEXIST;
 268         }
 269
 270         /* Add new node and rebalance tree. */
 271         rb_link_node(&res->node, parent, new);
 272         rb_insert_color(&res->node, root);
 273
 274         return 0;
 275 }
 276
 277 enum qp_transition {
 278         QP_TRANS_INIT2RTR,
 279         QP_TRANS_RTR2RTS,
 280         QP_TRANS_RTS2RTS,
 281         QP_TRANS_SQERR2RTS,
 282         QP_TRANS_SQD2SQD,
 283         QP_TRANS_SQD2RTS
 284 };
 285
 286 /* For Debug uses */
 287 static const char *resource_str(enum mlx4_resource rt)
 288 {
 289         switch (rt) {
 290         case RES_QP: return "RES_QP";
 291         case RES_CQ: return "RES_CQ";
 292         case RES_SRQ: return "RES_SRQ";
 293         case RES_MPT: return "RES_MPT";
 294         case RES_MTT: return "RES_MTT";
 295         case RES_MAC: return  "RES_MAC";
 296         case RES_VLAN: return  "RES_VLAN";
 297         case RES_EQ: return "RES_EQ";
 298         case RES_COUNTER: return "RES_COUNTER";
 299         case RES_FS_RULE: return "RES_FS_RULE";
 300         case RES_XRCD: return "RES_XRCD";
 301         default: return "Unknown resource type !!!";
 302         };
 303 }
 304
 305 static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
 306 static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
 307                                       enum mlx4_resource res_type, int count,
 308                                       int port)
 309 {
 310         struct mlx4_priv *priv = mlx4_priv(dev);
 311         struct resource_allocator *res_alloc =
 312                 &priv->mfunc.master.res_tracker.res_alloc[res_type];
 313         int err = -EINVAL;
 314         int allocated, free, reserved, guaranteed, from_free;
 315         int from_rsvd;
 316
 317         if (slave > dev->persist->num_vfs)
 318                 return -EINVAL;
 319
 320         spin_lock(&res_alloc->alloc_lock);
 321         allocated = (port > 0) ?
 322                 res_alloc->allocated[(port - 1) *
 323                 (dev->persist->num_vfs + 1) + slave] :
 324                 res_alloc->allocated[slave];
 325         free = (port > 0) ? res_alloc->res_port_free[port - 1] :
 326                 res_alloc->res_free;
 327         reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
 328                 res_alloc->res_reserved;
 329         guaranteed = res_alloc->guaranteed[slave];
 330
 331         if (allocated + count > res_alloc->quota[slave]) {
 332                 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
 333                           slave, port, resource_str(res_type), count,
 334                           allocated, res_alloc->quota[slave]);
 335                 goto out;
 336         }
 337
 338         if (allocated + count <= guaranteed) {
 339                 err = 0;
 340                 from_rsvd = count;
 341         } else {
 342                 /* portion may need to be obtained from free area */
 343                 if (guaranteed - allocated > 0)
 344                         from_free = count - (guaranteed - allocated);
 345                 else
 346                         from_free = count;
 347
 348                 from_rsvd = count - from_free;
 349
 350                 if (free - from_free >= reserved)
 351                         err = 0;
 352                 else
 353                         mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
 354                                   slave, port, resource_str(res_type), free,
 355                                   from_free, reserved);
 356         }
 357
 358         if (!err) {
 359                 /* grant the request */
 360                 if (port > 0) {
 361                         res_alloc->allocated[(port - 1) *
 362                         (dev->persist->num_vfs + 1) + slave] += count;
 363                         res_alloc->res_port_free[port - 1] -= count;
 364                         res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
 365                 } else {
 366                         res_alloc->allocated[slave] += count;
 367                         res_alloc->res_free -= count;
 368                         res_alloc->res_reserved -= from_rsvd;
 369                 }
 370         }
 371
 372 out:
 373         spin_unlock(&res_alloc->alloc_lock);
 374         return err;
 375 }
 376
 377 static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
 378                                     enum mlx4_resource res_type, int count,
 379                                     int port)
 380 {
 381         struct mlx4_priv *priv = mlx4_priv(dev);
 382         struct resource_allocator *res_alloc =
 383                 &priv->mfunc.master.res_tracker.res_alloc[res_type];
 384         int allocated, guaranteed, from_rsvd;
 385
 386         if (slave > dev->persist->num_vfs)
 387                 return;
 388
 389         spin_lock(&res_alloc->alloc_lock);
 390
 391         allocated = (port > 0) ?
 392                 res_alloc->allocated[(port - 1) *
 393                 (dev->persist->num_vfs + 1) + slave] :
 394                 res_alloc->allocated[slave];
 395         guaranteed = res_alloc->guaranteed[slave];
 396
 397         if (allocated - count >= guaranteed) {
 398                 from_rsvd = 0;
 399         } else {
 400                 /* portion may need to be returned to reserved area */
 401                 if (allocated - guaranteed > 0)
 402                         from_rsvd = count - (allocated - guaranteed);
 403                 else
 404                         from_rsvd = count;
 405         }
 406
 407         if (port > 0) {
 408                 res_alloc->allocated[(port - 1) *
 409                 (dev->persist->num_vfs + 1) + slave] -= count;
 410                 res_alloc->res_port_free[port - 1] += count;
 411                 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
 412         } else {
 413                 res_alloc->allocated[slave] -= count;
 414                 res_alloc->res_free += count;
 415                 res_alloc->res_reserved += from_rsvd;
 416         }
 417
 418         spin_unlock(&res_alloc->alloc_lock);
 419         return;
 420 }
 421
 422 static inline void initialize_res_quotas(struct mlx4_dev *dev,
 423                                          struct resource_allocator *res_alloc,
 424                                          enum mlx4_resource res_type,
 425                                          int vf, int num_instances)
 426 {
 427         res_alloc->guaranteed[vf] = num_instances /
 428                                     (2 * (dev->persist->num_vfs + 1));
 429         res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
 430         if (vf == mlx4_master_func_num(dev)) {
 431                 res_alloc->res_free = num_instances;
 432                 if (res_type == RES_MTT) {
 433                         /* reserved mtts will be taken out of the PF allocation */
 434                         res_alloc->res_free += dev->caps.reserved_mtts;
 435                         res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
 436                         res_alloc->quota[vf] += dev->caps.reserved_mtts;
 437                 }
 438         }
 439 }
 440
 441 void mlx4_init_quotas(struct mlx4_dev *dev)
 442 {
 443         struct mlx4_priv *priv = mlx4_priv(dev);
 444         int pf;
 445
 446         /* quotas for VFs are initialized in mlx4_slave_cap */
 447         if (mlx4_is_slave(dev))
 448                 return;
 449
 450         if (!mlx4_is_mfunc(dev)) {
 451                 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
 452                         mlx4_num_reserved_sqps(dev);
 453                 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
 454                 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
 455                 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
 456                 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
 457                 return;
 458         }
 459
 460         pf = mlx4_master_func_num(dev);
 461         dev->quotas.qp =
 462                 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
 463         dev->quotas.cq =
 464                 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
 465         dev->quotas.srq =
 466                 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
 467         dev->quotas.mtt =
 468                 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
 469         dev->quotas.mpt =
 470                 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
 471 }
 472
 473 static int get_max_gauranteed_vfs_counter(struct mlx4_dev *dev)
 474 {
 475         /* reduce the sink counter */
 476         return (dev->caps.max_counters - 1 -
 477                 (MLX4_PF_COUNTERS_PER_PORT * MLX4_MAX_PORTS))
 478                 / MLX4_MAX_PORTS;
 479 }
 480
 481 int mlx4_init_resource_tracker(struct mlx4_dev *dev)
 482 {
 483         struct mlx4_priv *priv = mlx4_priv(dev);
 484         int i, j;
 485         int t;
 486         int max_vfs_guarantee_counter = get_max_gauranteed_vfs_counter(dev);
 487
 488         priv->mfunc.master.res_tracker.slave_list =
 489                 kzalloc(dev->num_slaves * sizeof(struct slave_list),
 490                         GFP_KERNEL);
 491         if (!priv->mfunc.master.res_tracker.slave_list)
 492                 return -ENOMEM;
 493
 494         for (i = 0 ; i < dev->num_slaves; i++) {
 495                 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
 496                         INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
 497                                        slave_list[i].res_list[t]);
 498                 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
 499         }
 500
 501         mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
 502                  dev->num_slaves);
 503         for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
 504                 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
 505
 506         for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
 507                 struct resource_allocator *res_alloc =
 508                         &priv->mfunc.master.res_tracker.res_alloc[i];
 509                 res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) *
 510                                            sizeof(int), GFP_KERNEL);
 511                 res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) *
 512                                                 sizeof(int), GFP_KERNEL);
 513                 if (i == RES_MAC || i == RES_VLAN)
 514                         res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
 515                                                        (dev->persist->num_vfs
 516                                                        + 1) *
 517                                                        sizeof(int), GFP_KERNEL);
 518                 else
 519                         res_alloc->allocated = kzalloc((dev->persist->
 520                                                         num_vfs + 1) *
 521                                                        sizeof(int), GFP_KERNEL);
 522                 /* Reduce the sink counter */
 523                 if (i == RES_COUNTER)
 524                         res_alloc->res_free = dev->caps.max_counters - 1;
 525
 526                 if (!res_alloc->quota || !res_alloc->guaranteed ||
 527                     !res_alloc->allocated)
 528                         goto no_mem_err;
 529
 530                 spin_lock_init(&res_alloc->alloc_lock);
 531                 for (t = 0; t < dev->persist->num_vfs + 1; t++) {
 532                         struct mlx4_active_ports actv_ports =
 533                                 mlx4_get_active_ports(dev, t);
 534                         switch (i) {
 535                         case RES_QP:
 536                                 initialize_res_quotas(dev, res_alloc, RES_QP,
 537                                                       t, dev->caps.num_qps -
 538                                                       dev->caps.reserved_qps -
 539                                                       mlx4_num_reserved_sqps(dev));
 540                                 break;
 541                         case RES_CQ:
 542                                 initialize_res_quotas(dev, res_alloc, RES_CQ,
 543                                                       t, dev->caps.num_cqs -
 544                                                       dev->caps.reserved_cqs);
 545                                 break;
 546                         case RES_SRQ:
 547                                 initialize_res_quotas(dev, res_alloc, RES_SRQ,
 548                                                       t, dev->caps.num_srqs -
 549                                                       dev->caps.reserved_srqs);
 550                                 break;
 551                         case RES_MPT:
 552                                 initialize_res_quotas(dev, res_alloc, RES_MPT,
 553                                                       t, dev->caps.num_mpts -
 554                                                       dev->caps.reserved_mrws);
 555                                 break;
 556                         case RES_MTT:
 557                                 initialize_res_quotas(dev, res_alloc, RES_MTT,
 558                                                       t, dev->caps.num_mtts -
 559                                                       dev->caps.reserved_mtts);
 560                                 break;
 561                         case RES_MAC:
 562                                 if (t == mlx4_master_func_num(dev)) {
 563                                         int max_vfs_pport = 0;
 564                                         /* Calculate the max vfs per port for */
 565                                         /* both ports.                        */
 566                                         for (j = 0; j < dev->caps.num_ports;
 567                                              j++) {
 568                                                 struct mlx4_slaves_pport slaves_pport =
 569                                                         mlx4_phys_to_slaves_pport(dev, j + 1);
 570                                                 unsigned current_slaves =
 571                                                         bitmap_weight(slaves_pport.slaves,
 572                                                                       dev->caps.num_ports) - 1;
 573                                                 if (max_vfs_pport < current_slaves)
 574                                                         max_vfs_pport =
 575                                                                 current_slaves;
 576                                         }
 577                                         res_alloc->quota[t] =
 578                                                 MLX4_MAX_MAC_NUM -
 579                                                 2 * max_vfs_pport;
 580                                         res_alloc->guaranteed[t] = 2;
 581                                         for (j = 0; j < MLX4_MAX_PORTS; j++)
 582                                                 res_alloc->res_port_free[j] =
 583                                                         MLX4_MAX_MAC_NUM;
 584                                 } else {
 585                                         res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
 586                                         res_alloc->guaranteed[t] = 2;
 587                                 }
 588                                 break;
 589                         case RES_VLAN:
 590                                 if (t == mlx4_master_func_num(dev)) {
 591                                         res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
 592                                         res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
 593                                         for (j = 0; j < MLX4_MAX_PORTS; j++)
 594                                                 res_alloc->res_port_free[j] =
 595                                                         res_alloc->quota[t];
 596                                 } else {
 597                                         res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
 598                                         res_alloc->guaranteed[t] = 0;
 599                                 }
 600                                 break;
 601                         case RES_COUNTER:
 602                                 res_alloc->quota[t] = dev->caps.max_counters;
 603                                 if (t == mlx4_master_func_num(dev))
 604                                         res_alloc->guaranteed[t] =
 605                                                 MLX4_PF_COUNTERS_PER_PORT *
 606                                                 MLX4_MAX_PORTS;
 607                                 else if (t <= max_vfs_guarantee_counter)
 608                                         res_alloc->guaranteed[t] =
 609                                                 MLX4_VF_COUNTERS_PER_PORT *
 610                                                 MLX4_MAX_PORTS;
 611                                 else
 612                                         res_alloc->guaranteed[t] = 0;
 613                                 res_alloc->res_free -= res_alloc->guaranteed[t];
 614                                 break;
 615                         default:
 616                                 break;
 617                         }
 618                         if (i == RES_MAC || i == RES_VLAN) {
 619                                 for (j = 0; j < dev->caps.num_ports; j++)
 620                                         if (test_bit(j, actv_ports.ports))
 621                                                 res_alloc->res_port_rsvd[j] +=
 622                                                         res_alloc->guaranteed[t];
 623                         } else {
 624                                 res_alloc->res_reserved += res_alloc->guaranteed[t];
 625                         }
 626                 }
 627         }
 628         spin_lock_init(&priv->mfunc.master.res_tracker.lock);
 629         return 0;
 630
 631 no_mem_err:
 632         for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
 633                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
 634                 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
 635                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
 636                 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
 637                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
 638                 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
 639         }
 640         return -ENOMEM;
 641 }
 642
 643 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
 644                                 enum mlx4_res_tracker_free_type type)
 645 {
 646         struct mlx4_priv *priv = mlx4_priv(dev);
 647         int i;
 648
 649         if (priv->mfunc.master.res_tracker.slave_list) {
 650                 if (type != RES_TR_FREE_STRUCTS_ONLY) {
 651                         for (i = 0; i < dev->num_slaves; i++) {
 652                                 if (type == RES_TR_FREE_ALL ||
 653                                     dev->caps.function != i)
 654                                         mlx4_delete_all_resources_for_slave(dev, i);
 655                         }
 656                         /* free master's vlans */
 657                         i = dev->caps.function;
 658                         mlx4_reset_roce_gids(dev, i);
 659                         mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
 660                         rem_slave_vlans(dev, i);
 661                         mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
 662                 }
 663
 664                 if (type != RES_TR_FREE_SLAVES_ONLY) {
 665                         for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
 666                                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
 667                                 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
 668                                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
 669                                 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
 670                                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
 671                                 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
 672                         }
 673                         kfree(priv->mfunc.master.res_tracker.slave_list);
 674                         priv->mfunc.master.res_tracker.slave_list = NULL;
 675                 }
 676         }
 677 }
 678
 679 static void update_pkey_index(struct mlx4_dev *dev, int slave,
 680                               struct mlx4_cmd_mailbox *inbox)
 681 {
 682         u8 sched = *(u8 *)(inbox->buf + 64);
 683         u8 orig_index = *(u8 *)(inbox->buf + 35);
 684         u8 new_index;
 685         struct mlx4_priv *priv = mlx4_priv(dev);
 686         int port;
 687
 688         port = (sched >> 6 & 1) + 1;
 689
 690         new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
 691         *(u8 *)(inbox->buf + 35) = new_index;
 692 }
 693
 694 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
 695                        u8 slave)
 696 {
 697         struct mlx4_qp_context  *qp_ctx = inbox->buf + 8;
 698         enum mlx4_qp_optpar     optpar = be32_to_cpu(*(__be32 *) inbox->buf);
 699         u32                     ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
 700         int port;
 701
 702         if (MLX4_QP_ST_UD == ts) {
 703                 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
 704                 if (mlx4_is_eth(dev, port))
 705                         qp_ctx->pri_path.mgid_index =
 706                                 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
 707                 else
 708                         qp_ctx->pri_path.mgid_index = slave | 0x80;
 709
 710         } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
 711                 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
 712                         port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
 713                         if (mlx4_is_eth(dev, port)) {
 714                                 qp_ctx->pri_path.mgid_index +=
 715                                         mlx4_get_base_gid_ix(dev, slave, port);
 716                                 qp_ctx->pri_path.mgid_index &= 0x7f;
 717                         } else {
 718                                 qp_ctx->pri_path.mgid_index = slave & 0x7F;
 719                         }
 720                 }
 721                 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
 722                         port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
 723                         if (mlx4_is_eth(dev, port)) {
 724                                 qp_ctx->alt_path.mgid_index +=
 725                                         mlx4_get_base_gid_ix(dev, slave, port);
 726                                 qp_ctx->alt_path.mgid_index &= 0x7f;
 727                         } else {
 728                                 qp_ctx->alt_path.mgid_index = slave & 0x7F;
 729                         }
 730                 }
 731         }
 732 }
 733
 734 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
 735                           u8 slave, int port);
 736
 737 static int update_vport_qp_param(struct mlx4_dev *dev,
 738                                  struct mlx4_cmd_mailbox *inbox,
 739                                  u8 slave, u32 qpn)
 740 {
 741         struct mlx4_qp_context  *qpc = inbox->buf + 8;
 742         struct mlx4_vport_oper_state *vp_oper;
 743         struct mlx4_priv *priv;
 744         u32 qp_type;
 745         int port, err = 0;
 746
 747         port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
 748         priv = mlx4_priv(dev);
 749         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
 750         qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
 751
 752         err = handle_counter(dev, qpc, slave, port);
 753         if (err)
 754                 goto out;
 755
 756         if (MLX4_VGT != vp_oper->state.default_vlan) {
 757                 /* the reserved QPs (special, proxy, tunnel)
 758                  * do not operate over vlans
 759                  */
 760                 if (mlx4_is_qp_reserved(dev, qpn))
 761                         return 0;
 762
 763                 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
 764                 if (qp_type == MLX4_QP_ST_UD ||
 765                     (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
 766                         if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
 767                                 *(__be32 *)inbox->buf =
 768                                         cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
 769                                         MLX4_QP_OPTPAR_VLAN_STRIPPING);
 770                                 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
 771                         } else {
 772                                 struct mlx4_update_qp_params params = {.flags = 0};
 773
 774                                 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, &params);
 775                                 if (err)
 776                                         goto out;
 777                         }
 778                 }
 779
 780                 /* preserve IF_COUNTER flag */
 781                 qpc->pri_path.vlan_control &=
 782                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
 783                 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
 784                     dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
 785                         qpc->pri_path.vlan_control |=
 786                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 787                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
 788                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
 789                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
 790                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
 791                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
 792                 } else if (0 != vp_oper->state.default_vlan) {
 793                         if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD)) {
 794                                 /* vst QinQ should block untagged on TX,
 795                                  * but cvlan is in payload and phv is set so
 796                                  * hw see it as untagged. Block tagged instead.
 797                                  */
 798                                 qpc->pri_path.vlan_control |=
 799                                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
 800                                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 801                                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
 802                                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
 803                         } else { /* vst 802.1Q */
 804                                 qpc->pri_path.vlan_control |=
 805                                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 806                                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
 807                                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
 808                         }
 809                 } else { /* priority tagged */
 810                         qpc->pri_path.vlan_control |=
 811                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 812                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
 813                 }
 814
 815                 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
 816                 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
 817                 qpc->pri_path.fl |= MLX4_FL_ETH_HIDE_CQE_VLAN;
 818                 if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD))
 819                         qpc->pri_path.fl |= MLX4_FL_SV;
 820                 else
 821                         qpc->pri_path.fl |= MLX4_FL_CV;
 822                 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
 823                 qpc->pri_path.sched_queue &= 0xC7;
 824                 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
 825                 qpc->qos_vport = vp_oper->state.qos_vport;
 826         }
 827         if (vp_oper->state.spoofchk) {
 828                 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
 829                 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
 830         }
 831 out:
 832         return err;
 833 }
 834
 835 static int mpt_mask(struct mlx4_dev *dev)
 836 {
 837         return dev->caps.num_mpts - 1;
 838 }
 839
 840 static void *find_res(struct mlx4_dev *dev, u64 res_id,
 841                       enum mlx4_resource type)
 842 {
 843         struct mlx4_priv *priv = mlx4_priv(dev);
 844
 845         return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
 846                                   res_id);
 847 }
 848
 849 static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
 850                    enum mlx4_resource type,
 851                    void *res)
 852 {
 853         struct res_common *r;
 854         int err = 0;
 855
 856         spin_lock_irq(mlx4_tlock(dev));
 857         r = find_res(dev, res_id, type);
 858         if (!r) {
 859                 err = -ENONET;
 860                 goto exit;
 861         }
 862
 863         if (r->state == RES_ANY_BUSY) {
 864                 err = -EBUSY;
 865                 goto exit;
 866         }
 867
 868         if (r->owner != slave) {
 869                 err = -EPERM;
 870                 goto exit;
 871         }
 872
 873         r->from_state = r->state;
 874         r->state = RES_ANY_BUSY;
 875
 876         if (res)
 877                 *((struct res_common **)res) = r;
 878
 879 exit:
 880         spin_unlock_irq(mlx4_tlock(dev));
 881         return err;
 882 }
 883
 884 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
 885                                     enum mlx4_resource type,
 886                                     u64 res_id, int *slave)
 887 {
 888
 889         struct res_common *r;
 890         int err = -ENOENT;
 891         int id = res_id;
 892
 893         if (type == RES_QP)
 894                 id &= 0x7fffff;
 895         spin_lock(mlx4_tlock(dev));
 896
 897         r = find_res(dev, id, type);
 898         if (r) {
 899                 *slave = r->owner;
 900                 err = 0;
 901         }
 902         spin_unlock(mlx4_tlock(dev));
 903
 904         return err;
 905 }
 906
 907 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
 908                     enum mlx4_resource type)
 909 {
 910         struct res_common *r;
 911
 912         spin_lock_irq(mlx4_tlock(dev));
 913         r = find_res(dev, res_id, type);
 914         if (r)
 915                 r->state = r->from_state;
 916         spin_unlock_irq(mlx4_tlock(dev));
 917 }
 918
 919 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
 920                              u64 in_param, u64 *out_param, int port);
 921
 922 static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port,
 923                                    int counter_index)
 924 {
 925         struct res_common *r;
 926         struct res_counter *counter;
 927         int ret = 0;
 928
 929         if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
 930                 return ret;
 931
 932         spin_lock_irq(mlx4_tlock(dev));
 933         r = find_res(dev, counter_index, RES_COUNTER);
 934         if (!r || r->owner != slave) {
 935                 ret = -EINVAL;
 936         } else {
 937                 counter = container_of(r, struct res_counter, com);
 938                 if (!counter->port)
 939                         counter->port = port;
 940         }
 941
 942         spin_unlock_irq(mlx4_tlock(dev));
 943         return ret;
 944 }
 945
 946 static int handle_unexisting_counter(struct mlx4_dev *dev,
 947                                      struct mlx4_qp_context *qpc, u8 slave,
 948                                      int port)
 949 {
 950         struct mlx4_priv *priv = mlx4_priv(dev);
 951         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
 952         struct res_common *tmp;
 953         struct res_counter *counter;
 954         u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev);
 955         int err = 0;
 956
 957         spin_lock_irq(mlx4_tlock(dev));
 958         list_for_each_entry(tmp,
 959                             &tracker->slave_list[slave].res_list[RES_COUNTER],
 960                             list) {
 961                 counter = container_of(tmp, struct res_counter, com);
 962                 if (port == counter->port) {
 963                         qpc->pri_path.counter_index  = counter->com.res_id;
 964                         spin_unlock_irq(mlx4_tlock(dev));
 965                         return 0;
 966                 }
 967         }
 968         spin_unlock_irq(mlx4_tlock(dev));
 969
 970         /* No existing counter, need to allocate a new counter */
 971         err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx,
 972                                 port);
 973         if (err == -ENOENT) {
 974                 err = 0;
 975         } else if (err && err != -ENOSPC) {
 976                 mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n",
 977                          __func__, slave, err);
 978         } else {
 979                 qpc->pri_path.counter_index = counter_idx;
 980                 mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n",
 981                          __func__, slave, qpc->pri_path.counter_index);
 982                 err = 0;
 983         }
 984
 985         return err;
 986 }
 987
 988 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
 989                           u8 slave, int port)
 990 {
 991         if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev))
 992                 return handle_existing_counter(dev, slave, port,
 993                                                qpc->pri_path.counter_index);
 994
 995         return handle_unexisting_counter(dev, qpc, slave, port);
 996 }
 997
 998 static struct res_common *alloc_qp_tr(int id)
 999 {
1000         struct res_qp *ret;
1001
1002         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1003         if (!ret)
1004                 return NULL;
1005
1006         ret->com.res_id = id;
1007         ret->com.state = RES_QP_RESERVED;
1008         ret->local_qpn = id;
1009         INIT_LIST_HEAD(&ret->mcg_list);
1010         spin_lock_init(&ret->mcg_spl);
1011         atomic_set(&ret->ref_count, 0);
1012
1013         return &ret->com;
1014 }
1015
1016 static struct res_common *alloc_mtt_tr(int id, int order)
1017 {
1018         struct res_mtt *ret;
1019
1020         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1021         if (!ret)
1022                 return NULL;
1023
1024         ret->com.res_id = id;
1025         ret->order = order;
1026         ret->com.state = RES_MTT_ALLOCATED;
1027         atomic_set(&ret->ref_count, 0);
1028
1029         return &ret->com;
1030 }
1031
1032 static struct res_common *alloc_mpt_tr(int id, int key)
1033 {
1034         struct res_mpt *ret;
1035
1036         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1037         if (!ret)
1038                 return NULL;
1039
1040         ret->com.res_id = id;
1041         ret->com.state = RES_MPT_RESERVED;
1042         ret->key = key;
1043
1044         return &ret->com;
1045 }
1046
1047 static struct res_common *alloc_eq_tr(int id)
1048 {
1049         struct res_eq *ret;
1050
1051         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1052         if (!ret)
1053                 return NULL;
1054
1055         ret->com.res_id = id;
1056         ret->com.state = RES_EQ_RESERVED;
1057
1058         return &ret->com;
1059 }
1060
1061 static struct res_common *alloc_cq_tr(int id)
1062 {
1063         struct res_cq *ret;
1064
1065         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1066         if (!ret)
1067                 return NULL;
1068
1069         ret->com.res_id = id;
1070         ret->com.state = RES_CQ_ALLOCATED;
1071         atomic_set(&ret->ref_count, 0);
1072
1073         return &ret->com;
1074 }
1075
1076 static struct res_common *alloc_srq_tr(int id)
1077 {
1078         struct res_srq *ret;
1079
1080         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1081         if (!ret)
1082                 return NULL;
1083
1084         ret->com.res_id = id;
1085         ret->com.state = RES_SRQ_ALLOCATED;
1086         atomic_set(&ret->ref_count, 0);
1087
1088         return &ret->com;
1089 }
1090
1091 static struct res_common *alloc_counter_tr(int id, int port)
1092 {
1093         struct res_counter *ret;
1094
1095         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1096         if (!ret)
1097                 return NULL;
1098
1099         ret->com.res_id = id;
1100         ret->com.state = RES_COUNTER_ALLOCATED;
1101         ret->port = port;
1102
1103         return &ret->com;
1104 }
1105
1106 static struct res_common *alloc_xrcdn_tr(int id)
1107 {
1108         struct res_xrcdn *ret;
1109
1110         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1111         if (!ret)
1112                 return NULL;
1113
1114         ret->com.res_id = id;
1115         ret->com.state = RES_XRCD_ALLOCATED;
1116
1117         return &ret->com;
1118 }
1119
1120 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1121 {
1122         struct res_fs_rule *ret;
1123
1124         ret = kzalloc(sizeof *ret, GFP_KERNEL);
1125         if (!ret)
1126                 return NULL;
1127
1128         ret->com.res_id = id;
1129         ret->com.state = RES_FS_RULE_ALLOCATED;
1130         ret->qpn = qpn;
1131         return &ret->com;
1132 }
1133
1134 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
1135                                    int extra)
1136 {
1137         struct res_common *ret;
1138
1139         switch (type) {
1140         case RES_QP:
1141                 ret = alloc_qp_tr(id);
1142                 break;
1143         case RES_MPT:
1144                 ret = alloc_mpt_tr(id, extra);
1145                 break;
1146         case RES_MTT:
1147                 ret = alloc_mtt_tr(id, extra);
1148                 break;
1149         case RES_EQ:
1150                 ret = alloc_eq_tr(id);
1151                 break;
1152         case RES_CQ:
1153                 ret = alloc_cq_tr(id);
1154                 break;
1155         case RES_SRQ:
1156                 ret = alloc_srq_tr(id);
1157                 break;
1158         case RES_MAC:
1159                 pr_err("implementation missing\n");
1160                 return NULL;
1161         case RES_COUNTER:
1162                 ret = alloc_counter_tr(id, extra);
1163                 break;
1164         case RES_XRCD:
1165                 ret = alloc_xrcdn_tr(id);
1166                 break;
1167         case RES_FS_RULE:
1168                 ret = alloc_fs_rule_tr(id, extra);
1169                 break;
1170         default:
1171                 return NULL;
1172         }
1173         if (ret)
1174                 ret->owner = slave;
1175
1176         return ret;
1177 }
1178
1179 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1180                           struct mlx4_counter *data)
1181 {
1182         struct mlx4_priv *priv = mlx4_priv(dev);
1183         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1184         struct res_common *tmp;
1185         struct res_counter *counter;
1186         int *counters_arr;
1187         int i = 0, err = 0;
1188
1189         memset(data, 0, sizeof(*data));
1190
1191         counters_arr = kmalloc_array(dev->caps.max_counters,
1192                                      sizeof(*counters_arr), GFP_KERNEL);
1193         if (!counters_arr)
1194                 return -ENOMEM;
1195
1196         spin_lock_irq(mlx4_tlock(dev));
1197         list_for_each_entry(tmp,
1198                             &tracker->slave_list[slave].res_list[RES_COUNTER],
1199                             list) {
1200                 counter = container_of(tmp, struct res_counter, com);
1201                 if (counter->port == port) {
1202                         counters_arr[i] = (int)tmp->res_id;
1203                         i++;
1204                 }
1205         }
1206         spin_unlock_irq(mlx4_tlock(dev));
1207         counters_arr[i] = -1;
1208
1209         i = 0;
1210
1211         while (counters_arr[i] != -1) {
1212                 err = mlx4_get_counter_stats(dev, counters_arr[i], data,
1213                                              0);
1214                 if (err) {
1215                         memset(data, 0, sizeof(*data));
1216                         goto table_changed;
1217                 }
1218                 i++;
1219         }
1220
1221 table_changed:
1222         kfree(counters_arr);
1223         return 0;
1224 }
1225
1226 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1227                          enum mlx4_resource type, int extra)
1228 {
1229         int i;
1230         int err;
1231         struct mlx4_priv *priv = mlx4_priv(dev);
1232         struct res_common **res_arr;
1233         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1234         struct rb_root *root = &tracker->res_tree[type];
1235
1236         res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1237         if (!res_arr)
1238                 return -ENOMEM;
1239
1240         for (i = 0; i < count; ++i) {
1241                 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1242                 if (!res_arr[i]) {
1243                         for (--i; i >= 0; --i)
1244                                 kfree(res_arr[i]);
1245
1246                         kfree(res_arr);
1247                         return -ENOMEM;
1248                 }
1249         }
1250
1251         spin_lock_irq(mlx4_tlock(dev));
1252         for (i = 0; i < count; ++i) {
1253                 if (find_res(dev, base + i, type)) {
1254                         err = -EEXIST;
1255                         goto undo;
1256                 }
1257                 err = res_tracker_insert(root, res_arr[i]);
1258                 if (err)
1259                         goto undo;
1260                 list_add_tail(&res_arr[i]->list,
1261                               &tracker->slave_list[slave].res_list[type]);
1262         }
1263         spin_unlock_irq(mlx4_tlock(dev));
1264         kfree(res_arr);
1265
1266         return 0;
1267
1268 undo:
1269         for (--i; i >= 0; --i) {
1270                 rb_erase(&res_arr[i]->node, root);
1271                 list_del_init(&res_arr[i]->list);
1272         }
1273
1274         spin_unlock_irq(mlx4_tlock(dev));
1275
1276         for (i = 0; i < count; ++i)
1277                 kfree(res_arr[i]);
1278
1279         kfree(res_arr);
1280
1281         return err;
1282 }
1283
1284 static int remove_qp_ok(struct res_qp *res)
1285 {
1286         if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1287             !list_empty(&res->mcg_list)) {
1288                 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1289                        res->com.state, atomic_read(&res->ref_count));
1290                 return -EBUSY;
1291         } else if (res->com.state != RES_QP_RESERVED) {
1292                 return -EPERM;
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int remove_mtt_ok(struct res_mtt *res, int order)
1299 {
1300         if (res->com.state == RES_MTT_BUSY ||
1301             atomic_read(&res->ref_count)) {
1302                 pr_devel("%s-%d: state %s, ref_count %d\n",
1303                          __func__, __LINE__,
1304                          mtt_states_str(res->com.state),
1305                          atomic_read(&res->ref_count));
1306                 return -EBUSY;
1307         } else if (res->com.state != RES_MTT_ALLOCATED)
1308                 return -EPERM;
1309         else if (res->order != order)
1310                 return -EINVAL;
1311
1312         return 0;
1313 }
1314
1315 static int remove_mpt_ok(struct res_mpt *res)
1316 {
1317         if (res->com.state == RES_MPT_BUSY)
1318                 return -EBUSY;
1319         else if (res->com.state != RES_MPT_RESERVED)
1320                 return -EPERM;
1321
1322         return 0;
1323 }
1324
1325 static int remove_eq_ok(struct res_eq *res)
1326 {
1327         if (res->com.state == RES_MPT_BUSY)
1328                 return -EBUSY;
1329         else if (res->com.state != RES_MPT_RESERVED)
1330                 return -EPERM;
1331
1332         return 0;
1333 }
1334
1335 static int remove_counter_ok(struct res_counter *res)
1336 {
1337         if (res->com.state == RES_COUNTER_BUSY)
1338                 return -EBUSY;
1339         else if (res->com.state != RES_COUNTER_ALLOCATED)
1340                 return -EPERM;
1341
1342         return 0;
1343 }
1344
1345 static int remove_xrcdn_ok(struct res_xrcdn *res)
1346 {
1347         if (res->com.state == RES_XRCD_BUSY)
1348                 return -EBUSY;
1349         else if (res->com.state != RES_XRCD_ALLOCATED)
1350                 return -EPERM;
1351
1352         return 0;
1353 }
1354
1355 static int remove_fs_rule_ok(struct res_fs_rule *res)
1356 {
1357         if (res->com.state == RES_FS_RULE_BUSY)
1358                 return -EBUSY;
1359         else if (res->com.state != RES_FS_RULE_ALLOCATED)
1360                 return -EPERM;
1361
1362         return 0;
1363 }
1364
1365 static int remove_cq_ok(struct res_cq *res)
1366 {
1367         if (res->com.state == RES_CQ_BUSY)
1368                 return -EBUSY;
1369         else if (res->com.state != RES_CQ_ALLOCATED)
1370                 return -EPERM;
1371
1372         return 0;
1373 }
1374
1375 static int remove_srq_ok(struct res_srq *res)
1376 {
1377         if (res->com.state == RES_SRQ_BUSY)
1378                 return -EBUSY;
1379         else if (res->com.state != RES_SRQ_ALLOCATED)
1380                 return -EPERM;
1381
1382         return 0;
1383 }
1384
1385 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1386 {
1387         switch (type) {
1388         case RES_QP:
1389                 return remove_qp_ok((struct res_qp *)res);
1390         case RES_CQ:
1391                 return remove_cq_ok((struct res_cq *)res);
1392         case RES_SRQ:
1393                 return remove_srq_ok((struct res_srq *)res);
1394         case RES_MPT:
1395                 return remove_mpt_ok((struct res_mpt *)res);
1396         case RES_MTT:
1397                 return remove_mtt_ok((struct res_mtt *)res, extra);
1398         case RES_MAC:
1399                 return -ENOSYS;
1400         case RES_EQ:
1401                 return remove_eq_ok((struct res_eq *)res);
1402         case RES_COUNTER:
1403                 return remove_counter_ok((struct res_counter *)res);
1404         case RES_XRCD:
1405                 return remove_xrcdn_ok((struct res_xrcdn *)res);
1406         case RES_FS_RULE:
1407                 return remove_fs_rule_ok((struct res_fs_rule *)res);
1408         default:
1409                 return -EINVAL;
1410         }
1411 }
1412
1413 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1414                          enum mlx4_resource type, int extra)
1415 {
1416         u64 i;
1417         int err;
1418         struct mlx4_priv *priv = mlx4_priv(dev);
1419         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1420         struct res_common *r;
1421
1422         spin_lock_irq(mlx4_tlock(dev));
1423         for (i = base; i < base + count; ++i) {
1424                 r = res_tracker_lookup(&tracker->res_tree[type], i);
1425                 if (!r) {
1426                         err = -ENOENT;
1427                         goto out;
1428                 }
1429                 if (r->owner != slave) {
1430                         err = -EPERM;
1431                         goto out;
1432                 }
1433                 err = remove_ok(r, type, extra);
1434                 if (err)
1435                         goto out;
1436         }
1437
1438         for (i = base; i < base + count; ++i) {
1439                 r = res_tracker_lookup(&tracker->res_tree[type], i);
1440                 rb_erase(&r->node, &tracker->res_tree[type]);
1441                 list_del(&r->list);
1442                 kfree(r);
1443         }
1444         err = 0;
1445
1446 out:
1447         spin_unlock_irq(mlx4_tlock(dev));
1448
1449         return err;
1450 }
1451
1452 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1453                                 enum res_qp_states state, struct res_qp **qp,
1454                                 int alloc)
1455 {
1456         struct mlx4_priv *priv = mlx4_priv(dev);
1457         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1458         struct res_qp *r;
1459         int err = 0;
1460
1461         spin_lock_irq(mlx4_tlock(dev));
1462         r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
1463         if (!r)
1464                 err = -ENOENT;
1465         else if (r->com.owner != slave)
1466                 err = -EPERM;
1467         else {
1468                 switch (state) {
1469                 case RES_QP_BUSY:
1470                         mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
1471                                  __func__, r->com.res_id);
1472                         err = -EBUSY;
1473                         break;
1474
1475                 case RES_QP_RESERVED:
1476                         if (r->com.state == RES_QP_MAPPED && !alloc)
1477                                 break;
1478
1479                         mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
1480                         err = -EINVAL;
1481                         break;
1482
1483                 case RES_QP_MAPPED:
1484                         if ((r->com.state == RES_QP_RESERVED && alloc) ||
1485                             r->com.state == RES_QP_HW)
1486                                 break;
1487                         else {
1488                                 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
1489                                           r->com.res_id);
1490                                 err = -EINVAL;
1491                         }
1492
1493                         break;
1494
1495                 case RES_QP_HW:
1496                         if (r->com.state != RES_QP_MAPPED)
1497                                 err = -EINVAL;
1498                         break;
1499                 default:
1500                         err = -EINVAL;
1501                 }
1502
1503                 if (!err) {
1504                         r->com.from_state = r->com.state;
1505                         r->com.to_state = state;
1506                         r->com.state = RES_QP_BUSY;
1507                         if (qp)
1508                                 *qp = r;
1509                 }
1510         }
1511
1512         spin_unlock_irq(mlx4_tlock(dev));
1513
1514         return err;
1515 }
1516
1517 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1518                                 enum res_mpt_states state, struct res_mpt **mpt)
1519 {
1520         struct mlx4_priv *priv = mlx4_priv(dev);
1521         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1522         struct res_mpt *r;
1523         int err = 0;
1524
1525         spin_lock_irq(mlx4_tlock(dev));
1526         r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
1527         if (!r)
1528                 err = -ENOENT;
1529         else if (r->com.owner != slave)
1530                 err = -EPERM;
1531         else {
1532                 switch (state) {
1533                 case RES_MPT_BUSY:
1534                         err = -EINVAL;
1535                         break;
1536
1537                 case RES_MPT_RESERVED:
1538                         if (r->com.state != RES_MPT_MAPPED)
1539                                 err = -EINVAL;
1540                         break;
1541
1542                 case RES_MPT_MAPPED:
1543                         if (r->com.state != RES_MPT_RESERVED &&
1544                             r->com.state != RES_MPT_HW)
1545                                 err = -EINVAL;
1546                         break;
1547
1548                 case RES_MPT_HW:
1549                         if (r->com.state != RES_MPT_MAPPED)
1550                                 err = -EINVAL;
1551                         break;
1552                 default:
1553                         err = -EINVAL;
1554                 }
1555
1556                 if (!err) {
1557                         r->com.from_state = r->com.state;
1558                         r->com.to_state = state;
1559                         r->com.state = RES_MPT_BUSY;
1560                         if (mpt)
1561                                 *mpt = r;
1562                 }
1563         }
1564
1565         spin_unlock_irq(mlx4_tlock(dev));
1566
1567         return err;
1568 }
1569
1570 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1571                                 enum res_eq_states state, struct res_eq **eq)
1572 {
1573         struct mlx4_priv *priv = mlx4_priv(dev);
1574         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1575         struct res_eq *r;
1576         int err = 0;
1577
1578         spin_lock_irq(mlx4_tlock(dev));
1579         r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
1580         if (!r)
1581                 err = -ENOENT;
1582         else if (r->com.owner != slave)
1583                 err = -EPERM;
1584         else {
1585                 switch (state) {
1586                 case RES_EQ_BUSY:
1587                         err = -EINVAL;
1588                         break;
1589
1590                 case RES_EQ_RESERVED:
1591                         if (r->com.state != RES_EQ_HW)
1592                                 err = -EINVAL;
1593                         break;
1594
1595                 case RES_EQ_HW:
1596                         if (r->com.state != RES_EQ_RESERVED)
1597                                 err = -EINVAL;
1598                         break;
1599
1600                 default:
1601                         err = -EINVAL;
1602                 }
1603
1604                 if (!err) {
1605                         r->com.from_state = r->com.state;
1606                         r->com.to_state = state;
1607                         r->com.state = RES_EQ_BUSY;
1608                 }
1609         }
1610
1611         spin_unlock_irq(mlx4_tlock(dev));
1612
1613         if (!err && eq)
1614                 *eq = r;
1615
1616         return err;
1617 }
1618
1619 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1620                                 enum res_cq_states state, struct res_cq **cq)
1621 {
1622         struct mlx4_priv *priv = mlx4_priv(dev);
1623         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1624         struct res_cq *r;
1625         int err;
1626
1627         spin_lock_irq(mlx4_tlock(dev));
1628         r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
1629         if (!r) {
1630                 err = -ENOENT;
1631         } else if (r->com.owner != slave) {
1632                 err = -EPERM;
1633         } else if (state == RES_CQ_ALLOCATED) {
1634                 if (r->com.state != RES_CQ_HW)
1635                         err = -EINVAL;
1636                 else if (atomic_read(&r->ref_count))
1637                         err = -EBUSY;
1638                 else
1639                         err = 0;
1640         } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1641                 err = -EINVAL;
1642         } else {
1643                 err = 0;
1644         }
1645
1646         if (!err) {
1647                 r->com.from_state = r->com.state;
1648                 r->com.to_state = state;
1649                 r->com.state = RES_CQ_BUSY;
1650                 if (cq)
1651                         *cq = r;
1652         }
1653
1654         spin_unlock_irq(mlx4_tlock(dev));
1655
1656         return err;
1657 }
1658
1659 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1660                                  enum res_srq_states state, struct res_srq **srq)
1661 {
1662         struct mlx4_priv *priv = mlx4_priv(dev);
1663         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1664         struct res_srq *r;
1665         int err = 0;
1666
1667         spin_lock_irq(mlx4_tlock(dev));
1668         r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
1669         if (!r) {
1670                 err = -ENOENT;
1671         } else if (r->com.owner != slave) {
1672                 err = -EPERM;
1673         } else if (state == RES_SRQ_ALLOCATED) {
1674                 if (r->com.state != RES_SRQ_HW)
1675                         err = -EINVAL;
1676                 else if (atomic_read(&r->ref_count))
1677                         err = -EBUSY;
1678         } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1679                 err = -EINVAL;
1680         }
1681
1682         if (!err) {
1683                 r->com.from_state = r->com.state;
1684                 r->com.to_state = state;
1685                 r->com.state = RES_SRQ_BUSY;
1686                 if (srq)
1687                         *srq = r;
1688         }
1689
1690         spin_unlock_irq(mlx4_tlock(dev));
1691
1692         return err;
1693 }
1694
1695 static void res_abort_move(struct mlx4_dev *dev, int slave,
1696                            enum mlx4_resource type, int id)
1697 {
1698         struct mlx4_priv *priv = mlx4_priv(dev);
1699         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1700         struct res_common *r;
1701
1702         spin_lock_irq(mlx4_tlock(dev));
1703         r = res_tracker_lookup(&tracker->res_tree[type], id);
1704         if (r && (r->owner == slave))
1705                 r->state = r->from_state;
1706         spin_unlock_irq(mlx4_tlock(dev));
1707 }
1708
1709 static void res_end_move(struct mlx4_dev *dev, int slave,
1710                          enum mlx4_resource type, int id)
1711 {
1712         struct mlx4_priv *priv = mlx4_priv(dev);
1713         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1714         struct res_common *r;
1715
1716         spin_lock_irq(mlx4_tlock(dev));
1717         r = res_tracker_lookup(&tracker->res_tree[type], id);
1718         if (r && (r->owner == slave))
1719                 r->state = r->to_state;
1720         spin_unlock_irq(mlx4_tlock(dev));
1721 }
1722
1723 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1724 {
1725         return mlx4_is_qp_reserved(dev, qpn) &&
1726                 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
1727 }
1728
1729 static int fw_reserved(struct mlx4_dev *dev, int qpn)
1730 {
1731         return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1732 }
1733
1734 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1735                         u64 in_param, u64 *out_param)
1736 {
1737         int err;
1738         int count;
1739         int align;
1740         int base;
1741         int qpn;
1742         u8 flags;
1743
1744         switch (op) {
1745         case RES_OP_RESERVE:
1746                 count = get_param_l(&in_param) & 0xffffff;
1747                 /* Turn off all unsupported QP allocation flags that the
1748                  * slave tries to set.
1749                  */
1750                 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
1751                 align = get_param_h(&in_param);
1752                 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
1753                 if (err)
1754                         return err;
1755
1756                 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
1757                 if (err) {
1758                         mlx4_release_resource(dev, slave, RES_QP, count, 0);
1759                         return err;
1760                 }
1761
1762                 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1763                 if (err) {
1764                         mlx4_release_resource(dev, slave, RES_QP, count, 0);
1765                         __mlx4_qp_release_range(dev, base, count);
1766                         return err;
1767                 }
1768                 set_param_l(out_param, base);
1769                 break;
1770         case RES_OP_MAP_ICM:
1771                 qpn = get_param_l(&in_param) & 0x7fffff;
1772                 if (valid_reserved(dev, slave, qpn)) {
1773                         err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1774                         if (err)
1775                                 return err;
1776                 }
1777
1778                 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1779                                            NULL, 1);
1780                 if (err)
1781                         return err;
1782
1783                 if (!fw_reserved(dev, qpn)) {
1784                         err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL);
1785                         if (err) {
1786                                 res_abort_move(dev, slave, RES_QP, qpn);
1787                                 return err;
1788                         }
1789                 }
1790
1791                 res_end_move(dev, slave, RES_QP, qpn);
1792                 break;
1793
1794         default:
1795                 err = -EINVAL;
1796                 break;
1797         }
1798         return err;
1799 }
1800
1801 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1802                          u64 in_param, u64 *out_param)
1803 {
1804         int err = -EINVAL;
1805         int base;
1806         int order;
1807
1808         if (op != RES_OP_RESERVE_AND_MAP)
1809                 return err;
1810
1811         order = get_param_l(&in_param);
1812
1813         err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1814         if (err)
1815                 return err;
1816
1817         base = __mlx4_alloc_mtt_range(dev, order);
1818         if (base == -1) {
1819                 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1820                 return -ENOMEM;
1821         }
1822
1823         err = add_res_range(dev, slave, base, 1, RES_MTT, order);
1824         if (err) {
1825                 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1826                 __mlx4_free_mtt_range(dev, base, order);
1827         } else {
1828                 set_param_l(out_param, base);
1829         }
1830
1831         return err;
1832 }
1833
1834 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1835                          u64 in_param, u64 *out_param)
1836 {
1837         int err = -EINVAL;
1838         int index;
1839         int id;
1840         struct res_mpt *mpt;
1841
1842         switch (op) {
1843         case RES_OP_RESERVE:
1844                 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1845                 if (err)
1846                         break;
1847
1848                 index = __mlx4_mpt_reserve(dev);
1849                 if (index == -1) {
1850                         mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1851                         break;
1852                 }
1853                 id = index & mpt_mask(dev);
1854
1855                 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1856                 if (err) {
1857                         mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1858                         __mlx4_mpt_release(dev, index);
1859                         break;
1860                 }
1861                 set_param_l(out_param, index);
1862                 break;
1863         case RES_OP_MAP_ICM:
1864                 index = get_param_l(&in_param);
1865                 id = index & mpt_mask(dev);
1866                 err = mr_res_start_move_to(dev, slave, id,
1867                                            RES_MPT_MAPPED, &mpt);
1868                 if (err)
1869                         return err;
1870
1871                 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL);
1872                 if (err) {
1873                         res_abort_move(dev, slave, RES_MPT, id);
1874                         return err;
1875                 }
1876
1877                 res_end_move(dev, slave, RES_MPT, id);
1878                 break;
1879         }
1880         return err;
1881 }
1882
1883 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1884                         u64 in_param, u64 *out_param)
1885 {
1886         int cqn;
1887         int err;
1888
1889         switch (op) {
1890         case RES_OP_RESERVE_AND_MAP:
1891                 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
1892                 if (err)
1893                         break;
1894
1895                 err = __mlx4_cq_alloc_icm(dev, &cqn);
1896                 if (err) {
1897                         mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1898                         break;
1899                 }
1900
1901                 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1902                 if (err) {
1903                         mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1904                         __mlx4_cq_free_icm(dev, cqn);
1905                         break;
1906                 }
1907
1908                 set_param_l(out_param, cqn);
1909                 break;
1910
1911         default:
1912                 err = -EINVAL;
1913         }
1914
1915         return err;
1916 }
1917
1918 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1919                          u64 in_param, u64 *out_param)
1920 {
1921         int srqn;
1922         int err;
1923
1924         switch (op) {
1925         case RES_OP_RESERVE_AND_MAP:
1926                 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
1927                 if (err)
1928                         break;
1929
1930                 err = __mlx4_srq_alloc_icm(dev, &srqn);
1931                 if (err) {
1932                         mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1933                         break;
1934                 }
1935
1936                 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1937                 if (err) {
1938                         mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1939                         __mlx4_srq_free_icm(dev, srqn);
1940                         break;
1941                 }
1942
1943                 set_param_l(out_param, srqn);
1944                 break;
1945
1946         default:
1947                 err = -EINVAL;
1948         }
1949
1950         return err;
1951 }
1952
1953 static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1954                                      u8 smac_index, u64 *mac)
1955 {
1956         struct mlx4_priv *priv = mlx4_priv(dev);
1957         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1958         struct list_head *mac_list =
1959                 &tracker->slave_list[slave].res_list[RES_MAC];
1960         struct mac_res *res, *tmp;
1961
1962         list_for_each_entry_safe(res, tmp, mac_list, list) {
1963                 if (res->smac_index == smac_index && res->port == (u8) port) {
1964                         *mac = res->mac;
1965                         return 0;
1966                 }
1967         }
1968         return -ENOENT;
1969 }
1970
1971 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
1972 {
1973         struct mlx4_priv *priv = mlx4_priv(dev);
1974         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1975         struct list_head *mac_list =
1976                 &tracker->slave_list[slave].res_list[RES_MAC];
1977         struct mac_res *res, *tmp;
1978
1979         list_for_each_entry_safe(res, tmp, mac_list, list) {
1980                 if (res->mac == mac && res->port == (u8) port) {
1981                         /* mac found. update ref count */
1982                         ++res->ref_count;
1983                         return 0;
1984                 }
1985         }
1986
1987         if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1988                 return -EINVAL;
1989         res = kzalloc(sizeof *res, GFP_KERNEL);
1990         if (!res) {
1991                 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1992                 return -ENOMEM;
1993         }
1994         res->mac = mac;
1995         res->port = (u8) port;
1996         res->smac_index = smac_index;
1997         res->ref_count = 1;
1998         list_add_tail(&res->list,
1999                       &tracker->slave_list[slave].res_list[RES_MAC]);
2000         return 0;
2001 }
2002
2003 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
2004                                int port)
2005 {
2006         struct mlx4_priv *priv = mlx4_priv(dev);
2007         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2008         struct list_head *mac_list =
2009                 &tracker->slave_list[slave].res_list[RES_MAC];
2010         struct mac_res *res, *tmp;
2011
2012         list_for_each_entry_safe(res, tmp, mac_list, list) {
2013                 if (res->mac == mac && res->port == (u8) port) {
2014                         if (!--res->ref_count) {
2015                                 list_del(&res->list);
2016                                 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
2017                                 kfree(res);
2018                         }
2019                         break;
2020                 }
2021         }
2022 }
2023
2024 static void rem_slave_macs(struct mlx4_dev *dev, int slave)
2025 {
2026         struct mlx4_priv *priv = mlx4_priv(dev);
2027         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2028         struct list_head *mac_list =
2029                 &tracker->slave_list[slave].res_list[RES_MAC];
2030         struct mac_res *res, *tmp;
2031         int i;
2032
2033         list_for_each_entry_safe(res, tmp, mac_list, list) {
2034                 list_del(&res->list);
2035                 /* dereference the mac the num times the slave referenced it */
2036                 for (i = 0; i < res->ref_count; i++)
2037                         __mlx4_unregister_mac(dev, res->port, res->mac);
2038                 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
2039                 kfree(res);
2040         }
2041 }
2042
2043 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2044                          u64 in_param, u64 *out_param, int in_port)
2045 {
2046         int err = -EINVAL;
2047         int port;
2048         u64 mac;
2049         u8 smac_index;
2050
2051         if (op != RES_OP_RESERVE_AND_MAP)
2052                 return err;
2053
2054         port = !in_port ? get_param_l(out_param) : in_port;
2055         port = mlx4_slave_convert_port(
2056                         dev, slave, port);
2057
2058         if (port < 0)
2059                 return -EINVAL;
2060         mac = in_param;
2061
2062         err = __mlx4_register_mac(dev, port, mac);
2063         if (err >= 0) {
2064                 smac_index = err;
2065                 set_param_l(out_param, err);
2066                 err = 0;
2067         }
2068
2069         if (!err) {
2070                 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
2071                 if (err)
2072                         __mlx4_unregister_mac(dev, port, mac);
2073         }
2074         return err;
2075 }
2076
2077 static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2078                              int port, int vlan_index)
2079 {
2080         struct mlx4_priv *priv = mlx4_priv(dev);
2081         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2082         struct list_head *vlan_list =
2083                 &tracker->slave_list[slave].res_list[RES_VLAN];
2084         struct vlan_res *res, *tmp;
2085
2086         list_for_each_entry_safe(res, tmp, vlan_list, list) {
2087                 if (res->vlan == vlan && res->port == (u8) port) {
2088                         /* vlan found. update ref count */
2089                         ++res->ref_count;
2090                         return 0;
2091                 }
2092         }
2093
2094         if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
2095                 return -EINVAL;
2096         res = kzalloc(sizeof(*res), GFP_KERNEL);
2097         if (!res) {
2098                 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
2099                 return -ENOMEM;
2100         }
2101         res->vlan = vlan;
2102         res->port = (u8) port;
2103         res->vlan_index = vlan_index;
2104         res->ref_count = 1;
2105         list_add_tail(&res->list,
2106                       &tracker->slave_list[slave].res_list[RES_VLAN]);
2107         return 0;
2108 }
2109
2110
2111 static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2112                                 int port)
2113 {
2114         struct mlx4_priv *priv = mlx4_priv(dev);
2115         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2116         struct list_head *vlan_list =
2117                 &tracker->slave_list[slave].res_list[RES_VLAN];
2118         struct vlan_res *res, *tmp;
2119
2120         list_for_each_entry_safe(res, tmp, vlan_list, list) {
2121                 if (res->vlan == vlan && res->port == (u8) port) {
2122                         if (!--res->ref_count) {
2123                                 list_del(&res->list);
2124                                 mlx4_release_resource(dev, slave, RES_VLAN,
2125                                                       1, port);
2126                                 kfree(res);
2127                         }
2128                         break;
2129                 }
2130         }
2131 }
2132
2133 static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
2134 {
2135         struct mlx4_priv *priv = mlx4_priv(dev);
2136         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2137         struct list_head *vlan_list =
2138                 &tracker->slave_list[slave].res_list[RES_VLAN];
2139         struct vlan_res *res, *tmp;
2140         int i;
2141
2142         list_for_each_entry_safe(res, tmp, vlan_list, list) {
2143                 list_del(&res->list);
2144                 /* dereference the vlan the num times the slave referenced it */
2145                 for (i = 0; i < res->ref_count; i++)
2146                         __mlx4_unregister_vlan(dev, res->port, res->vlan);
2147                 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
2148                 kfree(res);
2149         }
2150 }
2151
2152 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2153                           u64 in_param, u64 *out_param, int in_port)
2154 {
2155         struct mlx4_priv *priv = mlx4_priv(dev);
2156         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2157         int err;
2158         u16 vlan;
2159         int vlan_index;
2160         int port;
2161
2162         port = !in_port ? get_param_l(out_param) : in_port;
2163
2164         if (!port || op != RES_OP_RESERVE_AND_MAP)
2165                 return -EINVAL;
2166
2167         port = mlx4_slave_convert_port(
2168                         dev, slave, port);
2169
2170         if (port < 0)
2171                 return -EINVAL;
2172         /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
2173         if (!in_port && port > 0 && port <= dev->caps.num_ports) {
2174                 slave_state[slave].old_vlan_api = true;
2175                 return 0;
2176         }
2177
2178         vlan = (u16) in_param;
2179
2180         err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
2181         if (!err) {
2182                 set_param_l(out_param, (u32) vlan_index);
2183                 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
2184                 if (err)
2185                         __mlx4_unregister_vlan(dev, port, vlan);
2186         }
2187         return err;
2188 }
2189
2190 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2191                              u64 in_param, u64 *out_param, int port)
2192 {
2193         u32 index;
2194         int err;
2195
2196         if (op != RES_OP_RESERVE)
2197                 return -EINVAL;
2198
2199         err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
2200         if (err)
2201                 return err;
2202
2203         err = __mlx4_counter_alloc(dev, &index);
2204         if (err) {
2205                 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2206                 return err;
2207         }
2208
2209         err = add_res_range(dev, slave, index, 1, RES_COUNTER, port);
2210         if (err) {
2211                 __mlx4_counter_free(dev, index);
2212                 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2213         } else {
2214                 set_param_l(out_param, index);
2215         }
2216
2217         return err;
2218 }
2219
2220 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2221                            u64 in_param, u64 *out_param)
2222 {
2223         u32 xrcdn;
2224         int err;
2225
2226         if (op != RES_OP_RESERVE)
2227                 return -EINVAL;
2228
2229         err = __mlx4_xrcd_alloc(dev, &xrcdn);
2230         if (err)
2231                 return err;
2232
2233         err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2234         if (err)
2235                 __mlx4_xrcd_free(dev, xrcdn);
2236         else
2237                 set_param_l(out_param, xrcdn);
2238
2239         return err;
2240 }
2241
2242 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2243                            struct mlx4_vhcr *vhcr,
2244                            struct mlx4_cmd_mailbox *inbox,
2245                            struct mlx4_cmd_mailbox *outbox,
2246                            struct mlx4_cmd_info *cmd)
2247 {
2248         int err;
2249         int alop = vhcr->op_modifier;
2250
2251         switch (vhcr->in_modifier & 0xFF) {
2252         case RES_QP:
2253                 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2254                                    vhcr->in_param, &vhcr->out_param);
2255                 break;
2256
2257         case RES_MTT:
2258                 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2259                                     vhcr->in_param, &vhcr->out_param);
2260                 break;
2261
2262         case RES_MPT:
2263                 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2264                                     vhcr->in_param, &vhcr->out_param);
2265                 break;
2266
2267         case RES_CQ:
2268                 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2269                                    vhcr->in_param, &vhcr->out_param);
2270                 break;
2271
2272         case RES_SRQ:
2273                 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2274                                     vhcr->in_param, &vhcr->out_param);
2275                 break;
2276
2277         case RES_MAC:
2278                 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
2279                                     vhcr->in_param, &vhcr->out_param,
2280                                     (vhcr->in_modifier >> 8) & 0xFF);
2281                 break;
2282
2283         case RES_VLAN:
2284                 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
2285                                      vhcr->in_param, &vhcr->out_param,
2286                                      (vhcr->in_modifier >> 8) & 0xFF);
2287                 break;
2288
2289         case RES_COUNTER:
2290                 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2291                                         vhcr->in_param, &vhcr->out_param, 0);
2292                 break;
2293
2294         case RES_XRCD:
2295                 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2296                                       vhcr->in_param, &vhcr->out_param);
2297                 break;
2298
2299         default:
2300                 err = -EINVAL;
2301                 break;
2302         }
2303
2304         return err;
2305 }
2306
2307 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2308                        u64 in_param)
2309 {
2310         int err;
2311         int count;
2312         int base;
2313         int qpn;
2314
2315         switch (op) {
2316         case RES_OP_RESERVE:
2317                 base = get_param_l(&in_param) & 0x7fffff;
2318                 count = get_param_h(&in_param);
2319                 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2320                 if (err)
2321                         break;
2322                 mlx4_release_resource(dev, slave, RES_QP, count, 0);
2323                 __mlx4_qp_release_range(dev, base, count);
2324                 break;
2325         case RES_OP_MAP_ICM:
2326                 qpn = get_param_l(&in_param) & 0x7fffff;
2327                 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2328                                            NULL, 0);
2329                 if (err)
2330                         return err;
2331
2332                 if (!fw_reserved(dev, qpn))
2333                         __mlx4_qp_free_icm(dev, qpn);
2334
2335                 res_end_move(dev, slave, RES_QP, qpn);
2336
2337                 if (valid_reserved(dev, slave, qpn))
2338                         err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2339                 break;
2340         default:
2341                 err = -EINVAL;
2342                 break;
2343         }
2344         return err;
2345 }
2346
2347 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2348                         u64 in_param, u64 *out_param)
2349 {
2350         int err = -EINVAL;
2351         int base;
2352         int order;
2353
2354         if (op != RES_OP_RESERVE_AND_MAP)
2355                 return err;
2356
2357         base = get_param_l(&in_param);
2358         order = get_param_h(&in_param);
2359         err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
2360         if (!err) {
2361                 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
2362                 __mlx4_free_mtt_range(dev, base, order);
2363         }
2364         return err;
2365 }
2366
2367 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2368                         u64 in_param)
2369 {
2370         int err = -EINVAL;
2371         int index;
2372         int id;
2373         struct res_mpt *mpt;
2374
2375         switch (op) {
2376         case RES_OP_RESERVE:
2377                 index = get_param_l(&in_param);
2378                 id = index & mpt_mask(dev);
2379                 err = get_res(dev, slave, id, RES_MPT, &mpt);
2380                 if (err)
2381                         break;
2382                 index = mpt->key;
2383                 put_res(dev, slave, id, RES_MPT);
2384
2385                 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2386                 if (err)
2387                         break;
2388                 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
2389                 __mlx4_mpt_release(dev, index);
2390                 break;
2391         case RES_OP_MAP_ICM:
2392                 index = get_param_l(&in_param);
2393                 id = index & mpt_mask(dev);
2394                 err = mr_res_start_move_to(dev, slave, id,
2395                                            RES_MPT_RESERVED, &mpt);
2396                 if (err)
2397                         return err;
2398
2399                 __mlx4_mpt_free_icm(dev, mpt->key);
2400                 res_end_move(dev, slave, RES_MPT, id);
2401                 break;
2402         default:
2403                 err = -EINVAL;
2404                 break;
2405         }
2406         return err;
2407 }
2408
2409 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2410                        u64 in_param, u64 *out_param)
2411 {
2412         int cqn;
2413         int err;
2414
2415         switch (op) {
2416         case RES_OP_RESERVE_AND_MAP:
2417                 cqn = get_param_l(&in_param);
2418                 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2419                 if (err)
2420                         break;
2421
2422                 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
2423                 __mlx4_cq_free_icm(dev, cqn);
2424                 break;
2425
2426         default:
2427                 err = -EINVAL;
2428                 break;
2429         }
2430
2431         return err;
2432 }
2433
2434 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2435                         u64 in_param, u64 *out_param)
2436 {
2437         int srqn;
2438         int err;
2439
2440         switch (op) {
2441         case RES_OP_RESERVE_AND_MAP:
2442                 srqn = get_param_l(&in_param);
2443                 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2444                 if (err)
2445                         break;
2446
2447                 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
2448                 __mlx4_srq_free_icm(dev, srqn);
2449                 break;
2450
2451         default:
2452                 err = -EINVAL;
2453                 break;
2454         }
2455
2456         return err;
2457 }
2458
2459 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2460                             u64 in_param, u64 *out_param, int in_port)
2461 {
2462         int port;
2463         int err = 0;
2464
2465         switch (op) {
2466         case RES_OP_RESERVE_AND_MAP:
2467                 port = !in_port ? get_param_l(out_param) : in_port;
2468                 port = mlx4_slave_convert_port(
2469                                 dev, slave, port);
2470
2471                 if (port < 0)
2472                         return -EINVAL;
2473                 mac_del_from_slave(dev, slave, in_param, port);
2474                 __mlx4_unregister_mac(dev, port, in_param);
2475                 break;
2476         default:
2477                 err = -EINVAL;
2478                 break;
2479         }
2480
2481         return err;
2482
2483 }
2484
2485 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2486                             u64 in_param, u64 *out_param, int port)
2487 {
2488         struct mlx4_priv *priv = mlx4_priv(dev);
2489         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2490         int err = 0;
2491
2492         port = mlx4_slave_convert_port(
2493                         dev, slave, port);
2494
2495         if (port < 0)
2496                 return -EINVAL;
2497         switch (op) {
2498         case RES_OP_RESERVE_AND_MAP:
2499                 if (slave_state[slave].old_vlan_api)
2500                         return 0;
2501                 if (!port)
2502                         return -EINVAL;
2503                 vlan_del_from_slave(dev, slave, in_param, port);
2504                 __mlx4_unregister_vlan(dev, port, in_param);
2505                 break;
2506         default:
2507                 err = -EINVAL;
2508                 break;
2509         }
2510
2511         return err;
2512 }
2513
2514 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2515                             u64 in_param, u64 *out_param)
2516 {
2517         int index;
2518         int err;
2519
2520         if (op != RES_OP_RESERVE)
2521                 return -EINVAL;
2522
2523         index = get_param_l(&in_param);
2524         if (index == MLX4_SINK_COUNTER_INDEX(dev))
2525                 return 0;
2526
2527         err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2528         if (err)
2529                 return err;
2530
2531         __mlx4_counter_free(dev, index);
2532         mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2533
2534         return err;
2535 }
2536
2537 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2538                           u64 in_param, u64 *out_param)
2539 {
2540         int xrcdn;
2541         int err;
2542
2543         if (op != RES_OP_RESERVE)
2544                 return -EINVAL;
2545
2546         xrcdn = get_param_l(&in_param);
2547         err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2548         if (err)
2549                 return err;
2550
2551         __mlx4_xrcd_free(dev, xrcdn);
2552
2553         return err;
2554 }
2555
2556 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2557                           struct mlx4_vhcr *vhcr,
2558                           struct mlx4_cmd_mailbox *inbox,
2559                           struct mlx4_cmd_mailbox *outbox,
2560                           struct mlx4_cmd_info *cmd)
2561 {
2562         int err = -EINVAL;
2563         int alop = vhcr->op_modifier;
2564
2565         switch (vhcr->in_modifier & 0xFF) {
2566         case RES_QP:
2567                 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2568                                   vhcr->in_param);
2569                 break;
2570
2571         case RES_MTT:
2572                 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2573                                    vhcr->in_param, &vhcr->out_param);
2574                 break;
2575
2576         case RES_MPT:
2577                 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2578                                    vhcr->in_param);
2579                 break;
2580
2581         case RES_CQ:
2582                 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2583                                   vhcr->in_param, &vhcr->out_param);
2584                 break;
2585
2586         case RES_SRQ:
2587                 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2588                                    vhcr->in_param, &vhcr->out_param);
2589                 break;
2590
2591         case RES_MAC:
2592                 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
2593                                    vhcr->in_param, &vhcr->out_param,
2594                                    (vhcr->in_modifier >> 8) & 0xFF);
2595                 break;
2596
2597         case RES_VLAN:
2598                 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
2599                                     vhcr->in_param, &vhcr->out_param,
2600                                     (vhcr->in_modifier >> 8) & 0xFF);
2601                 break;
2602
2603         case RES_COUNTER:
2604                 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2605                                        vhcr->in_param, &vhcr->out_param);
2606                 break;
2607
2608         case RES_XRCD:
2609                 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2610                                      vhcr->in_param, &vhcr->out_param);
2611
2612         default:
2613                 break;
2614         }
2615         return err;
2616 }
2617
2618 /* ugly but other choices are uglier */
2619 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2620 {
2621         return (be32_to_cpu(mpt->flags) >> 9) & 1;
2622 }
2623
2624 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
2625 {
2626         return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
2627 }
2628
2629 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2630 {
2631         return be32_to_cpu(mpt->mtt_sz);
2632 }
2633
2634 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2635 {
2636         return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2637 }
2638
2639 static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2640 {
2641         return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2642 }
2643
2644 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2645 {
2646         return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2647 }
2648
2649 static int mr_is_region(struct mlx4_mpt_entry *mpt)
2650 {
2651         return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2652 }
2653
2654 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
2655 {
2656         return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2657 }
2658
2659 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
2660 {
2661         return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2662 }
2663
2664 static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2665 {
2666         int page_shift = (qpc->log_page_size & 0x3f) + 12;
2667         int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2668         int log_sq_sride = qpc->sq_size_stride & 7;
2669         int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2670         int log_rq_stride = qpc->rq_size_stride & 7;
2671         int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2672         int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
2673         u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2674         int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
2675         int sq_size;
2676         int rq_size;
2677         int total_pages;
2678         int total_mem;
2679         int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2680
2681         sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2682         rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2683         total_mem = sq_size + rq_size;
2684         total_pages =
2685                 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2686                                    page_shift);
2687
2688         return total_pages;
2689 }
2690
2691 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2692                            int size, struct res_mtt *mtt)
2693 {
2694         int res_start = mtt->com.res_id;
2695         int res_size = (1 << mtt->order);
2696
2697         if (start < res_start || start + size > res_start + res_size)
2698                 return -EPERM;
2699         return 0;
2700 }
2701
2702 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2703                            struct mlx4_vhcr *vhcr,
2704                            struct mlx4_cmd_mailbox *inbox,
2705                            struct mlx4_cmd_mailbox *outbox,
2706                            struct mlx4_cmd_info *cmd)
2707 {
2708         int err;
2709         int index = vhcr->in_modifier;
2710         struct res_mtt *mtt;
2711         struct res_mpt *mpt;
2712         int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
2713         int phys;
2714         int id;
2715         u32 pd;
2716         int pd_slave;
2717
2718         id = index & mpt_mask(dev);
2719         err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2720         if (err)
2721                 return err;
2722
2723         /* Disable memory windows for VFs. */
2724         if (!mr_is_region(inbox->buf)) {
2725                 err = -EPERM;
2726                 goto ex_abort;
2727         }
2728
2729         /* Make sure that the PD bits related to the slave id are zeros. */
2730         pd = mr_get_pd(inbox->buf);
2731         pd_slave = (pd >> 17) & 0x7f;
2732         if (pd_slave != 0 && --pd_slave != slave) {
2733                 err = -EPERM;
2734                 goto ex_abort;
2735         }
2736
2737         if (mr_is_fmr(inbox->buf)) {
2738                 /* FMR and Bind Enable are forbidden in slave devices. */
2739                 if (mr_is_bind_enabled(inbox->buf)) {
2740                         err = -EPERM;
2741                         goto ex_abort;
2742                 }
2743                 /* FMR and Memory Windows are also forbidden. */
2744                 if (!mr_is_region(inbox->buf)) {
2745                         err = -EPERM;
2746                         goto ex_abort;
2747                 }
2748         }
2749
2750         phys = mr_phys_mpt(inbox->buf);
2751         if (!phys) {
2752                 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2753                 if (err)
2754                         goto ex_abort;
2755
2756                 err = check_mtt_range(dev, slave, mtt_base,
2757                                       mr_get_mtt_size(inbox->buf), mtt);
2758                 if (err)
2759                         goto ex_put;
2760
2761                 mpt->mtt = mtt;
2762         }
2763
2764         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2765         if (err)
2766                 goto ex_put;
2767
2768         if (!phys) {
2769                 atomic_inc(&mtt->ref_count);
2770                 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2771         }
2772
2773         res_end_move(dev, slave, RES_MPT, id);
2774         return 0;
2775
2776 ex_put:
2777         if (!phys)
2778                 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2779 ex_abort:
2780         res_abort_move(dev, slave, RES_MPT, id);
2781
2782         return err;
2783 }
2784
2785 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2786                            struct mlx4_vhcr *vhcr,
2787                            struct mlx4_cmd_mailbox *inbox,
2788                            struct mlx4_cmd_mailbox *outbox,
2789                            struct mlx4_cmd_info *cmd)
2790 {
2791         int err;
2792         int index = vhcr->in_modifier;
2793         struct res_mpt *mpt;
2794         int id;
2795
2796         id = index & mpt_mask(dev);
2797         err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2798         if (err)
2799                 return err;
2800
2801         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2802         if (err)
2803                 goto ex_abort;
2804
2805         if (mpt->mtt)
2806                 atomic_dec(&mpt->mtt->ref_count);
2807
2808         res_end_move(dev, slave, RES_MPT, id);
2809         return 0;
2810
2811 ex_abort:
2812         res_abort_move(dev, slave, RES_MPT, id);
2813
2814         return err;
2815 }
2816
2817 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2818                            struct mlx4_vhcr *vhcr,
2819                            struct mlx4_cmd_mailbox *inbox,
2820                            struct mlx4_cmd_mailbox *outbox,
2821                            struct mlx4_cmd_info *cmd)
2822 {
2823         int err;
2824         int index = vhcr->in_modifier;
2825         struct res_mpt *mpt;
2826         int id;
2827
2828         id = index & mpt_mask(dev);
2829         err = get_res(dev, slave, id, RES_MPT, &mpt);
2830         if (err)
2831                 return err;
2832
2833         if (mpt->com.from_state == RES_MPT_MAPPED) {
2834                 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2835                  * that, the VF must read the MPT. But since the MPT entry memory is not
2836                  * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2837                  * entry contents. To guarantee that the MPT cannot be changed, the driver
2838                  * must perform HW2SW_MPT before this query and return the MPT entry to HW
2839                  * ownership fofollowing the change. The change here allows the VF to
2840                  * perform QUERY_MPT also when the entry is in SW ownership.
2841                  */
2842                 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2843                                         &mlx4_priv(dev)->mr_table.dmpt_table,
2844                                         mpt->key, NULL);
2845
2846                 if (NULL == mpt_entry || NULL == outbox->buf) {
2847                         err = -EINVAL;
2848                         goto out;
2849                 }
2850
2851                 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2852
2853                 err = 0;
2854         } else if (mpt->com.from_state == RES_MPT_HW) {
2855                 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2856         } else {
2857                 err = -EBUSY;
2858                 goto out;
2859         }
2860
2861
2862 out:
2863         put_res(dev, slave, id, RES_MPT);
2864         return err;
2865 }
2866
2867 static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2868 {
2869         return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2870 }
2871
2872 static int qp_get_scqn(struct mlx4_qp_context *qpc)
2873 {
2874         return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2875 }
2876
2877 static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2878 {
2879         return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2880 }
2881
2882 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2883                                   struct mlx4_qp_context *context)
2884 {
2885         u32 qpn = vhcr->in_modifier & 0xffffff;
2886         u32 qkey = 0;
2887
2888         if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2889                 return;
2890
2891         /* adjust qkey in qp context */
2892         context->qkey = cpu_to_be32(qkey);
2893 }
2894
2895 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
2896                                  struct mlx4_qp_context *qpc,
2897                                  struct mlx4_cmd_mailbox *inbox);
2898
2899 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2900                              struct mlx4_vhcr *vhcr,
2901                              struct mlx4_cmd_mailbox *inbox,
2902                              struct mlx4_cmd_mailbox *outbox,
2903                              struct mlx4_cmd_info *cmd)
2904 {
2905         int err;
2906         int qpn = vhcr->in_modifier & 0x7fffff;
2907         struct res_mtt *mtt;
2908         struct res_qp *qp;
2909         struct mlx4_qp_context *qpc = inbox->buf + 8;
2910         int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
2911         int mtt_size = qp_get_mtt_size(qpc);
2912         struct res_cq *rcq;
2913         struct res_cq *scq;
2914         int rcqn = qp_get_rcqn(qpc);
2915         int scqn = qp_get_scqn(qpc);
2916         u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2917         int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2918         struct res_srq *srq;
2919         int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2920
2921         err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
2922         if (err)
2923                 return err;
2924
2925         err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2926         if (err)
2927                 return err;
2928         qp->local_qpn = local_qpn;
2929         qp->sched_queue = 0;
2930         qp->param3 = 0;
2931         qp->vlan_control = 0;
2932         qp->fvl_rx = 0;
2933         qp->pri_path_fl = 0;
2934         qp->vlan_index = 0;
2935         qp->feup = 0;
2936         qp->qpc_flags = be32_to_cpu(qpc->flags);
2937
2938         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2939         if (err)
2940                 goto ex_abort;
2941
2942         err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2943         if (err)
2944                 goto ex_put_mtt;
2945
2946         err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2947         if (err)
2948                 goto ex_put_mtt;
2949
2950         if (scqn != rcqn) {
2951                 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2952                 if (err)
2953                         goto ex_put_rcq;
2954         } else
2955                 scq = rcq;
2956
2957         if (use_srq) {
2958                 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2959                 if (err)
2960                         goto ex_put_scq;
2961         }
2962
2963         adjust_proxy_tun_qkey(dev, vhcr, qpc);
2964         update_pkey_index(dev, slave, inbox);
2965         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2966         if (err)
2967                 goto ex_put_srq;
2968         atomic_inc(&mtt->ref_count);
2969         qp->mtt = mtt;
2970         atomic_inc(&rcq->ref_count);
2971         qp->rcq = rcq;
2972         atomic_inc(&scq->ref_count);
2973         qp->scq = scq;
2974
2975         if (scqn != rcqn)
2976                 put_res(dev, slave, scqn, RES_CQ);
2977
2978         if (use_srq) {
2979                 atomic_inc(&srq->ref_count);
2980                 put_res(dev, slave, srqn, RES_SRQ);
2981                 qp->srq = srq;
2982         }
2983
2984         /* Save param3 for dynamic changes from VST back to VGT */
2985         qp->param3 = qpc->param3;
2986         put_res(dev, slave, rcqn, RES_CQ);
2987         put_res(dev, slave, mtt_base, RES_MTT);
2988         res_end_move(dev, slave, RES_QP, qpn);
2989
2990         return 0;
2991
2992 ex_put_srq:
2993         if (use_srq)
2994                 put_res(dev, slave, srqn, RES_SRQ);
2995 ex_put_scq:
2996         if (scqn != rcqn)
2997                 put_res(dev, slave, scqn, RES_CQ);
2998 ex_put_rcq:
2999         put_res(dev, slave, rcqn, RES_CQ);
3000 ex_put_mtt:
3001         put_res(dev, slave, mtt_base, RES_MTT);
3002 ex_abort:
3003         res_abort_move(dev, slave, RES_QP, qpn);
3004
3005         return err;
3006 }
3007
3008 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
3009 {
3010         return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
3011 }
3012
3013 static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
3014 {
3015         int log_eq_size = eqc->log_eq_size & 0x1f;
3016         int page_shift = (eqc->log_page_size & 0x3f) + 12;
3017
3018         if (log_eq_size + 5 < page_shift)
3019                 return 1;
3020
3021         return 1 << (log_eq_size + 5 - page_shift);
3022 }
3023
3024 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
3025 {
3026         return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
3027 }
3028
3029 static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
3030 {
3031         int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
3032         int page_shift = (cqc->log_page_size & 0x3f) + 12;
3033
3034         if (log_cq_size + 5 < page_shift)
3035                 return 1;
3036
3037         return 1 << (log_cq_size + 5 - page_shift);
3038 }
3039
3040 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3041                           struct mlx4_vhcr *vhcr,
3042                           struct mlx4_cmd_mailbox *inbox,
3043                           struct mlx4_cmd_mailbox *outbox,
3044                           struct mlx4_cmd_info *cmd)
3045 {
3046         int err;
3047         int eqn = vhcr->in_modifier;
3048         int res_id = (slave << 10) | eqn;
3049         struct mlx4_eq_context *eqc = inbox->buf;
3050         int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
3051         int mtt_size = eq_get_mtt_size(eqc);
3052         struct res_eq *eq;
3053         struct res_mtt *mtt;
3054
3055         err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3056         if (err)
3057                 return err;
3058         err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
3059         if (err)
3060                 goto out_add;
3061
3062         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3063         if (err)
3064                 goto out_move;
3065
3066         err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
3067         if (err)
3068                 goto out_put;
3069
3070         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3071         if (err)
3072                 goto out_put;
3073
3074         atomic_inc(&mtt->ref_count);
3075         eq->mtt = mtt;
3076         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3077         res_end_move(dev, slave, RES_EQ, res_id);
3078         return 0;
3079
3080 out_put:
3081         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3082 out_move:
3083         res_abort_move(dev, slave, RES_EQ, res_id);
3084 out_add:
3085         rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3086         return err;
3087 }
3088
3089 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
3090                             struct mlx4_vhcr *vhcr,
3091                             struct mlx4_cmd_mailbox *inbox,
3092                             struct mlx4_cmd_mailbox *outbox,
3093                             struct mlx4_cmd_info *cmd)
3094 {
3095         int err;
3096         u8 get = vhcr->op_modifier;
3097
3098         if (get != 1)
3099                 return -EPERM;
3100
3101         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3102
3103         return err;
3104 }
3105
3106 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
3107                               int len, struct res_mtt **res)
3108 {
3109         struct mlx4_priv *priv = mlx4_priv(dev);
3110         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3111         struct res_mtt *mtt;
3112         int err = -EINVAL;
3113
3114         spin_lock_irq(mlx4_tlock(dev));
3115         list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
3116                             com.list) {
3117                 if (!check_mtt_range(dev, slave, start, len, mtt)) {
3118                         *res = mtt;
3119                         mtt->com.from_state = mtt->com.state;
3120                         mtt->com.state = RES_MTT_BUSY;
3121                         err = 0;
3122                         break;
3123                 }
3124         }
3125         spin_unlock_irq(mlx4_tlock(dev));
3126
3127         return err;
3128 }
3129
3130 static int verify_qp_parameters(struct mlx4_dev *dev,
3131                                 struct mlx4_vhcr *vhcr,
3132                                 struct mlx4_cmd_mailbox *inbox,
3133                                 enum qp_transition transition, u8 slave)
3134 {
3135         u32                     qp_type;
3136         u32                     qpn;
3137         struct mlx4_qp_context  *qp_ctx;
3138         enum mlx4_qp_optpar     optpar;
3139         int port;
3140         int num_gids;
3141
3142         qp_ctx  = inbox->buf + 8;
3143         qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
3144         optpar  = be32_to_cpu(*(__be32 *) inbox->buf);
3145
3146         if (slave != mlx4_master_func_num(dev)) {
3147                 qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
3148                 /* setting QP rate-limit is disallowed for VFs */
3149                 if (qp_ctx->rate_limit_params)
3150                         return -EPERM;
3151         }
3152
3153         switch (qp_type) {
3154         case MLX4_QP_ST_RC:
3155         case MLX4_QP_ST_XRC:
3156         case MLX4_QP_ST_UC:
3157                 switch (transition) {
3158                 case QP_TRANS_INIT2RTR:
3159                 case QP_TRANS_RTR2RTS:
3160                 case QP_TRANS_RTS2RTS:
3161                 case QP_TRANS_SQD2SQD:
3162                 case QP_TRANS_SQD2RTS:
3163                         if (slave != mlx4_master_func_num(dev)) {
3164                                 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
3165                                         port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3166                                         if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3167                                                 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3168                                         else
3169                                                 num_gids = 1;
3170                                         if (qp_ctx->pri_path.mgid_index >= num_gids)
3171                                                 return -EINVAL;
3172                                 }
3173                                 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3174                                         port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
3175                                         if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3176                                                 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3177                                         else
3178                                                 num_gids = 1;
3179                                         if (qp_ctx->alt_path.mgid_index >= num_gids)
3180                                                 return -EINVAL;
3181                                 }
3182                         }
3183                         break;
3184                 default:
3185                         break;
3186                 }
3187                 break;
3188
3189         case MLX4_QP_ST_MLX:
3190                 qpn = vhcr->in_modifier & 0x7fffff;
3191                 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3192                 if (transition == QP_TRANS_INIT2RTR &&
3193                     slave != mlx4_master_func_num(dev) &&
3194                     mlx4_is_qp_reserved(dev, qpn) &&
3195                     !mlx4_vf_smi_enabled(dev, slave, port)) {
3196                         /* only enabled VFs may create MLX proxy QPs */
3197                         mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
3198                                  __func__, slave, port);
3199                         return -EPERM;
3200                 }
3201                 break;
3202
3203         default:
3204                 break;
3205         }
3206
3207         return 0;
3208 }
3209
3210 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
3211                            struct mlx4_vhcr *vhcr,
3212                            struct mlx4_cmd_mailbox *inbox,
3213                            struct mlx4_cmd_mailbox *outbox,
3214                            struct mlx4_cmd_info *cmd)
3215 {
3216         struct mlx4_mtt mtt;
3217         __be64 *page_list = inbox->buf;
3218         u64 *pg_list = (u64 *)page_list;
3219         int i;
3220         struct res_mtt *rmtt = NULL;
3221         int start = be64_to_cpu(page_list[0]);
3222         int npages = vhcr->in_modifier;
3223         int err;
3224
3225         err = get_containing_mtt(dev, slave, start, npages, &rmtt);
3226         if (err)
3227                 return err;
3228
3229         /* Call the SW implementation of write_mtt:
3230          * - Prepare a dummy mtt struct
3231          * - Translate inbox contents to simple addresses in host endianness */
3232         mtt.offset = 0;  /* TBD this is broken but I don't handle it since
3233                             we don't really use it */
3234         mtt.order = 0;
3235         mtt.page_shift = 0;
3236         for (i = 0; i < npages; ++i)
3237                 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
3238
3239         err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
3240                                ((u64 *)page_list + 2));
3241
3242         if (rmtt)
3243                 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
3244
3245         return err;
3246 }
3247
3248 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3249                           struct mlx4_vhcr *vhcr,
3250                           struct mlx4_cmd_mailbox *inbox,
3251                           struct mlx4_cmd_mailbox *outbox,
3252                           struct mlx4_cmd_info *cmd)
3253 {
3254         int eqn = vhcr->in_modifier;
3255         int res_id = eqn | (slave << 10);
3256         struct res_eq *eq;
3257         int err;
3258
3259         err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3260         if (err)
3261                 return err;
3262
3263         err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3264         if (err)
3265                 goto ex_abort;
3266
3267         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3268         if (err)
3269                 goto ex_put;
3270
3271         atomic_dec(&eq->mtt->ref_count);
3272         put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3273         res_end_move(dev, slave, RES_EQ, res_id);
3274         rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3275
3276         return 0;
3277
3278 ex_put:
3279         put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3280 ex_abort:
3281         res_abort_move(dev, slave, RES_EQ, res_id);
3282
3283         return err;
3284 }
3285
3286 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3287 {
3288         struct mlx4_priv *priv = mlx4_priv(dev);
3289         struct mlx4_slave_event_eq_info *event_eq;
3290         struct mlx4_cmd_mailbox *mailbox;
3291         u32 in_modifier = 0;
3292         int err;
3293         int res_id;
3294         struct res_eq *req;
3295
3296         if (!priv->mfunc.master.slave_state)
3297                 return -EINVAL;
3298
3299         /* check for slave valid, slave not PF, and slave active */
3300         if (slave < 0 || slave > dev->persist->num_vfs ||
3301             slave == dev->caps.function ||
3302             !priv->mfunc.master.slave_state[slave].active)
3303                 return 0;
3304
3305         event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
3306
3307         /* Create the event only if the slave is registered */
3308         if (event_eq->eqn < 0)
3309                 return 0;
3310
3311         mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3312         res_id = (slave << 10) | event_eq->eqn;
3313         err = get_res(dev, slave, res_id, RES_EQ, &req);
3314         if (err)
3315                 goto unlock;
3316
3317         if (req->com.from_state != RES_EQ_HW) {
3318                 err = -EINVAL;
3319                 goto put;
3320         }
3321
3322         mailbox = mlx4_alloc_cmd_mailbox(dev);
3323         if (IS_ERR(mailbox)) {
3324                 err = PTR_ERR(mailbox);
3325                 goto put;
3326         }
3327
3328         if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3329                 ++event_eq->token;
3330                 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3331         }
3332
3333         memcpy(mailbox->buf, (u8 *) eqe, 28);
3334
3335         in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16);
3336
3337         err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3338                        MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3339                        MLX4_CMD_NATIVE);
3340
3341         put_res(dev, slave, res_id, RES_EQ);
3342         mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3343         mlx4_free_cmd_mailbox(dev, mailbox);
3344         return err;
3345
3346 put:
3347         put_res(dev, slave, res_id, RES_EQ);
3348
3349 unlock:
3350         mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3351         return err;
3352 }
3353
3354 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3355                           struct mlx4_vhcr *vhcr,
3356                           struct mlx4_cmd_mailbox *inbox,
3357                           struct mlx4_cmd_mailbox *outbox,
3358                           struct mlx4_cmd_info *cmd)
3359 {
3360         int eqn = vhcr->in_modifier;
3361         int res_id = eqn | (slave << 10);
3362         struct res_eq *eq;
3363         int err;
3364
3365         err = get_res(dev, slave, res_id, RES_EQ, &eq);
3366         if (err)
3367                 return err;
3368
3369         if (eq->com.from_state != RES_EQ_HW) {
3370                 err = -EINVAL;
3371                 goto ex_put;
3372         }
3373
3374         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3375
3376 ex_put:
3377         put_res(dev, slave, res_id, RES_EQ);
3378         return err;
3379 }
3380
3381 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3382                           struct mlx4_vhcr *vhcr,
3383                           struct mlx4_cmd_mailbox *inbox,
3384                           struct mlx4_cmd_mailbox *outbox,
3385                           struct mlx4_cmd_info *cmd)
3386 {
3387         int err;
3388         int cqn = vhcr->in_modifier;
3389         struct mlx4_cq_context *cqc = inbox->buf;
3390         int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3391         struct res_cq *cq = NULL;
3392         struct res_mtt *mtt;
3393
3394         err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3395         if (err)
3396                 return err;
3397         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3398         if (err)
3399                 goto out_move;
3400         err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3401         if (err)
3402                 goto out_put;
3403         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3404         if (err)
3405                 goto out_put;
3406         atomic_inc(&mtt->ref_count);
3407         cq->mtt = mtt;
3408         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3409         res_end_move(dev, slave, RES_CQ, cqn);
3410         return 0;
3411
3412 out_put:
3413         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3414 out_move:
3415         res_abort_move(dev, slave, RES_CQ, cqn);
3416         return err;
3417 }
3418
3419 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3420                           struct mlx4_vhcr *vhcr,
3421                           struct mlx4_cmd_mailbox *inbox,
3422                           struct mlx4_cmd_mailbox *outbox,
3423                           struct mlx4_cmd_info *cmd)
3424 {
3425         int err;
3426         int cqn = vhcr->in_modifier;
3427         struct res_cq *cq = NULL;
3428
3429         err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3430         if (err)
3431                 return err;
3432         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3433         if (err)
3434                 goto out_move;
3435         atomic_dec(&cq->mtt->ref_count);
3436         res_end_move(dev, slave, RES_CQ, cqn);
3437         return 0;
3438
3439 out_move:
3440         res_abort_move(dev, slave, RES_CQ, cqn);
3441         return err;
3442 }
3443
3444 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3445                           struct mlx4_vhcr *vhcr,
3446                           struct mlx4_cmd_mailbox *inbox,
3447                           struct mlx4_cmd_mailbox *outbox,
3448                           struct mlx4_cmd_info *cmd)
3449 {
3450         int cqn = vhcr->in_modifier;
3451         struct res_cq *cq;
3452         int err;
3453
3454         err = get_res(dev, slave, cqn, RES_CQ, &cq);
3455         if (err)
3456                 return err;
3457
3458         if (cq->com.from_state != RES_CQ_HW)
3459                 goto ex_put;
3460
3461         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3462 ex_put:
3463         put_res(dev, slave, cqn, RES_CQ);
3464
3465         return err;
3466 }
3467
3468 static int handle_resize(struct mlx4_dev *dev, int slave,
3469                          struct mlx4_vhcr *vhcr,
3470                          struct mlx4_cmd_mailbox *inbox,
3471                          struct mlx4_cmd_mailbox *outbox,
3472                          struct mlx4_cmd_info *cmd,
3473                          struct res_cq *cq)
3474 {
3475         int err;
3476         struct res_mtt *orig_mtt;
3477         struct res_mtt *mtt;
3478         struct mlx4_cq_context *cqc = inbox->buf;
3479         int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3480
3481         err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3482         if (err)
3483                 return err;
3484
3485         if (orig_mtt != cq->mtt) {
3486                 err = -EINVAL;
3487                 goto ex_put;
3488         }
3489
3490         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3491         if (err)
3492                 goto ex_put;
3493
3494         err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3495         if (err)
3496                 goto ex_put1;
3497         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3498         if (err)
3499                 goto ex_put1;
3500         atomic_dec(&orig_mtt->ref_count);
3501         put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3502         atomic_inc(&mtt->ref_count);
3503         cq->mtt = mtt;
3504         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3505         return 0;
3506
3507 ex_put1:
3508         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3509 ex_put:
3510         put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3511
3512         return err;
3513
3514 }
3515
3516 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3517                            struct mlx4_vhcr *vhcr,
3518                            struct mlx4_cmd_mailbox *inbox,
3519                            struct mlx4_cmd_mailbox *outbox,
3520                            struct mlx4_cmd_info *cmd)
3521 {
3522         int cqn = vhcr->in_modifier;
3523         struct res_cq *cq;
3524         int err;
3525
3526         err = get_res(dev, slave, cqn, RES_CQ, &cq);
3527         if (err)
3528                 return err;
3529
3530         if (cq->com.from_state != RES_CQ_HW)
3531                 goto ex_put;
3532
3533         if (vhcr->op_modifier == 0) {
3534                 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
3535                 goto ex_put;
3536         }
3537
3538         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3539 ex_put:
3540         put_res(dev, slave, cqn, RES_CQ);
3541
3542         return err;
3543 }
3544
3545 static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3546 {
3547         int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3548         int log_rq_stride = srqc->logstride & 7;
3549         int page_shift = (srqc->log_page_size & 0x3f) + 12;
3550
3551         if (log_srq_size + log_rq_stride + 4 < page_shift)
3552                 return 1;
3553
3554         return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3555 }
3556
3557 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3558                            struct mlx4_vhcr *vhcr,
3559                            struct mlx4_cmd_mailbox *inbox,
3560                            struct mlx4_cmd_mailbox *outbox,
3561                            struct mlx4_cmd_info *cmd)
3562 {
3563         int err;
3564         int srqn = vhcr->in_modifier;
3565         struct res_mtt *mtt;
3566         struct res_srq *srq = NULL;
3567         struct mlx4_srq_context *srqc = inbox->buf;
3568         int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
3569
3570         if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3571                 return -EINVAL;
3572
3573         err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3574         if (err)
3575                 return err;
3576         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3577         if (err)
3578                 goto ex_abort;
3579         err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3580                               mtt);
3581         if (err)
3582                 goto ex_put_mtt;
3583
3584         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3585         if (err)
3586                 goto ex_put_mtt;
3587
3588         atomic_inc(&mtt->ref_count);
3589         srq->mtt = mtt;
3590         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3591         res_end_move(dev, slave, RES_SRQ, srqn);
3592         return 0;
3593
3594 ex_put_mtt:
3595         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3596 ex_abort:
3597         res_abort_move(dev, slave, RES_SRQ, srqn);
3598
3599         return err;
3600 }
3601
3602 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3603                            struct mlx4_vhcr *vhcr,
3604                            struct mlx4_cmd_mailbox *inbox,
3605                            struct mlx4_cmd_mailbox *outbox,
3606                            struct mlx4_cmd_info *cmd)
3607 {
3608         int err;
3609         int srqn = vhcr->in_modifier;
3610         struct res_srq *srq = NULL;
3611
3612         err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3613         if (err)
3614                 return err;
3615         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3616         if (err)
3617                 goto ex_abort;
3618         atomic_dec(&srq->mtt->ref_count);
3619         if (srq->cq)
3620                 atomic_dec(&srq->cq->ref_count);
3621         res_end_move(dev, slave, RES_SRQ, srqn);
3622
3623         return 0;
3624
3625 ex_abort:
3626         res_abort_move(dev, slave, RES_SRQ, srqn);
3627
3628         return err;
3629 }
3630
3631 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3632                            struct mlx4_vhcr *vhcr,
3633                            struct mlx4_cmd_mailbox *inbox,
3634                            struct mlx4_cmd_mailbox *outbox,
3635                            struct mlx4_cmd_info *cmd)
3636 {
3637         int err;
3638         int srqn = vhcr->in_modifier;
3639         struct res_srq *srq;
3640
3641         err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3642         if (err)
3643                 return err;
3644         if (srq->com.from_state != RES_SRQ_HW) {
3645                 err = -EBUSY;
3646                 goto out;
3647         }
3648         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3649 out:
3650         put_res(dev, slave, srqn, RES_SRQ);
3651         return err;
3652 }
3653
3654 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3655                          struct mlx4_vhcr *vhcr,
3656                          struct mlx4_cmd_mailbox *inbox,
3657                          struct mlx4_cmd_mailbox *outbox,
3658                          struct mlx4_cmd_info *cmd)
3659 {
3660         int err;
3661         int srqn = vhcr->in_modifier;
3662         struct res_srq *srq;
3663
3664         err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3665         if (err)
3666                 return err;
3667
3668         if (srq->com.from_state != RES_SRQ_HW) {
3669                 err = -EBUSY;
3670                 goto out;
3671         }
3672
3673         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3674 out:
3675         put_res(dev, slave, srqn, RES_SRQ);
3676         return err;
3677 }
3678
3679 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3680                         struct mlx4_vhcr *vhcr,
3681                         struct mlx4_cmd_mailbox *inbox,
3682                         struct mlx4_cmd_mailbox *outbox,
3683                         struct mlx4_cmd_info *cmd)
3684 {
3685         int err;
3686         int qpn = vhcr->in_modifier & 0x7fffff;
3687         struct res_qp *qp;
3688
3689         err = get_res(dev, slave, qpn, RES_QP, &qp);
3690         if (err)
3691                 return err;
3692         if (qp->com.from_state != RES_QP_HW) {
3693                 err = -EBUSY;
3694                 goto out;
3695         }
3696
3697         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3698 out:
3699         put_res(dev, slave, qpn, RES_QP);
3700         return err;
3701 }
3702
3703 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3704                               struct mlx4_vhcr *vhcr,
3705                               struct mlx4_cmd_mailbox *inbox,
3706                               struct mlx4_cmd_mailbox *outbox,
3707                               struct mlx4_cmd_info *cmd)
3708 {
3709         struct mlx4_qp_context *context = inbox->buf + 8;
3710         adjust_proxy_tun_qkey(dev, vhcr, context);
3711         update_pkey_index(dev, slave, inbox);
3712         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3713 }
3714
3715 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3716                                   struct mlx4_qp_context *qpc,
3717                                   struct mlx4_cmd_mailbox *inbox)
3718 {
3719         enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3720         u8 pri_sched_queue;
3721         int port = mlx4_slave_convert_port(
3722                    dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3723
3724         if (port < 0)
3725                 return -EINVAL;
3726
3727         pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3728                           ((port & 1) << 6);
3729
3730         if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) ||
3731             qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) {
3732                 qpc->pri_path.sched_queue = pri_sched_queue;
3733         }
3734
3735         if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3736                 port = mlx4_slave_convert_port(
3737                                 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3738                                 + 1) - 1;
3739                 if (port < 0)
3740                         return -EINVAL;
3741                 qpc->alt_path.sched_queue =
3742                         (qpc->alt_path.sched_queue & ~(1 << 6)) |
3743                         (port & 1) << 6;
3744         }
3745         return 0;
3746 }
3747
3748 static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3749                                 struct mlx4_qp_context *qpc,
3750                                 struct mlx4_cmd_mailbox *inbox)
3751 {
3752         u64 mac;
3753         int port;
3754         u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3755         u8 sched = *(u8 *)(inbox->buf + 64);
3756         u8 smac_ix;
3757
3758         port = (sched >> 6 & 1) + 1;
3759         if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3760                 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3761                 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3762                         return -ENOENT;
3763         }
3764         return 0;
3765 }
3766
3767 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3768                              struct mlx4_vhcr *vhcr,
3769                              struct mlx4_cmd_mailbox *inbox,
3770                              struct mlx4_cmd_mailbox *outbox,
3771                              struct mlx4_cmd_info *cmd)
3772 {
3773         int err;
3774         struct mlx4_qp_context *qpc = inbox->buf + 8;
3775         int qpn = vhcr->in_modifier & 0x7fffff;
3776         struct res_qp *qp;
3777         u8 orig_sched_queue;
3778         u8 orig_vlan_control = qpc->pri_path.vlan_control;
3779         u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3780         u8 orig_pri_path_fl = qpc->pri_path.fl;
3781         u8 orig_vlan_index = qpc->pri_path.vlan_index;
3782         u8 orig_feup = qpc->pri_path.feup;
3783
3784         err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3785         if (err)
3786                 return err;
3787         err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
3788         if (err)
3789                 return err;
3790
3791         if (roce_verify_mac(dev, slave, qpc, inbox))
3792                 return -EINVAL;
3793
3794         update_pkey_index(dev, slave, inbox);
3795         update_gid(dev, inbox, (u8)slave);
3796         adjust_proxy_tun_qkey(dev, vhcr, qpc);
3797         orig_sched_queue = qpc->pri_path.sched_queue;
3798
3799         err = get_res(dev, slave, qpn, RES_QP, &qp);
3800         if (err)
3801                 return err;
3802         if (qp->com.from_state != RES_QP_HW) {
3803                 err = -EBUSY;
3804                 goto out;
3805         }
3806
3807         err = update_vport_qp_param(dev, inbox, slave, qpn);
3808         if (err)
3809                 goto out;
3810
3811         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3812 out:
3813         /* if no error, save sched queue value passed in by VF. This is
3814          * essentially the QOS value provided by the VF. This will be useful
3815          * if we allow dynamic changes from VST back to VGT
3816          */
3817         if (!err) {
3818                 qp->sched_queue = orig_sched_queue;
3819                 qp->vlan_control = orig_vlan_control;
3820                 qp->fvl_rx      =  orig_fvl_rx;
3821                 qp->pri_path_fl = orig_pri_path_fl;
3822                 qp->vlan_index  = orig_vlan_index;
3823                 qp->feup        = orig_feup;
3824         }
3825         put_res(dev, slave, qpn, RES_QP);
3826         return err;
3827 }
3828
3829 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3830                             struct mlx4_vhcr *vhcr,
3831                             struct mlx4_cmd_mailbox *inbox,
3832                             struct mlx4_cmd_mailbox *outbox,
3833                             struct mlx4_cmd_info *cmd)
3834 {
3835         int err;
3836         struct mlx4_qp_context *context = inbox->buf + 8;
3837
3838         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3839         if (err)
3840                 return err;
3841         err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
3842         if (err)
3843                 return err;
3844
3845         update_pkey_index(dev, slave, inbox);
3846         update_gid(dev, inbox, (u8)slave);
3847         adjust_proxy_tun_qkey(dev, vhcr, context);
3848         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3849 }
3850
3851 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3852                             struct mlx4_vhcr *vhcr,
3853                             struct mlx4_cmd_mailbox *inbox,
3854                             struct mlx4_cmd_mailbox *outbox,
3855                             struct mlx4_cmd_info *cmd)
3856 {
3857         int err;
3858         struct mlx4_qp_context *context = inbox->buf + 8;
3859
3860         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3861         if (err)
3862                 return err;
3863         err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
3864         if (err)
3865                 return err;
3866
3867         update_pkey_index(dev, slave, inbox);
3868         update_gid(dev, inbox, (u8)slave);
3869         adjust_proxy_tun_qkey(dev, vhcr, context);
3870         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3871 }
3872
3873
3874 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3875                               struct mlx4_vhcr *vhcr,
3876                               struct mlx4_cmd_mailbox *inbox,
3877                               struct mlx4_cmd_mailbox *outbox,
3878                               struct mlx4_cmd_info *cmd)
3879 {
3880         struct mlx4_qp_context *context = inbox->buf + 8;
3881         int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3882         if (err)
3883                 return err;
3884         adjust_proxy_tun_qkey(dev, vhcr, context);
3885         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3886 }
3887
3888 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3889                             struct mlx4_vhcr *vhcr,
3890                             struct mlx4_cmd_mailbox *inbox,
3891                             struct mlx4_cmd_mailbox *outbox,
3892                             struct mlx4_cmd_info *cmd)
3893 {
3894         int err;
3895         struct mlx4_qp_context *context = inbox->buf + 8;
3896
3897         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3898         if (err)
3899                 return err;
3900         err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
3901         if (err)
3902                 return err;
3903
3904         adjust_proxy_tun_qkey(dev, vhcr, context);
3905         update_gid(dev, inbox, (u8)slave);
3906         update_pkey_index(dev, slave, inbox);
3907         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3908 }
3909
3910 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3911                             struct mlx4_vhcr *vhcr,
3912                             struct mlx4_cmd_mailbox *inbox,
3913                             struct mlx4_cmd_mailbox *outbox,
3914                             struct mlx4_cmd_info *cmd)
3915 {
3916         int err;
3917         struct mlx4_qp_context *context = inbox->buf + 8;
3918
3919         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3920         if (err)
3921                 return err;
3922         err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
3923         if (err)
3924                 return err;
3925
3926         adjust_proxy_tun_qkey(dev, vhcr, context);
3927         update_gid(dev, inbox, (u8)slave);
3928         update_pkey_index(dev, slave, inbox);
3929         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3930 }
3931
3932 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3933                          struct mlx4_vhcr *vhcr,
3934                          struct mlx4_cmd_mailbox *inbox,
3935                          struct mlx4_cmd_mailbox *outbox,
3936                          struct mlx4_cmd_info *cmd)
3937 {
3938         int err;
3939         int qpn = vhcr->in_modifier & 0x7fffff;
3940         struct res_qp *qp;
3941
3942         err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3943         if (err)
3944                 return err;
3945         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3946         if (err)
3947                 goto ex_abort;
3948
3949         atomic_dec(&qp->mtt->ref_count);
3950         atomic_dec(&qp->rcq->ref_count);
3951         atomic_dec(&qp->scq->ref_count);
3952         if (qp->srq)
3953                 atomic_dec(&qp->srq->ref_count);
3954         res_end_move(dev, slave, RES_QP, qpn);
3955         return 0;
3956
3957 ex_abort:
3958         res_abort_move(dev, slave, RES_QP, qpn);
3959
3960         return err;
3961 }
3962
3963 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3964                                 struct res_qp *rqp, u8 *gid)
3965 {
3966         struct res_gid *res;
3967
3968         list_for_each_entry(res, &rqp->mcg_list, list) {
3969                 if (!memcmp(res->gid, gid, 16))
3970                         return res;
3971         }
3972         return NULL;
3973 }
3974
3975 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3976                        u8 *gid, enum mlx4_protocol prot,
3977                        enum mlx4_steer_type steer, u64 reg_id)
3978 {
3979         struct res_gid *res;
3980         int err;
3981
3982         res = kzalloc(sizeof *res, GFP_KERNEL);
3983         if (!res)
3984                 return -ENOMEM;
3985
3986         spin_lock_irq(&rqp->mcg_spl);
3987         if (find_gid(dev, slave, rqp, gid)) {
3988                 kfree(res);
3989                 err = -EEXIST;
3990         } else {
3991                 memcpy(res->gid, gid, 16);
3992                 res->prot = prot;
3993                 res->steer = steer;
3994                 res->reg_id = reg_id;
3995                 list_add_tail(&res->list, &rqp->mcg_list);
3996                 err = 0;
3997         }
3998         spin_unlock_irq(&rqp->mcg_spl);
3999
4000         return err;
4001 }
4002
4003 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
4004                        u8 *gid, enum mlx4_protocol prot,
4005                        enum mlx4_steer_type steer, u64 *reg_id)
4006 {
4007         struct res_gid *res;
4008         int err;
4009
4010         spin_lock_irq(&rqp->mcg_spl);
4011         res = find_gid(dev, slave, rqp, gid);
4012         if (!res || res->prot != prot || res->steer != steer)
4013                 err = -EINVAL;
4014         else {
4015                 *reg_id = res->reg_id;
4016                 list_del(&res->list);
4017                 kfree(res);
4018                 err = 0;
4019         }
4020         spin_unlock_irq(&rqp->mcg_spl);
4021
4022         return err;
4023 }
4024
4025 static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
4026                      u8 gid[16], int block_loopback, enum mlx4_protocol prot,
4027                      enum mlx4_steer_type type, u64 *reg_id)
4028 {
4029         switch (dev->caps.steering_mode) {
4030         case MLX4_STEERING_MODE_DEVICE_MANAGED: {
4031                 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4032                 if (port < 0)
4033                         return port;
4034                 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
4035                                                 block_loopback, prot,
4036                                                 reg_id);
4037         }
4038         case MLX4_STEERING_MODE_B0:
4039                 if (prot == MLX4_PROT_ETH) {
4040                         int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4041                         if (port < 0)
4042                                 return port;
4043                         gid[5] = port;
4044                 }
4045                 return mlx4_qp_attach_common(dev, qp, gid,
4046                                             block_loopback, prot, type);
4047         default:
4048                 return -EINVAL;
4049         }
4050 }
4051
4052 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
4053                      u8 gid[16], enum mlx4_protocol prot,
4054                      enum mlx4_steer_type type, u64 reg_id)
4055 {
4056         switch (dev->caps.steering_mode) {
4057         case MLX4_STEERING_MODE_DEVICE_MANAGED:
4058                 return mlx4_flow_detach(dev, reg_id);
4059         case MLX4_STEERING_MODE_B0:
4060                 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
4061         default:
4062                 return -EINVAL;
4063         }
4064 }
4065
4066 static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
4067                             u8 *gid, enum mlx4_protocol prot)
4068 {
4069         int real_port;
4070
4071         if (prot != MLX4_PROT_ETH)
4072                 return 0;
4073
4074         if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
4075             dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
4076                 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
4077                 if (real_port < 0)
4078                         return -EINVAL;
4079                 gid[5] = real_port;
4080         }
4081
4082         return 0;
4083 }
4084
4085 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4086                                struct mlx4_vhcr *vhcr,
4087                                struct mlx4_cmd_mailbox *inbox,
4088                                struct mlx4_cmd_mailbox *outbox,
4089                                struct mlx4_cmd_info *cmd)
4090 {
4091         struct mlx4_qp qp; /* dummy for calling attach/detach */
4092         u8 *gid = inbox->buf;
4093         enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
4094         int err;
4095         int qpn;
4096         struct res_qp *rqp;
4097         u64 reg_id = 0;
4098         int attach = vhcr->op_modifier;
4099         int block_loopback = vhcr->in_modifier >> 31;
4100         u8 steer_type_mask = 2;
4101         enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
4102
4103         qpn = vhcr->in_modifier & 0xffffff;
4104         err = get_res(dev, slave, qpn, RES_QP, &rqp);
4105         if (err)
4106                 return err;
4107
4108         qp.qpn = qpn;
4109         if (attach) {
4110                 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
4111                                 type, &reg_id);
4112                 if (err) {
4113                         pr_err("Fail to attach rule to qp 0x%x\n", qpn);
4114                         goto ex_put;
4115                 }
4116                 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
4117                 if (err)
4118                         goto ex_detach;
4119         } else {
4120                 err = mlx4_adjust_port(dev, slave, gid, prot);
4121                 if (err)
4122                         goto ex_put;
4123
4124                 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
4125                 if (err)
4126                         goto ex_put;
4127
4128                 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
4129                 if (err)
4130                         pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
4131                                qpn, reg_id);
4132         }
4133         put_res(dev, slave, qpn, RES_QP);
4134         return err;
4135
4136 ex_detach:
4137         qp_detach(dev, &qp, gid, prot, type, reg_id);
4138 ex_put:
4139         put_res(dev, slave, qpn, RES_QP);
4140         return err;
4141 }
4142
4143 /*
4144  * MAC validation for Flow Steering rules.
4145  * VF can attach rules only with a mac address which is assigned to it.
4146  */
4147 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
4148                                    struct list_head *rlist)
4149 {
4150         struct mac_res *res, *tmp;
4151         __be64 be_mac;
4152
4153         /* make sure it isn't multicast or broadcast mac*/
4154         if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
4155             !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4156                 list_for_each_entry_safe(res, tmp, rlist, list) {
4157                         be_mac = cpu_to_be64(res->mac << 16);
4158                         if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
4159                                 return 0;
4160                 }
4161                 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
4162                        eth_header->eth.dst_mac, slave);
4163                 return -EINVAL;
4164         }
4165         return 0;
4166 }
4167
4168 /*
4169  * In case of missing eth header, append eth header with a MAC address
4170  * assigned to the VF.
4171  */
4172 static int add_eth_header(struct mlx4_dev *dev, int slave,
4173                           struct mlx4_cmd_mailbox *inbox,
4174                           struct list_head *rlist, int header_id)
4175 {
4176         struct mac_res *res, *tmp;
4177         u8 port;
4178         struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4179         struct mlx4_net_trans_rule_hw_eth *eth_header;
4180         struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
4181         struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
4182         __be64 be_mac = 0;
4183         __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
4184
4185         ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4186         port = ctrl->port;
4187         eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
4188
4189         /* Clear a space in the inbox for eth header */
4190         switch (header_id) {
4191         case MLX4_NET_TRANS_RULE_ID_IPV4:
4192                 ip_header =
4193                         (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
4194                 memmove(ip_header, eth_header,
4195                         sizeof(*ip_header) + sizeof(*l4_header));
4196                 break;
4197         case MLX4_NET_TRANS_RULE_ID_TCP:
4198         case MLX4_NET_TRANS_RULE_ID_UDP:
4199                 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
4200                             (eth_header + 1);
4201                 memmove(l4_header, eth_header, sizeof(*l4_header));
4202                 break;
4203         default:
4204                 return -EINVAL;
4205         }
4206         list_for_each_entry_safe(res, tmp, rlist, list) {
4207                 if (port == res->port) {
4208                         be_mac = cpu_to_be64(res->mac << 16);
4209                         break;
4210                 }
4211         }
4212         if (!be_mac) {
4213                 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
4214                        port);
4215                 return -EINVAL;
4216         }
4217
4218         memset(eth_header, 0, sizeof(*eth_header));
4219         eth_header->size = sizeof(*eth_header) >> 2;
4220         eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
4221         memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
4222         memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
4223
4224         return 0;
4225
4226 }
4227
4228 #define MLX4_UPD_QP_PATH_MASK_SUPPORTED      (                                \
4229         1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX                     |\
4230         1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)
4231 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
4232                            struct mlx4_vhcr *vhcr,
4233                            struct mlx4_cmd_mailbox *inbox,
4234                            struct mlx4_cmd_mailbox *outbox,
4235                            struct mlx4_cmd_info *cmd_info)
4236 {
4237         int err;
4238         u32 qpn = vhcr->in_modifier & 0xffffff;
4239         struct res_qp *rqp;
4240         u64 mac;
4241         unsigned port;
4242         u64 pri_addr_path_mask;
4243         struct mlx4_update_qp_context *cmd;
4244         int smac_index;
4245
4246         cmd = (struct mlx4_update_qp_context *)inbox->buf;
4247
4248         pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
4249         if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
4250             (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
4251                 return -EPERM;
4252
4253         if ((pri_addr_path_mask &
4254              (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) &&
4255                 !(dev->caps.flags2 &
4256                   MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
4257                 mlx4_warn(dev, "Src check LB for slave %d isn't supported\n",
4258                           slave);
4259                 return -ENOTSUPP;
4260         }
4261
4262         /* Just change the smac for the QP */
4263         err = get_res(dev, slave, qpn, RES_QP, &rqp);
4264         if (err) {
4265                 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
4266                 return err;
4267         }
4268
4269         port = (rqp->sched_queue >> 6 & 1) + 1;
4270
4271         if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
4272                 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4273                 err = mac_find_smac_ix_in_slave(dev, slave, port,
4274                                                 smac_index, &mac);
4275
4276                 if (err) {
4277                         mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4278                                  qpn, smac_index);
4279                         goto err_mac;
4280                 }
4281         }
4282
4283         err = mlx4_cmd(dev, inbox->dma,
4284                        vhcr->in_modifier, 0,
4285                        MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4286                        MLX4_CMD_NATIVE);
4287         if (err) {
4288                 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4289                 goto err_mac;
4290         }
4291
4292 err_mac:
4293         put_res(dev, slave, qpn, RES_QP);
4294         return err;
4295 }
4296
4297 static u32 qp_attach_mbox_size(void *mbox)
4298 {
4299         u32 size = sizeof(struct mlx4_net_trans_rule_hw_ctrl);
4300         struct _rule_hw  *rule_header;
4301
4302         rule_header = (struct _rule_hw *)(mbox + size);
4303
4304         while (rule_header->size) {
4305                 size += rule_header->size * sizeof(u32);
4306                 rule_header += 1;
4307         }
4308         return size;
4309 }
4310
4311 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule);
4312
4313 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4314                                          struct mlx4_vhcr *vhcr,
4315                                          struct mlx4_cmd_mailbox *inbox,
4316                                          struct mlx4_cmd_mailbox *outbox,
4317                                          struct mlx4_cmd_info *cmd)
4318 {
4319
4320         struct mlx4_priv *priv = mlx4_priv(dev);
4321         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4322         struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
4323         int err;
4324         int qpn;
4325         struct res_qp *rqp;
4326         struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4327         struct _rule_hw  *rule_header;
4328         int header_id;
4329         struct res_fs_rule *rrule;
4330         u32 mbox_size;
4331
4332         if (dev->caps.steering_mode !=
4333             MLX4_STEERING_MODE_DEVICE_MANAGED)
4334                 return -EOPNOTSUPP;
4335
4336         ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4337         err = mlx4_slave_convert_port(dev, slave, ctrl->port);
4338         if (err <= 0)
4339                 return -EINVAL;
4340         ctrl->port = err;
4341         qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
4342         err = get_res(dev, slave, qpn, RES_QP, &rqp);
4343         if (err) {
4344                 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
4345                 return err;
4346         }
4347         rule_header = (struct _rule_hw *)(ctrl + 1);
4348         header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4349
4350         if (header_id == MLX4_NET_TRANS_RULE_ID_ETH)
4351                 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
4352
4353         switch (header_id) {
4354         case MLX4_NET_TRANS_RULE_ID_ETH:
4355                 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4356                         err = -EINVAL;
4357                         goto err_put_qp;
4358                 }
4359                 break;
4360         case MLX4_NET_TRANS_RULE_ID_IB:
4361                 break;
4362         case MLX4_NET_TRANS_RULE_ID_IPV4:
4363         case MLX4_NET_TRANS_RULE_ID_TCP:
4364         case MLX4_NET_TRANS_RULE_ID_UDP:
4365                 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
4366                 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4367                         err = -EINVAL;
4368                         goto err_put_qp;
4369                 }
4370                 vhcr->in_modifier +=
4371                         sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4372                 break;
4373         default:
4374                 pr_err("Corrupted mailbox\n");
4375                 err = -EINVAL;
4376                 goto err_put_qp;
4377         }
4378
4379         err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4380                            vhcr->in_modifier, 0,
4381                            MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4382                            MLX4_CMD_NATIVE);
4383         if (err)
4384                 goto err_put_qp;
4385
4386
4387         err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
4388         if (err) {
4389                 mlx4_err(dev, "Fail to add flow steering resources\n");
4390                 goto err_detach;
4391         }
4392
4393         err = get_res(dev, slave, vhcr->out_param, RES_FS_RULE, &rrule);
4394         if (err)
4395                 goto err_detach;
4396
4397         mbox_size = qp_attach_mbox_size(inbox->buf);
4398         rrule->mirr_mbox = kmalloc(mbox_size, GFP_KERNEL);
4399         if (!rrule->mirr_mbox) {
4400                 err = -ENOMEM;
4401                 goto err_put_rule;
4402         }
4403         rrule->mirr_mbox_size = mbox_size;
4404         rrule->mirr_rule_id = 0;
4405         memcpy(rrule->mirr_mbox, inbox->buf, mbox_size);
4406
4407         /* set different port */
4408         ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)rrule->mirr_mbox;
4409         if (ctrl->port == 1)
4410                 ctrl->port = 2;
4411         else
4412                 ctrl->port = 1;
4413
4414         if (mlx4_is_bonded(dev))
4415                 mlx4_do_mirror_rule(dev, rrule);
4416
4417         atomic_inc(&rqp->ref_count);
4418
4419 err_put_rule:
4420         put_res(dev, slave, vhcr->out_param, RES_FS_RULE);
4421 err_detach:
4422         /* detach rule on error */
4423         if (err)
4424                 mlx4_cmd(dev, vhcr->out_param, 0, 0,
4425                          MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4426                          MLX4_CMD_NATIVE);
4427 err_put_qp:
4428         put_res(dev, slave, qpn, RES_QP);
4429         return err;
4430 }
4431
4432 static int mlx4_undo_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4433 {
4434         int err;
4435
4436         err = rem_res_range(dev, fs_rule->com.owner, fs_rule->com.res_id, 1, RES_FS_RULE, 0);
4437         if (err) {
4438                 mlx4_err(dev, "Fail to remove flow steering resources\n");
4439                 return err;
4440         }
4441
4442         mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4443                  MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
4444         return 0;
4445 }
4446
4447 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4448                                          struct mlx4_vhcr *vhcr,
4449                                          struct mlx4_cmd_mailbox *inbox,
4450                                          struct mlx4_cmd_mailbox *outbox,
4451                                          struct mlx4_cmd_info *cmd)
4452 {
4453         int err;
4454         struct res_qp *rqp;
4455         struct res_fs_rule *rrule;
4456         u64 mirr_reg_id;
4457         int qpn;
4458
4459         if (dev->caps.steering_mode !=
4460             MLX4_STEERING_MODE_DEVICE_MANAGED)
4461                 return -EOPNOTSUPP;
4462
4463         err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4464         if (err)
4465                 return err;
4466
4467         if (!rrule->mirr_mbox) {
4468                 mlx4_err(dev, "Mirror rules cannot be removed explicitly\n");
4469                 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4470                 return -EINVAL;
4471         }
4472         mirr_reg_id = rrule->mirr_rule_id;
4473         kfree(rrule->mirr_mbox);
4474         qpn = rrule->qpn;
4475
4476         /* Release the rule form busy state before removal */
4477         put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4478         err = get_res(dev, slave, qpn, RES_QP, &rqp);
4479         if (err)
4480                 return err;
4481
4482         if (mirr_reg_id && mlx4_is_bonded(dev)) {
4483                 err = get_res(dev, slave, mirr_reg_id, RES_FS_RULE, &rrule);
4484                 if (err) {
4485                         mlx4_err(dev, "Fail to get resource of mirror rule\n");
4486                 } else {
4487                         put_res(dev, slave, mirr_reg_id, RES_FS_RULE);
4488                         mlx4_undo_mirror_rule(dev, rrule);
4489                 }
4490         }
4491         err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4492         if (err) {
4493                 mlx4_err(dev, "Fail to remove flow steering resources\n");
4494                 goto out;
4495         }
4496
4497         err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4498                        MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4499                        MLX4_CMD_NATIVE);
4500         if (!err)
4501                 atomic_dec(&rqp->ref_count);
4502 out:
4503         put_res(dev, slave, qpn, RES_QP);
4504         return err;
4505 }
4506
4507 enum {
4508         BUSY_MAX_RETRIES = 10
4509 };
4510
4511 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4512                                struct mlx4_vhcr *vhcr,
4513                                struct mlx4_cmd_mailbox *inbox,
4514                                struct mlx4_cmd_mailbox *outbox,
4515                                struct mlx4_cmd_info *cmd)
4516 {
4517         int err;
4518         int index = vhcr->in_modifier & 0xffff;
4519
4520         err = get_res(dev, slave, index, RES_COUNTER, NULL);
4521         if (err)
4522                 return err;
4523
4524         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4525         put_res(dev, slave, index, RES_COUNTER);
4526         return err;
4527 }
4528
4529 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4530 {
4531         struct res_gid *rgid;
4532         struct res_gid *tmp;
4533         struct mlx4_qp qp; /* dummy for calling attach/detach */
4534
4535         list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
4536                 switch (dev->caps.steering_mode) {
4537                 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4538                         mlx4_flow_detach(dev, rgid->reg_id);
4539                         break;
4540                 case MLX4_STEERING_MODE_B0:
4541                         qp.qpn = rqp->local_qpn;
4542                         (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4543                                                      rgid->prot, rgid->steer);
4544                         break;
4545                 }
4546                 list_del(&rgid->list);
4547                 kfree(rgid);
4548         }
4549 }
4550
4551 static int _move_all_busy(struct mlx4_dev *dev, int slave,
4552                           enum mlx4_resource type, int print)
4553 {
4554         struct mlx4_priv *priv = mlx4_priv(dev);
4555         struct mlx4_resource_tracker *tracker =
4556                 &priv->mfunc.master.res_tracker;
4557         struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4558         struct res_common *r;
4559         struct res_common *tmp;
4560         int busy;
4561
4562         busy = 0;
4563         spin_lock_irq(mlx4_tlock(dev));
4564         list_for_each_entry_safe(r, tmp, rlist, list) {
4565                 if (r->owner == slave) {
4566                         if (!r->removing) {
4567                                 if (r->state == RES_ANY_BUSY) {
4568                                         if (print)
4569                                                 mlx4_dbg(dev,
4570                                                          "%s id 0x%llx is busy\n",
4571                                                           resource_str(type),
4572                                                           r->res_id);
4573                                         ++busy;
4574                                 } else {
4575                                         r->from_state = r->state;
4576                                         r->state = RES_ANY_BUSY;
4577                                         r->removing = 1;
4578                                 }
4579                         }
4580                 }
4581         }
4582         spin_unlock_irq(mlx4_tlock(dev));
4583
4584         return busy;
4585 }
4586
4587 static int move_all_busy(struct mlx4_dev *dev, int slave,
4588                          enum mlx4_resource type)
4589 {
4590         unsigned long begin;
4591         int busy;
4592
4593         begin = jiffies;
4594         do {
4595                 busy = _move_all_busy(dev, slave, type, 0);
4596                 if (time_after(jiffies, begin + 5 * HZ))
4597                         break;
4598                 if (busy)
4599                         cond_resched();
4600         } while (busy);
4601
4602         if (busy)
4603                 busy = _move_all_busy(dev, slave, type, 1);
4604
4605         return busy;
4606 }
4607 static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4608 {
4609         struct mlx4_priv *priv = mlx4_priv(dev);
4610         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4611         struct list_head *qp_list =
4612                 &tracker->slave_list[slave].res_list[RES_QP];
4613         struct res_qp *qp;
4614         struct res_qp *tmp;
4615         int state;
4616         u64 in_param;
4617         int qpn;
4618         int err;
4619
4620         err = move_all_busy(dev, slave, RES_QP);
4621         if (err)
4622                 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4623                           slave);
4624
4625         spin_lock_irq(mlx4_tlock(dev));
4626         list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4627                 spin_unlock_irq(mlx4_tlock(dev));
4628                 if (qp->com.owner == slave) {
4629                         qpn = qp->com.res_id;
4630                         detach_qp(dev, slave, qp);
4631                         state = qp->com.from_state;
4632                         while (state != 0) {
4633                                 switch (state) {
4634                                 case RES_QP_RESERVED:
4635                                         spin_lock_irq(mlx4_tlock(dev));
4636                                         rb_erase(&qp->com.node,
4637                                                  &tracker->res_tree[RES_QP]);
4638                                         list_del(&qp->com.list);
4639                                         spin_unlock_irq(mlx4_tlock(dev));
4640                                         if (!valid_reserved(dev, slave, qpn)) {
4641                                                 __mlx4_qp_release_range(dev, qpn, 1);
4642                                                 mlx4_release_resource(dev, slave,
4643                                                                       RES_QP, 1, 0);
4644                                         }
4645                                         kfree(qp);
4646                                         state = 0;
4647                                         break;
4648                                 case RES_QP_MAPPED:
4649                                         if (!valid_reserved(dev, slave, qpn))
4650                                                 __mlx4_qp_free_icm(dev, qpn);
4651                                         state = RES_QP_RESERVED;
4652                                         break;
4653                                 case RES_QP_HW:
4654                                         in_param = slave;
4655                                         err = mlx4_cmd(dev, in_param,
4656                                                        qp->local_qpn, 2,
4657                                                        MLX4_CMD_2RST_QP,
4658                                                        MLX4_CMD_TIME_CLASS_A,
4659                                                        MLX4_CMD_NATIVE);
4660                                         if (err)
4661                                                 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4662                                                          slave, qp->local_qpn);
4663                                         atomic_dec(&qp->rcq->ref_count);
4664                                         atomic_dec(&qp->scq->ref_count);
4665                                         atomic_dec(&qp->mtt->ref_count);
4666                                         if (qp->srq)
4667                                                 atomic_dec(&qp->srq->ref_count);
4668                                         state = RES_QP_MAPPED;
4669                                         break;
4670                                 default:
4671                                         state = 0;
4672                                 }
4673                         }
4674                 }
4675                 spin_lock_irq(mlx4_tlock(dev));
4676         }
4677         spin_unlock_irq(mlx4_tlock(dev));
4678 }
4679
4680 static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4681 {
4682         struct mlx4_priv *priv = mlx4_priv(dev);
4683         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4684         struct list_head *srq_list =
4685                 &tracker->slave_list[slave].res_list[RES_SRQ];
4686         struct res_srq *srq;
4687         struct res_srq *tmp;
4688         int state;
4689         u64 in_param;
4690         LIST_HEAD(tlist);
4691         int srqn;
4692         int err;
4693
4694         err = move_all_busy(dev, slave, RES_SRQ);
4695         if (err)
4696                 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4697                           slave);
4698
4699         spin_lock_irq(mlx4_tlock(dev));
4700         list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4701                 spin_unlock_irq(mlx4_tlock(dev));
4702                 if (srq->com.owner == slave) {
4703                         srqn = srq->com.res_id;
4704                         state = srq->com.from_state;
4705                         while (state != 0) {
4706                                 switch (state) {
4707                                 case RES_SRQ_ALLOCATED:
4708                                         __mlx4_srq_free_icm(dev, srqn);
4709                                         spin_lock_irq(mlx4_tlock(dev));
4710                                         rb_erase(&srq->com.node,
4711                                                  &tracker->res_tree[RES_SRQ]);
4712                                         list_del(&srq->com.list);
4713                                         spin_unlock_irq(mlx4_tlock(dev));
4714                                         mlx4_release_resource(dev, slave,
4715                                                               RES_SRQ, 1, 0);
4716                                         kfree(srq);
4717                                         state = 0;
4718                                         break;
4719
4720                                 case RES_SRQ_HW:
4721                                         in_param = slave;
4722                                         err = mlx4_cmd(dev, in_param, srqn, 1,
4723                                                        MLX4_CMD_HW2SW_SRQ,
4724                                                        MLX4_CMD_TIME_CLASS_A,
4725                                                        MLX4_CMD_NATIVE);
4726                                         if (err)
4727                                                 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
4728                                                          slave, srqn);
4729
4730                                         atomic_dec(&srq->mtt->ref_count);
4731                                         if (srq->cq)
4732                                                 atomic_dec(&srq->cq->ref_count);
4733                                         state = RES_SRQ_ALLOCATED;
4734                                         break;
4735
4736                                 default:
4737                                         state = 0;
4738                                 }
4739                         }
4740                 }
4741                 spin_lock_irq(mlx4_tlock(dev));
4742         }
4743         spin_unlock_irq(mlx4_tlock(dev));
4744 }
4745
4746 static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4747 {
4748         struct mlx4_priv *priv = mlx4_priv(dev);
4749         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4750         struct list_head *cq_list =
4751                 &tracker->slave_list[slave].res_list[RES_CQ];
4752         struct res_cq *cq;
4753         struct res_cq *tmp;
4754         int state;
4755         u64 in_param;
4756         LIST_HEAD(tlist);
4757         int cqn;
4758         int err;
4759
4760         err = move_all_busy(dev, slave, RES_CQ);
4761         if (err)
4762                 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4763                           slave);
4764
4765         spin_lock_irq(mlx4_tlock(dev));
4766         list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4767                 spin_unlock_irq(mlx4_tlock(dev));
4768                 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4769                         cqn = cq->com.res_id;
4770                         state = cq->com.from_state;
4771                         while (state != 0) {
4772                                 switch (state) {
4773                                 case RES_CQ_ALLOCATED:
4774                                         __mlx4_cq_free_icm(dev, cqn);
4775                                         spin_lock_irq(mlx4_tlock(dev));
4776                                         rb_erase(&cq->com.node,
4777                                                  &tracker->res_tree[RES_CQ]);
4778                                         list_del(&cq->com.list);
4779                                         spin_unlock_irq(mlx4_tlock(dev));
4780                                         mlx4_release_resource(dev, slave,
4781                                                               RES_CQ, 1, 0);
4782                                         kfree(cq);
4783                                         state = 0;
4784                                         break;
4785
4786                                 case RES_CQ_HW:
4787                                         in_param = slave;
4788                                         err = mlx4_cmd(dev, in_param, cqn, 1,
4789                                                        MLX4_CMD_HW2SW_CQ,
4790                                                        MLX4_CMD_TIME_CLASS_A,
4791                                                        MLX4_CMD_NATIVE);
4792                                         if (err)
4793                                                 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
4794                                                          slave, cqn);
4795                                         atomic_dec(&cq->mtt->ref_count);
4796                                         state = RES_CQ_ALLOCATED;
4797                                         break;
4798
4799                                 default:
4800                                         state = 0;
4801                                 }
4802                         }
4803                 }
4804                 spin_lock_irq(mlx4_tlock(dev));
4805         }
4806         spin_unlock_irq(mlx4_tlock(dev));
4807 }
4808
4809 static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4810 {
4811         struct mlx4_priv *priv = mlx4_priv(dev);
4812         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4813         struct list_head *mpt_list =
4814                 &tracker->slave_list[slave].res_list[RES_MPT];
4815         struct res_mpt *mpt;
4816         struct res_mpt *tmp;
4817         int state;
4818         u64 in_param;
4819         LIST_HEAD(tlist);
4820         int mptn;
4821         int err;
4822
4823         err = move_all_busy(dev, slave, RES_MPT);
4824         if (err)
4825                 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4826                           slave);
4827
4828         spin_lock_irq(mlx4_tlock(dev));
4829         list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4830                 spin_unlock_irq(mlx4_tlock(dev));
4831                 if (mpt->com.owner == slave) {
4832                         mptn = mpt->com.res_id;
4833                         state = mpt->com.from_state;
4834                         while (state != 0) {
4835                                 switch (state) {
4836                                 case RES_MPT_RESERVED:
4837                                         __mlx4_mpt_release(dev, mpt->key);
4838                                         spin_lock_irq(mlx4_tlock(dev));
4839                                         rb_erase(&mpt->com.node,
4840                                                  &tracker->res_tree[RES_MPT]);
4841                                         list_del(&mpt->com.list);
4842                                         spin_unlock_irq(mlx4_tlock(dev));
4843                                         mlx4_release_resource(dev, slave,
4844                                                               RES_MPT, 1, 0);
4845                                         kfree(mpt);
4846                                         state = 0;
4847                                         break;
4848
4849                                 case RES_MPT_MAPPED:
4850                                         __mlx4_mpt_free_icm(dev, mpt->key);
4851                                         state = RES_MPT_RESERVED;
4852                                         break;
4853
4854                                 case RES_MPT_HW:
4855                                         in_param = slave;
4856                                         err = mlx4_cmd(dev, in_param, mptn, 0,
4857                                                      MLX4_CMD_HW2SW_MPT,
4858                                                      MLX4_CMD_TIME_CLASS_A,
4859                                                      MLX4_CMD_NATIVE);
4860                                         if (err)
4861                                                 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
4862                                                          slave, mptn);
4863                                         if (mpt->mtt)
4864                                                 atomic_dec(&mpt->mtt->ref_count);
4865                                         state = RES_MPT_MAPPED;
4866                                         break;
4867                                 default:
4868                                         state = 0;
4869                                 }
4870                         }
4871                 }
4872                 spin_lock_irq(mlx4_tlock(dev));
4873         }
4874         spin_unlock_irq(mlx4_tlock(dev));
4875 }
4876
4877 static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4878 {
4879         struct mlx4_priv *priv = mlx4_priv(dev);
4880         struct mlx4_resource_tracker *tracker =
4881                 &priv->mfunc.master.res_tracker;
4882         struct list_head *mtt_list =
4883                 &tracker->slave_list[slave].res_list[RES_MTT];
4884         struct res_mtt *mtt;
4885         struct res_mtt *tmp;
4886         int state;
4887         LIST_HEAD(tlist);
4888         int base;
4889         int err;
4890
4891         err = move_all_busy(dev, slave, RES_MTT);
4892         if (err)
4893                 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts  - too busy for slave %d\n",
4894                           slave);
4895
4896         spin_lock_irq(mlx4_tlock(dev));
4897         list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4898                 spin_unlock_irq(mlx4_tlock(dev));
4899                 if (mtt->com.owner == slave) {
4900                         base = mtt->com.res_id;
4901                         state = mtt->com.from_state;
4902                         while (state != 0) {
4903                                 switch (state) {
4904                                 case RES_MTT_ALLOCATED:
4905                                         __mlx4_free_mtt_range(dev, base,
4906                                                               mtt->order);
4907                                         spin_lock_irq(mlx4_tlock(dev));
4908                                         rb_erase(&mtt->com.node,
4909                                                  &tracker->res_tree[RES_MTT]);
4910                                         list_del(&mtt->com.list);
4911                                         spin_unlock_irq(mlx4_tlock(dev));
4912                                         mlx4_release_resource(dev, slave, RES_MTT,
4913                                                               1 << mtt->order, 0);
4914                                         kfree(mtt);
4915                                         state = 0;
4916                                         break;
4917
4918                                 default:
4919                                         state = 0;
4920                                 }
4921                         }
4922                 }
4923                 spin_lock_irq(mlx4_tlock(dev));
4924         }
4925         spin_unlock_irq(mlx4_tlock(dev));
4926 }
4927
4928 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4929 {
4930         struct mlx4_cmd_mailbox *mailbox;
4931         int err;
4932         struct res_fs_rule *mirr_rule;
4933         u64 reg_id;
4934
4935         mailbox = mlx4_alloc_cmd_mailbox(dev);
4936         if (IS_ERR(mailbox))
4937                 return PTR_ERR(mailbox);
4938
4939         if (!fs_rule->mirr_mbox) {
4940                 mlx4_err(dev, "rule mirroring mailbox is null\n");
4941                 return -EINVAL;
4942         }
4943         memcpy(mailbox->buf, fs_rule->mirr_mbox, fs_rule->mirr_mbox_size);
4944         err = mlx4_cmd_imm(dev, mailbox->dma, &reg_id, fs_rule->mirr_mbox_size >> 2, 0,
4945                            MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4946                            MLX4_CMD_NATIVE);
4947         mlx4_free_cmd_mailbox(dev, mailbox);
4948
4949         if (err)
4950                 goto err;
4951
4952         err = add_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, fs_rule->qpn);
4953         if (err)
4954                 goto err_detach;
4955
4956         err = get_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE, &mirr_rule);
4957         if (err)
4958                 goto err_rem;
4959
4960         fs_rule->mirr_rule_id = reg_id;
4961         mirr_rule->mirr_rule_id = 0;
4962         mirr_rule->mirr_mbox_size = 0;
4963         mirr_rule->mirr_mbox = NULL;
4964         put_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE);
4965
4966         return 0;
4967 err_rem:
4968         rem_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, 0);
4969 err_detach:
4970         mlx4_cmd(dev, reg_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4971                  MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
4972 err:
4973         return err;
4974 }
4975
4976 static int mlx4_mirror_fs_rules(struct mlx4_dev *dev, bool bond)
4977 {
4978         struct mlx4_priv *priv = mlx4_priv(dev);
4979         struct mlx4_resource_tracker *tracker =
4980                 &priv->mfunc.master.res_tracker;
4981         struct rb_root *root = &tracker->res_tree[RES_FS_RULE];
4982         struct rb_node *p;
4983         struct res_fs_rule *fs_rule;
4984         int err = 0;
4985         LIST_HEAD(mirr_list);
4986
4987         for (p = rb_first(root); p; p = rb_next(p)) {
4988                 fs_rule = rb_entry(p, struct res_fs_rule, com.node);
4989                 if ((bond && fs_rule->mirr_mbox_size) ||
4990                     (!bond && !fs_rule->mirr_mbox_size))
4991                         list_add_tail(&fs_rule->mirr_list, &mirr_list);
4992         }
4993
4994         list_for_each_entry(fs_rule, &mirr_list, mirr_list) {
4995                 if (bond)
4996                         err += mlx4_do_mirror_rule(dev, fs_rule);
4997                 else
4998                         err += mlx4_undo_mirror_rule(dev, fs_rule);
4999         }
5000         return err;
5001 }
5002
5003 int mlx4_bond_fs_rules(struct mlx4_dev *dev)
5004 {
5005         return mlx4_mirror_fs_rules(dev, true);
5006 }
5007
5008 int mlx4_unbond_fs_rules(struct mlx4_dev *dev)
5009 {
5010         return mlx4_mirror_fs_rules(dev, false);
5011 }
5012
5013 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
5014 {
5015         struct mlx4_priv *priv = mlx4_priv(dev);
5016         struct mlx4_resource_tracker *tracker =
5017                 &priv->mfunc.master.res_tracker;
5018         struct list_head *fs_rule_list =
5019                 &tracker->slave_list[slave].res_list[RES_FS_RULE];
5020         struct res_fs_rule *fs_rule;
5021         struct res_fs_rule *tmp;
5022         int state;
5023         u64 base;
5024         int err;
5025
5026         err = move_all_busy(dev, slave, RES_FS_RULE);
5027         if (err)
5028                 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
5029                           slave);
5030
5031         spin_lock_irq(mlx4_tlock(dev));
5032         list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
5033                 spin_unlock_irq(mlx4_tlock(dev));
5034                 if (fs_rule->com.owner == slave) {
5035                         base = fs_rule->com.res_id;
5036                         state = fs_rule->com.from_state;
5037                         while (state != 0) {
5038                                 switch (state) {
5039                                 case RES_FS_RULE_ALLOCATED:
5040                                         /* detach rule */
5041                                         err = mlx4_cmd(dev, base, 0, 0,
5042                                                        MLX4_QP_FLOW_STEERING_DETACH,
5043                                                        MLX4_CMD_TIME_CLASS_A,
5044                                                        MLX4_CMD_NATIVE);
5045
5046                                         spin_lock_irq(mlx4_tlock(dev));
5047                                         rb_erase(&fs_rule->com.node,
5048                                                  &tracker->res_tree[RES_FS_RULE]);
5049                                         list_del(&fs_rule->com.list);
5050                                         spin_unlock_irq(mlx4_tlock(dev));
5051                                         kfree(fs_rule);
5052                                         state = 0;
5053                                         break;
5054
5055                                 default:
5056                                         state = 0;
5057                                 }
5058                         }
5059                 }
5060                 spin_lock_irq(mlx4_tlock(dev));
5061         }
5062         spin_unlock_irq(mlx4_tlock(dev));
5063 }
5064
5065 static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
5066 {
5067         struct mlx4_priv *priv = mlx4_priv(dev);
5068         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5069         struct list_head *eq_list =
5070                 &tracker->slave_list[slave].res_list[RES_EQ];
5071         struct res_eq *eq;
5072         struct res_eq *tmp;
5073         int err;
5074         int state;
5075         LIST_HEAD(tlist);
5076         int eqn;
5077
5078         err = move_all_busy(dev, slave, RES_EQ);
5079         if (err)
5080                 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
5081                           slave);
5082
5083         spin_lock_irq(mlx4_tlock(dev));
5084         list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
5085                 spin_unlock_irq(mlx4_tlock(dev));
5086                 if (eq->com.owner == slave) {
5087                         eqn = eq->com.res_id;
5088                         state = eq->com.from_state;
5089                         while (state != 0) {
5090                                 switch (state) {
5091                                 case RES_EQ_RESERVED:
5092                                         spin_lock_irq(mlx4_tlock(dev));
5093                                         rb_erase(&eq->com.node,
5094                                                  &tracker->res_tree[RES_EQ]);
5095                                         list_del(&eq->com.list);
5096                                         spin_unlock_irq(mlx4_tlock(dev));
5097                                         kfree(eq);
5098                                         state = 0;
5099                                         break;
5100
5101                                 case RES_EQ_HW:
5102                                         err = mlx4_cmd(dev, slave, eqn & 0x3ff,
5103                                                        1, MLX4_CMD_HW2SW_EQ,
5104                                                        MLX4_CMD_TIME_CLASS_A,
5105                                                        MLX4_CMD_NATIVE);
5106                                         if (err)
5107                                                 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
5108                                                          slave, eqn & 0x3ff);
5109                                         atomic_dec(&eq->mtt->ref_count);
5110                                         state = RES_EQ_RESERVED;
5111                                         break;
5112
5113                                 default:
5114                                         state = 0;
5115                                 }
5116                         }
5117                 }
5118                 spin_lock_irq(mlx4_tlock(dev));
5119         }
5120         spin_unlock_irq(mlx4_tlock(dev));
5121 }
5122
5123 static void rem_slave_counters(struct mlx4_dev *dev, int slave)
5124 {
5125         struct mlx4_priv *priv = mlx4_priv(dev);
5126         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5127         struct list_head *counter_list =
5128                 &tracker->slave_list[slave].res_list[RES_COUNTER];
5129         struct res_counter *counter;
5130         struct res_counter *tmp;
5131         int err;
5132         int *counters_arr = NULL;
5133         int i, j;
5134
5135         err = move_all_busy(dev, slave, RES_COUNTER);
5136         if (err)
5137                 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
5138                           slave);
5139
5140         counters_arr = kmalloc_array(dev->caps.max_counters,
5141                                      sizeof(*counters_arr), GFP_KERNEL);
5142         if (!counters_arr)
5143                 return;
5144
5145         do {
5146                 i = 0;
5147                 j = 0;
5148                 spin_lock_irq(mlx4_tlock(dev));
5149                 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
5150                         if (counter->com.owner == slave) {
5151                                 counters_arr[i++] = counter->com.res_id;
5152                                 rb_erase(&counter->com.node,
5153                                          &tracker->res_tree[RES_COUNTER]);
5154                                 list_del(&counter->com.list);
5155                                 kfree(counter);
5156                         }
5157                 }
5158                 spin_unlock_irq(mlx4_tlock(dev));
5159
5160                 while (j < i) {
5161                         __mlx4_counter_free(dev, counters_arr[j++]);
5162                         mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
5163                 }
5164         } while (i);
5165
5166         kfree(counters_arr);
5167 }
5168
5169 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
5170 {
5171         struct mlx4_priv *priv = mlx4_priv(dev);
5172         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5173         struct list_head *xrcdn_list =
5174                 &tracker->slave_list[slave].res_list[RES_XRCD];
5175         struct res_xrcdn *xrcd;
5176         struct res_xrcdn *tmp;
5177         int err;
5178         int xrcdn;
5179
5180         err = move_all_busy(dev, slave, RES_XRCD);
5181         if (err)
5182                 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
5183                           slave);
5184
5185         spin_lock_irq(mlx4_tlock(dev));
5186         list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
5187                 if (xrcd->com.owner == slave) {
5188                         xrcdn = xrcd->com.res_id;
5189                         rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
5190                         list_del(&xrcd->com.list);
5191                         kfree(xrcd);
5192                         __mlx4_xrcd_free(dev, xrcdn);
5193                 }
5194         }
5195         spin_unlock_irq(mlx4_tlock(dev));
5196 }
5197
5198 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
5199 {
5200         struct mlx4_priv *priv = mlx4_priv(dev);
5201         mlx4_reset_roce_gids(dev, slave);
5202         mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5203         rem_slave_vlans(dev, slave);
5204         rem_slave_macs(dev, slave);
5205         rem_slave_fs_rule(dev, slave);
5206         rem_slave_qps(dev, slave);
5207         rem_slave_srqs(dev, slave);
5208         rem_slave_cqs(dev, slave);
5209         rem_slave_mrs(dev, slave);
5210         rem_slave_eqs(dev, slave);
5211         rem_slave_mtts(dev, slave);
5212         rem_slave_counters(dev, slave);
5213         rem_slave_xrcdns(dev, slave);
5214         mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5215 }
5216
5217 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
5218 {
5219         struct mlx4_vf_immed_vlan_work *work =
5220                 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
5221         struct mlx4_cmd_mailbox *mailbox;
5222         struct mlx4_update_qp_context *upd_context;
5223         struct mlx4_dev *dev = &work->priv->dev;
5224         struct mlx4_resource_tracker *tracker =
5225                 &work->priv->mfunc.master.res_tracker;
5226         struct list_head *qp_list =
5227                 &tracker->slave_list[work->slave].res_list[RES_QP];
5228         struct res_qp *qp;
5229         struct res_qp *tmp;
5230         u64 qp_path_mask_vlan_ctrl =
5231                        ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
5232                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
5233                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
5234                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
5235                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
5236                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
5237
5238         u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
5239                        (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
5240                        (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
5241                        (1ULL << MLX4_UPD_QP_PATH_MASK_SV) |
5242                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
5243                        (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
5244                        (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
5245                        (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
5246
5247         int err;
5248         int port, errors = 0;
5249         u8 vlan_control;
5250
5251         if (mlx4_is_slave(dev)) {
5252                 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
5253                           work->slave);
5254                 goto out;
5255         }
5256
5257         mailbox = mlx4_alloc_cmd_mailbox(dev);
5258         if (IS_ERR(mailbox))
5259                 goto out;
5260         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
5261                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5262                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5263                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
5264                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5265                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
5266                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5267         else if (!work->vlan_id)
5268                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5269                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5270         else if (work->vlan_proto == htons(ETH_P_8021AD))
5271                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5272                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5273                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5274                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5275         else  /* vst 802.1Q */
5276                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5277                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5278                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5279
5280         upd_context = mailbox->buf;
5281         upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
5282
5283         spin_lock_irq(mlx4_tlock(dev));
5284         list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
5285                 spin_unlock_irq(mlx4_tlock(dev));
5286                 if (qp->com.owner == work->slave) {
5287                         if (qp->com.from_state != RES_QP_HW ||
5288                             !qp->sched_queue ||  /* no INIT2RTR trans yet */
5289                             mlx4_is_qp_reserved(dev, qp->local_qpn) ||
5290                             qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
5291                                 spin_lock_irq(mlx4_tlock(dev));
5292                                 continue;
5293                         }
5294                         port = (qp->sched_queue >> 6 & 1) + 1;
5295                         if (port != work->port) {
5296                                 spin_lock_irq(mlx4_tlock(dev));
5297                                 continue;
5298                         }
5299                         if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
5300                                 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
5301                         else
5302                                 upd_context->primary_addr_path_mask =
5303                                         cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
5304                         if (work->vlan_id == MLX4_VGT) {
5305                                 upd_context->qp_context.param3 = qp->param3;
5306                                 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
5307                                 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
5308                                 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
5309                                 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
5310                                 upd_context->qp_context.pri_path.feup = qp->feup;
5311                                 upd_context->qp_context.pri_path.sched_queue =
5312                                         qp->sched_queue;
5313                         } else {
5314                                 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
5315                                 upd_context->qp_context.pri_path.vlan_control = vlan_control;
5316                                 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
5317                                 upd_context->qp_context.pri_path.fvl_rx =
5318                                         qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
5319                                 upd_context->qp_context.pri_path.fl =
5320                                         qp->pri_path_fl | MLX4_FL_ETH_HIDE_CQE_VLAN;
5321                                 if (work->vlan_proto == htons(ETH_P_8021AD))
5322                                         upd_context->qp_context.pri_path.fl |= MLX4_FL_SV;
5323                                 else
5324                                         upd_context->qp_context.pri_path.fl |= MLX4_FL_CV;
5325                                 upd_context->qp_context.pri_path.feup =
5326                                         qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
5327                                 upd_context->qp_context.pri_path.sched_queue =
5328                                         qp->sched_queue & 0xC7;
5329                                 upd_context->qp_context.pri_path.sched_queue |=
5330                                         ((work->qos & 0x7) << 3);
5331                                 upd_context->qp_mask |=
5332                                         cpu_to_be64(1ULL <<
5333                                                     MLX4_UPD_QP_MASK_QOS_VPP);
5334                                 upd_context->qp_context.qos_vport =
5335                                         work->qos_vport;
5336                         }
5337
5338                         err = mlx4_cmd(dev, mailbox->dma,
5339                                        qp->local_qpn & 0xffffff,
5340                                        0, MLX4_CMD_UPDATE_QP,
5341                                        MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
5342                         if (err) {
5343                                 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
5344                                           work->slave, port, qp->local_qpn, err);
5345                                 errors++;
5346                         }
5347                 }
5348                 spin_lock_irq(mlx4_tlock(dev));
5349         }
5350         spin_unlock_irq(mlx4_tlock(dev));
5351         mlx4_free_cmd_mailbox(dev, mailbox);
5352
5353         if (errors)
5354                 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
5355                          errors, work->slave, work->port);
5356
5357         /* unregister previous vlan_id if needed and we had no errors
5358          * while updating the QPs
5359          */
5360         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
5361             NO_INDX != work->orig_vlan_ix)
5362                 __mlx4_unregister_vlan(&work->priv->dev, work->port,
5363                                        work->orig_vlan_id);
5364 out:
5365         kfree(work);
5366         return;
5367 }