drivers/net/ethernet/mellanox/mlx4/en_tx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <asm/page.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/tcp.h>
  43 #include <linux/ip.h>
  44 #include <linux/ipv6.h>
  45 #include <linux/moduleparam.h>
  46
  47 #include "mlx4_en.h"
  48
  49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  50                            struct mlx4_en_tx_ring **pring, u32 size,
  51                            u16 stride, int node, int queue_index)
  52 {
  53         struct mlx4_en_dev *mdev = priv->mdev;
  54         struct mlx4_en_tx_ring *ring;
  55         int tmp;
  56         int err;
  57
  58         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
  59         if (!ring) {
  60                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  61                 if (!ring) {
  62                         en_err(priv, "Failed allocating TX ring\n");
  63                         return -ENOMEM;
  64                 }
  65         }
  66
  67         ring->size = size;
  68         ring->size_mask = size - 1;
  69         ring->sp_stride = stride;
  70         ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
  71
  72         tmp = size * sizeof(struct mlx4_en_tx_info);
  73         ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
  74         if (!ring->tx_info) {
  75                 ring->tx_info = vmalloc(tmp);
  76                 if (!ring->tx_info) {
  77                         err = -ENOMEM;
  78                         goto err_ring;
  79                 }
  80         }
  81
  82         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  83                  ring->tx_info, tmp);
  84
  85         ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
  86         if (!ring->bounce_buf) {
  87                 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  88                 if (!ring->bounce_buf) {
  89                         err = -ENOMEM;
  90                         goto err_info;
  91                 }
  92         }
  93         ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE);
  94
  95         /* Allocate HW buffers on provided NUMA node */
  96         set_dev_node(&mdev->dev->persist->pdev->dev, node);
  97         err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
  98         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
  99         if (err) {
 100                 en_err(priv, "Failed allocating hwq resources\n");
 101                 goto err_bounce;
 102         }
 103
 104         ring->buf = ring->sp_wqres.buf.direct.buf;
 105
 106         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
 107                ring, ring->buf, ring->size, ring->buf_size,
 108                (unsigned long long) ring->sp_wqres.buf.direct.map);
 109
 110         err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
 111                                     MLX4_RESERVE_ETH_BF_QP);
 112         if (err) {
 113                 en_err(priv, "failed reserving qp for TX ring\n");
 114                 goto err_hwq_res;
 115         }
 116
 117         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp, GFP_KERNEL);
 118         if (err) {
 119                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 120                 goto err_reserve;
 121         }
 122         ring->sp_qp.event = mlx4_en_sqp_event;
 123
 124         err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
 125         if (err) {
 126                 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
 127                 ring->bf.uar = &mdev->priv_uar;
 128                 ring->bf.uar->map = mdev->uar_map;
 129                 ring->bf_enabled = false;
 130                 ring->bf_alloced = false;
 131                 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
 132         } else {
 133                 ring->bf_alloced = true;
 134                 ring->bf_enabled = !!(priv->pflags &
 135                                       MLX4_EN_PRIV_FLAGS_BLUEFLAME);
 136         }
 137
 138         ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
 139         ring->queue_index = queue_index;
 140
 141         if (queue_index < priv->num_tx_rings_p_up)
 142                 cpumask_set_cpu(cpumask_local_spread(queue_index,
 143                                                      priv->mdev->dev->numa_node),
 144                                 &ring->sp_affinity_mask);
 145
 146         *pring = ring;
 147         return 0;
 148
 149 err_reserve:
 150         mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
 151 err_hwq_res:
 152         mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 153 err_bounce:
 154         kfree(ring->bounce_buf);
 155         ring->bounce_buf = NULL;
 156 err_info:
 157         kvfree(ring->tx_info);
 158         ring->tx_info = NULL;
 159 err_ring:
 160         kfree(ring);
 161         *pring = NULL;
 162         return err;
 163 }
 164
 165 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 166                              struct mlx4_en_tx_ring **pring)
 167 {
 168         struct mlx4_en_dev *mdev = priv->mdev;
 169         struct mlx4_en_tx_ring *ring = *pring;
 170         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 171
 172         if (ring->bf_alloced)
 173                 mlx4_bf_free(mdev->dev, &ring->bf);
 174         mlx4_qp_remove(mdev->dev, &ring->sp_qp);
 175         mlx4_qp_free(mdev->dev, &ring->sp_qp);
 176         mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
 177         mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 178         kfree(ring->bounce_buf);
 179         ring->bounce_buf = NULL;
 180         kvfree(ring->tx_info);
 181         ring->tx_info = NULL;
 182         kfree(ring);
 183         *pring = NULL;
 184 }
 185
 186 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 187                              struct mlx4_en_tx_ring *ring,
 188                              int cq, int user_prio)
 189 {
 190         struct mlx4_en_dev *mdev = priv->mdev;
 191         int err;
 192
 193         ring->sp_cqn = cq;
 194         ring->prod = 0;
 195         ring->cons = 0xffffffff;
 196         ring->last_nr_txbb = 1;
 197         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 198         memset(ring->buf, 0, ring->buf_size);
 199         ring->free_tx_desc = mlx4_en_free_tx_desc;
 200
 201         ring->sp_qp_state = MLX4_QP_STATE_RST;
 202         ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8);
 203         ring->mr_key = cpu_to_be32(mdev->mr.key);
 204
 205         mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn,
 206                                 ring->sp_cqn, user_prio, &ring->sp_context);
 207         if (ring->bf_alloced)
 208                 ring->sp_context.usr_page =
 209                         cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev,
 210                                                          ring->bf.uar->index));
 211
 212         err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context,
 213                                &ring->sp_qp, &ring->sp_qp_state);
 214         if (!cpumask_empty(&ring->sp_affinity_mask))
 215                 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask,
 216                                     ring->queue_index);
 217
 218         return err;
 219 }
 220
 221 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 222                                 struct mlx4_en_tx_ring *ring)
 223 {
 224         struct mlx4_en_dev *mdev = priv->mdev;
 225
 226         mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state,
 227                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp);
 228 }
 229
 230 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
 231 {
 232         return ring->prod - ring->cons > ring->full_size;
 233 }
 234
 235 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
 236                               struct mlx4_en_tx_ring *ring, int index,
 237                               u8 owner)
 238 {
 239         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 240         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 241         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 242         void *end = ring->buf + ring->buf_size;
 243         __be32 *ptr = (__be32 *)tx_desc;
 244         int i;
 245
 246         /* Optimize the common case when there are no wraparounds */
 247         if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 248                 /* Stamp the freed descriptor */
 249                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 250                      i += STAMP_STRIDE) {
 251                         *ptr = stamp;
 252                         ptr += STAMP_DWORDS;
 253                 }
 254         } else {
 255                 /* Stamp the freed descriptor */
 256                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 257                      i += STAMP_STRIDE) {
 258                         *ptr = stamp;
 259                         ptr += STAMP_DWORDS;
 260                         if ((void *)ptr >= end) {
 261                                 ptr = ring->buf;
 262                                 stamp ^= cpu_to_be32(0x80000000);
 263                         }
 264                 }
 265         }
 266 }
 267
 268
 269 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 270                          struct mlx4_en_tx_ring *ring,
 271                          int index, u8 owner, u64 timestamp,
 272                          int napi_mode)
 273 {
 274         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 275         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 276         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 277         void *end = ring->buf + ring->buf_size;
 278         struct sk_buff *skb = tx_info->skb;
 279         int nr_maps = tx_info->nr_maps;
 280         int i;
 281
 282         /* We do not touch skb here, so prefetch skb->users location
 283          * to speedup consume_skb()
 284          */
 285         prefetchw(&skb->users);
 286
 287         if (unlikely(timestamp)) {
 288                 struct skb_shared_hwtstamps hwts;
 289
 290                 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
 291                 skb_tstamp_tx(skb, &hwts);
 292         }
 293
 294         /* Optimize the common case when there are no wraparounds */
 295         if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 296                 if (!tx_info->inl) {
 297                         if (tx_info->linear)
 298                                 dma_unmap_single(priv->ddev,
 299                                                 tx_info->map0_dma,
 300                                                 tx_info->map0_byte_count,
 301                                                 PCI_DMA_TODEVICE);
 302                         else
 303                                 dma_unmap_page(priv->ddev,
 304                                                tx_info->map0_dma,
 305                                                tx_info->map0_byte_count,
 306                                                PCI_DMA_TODEVICE);
 307                         for (i = 1; i < nr_maps; i++) {
 308                                 data++;
 309                                 dma_unmap_page(priv->ddev,
 310                                         (dma_addr_t)be64_to_cpu(data->addr),
 311                                         be32_to_cpu(data->byte_count),
 312                                         PCI_DMA_TODEVICE);
 313                         }
 314                 }
 315         } else {
 316                 if (!tx_info->inl) {
 317                         if ((void *) data >= end) {
 318                                 data = ring->buf + ((void *)data - end);
 319                         }
 320
 321                         if (tx_info->linear)
 322                                 dma_unmap_single(priv->ddev,
 323                                                 tx_info->map0_dma,
 324                                                 tx_info->map0_byte_count,
 325                                                 PCI_DMA_TODEVICE);
 326                         else
 327                                 dma_unmap_page(priv->ddev,
 328                                                tx_info->map0_dma,
 329                                                tx_info->map0_byte_count,
 330                                                PCI_DMA_TODEVICE);
 331                         for (i = 1; i < nr_maps; i++) {
 332                                 data++;
 333                                 /* Check for wraparound before unmapping */
 334                                 if ((void *) data >= end)
 335                                         data = ring->buf;
 336                                 dma_unmap_page(priv->ddev,
 337                                         (dma_addr_t)be64_to_cpu(data->addr),
 338                                         be32_to_cpu(data->byte_count),
 339                                         PCI_DMA_TODEVICE);
 340                         }
 341                 }
 342         }
 343         napi_consume_skb(skb, napi_mode);
 344
 345         return tx_info->nr_txbb;
 346 }
 347
 348 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
 349                             struct mlx4_en_tx_ring *ring,
 350                             int index, u8 owner, u64 timestamp,
 351                             int napi_mode)
 352 {
 353         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 354         struct mlx4_en_rx_alloc frame = {
 355                 .page = tx_info->page,
 356                 .dma = tx_info->map0_dma,
 357                 .page_offset = XDP_PACKET_HEADROOM,
 358                 .page_size = PAGE_SIZE,
 359         };
 360
 361         if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) {
 362                 dma_unmap_page(priv->ddev, tx_info->map0_dma,
 363                                PAGE_SIZE, priv->frag_info[0].dma_dir);
 364                 put_page(tx_info->page);
 365         }
 366
 367         return tx_info->nr_txbb;
 368 }
 369
 370 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 371 {
 372         struct mlx4_en_priv *priv = netdev_priv(dev);
 373         int cnt = 0;
 374
 375         /* Skip last polled descriptor */
 376         ring->cons += ring->last_nr_txbb;
 377         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 378                  ring->cons, ring->prod);
 379
 380         if ((u32) (ring->prod - ring->cons) > ring->size) {
 381                 if (netif_msg_tx_err(priv))
 382                         en_warn(priv, "Tx consumer passed producer!\n");
 383                 return 0;
 384         }
 385
 386         while (ring->cons != ring->prod) {
 387                 ring->last_nr_txbb = ring->free_tx_desc(priv, ring,
 388                                                 ring->cons & ring->size_mask,
 389                                                 !!(ring->cons & ring->size), 0,
 390                                                 0 /* Non-NAPI caller */);
 391                 ring->cons += ring->last_nr_txbb;
 392                 cnt++;
 393         }
 394
 395         if (ring->tx_queue)
 396                 netdev_tx_reset_queue(ring->tx_queue);
 397
 398         if (cnt)
 399                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 400
 401         return cnt;
 402 }
 403
 404 static bool mlx4_en_process_tx_cq(struct net_device *dev,
 405                                   struct mlx4_en_cq *cq, int napi_budget)
 406 {
 407         struct mlx4_en_priv *priv = netdev_priv(dev);
 408         struct mlx4_cq *mcq = &cq->mcq;
 409         struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring];
 410         struct mlx4_cqe *cqe;
 411         u16 index;
 412         u16 new_index, ring_index, stamp_index;
 413         u32 txbbs_skipped = 0;
 414         u32 txbbs_stamp = 0;
 415         u32 cons_index = mcq->cons_index;
 416         int size = cq->size;
 417         u32 size_mask = ring->size_mask;
 418         struct mlx4_cqe *buf = cq->buf;
 419         u32 packets = 0;
 420         u32 bytes = 0;
 421         int factor = priv->cqe_factor;
 422         int done = 0;
 423         int budget = priv->tx_work_limit;
 424         u32 last_nr_txbb;
 425         u32 ring_cons;
 426
 427         if (!priv->port_up)
 428                 return true;
 429
 430         netdev_txq_bql_complete_prefetchw(ring->tx_queue);
 431
 432         index = cons_index & size_mask;
 433         cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 434         last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
 435         ring_cons = ACCESS_ONCE(ring->cons);
 436         ring_index = ring_cons & size_mask;
 437         stamp_index = ring_index;
 438
 439         /* Process all completed CQEs */
 440         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 441                         cons_index & size) && (done < budget)) {
 442                 /*
 443                  * make sure we read the CQE after we read the
 444                  * ownership bit
 445                  */
 446                 dma_rmb();
 447
 448                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 449                              MLX4_CQE_OPCODE_ERROR)) {
 450                         struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
 451
 452                         en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
 453                                cqe_err->vendor_err_syndrome,
 454                                cqe_err->syndrome);
 455                 }
 456
 457                 /* Skip over last polled CQE */
 458                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 459
 460                 do {
 461                         u64 timestamp = 0;
 462
 463                         txbbs_skipped += last_nr_txbb;
 464                         ring_index = (ring_index + last_nr_txbb) & size_mask;
 465
 466                         if (unlikely(ring->tx_info[ring_index].ts_requested))
 467                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 468
 469                         /* free next descriptor */
 470                         last_nr_txbb = ring->free_tx_desc(
 471                                         priv, ring, ring_index,
 472                                         !!((ring_cons + txbbs_skipped) &
 473                                         ring->size), timestamp, napi_budget);
 474
 475                         mlx4_en_stamp_wqe(priv, ring, stamp_index,
 476                                           !!((ring_cons + txbbs_stamp) &
 477                                                 ring->size));
 478                         stamp_index = ring_index;
 479                         txbbs_stamp = txbbs_skipped;
 480                         packets++;
 481                         bytes += ring->tx_info[ring_index].nr_bytes;
 482                 } while ((++done < budget) && (ring_index != new_index));
 483
 484                 ++cons_index;
 485                 index = cons_index & size_mask;
 486                 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 487         }
 488
 489
 490         /*
 491          * To prevent CQ overflow we first update CQ consumer and only then
 492          * the ring consumer.
 493          */
 494         mcq->cons_index = cons_index;
 495         mlx4_cq_set_ci(mcq);
 496         wmb();
 497
 498         /* we want to dirty this cache line once */
 499         ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
 500         ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
 501
 502         if (ring->free_tx_desc == mlx4_en_recycle_tx_desc)
 503                 return done < budget;
 504
 505         netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 506
 507         /* Wakeup Tx queue if this stopped, and ring is not full.
 508          */
 509         if (netif_tx_queue_stopped(ring->tx_queue) &&
 510             !mlx4_en_is_tx_ring_full(ring)) {
 511                 netif_tx_wake_queue(ring->tx_queue);
 512                 ring->wake_queue++;
 513         }
 514         return done < budget;
 515 }
 516
 517 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 518 {
 519         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 520         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 521
 522         if (likely(priv->port_up))
 523                 napi_schedule_irqoff(&cq->napi);
 524         else
 525                 mlx4_en_arm_cq(priv, cq);
 526 }
 527
 528 /* TX CQ polling - called by NAPI */
 529 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
 530 {
 531         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 532         struct net_device *dev = cq->dev;
 533         struct mlx4_en_priv *priv = netdev_priv(dev);
 534         int clean_complete;
 535
 536         clean_complete = mlx4_en_process_tx_cq(dev, cq, budget);
 537         if (!clean_complete)
 538                 return budget;
 539
 540         napi_complete(napi);
 541         mlx4_en_arm_cq(priv, cq);
 542
 543         return 0;
 544 }
 545
 546 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 547                                                       struct mlx4_en_tx_ring *ring,
 548                                                       u32 index,
 549                                                       unsigned int desc_size)
 550 {
 551         u32 copy = (ring->size - index) * TXBB_SIZE;
 552         int i;
 553
 554         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 555                 if ((i & (TXBB_SIZE - 1)) == 0)
 556                         wmb();
 557
 558                 *((u32 *) (ring->buf + i)) =
 559                         *((u32 *) (ring->bounce_buf + copy + i));
 560         }
 561
 562         for (i = copy - 4; i >= 4 ; i -= 4) {
 563                 if ((i & (TXBB_SIZE - 1)) == 0)
 564                         wmb();
 565
 566                 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
 567                         *((u32 *) (ring->bounce_buf + i));
 568         }
 569
 570         /* Return real descriptor location */
 571         return ring->buf + index * TXBB_SIZE;
 572 }
 573
 574 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
 575  *
 576  * It seems strange we do not simply use skb_copy_bits().
 577  * This would allow to inline all skbs iff skb->len <= inline_thold
 578  *
 579  * Note that caller already checked skb was not a gso packet
 580  */
 581 static bool is_inline(int inline_thold, const struct sk_buff *skb,
 582                       const struct skb_shared_info *shinfo,
 583                       void **pfrag)
 584 {
 585         void *ptr;
 586
 587         if (skb->len > inline_thold || !inline_thold)
 588                 return false;
 589
 590         if (shinfo->nr_frags == 1) {
 591                 ptr = skb_frag_address_safe(&shinfo->frags[0]);
 592                 if (unlikely(!ptr))
 593                         return false;
 594                 *pfrag = ptr;
 595                 return true;
 596         }
 597         if (shinfo->nr_frags)
 598                 return false;
 599         return true;
 600 }
 601
 602 static int inline_size(const struct sk_buff *skb)
 603 {
 604         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 605             <= MLX4_INLINE_ALIGN)
 606                 return ALIGN(skb->len + CTRL_SIZE +
 607                              sizeof(struct mlx4_wqe_inline_seg), 16);
 608         else
 609                 return ALIGN(skb->len + CTRL_SIZE + 2 *
 610                              sizeof(struct mlx4_wqe_inline_seg), 16);
 611 }
 612
 613 static int get_real_size(const struct sk_buff *skb,
 614                          const struct skb_shared_info *shinfo,
 615                          struct net_device *dev,
 616                          int *lso_header_size,
 617                          bool *inline_ok,
 618                          void **pfrag)
 619 {
 620         struct mlx4_en_priv *priv = netdev_priv(dev);
 621         int real_size;
 622
 623         if (shinfo->gso_size) {
 624                 *inline_ok = false;
 625                 if (skb->encapsulation)
 626                         *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
 627                 else
 628                         *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 629                 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
 630                         ALIGN(*lso_header_size + 4, DS_SIZE);
 631                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
 632                         /* We add a segment for the skb linear buffer only if
 633                          * it contains data */
 634                         if (*lso_header_size < skb_headlen(skb))
 635                                 real_size += DS_SIZE;
 636                         else {
 637                                 if (netif_msg_tx_err(priv))
 638                                         en_warn(priv, "Non-linear headers\n");
 639                                 return 0;
 640                         }
 641                 }
 642         } else {
 643                 *lso_header_size = 0;
 644                 *inline_ok = is_inline(priv->prof->inline_thold, skb,
 645                                        shinfo, pfrag);
 646
 647                 if (*inline_ok)
 648                         real_size = inline_size(skb);
 649                 else
 650                         real_size = CTRL_SIZE +
 651                                     (shinfo->nr_frags + 1) * DS_SIZE;
 652         }
 653
 654         return real_size;
 655 }
 656
 657 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
 658                              const struct sk_buff *skb,
 659                              const struct skb_shared_info *shinfo,
 660                              void *fragptr)
 661 {
 662         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 663         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
 664         unsigned int hlen = skb_headlen(skb);
 665
 666         if (skb->len <= spc) {
 667                 if (likely(skb->len >= MIN_PKT_LEN)) {
 668                         inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 669                 } else {
 670                         inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
 671                         memset(((void *)(inl + 1)) + skb->len, 0,
 672                                MIN_PKT_LEN - skb->len);
 673                 }
 674                 skb_copy_from_linear_data(skb, inl + 1, hlen);
 675                 if (shinfo->nr_frags)
 676                         memcpy(((void *)(inl + 1)) + hlen, fragptr,
 677                                skb_frag_size(&shinfo->frags[0]));
 678
 679         } else {
 680                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
 681                 if (hlen <= spc) {
 682                         skb_copy_from_linear_data(skb, inl + 1, hlen);
 683                         if (hlen < spc) {
 684                                 memcpy(((void *)(inl + 1)) + hlen,
 685                                        fragptr, spc - hlen);
 686                                 fragptr +=  spc - hlen;
 687                         }
 688                         inl = (void *) (inl + 1) + spc;
 689                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 690                 } else {
 691                         skb_copy_from_linear_data(skb, inl + 1, spc);
 692                         inl = (void *) (inl + 1) + spc;
 693                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 694                                                          hlen - spc);
 695                         if (shinfo->nr_frags)
 696                                 memcpy(((void *)(inl + 1)) + hlen - spc,
 697                                        fragptr,
 698                                        skb_frag_size(&shinfo->frags[0]));
 699                 }
 700
 701                 dma_wmb();
 702                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 703         }
 704 }
 705
 706 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 707                          void *accel_priv, select_queue_fallback_t fallback)
 708 {
 709         struct mlx4_en_priv *priv = netdev_priv(dev);
 710         u16 rings_p_up = priv->num_tx_rings_p_up;
 711         u8 up = 0;
 712
 713         if (netdev_get_num_tc(dev))
 714                 return skb_tx_hash(dev, skb);
 715
 716         if (skb_vlan_tag_present(skb))
 717                 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT;
 718
 719         return fallback(dev, skb) % rings_p_up + up * rings_p_up;
 720 }
 721
 722 static void mlx4_bf_copy(void __iomem *dst, const void *src,
 723                          unsigned int bytecnt)
 724 {
 725         __iowrite64_copy(dst, src, bytecnt / 8);
 726 }
 727
 728 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring)
 729 {
 730         wmb();
 731         /* Since there is no iowrite*_native() that writes the
 732          * value as is, without byteswapping - using the one
 733          * the doesn't do byteswapping in the relevant arch
 734          * endianness.
 735          */
 736 #if defined(__LITTLE_ENDIAN)
 737         iowrite32(
 738 #else
 739         iowrite32be(
 740 #endif
 741                   ring->doorbell_qpn,
 742                   ring->bf.uar->map + MLX4_SEND_DOORBELL);
 743 }
 744
 745 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring,
 746                                   struct mlx4_en_tx_desc *tx_desc,
 747                                   union mlx4_wqe_qpn_vlan qpn_vlan,
 748                                   int desc_size, int bf_index,
 749                                   __be32 op_own, bool bf_ok,
 750                                   bool send_doorbell)
 751 {
 752         tx_desc->ctrl.qpn_vlan = qpn_vlan;
 753
 754         if (bf_ok) {
 755                 op_own |= htonl((bf_index & 0xffff) << 8);
 756                 /* Ensure new descriptor hits memory
 757                  * before setting ownership of this descriptor to HW
 758                  */
 759                 dma_wmb();
 760                 tx_desc->ctrl.owner_opcode = op_own;
 761
 762                 wmb();
 763
 764                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
 765                              desc_size);
 766
 767                 wmb();
 768
 769                 ring->bf.offset ^= ring->bf.buf_size;
 770         } else {
 771                 /* Ensure new descriptor hits memory
 772                  * before setting ownership of this descriptor to HW
 773                  */
 774                 dma_wmb();
 775                 tx_desc->ctrl.owner_opcode = op_own;
 776                 if (send_doorbell)
 777                         mlx4_en_xmit_doorbell(ring);
 778                 else
 779                         ring->xmit_more++;
 780         }
 781 }
 782
 783 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 784 {
 785         struct skb_shared_info *shinfo = skb_shinfo(skb);
 786         struct mlx4_en_priv *priv = netdev_priv(dev);
 787         union mlx4_wqe_qpn_vlan qpn_vlan = {};
 788         struct device *ddev = priv->ddev;
 789         struct mlx4_en_tx_ring *ring;
 790         struct mlx4_en_tx_desc *tx_desc;
 791         struct mlx4_wqe_data_seg *data;
 792         struct mlx4_en_tx_info *tx_info;
 793         int tx_ind = 0;
 794         int nr_txbb;
 795         int desc_size;
 796         int real_size;
 797         u32 index, bf_index;
 798         __be32 op_own;
 799         u16 vlan_proto = 0;
 800         int i_frag;
 801         int lso_header_size;
 802         void *fragptr = NULL;
 803         bool bounce = false;
 804         bool send_doorbell;
 805         bool stop_queue;
 806         bool inline_ok;
 807         u32 ring_cons;
 808         bool bf_ok;
 809
 810         tx_ind = skb_get_queue_mapping(skb);
 811         ring = priv->tx_ring[TX][tx_ind];
 812
 813         if (!priv->port_up)
 814                 goto tx_drop;
 815
 816         /* fetch ring->cons far ahead before needing it to avoid stall */
 817         ring_cons = ACCESS_ONCE(ring->cons);
 818
 819         real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
 820                                   &inline_ok, &fragptr);
 821         if (unlikely(!real_size))
 822                 goto tx_drop_count;
 823
 824         /* Align descriptor to TXBB size */
 825         desc_size = ALIGN(real_size, TXBB_SIZE);
 826         nr_txbb = desc_size / TXBB_SIZE;
 827         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 828                 if (netif_msg_tx_err(priv))
 829                         en_warn(priv, "Oversized header or SG list\n");
 830                 goto tx_drop_count;
 831         }
 832
 833         bf_ok = ring->bf_enabled;
 834         if (skb_vlan_tag_present(skb)) {
 835                 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb));
 836                 vlan_proto = be16_to_cpu(skb->vlan_proto);
 837                 if (vlan_proto == ETH_P_8021AD)
 838                         qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
 839                 else if (vlan_proto == ETH_P_8021Q)
 840                         qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
 841                 else
 842                         qpn_vlan.ins_vlan = 0;
 843                 bf_ok = false;
 844         }
 845
 846         netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
 847
 848         /* Track current inflight packets for performance analysis */
 849         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 850                          (u32)(ring->prod - ring_cons - 1));
 851
 852         /* Packet is good - grab an index and transmit it */
 853         index = ring->prod & ring->size_mask;
 854         bf_index = ring->prod;
 855
 856         /* See if we have enough space for whole descriptor TXBB for setting
 857          * SW ownership on next descriptor; if not, use a bounce buffer. */
 858         if (likely(index + nr_txbb <= ring->size))
 859                 tx_desc = ring->buf + index * TXBB_SIZE;
 860         else {
 861                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 862                 bounce = true;
 863                 bf_ok = false;
 864         }
 865
 866         /* Save skb in tx_info ring */
 867         tx_info = &ring->tx_info[index];
 868         tx_info->skb = skb;
 869         tx_info->nr_txbb = nr_txbb;
 870
 871         data = &tx_desc->data;
 872         if (lso_header_size)
 873                 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
 874                                                       DS_SIZE));
 875
 876         /* valid only for none inline segments */
 877         tx_info->data_offset = (void *)data - (void *)tx_desc;
 878
 879         tx_info->inl = inline_ok;
 880
 881         tx_info->linear = (lso_header_size < skb_headlen(skb) &&
 882                            !inline_ok) ? 1 : 0;
 883
 884         tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
 885         data += tx_info->nr_maps - 1;
 886
 887         if (!tx_info->inl) {
 888                 dma_addr_t dma = 0;
 889                 u32 byte_count = 0;
 890
 891                 /* Map fragments if any */
 892                 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
 893                         const struct skb_frag_struct *frag;
 894
 895                         frag = &shinfo->frags[i_frag];
 896                         byte_count = skb_frag_size(frag);
 897                         dma = skb_frag_dma_map(ddev, frag,
 898                                                0, byte_count,
 899                                                DMA_TO_DEVICE);
 900                         if (dma_mapping_error(ddev, dma))
 901                                 goto tx_drop_unmap;
 902
 903                         data->addr = cpu_to_be64(dma);
 904                         data->lkey = ring->mr_key;
 905                         dma_wmb();
 906                         data->byte_count = cpu_to_be32(byte_count);
 907                         --data;
 908                 }
 909
 910                 /* Map linear part if needed */
 911                 if (tx_info->linear) {
 912                         byte_count = skb_headlen(skb) - lso_header_size;
 913
 914                         dma = dma_map_single(ddev, skb->data +
 915                                              lso_header_size, byte_count,
 916                                              PCI_DMA_TODEVICE);
 917                         if (dma_mapping_error(ddev, dma))
 918                                 goto tx_drop_unmap;
 919
 920                         data->addr = cpu_to_be64(dma);
 921                         data->lkey = ring->mr_key;
 922                         dma_wmb();
 923                         data->byte_count = cpu_to_be32(byte_count);
 924                 }
 925                 /* tx completion can avoid cache line miss for common cases */
 926                 tx_info->map0_dma = dma;
 927                 tx_info->map0_byte_count = byte_count;
 928         }
 929
 930         /*
 931          * For timestamping add flag to skb_shinfo and
 932          * set flag for further reference
 933          */
 934         tx_info->ts_requested = 0;
 935         if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
 936                      shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
 937                 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
 938                 tx_info->ts_requested = 1;
 939         }
 940
 941         /* Prepare ctrl segement apart opcode+ownership, which depends on
 942          * whether LSO is used */
 943         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 944         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 945                 if (!skb->encapsulation)
 946                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 947                                                                  MLX4_WQE_CTRL_TCP_UDP_CSUM);
 948                 else
 949                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
 950                 ring->tx_csum++;
 951         }
 952
 953         if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
 954                 struct ethhdr *ethh;
 955
 956                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
 957                  * so that VFs and PF can communicate with each other
 958                  */
 959                 ethh = (struct ethhdr *)skb->data;
 960                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
 961                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
 962         }
 963
 964         /* Handle LSO (TSO) packets */
 965         if (lso_header_size) {
 966                 int i;
 967
 968                 /* Mark opcode as LSO */
 969                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
 970                         ((ring->prod & ring->size) ?
 971                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 972
 973                 /* Fill in the LSO prefix */
 974                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
 975                         shinfo->gso_size << 16 | lso_header_size);
 976
 977                 /* Copy headers;
 978                  * note that we already verified that it is linear */
 979                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
 980
 981                 ring->tso_packets++;
 982
 983                 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
 984                         !!((skb->len - lso_header_size) % shinfo->gso_size);
 985                 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
 986                 ring->packets += i;
 987         } else {
 988                 /* Normal (Non LSO) packet */
 989                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
 990                         ((ring->prod & ring->size) ?
 991                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 992                 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
 993                 ring->packets++;
 994         }
 995         ring->bytes += tx_info->nr_bytes;
 996         netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
 997         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
 998
 999         if (tx_info->inl)
1000                 build_inline_wqe(tx_desc, skb, shinfo, fragptr);
1001
1002         if (skb->encapsulation) {
1003                 union {
1004                         struct iphdr *v4;
1005                         struct ipv6hdr *v6;
1006                         unsigned char *hdr;
1007                 } ip;
1008                 u8 proto;
1009
1010                 ip.hdr = skb_inner_network_header(skb);
1011                 proto = (ip.v4->version == 4) ? ip.v4->protocol :
1012                                                 ip.v6->nexthdr;
1013
1014                 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP)
1015                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
1016                 else
1017                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
1018         }
1019
1020         ring->prod += nr_txbb;
1021
1022         /* If we used a bounce buffer then copy descriptor back into place */
1023         if (unlikely(bounce))
1024                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
1025
1026         skb_tx_timestamp(skb);
1027
1028         /* Check available TXBBs And 2K spare for prefetch */
1029         stop_queue = mlx4_en_is_tx_ring_full(ring);
1030         if (unlikely(stop_queue)) {
1031                 netif_tx_stop_queue(ring->tx_queue);
1032                 ring->queue_stopped++;
1033         }
1034         send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
1035
1036         real_size = (real_size / 16) & 0x3f;
1037
1038         bf_ok &= desc_size <= MAX_BF && send_doorbell;
1039
1040         if (bf_ok)
1041                 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size);
1042         else
1043                 qpn_vlan.fence_size = real_size;
1044
1045         mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index,
1046                               op_own, bf_ok, send_doorbell);
1047
1048         if (unlikely(stop_queue)) {
1049                 /* If queue was emptied after the if (stop_queue) , and before
1050                  * the netif_tx_stop_queue() - need to wake the queue,
1051                  * or else it will remain stopped forever.
1052                  * Need a memory barrier to make sure ring->cons was not
1053                  * updated before queue was stopped.
1054                  */
1055                 smp_rmb();
1056
1057                 ring_cons = ACCESS_ONCE(ring->cons);
1058                 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1059                         netif_tx_wake_queue(ring->tx_queue);
1060                         ring->wake_queue++;
1061                 }
1062         }
1063         return NETDEV_TX_OK;
1064
1065 tx_drop_unmap:
1066         en_err(priv, "DMA mapping error\n");
1067
1068         while (++i_frag < shinfo->nr_frags) {
1069                 ++data;
1070                 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
1071                                be32_to_cpu(data->byte_count),
1072                                PCI_DMA_TODEVICE);
1073         }
1074
1075 tx_drop_count:
1076         ring->tx_dropped++;
1077 tx_drop:
1078         dev_kfree_skb_any(skb);
1079         return NETDEV_TX_OK;
1080 }
1081
1082 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
1083                                struct mlx4_en_rx_alloc *frame,
1084                                struct net_device *dev, unsigned int length,
1085                                int tx_ind, int *doorbell_pending)
1086 {
1087         struct mlx4_en_priv *priv = netdev_priv(dev);
1088         union mlx4_wqe_qpn_vlan qpn_vlan = {};
1089         struct mlx4_en_tx_ring *ring;
1090         struct mlx4_en_tx_desc *tx_desc;
1091         struct mlx4_wqe_data_seg *data;
1092         struct mlx4_en_tx_info *tx_info;
1093         int index, bf_index;
1094         bool send_doorbell;
1095         int nr_txbb = 1;
1096         bool stop_queue;
1097         dma_addr_t dma;
1098         int real_size;
1099         __be32 op_own;
1100         u32 ring_cons;
1101         bool bf_ok;
1102
1103         BUILD_BUG_ON_MSG(ALIGN(CTRL_SIZE + DS_SIZE, TXBB_SIZE) != TXBB_SIZE,
1104                          "mlx4_en_xmit_frame requires minimum size tx desc");
1105
1106         ring = priv->tx_ring[TX_XDP][tx_ind];
1107
1108         if (!priv->port_up)
1109                 goto tx_drop;
1110
1111         if (mlx4_en_is_tx_ring_full(ring))
1112                 goto tx_drop_count;
1113
1114         /* fetch ring->cons far ahead before needing it to avoid stall */
1115         ring_cons = READ_ONCE(ring->cons);
1116
1117         index = ring->prod & ring->size_mask;
1118         tx_info = &ring->tx_info[index];
1119
1120         bf_ok = ring->bf_enabled;
1121
1122         /* Track current inflight packets for performance analysis */
1123         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
1124                          (u32)(ring->prod - ring_cons - 1));
1125
1126         bf_index = ring->prod;
1127         tx_desc = ring->buf + index * TXBB_SIZE;
1128         data = &tx_desc->data;
1129
1130         dma = frame->dma;
1131
1132         tx_info->page = frame->page;
1133         frame->page = NULL;
1134         tx_info->map0_dma = dma;
1135         tx_info->map0_byte_count = PAGE_SIZE;
1136         tx_info->nr_txbb = nr_txbb;
1137         tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN);
1138         tx_info->data_offset = (void *)data - (void *)tx_desc;
1139         tx_info->ts_requested = 0;
1140         tx_info->nr_maps = 1;
1141         tx_info->linear = 1;
1142         tx_info->inl = 0;
1143
1144         dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset,
1145                                          length, PCI_DMA_TODEVICE);
1146
1147         data->addr = cpu_to_be64(dma + frame->page_offset);
1148         data->lkey = ring->mr_key;
1149         dma_wmb();
1150         data->byte_count = cpu_to_be32(length);
1151
1152         /* tx completion can avoid cache line miss for common cases */
1153         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
1154
1155         op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1156                 ((ring->prod & ring->size) ?
1157                  cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1158
1159         rx_ring->xdp_tx++;
1160         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length);
1161
1162         ring->prod += nr_txbb;
1163
1164         stop_queue = mlx4_en_is_tx_ring_full(ring);
1165         send_doorbell = stop_queue ||
1166                                 *doorbell_pending > MLX4_EN_DOORBELL_BUDGET;
1167         bf_ok &= send_doorbell;
1168
1169         real_size = ((CTRL_SIZE + nr_txbb * DS_SIZE) / 16) & 0x3f;
1170
1171         if (bf_ok)
1172                 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size);
1173         else
1174                 qpn_vlan.fence_size = real_size;
1175
1176         mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, TXBB_SIZE, bf_index,
1177                               op_own, bf_ok, send_doorbell);
1178         *doorbell_pending = send_doorbell ? 0 : *doorbell_pending + 1;
1179
1180         return NETDEV_TX_OK;
1181
1182 tx_drop_count:
1183         rx_ring->xdp_tx_full++;
1184 tx_drop:
1185         return NETDEV_TX_BUSY;
1186 }