drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/rculist.h>
  40 #include <linux/if_ether.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/irq.h>
  44
  45 #if IS_ENABLED(CONFIG_IPV6)
  46 #include <net/ip6_checksum.h>
  47 #endif
  48
  49 #include "mlx4_en.h"
  50
  51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  52                             struct mlx4_en_rx_alloc *page_alloc,
  53                             const struct mlx4_en_frag_info *frag_info,
  54                             gfp_t _gfp)
  55 {
  56         int order;
  57         struct page *page;
  58         dma_addr_t dma;
  59
  60         for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
  61                 gfp_t gfp = _gfp;
  62
  63                 if (order)
  64                         gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
  65                 page = alloc_pages(gfp, order);
  66                 if (likely(page))
  67                         break;
  68                 if (--order < 0 ||
  69                     ((PAGE_SIZE << order) < frag_info->frag_size))
  70                         return -ENOMEM;
  71         }
  72         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  73                            PCI_DMA_FROMDEVICE);
  74         if (dma_mapping_error(priv->ddev, dma)) {
  75                 put_page(page);
  76                 return -ENOMEM;
  77         }
  78         page_alloc->page_size = PAGE_SIZE << order;
  79         page_alloc->page = page;
  80         page_alloc->dma = dma;
  81         page_alloc->page_offset = 0;
  82         /* Not doing get_page() for each frag is a big win
  83          * on asymetric workloads. Note we can not use atomic_set().
  84          */
  85         page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
  86         return 0;
  87 }
  88
  89 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  90                                struct mlx4_en_rx_desc *rx_desc,
  91                                struct mlx4_en_rx_alloc *frags,
  92                                struct mlx4_en_rx_alloc *ring_alloc,
  93                                gfp_t gfp)
  94 {
  95         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  96         const struct mlx4_en_frag_info *frag_info;
  97         struct page *page;
  98         dma_addr_t dma;
  99         int i;
 100
 101         for (i = 0; i < priv->num_frags; i++) {
 102                 frag_info = &priv->frag_info[i];
 103                 page_alloc[i] = ring_alloc[i];
 104                 page_alloc[i].page_offset += frag_info->frag_stride;
 105
 106                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 107                     ring_alloc[i].page_size)
 108                         continue;
 109
 110                 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
 111                         goto out;
 112         }
 113
 114         for (i = 0; i < priv->num_frags; i++) {
 115                 frags[i] = ring_alloc[i];
 116                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
 117                 ring_alloc[i] = page_alloc[i];
 118                 rx_desc->data[i].addr = cpu_to_be64(dma);
 119         }
 120
 121         return 0;
 122
 123 out:
 124         while (i--) {
 125                 if (page_alloc[i].page != ring_alloc[i].page) {
 126                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 127                                 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
 128                         page = page_alloc[i].page;
 129                         /* Revert changes done by mlx4_alloc_pages */
 130                         page_ref_sub(page, page_alloc[i].page_size /
 131                                            priv->frag_info[i].frag_stride - 1);
 132                         put_page(page);
 133                 }
 134         }
 135         return -ENOMEM;
 136 }
 137
 138 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 139                               struct mlx4_en_rx_alloc *frags,
 140                               int i)
 141 {
 142         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 143         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 144
 145
 146         if (next_frag_end > frags[i].page_size)
 147                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 148                                PCI_DMA_FROMDEVICE);
 149
 150         if (frags[i].page)
 151                 put_page(frags[i].page);
 152 }
 153
 154 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 155                                   struct mlx4_en_rx_ring *ring)
 156 {
 157         int i;
 158         struct mlx4_en_rx_alloc *page_alloc;
 159
 160         for (i = 0; i < priv->num_frags; i++) {
 161                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 162
 163                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 164                                      frag_info, GFP_KERNEL | __GFP_COLD))
 165                         goto out;
 166
 167                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 168                        i, ring->page_alloc[i].page_size,
 169                        page_ref_count(ring->page_alloc[i].page));
 170         }
 171         return 0;
 172
 173 out:
 174         while (i--) {
 175                 struct page *page;
 176
 177                 page_alloc = &ring->page_alloc[i];
 178                 dma_unmap_page(priv->ddev, page_alloc->dma,
 179                                page_alloc->page_size, PCI_DMA_FROMDEVICE);
 180                 page = page_alloc->page;
 181                 /* Revert changes done by mlx4_alloc_pages */
 182                 page_ref_sub(page, page_alloc->page_size /
 183                                    priv->frag_info[i].frag_stride - 1);
 184                 put_page(page);
 185                 page_alloc->page = NULL;
 186         }
 187         return -ENOMEM;
 188 }
 189
 190 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 191                                       struct mlx4_en_rx_ring *ring)
 192 {
 193         struct mlx4_en_rx_alloc *page_alloc;
 194         int i;
 195
 196         for (i = 0; i < priv->num_frags; i++) {
 197                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 198
 199                 page_alloc = &ring->page_alloc[i];
 200                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 201                        i, page_count(page_alloc->page));
 202
 203                 dma_unmap_page(priv->ddev, page_alloc->dma,
 204                                 page_alloc->page_size, PCI_DMA_FROMDEVICE);
 205                 while (page_alloc->page_offset + frag_info->frag_stride <
 206                        page_alloc->page_size) {
 207                         put_page(page_alloc->page);
 208                         page_alloc->page_offset += frag_info->frag_stride;
 209                 }
 210                 page_alloc->page = NULL;
 211         }
 212 }
 213
 214 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 215                                  struct mlx4_en_rx_ring *ring, int index)
 216 {
 217         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 218         int possible_frags;
 219         int i;
 220
 221         /* Set size and memtype fields */
 222         for (i = 0; i < priv->num_frags; i++) {
 223                 rx_desc->data[i].byte_count =
 224                         cpu_to_be32(priv->frag_info[i].frag_size);
 225                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 226         }
 227
 228         /* If the number of used fragments does not fill up the ring stride,
 229          * remaining (unused) fragments must be padded with null address/size
 230          * and a special memory key */
 231         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 232         for (i = priv->num_frags; i < possible_frags; i++) {
 233                 rx_desc->data[i].byte_count = 0;
 234                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 235                 rx_desc->data[i].addr = 0;
 236         }
 237 }
 238
 239 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 240                                    struct mlx4_en_rx_ring *ring, int index,
 241                                    gfp_t gfp)
 242 {
 243         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 244         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 245                                         (index << priv->log_rx_info);
 246
 247         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 248 }
 249
 250 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 251 {
 252         return ring->prod == ring->cons;
 253 }
 254
 255 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 256 {
 257         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 258 }
 259
 260 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 261                                  struct mlx4_en_rx_ring *ring,
 262                                  int index)
 263 {
 264         struct mlx4_en_rx_alloc *frags;
 265         int nr;
 266
 267         frags = ring->rx_info + (index << priv->log_rx_info);
 268         for (nr = 0; nr < priv->num_frags; nr++) {
 269                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 270                 mlx4_en_free_frag(priv, frags, nr);
 271         }
 272 }
 273
 274 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 275 {
 276         struct mlx4_en_rx_ring *ring;
 277         int ring_ind;
 278         int buf_ind;
 279         int new_size;
 280
 281         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 282                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 283                         ring = priv->rx_ring[ring_ind];
 284
 285                         if (mlx4_en_prepare_rx_desc(priv, ring,
 286                                                     ring->actual_size,
 287                                                     GFP_KERNEL | __GFP_COLD)) {
 288                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 289                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 290                                         return -ENOMEM;
 291                                 } else {
 292                                         new_size = rounddown_pow_of_two(ring->actual_size);
 293                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 294                                                 ring->actual_size, new_size);
 295                                         goto reduce_rings;
 296                                 }
 297                         }
 298                         ring->actual_size++;
 299                         ring->prod++;
 300                 }
 301         }
 302         return 0;
 303
 304 reduce_rings:
 305         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 306                 ring = priv->rx_ring[ring_ind];
 307                 while (ring->actual_size > new_size) {
 308                         ring->actual_size--;
 309                         ring->prod--;
 310                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 311                 }
 312         }
 313
 314         return 0;
 315 }
 316
 317 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 318                                 struct mlx4_en_rx_ring *ring)
 319 {
 320         int index;
 321
 322         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 323                ring->cons, ring->prod);
 324
 325         /* Unmap and free Rx buffers */
 326         while (!mlx4_en_is_ring_empty(ring)) {
 327                 index = ring->cons & ring->size_mask;
 328                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 329                 mlx4_en_free_rx_desc(priv, ring, index);
 330                 ++ring->cons;
 331         }
 332 }
 333
 334 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 335 {
 336         int i;
 337         int num_of_eqs;
 338         int num_rx_rings;
 339         struct mlx4_dev *dev = mdev->dev;
 340
 341         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 342                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 343                                    min_t(int,
 344                                          mlx4_get_eqs_per_port(mdev->dev, i),
 345                                          DEF_RX_RINGS));
 346
 347                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 348                         min_t(int, num_of_eqs,
 349                               netif_get_num_default_rss_queues());
 350                 mdev->profile.prof[i].rx_ring_num =
 351                         rounddown_pow_of_two(num_rx_rings);
 352         }
 353 }
 354
 355 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 356                            struct mlx4_en_rx_ring **pring,
 357                            u32 size, u16 stride, int node)
 358 {
 359         struct mlx4_en_dev *mdev = priv->mdev;
 360         struct mlx4_en_rx_ring *ring;
 361         int err = -ENOMEM;
 362         int tmp;
 363
 364         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 365         if (!ring) {
 366                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 367                 if (!ring) {
 368                         en_err(priv, "Failed to allocate RX ring structure\n");
 369                         return -ENOMEM;
 370                 }
 371         }
 372
 373         ring->prod = 0;
 374         ring->cons = 0;
 375         ring->size = size;
 376         ring->size_mask = size - 1;
 377         ring->stride = stride;
 378         ring->log_stride = ffs(ring->stride) - 1;
 379         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 380
 381         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 382                                         sizeof(struct mlx4_en_rx_alloc));
 383         ring->rx_info = vmalloc_node(tmp, node);
 384         if (!ring->rx_info) {
 385                 ring->rx_info = vmalloc(tmp);
 386                 if (!ring->rx_info) {
 387                         err = -ENOMEM;
 388                         goto err_ring;
 389                 }
 390         }
 391
 392         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 393                  ring->rx_info, tmp);
 394
 395         /* Allocate HW buffers on provided NUMA node */
 396         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 397         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
 398                                  ring->buf_size, 2 * PAGE_SIZE);
 399         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 400         if (err)
 401                 goto err_info;
 402
 403         err = mlx4_en_map_buffer(&ring->wqres.buf);
 404         if (err) {
 405                 en_err(priv, "Failed to map RX buffer\n");
 406                 goto err_hwq;
 407         }
 408         ring->buf = ring->wqres.buf.direct.buf;
 409
 410         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 411
 412         *pring = ring;
 413         return 0;
 414
 415 err_hwq:
 416         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 417 err_info:
 418         vfree(ring->rx_info);
 419         ring->rx_info = NULL;
 420 err_ring:
 421         kfree(ring);
 422         *pring = NULL;
 423
 424         return err;
 425 }
 426
 427 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 428 {
 429         struct mlx4_en_rx_ring *ring;
 430         int i;
 431         int ring_ind;
 432         int err;
 433         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 434                                         DS_SIZE * priv->num_frags);
 435
 436         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 437                 ring = priv->rx_ring[ring_ind];
 438
 439                 ring->prod = 0;
 440                 ring->cons = 0;
 441                 ring->actual_size = 0;
 442                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 443
 444                 ring->stride = stride;
 445                 if (ring->stride <= TXBB_SIZE)
 446                         ring->buf += TXBB_SIZE;
 447
 448                 ring->log_stride = ffs(ring->stride) - 1;
 449                 ring->buf_size = ring->size * ring->stride;
 450
 451                 memset(ring->buf, 0, ring->buf_size);
 452                 mlx4_en_update_rx_prod_db(ring);
 453
 454                 /* Initialize all descriptors */
 455                 for (i = 0; i < ring->size; i++)
 456                         mlx4_en_init_rx_desc(priv, ring, i);
 457
 458                 /* Initialize page allocators */
 459                 err = mlx4_en_init_allocator(priv, ring);
 460                 if (err) {
 461                         en_err(priv, "Failed initializing ring allocator\n");
 462                         if (ring->stride <= TXBB_SIZE)
 463                                 ring->buf -= TXBB_SIZE;
 464                         ring_ind--;
 465                         goto err_allocator;
 466                 }
 467         }
 468         err = mlx4_en_fill_rx_buffers(priv);
 469         if (err)
 470                 goto err_buffers;
 471
 472         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 473                 ring = priv->rx_ring[ring_ind];
 474
 475                 ring->size_mask = ring->actual_size - 1;
 476                 mlx4_en_update_rx_prod_db(ring);
 477         }
 478
 479         return 0;
 480
 481 err_buffers:
 482         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 483                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 484
 485         ring_ind = priv->rx_ring_num - 1;
 486 err_allocator:
 487         while (ring_ind >= 0) {
 488                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 489                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 490                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 491                 ring_ind--;
 492         }
 493         return err;
 494 }
 495
 496 /* We recover from out of memory by scheduling our napi poll
 497  * function (mlx4_en_process_cq), which tries to allocate
 498  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 499  */
 500 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 501 {
 502         int ring;
 503
 504         if (!priv->port_up)
 505                 return;
 506
 507         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 508                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
 509                         napi_reschedule(&priv->rx_cq[ring]->napi);
 510         }
 511 }
 512
 513 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 514                              struct mlx4_en_rx_ring **pring,
 515                              u32 size, u16 stride)
 516 {
 517         struct mlx4_en_dev *mdev = priv->mdev;
 518         struct mlx4_en_rx_ring *ring = *pring;
 519
 520         mlx4_en_unmap_buffer(&ring->wqres.buf);
 521         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 522         vfree(ring->rx_info);
 523         ring->rx_info = NULL;
 524         kfree(ring);
 525         *pring = NULL;
 526 #ifdef CONFIG_RFS_ACCEL
 527         mlx4_en_cleanup_filters(priv);
 528 #endif
 529 }
 530
 531 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 532                                 struct mlx4_en_rx_ring *ring)
 533 {
 534         mlx4_en_free_rx_buf(priv, ring);
 535         if (ring->stride <= TXBB_SIZE)
 536                 ring->buf -= TXBB_SIZE;
 537         mlx4_en_destroy_allocator(priv, ring);
 538 }
 539
 540
 541 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 542                                     struct mlx4_en_rx_desc *rx_desc,
 543                                     struct mlx4_en_rx_alloc *frags,
 544                                     struct sk_buff *skb,
 545                                     int length)
 546 {
 547         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 548         struct mlx4_en_frag_info *frag_info;
 549         int nr;
 550         dma_addr_t dma;
 551
 552         /* Collect used fragments while replacing them in the HW descriptors */
 553         for (nr = 0; nr < priv->num_frags; nr++) {
 554                 frag_info = &priv->frag_info[nr];
 555                 if (length <= frag_info->frag_prefix_size)
 556                         break;
 557                 if (!frags[nr].page)
 558                         goto fail;
 559
 560                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 561                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 562                                         DMA_FROM_DEVICE);
 563
 564                 /* Save page reference in skb */
 565                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 566                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 567                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 568                 skb->truesize += frag_info->frag_stride;
 569                 frags[nr].page = NULL;
 570         }
 571         /* Adjust size of last fragment to match actual length */
 572         if (nr > 0)
 573                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 574                         length - priv->frag_info[nr - 1].frag_prefix_size);
 575         return nr;
 576
 577 fail:
 578         while (nr > 0) {
 579                 nr--;
 580                 __skb_frag_unref(&skb_frags_rx[nr]);
 581         }
 582         return 0;
 583 }
 584
 585
 586 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 587                                       struct mlx4_en_rx_desc *rx_desc,
 588                                       struct mlx4_en_rx_alloc *frags,
 589                                       unsigned int length)
 590 {
 591         struct sk_buff *skb;
 592         void *va;
 593         int used_frags;
 594         dma_addr_t dma;
 595
 596         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 597         if (!skb) {
 598                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 599                 return NULL;
 600         }
 601         skb_reserve(skb, NET_IP_ALIGN);
 602         skb->len = length;
 603
 604         /* Get pointer to first fragment so we could copy the headers into the
 605          * (linear part of the) skb */
 606         va = page_address(frags[0].page) + frags[0].page_offset;
 607
 608         if (length <= SMALL_PACKET_SIZE) {
 609                 /* We are copying all relevant data to the skb - temporarily
 610                  * sync buffers for the copy */
 611                 dma = be64_to_cpu(rx_desc->data[0].addr);
 612                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 613                                         DMA_FROM_DEVICE);
 614                 skb_copy_to_linear_data(skb, va, length);
 615                 skb->tail += length;
 616         } else {
 617                 unsigned int pull_len;
 618
 619                 /* Move relevant fragments to skb */
 620                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 621                                                         skb, length);
 622                 if (unlikely(!used_frags)) {
 623                         kfree_skb(skb);
 624                         return NULL;
 625                 }
 626                 skb_shinfo(skb)->nr_frags = used_frags;
 627
 628                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 629                 /* Copy headers into the skb linear buffer */
 630                 memcpy(skb->data, va, pull_len);
 631                 skb->tail += pull_len;
 632
 633                 /* Skip headers in first fragment */
 634                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 635
 636                 /* Adjust size of first fragment */
 637                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 638                 skb->data_len = length - pull_len;
 639         }
 640         return skb;
 641 }
 642
 643 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 644 {
 645         int i;
 646         int offset = ETH_HLEN;
 647
 648         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 649                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 650                         goto out_loopback;
 651         }
 652         /* Loopback found */
 653         priv->loopback_ok = 1;
 654
 655 out_loopback:
 656         dev_kfree_skb_any(skb);
 657 }
 658
 659 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 660                                      struct mlx4_en_rx_ring *ring)
 661 {
 662         int index = ring->prod & ring->size_mask;
 663
 664         while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
 665                 if (mlx4_en_prepare_rx_desc(priv, ring, index,
 666                                             GFP_ATOMIC | __GFP_COLD))
 667                         break;
 668                 ring->prod++;
 669                 index = ring->prod & ring->size_mask;
 670         }
 671 }
 672
 673 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 674  * over it and add it to the hardware's checksum calculation
 675  */
 676 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 677                                          struct vlan_hdr *vlanh)
 678 {
 679         return csum_add(hw_checksum, *(__wsum *)vlanh);
 680 }
 681
 682 /* Although the stack expects checksum which doesn't include the pseudo
 683  * header, the HW adds it. To address that, we are subtracting the pseudo
 684  * header checksum from the checksum value provided by the HW.
 685  */
 686 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 687                                 struct iphdr *iph)
 688 {
 689         __u16 length_for_csum = 0;
 690         __wsum csum_pseudo_header = 0;
 691
 692         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 693         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 694                                                 length_for_csum, iph->protocol, 0);
 695         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 696 }
 697
 698 #if IS_ENABLED(CONFIG_IPV6)
 699 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 700  * we also compute/add the IP header checksum which
 701  * is not added by the HW.
 702  */
 703 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 704                                struct ipv6hdr *ipv6h)
 705 {
 706         __wsum csum_pseudo_hdr = 0;
 707
 708         if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
 709                 return -1;
 710         hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8));
 711
 712         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 713                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 714         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 715         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 716
 717         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 718         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 719         return 0;
 720 }
 721 #endif
 722 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 723                       netdev_features_t dev_features)
 724 {
 725         __wsum hw_checksum = 0;
 726
 727         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 728
 729         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 730
 731         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 732             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 733                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 734                 hdr += sizeof(struct vlan_hdr);
 735         }
 736
 737         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 738                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 739 #if IS_ENABLED(CONFIG_IPV6)
 740         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 741                 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
 742                         return -1;
 743 #endif
 744         return 0;
 745 }
 746
 747 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 748 {
 749         struct mlx4_en_priv *priv = netdev_priv(dev);
 750         struct mlx4_en_dev *mdev = priv->mdev;
 751         struct mlx4_cqe *cqe;
 752         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 753         struct mlx4_en_rx_alloc *frags;
 754         struct mlx4_en_rx_desc *rx_desc;
 755         struct sk_buff *skb;
 756         int index;
 757         int nr;
 758         unsigned int length;
 759         int polled = 0;
 760         int ip_summed;
 761         int factor = priv->cqe_factor;
 762         u64 timestamp;
 763         bool l2_tunnel;
 764
 765         if (!priv->port_up)
 766                 return 0;
 767
 768         if (budget <= 0)
 769                 return polled;
 770
 771         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 772          * descriptor offset can be deduced from the CQE index instead of
 773          * reading 'cqe->index' */
 774         index = cq->mcq.cons_index & ring->size_mask;
 775         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 776
 777         /* Process all completed CQEs */
 778         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 779                     cq->mcq.cons_index & cq->size)) {
 780
 781                 frags = ring->rx_info + (index << priv->log_rx_info);
 782                 rx_desc = ring->buf + (index << ring->log_stride);
 783
 784                 /*
 785                  * make sure we read the CQE after we read the ownership bit
 786                  */
 787                 dma_rmb();
 788
 789                 /* Drop packet on bad receive or bad checksum */
 790                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 791                                                 MLX4_CQE_OPCODE_ERROR)) {
 792                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 793                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 794                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 795                         goto next;
 796                 }
 797                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 798                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 799                         goto next;
 800                 }
 801
 802                 /* Check if we need to drop the packet if SRIOV is not enabled
 803                  * and not performing the selftest or flb disabled
 804                  */
 805                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 806                         struct ethhdr *ethh;
 807                         dma_addr_t dma;
 808                         /* Get pointer to first fragment since we haven't
 809                          * skb yet and cast it to ethhdr struct
 810                          */
 811                         dma = be64_to_cpu(rx_desc->data[0].addr);
 812                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 813                                                 DMA_FROM_DEVICE);
 814                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 815                                                  frags[0].page_offset);
 816
 817                         if (is_multicast_ether_addr(ethh->h_dest)) {
 818                                 struct mlx4_mac_entry *entry;
 819                                 struct hlist_head *bucket;
 820                                 unsigned int mac_hash;
 821
 822                                 /* Drop the packet, since HW loopback-ed it */
 823                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 824                                 bucket = &priv->mac_hash[mac_hash];
 825                                 rcu_read_lock();
 826                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 827                                         if (ether_addr_equal_64bits(entry->mac,
 828                                                                     ethh->h_source)) {
 829                                                 rcu_read_unlock();
 830                                                 goto next;
 831                                         }
 832                                 }
 833                                 rcu_read_unlock();
 834                         }
 835                 }
 836
 837                 /*
 838                  * Packet is OK - process it.
 839                  */
 840                 length = be32_to_cpu(cqe->byte_cnt);
 841                 length -= ring->fcs_del;
 842                 ring->bytes += length;
 843                 ring->packets++;
 844                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 845                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 846
 847                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 848                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 849                                                       MLX4_CQE_STATUS_UDP)) {
 850                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 851                                     cqe->checksum == cpu_to_be16(0xffff)) {
 852                                         ip_summed = CHECKSUM_UNNECESSARY;
 853                                         ring->csum_ok++;
 854                                 } else {
 855                                         ip_summed = CHECKSUM_NONE;
 856                                         ring->csum_none++;
 857                                 }
 858                         } else {
 859                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 860                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 861                                                                MLX4_CQE_STATUS_IPV6))) {
 862                                         ip_summed = CHECKSUM_COMPLETE;
 863                                         ring->csum_complete++;
 864                                 } else {
 865                                         ip_summed = CHECKSUM_NONE;
 866                                         ring->csum_none++;
 867                                 }
 868                         }
 869                 } else {
 870                         ip_summed = CHECKSUM_NONE;
 871                         ring->csum_none++;
 872                 }
 873
 874                 /* This packet is eligible for GRO if it is:
 875                  * - DIX Ethernet (type interpretation)
 876                  * - TCP/IP (v4)
 877                  * - without IP options
 878                  * - not an IP fragment
 879                  */
 880                 if (dev->features & NETIF_F_GRO) {
 881                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 882                         if (!gro_skb)
 883                                 goto next;
 884
 885                         nr = mlx4_en_complete_rx_desc(priv,
 886                                 rx_desc, frags, gro_skb,
 887                                 length);
 888                         if (!nr)
 889                                 goto next;
 890
 891                         if (ip_summed == CHECKSUM_COMPLETE) {
 892                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 893                                 if (check_csum(cqe, gro_skb, va,
 894                                                dev->features)) {
 895                                         ip_summed = CHECKSUM_NONE;
 896                                         ring->csum_none++;
 897                                         ring->csum_complete--;
 898                                 }
 899                         }
 900
 901                         skb_shinfo(gro_skb)->nr_frags = nr;
 902                         gro_skb->len = length;
 903                         gro_skb->data_len = length;
 904                         gro_skb->ip_summed = ip_summed;
 905
 906                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 907                                 gro_skb->csum_level = 1;
 908
 909                         if ((cqe->vlan_my_qpn &
 910                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
 911                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
 912                                 u16 vid = be16_to_cpu(cqe->sl_vid);
 913
 914                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
 915                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 916                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
 917                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
 918                                 __vlan_hwaccel_put_tag(gro_skb,
 919                                                        htons(ETH_P_8021AD),
 920                                                        be16_to_cpu(cqe->sl_vid));
 921                         }
 922
 923                         if (dev->features & NETIF_F_RXHASH)
 924                                 skb_set_hash(gro_skb,
 925                                              be32_to_cpu(cqe->immed_rss_invalid),
 926                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
 927                                                 PKT_HASH_TYPE_L4 :
 928                                                 PKT_HASH_TYPE_L3);
 929
 930                         skb_record_rx_queue(gro_skb, cq->ring);
 931
 932                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 933                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 934                                 mlx4_en_fill_hwtstamps(mdev,
 935                                                        skb_hwtstamps(gro_skb),
 936                                                        timestamp);
 937                         }
 938
 939                         napi_gro_frags(&cq->napi);
 940                         goto next;
 941                 }
 942
 943                 /* GRO not possible, complete processing here */
 944                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
 945                 if (!skb) {
 946                         ring->dropped++;
 947                         goto next;
 948                 }
 949
 950                 if (unlikely(priv->validate_loopback)) {
 951                         validate_loopback(priv, skb);
 952                         goto next;
 953                 }
 954
 955                 if (ip_summed == CHECKSUM_COMPLETE) {
 956                         if (check_csum(cqe, skb, skb->data, dev->features)) {
 957                                 ip_summed = CHECKSUM_NONE;
 958                                 ring->csum_complete--;
 959                                 ring->csum_none++;
 960                         }
 961                 }
 962
 963                 skb->ip_summed = ip_summed;
 964                 skb->protocol = eth_type_trans(skb, dev);
 965                 skb_record_rx_queue(skb, cq->ring);
 966
 967                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 968                         skb->csum_level = 1;
 969
 970                 if (dev->features & NETIF_F_RXHASH)
 971                         skb_set_hash(skb,
 972                                      be32_to_cpu(cqe->immed_rss_invalid),
 973                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
 974                                         PKT_HASH_TYPE_L4 :
 975                                         PKT_HASH_TYPE_L3);
 976
 977                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
 978                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
 979                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
 980                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
 981                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
 982                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
 983                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
 984                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
 985                                                be16_to_cpu(cqe->sl_vid));
 986
 987                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
 988                         timestamp = mlx4_en_get_cqe_ts(cqe);
 989                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
 990                                                timestamp);
 991                 }
 992
 993                 napi_gro_receive(&cq->napi, skb);
 994 next:
 995                 for (nr = 0; nr < priv->num_frags; nr++)
 996                         mlx4_en_free_frag(priv, frags, nr);
 997
 998                 ++cq->mcq.cons_index;
 999                 index = (cq->mcq.cons_index) & ring->size_mask;
1000                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1001                 if (++polled == budget)
1002                         goto out;
1003         }
1004
1005 out:
1006         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1007         mlx4_cq_set_ci(&cq->mcq);
1008         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1009         ring->cons = cq->mcq.cons_index;
1010         mlx4_en_refill_rx_buffers(priv, ring);
1011         mlx4_en_update_rx_prod_db(ring);
1012         return polled;
1013 }
1014
1015
1016 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1017 {
1018         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1019         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1020
1021         if (likely(priv->port_up))
1022                 napi_schedule_irqoff(&cq->napi);
1023         else
1024                 mlx4_en_arm_cq(priv, cq);
1025 }
1026
1027 /* Rx CQ polling - called by NAPI */
1028 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1029 {
1030         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1031         struct net_device *dev = cq->dev;
1032         struct mlx4_en_priv *priv = netdev_priv(dev);
1033         int done;
1034
1035         done = mlx4_en_process_rx_cq(dev, cq, budget);
1036
1037         /* If we used up all the quota - we're probably not done yet... */
1038         if (done == budget) {
1039                 const struct cpumask *aff;
1040                 struct irq_data *idata;
1041                 int cpu_curr;
1042
1043                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1044
1045                 cpu_curr = smp_processor_id();
1046                 idata = irq_desc_get_irq_data(cq->irq_desc);
1047                 aff = irq_data_get_affinity_mask(idata);
1048
1049                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1050                         return budget;
1051
1052                 /* Current cpu is not according to smp_irq_affinity -
1053                  * probably affinity changed. need to stop this NAPI
1054                  * poll, and restart it on the right CPU
1055                  */
1056                 done = 0;
1057         }
1058         /* Done for now */
1059         napi_complete_done(napi, done);
1060         mlx4_en_arm_cq(priv, cq);
1061         return done;
1062 }
1063
1064 static const int frag_sizes[] = {
1065         FRAG_SZ0,
1066         FRAG_SZ1,
1067         FRAG_SZ2,
1068         FRAG_SZ3
1069 };
1070
1071 void mlx4_en_calc_rx_buf(struct net_device *dev)
1072 {
1073         struct mlx4_en_priv *priv = netdev_priv(dev);
1074         /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
1075          * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
1076          */
1077         int eff_mtu = dev->mtu + ETH_HLEN + (2 * VLAN_HLEN);
1078         int buf_size = 0;
1079         int i = 0;
1080
1081         while (buf_size < eff_mtu) {
1082                 priv->frag_info[i].frag_size =
1083                         (eff_mtu > buf_size + frag_sizes[i]) ?
1084                                 frag_sizes[i] : eff_mtu - buf_size;
1085                 priv->frag_info[i].frag_prefix_size = buf_size;
1086                 priv->frag_info[i].frag_stride =
1087                                 ALIGN(priv->frag_info[i].frag_size,
1088                                       SMP_CACHE_BYTES);
1089                 buf_size += priv->frag_info[i].frag_size;
1090                 i++;
1091         }
1092
1093         priv->num_frags = i;
1094         priv->rx_skb_size = eff_mtu;
1095         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1096
1097         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1098                eff_mtu, priv->num_frags);
1099         for (i = 0; i < priv->num_frags; i++) {
1100                 en_err(priv,
1101                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1102                        i,
1103                        priv->frag_info[i].frag_size,
1104                        priv->frag_info[i].frag_prefix_size,
1105                        priv->frag_info[i].frag_stride);
1106         }
1107 }
1108
1109 /* RSS related functions */
1110
1111 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1112                                  struct mlx4_en_rx_ring *ring,
1113                                  enum mlx4_qp_state *state,
1114                                  struct mlx4_qp *qp)
1115 {
1116         struct mlx4_en_dev *mdev = priv->mdev;
1117         struct mlx4_qp_context *context;
1118         int err = 0;
1119
1120         context = kmalloc(sizeof(*context), GFP_KERNEL);
1121         if (!context)
1122                 return -ENOMEM;
1123
1124         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1125         if (err) {
1126                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1127                 goto out;
1128         }
1129         qp->event = mlx4_en_sqp_event;
1130
1131         memset(context, 0, sizeof *context);
1132         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1133                                 qpn, ring->cqn, -1, context);
1134         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1135
1136         /* Cancel FCS removal if FW allows */
1137         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1138                 context->param3 |= cpu_to_be32(1 << 29);
1139                 if (priv->dev->features & NETIF_F_RXFCS)
1140                         ring->fcs_del = 0;
1141                 else
1142                         ring->fcs_del = ETH_FCS_LEN;
1143         } else
1144                 ring->fcs_del = 0;
1145
1146         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1147         if (err) {
1148                 mlx4_qp_remove(mdev->dev, qp);
1149                 mlx4_qp_free(mdev->dev, qp);
1150         }
1151         mlx4_en_update_rx_prod_db(ring);
1152 out:
1153         kfree(context);
1154         return err;
1155 }
1156
1157 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1158 {
1159         int err;
1160         u32 qpn;
1161
1162         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1163                                     MLX4_RESERVE_A0_QP);
1164         if (err) {
1165                 en_err(priv, "Failed reserving drop qpn\n");
1166                 return err;
1167         }
1168         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1169         if (err) {
1170                 en_err(priv, "Failed allocating drop qp\n");
1171                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1172                 return err;
1173         }
1174
1175         return 0;
1176 }
1177
1178 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1179 {
1180         u32 qpn;
1181
1182         qpn = priv->drop_qp.qpn;
1183         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1184         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1185         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1186 }
1187
1188 /* Allocate rx qp's and configure them according to rss map */
1189 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1190 {
1191         struct mlx4_en_dev *mdev = priv->mdev;
1192         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1193         struct mlx4_qp_context context;
1194         struct mlx4_rss_context *rss_context;
1195         int rss_rings;
1196         void *ptr;
1197         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1198                         MLX4_RSS_TCP_IPV6);
1199         int i, qpn;
1200         int err = 0;
1201         int good_qps = 0;
1202
1203         en_dbg(DRV, priv, "Configuring rss steering\n");
1204         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1205                                     priv->rx_ring_num,
1206                                     &rss_map->base_qpn, 0);
1207         if (err) {
1208                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1209                 return err;
1210         }
1211
1212         for (i = 0; i < priv->rx_ring_num; i++) {
1213                 qpn = rss_map->base_qpn + i;
1214                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1215                                             &rss_map->state[i],
1216                                             &rss_map->qps[i]);
1217                 if (err)
1218                         goto rss_err;
1219
1220                 ++good_qps;
1221         }
1222
1223         /* Configure RSS indirection qp */
1224         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1225         if (err) {
1226                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1227                 goto rss_err;
1228         }
1229         rss_map->indir_qp.event = mlx4_en_sqp_event;
1230         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1231                                 priv->rx_ring[0]->cqn, -1, &context);
1232
1233         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1234                 rss_rings = priv->rx_ring_num;
1235         else
1236                 rss_rings = priv->prof->rss_rings;
1237
1238         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1239                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1240         rss_context = ptr;
1241         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1242                                             (rss_map->base_qpn));
1243         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1244         if (priv->mdev->profile.udp_rss) {
1245                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1246                 rss_context->base_qpn_udp = rss_context->default_qpn;
1247         }
1248
1249         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1250                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1251                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1252         }
1253
1254         rss_context->flags = rss_mask;
1255         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1256         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1257                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1258         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1259                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1260                 memcpy(rss_context->rss_key, priv->rss_key,
1261                        MLX4_EN_RSS_KEY_SIZE);
1262         } else {
1263                 en_err(priv, "Unknown RSS hash function requested\n");
1264                 err = -EINVAL;
1265                 goto indir_err;
1266         }
1267         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1268                                &rss_map->indir_qp, &rss_map->indir_state);
1269         if (err)
1270                 goto indir_err;
1271
1272         return 0;
1273
1274 indir_err:
1275         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1276                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1277         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1278         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1279 rss_err:
1280         for (i = 0; i < good_qps; i++) {
1281                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1282                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1283                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1284                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1285         }
1286         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1287         return err;
1288 }
1289
1290 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1291 {
1292         struct mlx4_en_dev *mdev = priv->mdev;
1293         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1294         int i;
1295
1296         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1297                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1298         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1299         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1300
1301         for (i = 0; i < priv->rx_ring_num; i++) {
1302                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1303                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1304                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1305                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1306         }
1307         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1308 }