2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
37 #include <linux/slab.h>
39 #include <linux/tcp.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47 #include <linux/of_device.h>
48 #include <linux/of_net.h>
54 #define DRV_NAME "sky2"
55 #define DRV_VERSION "1.30"
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
68 /* This is the worst case number of transmit list elements for a single skb:
69 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
70 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
71 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
72 #define TX_MAX_PENDING 1024
73 #define TX_DEF_PENDING 63
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
81 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100 static int legacy_pme = 0;
101 module_param(legacy_pme, int, 0);
102 MODULE_PARM_DESC(legacy_pme, "Legacy power management");
104 static const struct pci_device_id sky2_id_table[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
145 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
146 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
150 MODULE_DEVICE_TABLE(pci, sky2_id_table);
152 /* Avoid conditionals by using array */
153 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
154 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
155 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
157 static void sky2_set_multicast(struct net_device *dev);
158 static irqreturn_t sky2_intr(int irq, void *dev_id);
160 /* Access to PHY via serial interconnect */
161 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
165 gma_write16(hw, port, GM_SMI_DATA, val);
166 gma_write16(hw, port, GM_SMI_CTRL,
167 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169 for (i = 0; i < PHY_RETRIES; i++) {
170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
174 if (!(ctrl & GM_SMI_CT_BUSY))
180 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
188 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
193 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195 for (i = 0; i < PHY_RETRIES; i++) {
196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
200 if (ctrl & GM_SMI_CT_RD_VAL) {
201 *val = gma_read16(hw, port, GM_SMI_DATA);
208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
215 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
218 __gm_phy_read(hw, port, reg, &v);
223 static void sky2_power_on(struct sky2_hw *hw)
225 /* switch power to VCC (WA for VAUX problem) */
226 sky2_write8(hw, B0_POWER_CTRL,
227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
229 /* disable Core Clock Division, */
230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
233 /* enable bits are inverted */
234 sky2_write8(hw, B2_Y2_CLK_GATE,
235 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
236 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
237 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
244 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
246 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
247 /* set all bits to 0 except bits 15..12 and 8 */
248 reg &= P_ASPM_CONTROL_MSK;
249 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
251 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
252 /* set all bits to 0 except bits 28 & 27 */
253 reg &= P_CTL_TIM_VMAIN_AV_MSK;
254 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
258 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
265 sky2_read32(hw, B2_GP_IO);
268 /* Turn on "driver loaded" LED */
269 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
272 static void sky2_power_aux(struct sky2_hw *hw)
274 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
275 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
277 /* enable bits are inverted */
278 sky2_write8(hw, B2_Y2_CLK_GATE,
279 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
280 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
281 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
283 /* switch power to VAUX if supported and PME from D3cold */
284 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
285 pci_pme_capable(hw->pdev, PCI_D3cold))
286 sky2_write8(hw, B0_POWER_CTRL,
287 (PC_VAUX_ENA | PC_VCC_ENA |
288 PC_VAUX_ON | PC_VCC_OFF));
290 /* turn off "driver loaded LED" */
291 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
294 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
298 /* disable all GMAC IRQ's */
299 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
301 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
302 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
303 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
304 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
306 reg = gma_read16(hw, port, GM_RX_CTRL);
307 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
308 gma_write16(hw, port, GM_RX_CTRL, reg);
311 /* flow control to advertise bits */
312 static const u16 copper_fc_adv[] = {
314 [FC_TX] = PHY_M_AN_ASP,
315 [FC_RX] = PHY_M_AN_PC,
316 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
319 /* flow control to advertise bits when using 1000BaseX */
320 static const u16 fiber_fc_adv[] = {
321 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
322 [FC_TX] = PHY_M_P_ASYM_MD_X,
323 [FC_RX] = PHY_M_P_SYM_MD_X,
324 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
327 /* flow control to GMA disable bits */
328 static const u16 gm_fc_disable[] = {
329 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
330 [FC_TX] = GM_GPCR_FC_RX_DIS,
331 [FC_RX] = GM_GPCR_FC_TX_DIS,
336 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
338 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
339 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
341 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
342 !(hw->flags & SKY2_HW_NEWER_PHY)) {
343 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
345 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
347 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
349 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
350 if (hw->chip_id == CHIP_ID_YUKON_EC)
351 /* set downshift counter to 3x and enable downshift */
352 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
354 /* set master & slave downshift counter to 1x */
355 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
357 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
360 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
361 if (sky2_is_copper(hw)) {
362 if (!(hw->flags & SKY2_HW_GIGABIT)) {
363 /* enable automatic crossover */
364 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
366 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
367 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
370 /* Enable Class A driver for FE+ A0 */
371 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
372 spec |= PHY_M_FESC_SEL_CL_A;
373 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
376 /* disable energy detect */
377 ctrl &= ~PHY_M_PC_EN_DET_MSK;
379 /* enable automatic crossover */
380 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
382 /* downshift on PHY 88E1112 and 88E1149 is changed */
383 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
384 (hw->flags & SKY2_HW_NEWER_PHY)) {
385 /* set downshift counter to 3x and enable downshift */
386 ctrl &= ~PHY_M_PC_DSC_MSK;
387 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
391 /* workaround for deviation #4.88 (CRC errors) */
392 /* disable Automatic Crossover */
394 ctrl &= ~PHY_M_PC_MDIX_MSK;
397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
399 /* special setup for PHY 88E1112 Fiber */
400 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
401 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
403 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
406 ctrl &= ~PHY_M_MAC_MD_MSK;
407 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
410 if (hw->pmd_type == 'P') {
411 /* select page 1 to access Fiber registers */
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
414 /* for SFP-module set SIGDET polarity to low */
415 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
416 ctrl |= PHY_M_FIB_SIGD_POL;
417 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
420 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
428 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
429 if (sky2_is_copper(hw)) {
430 if (sky2->advertising & ADVERTISED_1000baseT_Full)
431 ct1000 |= PHY_M_1000C_AFD;
432 if (sky2->advertising & ADVERTISED_1000baseT_Half)
433 ct1000 |= PHY_M_1000C_AHD;
434 if (sky2->advertising & ADVERTISED_100baseT_Full)
435 adv |= PHY_M_AN_100_FD;
436 if (sky2->advertising & ADVERTISED_100baseT_Half)
437 adv |= PHY_M_AN_100_HD;
438 if (sky2->advertising & ADVERTISED_10baseT_Full)
439 adv |= PHY_M_AN_10_FD;
440 if (sky2->advertising & ADVERTISED_10baseT_Half)
441 adv |= PHY_M_AN_10_HD;
443 } else { /* special defines for FIBER (88E1040S only) */
444 if (sky2->advertising & ADVERTISED_1000baseT_Full)
445 adv |= PHY_M_AN_1000X_AFD;
446 if (sky2->advertising & ADVERTISED_1000baseT_Half)
447 adv |= PHY_M_AN_1000X_AHD;
450 /* Restart Auto-negotiation */
451 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
453 /* forced speed/duplex settings */
454 ct1000 = PHY_M_1000C_MSE;
456 /* Disable auto update for duplex flow control and duplex */
457 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
459 switch (sky2->speed) {
461 ctrl |= PHY_CT_SP1000;
462 reg |= GM_GPCR_SPEED_1000;
465 ctrl |= PHY_CT_SP100;
466 reg |= GM_GPCR_SPEED_100;
470 if (sky2->duplex == DUPLEX_FULL) {
471 reg |= GM_GPCR_DUP_FULL;
472 ctrl |= PHY_CT_DUP_MD;
473 } else if (sky2->speed < SPEED_1000)
474 sky2->flow_mode = FC_NONE;
477 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
478 if (sky2_is_copper(hw))
479 adv |= copper_fc_adv[sky2->flow_mode];
481 adv |= fiber_fc_adv[sky2->flow_mode];
483 reg |= GM_GPCR_AU_FCT_DIS;
484 reg |= gm_fc_disable[sky2->flow_mode];
486 /* Forward pause packets to GMAC? */
487 if (sky2->flow_mode & FC_RX)
488 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
490 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
493 gma_write16(hw, port, GM_GP_CTRL, reg);
495 if (hw->flags & SKY2_HW_GIGABIT)
496 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
498 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
499 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
501 /* Setup Phy LED's */
502 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
505 switch (hw->chip_id) {
506 case CHIP_ID_YUKON_FE:
507 /* on 88E3082 these bits are at 11..9 (shifted left) */
508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
510 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
512 /* delete ACT LED control bits */
513 ctrl &= ~PHY_M_FELP_LED1_MSK;
514 /* change ACT LED control to blink mode */
515 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
516 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
519 case CHIP_ID_YUKON_FE_P:
520 /* Enable Link Partner Next Page */
521 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
522 ctrl |= PHY_M_PC_ENA_LIP_NP;
524 /* disable Energy Detect and enable scrambler */
525 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
526 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
528 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
529 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
530 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
531 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
533 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
536 case CHIP_ID_YUKON_XL:
537 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
539 /* select page 3 to access LED control register */
540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
542 /* set LED Function Control register */
543 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
544 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
545 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
546 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
547 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
549 /* set Polarity Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
551 (PHY_M_POLC_LS1_P_MIX(4) |
552 PHY_M_POLC_IS0_P_MIX(4) |
553 PHY_M_POLC_LOS_CTRL(2) |
554 PHY_M_POLC_INIT_CTRL(2) |
555 PHY_M_POLC_STA1_CTRL(2) |
556 PHY_M_POLC_STA0_CTRL(2)));
558 /* restore page register */
559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
562 case CHIP_ID_YUKON_EC_U:
563 case CHIP_ID_YUKON_EX:
564 case CHIP_ID_YUKON_SUPR:
565 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
567 /* select page 3 to access LED control register */
568 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
570 /* set LED Function Control register */
571 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
572 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
573 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
574 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
575 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
577 /* set Blink Rate in LED Timer Control Register */
578 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
579 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
580 /* restore page register */
581 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
585 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
586 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
588 /* turn off the Rx LED (LED_RX) */
589 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
592 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
593 /* apply fixes in PHY AFE */
594 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
596 /* increase differential signal amplitude in 10BASE-T */
597 gm_phy_write(hw, port, 0x18, 0xaa99);
598 gm_phy_write(hw, port, 0x17, 0x2011);
600 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
601 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
602 gm_phy_write(hw, port, 0x18, 0xa204);
603 gm_phy_write(hw, port, 0x17, 0x2002);
606 /* set page register to 0 */
607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
608 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
609 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
610 /* apply workaround for integrated resistors calibration */
611 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
612 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
613 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
614 /* apply fixes in PHY AFE */
615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
617 /* apply RDAC termination workaround */
618 gm_phy_write(hw, port, 24, 0x2800);
619 gm_phy_write(hw, port, 23, 0x2001);
621 /* set page register back to 0 */
622 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
623 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
624 hw->chip_id < CHIP_ID_YUKON_SUPR) {
625 /* no effect on Yukon-XL */
626 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
628 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
629 sky2->speed == SPEED_100) {
630 /* turn on 100 Mbps LED (LED_LINK100) */
631 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
635 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
637 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
638 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
640 /* This a phy register setup workaround copied from vendor driver. */
641 static const struct {
647 /* { 0x155, 0x130b },*/
653 /* { 0x154, 0x2f39 },*/
657 /* { 0x158, 0x1223 },*/
664 /* Start Workaround for OptimaEEE Rev.Z0 */
665 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
667 gm_phy_write(hw, port, 1, 0x4099);
668 gm_phy_write(hw, port, 3, 0x1120);
669 gm_phy_write(hw, port, 11, 0x113c);
670 gm_phy_write(hw, port, 14, 0x8100);
671 gm_phy_write(hw, port, 15, 0x112a);
672 gm_phy_write(hw, port, 17, 0x1008);
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
675 gm_phy_write(hw, port, 1, 0x20b0);
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
679 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
680 /* apply AFE settings */
681 gm_phy_write(hw, port, 17, eee_afe[i].val);
682 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
685 /* End Workaround for OptimaEEE */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
688 /* Enable 10Base-Te (EEE) */
689 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
690 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
691 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
692 reg | PHY_M_10B_TE_ENABLE);
696 /* Enable phy interrupt on auto-negotiation complete (or link up) */
697 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
698 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
700 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
703 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
704 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
706 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
712 reg1 &= ~phy_power[port];
714 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
715 reg1 |= coma_mode[port];
717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
719 sky2_pci_read32(hw, PCI_DEV_REG1);
721 if (hw->chip_id == CHIP_ID_YUKON_FE)
722 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
723 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
724 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
727 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
732 /* release GPHY Control reset */
733 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
735 /* release GMAC reset */
736 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738 if (hw->flags & SKY2_HW_NEWER_PHY) {
739 /* select page 2 to access MAC control register */
740 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
742 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
743 /* allow GMII Power Down */
744 ctrl &= ~PHY_M_MAC_GMIF_PUP;
745 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
747 /* set page register back to 0 */
748 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
751 /* setup General Purpose Control Register */
752 gma_write16(hw, port, GM_GP_CTRL,
753 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
754 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
757 if (hw->chip_id != CHIP_ID_YUKON_EC) {
758 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
759 /* select page 2 to access MAC control register */
760 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
762 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
763 /* enable Power Down */
764 ctrl |= PHY_M_PC_POW_D_ENA;
765 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
767 /* set page register back to 0 */
768 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
771 /* set IEEE compatible Power Down Mode (dev. #4.99) */
772 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
775 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
776 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
777 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
778 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
779 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
782 /* configure IPG according to used link speed */
783 static void sky2_set_ipg(struct sky2_port *sky2)
787 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
788 reg &= ~GM_SMOD_IPG_MSK;
789 if (sky2->speed > SPEED_100)
790 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
792 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
793 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
797 static void sky2_enable_rx_tx(struct sky2_port *sky2)
799 struct sky2_hw *hw = sky2->hw;
800 unsigned port = sky2->port;
803 reg = gma_read16(hw, port, GM_GP_CTRL);
804 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
805 gma_write16(hw, port, GM_GP_CTRL, reg);
808 /* Force a renegotiation */
809 static void sky2_phy_reinit(struct sky2_port *sky2)
811 spin_lock_bh(&sky2->phy_lock);
812 sky2_phy_init(sky2->hw, sky2->port);
813 sky2_enable_rx_tx(sky2);
814 spin_unlock_bh(&sky2->phy_lock);
817 /* Put device in state to listen for Wake On Lan */
818 static void sky2_wol_init(struct sky2_port *sky2)
820 struct sky2_hw *hw = sky2->hw;
821 unsigned port = sky2->port;
822 enum flow_control save_mode;
825 /* Bring hardware out of reset */
826 sky2_write16(hw, B0_CTST, CS_RST_CLR);
827 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
830 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
833 * sky2_reset will re-enable on resume
835 save_mode = sky2->flow_mode;
836 ctrl = sky2->advertising;
838 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
839 sky2->flow_mode = FC_NONE;
841 spin_lock_bh(&sky2->phy_lock);
842 sky2_phy_power_up(hw, port);
843 sky2_phy_init(hw, port);
844 spin_unlock_bh(&sky2->phy_lock);
846 sky2->flow_mode = save_mode;
847 sky2->advertising = ctrl;
849 /* Set GMAC to no flow control and auto update for speed/duplex */
850 gma_write16(hw, port, GM_GP_CTRL,
851 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
852 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
854 /* Set WOL address */
855 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
856 sky2->netdev->dev_addr, ETH_ALEN);
858 /* Turn on appropriate WOL control bits */
859 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
861 if (sky2->wol & WAKE_PHY)
862 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
864 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
866 if (sky2->wol & WAKE_MAGIC)
867 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
869 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
871 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
872 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
874 /* Disable PiG firmware */
875 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
877 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
879 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
880 reg1 |= PCI_Y2_PME_LEGACY;
881 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
885 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
886 sky2_read32(hw, B0_CTST);
889 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
891 struct net_device *dev = hw->dev[port];
893 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
894 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
895 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
896 /* Yukon-Extreme B0 and further Extreme devices */
897 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
898 } else if (dev->mtu > ETH_DATA_LEN) {
899 /* set Tx GMAC FIFO Almost Empty Threshold */
900 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
901 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
903 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
908 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
910 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
914 const u8 *addr = hw->dev[port]->dev_addr;
916 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
917 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
919 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
921 if (hw->chip_id == CHIP_ID_YUKON_XL &&
922 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
924 /* WA DEV_472 -- looks like crossed wires on port 2 */
925 /* clear GMAC 1 Control reset */
926 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
928 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
929 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
930 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
931 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
932 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
935 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
937 /* Enable Transmit FIFO Underrun */
938 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
940 spin_lock_bh(&sky2->phy_lock);
941 sky2_phy_power_up(hw, port);
942 sky2_phy_init(hw, port);
943 spin_unlock_bh(&sky2->phy_lock);
946 reg = gma_read16(hw, port, GM_PHY_ADDR);
947 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
949 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
950 gma_read16(hw, port, i);
951 gma_write16(hw, port, GM_PHY_ADDR, reg);
953 /* transmit control */
954 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
956 /* receive control reg: unicast + multicast + no FCS */
957 gma_write16(hw, port, GM_RX_CTRL,
958 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
960 /* transmit flow control */
961 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
963 /* transmit parameter */
964 gma_write16(hw, port, GM_TX_PARAM,
965 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
966 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
967 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
968 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
970 /* serial mode register */
971 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
972 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
974 if (hw->dev[port]->mtu > ETH_DATA_LEN)
975 reg |= GM_SMOD_JUMBO_ENA;
977 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
978 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
979 reg |= GM_NEW_FLOW_CTRL;
981 gma_write16(hw, port, GM_SERIAL_MODE, reg);
983 /* virtual address for data */
984 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
986 /* physical address: used for pause frames */
987 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
989 /* ignore counter overflows */
990 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
991 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
992 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
994 /* Configure Rx MAC FIFO */
995 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
996 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
997 if (hw->chip_id == CHIP_ID_YUKON_EX ||
998 hw->chip_id == CHIP_ID_YUKON_FE_P)
999 rx_reg |= GMF_RX_OVER_ON;
1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
1003 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1004 /* Hardware errata - clear flush mask */
1005 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1007 /* Flush Rx MAC FIFO on any flow control or error */
1008 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1011 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1012 reg = RX_GMF_FL_THR_DEF + 1;
1013 /* Another magic mystery workaround from sk98lin */
1014 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1015 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1017 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1019 /* Configure Tx MAC FIFO */
1020 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1021 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1023 /* On chips without ram buffer, pause is controlled by MAC level */
1024 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1025 /* Pause threshold is scaled by 8 in bytes */
1026 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1027 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1031 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1032 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1034 sky2_set_tx_stfwd(hw, port);
1037 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1038 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1039 /* disable dynamic watermark */
1040 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1041 reg &= ~TX_DYN_WM_ENA;
1042 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1046 /* Assign Ram Buffer allocation to queue */
1047 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1051 /* convert from K bytes to qwords used for hw register */
1054 end = start + space - 1;
1056 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1057 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1058 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1059 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1060 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1062 if (q == Q_R1 || q == Q_R2) {
1063 u32 tp = space - space/4;
1065 /* On receive queue's set the thresholds
1066 * give receiver priority when > 3/4 full
1067 * send pause when down to 2K
1069 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1070 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1072 tp = space - 8192/8;
1073 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1074 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1076 /* Enable store & forward on Tx queue's because
1077 * Tx FIFO is only 1K on Yukon
1079 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1082 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1083 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1086 /* Setup Bus Memory Interface */
1087 static void sky2_qset(struct sky2_hw *hw, u16 q)
1089 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1090 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1091 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1092 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1095 /* Setup prefetch unit registers. This is the interface between
1096 * hardware and driver list elements
1098 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1099 dma_addr_t addr, u32 last)
1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1105 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1106 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1108 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1111 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1113 struct sky2_tx_le *le = sky2->tx_le + *slot;
1115 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1120 static void tx_init(struct sky2_port *sky2)
1122 struct sky2_tx_le *le;
1124 sky2->tx_prod = sky2->tx_cons = 0;
1125 sky2->tx_tcpsum = 0;
1126 sky2->tx_last_mss = 0;
1127 netdev_reset_queue(sky2->netdev);
1129 le = get_tx_le(sky2, &sky2->tx_prod);
1131 le->opcode = OP_ADDR64 | HW_OWNER;
1132 sky2->tx_last_upper = 0;
1135 /* Update chip's next pointer */
1136 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1138 /* Make sure write' to descriptors are complete before we tell hardware */
1140 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1142 /* Synchronize I/O on since next processor may write to tail */
1147 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1149 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1150 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1155 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1159 /* Space needed for frame data + headers rounded up */
1160 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1162 /* Stopping point for hardware truncation */
1163 return (size - 8) / sizeof(u32);
1166 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1168 struct rx_ring_info *re;
1171 /* Space needed for frame data + headers rounded up */
1172 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1174 sky2->rx_nfrags = size >> PAGE_SHIFT;
1175 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1177 /* Compute residue after pages */
1178 size -= sky2->rx_nfrags << PAGE_SHIFT;
1180 /* Optimize to handle small packets and headers */
1181 if (size < copybreak)
1183 if (size < ETH_HLEN)
1189 /* Build description to hardware for one receive segment */
1190 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1191 dma_addr_t map, unsigned len)
1193 struct sky2_rx_le *le;
1195 if (sizeof(dma_addr_t) > sizeof(u32)) {
1196 le = sky2_next_rx(sky2);
1197 le->addr = cpu_to_le32(upper_32_bits(map));
1198 le->opcode = OP_ADDR64 | HW_OWNER;
1201 le = sky2_next_rx(sky2);
1202 le->addr = cpu_to_le32(lower_32_bits(map));
1203 le->length = cpu_to_le16(len);
1204 le->opcode = op | HW_OWNER;
1207 /* Build description to hardware for one possibly fragmented skb */
1208 static void sky2_rx_submit(struct sky2_port *sky2,
1209 const struct rx_ring_info *re)
1213 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1215 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1216 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1220 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1223 struct sk_buff *skb = re->skb;
1226 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1227 if (pci_dma_mapping_error(pdev, re->data_addr))
1230 dma_unmap_len_set(re, data_size, size);
1232 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1233 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1235 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1236 skb_frag_size(frag),
1239 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1240 goto map_page_error;
1246 pci_unmap_page(pdev, re->frag_addr[i],
1247 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1248 PCI_DMA_FROMDEVICE);
1251 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1252 PCI_DMA_FROMDEVICE);
1255 if (net_ratelimit())
1256 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1261 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1263 struct sk_buff *skb = re->skb;
1266 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1267 PCI_DMA_FROMDEVICE);
1269 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1270 pci_unmap_page(pdev, re->frag_addr[i],
1271 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1272 PCI_DMA_FROMDEVICE);
1275 /* Tell chip where to start receive checksum.
1276 * Actually has two checksums, but set both same to avoid possible byte
1279 static void rx_set_checksum(struct sky2_port *sky2)
1281 struct sky2_rx_le *le = sky2_next_rx(sky2);
1283 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1285 le->opcode = OP_TCPSTART | HW_OWNER;
1287 sky2_write32(sky2->hw,
1288 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1289 (sky2->netdev->features & NETIF_F_RXCSUM)
1290 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1293 /* Enable/disable receive hash calculation (RSS) */
1294 static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
1300 /* Supports IPv6 and other modes */
1301 if (hw->flags & SKY2_HW_NEW_LE) {
1303 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1306 /* Program RSS initial values */
1307 if (features & NETIF_F_RXHASH) {
1310 netdev_rss_key_fill(rss_key, sizeof(rss_key));
1311 for (i = 0; i < nkeys; i++)
1312 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1315 /* Need to turn on (undocumented) flag to make hashing work */
1316 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1319 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1320 BMU_ENA_RX_RSS_HASH);
1322 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1323 BMU_DIS_RX_RSS_HASH);
1327 * The RX Stop command will not work for Yukon-2 if the BMU does not
1328 * reach the end of packet and since we can't make sure that we have
1329 * incoming data, we must reset the BMU while it is not doing a DMA
1330 * transfer. Since it is possible that the RX path is still active,
1331 * the RX RAM buffer will be stopped first, so any possible incoming
1332 * data will not trigger a DMA. After the RAM buffer is stopped, the
1333 * BMU is polled until any DMA in progress is ended and only then it
1336 static void sky2_rx_stop(struct sky2_port *sky2)
1338 struct sky2_hw *hw = sky2->hw;
1339 unsigned rxq = rxqaddr[sky2->port];
1342 /* disable the RAM Buffer receive queue */
1343 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1345 for (i = 0; i < 0xffff; i++)
1346 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1347 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1350 netdev_warn(sky2->netdev, "receiver stop failed\n");
1352 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1354 /* reset the Rx prefetch unit */
1355 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1359 /* Clean out receive buffer area, assumes receiver hardware stopped */
1360 static void sky2_rx_clean(struct sky2_port *sky2)
1365 memset(sky2->rx_le, 0, RX_LE_BYTES);
1367 for (i = 0; i < sky2->rx_pending; i++) {
1368 struct rx_ring_info *re = sky2->rx_ring + i;
1371 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1378 /* Basic MII support */
1379 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1381 struct mii_ioctl_data *data = if_mii(ifr);
1382 struct sky2_port *sky2 = netdev_priv(dev);
1383 struct sky2_hw *hw = sky2->hw;
1384 int err = -EOPNOTSUPP;
1386 if (!netif_running(dev))
1387 return -ENODEV; /* Phy still in reset */
1391 data->phy_id = PHY_ADDR_MARV;
1397 spin_lock_bh(&sky2->phy_lock);
1398 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1399 spin_unlock_bh(&sky2->phy_lock);
1401 data->val_out = val;
1406 spin_lock_bh(&sky2->phy_lock);
1407 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1409 spin_unlock_bh(&sky2->phy_lock);
1415 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1417 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1419 struct sky2_port *sky2 = netdev_priv(dev);
1420 struct sky2_hw *hw = sky2->hw;
1421 u16 port = sky2->port;
1423 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1424 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1427 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1430 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1431 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1434 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1436 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1439 /* Can't do transmit offload of vlan without hw vlan */
1440 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1444 /* Amount of required worst case padding in rx buffer */
1445 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1447 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1451 * Allocate an skb for receiving. If the MTU is large enough
1452 * make the skb non-linear with a fragment list of pages.
1454 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1456 struct sk_buff *skb;
1459 skb = __netdev_alloc_skb(sky2->netdev,
1460 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1465 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1466 unsigned char *start;
1468 * Workaround for a bug in FIFO that cause hang
1469 * if the FIFO if the receive buffer is not 64 byte aligned.
1470 * The buffer returned from netdev_alloc_skb is
1471 * aligned except if slab debugging is enabled.
1473 start = PTR_ALIGN(skb->data, 8);
1474 skb_reserve(skb, start - skb->data);
1476 skb_reserve(skb, NET_IP_ALIGN);
1478 for (i = 0; i < sky2->rx_nfrags; i++) {
1479 struct page *page = alloc_page(gfp);
1483 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1493 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1495 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1498 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1500 struct sky2_hw *hw = sky2->hw;
1503 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1506 for (i = 0; i < sky2->rx_pending; i++) {
1507 struct rx_ring_info *re = sky2->rx_ring + i;
1509 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1513 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1514 dev_kfree_skb(re->skb);
1523 * Setup receiver buffer pool.
1524 * Normal case this ends up creating one list element for skb
1525 * in the receive ring. Worst case if using large MTU and each
1526 * allocation falls on a different 64 bit region, that results
1527 * in 6 list elements per ring entry.
1528 * One element is used for checksum enable/disable, and one
1529 * extra to avoid wrap.
1531 static void sky2_rx_start(struct sky2_port *sky2)
1533 struct sky2_hw *hw = sky2->hw;
1534 struct rx_ring_info *re;
1535 unsigned rxq = rxqaddr[sky2->port];
1538 sky2->rx_put = sky2->rx_next = 0;
1541 /* On PCI express lowering the watermark gives better performance */
1542 if (pci_is_pcie(hw->pdev))
1543 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1545 /* These chips have no ram buffer?
1546 * MAC Rx RAM Read is controlled by hardware */
1547 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1548 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1549 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1551 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1553 if (!(hw->flags & SKY2_HW_NEW_LE))
1554 rx_set_checksum(sky2);
1556 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1557 rx_set_rss(sky2->netdev, sky2->netdev->features);
1559 /* submit Rx ring */
1560 for (i = 0; i < sky2->rx_pending; i++) {
1561 re = sky2->rx_ring + i;
1562 sky2_rx_submit(sky2, re);
1566 * The receiver hangs if it receives frames larger than the
1567 * packet buffer. As a workaround, truncate oversize frames, but
1568 * the register is limited to 9 bits, so if you do frames > 2052
1569 * you better get the MTU right!
1571 thresh = sky2_get_rx_threshold(sky2);
1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1575 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1576 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1579 /* Tell chip about available buffers */
1580 sky2_rx_update(sky2, rxq);
1582 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1583 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1585 * Disable flushing of non ASF packets;
1586 * must be done after initializing the BMUs;
1587 * drivers without ASF support should do this too, otherwise
1588 * it may happen that they cannot run on ASF devices;
1589 * remember that the MAC FIFO isn't reset during initialization.
1591 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1594 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1595 /* Enable RX Home Address & Routing Header checksum fix */
1596 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1597 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1599 /* Enable TX Home Address & Routing Header checksum fix */
1600 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1601 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1605 static int sky2_alloc_buffers(struct sky2_port *sky2)
1607 struct sky2_hw *hw = sky2->hw;
1609 /* must be power of 2 */
1610 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1611 sky2->tx_ring_size *
1612 sizeof(struct sky2_tx_le),
1617 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1622 sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES,
1627 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1632 return sky2_alloc_rx_skbs(sky2);
1637 static void sky2_free_buffers(struct sky2_port *sky2)
1639 struct sky2_hw *hw = sky2->hw;
1641 sky2_rx_clean(sky2);
1644 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1645 sky2->rx_le, sky2->rx_le_map);
1649 pci_free_consistent(hw->pdev,
1650 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1651 sky2->tx_le, sky2->tx_le_map);
1654 kfree(sky2->tx_ring);
1655 kfree(sky2->rx_ring);
1657 sky2->tx_ring = NULL;
1658 sky2->rx_ring = NULL;
1661 static void sky2_hw_up(struct sky2_port *sky2)
1663 struct sky2_hw *hw = sky2->hw;
1664 unsigned port = sky2->port;
1667 struct net_device *otherdev = hw->dev[sky2->port^1];
1672 * On dual port PCI-X card, there is an problem where status
1673 * can be received out of order due to split transactions
1675 if (otherdev && netif_running(otherdev) &&
1676 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1679 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1680 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1681 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1684 sky2_mac_init(hw, port);
1686 /* Register is number of 4K blocks on internal RAM buffer. */
1687 ramsize = sky2_read8(hw, B2_E_0) * 4;
1691 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1693 rxspace = ramsize / 2;
1695 rxspace = 8 + (2*(ramsize - 16))/3;
1697 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1698 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1700 /* Make sure SyncQ is disabled */
1701 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1705 sky2_qset(hw, txqaddr[port]);
1707 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1708 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1709 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1711 /* Set almost empty threshold */
1712 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1713 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1714 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1716 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1717 sky2->tx_ring_size - 1);
1719 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1720 netdev_update_features(sky2->netdev);
1722 sky2_rx_start(sky2);
1725 /* Setup device IRQ and enable napi to process */
1726 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1728 struct pci_dev *pdev = hw->pdev;
1731 err = request_irq(pdev->irq, sky2_intr,
1732 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1735 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1737 hw->flags |= SKY2_HW_IRQ_SETUP;
1739 napi_enable(&hw->napi);
1740 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1741 sky2_read32(hw, B0_IMSK);
1748 /* Bring up network interface. */
1749 static int sky2_open(struct net_device *dev)
1751 struct sky2_port *sky2 = netdev_priv(dev);
1752 struct sky2_hw *hw = sky2->hw;
1753 unsigned port = sky2->port;
1757 netif_carrier_off(dev);
1759 err = sky2_alloc_buffers(sky2);
1763 /* With single port, IRQ is setup when device is brought up */
1764 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1769 /* Enable interrupts from phy/mac for port */
1770 imask = sky2_read32(hw, B0_IMSK);
1772 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1773 hw->chip_id == CHIP_ID_YUKON_PRM ||
1774 hw->chip_id == CHIP_ID_YUKON_OP_2)
1775 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1777 imask |= portirq_msk[port];
1778 sky2_write32(hw, B0_IMSK, imask);
1779 sky2_read32(hw, B0_IMSK);
1781 netif_info(sky2, ifup, dev, "enabling interface\n");
1786 sky2_free_buffers(sky2);
1790 /* Modular subtraction in ring */
1791 static inline int tx_inuse(const struct sky2_port *sky2)
1793 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1796 /* Number of list elements available for next tx */
1797 static inline int tx_avail(const struct sky2_port *sky2)
1799 return sky2->tx_pending - tx_inuse(sky2);
1802 /* Estimate of number of transmit list elements required */
1803 static unsigned tx_le_req(const struct sk_buff *skb)
1807 count = (skb_shinfo(skb)->nr_frags + 1)
1808 * (sizeof(dma_addr_t) / sizeof(u32));
1810 if (skb_is_gso(skb))
1812 else if (sizeof(dma_addr_t) == sizeof(u32))
1813 ++count; /* possible vlan */
1815 if (skb->ip_summed == CHECKSUM_PARTIAL)
1821 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1823 if (re->flags & TX_MAP_SINGLE)
1824 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1825 dma_unmap_len(re, maplen),
1827 else if (re->flags & TX_MAP_PAGE)
1828 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1829 dma_unmap_len(re, maplen),
1835 * Put one packet in ring for transmit.
1836 * A single packet can generate multiple list elements, and
1837 * the number of ring elements will probably be less than the number
1838 * of list elements used.
1840 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1841 struct net_device *dev)
1843 struct sky2_port *sky2 = netdev_priv(dev);
1844 struct sky2_hw *hw = sky2->hw;
1845 struct sky2_tx_le *le = NULL;
1846 struct tx_ring_info *re;
1854 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1855 return NETDEV_TX_BUSY;
1857 len = skb_headlen(skb);
1858 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1860 if (pci_dma_mapping_error(hw->pdev, mapping))
1863 slot = sky2->tx_prod;
1864 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1865 "tx queued, slot %u, len %d\n", slot, skb->len);
1867 /* Send high bits if needed */
1868 upper = upper_32_bits(mapping);
1869 if (upper != sky2->tx_last_upper) {
1870 le = get_tx_le(sky2, &slot);
1871 le->addr = cpu_to_le32(upper);
1872 sky2->tx_last_upper = upper;
1873 le->opcode = OP_ADDR64 | HW_OWNER;
1876 /* Check for TCP Segmentation Offload */
1877 mss = skb_shinfo(skb)->gso_size;
1880 if (!(hw->flags & SKY2_HW_NEW_LE))
1881 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1883 if (mss != sky2->tx_last_mss) {
1884 le = get_tx_le(sky2, &slot);
1885 le->addr = cpu_to_le32(mss);
1887 if (hw->flags & SKY2_HW_NEW_LE)
1888 le->opcode = OP_MSS | HW_OWNER;
1890 le->opcode = OP_LRGLEN | HW_OWNER;
1891 sky2->tx_last_mss = mss;
1897 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1898 if (skb_vlan_tag_present(skb)) {
1900 le = get_tx_le(sky2, &slot);
1902 le->opcode = OP_VLAN|HW_OWNER;
1904 le->opcode |= OP_VLAN;
1905 le->length = cpu_to_be16(skb_vlan_tag_get(skb));
1909 /* Handle TCP checksum offload */
1910 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1911 /* On Yukon EX (some versions) encoding change. */
1912 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1913 ctrl |= CALSUM; /* auto checksum */
1915 const unsigned offset = skb_transport_offset(skb);
1918 tcpsum = offset << 16; /* sum start */
1919 tcpsum |= offset + skb->csum_offset; /* sum write */
1921 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1922 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1925 if (tcpsum != sky2->tx_tcpsum) {
1926 sky2->tx_tcpsum = tcpsum;
1928 le = get_tx_le(sky2, &slot);
1929 le->addr = cpu_to_le32(tcpsum);
1930 le->length = 0; /* initial checksum value */
1931 le->ctrl = 1; /* one packet */
1932 le->opcode = OP_TCPLISW | HW_OWNER;
1937 re = sky2->tx_ring + slot;
1938 re->flags = TX_MAP_SINGLE;
1939 dma_unmap_addr_set(re, mapaddr, mapping);
1940 dma_unmap_len_set(re, maplen, len);
1942 le = get_tx_le(sky2, &slot);
1943 le->addr = cpu_to_le32(lower_32_bits(mapping));
1944 le->length = cpu_to_le16(len);
1946 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1949 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1950 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1952 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1953 skb_frag_size(frag), DMA_TO_DEVICE);
1955 if (dma_mapping_error(&hw->pdev->dev, mapping))
1956 goto mapping_unwind;
1958 upper = upper_32_bits(mapping);
1959 if (upper != sky2->tx_last_upper) {
1960 le = get_tx_le(sky2, &slot);
1961 le->addr = cpu_to_le32(upper);
1962 sky2->tx_last_upper = upper;
1963 le->opcode = OP_ADDR64 | HW_OWNER;
1966 re = sky2->tx_ring + slot;
1967 re->flags = TX_MAP_PAGE;
1968 dma_unmap_addr_set(re, mapaddr, mapping);
1969 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1971 le = get_tx_le(sky2, &slot);
1972 le->addr = cpu_to_le32(lower_32_bits(mapping));
1973 le->length = cpu_to_le16(skb_frag_size(frag));
1975 le->opcode = OP_BUFFER | HW_OWNER;
1981 sky2->tx_prod = slot;
1983 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1984 netif_stop_queue(dev);
1986 netdev_sent_queue(dev, skb->len);
1987 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1989 return NETDEV_TX_OK;
1992 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1993 re = sky2->tx_ring + i;
1995 sky2_tx_unmap(hw->pdev, re);
1999 if (net_ratelimit())
2000 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2001 dev_kfree_skb_any(skb);
2002 return NETDEV_TX_OK;
2006 * Free ring elements from starting at tx_cons until "done"
2009 * 1. The hardware will tell us about partial completion of multi-part
2010 * buffers so make sure not to free skb to early.
2011 * 2. This may run in parallel start_xmit because the it only
2012 * looks at the tail of the queue of FIFO (tx_cons), not
2013 * the head (tx_prod)
2015 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2017 struct net_device *dev = sky2->netdev;
2019 unsigned int bytes_compl = 0, pkts_compl = 0;
2021 BUG_ON(done >= sky2->tx_ring_size);
2023 for (idx = sky2->tx_cons; idx != done;
2024 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2025 struct tx_ring_info *re = sky2->tx_ring + idx;
2026 struct sk_buff *skb = re->skb;
2028 sky2_tx_unmap(sky2->hw->pdev, re);
2031 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2032 "tx done %u\n", idx);
2035 bytes_compl += skb->len;
2038 dev_kfree_skb_any(skb);
2040 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2044 sky2->tx_cons = idx;
2047 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2049 u64_stats_update_begin(&sky2->tx_stats.syncp);
2050 sky2->tx_stats.packets += pkts_compl;
2051 sky2->tx_stats.bytes += bytes_compl;
2052 u64_stats_update_end(&sky2->tx_stats.syncp);
2055 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2057 /* Disable Force Sync bit and Enable Alloc bit */
2058 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2059 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2061 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2062 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2063 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2065 /* Reset the PCI FIFO of the async Tx queue */
2066 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2067 BMU_RST_SET | BMU_FIFO_RST);
2069 /* Reset the Tx prefetch units */
2070 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2073 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2074 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2076 sky2_read32(hw, B0_CTST);
2079 static void sky2_hw_down(struct sky2_port *sky2)
2081 struct sky2_hw *hw = sky2->hw;
2082 unsigned port = sky2->port;
2085 /* Force flow control off */
2086 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2088 /* Stop transmitter */
2089 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2090 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2092 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2093 RB_RST_SET | RB_DIS_OP_MD);
2095 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2096 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2097 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2099 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2101 /* Workaround shared GMAC reset */
2102 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2103 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2104 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2106 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2108 /* Force any delayed status interrupt and NAPI */
2109 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2110 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2111 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2112 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2116 spin_lock_bh(&sky2->phy_lock);
2117 sky2_phy_power_down(hw, port);
2118 spin_unlock_bh(&sky2->phy_lock);
2120 sky2_tx_reset(hw, port);
2122 /* Free any pending frames stuck in HW queue */
2123 sky2_tx_complete(sky2, sky2->tx_prod);
2126 /* Network shutdown */
2127 static int sky2_close(struct net_device *dev)
2129 struct sky2_port *sky2 = netdev_priv(dev);
2130 struct sky2_hw *hw = sky2->hw;
2132 /* Never really got started! */
2136 netif_info(sky2, ifdown, dev, "disabling interface\n");
2138 if (hw->ports == 1) {
2139 sky2_write32(hw, B0_IMSK, 0);
2140 sky2_read32(hw, B0_IMSK);
2142 napi_disable(&hw->napi);
2143 free_irq(hw->pdev->irq, hw);
2144 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2148 /* Disable port IRQ */
2149 imask = sky2_read32(hw, B0_IMSK);
2150 imask &= ~portirq_msk[sky2->port];
2151 sky2_write32(hw, B0_IMSK, imask);
2152 sky2_read32(hw, B0_IMSK);
2154 synchronize_irq(hw->pdev->irq);
2155 napi_synchronize(&hw->napi);
2160 sky2_free_buffers(sky2);
2165 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2167 if (hw->flags & SKY2_HW_FIBRE_PHY)
2170 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2171 if (aux & PHY_M_PS_SPEED_100)
2177 switch (aux & PHY_M_PS_SPEED_MSK) {
2178 case PHY_M_PS_SPEED_1000:
2180 case PHY_M_PS_SPEED_100:
2187 static void sky2_link_up(struct sky2_port *sky2)
2189 struct sky2_hw *hw = sky2->hw;
2190 unsigned port = sky2->port;
2191 static const char *fc_name[] = {
2200 sky2_enable_rx_tx(sky2);
2202 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2204 netif_carrier_on(sky2->netdev);
2206 mod_timer(&hw->watchdog_timer, jiffies + 1);
2208 /* Turn on link LED */
2209 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2210 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2212 netif_info(sky2, link, sky2->netdev,
2213 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2215 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2216 fc_name[sky2->flow_status]);
2219 static void sky2_link_down(struct sky2_port *sky2)
2221 struct sky2_hw *hw = sky2->hw;
2222 unsigned port = sky2->port;
2225 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2227 reg = gma_read16(hw, port, GM_GP_CTRL);
2228 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2229 gma_write16(hw, port, GM_GP_CTRL, reg);
2231 netif_carrier_off(sky2->netdev);
2233 /* Turn off link LED */
2234 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2236 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2238 sky2_phy_init(hw, port);
2241 static enum flow_control sky2_flow(int rx, int tx)
2244 return tx ? FC_BOTH : FC_RX;
2246 return tx ? FC_TX : FC_NONE;
2249 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2251 struct sky2_hw *hw = sky2->hw;
2252 unsigned port = sky2->port;
2255 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2256 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2257 if (lpa & PHY_M_AN_RF) {
2258 netdev_err(sky2->netdev, "remote fault\n");
2262 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2263 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2267 sky2->speed = sky2_phy_speed(hw, aux);
2268 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2270 /* Since the pause result bits seem to in different positions on
2271 * different chips. look at registers.
2273 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2274 /* Shift for bits in fiber PHY */
2275 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2276 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2278 if (advert & ADVERTISE_1000XPAUSE)
2279 advert |= ADVERTISE_PAUSE_CAP;
2280 if (advert & ADVERTISE_1000XPSE_ASYM)
2281 advert |= ADVERTISE_PAUSE_ASYM;
2282 if (lpa & LPA_1000XPAUSE)
2283 lpa |= LPA_PAUSE_CAP;
2284 if (lpa & LPA_1000XPAUSE_ASYM)
2285 lpa |= LPA_PAUSE_ASYM;
2288 sky2->flow_status = FC_NONE;
2289 if (advert & ADVERTISE_PAUSE_CAP) {
2290 if (lpa & LPA_PAUSE_CAP)
2291 sky2->flow_status = FC_BOTH;
2292 else if (advert & ADVERTISE_PAUSE_ASYM)
2293 sky2->flow_status = FC_RX;
2294 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2295 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2296 sky2->flow_status = FC_TX;
2299 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2300 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2301 sky2->flow_status = FC_NONE;
2303 if (sky2->flow_status & FC_TX)
2304 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2306 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2311 /* Interrupt from PHY */
2312 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2314 struct net_device *dev = hw->dev[port];
2315 struct sky2_port *sky2 = netdev_priv(dev);
2316 u16 istatus, phystat;
2318 if (!netif_running(dev))
2321 spin_lock(&sky2->phy_lock);
2322 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2323 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2325 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2328 if (istatus & PHY_M_IS_AN_COMPL) {
2329 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2330 !netif_carrier_ok(dev))
2335 if (istatus & PHY_M_IS_LSP_CHANGE)
2336 sky2->speed = sky2_phy_speed(hw, phystat);
2338 if (istatus & PHY_M_IS_DUP_CHANGE)
2340 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2342 if (istatus & PHY_M_IS_LST_CHANGE) {
2343 if (phystat & PHY_M_PS_LINK_UP)
2346 sky2_link_down(sky2);
2349 spin_unlock(&sky2->phy_lock);
2352 /* Special quick link interrupt (Yukon-2 Optima only) */
2353 static void sky2_qlink_intr(struct sky2_hw *hw)
2355 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2360 imask = sky2_read32(hw, B0_IMSK);
2361 imask &= ~Y2_IS_PHY_QLNK;
2362 sky2_write32(hw, B0_IMSK, imask);
2364 /* reset PHY Link Detect */
2365 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2366 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2367 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2368 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2373 /* Transmit timeout is only called if we are running, carrier is up
2374 * and tx queue is full (stopped).
2376 static void sky2_tx_timeout(struct net_device *dev)
2378 struct sky2_port *sky2 = netdev_priv(dev);
2379 struct sky2_hw *hw = sky2->hw;
2381 netif_err(sky2, timer, dev, "tx timeout\n");
2383 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2384 sky2->tx_cons, sky2->tx_prod,
2385 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2386 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2388 /* can't restart safely under softirq */
2389 schedule_work(&hw->restart_work);
2392 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2394 struct sky2_port *sky2 = netdev_priv(dev);
2395 struct sky2_hw *hw = sky2->hw;
2396 unsigned port = sky2->port;
2401 if (!netif_running(dev)) {
2403 netdev_update_features(dev);
2407 imask = sky2_read32(hw, B0_IMSK);
2408 sky2_write32(hw, B0_IMSK, 0);
2409 sky2_read32(hw, B0_IMSK);
2411 netif_trans_update(dev); /* prevent tx timeout */
2412 napi_disable(&hw->napi);
2413 netif_tx_disable(dev);
2415 synchronize_irq(hw->pdev->irq);
2417 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2418 sky2_set_tx_stfwd(hw, port);
2420 ctl = gma_read16(hw, port, GM_GP_CTRL);
2421 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2423 sky2_rx_clean(sky2);
2426 netdev_update_features(dev);
2428 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2429 if (sky2->speed > SPEED_100)
2430 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2432 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2434 if (dev->mtu > ETH_DATA_LEN)
2435 mode |= GM_SMOD_JUMBO_ENA;
2437 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2439 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2441 err = sky2_alloc_rx_skbs(sky2);
2443 sky2_rx_start(sky2);
2445 sky2_rx_clean(sky2);
2446 sky2_write32(hw, B0_IMSK, imask);
2448 sky2_read32(hw, B0_Y2_SP_LISR);
2449 napi_enable(&hw->napi);
2454 gma_write16(hw, port, GM_GP_CTRL, ctl);
2456 netif_wake_queue(dev);
2462 static inline bool needs_copy(const struct rx_ring_info *re,
2465 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2466 /* Some architectures need the IP header to be aligned */
2467 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2470 return length < copybreak;
2473 /* For small just reuse existing skb for next receive */
2474 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2475 const struct rx_ring_info *re,
2478 struct sk_buff *skb;
2480 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2482 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2483 length, PCI_DMA_FROMDEVICE);
2484 skb_copy_from_linear_data(re->skb, skb->data, length);
2485 skb->ip_summed = re->skb->ip_summed;
2486 skb->csum = re->skb->csum;
2487 skb_copy_hash(skb, re->skb);
2488 __vlan_hwaccel_copy_tag(skb, re->skb);
2490 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2491 length, PCI_DMA_FROMDEVICE);
2492 __vlan_hwaccel_clear_tag(re->skb);
2493 skb_clear_hash(re->skb);
2494 re->skb->ip_summed = CHECKSUM_NONE;
2495 skb_put(skb, length);
2500 /* Adjust length of skb with fragments to match received data */
2501 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2502 unsigned int length)
2507 /* put header into skb */
2508 size = min(length, hdr_space);
2513 num_frags = skb_shinfo(skb)->nr_frags;
2514 for (i = 0; i < num_frags; i++) {
2515 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2518 /* don't need this page */
2519 __skb_frag_unref(frag);
2520 --skb_shinfo(skb)->nr_frags;
2522 size = min(length, (unsigned) PAGE_SIZE);
2524 skb_frag_size_set(frag, size);
2525 skb->data_len += size;
2526 skb->truesize += PAGE_SIZE;
2533 /* Normal packet - take skb from ring element and put in a new one */
2534 static struct sk_buff *receive_new(struct sky2_port *sky2,
2535 struct rx_ring_info *re,
2536 unsigned int length)
2538 struct sk_buff *skb;
2539 struct rx_ring_info nre;
2540 unsigned hdr_space = sky2->rx_data_size;
2542 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2543 if (unlikely(!nre.skb))
2546 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2550 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2551 prefetch(skb->data);
2554 if (skb_shinfo(skb)->nr_frags)
2555 skb_put_frags(skb, hdr_space, length);
2557 skb_put(skb, length);
2561 dev_kfree_skb(nre.skb);
2567 * Receive one packet.
2568 * For larger packets, get new buffer.
2570 static struct sk_buff *sky2_receive(struct net_device *dev,
2571 u16 length, u32 status)
2573 struct sky2_port *sky2 = netdev_priv(dev);
2574 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2575 struct sk_buff *skb = NULL;
2576 u16 count = (status & GMR_FS_LEN) >> 16;
2578 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2579 "rx slot %u status 0x%x len %d\n",
2580 sky2->rx_next, status, length);
2582 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2583 prefetch(sky2->rx_ring + sky2->rx_next);
2585 if (skb_vlan_tag_present(re->skb))
2586 count -= VLAN_HLEN; /* Account for vlan tag */
2588 /* This chip has hardware problems that generates bogus status.
2589 * So do only marginal checking and expect higher level protocols
2590 * to handle crap frames.
2592 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2593 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2597 if (status & GMR_FS_ANY_ERR)
2600 if (!(status & GMR_FS_RX_OK))
2603 /* if length reported by DMA does not match PHY, packet was truncated */
2604 if (length != count)
2608 if (needs_copy(re, length))
2609 skb = receive_copy(sky2, re, length);
2611 skb = receive_new(sky2, re, length);
2613 dev->stats.rx_dropped += (skb == NULL);
2616 sky2_rx_submit(sky2, re);
2621 ++dev->stats.rx_errors;
2623 if (net_ratelimit())
2624 netif_info(sky2, rx_err, dev,
2625 "rx error, status 0x%x length %d\n", status, length);
2630 /* Transmit complete */
2631 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2633 struct sky2_port *sky2 = netdev_priv(dev);
2635 if (netif_running(dev)) {
2636 sky2_tx_complete(sky2, last);
2638 /* Wake unless it's detached, and called e.g. from sky2_close() */
2639 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2640 netif_wake_queue(dev);
2644 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2645 struct sk_buff *skb)
2647 if (skb->ip_summed == CHECKSUM_NONE)
2648 netif_receive_skb(skb);
2650 napi_gro_receive(&sky2->hw->napi, skb);
2653 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2654 unsigned packets, unsigned bytes)
2656 struct net_device *dev = hw->dev[port];
2657 struct sky2_port *sky2 = netdev_priv(dev);
2662 u64_stats_update_begin(&sky2->rx_stats.syncp);
2663 sky2->rx_stats.packets += packets;
2664 sky2->rx_stats.bytes += bytes;
2665 u64_stats_update_end(&sky2->rx_stats.syncp);
2667 sky2->last_rx = jiffies;
2668 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2671 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2673 /* If this happens then driver assuming wrong format for chip type */
2674 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2676 /* Both checksum counters are programmed to start at
2677 * the same offset, so unless there is a problem they
2678 * should match. This failure is an early indication that
2679 * hardware receive checksumming won't work.
2681 if (likely((u16)(status >> 16) == (u16)status)) {
2682 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2683 skb->ip_summed = CHECKSUM_COMPLETE;
2684 skb->csum = le16_to_cpu(status);
2686 dev_notice(&sky2->hw->pdev->dev,
2687 "%s: receive checksum problem (status = %#x)\n",
2688 sky2->netdev->name, status);
2690 /* Disable checksum offload
2691 * It will be reenabled on next ndo_set_features, but if it's
2692 * really broken, will get disabled again
2694 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2695 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2700 static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2702 struct sk_buff *skb;
2704 skb = sky2->rx_ring[sky2->rx_next].skb;
2705 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2708 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2710 struct sk_buff *skb;
2712 skb = sky2->rx_ring[sky2->rx_next].skb;
2713 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3);
2716 /* Process status response ring */
2717 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2720 unsigned int total_bytes[2] = { 0 };
2721 unsigned int total_packets[2] = { 0 };
2728 struct sky2_port *sky2;
2729 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2731 struct net_device *dev;
2732 struct sk_buff *skb;
2735 u8 opcode = le->opcode;
2737 if (!(opcode & HW_OWNER))
2740 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2742 port = le->css & CSS_LINK_BIT;
2743 dev = hw->dev[port];
2744 sky2 = netdev_priv(dev);
2745 length = le16_to_cpu(le->length);
2746 status = le32_to_cpu(le->status);
2749 switch (opcode & ~HW_OWNER) {
2751 total_packets[port]++;
2752 total_bytes[port] += length;
2754 skb = sky2_receive(dev, length, status);
2758 /* This chip reports checksum status differently */
2759 if (hw->flags & SKY2_HW_NEW_LE) {
2760 if ((dev->features & NETIF_F_RXCSUM) &&
2761 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2762 (le->css & CSS_TCPUDPCSOK))
2763 skb->ip_summed = CHECKSUM_UNNECESSARY;
2765 skb->ip_summed = CHECKSUM_NONE;
2768 skb->protocol = eth_type_trans(skb, dev);
2769 sky2_skb_rx(sky2, skb);
2771 /* Stop after net poll weight */
2772 if (++work_done >= to_do)
2777 sky2_rx_tag(sky2, length);
2781 sky2_rx_tag(sky2, length);
2784 if (likely(dev->features & NETIF_F_RXCSUM))
2785 sky2_rx_checksum(sky2, status);
2789 sky2_rx_hash(sky2, status);
2793 /* TX index reports status for both ports */
2794 sky2_tx_done(hw->dev[0], status & 0xfff);
2796 sky2_tx_done(hw->dev[1],
2797 ((status >> 24) & 0xff)
2798 | (u16)(length & 0xf) << 8);
2802 if (net_ratelimit())
2803 pr_warn("unknown status opcode 0x%x\n", opcode);
2805 } while (hw->st_idx != idx);
2807 /* Fully processed status ring so clear irq */
2808 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2811 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2812 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2817 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2819 struct net_device *dev = hw->dev[port];
2821 if (net_ratelimit())
2822 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2824 if (status & Y2_IS_PAR_RD1) {
2825 if (net_ratelimit())
2826 netdev_err(dev, "ram data read parity error\n");
2828 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2831 if (status & Y2_IS_PAR_WR1) {
2832 if (net_ratelimit())
2833 netdev_err(dev, "ram data write parity error\n");
2835 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2838 if (status & Y2_IS_PAR_MAC1) {
2839 if (net_ratelimit())
2840 netdev_err(dev, "MAC parity error\n");
2841 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2844 if (status & Y2_IS_PAR_RX1) {
2845 if (net_ratelimit())
2846 netdev_err(dev, "RX parity error\n");
2847 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2850 if (status & Y2_IS_TCP_TXA1) {
2851 if (net_ratelimit())
2852 netdev_err(dev, "TCP segmentation error\n");
2853 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2857 static void sky2_hw_intr(struct sky2_hw *hw)
2859 struct pci_dev *pdev = hw->pdev;
2860 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2861 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2865 if (status & Y2_IS_TIST_OV)
2866 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2868 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2871 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2872 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2873 if (net_ratelimit())
2874 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2877 sky2_pci_write16(hw, PCI_STATUS,
2878 pci_err | PCI_STATUS_ERROR_BITS);
2879 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2882 if (status & Y2_IS_PCI_EXP) {
2883 /* PCI-Express uncorrectable Error occurred */
2886 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2887 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2888 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2890 if (net_ratelimit())
2891 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2893 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2894 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2897 if (status & Y2_HWE_L1_MASK)
2898 sky2_hw_error(hw, 0, status);
2900 if (status & Y2_HWE_L1_MASK)
2901 sky2_hw_error(hw, 1, status);
2904 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2906 struct net_device *dev = hw->dev[port];
2907 struct sky2_port *sky2 = netdev_priv(dev);
2908 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2910 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2912 if (status & GM_IS_RX_CO_OV)
2913 gma_read16(hw, port, GM_RX_IRQ_SRC);
2915 if (status & GM_IS_TX_CO_OV)
2916 gma_read16(hw, port, GM_TX_IRQ_SRC);
2918 if (status & GM_IS_RX_FF_OR) {
2919 ++dev->stats.rx_fifo_errors;
2920 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2923 if (status & GM_IS_TX_FF_UR) {
2924 ++dev->stats.tx_fifo_errors;
2925 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2929 /* This should never happen it is a bug. */
2930 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2932 struct net_device *dev = hw->dev[port];
2933 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2935 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2936 dev->name, (unsigned) q, (unsigned) idx,
2937 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2939 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2942 static int sky2_rx_hung(struct net_device *dev)
2944 struct sky2_port *sky2 = netdev_priv(dev);
2945 struct sky2_hw *hw = sky2->hw;
2946 unsigned port = sky2->port;
2947 unsigned rxq = rxqaddr[port];
2948 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2949 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2950 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2951 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2953 /* If idle and MAC or PCI is stuck */
2954 if (sky2->check.last == sky2->last_rx &&
2955 ((mac_rp == sky2->check.mac_rp &&
2956 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2957 /* Check if the PCI RX hang */
2958 (fifo_rp == sky2->check.fifo_rp &&
2959 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2960 netdev_printk(KERN_DEBUG, dev,
2961 "hung mac %d:%d fifo %d (%d:%d)\n",
2962 mac_lev, mac_rp, fifo_lev,
2963 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2966 sky2->check.last = sky2->last_rx;
2967 sky2->check.mac_rp = mac_rp;
2968 sky2->check.mac_lev = mac_lev;
2969 sky2->check.fifo_rp = fifo_rp;
2970 sky2->check.fifo_lev = fifo_lev;
2975 static void sky2_watchdog(struct timer_list *t)
2977 struct sky2_hw *hw = from_timer(hw, t, watchdog_timer);
2979 /* Check for lost IRQ once a second */
2980 if (sky2_read32(hw, B0_ISRC)) {
2981 napi_schedule(&hw->napi);
2985 for (i = 0; i < hw->ports; i++) {
2986 struct net_device *dev = hw->dev[i];
2987 if (!netif_running(dev))
2991 /* For chips with Rx FIFO, check if stuck */
2992 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2993 sky2_rx_hung(dev)) {
2994 netdev_info(dev, "receiver hang detected\n");
2995 schedule_work(&hw->restart_work);
3004 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
3007 /* Hardware/software error handling */
3008 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
3010 if (net_ratelimit())
3011 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
3013 if (status & Y2_IS_HW_ERR)
3016 if (status & Y2_IS_IRQ_MAC1)
3017 sky2_mac_intr(hw, 0);
3019 if (status & Y2_IS_IRQ_MAC2)
3020 sky2_mac_intr(hw, 1);
3022 if (status & Y2_IS_CHK_RX1)
3023 sky2_le_error(hw, 0, Q_R1);
3025 if (status & Y2_IS_CHK_RX2)
3026 sky2_le_error(hw, 1, Q_R2);
3028 if (status & Y2_IS_CHK_TXA1)
3029 sky2_le_error(hw, 0, Q_XA1);
3031 if (status & Y2_IS_CHK_TXA2)
3032 sky2_le_error(hw, 1, Q_XA2);
3035 static int sky2_poll(struct napi_struct *napi, int work_limit)
3037 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3038 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3042 if (unlikely(status & Y2_IS_ERROR))
3043 sky2_err_intr(hw, status);
3045 if (status & Y2_IS_IRQ_PHY1)
3046 sky2_phy_intr(hw, 0);
3048 if (status & Y2_IS_IRQ_PHY2)
3049 sky2_phy_intr(hw, 1);
3051 if (status & Y2_IS_PHY_QLNK)
3052 sky2_qlink_intr(hw);
3054 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3055 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3057 if (work_done >= work_limit)
3061 napi_complete_done(napi, work_done);
3062 sky2_read32(hw, B0_Y2_SP_LISR);
3068 static irqreturn_t sky2_intr(int irq, void *dev_id)
3070 struct sky2_hw *hw = dev_id;
3073 /* Reading this mask interrupts as side effect */
3074 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3075 if (status == 0 || status == ~0) {
3076 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3080 prefetch(&hw->st_le[hw->st_idx]);
3082 napi_schedule(&hw->napi);
3087 #ifdef CONFIG_NET_POLL_CONTROLLER
3088 static void sky2_netpoll(struct net_device *dev)
3090 struct sky2_port *sky2 = netdev_priv(dev);
3092 napi_schedule(&sky2->hw->napi);
3096 /* Chip internal frequency for clock calculations */
3097 static u32 sky2_mhz(const struct sky2_hw *hw)
3099 switch (hw->chip_id) {
3100 case CHIP_ID_YUKON_EC:
3101 case CHIP_ID_YUKON_EC_U:
3102 case CHIP_ID_YUKON_EX:
3103 case CHIP_ID_YUKON_SUPR:
3104 case CHIP_ID_YUKON_UL_2:
3105 case CHIP_ID_YUKON_OPT:
3106 case CHIP_ID_YUKON_PRM:
3107 case CHIP_ID_YUKON_OP_2:
3110 case CHIP_ID_YUKON_FE:
3113 case CHIP_ID_YUKON_FE_P:
3116 case CHIP_ID_YUKON_XL:
3124 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3126 return sky2_mhz(hw) * us;
3129 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3131 return clk / sky2_mhz(hw);
3135 static int sky2_init(struct sky2_hw *hw)
3139 /* Enable all clocks and check for bad PCI access */
3140 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3142 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3144 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3145 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3147 switch (hw->chip_id) {
3148 case CHIP_ID_YUKON_XL:
3149 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3150 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3151 hw->flags |= SKY2_HW_RSS_BROKEN;
3154 case CHIP_ID_YUKON_EC_U:
3155 hw->flags = SKY2_HW_GIGABIT
3157 | SKY2_HW_ADV_POWER_CTL;
3160 case CHIP_ID_YUKON_EX:
3161 hw->flags = SKY2_HW_GIGABIT
3164 | SKY2_HW_ADV_POWER_CTL
3165 | SKY2_HW_RSS_CHKSUM;
3167 /* New transmit checksum */
3168 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3169 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3172 case CHIP_ID_YUKON_EC:
3173 /* This rev is really old, and requires untested workarounds */
3174 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3175 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3178 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3181 case CHIP_ID_YUKON_FE:
3182 hw->flags = SKY2_HW_RSS_BROKEN;
3185 case CHIP_ID_YUKON_FE_P:
3186 hw->flags = SKY2_HW_NEWER_PHY
3188 | SKY2_HW_AUTO_TX_SUM
3189 | SKY2_HW_ADV_POWER_CTL;
3191 /* The workaround for status conflicts VLAN tag detection. */
3192 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3193 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3196 case CHIP_ID_YUKON_SUPR:
3197 hw->flags = SKY2_HW_GIGABIT
3200 | SKY2_HW_AUTO_TX_SUM
3201 | SKY2_HW_ADV_POWER_CTL;
3203 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3204 hw->flags |= SKY2_HW_RSS_CHKSUM;
3207 case CHIP_ID_YUKON_UL_2:
3208 hw->flags = SKY2_HW_GIGABIT
3209 | SKY2_HW_ADV_POWER_CTL;
3212 case CHIP_ID_YUKON_OPT:
3213 case CHIP_ID_YUKON_PRM:
3214 case CHIP_ID_YUKON_OP_2:
3215 hw->flags = SKY2_HW_GIGABIT
3217 | SKY2_HW_ADV_POWER_CTL;
3221 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3226 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3227 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3228 hw->flags |= SKY2_HW_FIBRE_PHY;
3231 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3232 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3233 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3237 if (sky2_read8(hw, B2_E_0))
3238 hw->flags |= SKY2_HW_RAM_BUFFER;
3243 static void sky2_reset(struct sky2_hw *hw)
3245 struct pci_dev *pdev = hw->pdev;
3248 u32 hwe_mask = Y2_HWE_ALL_MASK;
3251 if (hw->chip_id == CHIP_ID_YUKON_EX
3252 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3253 sky2_write32(hw, CPU_WDOG, 0);
3254 status = sky2_read16(hw, HCU_CCSR);
3255 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3256 HCU_CCSR_UC_STATE_MSK);
3258 * CPU clock divider shouldn't be used because
3259 * - ASF firmware may malfunction
3260 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3262 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3263 sky2_write16(hw, HCU_CCSR, status);
3264 sky2_write32(hw, CPU_WDOG, 0);
3266 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3267 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3270 sky2_write8(hw, B0_CTST, CS_RST_SET);
3271 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3273 /* allow writes to PCI config */
3274 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3276 /* clear PCI errors, if any */
3277 status = sky2_pci_read16(hw, PCI_STATUS);
3278 status |= PCI_STATUS_ERROR_BITS;
3279 sky2_pci_write16(hw, PCI_STATUS, status);
3281 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3283 if (pci_is_pcie(pdev)) {
3284 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3287 /* If error bit is stuck on ignore it */
3288 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3289 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3291 hwe_mask |= Y2_IS_PCI_EXP;
3295 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3297 for (i = 0; i < hw->ports; i++) {
3298 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3299 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3301 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3302 hw->chip_id == CHIP_ID_YUKON_SUPR)
3303 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3304 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3309 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3310 /* enable MACSec clock gating */
3311 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3314 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3315 hw->chip_id == CHIP_ID_YUKON_PRM ||
3316 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3319 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3320 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3321 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3323 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3326 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3327 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3329 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3333 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3334 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3336 /* reset PHY Link Detect */
3337 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3338 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3340 /* check if PSMv2 was running before */
3341 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3342 if (reg & PCI_EXP_LNKCTL_ASPMC)
3343 /* restore the PCIe Link Control register */
3344 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3347 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3348 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3349 /* change PHY Interrupt polarity to low active */
3350 reg = sky2_read16(hw, GPHY_CTRL);
3351 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3353 /* adapt HW for low active PHY Interrupt */
3354 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3355 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3358 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3360 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3361 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3364 /* Clear I2C IRQ noise */
3365 sky2_write32(hw, B2_I2C_IRQ, 1);
3367 /* turn off hardware timer (unused) */
3368 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3369 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3371 /* Turn off descriptor polling */
3372 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3374 /* Turn off receive timestamp */
3375 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3376 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3378 /* enable the Tx Arbiters */
3379 for (i = 0; i < hw->ports; i++)
3380 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3382 /* Initialize ram interface */
3383 for (i = 0; i < hw->ports; i++) {
3384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3395 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3400 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3402 for (i = 0; i < hw->ports; i++)
3403 sky2_gmac_reset(hw, i);
3405 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3408 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3409 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3411 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3412 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3414 /* Set the list last index */
3415 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3417 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3418 sky2_write8(hw, STAT_FIFO_WM, 16);
3420 /* set Status-FIFO ISR watermark */
3421 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3422 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3424 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3426 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3427 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3428 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3430 /* enable status unit */
3431 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3433 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3434 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3435 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3438 /* Take device down (offline).
3439 * Equivalent to doing dev_stop() but this does not
3440 * inform upper layers of the transition.
3442 static void sky2_detach(struct net_device *dev)
3444 if (netif_running(dev)) {
3446 netif_device_detach(dev); /* stop txq */
3447 netif_tx_unlock(dev);
3452 /* Bring device back after doing sky2_detach */
3453 static int sky2_reattach(struct net_device *dev)
3457 if (netif_running(dev)) {
3458 err = sky2_open(dev);
3460 netdev_info(dev, "could not restart %d\n", err);
3463 netif_device_attach(dev);
3464 sky2_set_multicast(dev);
3471 static void sky2_all_down(struct sky2_hw *hw)
3475 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3476 sky2_write32(hw, B0_IMSK, 0);
3477 sky2_read32(hw, B0_IMSK);
3479 synchronize_irq(hw->pdev->irq);
3480 napi_disable(&hw->napi);
3483 for (i = 0; i < hw->ports; i++) {
3484 struct net_device *dev = hw->dev[i];
3485 struct sky2_port *sky2 = netdev_priv(dev);
3487 if (!netif_running(dev))
3490 netif_carrier_off(dev);
3491 netif_tx_disable(dev);
3496 static void sky2_all_up(struct sky2_hw *hw)
3498 u32 imask = Y2_IS_BASE;
3501 for (i = 0; i < hw->ports; i++) {
3502 struct net_device *dev = hw->dev[i];
3503 struct sky2_port *sky2 = netdev_priv(dev);
3505 if (!netif_running(dev))
3509 sky2_set_multicast(dev);
3510 imask |= portirq_msk[i];
3511 netif_wake_queue(dev);
3514 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3515 sky2_write32(hw, B0_IMSK, imask);
3516 sky2_read32(hw, B0_IMSK);
3517 sky2_read32(hw, B0_Y2_SP_LISR);
3518 napi_enable(&hw->napi);
3522 static void sky2_restart(struct work_struct *work)
3524 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3535 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3537 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3540 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3542 const struct sky2_port *sky2 = netdev_priv(dev);
3544 wol->supported = sky2_wol_supported(sky2->hw);
3545 wol->wolopts = sky2->wol;
3548 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3550 struct sky2_port *sky2 = netdev_priv(dev);
3551 struct sky2_hw *hw = sky2->hw;
3552 bool enable_wakeup = false;
3555 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3556 !device_can_wakeup(&hw->pdev->dev))
3559 sky2->wol = wol->wolopts;
3561 for (i = 0; i < hw->ports; i++) {
3562 struct net_device *dev = hw->dev[i];
3563 struct sky2_port *sky2 = netdev_priv(dev);
3566 enable_wakeup = true;
3568 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3573 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3575 if (sky2_is_copper(hw)) {
3576 u32 modes = SUPPORTED_10baseT_Half
3577 | SUPPORTED_10baseT_Full
3578 | SUPPORTED_100baseT_Half
3579 | SUPPORTED_100baseT_Full;
3581 if (hw->flags & SKY2_HW_GIGABIT)
3582 modes |= SUPPORTED_1000baseT_Half
3583 | SUPPORTED_1000baseT_Full;
3586 return SUPPORTED_1000baseT_Half
3587 | SUPPORTED_1000baseT_Full;
3590 static int sky2_get_link_ksettings(struct net_device *dev,
3591 struct ethtool_link_ksettings *cmd)
3593 struct sky2_port *sky2 = netdev_priv(dev);
3594 struct sky2_hw *hw = sky2->hw;
3595 u32 supported, advertising;
3597 supported = sky2_supported_modes(hw);
3598 cmd->base.phy_address = PHY_ADDR_MARV;
3599 if (sky2_is_copper(hw)) {
3600 cmd->base.port = PORT_TP;
3601 cmd->base.speed = sky2->speed;
3602 supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3604 cmd->base.speed = SPEED_1000;
3605 cmd->base.port = PORT_FIBRE;
3606 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3609 advertising = sky2->advertising;
3610 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3611 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3612 cmd->base.duplex = sky2->duplex;
3614 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3616 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3622 static int sky2_set_link_ksettings(struct net_device *dev,
3623 const struct ethtool_link_ksettings *cmd)
3625 struct sky2_port *sky2 = netdev_priv(dev);
3626 const struct sky2_hw *hw = sky2->hw;
3627 u32 supported = sky2_supported_modes(hw);
3628 u32 new_advertising;
3630 ethtool_convert_link_mode_to_legacy_u32(&new_advertising,
3631 cmd->link_modes.advertising);
3633 if (cmd->base.autoneg == AUTONEG_ENABLE) {
3634 if (new_advertising & ~supported)
3637 if (sky2_is_copper(hw))
3638 sky2->advertising = new_advertising |
3642 sky2->advertising = new_advertising |
3646 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3651 u32 speed = cmd->base.speed;
3655 if (cmd->base.duplex == DUPLEX_FULL)
3656 setting = SUPPORTED_1000baseT_Full;
3657 else if (cmd->base.duplex == DUPLEX_HALF)
3658 setting = SUPPORTED_1000baseT_Half;
3663 if (cmd->base.duplex == DUPLEX_FULL)
3664 setting = SUPPORTED_100baseT_Full;
3665 else if (cmd->base.duplex == DUPLEX_HALF)
3666 setting = SUPPORTED_100baseT_Half;
3672 if (cmd->base.duplex == DUPLEX_FULL)
3673 setting = SUPPORTED_10baseT_Full;
3674 else if (cmd->base.duplex == DUPLEX_HALF)
3675 setting = SUPPORTED_10baseT_Half;
3683 if ((setting & supported) == 0)
3686 sky2->speed = speed;
3687 sky2->duplex = cmd->base.duplex;
3688 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3691 if (netif_running(dev)) {
3692 sky2_phy_reinit(sky2);
3693 sky2_set_multicast(dev);
3699 static void sky2_get_drvinfo(struct net_device *dev,
3700 struct ethtool_drvinfo *info)
3702 struct sky2_port *sky2 = netdev_priv(dev);
3704 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3705 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3706 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3707 sizeof(info->bus_info));
3710 static const struct sky2_stat {
3711 char name[ETH_GSTRING_LEN];
3714 { "tx_bytes", GM_TXO_OK_HI },
3715 { "rx_bytes", GM_RXO_OK_HI },
3716 { "tx_broadcast", GM_TXF_BC_OK },
3717 { "rx_broadcast", GM_RXF_BC_OK },
3718 { "tx_multicast", GM_TXF_MC_OK },
3719 { "rx_multicast", GM_RXF_MC_OK },
3720 { "tx_unicast", GM_TXF_UC_OK },
3721 { "rx_unicast", GM_RXF_UC_OK },
3722 { "tx_mac_pause", GM_TXF_MPAUSE },
3723 { "rx_mac_pause", GM_RXF_MPAUSE },
3724 { "collisions", GM_TXF_COL },
3725 { "late_collision",GM_TXF_LAT_COL },
3726 { "aborted", GM_TXF_ABO_COL },
3727 { "single_collisions", GM_TXF_SNG_COL },
3728 { "multi_collisions", GM_TXF_MUL_COL },
3730 { "rx_short", GM_RXF_SHT },
3731 { "rx_runt", GM_RXE_FRAG },
3732 { "rx_64_byte_packets", GM_RXF_64B },
3733 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3734 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3735 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3736 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3737 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3738 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3739 { "rx_too_long", GM_RXF_LNG_ERR },
3740 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3741 { "rx_jabber", GM_RXF_JAB_PKT },
3742 { "rx_fcs_error", GM_RXF_FCS_ERR },
3744 { "tx_64_byte_packets", GM_TXF_64B },
3745 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3746 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3747 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3748 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3749 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3750 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3751 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3754 static u32 sky2_get_msglevel(struct net_device *netdev)
3756 struct sky2_port *sky2 = netdev_priv(netdev);
3757 return sky2->msg_enable;
3760 static int sky2_nway_reset(struct net_device *dev)
3762 struct sky2_port *sky2 = netdev_priv(dev);
3764 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3767 sky2_phy_reinit(sky2);
3768 sky2_set_multicast(dev);
3773 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3775 struct sky2_hw *hw = sky2->hw;
3776 unsigned port = sky2->port;
3779 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3780 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3782 for (i = 2; i < count; i++)
3783 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3786 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3788 struct sky2_port *sky2 = netdev_priv(netdev);
3789 sky2->msg_enable = value;
3792 static int sky2_get_sset_count(struct net_device *dev, int sset)
3796 return ARRAY_SIZE(sky2_stats);
3802 static void sky2_get_ethtool_stats(struct net_device *dev,
3803 struct ethtool_stats *stats, u64 * data)
3805 struct sky2_port *sky2 = netdev_priv(dev);
3807 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3810 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3814 switch (stringset) {
3816 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3817 memcpy(data + i * ETH_GSTRING_LEN,
3818 sky2_stats[i].name, ETH_GSTRING_LEN);
3823 static int sky2_set_mac_address(struct net_device *dev, void *p)
3825 struct sky2_port *sky2 = netdev_priv(dev);
3826 struct sky2_hw *hw = sky2->hw;
3827 unsigned port = sky2->port;
3828 const struct sockaddr *addr = p;
3830 if (!is_valid_ether_addr(addr->sa_data))
3831 return -EADDRNOTAVAIL;
3833 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3834 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3835 dev->dev_addr, ETH_ALEN);
3836 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3837 dev->dev_addr, ETH_ALEN);
3839 /* virtual address for data */
3840 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3842 /* physical address: used for pause frames */
3843 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3848 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3852 bit = ether_crc(ETH_ALEN, addr) & 63;
3853 filter[bit >> 3] |= 1 << (bit & 7);
3856 static void sky2_set_multicast(struct net_device *dev)
3858 struct sky2_port *sky2 = netdev_priv(dev);
3859 struct sky2_hw *hw = sky2->hw;
3860 unsigned port = sky2->port;
3861 struct netdev_hw_addr *ha;
3865 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3867 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3868 memset(filter, 0, sizeof(filter));
3870 reg = gma_read16(hw, port, GM_RX_CTRL);
3871 reg |= GM_RXCR_UCF_ENA;
3873 if (dev->flags & IFF_PROMISC) /* promiscuous */
3874 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3875 else if (dev->flags & IFF_ALLMULTI)
3876 memset(filter, 0xff, sizeof(filter));
3877 else if (netdev_mc_empty(dev) && !rx_pause)
3878 reg &= ~GM_RXCR_MCF_ENA;
3880 reg |= GM_RXCR_MCF_ENA;
3883 sky2_add_filter(filter, pause_mc_addr);
3885 netdev_for_each_mc_addr(ha, dev)
3886 sky2_add_filter(filter, ha->addr);
3889 gma_write16(hw, port, GM_MC_ADDR_H1,
3890 (u16) filter[0] | ((u16) filter[1] << 8));
3891 gma_write16(hw, port, GM_MC_ADDR_H2,
3892 (u16) filter[2] | ((u16) filter[3] << 8));
3893 gma_write16(hw, port, GM_MC_ADDR_H3,
3894 (u16) filter[4] | ((u16) filter[5] << 8));
3895 gma_write16(hw, port, GM_MC_ADDR_H4,
3896 (u16) filter[6] | ((u16) filter[7] << 8));
3898 gma_write16(hw, port, GM_RX_CTRL, reg);
3901 static void sky2_get_stats(struct net_device *dev,
3902 struct rtnl_link_stats64 *stats)
3904 struct sky2_port *sky2 = netdev_priv(dev);
3905 struct sky2_hw *hw = sky2->hw;
3906 unsigned port = sky2->port;
3908 u64 _bytes, _packets;
3911 start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp);
3912 _bytes = sky2->rx_stats.bytes;
3913 _packets = sky2->rx_stats.packets;
3914 } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start));
3916 stats->rx_packets = _packets;
3917 stats->rx_bytes = _bytes;
3920 start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp);
3921 _bytes = sky2->tx_stats.bytes;
3922 _packets = sky2->tx_stats.packets;
3923 } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start));
3925 stats->tx_packets = _packets;
3926 stats->tx_bytes = _bytes;
3928 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3929 + get_stats32(hw, port, GM_RXF_BC_OK);
3931 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3933 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3934 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3935 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3936 + get_stats32(hw, port, GM_RXE_FRAG);
3937 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3939 stats->rx_dropped = dev->stats.rx_dropped;
3940 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3941 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3944 /* Can have one global because blinking is controlled by
3945 * ethtool and that is always under RTNL mutex
3947 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3949 struct sky2_hw *hw = sky2->hw;
3950 unsigned port = sky2->port;
3952 spin_lock_bh(&sky2->phy_lock);
3953 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3954 hw->chip_id == CHIP_ID_YUKON_EX ||
3955 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3957 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3958 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3962 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3963 PHY_M_LEDC_LOS_CTRL(8) |
3964 PHY_M_LEDC_INIT_CTRL(8) |
3965 PHY_M_LEDC_STA1_CTRL(8) |
3966 PHY_M_LEDC_STA0_CTRL(8));
3969 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3970 PHY_M_LEDC_LOS_CTRL(9) |
3971 PHY_M_LEDC_INIT_CTRL(9) |
3972 PHY_M_LEDC_STA1_CTRL(9) |
3973 PHY_M_LEDC_STA0_CTRL(9));
3976 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3977 PHY_M_LEDC_LOS_CTRL(0xa) |
3978 PHY_M_LEDC_INIT_CTRL(0xa) |
3979 PHY_M_LEDC_STA1_CTRL(0xa) |
3980 PHY_M_LEDC_STA0_CTRL(0xa));
3983 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3984 PHY_M_LEDC_LOS_CTRL(1) |
3985 PHY_M_LEDC_INIT_CTRL(8) |
3986 PHY_M_LEDC_STA1_CTRL(7) |
3987 PHY_M_LEDC_STA0_CTRL(7));
3990 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3992 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3993 PHY_M_LED_MO_DUP(mode) |
3994 PHY_M_LED_MO_10(mode) |
3995 PHY_M_LED_MO_100(mode) |
3996 PHY_M_LED_MO_1000(mode) |
3997 PHY_M_LED_MO_RX(mode) |
3998 PHY_M_LED_MO_TX(mode));
4000 spin_unlock_bh(&sky2->phy_lock);
4003 /* blink LED's for finding board */
4004 static int sky2_set_phys_id(struct net_device *dev,
4005 enum ethtool_phys_id_state state)
4007 struct sky2_port *sky2 = netdev_priv(dev);
4010 case ETHTOOL_ID_ACTIVE:
4011 return 1; /* cycle on/off once per second */
4012 case ETHTOOL_ID_INACTIVE:
4013 sky2_led(sky2, MO_LED_NORM);
4016 sky2_led(sky2, MO_LED_ON);
4018 case ETHTOOL_ID_OFF:
4019 sky2_led(sky2, MO_LED_OFF);
4026 static void sky2_get_pauseparam(struct net_device *dev,
4027 struct ethtool_pauseparam *ecmd)
4029 struct sky2_port *sky2 = netdev_priv(dev);
4031 switch (sky2->flow_mode) {
4033 ecmd->tx_pause = ecmd->rx_pause = 0;
4036 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4039 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4042 ecmd->tx_pause = ecmd->rx_pause = 1;
4045 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4046 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4049 static int sky2_set_pauseparam(struct net_device *dev,
4050 struct ethtool_pauseparam *ecmd)
4052 struct sky2_port *sky2 = netdev_priv(dev);
4054 if (ecmd->autoneg == AUTONEG_ENABLE)
4055 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4057 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4059 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4061 if (netif_running(dev))
4062 sky2_phy_reinit(sky2);
4067 static int sky2_get_coalesce(struct net_device *dev,
4068 struct ethtool_coalesce *ecmd)
4070 struct sky2_port *sky2 = netdev_priv(dev);
4071 struct sky2_hw *hw = sky2->hw;
4073 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4074 ecmd->tx_coalesce_usecs = 0;
4076 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4077 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4079 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4081 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4082 ecmd->rx_coalesce_usecs = 0;
4084 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4085 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4087 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4089 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4090 ecmd->rx_coalesce_usecs_irq = 0;
4092 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4093 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4096 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4101 /* Note: this affect both ports */
4102 static int sky2_set_coalesce(struct net_device *dev,
4103 struct ethtool_coalesce *ecmd)
4105 struct sky2_port *sky2 = netdev_priv(dev);
4106 struct sky2_hw *hw = sky2->hw;
4107 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4109 if (ecmd->tx_coalesce_usecs > tmax ||
4110 ecmd->rx_coalesce_usecs > tmax ||
4111 ecmd->rx_coalesce_usecs_irq > tmax)
4114 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4116 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4118 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4121 if (ecmd->tx_coalesce_usecs == 0)
4122 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4124 sky2_write32(hw, STAT_TX_TIMER_INI,
4125 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4126 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4128 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4130 if (ecmd->rx_coalesce_usecs == 0)
4131 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4133 sky2_write32(hw, STAT_LEV_TIMER_INI,
4134 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4135 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4137 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4139 if (ecmd->rx_coalesce_usecs_irq == 0)
4140 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4142 sky2_write32(hw, STAT_ISR_TIMER_INI,
4143 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4144 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4146 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4151 * Hardware is limited to min of 128 and max of 2048 for ring size
4152 * and rounded up to next power of two
4153 * to avoid division in modulus calclation
4155 static unsigned long roundup_ring_size(unsigned long pending)
4157 return max(128ul, roundup_pow_of_two(pending+1));
4160 static void sky2_get_ringparam(struct net_device *dev,
4161 struct ethtool_ringparam *ering)
4163 struct sky2_port *sky2 = netdev_priv(dev);
4165 ering->rx_max_pending = RX_MAX_PENDING;
4166 ering->tx_max_pending = TX_MAX_PENDING;
4168 ering->rx_pending = sky2->rx_pending;
4169 ering->tx_pending = sky2->tx_pending;
4172 static int sky2_set_ringparam(struct net_device *dev,
4173 struct ethtool_ringparam *ering)
4175 struct sky2_port *sky2 = netdev_priv(dev);
4177 if (ering->rx_pending > RX_MAX_PENDING ||
4178 ering->rx_pending < 8 ||
4179 ering->tx_pending < TX_MIN_PENDING ||
4180 ering->tx_pending > TX_MAX_PENDING)
4185 sky2->rx_pending = ering->rx_pending;
4186 sky2->tx_pending = ering->tx_pending;
4187 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4189 return sky2_reattach(dev);
4192 static int sky2_get_regs_len(struct net_device *dev)
4197 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4199 /* This complicated switch statement is to make sure and
4200 * only access regions that are unreserved.
4201 * Some blocks are only valid on dual port cards.
4205 case 5: /* Tx Arbiter 2 */
4207 case 14 ... 15: /* TX2 */
4208 case 17: case 19: /* Ram Buffer 2 */
4209 case 22 ... 23: /* Tx Ram Buffer 2 */
4210 case 25: /* Rx MAC Fifo 1 */
4211 case 27: /* Tx MAC Fifo 2 */
4212 case 31: /* GPHY 2 */
4213 case 40 ... 47: /* Pattern Ram 2 */
4214 case 52: case 54: /* TCP Segmentation 2 */
4215 case 112 ... 116: /* GMAC 2 */
4216 return hw->ports > 1;
4218 case 0: /* Control */
4219 case 2: /* Mac address */
4220 case 4: /* Tx Arbiter 1 */
4221 case 7: /* PCI express reg */
4223 case 12 ... 13: /* TX1 */
4224 case 16: case 18:/* Rx Ram Buffer 1 */
4225 case 20 ... 21: /* Tx Ram Buffer 1 */
4226 case 24: /* Rx MAC Fifo 1 */
4227 case 26: /* Tx MAC Fifo 1 */
4228 case 28 ... 29: /* Descriptor and status unit */
4229 case 30: /* GPHY 1*/
4230 case 32 ... 39: /* Pattern Ram 1 */
4231 case 48: case 50: /* TCP Segmentation 1 */
4232 case 56 ... 60: /* PCI space */
4233 case 80 ... 84: /* GMAC 1 */
4242 * Returns copy of control register region
4243 * Note: ethtool_get_regs always provides full size (16k) buffer
4245 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4248 const struct sky2_port *sky2 = netdev_priv(dev);
4249 const void __iomem *io = sky2->hw->regs;
4254 for (b = 0; b < 128; b++) {
4255 /* skip poisonous diagnostic ram region in block 3 */
4257 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4258 else if (sky2_reg_access_ok(sky2->hw, b))
4259 memcpy_fromio(p, io, 128);
4268 static int sky2_get_eeprom_len(struct net_device *dev)
4270 struct sky2_port *sky2 = netdev_priv(dev);
4271 struct sky2_hw *hw = sky2->hw;
4274 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4275 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4278 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4280 unsigned long start = jiffies;
4282 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4283 /* Can take up to 10.6 ms for write */
4284 if (time_after(jiffies, start + HZ/4)) {
4285 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4294 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4295 u16 offset, size_t length)
4299 while (length > 0) {
4302 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4303 rc = sky2_vpd_wait(hw, cap, 0);
4307 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4309 memcpy(data, &val, min(sizeof(val), length));
4310 offset += sizeof(u32);
4311 data += sizeof(u32);
4312 length -= sizeof(u32);
4318 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4319 u16 offset, unsigned int length)
4324 for (i = 0; i < length; i += sizeof(u32)) {
4325 u32 val = *(u32 *)(data + i);
4327 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4328 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4330 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4337 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4340 struct sky2_port *sky2 = netdev_priv(dev);
4341 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4346 eeprom->magic = SKY2_EEPROM_MAGIC;
4348 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4351 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4354 struct sky2_port *sky2 = netdev_priv(dev);
4355 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4360 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4363 /* Partial writes not supported */
4364 if ((eeprom->offset & 3) || (eeprom->len & 3))
4367 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4370 static netdev_features_t sky2_fix_features(struct net_device *dev,
4371 netdev_features_t features)
4373 const struct sky2_port *sky2 = netdev_priv(dev);
4374 const struct sky2_hw *hw = sky2->hw;
4376 /* In order to do Jumbo packets on these chips, need to turn off the
4377 * transmit store/forward. Therefore checksum offload won't work.
4379 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4380 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4381 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK);
4384 /* Some hardware requires receive checksum for RSS to work. */
4385 if ( (features & NETIF_F_RXHASH) &&
4386 !(features & NETIF_F_RXCSUM) &&
4387 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4388 netdev_info(dev, "receive hashing forces receive checksum\n");
4389 features |= NETIF_F_RXCSUM;
4395 static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4397 struct sky2_port *sky2 = netdev_priv(dev);
4398 netdev_features_t changed = dev->features ^ features;
4400 if ((changed & NETIF_F_RXCSUM) &&
4401 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4402 sky2_write32(sky2->hw,
4403 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4404 (features & NETIF_F_RXCSUM)
4405 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4408 if (changed & NETIF_F_RXHASH)
4409 rx_set_rss(dev, features);
4411 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4412 sky2_vlan_mode(dev, features);
4417 static const struct ethtool_ops sky2_ethtool_ops = {
4418 .get_drvinfo = sky2_get_drvinfo,
4419 .get_wol = sky2_get_wol,
4420 .set_wol = sky2_set_wol,
4421 .get_msglevel = sky2_get_msglevel,
4422 .set_msglevel = sky2_set_msglevel,
4423 .nway_reset = sky2_nway_reset,
4424 .get_regs_len = sky2_get_regs_len,
4425 .get_regs = sky2_get_regs,
4426 .get_link = ethtool_op_get_link,
4427 .get_eeprom_len = sky2_get_eeprom_len,
4428 .get_eeprom = sky2_get_eeprom,
4429 .set_eeprom = sky2_set_eeprom,
4430 .get_strings = sky2_get_strings,
4431 .get_coalesce = sky2_get_coalesce,
4432 .set_coalesce = sky2_set_coalesce,
4433 .get_ringparam = sky2_get_ringparam,
4434 .set_ringparam = sky2_set_ringparam,
4435 .get_pauseparam = sky2_get_pauseparam,
4436 .set_pauseparam = sky2_set_pauseparam,
4437 .set_phys_id = sky2_set_phys_id,
4438 .get_sset_count = sky2_get_sset_count,
4439 .get_ethtool_stats = sky2_get_ethtool_stats,
4440 .get_link_ksettings = sky2_get_link_ksettings,
4441 .set_link_ksettings = sky2_set_link_ksettings,
4444 #ifdef CONFIG_SKY2_DEBUG
4446 static struct dentry *sky2_debug;
4450 * Read and parse the first part of Vital Product Data
4452 #define VPD_SIZE 128
4453 #define VPD_MAGIC 0x82
4455 static const struct vpd_tag {
4459 { "PN", "Part Number" },
4460 { "EC", "Engineering Level" },
4461 { "MN", "Manufacturer" },
4462 { "SN", "Serial Number" },
4463 { "YA", "Asset Tag" },
4464 { "VL", "First Error Log Message" },
4465 { "VF", "Second Error Log Message" },
4466 { "VB", "Boot Agent ROM Configuration" },
4467 { "VE", "EFI UNDI Configuration" },
4470 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4478 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4479 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4481 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4482 buf = kmalloc(vpd_size, GFP_KERNEL);
4484 seq_puts(seq, "no memory!\n");
4488 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4489 seq_puts(seq, "VPD read failed\n");
4493 if (buf[0] != VPD_MAGIC) {
4494 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4498 if (len == 0 || len > vpd_size - 4) {
4499 seq_printf(seq, "Invalid id length: %d\n", len);
4503 seq_printf(seq, "%.*s\n", len, buf + 3);
4506 while (offs < vpd_size - 4) {
4509 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4511 len = buf[offs + 2];
4512 if (offs + len + 3 >= vpd_size)
4515 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4516 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4517 seq_printf(seq, " %s: %.*s\n",
4518 vpd_tags[i].label, len, buf + offs + 3);
4528 static int sky2_debug_show(struct seq_file *seq, void *v)
4530 struct net_device *dev = seq->private;
4531 const struct sky2_port *sky2 = netdev_priv(dev);
4532 struct sky2_hw *hw = sky2->hw;
4533 unsigned port = sky2->port;
4537 sky2_show_vpd(seq, hw);
4539 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4540 sky2_read32(hw, B0_ISRC),
4541 sky2_read32(hw, B0_IMSK),
4542 sky2_read32(hw, B0_Y2_SP_ICR));
4544 if (!netif_running(dev)) {
4545 seq_puts(seq, "network not running\n");
4549 napi_disable(&hw->napi);
4550 last = sky2_read16(hw, STAT_PUT_IDX);
4552 seq_printf(seq, "Status ring %u\n", hw->st_size);
4553 if (hw->st_idx == last)
4554 seq_puts(seq, "Status ring (empty)\n");
4556 seq_puts(seq, "Status ring\n");
4557 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4558 idx = RING_NEXT(idx, hw->st_size)) {
4559 const struct sky2_status_le *le = hw->st_le + idx;
4560 seq_printf(seq, "[%d] %#x %d %#x\n",
4561 idx, le->opcode, le->length, le->status);
4563 seq_puts(seq, "\n");
4566 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4567 sky2->tx_cons, sky2->tx_prod,
4568 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4569 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4571 /* Dump contents of tx ring */
4573 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4574 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4575 const struct sky2_tx_le *le = sky2->tx_le + idx;
4576 u32 a = le32_to_cpu(le->addr);
4579 seq_printf(seq, "%u:", idx);
4582 switch (le->opcode & ~HW_OWNER) {
4584 seq_printf(seq, " %#x:", a);
4587 seq_printf(seq, " mtu=%d", a);
4590 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4593 seq_printf(seq, " csum=%#x", a);
4596 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4599 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4602 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4605 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4606 a, le16_to_cpu(le->length));
4609 if (le->ctrl & EOP) {
4610 seq_putc(seq, '\n');
4615 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4616 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4617 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4618 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4620 sky2_read32(hw, B0_Y2_SP_LISR);
4621 napi_enable(&hw->napi);
4624 DEFINE_SHOW_ATTRIBUTE(sky2_debug);
4627 * Use network device events to create/remove/rename
4628 * debugfs file entries
4630 static int sky2_device_event(struct notifier_block *unused,
4631 unsigned long event, void *ptr)
4633 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4634 struct sky2_port *sky2 = netdev_priv(dev);
4636 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4640 case NETDEV_CHANGENAME:
4641 if (sky2->debugfs) {
4642 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4643 sky2_debug, dev->name);
4647 case NETDEV_GOING_DOWN:
4648 if (sky2->debugfs) {
4649 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4650 debugfs_remove(sky2->debugfs);
4651 sky2->debugfs = NULL;
4656 sky2->debugfs = debugfs_create_file(dev->name, 0444,
4659 if (IS_ERR(sky2->debugfs))
4660 sky2->debugfs = NULL;
4666 static struct notifier_block sky2_notifier = {
4667 .notifier_call = sky2_device_event,
4671 static __init void sky2_debug_init(void)
4675 ent = debugfs_create_dir("sky2", NULL);
4676 if (!ent || IS_ERR(ent))
4680 register_netdevice_notifier(&sky2_notifier);
4683 static __exit void sky2_debug_cleanup(void)
4686 unregister_netdevice_notifier(&sky2_notifier);
4687 debugfs_remove(sky2_debug);
4693 #define sky2_debug_init()
4694 #define sky2_debug_cleanup()
4697 /* Two copies of network device operations to handle special case of
4698 not allowing netpoll on second port */
4699 static const struct net_device_ops sky2_netdev_ops[2] = {
4701 .ndo_open = sky2_open,
4702 .ndo_stop = sky2_close,
4703 .ndo_start_xmit = sky2_xmit_frame,
4704 .ndo_do_ioctl = sky2_ioctl,
4705 .ndo_validate_addr = eth_validate_addr,
4706 .ndo_set_mac_address = sky2_set_mac_address,
4707 .ndo_set_rx_mode = sky2_set_multicast,
4708 .ndo_change_mtu = sky2_change_mtu,
4709 .ndo_fix_features = sky2_fix_features,
4710 .ndo_set_features = sky2_set_features,
4711 .ndo_tx_timeout = sky2_tx_timeout,
4712 .ndo_get_stats64 = sky2_get_stats,
4713 #ifdef CONFIG_NET_POLL_CONTROLLER
4714 .ndo_poll_controller = sky2_netpoll,
4718 .ndo_open = sky2_open,
4719 .ndo_stop = sky2_close,
4720 .ndo_start_xmit = sky2_xmit_frame,
4721 .ndo_do_ioctl = sky2_ioctl,
4722 .ndo_validate_addr = eth_validate_addr,
4723 .ndo_set_mac_address = sky2_set_mac_address,
4724 .ndo_set_rx_mode = sky2_set_multicast,
4725 .ndo_change_mtu = sky2_change_mtu,
4726 .ndo_fix_features = sky2_fix_features,
4727 .ndo_set_features = sky2_set_features,
4728 .ndo_tx_timeout = sky2_tx_timeout,
4729 .ndo_get_stats64 = sky2_get_stats,
4733 /* Initialize network device */
4734 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4735 int highmem, int wol)
4737 struct sky2_port *sky2;
4738 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4744 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4745 dev->irq = hw->pdev->irq;
4746 dev->ethtool_ops = &sky2_ethtool_ops;
4747 dev->watchdog_timeo = TX_WATCHDOG;
4748 dev->netdev_ops = &sky2_netdev_ops[port];
4750 sky2 = netdev_priv(dev);
4753 sky2->msg_enable = netif_msg_init(debug, default_msg);
4755 u64_stats_init(&sky2->tx_stats.syncp);
4756 u64_stats_init(&sky2->rx_stats.syncp);
4758 /* Auto speed and flow control */
4759 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4760 if (hw->chip_id != CHIP_ID_YUKON_XL)
4761 dev->hw_features |= NETIF_F_RXCSUM;
4763 sky2->flow_mode = FC_BOTH;
4767 sky2->advertising = sky2_supported_modes(hw);
4770 spin_lock_init(&sky2->phy_lock);
4772 sky2->tx_pending = TX_DEF_PENDING;
4773 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4774 sky2->rx_pending = RX_DEF_PENDING;
4776 hw->dev[port] = dev;
4780 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4783 dev->features |= NETIF_F_HIGHDMA;
4785 /* Enable receive hashing unless hardware is known broken */
4786 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4787 dev->hw_features |= NETIF_F_RXHASH;
4789 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4790 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4791 NETIF_F_HW_VLAN_CTAG_RX;
4792 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4795 dev->features |= dev->hw_features;
4797 /* MTU range: 60 - 1500 or 9000 */
4798 dev->min_mtu = ETH_ZLEN;
4799 if (hw->chip_id == CHIP_ID_YUKON_FE ||
4800 hw->chip_id == CHIP_ID_YUKON_FE_P)
4801 dev->max_mtu = ETH_DATA_LEN;
4803 dev->max_mtu = ETH_JUMBO_MTU;
4805 /* try to get mac address in the following order:
4806 * 1) from device tree data
4807 * 2) from internal registers set by bootloader
4809 iap = of_get_mac_address(hw->pdev->dev.of_node);
4811 memcpy(dev->dev_addr, iap, ETH_ALEN);
4813 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
4816 /* if the address is invalid, use a random value */
4817 if (!is_valid_ether_addr(dev->dev_addr)) {
4818 struct sockaddr sa = { AF_UNSPEC };
4821 "Invalid MAC address, defaulting to random\n");
4822 eth_hw_addr_random(dev);
4823 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
4824 if (sky2_set_mac_address(dev, &sa))
4825 netdev_warn(dev, "Failed to set MAC address.\n");
4831 static void sky2_show_addr(struct net_device *dev)
4833 const struct sky2_port *sky2 = netdev_priv(dev);
4835 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4838 /* Handle software interrupt used during MSI test */
4839 static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4841 struct sky2_hw *hw = dev_id;
4842 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4847 if (status & Y2_IS_IRQ_SW) {
4848 hw->flags |= SKY2_HW_USE_MSI;
4849 wake_up(&hw->msi_wait);
4850 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4852 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4857 /* Test interrupt path by forcing a a software IRQ */
4858 static int sky2_test_msi(struct sky2_hw *hw)
4860 struct pci_dev *pdev = hw->pdev;
4863 init_waitqueue_head(&hw->msi_wait);
4865 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4867 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4871 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4873 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4874 sky2_read8(hw, B0_CTST);
4876 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4878 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4879 /* MSI test failed, go back to INTx mode */
4880 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4881 "switching to INTx mode.\n");
4884 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4887 sky2_write32(hw, B0_IMSK, 0);
4888 sky2_read32(hw, B0_IMSK);
4890 free_irq(pdev->irq, hw);
4895 /* This driver supports yukon2 chipset only */
4896 static const char *sky2_name(u8 chipid, char *buf, int sz)
4898 const char *name[] = {
4900 "EC Ultra", /* 0xb4 */
4901 "Extreme", /* 0xb5 */
4905 "Supreme", /* 0xb9 */
4907 "Unknown", /* 0xbb */
4908 "Optima", /* 0xbc */
4909 "OptimaEEE", /* 0xbd */
4910 "Optima 2", /* 0xbe */
4913 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4914 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4916 snprintf(buf, sz, "(chip %#x)", chipid);
4920 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4922 struct net_device *dev, *dev1;
4924 int err, using_dac = 0, wol_default;
4928 err = pci_enable_device(pdev);
4930 dev_err(&pdev->dev, "cannot enable PCI device\n");
4934 /* Get configuration information
4935 * Note: only regular PCI config access once to test for HW issues
4936 * other PCI access through shared memory for speed and to
4937 * avoid MMCONFIG problems.
4939 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4941 dev_err(&pdev->dev, "PCI read config failed\n");
4942 goto err_out_disable;
4946 dev_err(&pdev->dev, "PCI configuration read error\n");
4948 goto err_out_disable;
4951 err = pci_request_regions(pdev, DRV_NAME);
4953 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4954 goto err_out_disable;
4957 pci_set_master(pdev);
4959 if (sizeof(dma_addr_t) > sizeof(u32) &&
4960 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4962 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4964 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4965 "for consistent allocations\n");
4966 goto err_out_free_regions;
4969 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4971 dev_err(&pdev->dev, "no usable DMA configuration\n");
4972 goto err_out_free_regions;
4978 /* The sk98lin vendor driver uses hardware byte swapping but
4979 * this driver uses software swapping.
4981 reg &= ~PCI_REV_DESC;
4982 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4984 dev_err(&pdev->dev, "PCI write config failed\n");
4985 goto err_out_free_regions;
4989 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4993 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4994 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4996 goto err_out_free_regions;
4999 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
5001 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
5003 dev_err(&pdev->dev, "cannot map device registers\n");
5004 goto err_out_free_hw;
5007 err = sky2_init(hw);
5009 goto err_out_iounmap;
5011 /* ring for status responses */
5012 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
5013 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5020 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
5021 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
5025 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
5028 goto err_out_free_pci;
5031 if (!disable_msi && pci_enable_msi(pdev) == 0) {
5032 err = sky2_test_msi(hw);
5034 pci_disable_msi(pdev);
5035 if (err != -EOPNOTSUPP)
5036 goto err_out_free_netdev;
5040 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5042 err = register_netdev(dev);
5044 dev_err(&pdev->dev, "cannot register net device\n");
5045 goto err_out_free_netdev;
5048 netif_carrier_off(dev);
5050 sky2_show_addr(dev);
5052 if (hw->ports > 1) {
5053 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
5056 goto err_out_unregister;
5059 err = register_netdev(dev1);
5061 dev_err(&pdev->dev, "cannot register second net device\n");
5062 goto err_out_free_dev1;
5065 err = sky2_setup_irq(hw, hw->irq_name);
5067 goto err_out_unregister_dev1;
5069 sky2_show_addr(dev1);
5072 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0);
5073 INIT_WORK(&hw->restart_work, sky2_restart);
5075 pci_set_drvdata(pdev, hw);
5076 pdev->d3_delay = 200;
5080 err_out_unregister_dev1:
5081 unregister_netdev(dev1);
5085 unregister_netdev(dev);
5086 err_out_free_netdev:
5087 if (hw->flags & SKY2_HW_USE_MSI)
5088 pci_disable_msi(pdev);
5091 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5092 hw->st_le, hw->st_dma);
5094 sky2_write8(hw, B0_CTST, CS_RST_SET);
5099 err_out_free_regions:
5100 pci_release_regions(pdev);
5102 pci_disable_device(pdev);
5107 static void sky2_remove(struct pci_dev *pdev)
5109 struct sky2_hw *hw = pci_get_drvdata(pdev);
5115 del_timer_sync(&hw->watchdog_timer);
5116 cancel_work_sync(&hw->restart_work);
5118 for (i = hw->ports-1; i >= 0; --i)
5119 unregister_netdev(hw->dev[i]);
5121 sky2_write32(hw, B0_IMSK, 0);
5122 sky2_read32(hw, B0_IMSK);
5126 sky2_write8(hw, B0_CTST, CS_RST_SET);
5127 sky2_read8(hw, B0_CTST);
5129 if (hw->ports > 1) {
5130 napi_disable(&hw->napi);
5131 free_irq(pdev->irq, hw);
5134 if (hw->flags & SKY2_HW_USE_MSI)
5135 pci_disable_msi(pdev);
5136 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5137 hw->st_le, hw->st_dma);
5138 pci_release_regions(pdev);
5139 pci_disable_device(pdev);
5141 for (i = hw->ports-1; i >= 0; --i)
5142 free_netdev(hw->dev[i]);
5148 static int sky2_suspend(struct device *dev)
5150 struct pci_dev *pdev = to_pci_dev(dev);
5151 struct sky2_hw *hw = pci_get_drvdata(pdev);
5157 del_timer_sync(&hw->watchdog_timer);
5158 cancel_work_sync(&hw->restart_work);
5163 for (i = 0; i < hw->ports; i++) {
5164 struct net_device *dev = hw->dev[i];
5165 struct sky2_port *sky2 = netdev_priv(dev);
5168 sky2_wol_init(sky2);
5177 #ifdef CONFIG_PM_SLEEP
5178 static int sky2_resume(struct device *dev)
5180 struct pci_dev *pdev = to_pci_dev(dev);
5181 struct sky2_hw *hw = pci_get_drvdata(pdev);
5187 /* Re-enable all clocks */
5188 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5190 dev_err(&pdev->dev, "PCI write config failed\n");
5202 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5203 pci_disable_device(pdev);
5207 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5208 #define SKY2_PM_OPS (&sky2_pm_ops)
5212 #define SKY2_PM_OPS NULL
5215 static void sky2_shutdown(struct pci_dev *pdev)
5217 struct sky2_hw *hw = pci_get_drvdata(pdev);
5220 for (port = 0; port < hw->ports; port++) {
5221 struct net_device *ndev = hw->dev[port];
5224 if (netif_running(ndev)) {
5226 netif_device_detach(ndev);
5230 sky2_suspend(&pdev->dev);
5231 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5232 pci_set_power_state(pdev, PCI_D3hot);
5235 static struct pci_driver sky2_driver = {
5237 .id_table = sky2_id_table,
5238 .probe = sky2_probe,
5239 .remove = sky2_remove,
5240 .shutdown = sky2_shutdown,
5241 .driver.pm = SKY2_PM_OPS,
5244 static int __init sky2_init_module(void)
5246 pr_info("driver version " DRV_VERSION "\n");
5249 return pci_register_driver(&sky2_driver);
5252 static void __exit sky2_cleanup_module(void)
5254 pci_unregister_driver(&sky2_driver);
5255 sky2_debug_cleanup();
5258 module_init(sky2_init_module);
5259 module_exit(sky2_cleanup_module);
5261 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5262 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5263 MODULE_LICENSE("GPL");
5264 MODULE_VERSION(DRV_VERSION);