drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/device.h>
   5 #include <linux/dma-direction.h>
   6 #include <linux/dma-mapping.h>
   7 #include <linux/err.h>
   8 #include <linux/pci.h>
   9 #include <linux/slab.h>
  10 #include "hclgevf_cmd.h"
  11 #include "hclgevf_main.h"
  12 #include "hnae3.h"
  13
  14 #define hclgevf_is_csq(ring) ((ring)->flag & HCLGEVF_TYPE_CSQ)
  15 #define hclgevf_ring_to_dma_dir(ring) (hclgevf_is_csq(ring) ? \
  16                                         DMA_TO_DEVICE : DMA_FROM_DEVICE)
  17 #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
  18
  19 static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
  20 {
  21         int ntc = ring->next_to_clean;
  22         int ntu = ring->next_to_use;
  23         int used;
  24
  25         used = (ntu - ntc + ring->desc_num) % ring->desc_num;
  26
  27         return ring->desc_num - used - 1;
  28 }
  29
  30 static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
  31 {
  32         struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
  33         u16 ntc = csq->next_to_clean;
  34         struct hclgevf_desc *desc;
  35         int clean = 0;
  36         u32 head;
  37
  38         desc = &csq->desc[ntc];
  39         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  40         while (head != ntc) {
  41                 memset(desc, 0, sizeof(*desc));
  42                 ntc++;
  43                 if (ntc == csq->desc_num)
  44                         ntc = 0;
  45                 desc = &csq->desc[ntc];
  46                 clean++;
  47         }
  48         csq->next_to_clean = ntc;
  49
  50         return clean;
  51 }
  52
  53 static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
  54 {
  55         u32 head;
  56
  57         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  58
  59         return head == hw->cmq.csq.next_to_use;
  60 }
  61
  62 static bool hclgevf_is_special_opcode(u16 opcode)
  63 {
  64         u16 spec_opcode[] = {0x30, 0x31, 0x32};
  65         int i;
  66
  67         for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
  68                 if (spec_opcode[i] == opcode)
  69                         return true;
  70         }
  71
  72         return false;
  73 }
  74
  75 static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
  76 {
  77         struct hclgevf_dev *hdev = ring->dev;
  78         struct hclgevf_hw *hw = &hdev->hw;
  79         u32 reg_val;
  80
  81         if (ring->flag == HCLGEVF_TYPE_CSQ) {
  82                 reg_val = (u32)ring->desc_dma_addr;
  83                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
  84                 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
  85                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
  86
  87                 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
  88                 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
  89                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val);
  90
  91                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
  92                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
  93         } else {
  94                 reg_val = (u32)ring->desc_dma_addr;
  95                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
  96                 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
  97                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
  98
  99                 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
 100                 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
 101                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val);
 102
 103                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
 104                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
 105         }
 106 }
 107
 108 static void hclgevf_cmd_init_regs(struct hclgevf_hw *hw)
 109 {
 110         hclgevf_cmd_config_regs(&hw->cmq.csq);
 111         hclgevf_cmd_config_regs(&hw->cmq.crq);
 112 }
 113
 114 static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
 115 {
 116         int size = ring->desc_num * sizeof(struct hclgevf_desc);
 117
 118         ring->desc = dma_alloc_coherent(cmq_ring_to_dev(ring), size,
 119                                         &ring->desc_dma_addr, GFP_KERNEL);
 120         if (!ring->desc)
 121                 return -ENOMEM;
 122
 123         return 0;
 124 }
 125
 126 static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
 127 {
 128         int size  = ring->desc_num * sizeof(struct hclgevf_desc);
 129
 130         if (ring->desc) {
 131                 dma_free_coherent(cmq_ring_to_dev(ring), size,
 132                                   ring->desc, ring->desc_dma_addr);
 133                 ring->desc = NULL;
 134         }
 135 }
 136
 137 static int hclgevf_alloc_cmd_queue(struct hclgevf_dev *hdev, int ring_type)
 138 {
 139         struct hclgevf_hw *hw = &hdev->hw;
 140         struct hclgevf_cmq_ring *ring =
 141                 (ring_type == HCLGEVF_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
 142         int ret;
 143
 144         ring->dev = hdev;
 145         ring->flag = ring_type;
 146
 147         /* allocate CSQ/CRQ descriptor */
 148         ret = hclgevf_alloc_cmd_desc(ring);
 149         if (ret)
 150                 dev_err(&hdev->pdev->dev, "failed(%d) to alloc %s desc\n", ret,
 151                         (ring_type == HCLGEVF_TYPE_CSQ) ? "CSQ" : "CRQ");
 152
 153         return ret;
 154 }
 155
 156 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
 157                                   enum hclgevf_opcode_type opcode, bool is_read)
 158 {
 159         memset(desc, 0, sizeof(struct hclgevf_desc));
 160         desc->opcode = cpu_to_le16(opcode);
 161         desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
 162                                  HCLGEVF_CMD_FLAG_IN);
 163         if (is_read)
 164                 desc->flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_WR);
 165         else
 166                 desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
 167 }
 168
 169 /* hclgevf_cmd_send - send command to command queue
 170  * @hw: pointer to the hw struct
 171  * @desc: prefilled descriptor for describing the command
 172  * @num : the number of descriptors to be sent
 173  *
 174  * This is the main send command for command queue, it
 175  * sends the queue, cleans the queue, etc
 176  */
 177 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
 178 {
 179         struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
 180         struct hclgevf_desc *desc_to_use;
 181         bool complete = false;
 182         u32 timeout = 0;
 183         int handle = 0;
 184         int status = 0;
 185         u16 retval;
 186         u16 opcode;
 187         int ntc;
 188
 189         spin_lock_bh(&hw->cmq.csq.lock);
 190
 191         if (num > hclgevf_ring_space(&hw->cmq.csq) ||
 192             test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
 193                 spin_unlock_bh(&hw->cmq.csq.lock);
 194                 return -EBUSY;
 195         }
 196
 197         /* Record the location of desc in the ring for this time
 198          * which will be use for hardware to write back
 199          */
 200         ntc = hw->cmq.csq.next_to_use;
 201         opcode = le16_to_cpu(desc[0].opcode);
 202         while (handle < num) {
 203                 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
 204                 *desc_to_use = desc[handle];
 205                 (hw->cmq.csq.next_to_use)++;
 206                 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
 207                         hw->cmq.csq.next_to_use = 0;
 208                 handle++;
 209         }
 210
 211         /* Write to hardware */
 212         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
 213                           hw->cmq.csq.next_to_use);
 214
 215         /* If the command is sync, wait for the firmware to write back,
 216          * if multi descriptors to be sent, use the first one to check
 217          */
 218         if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
 219                 do {
 220                         if (hclgevf_cmd_csq_done(hw))
 221                                 break;
 222                         udelay(1);
 223                         timeout++;
 224                 } while (timeout < hw->cmq.tx_timeout);
 225         }
 226
 227         if (hclgevf_cmd_csq_done(hw)) {
 228                 complete = true;
 229                 handle = 0;
 230
 231                 while (handle < num) {
 232                         /* Get the result of hardware write back */
 233                         desc_to_use = &hw->cmq.csq.desc[ntc];
 234                         desc[handle] = *desc_to_use;
 235
 236                         if (likely(!hclgevf_is_special_opcode(opcode)))
 237                                 retval = le16_to_cpu(desc[handle].retval);
 238                         else
 239                                 retval = le16_to_cpu(desc[0].retval);
 240
 241                         if ((enum hclgevf_cmd_return_status)retval ==
 242                             HCLGEVF_CMD_EXEC_SUCCESS)
 243                                 status = 0;
 244                         else
 245                                 status = -EIO;
 246                         hw->cmq.last_status = (enum hclgevf_cmd_status)retval;
 247                         ntc++;
 248                         handle++;
 249                         if (ntc == hw->cmq.csq.desc_num)
 250                                 ntc = 0;
 251                 }
 252         }
 253
 254         if (!complete)
 255                 status = -EAGAIN;
 256
 257         /* Clean the command send queue */
 258         handle = hclgevf_cmd_csq_clean(hw);
 259         if (handle != num) {
 260                 dev_warn(&hdev->pdev->dev,
 261                          "cleaned %d, need to clean %d\n", handle, num);
 262         }
 263
 264         spin_unlock_bh(&hw->cmq.csq.lock);
 265
 266         return status;
 267 }
 268
 269 static int  hclgevf_cmd_query_firmware_version(struct hclgevf_hw *hw,
 270                                                u32 *version)
 271 {
 272         struct hclgevf_query_version_cmd *resp;
 273         struct hclgevf_desc desc;
 274         int status;
 275
 276         resp = (struct hclgevf_query_version_cmd *)desc.data;
 277
 278         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
 279         status = hclgevf_cmd_send(hw, &desc, 1);
 280         if (!status)
 281                 *version = le32_to_cpu(resp->firmware);
 282
 283         return status;
 284 }
 285
 286 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
 287 {
 288         int ret;
 289
 290         /* Setup the lock for command queue */
 291         spin_lock_init(&hdev->hw.cmq.csq.lock);
 292         spin_lock_init(&hdev->hw.cmq.crq.lock);
 293
 294         hdev->hw.cmq.tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
 295         hdev->hw.cmq.csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 296         hdev->hw.cmq.crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 297
 298         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CSQ);
 299         if (ret) {
 300                 dev_err(&hdev->pdev->dev,
 301                         "CSQ ring setup error %d\n", ret);
 302                 return ret;
 303         }
 304
 305         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CRQ);
 306         if (ret) {
 307                 dev_err(&hdev->pdev->dev,
 308                         "CRQ ring setup error %d\n", ret);
 309                 goto err_csq;
 310         }
 311
 312         return 0;
 313 err_csq:
 314         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 315         return ret;
 316 }
 317
 318 int hclgevf_cmd_init(struct hclgevf_dev *hdev)
 319 {
 320         u32 version;
 321         int ret;
 322
 323         spin_lock_bh(&hdev->hw.cmq.csq.lock);
 324         spin_lock_bh(&hdev->hw.cmq.crq.lock);
 325
 326         /* initialize the pointers of async rx queue of mailbox */
 327         hdev->arq.hdev = hdev;
 328         hdev->arq.head = 0;
 329         hdev->arq.tail = 0;
 330         hdev->arq.count = 0;
 331         hdev->hw.cmq.csq.next_to_clean = 0;
 332         hdev->hw.cmq.csq.next_to_use = 0;
 333         hdev->hw.cmq.crq.next_to_clean = 0;
 334         hdev->hw.cmq.crq.next_to_use = 0;
 335
 336         hclgevf_cmd_init_regs(&hdev->hw);
 337
 338         spin_unlock_bh(&hdev->hw.cmq.crq.lock);
 339         spin_unlock_bh(&hdev->hw.cmq.csq.lock);
 340
 341         clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 342
 343         /* Check if there is new reset pending, because the higher level
 344          * reset may happen when lower level reset is being processed.
 345          */
 346         if (hclgevf_is_reset_pending(hdev)) {
 347                 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 348                 return -EBUSY;
 349         }
 350
 351         /* get firmware version */
 352         ret = hclgevf_cmd_query_firmware_version(&hdev->hw, &version);
 353         if (ret) {
 354                 dev_err(&hdev->pdev->dev,
 355                         "failed(%d) to query firmware version\n", ret);
 356                 return ret;
 357         }
 358         hdev->fw_version = version;
 359
 360         dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
 361
 362         return 0;
 363 }
 364
 365 static void hclgevf_cmd_uninit_regs(struct hclgevf_hw *hw)
 366 {
 367         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, 0);
 368         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, 0);
 369         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 0);
 370         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
 371         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
 372         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, 0);
 373         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, 0);
 374         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, 0);
 375         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
 376         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
 377 }
 378
 379 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
 380 {
 381         spin_lock_bh(&hdev->hw.cmq.csq.lock);
 382         spin_lock(&hdev->hw.cmq.crq.lock);
 383         clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 384         hclgevf_cmd_uninit_regs(&hdev->hw);
 385         spin_unlock(&hdev->hw.cmq.crq.lock);
 386         spin_unlock_bh(&hdev->hw.cmq.csq.lock);
 387         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 388         hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
 389 }