drivers/net/ethernet/freescale/fman/fman_port.c

   1 /*
   2  * Copyright 2008 - 2015 Freescale Semiconductor Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *     * Redistributions of source code must retain the above copyright
   7  *       notice, this list of conditions and the following disclaimer.
   8  *     * Redistributions in binary form must reproduce the above copyright
   9  *       notice, this list of conditions and the following disclaimer in the
  10  *       documentation and/or other materials provided with the distribution.
  11  *     * Neither the name of Freescale Semiconductor nor the
  12  *       names of its contributors may be used to endorse or promote products
  13  *       derived from this software without specific prior written permission.
  14  *
  15  *
  16  * ALTERNATIVELY, this software may be distributed under the terms of the
  17  * GNU General Public License ("GPL") as published by the Free Software
  18  * Foundation, either version 2 of that License or (at your option) any
  19  * later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/module.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/of_address.h>
  41 #include <linux/delay.h>
  42 #include <linux/libfdt_env.h>
  43
  44 #include "fman.h"
  45 #include "fman_port.h"
  46 #include "fman_sp.h"
  47 #include "fman_keygen.h"
  48
  49 /* Queue ID */
  50 #define DFLT_FQ_ID              0x00FFFFFF
  51
  52 /* General defines */
  53 #define PORT_BMI_FIFO_UNITS             0x100
  54
  55 #define MAX_PORT_FIFO_SIZE(bmi_max_fifo_size)   \
  56         min((u32)bmi_max_fifo_size, (u32)1024 * FMAN_BMI_FIFO_UNITS)
  57
  58 #define PORT_CG_MAP_NUM                 8
  59 #define PORT_PRS_RESULT_WORDS_NUM       8
  60 #define PORT_IC_OFFSET_UNITS            0x10
  61
  62 #define MIN_EXT_BUF_SIZE                64
  63
  64 #define BMI_PORT_REGS_OFFSET                            0
  65 #define QMI_PORT_REGS_OFFSET                            0x400
  66 #define HWP_PORT_REGS_OFFSET                            0x800
  67
  68 /* Default values */
  69 #define DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN              \
  70         DFLT_FM_SP_BUFFER_PREFIX_CONTEXT_DATA_ALIGN
  71
  72 #define DFLT_PORT_CUT_BYTES_FROM_END            4
  73
  74 #define DFLT_PORT_ERRORS_TO_DISCARD             FM_PORT_FRM_ERR_CLS_DISCARD
  75 #define DFLT_PORT_MAX_FRAME_LENGTH              9600
  76
  77 #define DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(bmi_max_fifo_size)  \
  78         MAX_PORT_FIFO_SIZE(bmi_max_fifo_size)
  79
  80 #define DFLT_PORT_RX_FIFO_THRESHOLD(major, bmi_max_fifo_size)   \
  81         (major == 6 ?                                           \
  82         MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) :         \
  83         (MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) * 3 / 4))        \
  84
  85 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS                0
  86
  87 /* QMI defines */
  88 #define QMI_DEQ_CFG_SUBPORTAL_MASK              0x1f
  89
  90 #define QMI_PORT_CFG_EN                         0x80000000
  91 #define QMI_PORT_STATUS_DEQ_FD_BSY              0x20000000
  92
  93 #define QMI_DEQ_CFG_PRI                         0x80000000
  94 #define QMI_DEQ_CFG_TYPE1                       0x10000000
  95 #define QMI_DEQ_CFG_TYPE2                       0x20000000
  96 #define QMI_DEQ_CFG_TYPE3                       0x30000000
  97 #define QMI_DEQ_CFG_PREFETCH_PARTIAL            0x01000000
  98 #define QMI_DEQ_CFG_PREFETCH_FULL               0x03000000
  99 #define QMI_DEQ_CFG_SP_MASK                     0xf
 100 #define QMI_DEQ_CFG_SP_SHIFT                    20
 101
 102 #define QMI_BYTE_COUNT_LEVEL_CONTROL(_type)     \
 103         (_type == FMAN_PORT_TYPE_TX ? 0x1400 : 0x400)
 104
 105 /* BMI defins */
 106 #define BMI_EBD_EN                              0x80000000
 107
 108 #define BMI_PORT_CFG_EN                         0x80000000
 109
 110 #define BMI_PORT_STATUS_BSY                     0x80000000
 111
 112 #define BMI_DMA_ATTR_SWP_SHIFT                  FMAN_SP_DMA_ATTR_SWP_SHIFT
 113 #define BMI_DMA_ATTR_WRITE_OPTIMIZE             FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE
 114
 115 #define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16
 116 #define BMI_RX_FIFO_THRESHOLD_ETHE              0x80000000
 117
 118 #define BMI_FRAME_END_CS_IGNORE_SHIFT           24
 119 #define BMI_FRAME_END_CS_IGNORE_MASK            0x0000001f
 120
 121 #define BMI_RX_FRAME_END_CUT_SHIFT              16
 122 #define BMI_RX_FRAME_END_CUT_MASK               0x0000001f
 123
 124 #define BMI_IC_TO_EXT_SHIFT                     FMAN_SP_IC_TO_EXT_SHIFT
 125 #define BMI_IC_TO_EXT_MASK                      0x0000001f
 126 #define BMI_IC_FROM_INT_SHIFT                   FMAN_SP_IC_FROM_INT_SHIFT
 127 #define BMI_IC_FROM_INT_MASK                    0x0000000f
 128 #define BMI_IC_SIZE_MASK                        0x0000001f
 129
 130 #define BMI_INT_BUF_MARG_SHIFT                  28
 131 #define BMI_INT_BUF_MARG_MASK                   0x0000000f
 132 #define BMI_EXT_BUF_MARG_START_SHIFT            FMAN_SP_EXT_BUF_MARG_START_SHIFT
 133 #define BMI_EXT_BUF_MARG_START_MASK             0x000001ff
 134 #define BMI_EXT_BUF_MARG_END_MASK               0x000001ff
 135
 136 #define BMI_CMD_MR_LEAC                         0x00200000
 137 #define BMI_CMD_MR_SLEAC                        0x00100000
 138 #define BMI_CMD_MR_MA                           0x00080000
 139 #define BMI_CMD_MR_DEAS                         0x00040000
 140 #define BMI_CMD_RX_MR_DEF                       (BMI_CMD_MR_LEAC | \
 141                                                 BMI_CMD_MR_SLEAC | \
 142                                                 BMI_CMD_MR_MA | \
 143                                                 BMI_CMD_MR_DEAS)
 144 #define BMI_CMD_TX_MR_DEF                       0
 145
 146 #define BMI_CMD_ATTR_ORDER                      0x80000000
 147 #define BMI_CMD_ATTR_SYNC                       0x02000000
 148 #define BMI_CMD_ATTR_COLOR_SHIFT                26
 149
 150 #define BMI_FIFO_PIPELINE_DEPTH_SHIFT           12
 151 #define BMI_FIFO_PIPELINE_DEPTH_MASK            0x0000000f
 152 #define BMI_NEXT_ENG_FD_BITS_SHIFT              24
 153
 154 #define BMI_EXT_BUF_POOL_VALID                  FMAN_SP_EXT_BUF_POOL_VALID
 155 #define BMI_EXT_BUF_POOL_EN_COUNTER             FMAN_SP_EXT_BUF_POOL_EN_COUNTER
 156 #define BMI_EXT_BUF_POOL_BACKUP         FMAN_SP_EXT_BUF_POOL_BACKUP
 157 #define BMI_EXT_BUF_POOL_ID_SHIFT               16
 158 #define BMI_EXT_BUF_POOL_ID_MASK                0x003F0000
 159 #define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16
 160
 161 #define BMI_TX_FIFO_MIN_FILL_SHIFT              16
 162
 163 #define BMI_PRIORITY_ELEVATION_LEVEL ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
 164 #define BMI_FIFO_THRESHOLD            ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
 165
 166 #define BMI_DEQUEUE_PIPELINE_DEPTH(_type, _speed)               \
 167         ((_type == FMAN_PORT_TYPE_TX && _speed == 10000) ? 4 : 1)
 168
 169 #define RX_ERRS_TO_ENQ                            \
 170         (FM_PORT_FRM_ERR_DMA                    | \
 171         FM_PORT_FRM_ERR_PHYSICAL                | \
 172         FM_PORT_FRM_ERR_SIZE                    | \
 173         FM_PORT_FRM_ERR_EXTRACTION              | \
 174         FM_PORT_FRM_ERR_NO_SCHEME               | \
 175         FM_PORT_FRM_ERR_PRS_TIMEOUT             | \
 176         FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT        | \
 177         FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED    | \
 178         FM_PORT_FRM_ERR_PRS_HDR_ERR             | \
 179         FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW        | \
 180         FM_PORT_FRM_ERR_IPRE)
 181
 182 /* NIA defines */
 183 #define NIA_ORDER_RESTOR                                0x00800000
 184 #define NIA_ENG_BMI                                     0x00500000
 185 #define NIA_ENG_QMI_ENQ                                 0x00540000
 186 #define NIA_ENG_QMI_DEQ                                 0x00580000
 187 #define NIA_ENG_HWP                                     0x00440000
 188 #define NIA_ENG_HWK                                     0x00480000
 189 #define NIA_BMI_AC_ENQ_FRAME                            0x00000002
 190 #define NIA_BMI_AC_TX_RELEASE                           0x000002C0
 191 #define NIA_BMI_AC_RELEASE                              0x000000C0
 192 #define NIA_BMI_AC_TX                                   0x00000274
 193 #define NIA_BMI_AC_FETCH_ALL_FRAME                      0x0000020c
 194
 195 /* Port IDs */
 196 #define TX_10G_PORT_BASE                0x30
 197 #define RX_10G_PORT_BASE                0x10
 198
 199 /* BMI Rx port register map */
 200 struct fman_port_rx_bmi_regs {
 201         u32 fmbm_rcfg;          /* Rx Configuration */
 202         u32 fmbm_rst;           /* Rx Status */
 203         u32 fmbm_rda;           /* Rx DMA attributes */
 204         u32 fmbm_rfp;           /* Rx FIFO Parameters */
 205         u32 fmbm_rfed;          /* Rx Frame End Data */
 206         u32 fmbm_ricp;          /* Rx Internal Context Parameters */
 207         u32 fmbm_rim;           /* Rx Internal Buffer Margins */
 208         u32 fmbm_rebm;          /* Rx External Buffer Margins */
 209         u32 fmbm_rfne;          /* Rx Frame Next Engine */
 210         u32 fmbm_rfca;          /* Rx Frame Command Attributes. */
 211         u32 fmbm_rfpne;         /* Rx Frame Parser Next Engine */
 212         u32 fmbm_rpso;          /* Rx Parse Start Offset */
 213         u32 fmbm_rpp;           /* Rx Policer Profile  */
 214         u32 fmbm_rccb;          /* Rx Coarse Classification Base */
 215         u32 fmbm_reth;          /* Rx Excessive Threshold */
 216         u32 reserved003c[1];    /* (0x03C 0x03F) */
 217         u32 fmbm_rprai[PORT_PRS_RESULT_WORDS_NUM];
 218         /* Rx Parse Results Array Init */
 219         u32 fmbm_rfqid;         /* Rx Frame Queue ID */
 220         u32 fmbm_refqid;        /* Rx Error Frame Queue ID */
 221         u32 fmbm_rfsdm;         /* Rx Frame Status Discard Mask */
 222         u32 fmbm_rfsem;         /* Rx Frame Status Error Mask */
 223         u32 fmbm_rfene;         /* Rx Frame Enqueue Next Engine */
 224         u32 reserved0074[0x2];  /* (0x074-0x07C)  */
 225         u32 fmbm_rcmne;         /* Rx Frame Continuous Mode Next Engine */
 226         u32 reserved0080[0x20]; /* (0x080 0x0FF)  */
 227         u32 fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
 228         /* Buffer Manager pool Information- */
 229         u32 fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];     /* Allocate Counter- */
 230         u32 reserved0130[8];    /* 0x130/0x140 - 0x15F reserved - */
 231         u32 fmbm_rcgm[PORT_CG_MAP_NUM]; /* Congestion Group Map */
 232         u32 fmbm_mpd;           /* BM Pool Depletion  */
 233         u32 reserved0184[0x1F]; /* (0x184 0x1FF) */
 234         u32 fmbm_rstc;          /* Rx Statistics Counters */
 235         u32 fmbm_rfrc;          /* Rx Frame Counter */
 236         u32 fmbm_rfbc;          /* Rx Bad Frames Counter */
 237         u32 fmbm_rlfc;          /* Rx Large Frames Counter */
 238         u32 fmbm_rffc;          /* Rx Filter Frames Counter */
 239         u32 fmbm_rfdc;          /* Rx Frame Discard Counter */
 240         u32 fmbm_rfldec;                /* Rx Frames List DMA Error Counter */
 241         u32 fmbm_rodc;          /* Rx Out of Buffers Discard nntr */
 242         u32 fmbm_rbdc;          /* Rx Buffers Deallocate Counter */
 243         u32 fmbm_rpec;          /* RX Prepare to enqueue Counte */
 244         u32 reserved0224[0x16]; /* (0x224 0x27F) */
 245         u32 fmbm_rpc;           /* Rx Performance Counters */
 246         u32 fmbm_rpcp;          /* Rx Performance Count Parameters */
 247         u32 fmbm_rccn;          /* Rx Cycle Counter */
 248         u32 fmbm_rtuc;          /* Rx Tasks Utilization Counter */
 249         u32 fmbm_rrquc;         /* Rx Receive Queue Utilization cntr */
 250         u32 fmbm_rduc;          /* Rx DMA Utilization Counter */
 251         u32 fmbm_rfuc;          /* Rx FIFO Utilization Counter */
 252         u32 fmbm_rpac;          /* Rx Pause Activation Counter */
 253         u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */
 254         u32 fmbm_rdcfg[0x3];    /* Rx Debug Configuration */
 255         u32 fmbm_rgpr;          /* Rx General Purpose Register */
 256         u32 reserved0310[0x3a];
 257 };
 258
 259 /* BMI Tx port register map */
 260 struct fman_port_tx_bmi_regs {
 261         u32 fmbm_tcfg;          /* Tx Configuration */
 262         u32 fmbm_tst;           /* Tx Status */
 263         u32 fmbm_tda;           /* Tx DMA attributes */
 264         u32 fmbm_tfp;           /* Tx FIFO Parameters */
 265         u32 fmbm_tfed;          /* Tx Frame End Data */
 266         u32 fmbm_ticp;          /* Tx Internal Context Parameters */
 267         u32 fmbm_tfdne;         /* Tx Frame Dequeue Next Engine. */
 268         u32 fmbm_tfca;          /* Tx Frame Command attribute. */
 269         u32 fmbm_tcfqid;        /* Tx Confirmation Frame Queue ID. */
 270         u32 fmbm_tefqid;        /* Tx Frame Error Queue ID */
 271         u32 fmbm_tfene;         /* Tx Frame Enqueue Next Engine */
 272         u32 fmbm_trlmts;        /* Tx Rate Limiter Scale */
 273         u32 fmbm_trlmt;         /* Tx Rate Limiter */
 274         u32 reserved0034[0x0e]; /* (0x034-0x6c) */
 275         u32 fmbm_tccb;          /* Tx Coarse Classification base */
 276         u32 fmbm_tfne;          /* Tx Frame Next Engine */
 277         u32 fmbm_tpfcm[0x02];
 278         /* Tx Priority based Flow Control (PFC) Mapping */
 279         u32 fmbm_tcmne;         /* Tx Frame Continuous Mode Next Engine */
 280         u32 reserved0080[0x60]; /* (0x080-0x200) */
 281         u32 fmbm_tstc;          /* Tx Statistics Counters */
 282         u32 fmbm_tfrc;          /* Tx Frame Counter */
 283         u32 fmbm_tfdc;          /* Tx Frames Discard Counter */
 284         u32 fmbm_tfledc;        /* Tx Frame len error discard cntr */
 285         u32 fmbm_tfufdc;        /* Tx Frame unsprt frmt discard cntr */
 286         u32 fmbm_tbdc;          /* Tx Buffers Deallocate Counter */
 287         u32 reserved0218[0x1A]; /* (0x218-0x280) */
 288         u32 fmbm_tpc;           /* Tx Performance Counters */
 289         u32 fmbm_tpcp;          /* Tx Performance Count Parameters */
 290         u32 fmbm_tccn;          /* Tx Cycle Counter */
 291         u32 fmbm_ttuc;          /* Tx Tasks Utilization Counter */
 292         u32 fmbm_ttcquc;        /* Tx Transmit conf Q util Counter */
 293         u32 fmbm_tduc;          /* Tx DMA Utilization Counter */
 294         u32 fmbm_tfuc;          /* Tx FIFO Utilization Counter */
 295         u32 reserved029c[16];   /* (0x29C-0x2FF) */
 296         u32 fmbm_tdcfg[0x3];    /* Tx Debug Configuration */
 297         u32 fmbm_tgpr;          /* Tx General Purpose Register */
 298         u32 reserved0310[0x3a]; /* (0x310-0x3FF) */
 299 };
 300
 301 /* BMI port register map */
 302 union fman_port_bmi_regs {
 303         struct fman_port_rx_bmi_regs rx;
 304         struct fman_port_tx_bmi_regs tx;
 305 };
 306
 307 /* QMI port register map */
 308 struct fman_port_qmi_regs {
 309         u32 fmqm_pnc;           /* PortID n Configuration Register */
 310         u32 fmqm_pns;           /* PortID n Status Register */
 311         u32 fmqm_pnts;          /* PortID n Task Status Register */
 312         u32 reserved00c[4];     /* 0xn00C - 0xn01B */
 313         u32 fmqm_pnen;          /* PortID n Enqueue NIA Register */
 314         u32 fmqm_pnetfc;                /* PortID n Enq Total Frame Counter */
 315         u32 reserved024[2];     /* 0xn024 - 0x02B */
 316         u32 fmqm_pndn;          /* PortID n Dequeue NIA Register */
 317         u32 fmqm_pndc;          /* PortID n Dequeue Config Register */
 318         u32 fmqm_pndtfc;                /* PortID n Dequeue tot Frame cntr */
 319         u32 fmqm_pndfdc;                /* PortID n Dequeue FQID Dflt Cntr */
 320         u32 fmqm_pndcc;         /* PortID n Dequeue Confirm Counter */
 321 };
 322
 323 #define HWP_HXS_COUNT 16
 324 #define HWP_HXS_PHE_REPORT 0x00000800
 325 #define HWP_HXS_PCAC_PSTAT 0x00000100
 326 #define HWP_HXS_PCAC_PSTOP 0x00000001
 327 struct fman_port_hwp_regs {
 328         struct {
 329                 u32 ssa; /* Soft Sequence Attachment */
 330                 u32 lcv; /* Line-up Enable Confirmation Mask */
 331         } pmda[HWP_HXS_COUNT]; /* Parse Memory Direct Access Registers */
 332         u32 reserved080[(0x3f8 - 0x080) / 4]; /* (0x080-0x3f7) */
 333         u32 fmpr_pcac; /* Configuration Access Control */
 334 };
 335
 336 /* QMI dequeue prefetch modes */
 337 enum fman_port_deq_prefetch {
 338         FMAN_PORT_DEQ_NO_PREFETCH, /* No prefetch mode */
 339         FMAN_PORT_DEQ_PART_PREFETCH, /* Partial prefetch mode */
 340         FMAN_PORT_DEQ_FULL_PREFETCH /* Full prefetch mode */
 341 };
 342
 343 /* A structure for defining FM port resources */
 344 struct fman_port_rsrc {
 345         u32 num; /* Committed required resource */
 346         u32 extra; /* Extra (not committed) required resource */
 347 };
 348
 349 enum fman_port_dma_swap {
 350         FMAN_PORT_DMA_NO_SWAP,  /* No swap, transfer data as is */
 351         FMAN_PORT_DMA_SWAP_LE,
 352         /* The transferred data should be swapped in PPC Little Endian mode */
 353         FMAN_PORT_DMA_SWAP_BE
 354         /* The transferred data should be swapped in Big Endian mode */
 355 };
 356
 357 /* Default port color */
 358 enum fman_port_color {
 359         FMAN_PORT_COLOR_GREEN,  /* Default port color is green */
 360         FMAN_PORT_COLOR_YELLOW, /* Default port color is yellow */
 361         FMAN_PORT_COLOR_RED,            /* Default port color is red */
 362         FMAN_PORT_COLOR_OVERRIDE        /* Ignore color */
 363 };
 364
 365 /* QMI dequeue from the SP channel - types */
 366 enum fman_port_deq_type {
 367         FMAN_PORT_DEQ_BY_PRI,
 368         /* Priority precedence and Intra-Class scheduling */
 369         FMAN_PORT_DEQ_ACTIVE_FQ,
 370         /* Active FQ precedence and Intra-Class scheduling */
 371         FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS
 372         /* Active FQ precedence and override Intra-Class scheduling */
 373 };
 374
 375 /* External buffer pools configuration */
 376 struct fman_port_bpools {
 377         u8 count;                       /* Num of pools to set up */
 378         bool counters_enable;           /* Enable allocate counters */
 379         u8 grp_bp_depleted_num;
 380         /* Number of depleted pools - if reached the BMI indicates
 381          * the MAC to send a pause frame
 382          */
 383         struct {
 384                 u8 bpid;                /* BM pool ID */
 385                 u16 size;
 386                 /* Pool's size - must be in ascending order */
 387                 bool is_backup;
 388                 /* If this is a backup pool */
 389                 bool grp_bp_depleted;
 390                 /* Consider this buffer in multiple pools depletion criteria */
 391                 bool single_bp_depleted;
 392                 /* Consider this buffer in single pool depletion criteria */
 393         } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM];
 394 };
 395
 396 struct fman_port_cfg {
 397         u32 dflt_fqid;
 398         u32 err_fqid;
 399         u32 pcd_base_fqid;
 400         u32 pcd_fqs_count;
 401         u8 deq_sp;
 402         bool deq_high_priority;
 403         enum fman_port_deq_type deq_type;
 404         enum fman_port_deq_prefetch deq_prefetch_option;
 405         u16 deq_byte_cnt;
 406         u8 cheksum_last_bytes_ignore;
 407         u8 rx_cut_end_bytes;
 408         struct fman_buf_pool_depletion buf_pool_depletion;
 409         struct fman_ext_pools ext_buf_pools;
 410         u32 tx_fifo_min_level;
 411         u32 tx_fifo_low_comf_level;
 412         u32 rx_pri_elevation;
 413         u32 rx_fifo_thr;
 414         struct fman_sp_buf_margins buf_margins;
 415         u32 int_buf_start_margin;
 416         struct fman_sp_int_context_data_copy int_context;
 417         u32 discard_mask;
 418         u32 err_mask;
 419         struct fman_buffer_prefix_content buffer_prefix_content;
 420         bool dont_release_buf;
 421
 422         u8 rx_fd_bits;
 423         u32 tx_fifo_deq_pipeline_depth;
 424         bool errata_A006320;
 425         bool excessive_threshold_register;
 426         bool fmbm_tfne_has_features;
 427
 428         enum fman_port_dma_swap dma_swap_data;
 429         enum fman_port_color color;
 430 };
 431
 432 struct fman_port_rx_pools_params {
 433         u8 num_of_pools;
 434         u16 second_largest_buf_size;
 435         u16 largest_buf_size;
 436 };
 437
 438 struct fman_port_dts_params {
 439         void __iomem *base_addr;        /* FMan port virtual memory */
 440         enum fman_port_type type;       /* Port type */
 441         u16 speed;                      /* Port speed */
 442         u8 id;                          /* HW Port Id */
 443         u32 qman_channel_id;            /* QMan channel id (non RX only) */
 444         struct fman *fman;              /* FMan Handle */
 445 };
 446
 447 struct fman_port {
 448         void *fm;
 449         struct device *dev;
 450         struct fman_rev_info rev_info;
 451         u8 port_id;
 452         enum fman_port_type port_type;
 453         u16 port_speed;
 454
 455         union fman_port_bmi_regs __iomem *bmi_regs;
 456         struct fman_port_qmi_regs __iomem *qmi_regs;
 457         struct fman_port_hwp_regs __iomem *hwp_regs;
 458
 459         struct fman_sp_buffer_offsets buffer_offsets;
 460
 461         u8 internal_buf_offset;
 462         struct fman_ext_pools ext_buf_pools;
 463
 464         u16 max_frame_length;
 465         struct fman_port_rsrc open_dmas;
 466         struct fman_port_rsrc tasks;
 467         struct fman_port_rsrc fifo_bufs;
 468         struct fman_port_rx_pools_params rx_pools_params;
 469
 470         struct fman_port_cfg *cfg;
 471         struct fman_port_dts_params dts_params;
 472
 473         u8 ext_pools_num;
 474         u32 max_port_fifo_size;
 475         u32 max_num_of_ext_pools;
 476         u32 max_num_of_sub_portals;
 477         u32 bm_max_num_of_pools;
 478 };
 479
 480 static int init_bmi_rx(struct fman_port *port)
 481 {
 482         struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx;
 483         struct fman_port_cfg *cfg = port->cfg;
 484         u32 tmp;
 485
 486         /* DMA attributes */
 487         tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT;
 488         /* Enable write optimization */
 489         tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE;
 490         iowrite32be(tmp, &regs->fmbm_rda);
 491
 492         /* Rx FIFO parameters */
 493         tmp = (cfg->rx_pri_elevation / PORT_BMI_FIFO_UNITS - 1) <<
 494                 BMI_RX_FIFO_PRI_ELEVATION_SHIFT;
 495         tmp |= cfg->rx_fifo_thr / PORT_BMI_FIFO_UNITS - 1;
 496         iowrite32be(tmp, &regs->fmbm_rfp);
 497
 498         if (cfg->excessive_threshold_register)
 499                 /* always allow access to the extra resources */
 500                 iowrite32be(BMI_RX_FIFO_THRESHOLD_ETHE, &regs->fmbm_reth);
 501
 502         /* Frame end data */
 503         tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) <<
 504                 BMI_FRAME_END_CS_IGNORE_SHIFT;
 505         tmp |= (cfg->rx_cut_end_bytes & BMI_RX_FRAME_END_CUT_MASK) <<
 506                 BMI_RX_FRAME_END_CUT_SHIFT;
 507         if (cfg->errata_A006320)
 508                 tmp &= 0xffe0ffff;
 509         iowrite32be(tmp, &regs->fmbm_rfed);
 510
 511         /* Internal context parameters */
 512         tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) &
 513                 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT;
 514         tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) &
 515                 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT;
 516         tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) &
 517                 BMI_IC_SIZE_MASK;
 518         iowrite32be(tmp, &regs->fmbm_ricp);
 519
 520         /* Internal buffer offset */
 521         tmp = ((cfg->int_buf_start_margin / PORT_IC_OFFSET_UNITS) &
 522                 BMI_INT_BUF_MARG_MASK) << BMI_INT_BUF_MARG_SHIFT;
 523         iowrite32be(tmp, &regs->fmbm_rim);
 524
 525         /* External buffer margins */
 526         tmp = (cfg->buf_margins.start_margins & BMI_EXT_BUF_MARG_START_MASK) <<
 527                 BMI_EXT_BUF_MARG_START_SHIFT;
 528         tmp |= cfg->buf_margins.end_margins & BMI_EXT_BUF_MARG_END_MASK;
 529         iowrite32be(tmp, &regs->fmbm_rebm);
 530
 531         /* Frame attributes */
 532         tmp = BMI_CMD_RX_MR_DEF;
 533         tmp |= BMI_CMD_ATTR_ORDER;
 534         tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT;
 535         /* Synchronization request */
 536         tmp |= BMI_CMD_ATTR_SYNC;
 537
 538         iowrite32be(tmp, &regs->fmbm_rfca);
 539
 540         /* NIA */
 541         tmp = (u32)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT;
 542
 543         tmp |= NIA_ENG_HWP;
 544         iowrite32be(tmp, &regs->fmbm_rfne);
 545
 546         /* Parser Next Engine NIA */
 547         iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME, &regs->fmbm_rfpne);
 548
 549         /* Enqueue NIA */
 550         iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, &regs->fmbm_rfene);
 551
 552         /* Default/error queues */
 553         iowrite32be((cfg->dflt_fqid & DFLT_FQ_ID), &regs->fmbm_rfqid);
 554         iowrite32be((cfg->err_fqid & DFLT_FQ_ID), &regs->fmbm_refqid);
 555
 556         /* Discard/error masks */
 557         iowrite32be(cfg->discard_mask, &regs->fmbm_rfsdm);
 558         iowrite32be(cfg->err_mask, &regs->fmbm_rfsem);
 559
 560         return 0;
 561 }
 562
 563 static int init_bmi_tx(struct fman_port *port)
 564 {
 565         struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx;
 566         struct fman_port_cfg *cfg = port->cfg;
 567         u32 tmp;
 568
 569         /* Tx Configuration register */
 570         tmp = 0;
 571         iowrite32be(tmp, &regs->fmbm_tcfg);
 572
 573         /* DMA attributes */
 574         tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT;
 575         iowrite32be(tmp, &regs->fmbm_tda);
 576
 577         /* Tx FIFO parameters */
 578         tmp = (cfg->tx_fifo_min_level / PORT_BMI_FIFO_UNITS) <<
 579                 BMI_TX_FIFO_MIN_FILL_SHIFT;
 580         tmp |= ((cfg->tx_fifo_deq_pipeline_depth - 1) &
 581                 BMI_FIFO_PIPELINE_DEPTH_MASK) << BMI_FIFO_PIPELINE_DEPTH_SHIFT;
 582         tmp |= (cfg->tx_fifo_low_comf_level / PORT_BMI_FIFO_UNITS) - 1;
 583         iowrite32be(tmp, &regs->fmbm_tfp);
 584
 585         /* Frame end data */
 586         tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) <<
 587                 BMI_FRAME_END_CS_IGNORE_SHIFT;
 588         iowrite32be(tmp, &regs->fmbm_tfed);
 589
 590         /* Internal context parameters */
 591         tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) &
 592                 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT;
 593         tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) &
 594                 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT;
 595         tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) &
 596                 BMI_IC_SIZE_MASK;
 597         iowrite32be(tmp, &regs->fmbm_ticp);
 598
 599         /* Frame attributes */
 600         tmp = BMI_CMD_TX_MR_DEF;
 601         tmp |= BMI_CMD_ATTR_ORDER;
 602         tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT;
 603         iowrite32be(tmp, &regs->fmbm_tfca);
 604
 605         /* Dequeue NIA + enqueue NIA */
 606         iowrite32be(NIA_ENG_QMI_DEQ, &regs->fmbm_tfdne);
 607         iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, &regs->fmbm_tfene);
 608         if (cfg->fmbm_tfne_has_features)
 609                 iowrite32be(!cfg->dflt_fqid ?
 610                             BMI_EBD_EN | NIA_BMI_AC_FETCH_ALL_FRAME :
 611                             NIA_BMI_AC_FETCH_ALL_FRAME, &regs->fmbm_tfne);
 612         if (!cfg->dflt_fqid && cfg->dont_release_buf) {
 613                 iowrite32be(DFLT_FQ_ID, &regs->fmbm_tcfqid);
 614                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
 615                             &regs->fmbm_tfene);
 616                 if (cfg->fmbm_tfne_has_features)
 617                         iowrite32be(ioread32be(&regs->fmbm_tfne) & ~BMI_EBD_EN,
 618                                     &regs->fmbm_tfne);
 619         }
 620
 621         /* Confirmation/error queues */
 622         if (cfg->dflt_fqid || !cfg->dont_release_buf)
 623                 iowrite32be(cfg->dflt_fqid & DFLT_FQ_ID, &regs->fmbm_tcfqid);
 624         iowrite32be((cfg->err_fqid & DFLT_FQ_ID), &regs->fmbm_tefqid);
 625
 626         return 0;
 627 }
 628
 629 static int init_qmi(struct fman_port *port)
 630 {
 631         struct fman_port_qmi_regs __iomem *regs = port->qmi_regs;
 632         struct fman_port_cfg *cfg = port->cfg;
 633         u32 tmp;
 634
 635         /* Rx port configuration */
 636         if (port->port_type == FMAN_PORT_TYPE_RX) {
 637                 /* Enqueue NIA */
 638                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, &regs->fmqm_pnen);
 639                 return 0;
 640         }
 641
 642         /* Continue with Tx port configuration */
 643         if (port->port_type == FMAN_PORT_TYPE_TX) {
 644                 /* Enqueue NIA */
 645                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
 646                             &regs->fmqm_pnen);
 647                 /* Dequeue NIA */
 648                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX, &regs->fmqm_pndn);
 649         }
 650
 651         /* Dequeue Configuration register */
 652         tmp = 0;
 653         if (cfg->deq_high_priority)
 654                 tmp |= QMI_DEQ_CFG_PRI;
 655
 656         switch (cfg->deq_type) {
 657         case FMAN_PORT_DEQ_BY_PRI:
 658                 tmp |= QMI_DEQ_CFG_TYPE1;
 659                 break;
 660         case FMAN_PORT_DEQ_ACTIVE_FQ:
 661                 tmp |= QMI_DEQ_CFG_TYPE2;
 662                 break;
 663         case FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS:
 664                 tmp |= QMI_DEQ_CFG_TYPE3;
 665                 break;
 666         default:
 667                 return -EINVAL;
 668         }
 669
 670         switch (cfg->deq_prefetch_option) {
 671         case FMAN_PORT_DEQ_NO_PREFETCH:
 672                 break;
 673         case FMAN_PORT_DEQ_PART_PREFETCH:
 674                 tmp |= QMI_DEQ_CFG_PREFETCH_PARTIAL;
 675                 break;
 676         case FMAN_PORT_DEQ_FULL_PREFETCH:
 677                 tmp |= QMI_DEQ_CFG_PREFETCH_FULL;
 678                 break;
 679         default:
 680                 return -EINVAL;
 681         }
 682
 683         tmp |= (cfg->deq_sp & QMI_DEQ_CFG_SP_MASK) << QMI_DEQ_CFG_SP_SHIFT;
 684         tmp |= cfg->deq_byte_cnt;
 685         iowrite32be(tmp, &regs->fmqm_pndc);
 686
 687         return 0;
 688 }
 689
 690 static void stop_port_hwp(struct fman_port *port)
 691 {
 692         struct fman_port_hwp_regs __iomem *regs = port->hwp_regs;
 693         int cnt = 100;
 694
 695         iowrite32be(HWP_HXS_PCAC_PSTOP, &regs->fmpr_pcac);
 696
 697         while (cnt-- > 0 &&
 698                (ioread32be(&regs->fmpr_pcac) & HWP_HXS_PCAC_PSTAT))
 699                 udelay(10);
 700         if (!cnt)
 701                 pr_err("Timeout stopping HW Parser\n");
 702 }
 703
 704 static void start_port_hwp(struct fman_port *port)
 705 {
 706         struct fman_port_hwp_regs __iomem *regs = port->hwp_regs;
 707         int cnt = 100;
 708
 709         iowrite32be(0, &regs->fmpr_pcac);
 710
 711         while (cnt-- > 0 &&
 712                !(ioread32be(&regs->fmpr_pcac) & HWP_HXS_PCAC_PSTAT))
 713                 udelay(10);
 714         if (!cnt)
 715                 pr_err("Timeout starting HW Parser\n");
 716 }
 717
 718 static void init_hwp(struct fman_port *port)
 719 {
 720         struct fman_port_hwp_regs __iomem *regs = port->hwp_regs;
 721         int i;
 722
 723         stop_port_hwp(port);
 724
 725         for (i = 0; i < HWP_HXS_COUNT; i++) {
 726                 /* enable HXS error reporting into FD[STATUS] PHE */
 727                 iowrite32be(0x00000000, &regs->pmda[i].ssa);
 728                 iowrite32be(0xffffffff, &regs->pmda[i].lcv);
 729         }
 730
 731         start_port_hwp(port);
 732 }
 733
 734 static int init(struct fman_port *port)
 735 {
 736         int err;
 737
 738         /* Init BMI registers */
 739         switch (port->port_type) {
 740         case FMAN_PORT_TYPE_RX:
 741                 err = init_bmi_rx(port);
 742                 if (!err)
 743                         init_hwp(port);
 744                 break;
 745         case FMAN_PORT_TYPE_TX:
 746                 err = init_bmi_tx(port);
 747                 break;
 748         default:
 749                 return -EINVAL;
 750         }
 751
 752         if (err)
 753                 return err;
 754
 755         /* Init QMI registers */
 756         err = init_qmi(port);
 757         if (err)
 758                 return err;
 759
 760         return 0;
 761 }
 762
 763 static int set_bpools(const struct fman_port *port,
 764                       const struct fman_port_bpools *bp)
 765 {
 766         u32 __iomem *bp_reg, *bp_depl_reg;
 767         u32 tmp;
 768         u8 i, max_bp_num;
 769         bool grp_depl_used = false, rx_port;
 770
 771         switch (port->port_type) {
 772         case FMAN_PORT_TYPE_RX:
 773                 max_bp_num = port->ext_pools_num;
 774                 rx_port = true;
 775                 bp_reg = port->bmi_regs->rx.fmbm_ebmpi;
 776                 bp_depl_reg = &port->bmi_regs->rx.fmbm_mpd;
 777                 break;
 778         default:
 779                 return -EINVAL;
 780         }
 781
 782         if (rx_port) {
 783                 /* Check buffers are provided in ascending order */
 784                 for (i = 0; (i < (bp->count - 1) &&
 785                              (i < FMAN_PORT_MAX_EXT_POOLS_NUM - 1)); i++) {
 786                         if (bp->bpool[i].size > bp->bpool[i + 1].size)
 787                                 return -EINVAL;
 788                 }
 789         }
 790
 791         /* Set up external buffers pools */
 792         for (i = 0; i < bp->count; i++) {
 793                 tmp = BMI_EXT_BUF_POOL_VALID;
 794                 tmp |= ((u32)bp->bpool[i].bpid <<
 795                         BMI_EXT_BUF_POOL_ID_SHIFT) & BMI_EXT_BUF_POOL_ID_MASK;
 796
 797                 if (rx_port) {
 798                         if (bp->counters_enable)
 799                                 tmp |= BMI_EXT_BUF_POOL_EN_COUNTER;
 800
 801                         if (bp->bpool[i].is_backup)
 802                                 tmp |= BMI_EXT_BUF_POOL_BACKUP;
 803
 804                         tmp |= (u32)bp->bpool[i].size;
 805                 }
 806
 807                 iowrite32be(tmp, &bp_reg[i]);
 808         }
 809
 810         /* Clear unused pools */
 811         for (i = bp->count; i < max_bp_num; i++)
 812                 iowrite32be(0, &bp_reg[i]);
 813
 814         /* Pools depletion */
 815         tmp = 0;
 816         for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) {
 817                 if (bp->bpool[i].grp_bp_depleted) {
 818                         grp_depl_used = true;
 819                         tmp |= 0x80000000 >> i;
 820                 }
 821
 822                 if (bp->bpool[i].single_bp_depleted)
 823                         tmp |= 0x80 >> i;
 824         }
 825
 826         if (grp_depl_used)
 827                 tmp |= ((u32)bp->grp_bp_depleted_num - 1) <<
 828                     BMI_POOL_DEP_NUM_OF_POOLS_SHIFT;
 829
 830         iowrite32be(tmp, bp_depl_reg);
 831         return 0;
 832 }
 833
 834 static bool is_init_done(struct fman_port_cfg *cfg)
 835 {
 836         /* Checks if FMan port driver parameters were initialized */
 837         if (!cfg)
 838                 return true;
 839
 840         return false;
 841 }
 842
 843 static int verify_size_of_fifo(struct fman_port *port)
 844 {
 845         u32 min_fifo_size_required = 0, opt_fifo_size_for_b2b = 0;
 846
 847         /* TX Ports */
 848         if (port->port_type == FMAN_PORT_TYPE_TX) {
 849                 min_fifo_size_required = (u32)
 850                     (roundup(port->max_frame_length,
 851                              FMAN_BMI_FIFO_UNITS) + (3 * FMAN_BMI_FIFO_UNITS));
 852
 853                 min_fifo_size_required +=
 854                     port->cfg->tx_fifo_deq_pipeline_depth *
 855                     FMAN_BMI_FIFO_UNITS;
 856
 857                 opt_fifo_size_for_b2b = min_fifo_size_required;
 858
 859                 /* Add some margin for back-to-back capability to improve
 860                  * performance, allows the hardware to pipeline new frame dma
 861                  * while the previous frame not yet transmitted.
 862                  */
 863                 if (port->port_speed == 10000)
 864                         opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS;
 865                 else
 866                         opt_fifo_size_for_b2b += 2 * FMAN_BMI_FIFO_UNITS;
 867         }
 868
 869         /* RX Ports */
 870         else if (port->port_type == FMAN_PORT_TYPE_RX) {
 871                 if (port->rev_info.major >= 6)
 872                         min_fifo_size_required = (u32)
 873                         (roundup(port->max_frame_length,
 874                                  FMAN_BMI_FIFO_UNITS) +
 875                                  (5 * FMAN_BMI_FIFO_UNITS));
 876                         /* 4 according to spec + 1 for FOF>0 */
 877                 else
 878                         min_fifo_size_required = (u32)
 879                         (roundup(min(port->max_frame_length,
 880                                      port->rx_pools_params.largest_buf_size),
 881                                      FMAN_BMI_FIFO_UNITS) +
 882                                      (7 * FMAN_BMI_FIFO_UNITS));
 883
 884                 opt_fifo_size_for_b2b = min_fifo_size_required;
 885
 886                 /* Add some margin for back-to-back capability to improve
 887                  * performance,allows the hardware to pipeline new frame dma
 888                  * while the previous frame not yet transmitted.
 889                  */
 890                 if (port->port_speed == 10000)
 891                         opt_fifo_size_for_b2b += 8 * FMAN_BMI_FIFO_UNITS;
 892                 else
 893                         opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS;
 894         }
 895
 896         WARN_ON(min_fifo_size_required <= 0);
 897         WARN_ON(opt_fifo_size_for_b2b < min_fifo_size_required);
 898
 899         /* Verify the size  */
 900         if (port->fifo_bufs.num < min_fifo_size_required)
 901                 dev_dbg(port->dev, "%s: FIFO size should be enlarged to %d bytes\n",
 902                         __func__, min_fifo_size_required);
 903         else if (port->fifo_bufs.num < opt_fifo_size_for_b2b)
 904                 dev_dbg(port->dev, "%s: For b2b processing,FIFO may be enlarged to %d bytes\n",
 905                         __func__, opt_fifo_size_for_b2b);
 906
 907         return 0;
 908 }
 909
 910 static int set_ext_buffer_pools(struct fman_port *port)
 911 {
 912         struct fman_ext_pools *ext_buf_pools = &port->cfg->ext_buf_pools;
 913         struct fman_buf_pool_depletion *buf_pool_depletion =
 914         &port->cfg->buf_pool_depletion;
 915         u8 ordered_array[FMAN_PORT_MAX_EXT_POOLS_NUM];
 916         u16 sizes_array[BM_MAX_NUM_OF_POOLS];
 917         int i = 0, j = 0, err;
 918         struct fman_port_bpools bpools;
 919
 920         memset(&ordered_array, 0, sizeof(u8) * FMAN_PORT_MAX_EXT_POOLS_NUM);
 921         memset(&sizes_array, 0, sizeof(u16) * BM_MAX_NUM_OF_POOLS);
 922         memcpy(&port->ext_buf_pools, ext_buf_pools,
 923                sizeof(struct fman_ext_pools));
 924
 925         fman_sp_set_buf_pools_in_asc_order_of_buf_sizes(ext_buf_pools,
 926                                                         ordered_array,
 927                                                         sizes_array);
 928
 929         memset(&bpools, 0, sizeof(struct fman_port_bpools));
 930         bpools.count = ext_buf_pools->num_of_pools_used;
 931         bpools.counters_enable = true;
 932         for (i = 0; i < ext_buf_pools->num_of_pools_used; i++) {
 933                 bpools.bpool[i].bpid = ordered_array[i];
 934                 bpools.bpool[i].size = sizes_array[ordered_array[i]];
 935         }
 936
 937         /* save pools parameters for later use */
 938         port->rx_pools_params.num_of_pools = ext_buf_pools->num_of_pools_used;
 939         port->rx_pools_params.largest_buf_size =
 940             sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 1]];
 941         port->rx_pools_params.second_largest_buf_size =
 942             sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 2]];
 943
 944         /* FMBM_RMPD reg. - pool depletion */
 945         if (buf_pool_depletion->pools_grp_mode_enable) {
 946                 bpools.grp_bp_depleted_num = buf_pool_depletion->num_of_pools;
 947                 for (i = 0; i < port->bm_max_num_of_pools; i++) {
 948                         if (buf_pool_depletion->pools_to_consider[i]) {
 949                                 for (j = 0; j < ext_buf_pools->
 950                                      num_of_pools_used; j++) {
 951                                         if (i == ordered_array[j]) {
 952                                                 bpools.bpool[j].
 953                                                     grp_bp_depleted = true;
 954                                                 break;
 955                                         }
 956                                 }
 957                         }
 958                 }
 959         }
 960
 961         if (buf_pool_depletion->single_pool_mode_enable) {
 962                 for (i = 0; i < port->bm_max_num_of_pools; i++) {
 963                         if (buf_pool_depletion->
 964                             pools_to_consider_for_single_mode[i]) {
 965                                 for (j = 0; j < ext_buf_pools->
 966                                      num_of_pools_used; j++) {
 967                                         if (i == ordered_array[j]) {
 968                                                 bpools.bpool[j].
 969                                                     single_bp_depleted = true;
 970                                                 break;
 971                                         }
 972                                 }
 973                         }
 974                 }
 975         }
 976
 977         err = set_bpools(port, &bpools);
 978         if (err != 0) {
 979                 dev_err(port->dev, "%s: set_bpools() failed\n", __func__);
 980                 return -EINVAL;
 981         }
 982
 983         return 0;
 984 }
 985
 986 static int init_low_level_driver(struct fman_port *port)
 987 {
 988         struct fman_port_cfg *cfg = port->cfg;
 989         u32 tmp_val;
 990
 991         switch (port->port_type) {
 992         case FMAN_PORT_TYPE_RX:
 993                 cfg->err_mask = (RX_ERRS_TO_ENQ & ~cfg->discard_mask);
 994                 break;
 995         default:
 996                 break;
 997         }
 998
 999         tmp_val = (u32)((port->internal_buf_offset % OFFSET_UNITS) ?
1000                 (port->internal_buf_offset / OFFSET_UNITS + 1) :
1001                 (port->internal_buf_offset / OFFSET_UNITS));
1002         port->internal_buf_offset = (u8)(tmp_val * OFFSET_UNITS);
1003         port->cfg->int_buf_start_margin = port->internal_buf_offset;
1004
1005         if (init(port) != 0) {
1006                 dev_err(port->dev, "%s: fman port initialization failed\n",
1007                         __func__);
1008                 return -ENODEV;
1009         }
1010
1011         /* The code bellow is a trick so the FM will not release the buffer
1012          * to BM nor will try to enqueue the frame to QM
1013          */
1014         if (port->port_type == FMAN_PORT_TYPE_TX) {
1015                 if (!cfg->dflt_fqid && cfg->dont_release_buf) {
1016                         /* override fmbm_tcfqid 0 with a false non-0 value.
1017                          * This will force FM to act according to tfene.
1018                          * Otherwise, if fmbm_tcfqid is 0 the FM will release
1019                          * buffers to BM regardless of fmbm_tfene
1020                          */
1021                         iowrite32be(0xFFFFFF, &port->bmi_regs->tx.fmbm_tcfqid);
1022                         iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
1023                                     &port->bmi_regs->tx.fmbm_tfene);
1024                 }
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int fill_soc_specific_params(struct fman_port *port)
1031 {
1032         u32 bmi_max_fifo_size;
1033
1034         bmi_max_fifo_size = fman_get_bmi_max_fifo_size(port->fm);
1035         port->max_port_fifo_size = MAX_PORT_FIFO_SIZE(bmi_max_fifo_size);
1036         port->bm_max_num_of_pools = 64;
1037
1038         /* P4080 - Major 2
1039          * P2041/P3041/P5020/P5040 - Major 3
1040          * Tx/Bx - Major 6
1041          */
1042         switch (port->rev_info.major) {
1043         case 2:
1044         case 3:
1045                 port->max_num_of_ext_pools              = 4;
1046                 port->max_num_of_sub_portals            = 12;
1047                 break;
1048
1049         case 6:
1050                 port->max_num_of_ext_pools              = 8;
1051                 port->max_num_of_sub_portals            = 16;
1052                 break;
1053
1054         default:
1055                 dev_err(port->dev, "%s: Unsupported FMan version\n", __func__);
1056                 return -EINVAL;
1057         }
1058
1059         return 0;
1060 }
1061
1062 static int get_dflt_fifo_deq_pipeline_depth(u8 major, enum fman_port_type type,
1063                                             u16 speed)
1064 {
1065         switch (type) {
1066         case FMAN_PORT_TYPE_RX:
1067         case FMAN_PORT_TYPE_TX:
1068                 switch (speed) {
1069                 case 10000:
1070                         return 4;
1071                 case 1000:
1072                         if (major >= 6)
1073                                 return 2;
1074                         else
1075                                 return 1;
1076                 default:
1077                         return 0;
1078                 }
1079         default:
1080                 return 0;
1081         }
1082 }
1083
1084 static int get_dflt_num_of_tasks(u8 major, enum fman_port_type type,
1085                                  u16 speed)
1086 {
1087         switch (type) {
1088         case FMAN_PORT_TYPE_RX:
1089         case FMAN_PORT_TYPE_TX:
1090                 switch (speed) {
1091                 case 10000:
1092                         return 16;
1093                 case 1000:
1094                         if (major >= 6)
1095                                 return 4;
1096                         else
1097                                 return 3;
1098                 default:
1099                         return 0;
1100                 }
1101         default:
1102                 return 0;
1103         }
1104 }
1105
1106 static int get_dflt_extra_num_of_tasks(u8 major, enum fman_port_type type,
1107                                        u16 speed)
1108 {
1109         switch (type) {
1110         case FMAN_PORT_TYPE_RX:
1111                 /* FMan V3 */
1112                 if (major >= 6)
1113                         return 0;
1114
1115                 /* FMan V2 */
1116                 if (speed == 10000)
1117                         return 8;
1118                 else
1119                         return 2;
1120         case FMAN_PORT_TYPE_TX:
1121         default:
1122                 return 0;
1123         }
1124 }
1125
1126 static int get_dflt_num_of_open_dmas(u8 major, enum fman_port_type type,
1127                                      u16 speed)
1128 {
1129         int val;
1130
1131         if (major >= 6) {
1132                 switch (type) {
1133                 case FMAN_PORT_TYPE_TX:
1134                         if (speed == 10000)
1135                                 val = 12;
1136                         else
1137                                 val = 3;
1138                         break;
1139                 case FMAN_PORT_TYPE_RX:
1140                         if (speed == 10000)
1141                                 val = 8;
1142                         else
1143                                 val = 2;
1144                         break;
1145                 default:
1146                         return 0;
1147                 }
1148         } else {
1149                 switch (type) {
1150                 case FMAN_PORT_TYPE_TX:
1151                 case FMAN_PORT_TYPE_RX:
1152                         if (speed == 10000)
1153                                 val = 8;
1154                         else
1155                                 val = 1;
1156                         break;
1157                 default:
1158                         val = 0;
1159                 }
1160         }
1161
1162         return val;
1163 }
1164
1165 static int get_dflt_extra_num_of_open_dmas(u8 major, enum fman_port_type type,
1166                                            u16 speed)
1167 {
1168         /* FMan V3 */
1169         if (major >= 6)
1170                 return 0;
1171
1172         /* FMan V2 */
1173         switch (type) {
1174         case FMAN_PORT_TYPE_RX:
1175         case FMAN_PORT_TYPE_TX:
1176                 if (speed == 10000)
1177                         return 8;
1178                 else
1179                         return 1;
1180         default:
1181                 return 0;
1182         }
1183 }
1184
1185 static int get_dflt_num_of_fifo_bufs(u8 major, enum fman_port_type type,
1186                                      u16 speed)
1187 {
1188         int val;
1189
1190         if (major >= 6) {
1191                 switch (type) {
1192                 case FMAN_PORT_TYPE_TX:
1193                         if (speed == 10000)
1194                                 val = 64;
1195                         else
1196                                 val = 50;
1197                         break;
1198                 case FMAN_PORT_TYPE_RX:
1199                         if (speed == 10000)
1200                                 val = 96;
1201                         else
1202                                 val = 50;
1203                         break;
1204                 default:
1205                         val = 0;
1206                 }
1207         } else {
1208                 switch (type) {
1209                 case FMAN_PORT_TYPE_TX:
1210                         if (speed == 10000)
1211                                 val = 48;
1212                         else
1213                                 val = 44;
1214                         break;
1215                 case FMAN_PORT_TYPE_RX:
1216                         if (speed == 10000)
1217                                 val = 48;
1218                         else
1219                                 val = 45;
1220                         break;
1221                 default:
1222                         val = 0;
1223                 }
1224         }
1225
1226         return val;
1227 }
1228
1229 static void set_dflt_cfg(struct fman_port *port,
1230                          struct fman_port_params *port_params)
1231 {
1232         struct fman_port_cfg *cfg = port->cfg;
1233
1234         cfg->dma_swap_data = FMAN_PORT_DMA_NO_SWAP;
1235         cfg->color = FMAN_PORT_COLOR_GREEN;
1236         cfg->rx_cut_end_bytes = DFLT_PORT_CUT_BYTES_FROM_END;
1237         cfg->rx_pri_elevation = BMI_PRIORITY_ELEVATION_LEVEL;
1238         cfg->rx_fifo_thr = BMI_FIFO_THRESHOLD;
1239         cfg->tx_fifo_low_comf_level = (5 * 1024);
1240         cfg->deq_type = FMAN_PORT_DEQ_BY_PRI;
1241         cfg->deq_prefetch_option = FMAN_PORT_DEQ_FULL_PREFETCH;
1242         cfg->tx_fifo_deq_pipeline_depth =
1243                 BMI_DEQUEUE_PIPELINE_DEPTH(port->port_type, port->port_speed);
1244         cfg->deq_byte_cnt = QMI_BYTE_COUNT_LEVEL_CONTROL(port->port_type);
1245
1246         cfg->rx_pri_elevation =
1247                 DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(port->max_port_fifo_size);
1248         port->cfg->rx_fifo_thr =
1249                 DFLT_PORT_RX_FIFO_THRESHOLD(port->rev_info.major,
1250                                             port->max_port_fifo_size);
1251
1252         if ((port->rev_info.major == 6) &&
1253             ((port->rev_info.minor == 0) || (port->rev_info.minor == 3)))
1254                 cfg->errata_A006320 = true;
1255
1256         /* Excessive Threshold register - exists for pre-FMv3 chips only */
1257         if (port->rev_info.major < 6)
1258                 cfg->excessive_threshold_register = true;
1259         else
1260                 cfg->fmbm_tfne_has_features = true;
1261
1262         cfg->buffer_prefix_content.data_align =
1263                 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN;
1264 }
1265
1266 static void set_rx_dflt_cfg(struct fman_port *port,
1267                             struct fman_port_params *port_params)
1268 {
1269         port->cfg->discard_mask = DFLT_PORT_ERRORS_TO_DISCARD;
1270
1271         memcpy(&port->cfg->ext_buf_pools,
1272                &port_params->specific_params.rx_params.ext_buf_pools,
1273                sizeof(struct fman_ext_pools));
1274         port->cfg->err_fqid =
1275                 port_params->specific_params.rx_params.err_fqid;
1276         port->cfg->dflt_fqid =
1277                 port_params->specific_params.rx_params.dflt_fqid;
1278         port->cfg->pcd_base_fqid =
1279                 port_params->specific_params.rx_params.pcd_base_fqid;
1280         port->cfg->pcd_fqs_count =
1281                 port_params->specific_params.rx_params.pcd_fqs_count;
1282 }
1283
1284 static void set_tx_dflt_cfg(struct fman_port *port,
1285                             struct fman_port_params *port_params,
1286                             struct fman_port_dts_params *dts_params)
1287 {
1288         port->cfg->tx_fifo_deq_pipeline_depth =
1289                 get_dflt_fifo_deq_pipeline_depth(port->rev_info.major,
1290                                                  port->port_type,
1291                                                  port->port_speed);
1292         port->cfg->err_fqid =
1293                 port_params->specific_params.non_rx_params.err_fqid;
1294         port->cfg->deq_sp =
1295                 (u8)(dts_params->qman_channel_id & QMI_DEQ_CFG_SUBPORTAL_MASK);
1296         port->cfg->dflt_fqid =
1297                 port_params->specific_params.non_rx_params.dflt_fqid;
1298         port->cfg->deq_high_priority = true;
1299 }
1300
1301 /**
1302  * fman_port_config
1303  * @port:       Pointer to the port structure
1304  * @params:     Pointer to data structure of parameters
1305  *
1306  * Creates a descriptor for the FM PORT module.
1307  * The routine returns a pointer to the FM PORT object.
1308  * This descriptor must be passed as first parameter to all other FM PORT
1309  * function calls.
1310  * No actual initialization or configuration of FM hardware is done by this
1311  * routine.
1312  *
1313  * Return: 0 on success; Error code otherwise.
1314  */
1315 int fman_port_config(struct fman_port *port, struct fman_port_params *params)
1316 {
1317         void __iomem *base_addr = port->dts_params.base_addr;
1318         int err;
1319
1320         /* Allocate the FM driver's parameters structure */
1321         port->cfg = kzalloc(sizeof(*port->cfg), GFP_KERNEL);
1322         if (!port->cfg)
1323                 return -EINVAL;
1324
1325         /* Initialize FM port parameters which will be kept by the driver */
1326         port->port_type = port->dts_params.type;
1327         port->port_speed = port->dts_params.speed;
1328         port->port_id = port->dts_params.id;
1329         port->fm = port->dts_params.fman;
1330         port->ext_pools_num = (u8)8;
1331
1332         /* get FM revision */
1333         fman_get_revision(port->fm, &port->rev_info);
1334
1335         err = fill_soc_specific_params(port);
1336         if (err)
1337                 goto err_port_cfg;
1338
1339         switch (port->port_type) {
1340         case FMAN_PORT_TYPE_RX:
1341                 set_rx_dflt_cfg(port, params);
1342                 /* fall through */
1343         case FMAN_PORT_TYPE_TX:
1344                 set_tx_dflt_cfg(port, params, &port->dts_params);
1345                 /* fall through */
1346         default:
1347                 set_dflt_cfg(port, params);
1348         }
1349
1350         /* Continue with other parameters */
1351         /* set memory map pointers */
1352         port->bmi_regs = base_addr + BMI_PORT_REGS_OFFSET;
1353         port->qmi_regs = base_addr + QMI_PORT_REGS_OFFSET;
1354         port->hwp_regs = base_addr + HWP_PORT_REGS_OFFSET;
1355
1356         port->max_frame_length = DFLT_PORT_MAX_FRAME_LENGTH;
1357         /* resource distribution. */
1358
1359         port->fifo_bufs.num =
1360         get_dflt_num_of_fifo_bufs(port->rev_info.major, port->port_type,
1361                                   port->port_speed) * FMAN_BMI_FIFO_UNITS;
1362         port->fifo_bufs.extra =
1363         DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS * FMAN_BMI_FIFO_UNITS;
1364
1365         port->open_dmas.num =
1366         get_dflt_num_of_open_dmas(port->rev_info.major,
1367                                   port->port_type, port->port_speed);
1368         port->open_dmas.extra =
1369         get_dflt_extra_num_of_open_dmas(port->rev_info.major,
1370                                         port->port_type, port->port_speed);
1371         port->tasks.num =
1372         get_dflt_num_of_tasks(port->rev_info.major,
1373                               port->port_type, port->port_speed);
1374         port->tasks.extra =
1375         get_dflt_extra_num_of_tasks(port->rev_info.major,
1376                                     port->port_type, port->port_speed);
1377
1378         /* FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 errata
1379          * workaround
1380          */
1381         if ((port->rev_info.major == 6) && (port->rev_info.minor == 0) &&
1382             (((port->port_type == FMAN_PORT_TYPE_TX) &&
1383             (port->port_speed == 1000)))) {
1384                 port->open_dmas.num = 16;
1385                 port->open_dmas.extra = 0;
1386         }
1387
1388         if (port->rev_info.major >= 6 &&
1389             port->port_type == FMAN_PORT_TYPE_TX &&
1390             port->port_speed == 1000) {
1391                 /* FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 Errata
1392                  * workaround
1393                  */
1394                 if (port->rev_info.major >= 6) {
1395                         u32 reg;
1396
1397                         reg = 0x00001013;
1398                         iowrite32be(reg, &port->bmi_regs->tx.fmbm_tfp);
1399                 }
1400         }
1401
1402         return 0;
1403
1404 err_port_cfg:
1405         kfree(port->cfg);
1406         return -EINVAL;
1407 }
1408 EXPORT_SYMBOL(fman_port_config);
1409
1410 /**
1411  * fman_port_use_kg_hash
1412  * port:        A pointer to a FM Port module.
1413  * Sets the HW KeyGen or the BMI as HW Parser next engine, enabling
1414  * or bypassing the KeyGen hashing of Rx traffic
1415  */
1416 void fman_port_use_kg_hash(struct fman_port *port, bool enable)
1417 {
1418         if (enable)
1419                 /* After the Parser frames go to KeyGen */
1420                 iowrite32be(NIA_ENG_HWK, &port->bmi_regs->rx.fmbm_rfpne);
1421         else
1422                 /* After the Parser frames go to BMI */
1423                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME,
1424                             &port->bmi_regs->rx.fmbm_rfpne);
1425 }
1426 EXPORT_SYMBOL(fman_port_use_kg_hash);
1427
1428 /**
1429  * fman_port_init
1430  * port:        A pointer to a FM Port module.
1431  * Initializes the FM PORT module by defining the software structure and
1432  * configuring the hardware registers.
1433  *
1434  * Return: 0 on success; Error code otherwise.
1435  */
1436 int fman_port_init(struct fman_port *port)
1437 {
1438         struct fman_port_init_params params;
1439         struct fman_keygen *keygen;
1440         struct fman_port_cfg *cfg;
1441         int err;
1442
1443         if (is_init_done(port->cfg))
1444                 return -EINVAL;
1445
1446         err = fman_sp_build_buffer_struct(&port->cfg->int_context,
1447                                           &port->cfg->buffer_prefix_content,
1448                                           &port->cfg->buf_margins,
1449                                           &port->buffer_offsets,
1450                                           &port->internal_buf_offset);
1451         if (err)
1452                 return err;
1453
1454         cfg = port->cfg;
1455
1456         if (port->port_type == FMAN_PORT_TYPE_RX) {
1457                 /* Call the external Buffer routine which also checks fifo
1458                  * size and updates it if necessary
1459                  */
1460                 /* define external buffer pools and pool depletion */
1461                 err = set_ext_buffer_pools(port);
1462                 if (err)
1463                         return err;
1464                 /* check if the largest external buffer pool is large enough */
1465                 if (cfg->buf_margins.start_margins + MIN_EXT_BUF_SIZE +
1466                     cfg->buf_margins.end_margins >
1467                     port->rx_pools_params.largest_buf_size) {
1468                         dev_err(port->dev, "%s: buf_margins.start_margins (%d) + minimum buf size (64) + buf_margins.end_margins (%d) is larger than maximum external buffer size (%d)\n",
1469                                 __func__, cfg->buf_margins.start_margins,
1470                                 cfg->buf_margins.end_margins,
1471                                 port->rx_pools_params.largest_buf_size);
1472                         return -EINVAL;
1473                 }
1474         }
1475
1476         /* Call FM module routine for communicating parameters */
1477         memset(&params, 0, sizeof(params));
1478         params.port_id = port->port_id;
1479         params.port_type = port->port_type;
1480         params.port_speed = port->port_speed;
1481         params.num_of_tasks = (u8)port->tasks.num;
1482         params.num_of_extra_tasks = (u8)port->tasks.extra;
1483         params.num_of_open_dmas = (u8)port->open_dmas.num;
1484         params.num_of_extra_open_dmas = (u8)port->open_dmas.extra;
1485
1486         if (port->fifo_bufs.num) {
1487                 err = verify_size_of_fifo(port);
1488                 if (err)
1489                         return err;
1490         }
1491         params.size_of_fifo = port->fifo_bufs.num;
1492         params.extra_size_of_fifo = port->fifo_bufs.extra;
1493         params.deq_pipeline_depth = port->cfg->tx_fifo_deq_pipeline_depth;
1494         params.max_frame_length = port->max_frame_length;
1495
1496         err = fman_set_port_params(port->fm, &params);
1497         if (err)
1498                 return err;
1499
1500         err = init_low_level_driver(port);
1501         if (err)
1502                 return err;
1503
1504         if (port->cfg->pcd_fqs_count) {
1505                 keygen = port->dts_params.fman->keygen;
1506                 err = keygen_port_hashing_init(keygen, port->port_id,
1507                                                port->cfg->pcd_base_fqid,
1508                                                port->cfg->pcd_fqs_count);
1509                 if (err)
1510                         return err;
1511
1512                 fman_port_use_kg_hash(port, true);
1513         }
1514
1515         kfree(port->cfg);
1516         port->cfg = NULL;
1517
1518         return 0;
1519 }
1520 EXPORT_SYMBOL(fman_port_init);
1521
1522 /**
1523  * fman_port_cfg_buf_prefix_content
1524  * @port                        A pointer to a FM Port module.
1525  * @buffer_prefix_content       A structure of parameters describing
1526  *                              the structure of the buffer.
1527  *                              Out parameter:
1528  *                              Start margin - offset of data from
1529  *                              start of external buffer.
1530  * Defines the structure, size and content of the application buffer.
1531  * The prefix, in Tx ports, if 'pass_prs_result', the application should set
1532  * a value to their offsets in the prefix of the FM will save the first
1533  * 'priv_data_size', than, depending on 'pass_prs_result' and
1534  * 'pass_time_stamp', copy parse result and timeStamp, and the packet itself
1535  * (in this order), to the application buffer, and to offset.
1536  * Calling this routine changes the buffer margins definitions in the internal
1537  * driver data base from its default configuration:
1538  * Data size:  [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PRIV_DATA_SIZE]
1539  * Pass Parser result: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_PRS_RESULT].
1540  * Pass timestamp: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_TIME_STAMP].
1541  * May be used for all ports
1542  *
1543  * Allowed only following fman_port_config() and before fman_port_init().
1544  *
1545  * Return: 0 on success; Error code otherwise.
1546  */
1547 int fman_port_cfg_buf_prefix_content(struct fman_port *port,
1548                                      struct fman_buffer_prefix_content *
1549                                      buffer_prefix_content)
1550 {
1551         if (is_init_done(port->cfg))
1552                 return -EINVAL;
1553
1554         memcpy(&port->cfg->buffer_prefix_content,
1555                buffer_prefix_content,
1556                sizeof(struct fman_buffer_prefix_content));
1557         /* if data_align was not initialized by user,
1558          * we return to driver's default
1559          */
1560         if (!port->cfg->buffer_prefix_content.data_align)
1561                 port->cfg->buffer_prefix_content.data_align =
1562                 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN;
1563
1564         return 0;
1565 }
1566 EXPORT_SYMBOL(fman_port_cfg_buf_prefix_content);
1567
1568 /**
1569  * fman_port_disable
1570  * port:        A pointer to a FM Port module.
1571  *
1572  * Gracefully disable an FM port. The port will not start new   tasks after all
1573  * tasks associated with the port are terminated.
1574  *
1575  * This is a blocking routine, it returns after port is gracefully stopped,
1576  * i.e. the port will not except new frames, but it will finish all frames
1577  * or tasks which were already began.
1578  * Allowed only following fman_port_init().
1579  *
1580  * Return: 0 on success; Error code otherwise.
1581  */
1582 int fman_port_disable(struct fman_port *port)
1583 {
1584         u32 __iomem *bmi_cfg_reg, *bmi_status_reg;
1585         u32 tmp;
1586         bool rx_port, failure = false;
1587         int count;
1588
1589         if (!is_init_done(port->cfg))
1590                 return -EINVAL;
1591
1592         switch (port->port_type) {
1593         case FMAN_PORT_TYPE_RX:
1594                 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg;
1595                 bmi_status_reg = &port->bmi_regs->rx.fmbm_rst;
1596                 rx_port = true;
1597                 break;
1598         case FMAN_PORT_TYPE_TX:
1599                 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg;
1600                 bmi_status_reg = &port->bmi_regs->tx.fmbm_tst;
1601                 rx_port = false;
1602                 break;
1603         default:
1604                 return -EINVAL;
1605         }
1606
1607         /* Disable QMI */
1608         if (!rx_port) {
1609                 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) & ~QMI_PORT_CFG_EN;
1610                 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc);
1611
1612                 /* Wait for QMI to finish FD handling */
1613                 count = 100;
1614                 do {
1615                         udelay(10);
1616                         tmp = ioread32be(&port->qmi_regs->fmqm_pns);
1617                 } while ((tmp & QMI_PORT_STATUS_DEQ_FD_BSY) && --count);
1618
1619                 if (count == 0) {
1620                         /* Timeout */
1621                         failure = true;
1622                 }
1623         }
1624
1625         /* Disable BMI */
1626         tmp = ioread32be(bmi_cfg_reg) & ~BMI_PORT_CFG_EN;
1627         iowrite32be(tmp, bmi_cfg_reg);
1628
1629         /* Wait for graceful stop end */
1630         count = 500;
1631         do {
1632                 udelay(10);
1633                 tmp = ioread32be(bmi_status_reg);
1634         } while ((tmp & BMI_PORT_STATUS_BSY) && --count);
1635
1636         if (count == 0) {
1637                 /* Timeout */
1638                 failure = true;
1639         }
1640
1641         if (failure)
1642                 dev_dbg(port->dev, "%s: FMan Port[%d]: BMI or QMI is Busy. Port forced down\n",
1643                         __func__,  port->port_id);
1644
1645         return 0;
1646 }
1647 EXPORT_SYMBOL(fman_port_disable);
1648
1649 /**
1650  * fman_port_enable
1651  * port:        A pointer to a FM Port module.
1652  *
1653  * A runtime routine provided to allow disable/enable of port.
1654  *
1655  * Allowed only following fman_port_init().
1656  *
1657  * Return: 0 on success; Error code otherwise.
1658  */
1659 int fman_port_enable(struct fman_port *port)
1660 {
1661         u32 __iomem *bmi_cfg_reg;
1662         u32 tmp;
1663         bool rx_port;
1664
1665         if (!is_init_done(port->cfg))
1666                 return -EINVAL;
1667
1668         switch (port->port_type) {
1669         case FMAN_PORT_TYPE_RX:
1670                 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg;
1671                 rx_port = true;
1672                 break;
1673         case FMAN_PORT_TYPE_TX:
1674                 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg;
1675                 rx_port = false;
1676                 break;
1677         default:
1678                 return -EINVAL;
1679         }
1680
1681         /* Enable QMI */
1682         if (!rx_port) {
1683                 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) | QMI_PORT_CFG_EN;
1684                 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc);
1685         }
1686
1687         /* Enable BMI */
1688         tmp = ioread32be(bmi_cfg_reg) | BMI_PORT_CFG_EN;
1689         iowrite32be(tmp, bmi_cfg_reg);
1690
1691         return 0;
1692 }
1693 EXPORT_SYMBOL(fman_port_enable);
1694
1695 /**
1696  * fman_port_bind
1697  * dev:         FMan Port OF device pointer
1698  *
1699  * Bind to a specific FMan Port.
1700  *
1701  * Allowed only after the port was created.
1702  *
1703  * Return: A pointer to the FMan port device.
1704  */
1705 struct fman_port *fman_port_bind(struct device *dev)
1706 {
1707         return (struct fman_port *)(dev_get_drvdata(get_device(dev)));
1708 }
1709 EXPORT_SYMBOL(fman_port_bind);
1710
1711 /**
1712  * fman_port_get_qman_channel_id
1713  * port:        Pointer to the FMan port devuce
1714  *
1715  * Get the QMan channel ID for the specific port
1716  *
1717  * Return: QMan channel ID
1718  */
1719 u32 fman_port_get_qman_channel_id(struct fman_port *port)
1720 {
1721         return port->dts_params.qman_channel_id;
1722 }
1723 EXPORT_SYMBOL(fman_port_get_qman_channel_id);
1724
1725 int fman_port_get_hash_result_offset(struct fman_port *port, u32 *offset)
1726 {
1727         if (port->buffer_offsets.hash_result_offset == ILLEGAL_BASE)
1728                 return -EINVAL;
1729
1730         *offset = port->buffer_offsets.hash_result_offset;
1731
1732         return 0;
1733 }
1734 EXPORT_SYMBOL(fman_port_get_hash_result_offset);
1735
1736 static int fman_port_probe(struct platform_device *of_dev)
1737 {
1738         struct fman_port *port;
1739         struct fman *fman;
1740         struct device_node *fm_node, *port_node;
1741         struct resource res;
1742         struct resource *dev_res;
1743         u32 val;
1744         int err = 0, lenp;
1745         enum fman_port_type port_type;
1746         u16 port_speed;
1747         u8 port_id;
1748
1749         port = kzalloc(sizeof(*port), GFP_KERNEL);
1750         if (!port)
1751                 return -ENOMEM;
1752
1753         port->dev = &of_dev->dev;
1754
1755         port_node = of_node_get(of_dev->dev.of_node);
1756
1757         /* Get the FM node */
1758         fm_node = of_get_parent(port_node);
1759         if (!fm_node) {
1760                 dev_err(port->dev, "%s: of_get_parent() failed\n", __func__);
1761                 err = -ENODEV;
1762                 goto return_err;
1763         }
1764
1765         fman = dev_get_drvdata(&of_find_device_by_node(fm_node)->dev);
1766         of_node_put(fm_node);
1767         if (!fman) {
1768                 err = -EINVAL;
1769                 goto return_err;
1770         }
1771
1772         err = of_property_read_u32(port_node, "cell-index", &val);
1773         if (err) {
1774                 dev_err(port->dev, "%s: reading cell-index for %pOF failed\n",
1775                         __func__, port_node);
1776                 err = -EINVAL;
1777                 goto return_err;
1778         }
1779         port_id = (u8)val;
1780         port->dts_params.id = port_id;
1781
1782         if (of_device_is_compatible(port_node, "fsl,fman-v3-port-tx")) {
1783                 port_type = FMAN_PORT_TYPE_TX;
1784                 port_speed = 1000;
1785                 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp))
1786                         port_speed = 10000;
1787
1788         } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-tx")) {
1789                 if (port_id >= TX_10G_PORT_BASE)
1790                         port_speed = 10000;
1791                 else
1792                         port_speed = 1000;
1793                 port_type = FMAN_PORT_TYPE_TX;
1794
1795         } else if (of_device_is_compatible(port_node, "fsl,fman-v3-port-rx")) {
1796                 port_type = FMAN_PORT_TYPE_RX;
1797                 port_speed = 1000;
1798                 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp))
1799                         port_speed = 10000;
1800
1801         } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-rx")) {
1802                 if (port_id >= RX_10G_PORT_BASE)
1803                         port_speed = 10000;
1804                 else
1805                         port_speed = 1000;
1806                 port_type = FMAN_PORT_TYPE_RX;
1807
1808         }  else {
1809                 dev_err(port->dev, "%s: Illegal port type\n", __func__);
1810                 err = -EINVAL;
1811                 goto return_err;
1812         }
1813
1814         port->dts_params.type = port_type;
1815         port->dts_params.speed = port_speed;
1816
1817         if (port_type == FMAN_PORT_TYPE_TX) {
1818                 u32 qman_channel_id;
1819
1820                 qman_channel_id = fman_get_qman_channel_id(fman, port_id);
1821                 if (qman_channel_id == 0) {
1822                         dev_err(port->dev, "%s: incorrect qman-channel-id\n",
1823                                 __func__);
1824                         err = -EINVAL;
1825                         goto return_err;
1826                 }
1827                 port->dts_params.qman_channel_id = qman_channel_id;
1828         }
1829
1830         err = of_address_to_resource(port_node, 0, &res);
1831         if (err < 0) {
1832                 dev_err(port->dev, "%s: of_address_to_resource() failed\n",
1833                         __func__);
1834                 err = -ENOMEM;
1835                 goto return_err;
1836         }
1837
1838         port->dts_params.fman = fman;
1839
1840         of_node_put(port_node);
1841
1842         dev_res = __devm_request_region(port->dev, &res, res.start,
1843                                         resource_size(&res), "fman-port");
1844         if (!dev_res) {
1845                 dev_err(port->dev, "%s: __devm_request_region() failed\n",
1846                         __func__);
1847                 err = -EINVAL;
1848                 goto free_port;
1849         }
1850
1851         port->dts_params.base_addr = devm_ioremap(port->dev, res.start,
1852                                                   resource_size(&res));
1853         if (!port->dts_params.base_addr)
1854                 dev_err(port->dev, "%s: devm_ioremap() failed\n", __func__);
1855
1856         dev_set_drvdata(&of_dev->dev, port);
1857
1858         return 0;
1859
1860 return_err:
1861         of_node_put(port_node);
1862 free_port:
1863         kfree(port);
1864         return err;
1865 }
1866
1867 static const struct of_device_id fman_port_match[] = {
1868         {.compatible = "fsl,fman-v3-port-rx"},
1869         {.compatible = "fsl,fman-v2-port-rx"},
1870         {.compatible = "fsl,fman-v3-port-tx"},
1871         {.compatible = "fsl,fman-v2-port-tx"},
1872         {}
1873 };
1874
1875 MODULE_DEVICE_TABLE(of, fman_port_match);
1876
1877 static struct platform_driver fman_port_driver = {
1878         .driver = {
1879                 .name = "fsl-fman-port",
1880                 .of_match_table = fman_port_match,
1881         },
1882         .probe = fman_port_probe,
1883 };
1884
1885 static int __init fman_port_load(void)
1886 {
1887         int err;
1888
1889         pr_debug("FSL DPAA FMan driver\n");
1890
1891         err = platform_driver_register(&fman_port_driver);
1892         if (err < 0)
1893                 pr_err("Error, platform_driver_register() = %d\n", err);
1894
1895         return err;
1896 }
1897 module_init(fman_port_load);
1898
1899 static void __exit fman_port_unload(void)
1900 {
1901         platform_driver_unregister(&fman_port_driver);
1902 }
1903 module_exit(fman_port_unload);
1904
1905 MODULE_LICENSE("Dual BSD/GPL");
1906 MODULE_DESCRIPTION("Freescale DPAA Frame Manager Port driver");