1 // SPDX-License-Identifier: GPL-2.0+
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/icmp.h>
45 #include <linux/spinlock.h>
46 #include <linux/workqueue.h>
47 #include <linux/bitops.h>
49 #include <linux/irq.h>
50 #include <linux/clk.h>
51 #include <linux/crc32.h>
52 #include <linux/platform_device.h>
53 #include <linux/mdio.h>
54 #include <linux/phy.h>
55 #include <linux/fec.h>
57 #include <linux/of_device.h>
58 #include <linux/of_gpio.h>
59 #include <linux/of_mdio.h>
60 #include <linux/of_net.h>
61 #include <linux/regulator/consumer.h>
62 #include <linux/if_vlan.h>
63 #include <linux/pinctrl/consumer.h>
64 #include <linux/prefetch.h>
65 #include <soc/imx/cpuidle.h>
67 #include <asm/cacheflush.h>
71 static void set_multicast_list(struct net_device *ndev);
72 static void fec_enet_itr_coal_init(struct net_device *ndev);
74 #define DRIVER_NAME "fec"
76 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
78 /* Pause frame feild and FIFO threshold */
79 #define FEC_ENET_FCE (1 << 5)
80 #define FEC_ENET_RSEM_V 0x84
81 #define FEC_ENET_RSFL_V 16
82 #define FEC_ENET_RAEM_V 0x8
83 #define FEC_ENET_RAFL_V 0x8
84 #define FEC_ENET_OPD_V 0xFFF0
85 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
87 static struct platform_device_id fec_devtype[] = {
89 /* keep it for coldfire */
94 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
98 .driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
102 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
111 .name = "mvf600-fec",
112 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
114 .name = "imx6sx-fec",
115 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
116 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
117 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
118 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
119 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
121 .name = "imx6ul-fec",
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
125 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
126 FEC_QUIRK_HAS_COALESCE,
131 MODULE_DEVICE_TABLE(platform, fec_devtype);
134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
135 IMX27_FEC, /* runs on i.mx27/35/51 */
143 static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
149 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
150 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
153 MODULE_DEVICE_TABLE(of, fec_dt_ids);
155 static unsigned char macaddr[ETH_ALEN];
156 module_param_array(macaddr, byte, NULL, 0);
157 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
159 #if defined(CONFIG_M5272)
161 * Some hardware gets it MAC address out of local flash memory.
162 * if this is non-zero then assume it is the address to get MAC from.
164 #if defined(CONFIG_NETtel)
165 #define FEC_FLASHMAC 0xf0006006
166 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
167 #define FEC_FLASHMAC 0xf0006000
168 #elif defined(CONFIG_CANCam)
169 #define FEC_FLASHMAC 0xf0020000
170 #elif defined (CONFIG_M5272C3)
171 #define FEC_FLASHMAC (0xffe04000 + 4)
172 #elif defined(CONFIG_MOD5272)
173 #define FEC_FLASHMAC 0xffc0406b
175 #define FEC_FLASHMAC 0
177 #endif /* CONFIG_M5272 */
179 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
181 * 2048 byte skbufs are allocated. However, alignment requirements
182 * varies between FEC variants. Worst case is 64, so round down by 64.
184 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
185 #define PKT_MINBUF_SIZE 64
187 /* FEC receive acceleration */
188 #define FEC_RACC_IPDIS (1 << 1)
189 #define FEC_RACC_PRODIS (1 << 2)
190 #define FEC_RACC_SHIFT16 BIT(7)
191 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
193 /* MIB Control Register */
194 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
197 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
198 * size bits. Other FEC hardware does not, so we need to take that into
199 * account when setting it.
201 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
202 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
203 defined(CONFIG_ARM64)
204 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
206 #define OPT_FRAME_SIZE 0
209 /* FEC MII MMFR bits definition */
210 #define FEC_MMFR_ST (1 << 30)
211 #define FEC_MMFR_OP_READ (2 << 28)
212 #define FEC_MMFR_OP_WRITE (1 << 28)
213 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
214 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
215 #define FEC_MMFR_TA (2 << 16)
216 #define FEC_MMFR_DATA(v) (v & 0xffff)
217 /* FEC ECR bits definition */
218 #define FEC_ECR_MAGICEN (1 << 2)
219 #define FEC_ECR_SLEEP (1 << 3)
221 #define FEC_MII_TIMEOUT 30000 /* us */
223 /* Transmitter timeout */
224 #define TX_TIMEOUT (2 * HZ)
226 #define FEC_PAUSE_FLAG_AUTONEG 0x1
227 #define FEC_PAUSE_FLAG_ENABLE 0x2
228 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
229 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
230 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
232 #define COPYBREAK_DEFAULT 256
234 /* Max number of allowed TCP segments for software TSO */
235 #define FEC_MAX_TSO_SEGS 100
236 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
238 #define IS_TSO_HEADER(txq, addr) \
239 ((addr >= txq->tso_hdrs_dma) && \
240 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
244 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
245 struct bufdesc_prop *bd)
247 return (bdp >= bd->last) ? bd->base
248 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
251 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
252 struct bufdesc_prop *bd)
254 return (bdp <= bd->base) ? bd->last
255 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
258 static int fec_enet_get_bd_index(struct bufdesc *bdp,
259 struct bufdesc_prop *bd)
261 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
264 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
268 entries = (((const char *)txq->dirty_tx -
269 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
271 return entries >= 0 ? entries : entries + txq->bd.ring_size;
274 static void swap_buffer(void *bufaddr, int len)
277 unsigned int *buf = bufaddr;
279 for (i = 0; i < len; i += 4, buf++)
283 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
286 unsigned int *src = src_buf;
287 unsigned int *dst = dst_buf;
289 for (i = 0; i < len; i += 4, src++, dst++)
293 static void fec_dump(struct net_device *ndev)
295 struct fec_enet_private *fep = netdev_priv(ndev);
297 struct fec_enet_priv_tx_q *txq;
300 netdev_info(ndev, "TX ring dump\n");
301 pr_info("Nr SC addr len SKB\n");
303 txq = fep->tx_queue[0];
307 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
309 bdp == txq->bd.cur ? 'S' : ' ',
310 bdp == txq->dirty_tx ? 'H' : ' ',
311 fec16_to_cpu(bdp->cbd_sc),
312 fec32_to_cpu(bdp->cbd_bufaddr),
313 fec16_to_cpu(bdp->cbd_datlen),
314 txq->tx_skbuff[index]);
315 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
317 } while (bdp != txq->bd.base);
320 static inline bool is_ipv4_pkt(struct sk_buff *skb)
322 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
326 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
328 /* Only run for packets requiring a checksum. */
329 if (skb->ip_summed != CHECKSUM_PARTIAL)
332 if (unlikely(skb_cow_head(skb, 0)))
335 if (is_ipv4_pkt(skb))
336 ip_hdr(skb)->check = 0;
337 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
342 static struct bufdesc *
343 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
345 struct net_device *ndev)
347 struct fec_enet_private *fep = netdev_priv(ndev);
348 struct bufdesc *bdp = txq->bd.cur;
349 struct bufdesc_ex *ebdp;
350 int nr_frags = skb_shinfo(skb)->nr_frags;
352 unsigned short status;
353 unsigned int estatus = 0;
354 skb_frag_t *this_frag;
360 for (frag = 0; frag < nr_frags; frag++) {
361 this_frag = &skb_shinfo(skb)->frags[frag];
362 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
363 ebdp = (struct bufdesc_ex *)bdp;
365 status = fec16_to_cpu(bdp->cbd_sc);
366 status &= ~BD_ENET_TX_STATS;
367 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
368 frag_len = skb_shinfo(skb)->frags[frag].size;
370 /* Handle the last BD specially */
371 if (frag == nr_frags - 1) {
372 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
373 if (fep->bufdesc_ex) {
374 estatus |= BD_ENET_TX_INT;
375 if (unlikely(skb_shinfo(skb)->tx_flags &
376 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
377 estatus |= BD_ENET_TX_TS;
381 if (fep->bufdesc_ex) {
382 if (fep->quirks & FEC_QUIRK_HAS_AVB)
383 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
384 if (skb->ip_summed == CHECKSUM_PARTIAL)
385 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
387 ebdp->cbd_esc = cpu_to_fec32(estatus);
390 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
392 index = fec_enet_get_bd_index(bdp, &txq->bd);
393 if (((unsigned long) bufaddr) & fep->tx_align ||
394 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
395 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
396 bufaddr = txq->tx_bounce[index];
398 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
399 swap_buffer(bufaddr, frag_len);
402 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
404 if (dma_mapping_error(&fep->pdev->dev, addr)) {
406 netdev_err(ndev, "Tx DMA memory map failed\n");
407 goto dma_mapping_error;
410 bdp->cbd_bufaddr = cpu_to_fec32(addr);
411 bdp->cbd_datlen = cpu_to_fec16(frag_len);
412 /* Make sure the updates to rest of the descriptor are
413 * performed before transferring ownership.
416 bdp->cbd_sc = cpu_to_fec16(status);
422 for (i = 0; i < frag; i++) {
423 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
424 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
425 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
427 return ERR_PTR(-ENOMEM);
430 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
431 struct sk_buff *skb, struct net_device *ndev)
433 struct fec_enet_private *fep = netdev_priv(ndev);
434 int nr_frags = skb_shinfo(skb)->nr_frags;
435 struct bufdesc *bdp, *last_bdp;
438 unsigned short status;
439 unsigned short buflen;
440 unsigned int estatus = 0;
444 entries_free = fec_enet_get_free_txdesc_num(txq);
445 if (entries_free < MAX_SKB_FRAGS + 1) {
446 dev_kfree_skb_any(skb);
448 netdev_err(ndev, "NOT enough BD for SG!\n");
452 /* Protocol checksum off-load for TCP and UDP. */
453 if (fec_enet_clear_csum(skb, ndev)) {
454 dev_kfree_skb_any(skb);
458 /* Fill in a Tx ring entry */
461 status = fec16_to_cpu(bdp->cbd_sc);
462 status &= ~BD_ENET_TX_STATS;
464 /* Set buffer length and buffer pointer */
466 buflen = skb_headlen(skb);
468 index = fec_enet_get_bd_index(bdp, &txq->bd);
469 if (((unsigned long) bufaddr) & fep->tx_align ||
470 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
471 memcpy(txq->tx_bounce[index], skb->data, buflen);
472 bufaddr = txq->tx_bounce[index];
474 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
475 swap_buffer(bufaddr, buflen);
478 /* Push the data cache so the CPM does not get stale memory data. */
479 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
480 if (dma_mapping_error(&fep->pdev->dev, addr)) {
481 dev_kfree_skb_any(skb);
483 netdev_err(ndev, "Tx DMA memory map failed\n");
488 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
489 if (IS_ERR(last_bdp)) {
490 dma_unmap_single(&fep->pdev->dev, addr,
491 buflen, DMA_TO_DEVICE);
492 dev_kfree_skb_any(skb);
496 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
497 if (fep->bufdesc_ex) {
498 estatus = BD_ENET_TX_INT;
499 if (unlikely(skb_shinfo(skb)->tx_flags &
500 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
501 estatus |= BD_ENET_TX_TS;
504 bdp->cbd_bufaddr = cpu_to_fec32(addr);
505 bdp->cbd_datlen = cpu_to_fec16(buflen);
507 if (fep->bufdesc_ex) {
509 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
511 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
513 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
515 if (fep->quirks & FEC_QUIRK_HAS_AVB)
516 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
518 if (skb->ip_summed == CHECKSUM_PARTIAL)
519 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
522 ebdp->cbd_esc = cpu_to_fec32(estatus);
525 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
526 /* Save skb pointer */
527 txq->tx_skbuff[index] = skb;
529 /* Make sure the updates to rest of the descriptor are performed before
530 * transferring ownership.
534 /* Send it on its way. Tell FEC it's ready, interrupt when done,
535 * it's the last BD of the frame, and to put the CRC on the end.
537 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
538 bdp->cbd_sc = cpu_to_fec16(status);
540 /* If this was the last BD in the ring, start at the beginning again. */
541 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
543 skb_tx_timestamp(skb);
545 /* Make sure the update to bdp and tx_skbuff are performed before
551 /* Trigger transmission start */
552 writel(0, txq->bd.reg_desc_active);
558 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
559 struct net_device *ndev,
560 struct bufdesc *bdp, int index, char *data,
561 int size, bool last_tcp, bool is_last)
563 struct fec_enet_private *fep = netdev_priv(ndev);
564 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
565 unsigned short status;
566 unsigned int estatus = 0;
569 status = fec16_to_cpu(bdp->cbd_sc);
570 status &= ~BD_ENET_TX_STATS;
572 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
574 if (((unsigned long) data) & fep->tx_align ||
575 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
576 memcpy(txq->tx_bounce[index], data, size);
577 data = txq->tx_bounce[index];
579 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
580 swap_buffer(data, size);
583 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
584 if (dma_mapping_error(&fep->pdev->dev, addr)) {
585 dev_kfree_skb_any(skb);
587 netdev_err(ndev, "Tx DMA memory map failed\n");
588 return NETDEV_TX_BUSY;
591 bdp->cbd_datlen = cpu_to_fec16(size);
592 bdp->cbd_bufaddr = cpu_to_fec32(addr);
594 if (fep->bufdesc_ex) {
595 if (fep->quirks & FEC_QUIRK_HAS_AVB)
596 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
597 if (skb->ip_summed == CHECKSUM_PARTIAL)
598 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
600 ebdp->cbd_esc = cpu_to_fec32(estatus);
603 /* Handle the last BD specially */
605 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
607 status |= BD_ENET_TX_INTR;
609 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
612 bdp->cbd_sc = cpu_to_fec16(status);
618 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
619 struct sk_buff *skb, struct net_device *ndev,
620 struct bufdesc *bdp, int index)
622 struct fec_enet_private *fep = netdev_priv(ndev);
623 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
624 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
626 unsigned long dmabuf;
627 unsigned short status;
628 unsigned int estatus = 0;
630 status = fec16_to_cpu(bdp->cbd_sc);
631 status &= ~BD_ENET_TX_STATS;
632 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
634 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
635 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
636 if (((unsigned long)bufaddr) & fep->tx_align ||
637 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
638 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
639 bufaddr = txq->tx_bounce[index];
641 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
642 swap_buffer(bufaddr, hdr_len);
644 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
645 hdr_len, DMA_TO_DEVICE);
646 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
647 dev_kfree_skb_any(skb);
649 netdev_err(ndev, "Tx DMA memory map failed\n");
650 return NETDEV_TX_BUSY;
654 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
655 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
657 if (fep->bufdesc_ex) {
658 if (fep->quirks & FEC_QUIRK_HAS_AVB)
659 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
660 if (skb->ip_summed == CHECKSUM_PARTIAL)
661 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
663 ebdp->cbd_esc = cpu_to_fec32(estatus);
666 bdp->cbd_sc = cpu_to_fec16(status);
671 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
673 struct net_device *ndev)
675 struct fec_enet_private *fep = netdev_priv(ndev);
676 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
677 int total_len, data_left;
678 struct bufdesc *bdp = txq->bd.cur;
680 unsigned int index = 0;
683 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
684 dev_kfree_skb_any(skb);
686 netdev_err(ndev, "NOT enough BD for TSO!\n");
690 /* Protocol checksum off-load for TCP and UDP. */
691 if (fec_enet_clear_csum(skb, ndev)) {
692 dev_kfree_skb_any(skb);
696 /* Initialize the TSO handler, and prepare the first payload */
697 tso_start(skb, &tso);
699 total_len = skb->len - hdr_len;
700 while (total_len > 0) {
703 index = fec_enet_get_bd_index(bdp, &txq->bd);
704 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
705 total_len -= data_left;
707 /* prepare packet headers: MAC + IP + TCP */
708 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
709 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
710 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
714 while (data_left > 0) {
717 size = min_t(int, tso.size, data_left);
718 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
719 index = fec_enet_get_bd_index(bdp, &txq->bd);
720 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
729 tso_build_data(skb, &tso, size);
732 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
735 /* Save skb pointer */
736 txq->tx_skbuff[index] = skb;
738 skb_tx_timestamp(skb);
741 /* Trigger transmission start */
742 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
743 !readl(txq->bd.reg_desc_active) ||
744 !readl(txq->bd.reg_desc_active) ||
745 !readl(txq->bd.reg_desc_active) ||
746 !readl(txq->bd.reg_desc_active))
747 writel(0, txq->bd.reg_desc_active);
752 /* TODO: Release all used data descriptors for TSO */
757 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
759 struct fec_enet_private *fep = netdev_priv(ndev);
761 unsigned short queue;
762 struct fec_enet_priv_tx_q *txq;
763 struct netdev_queue *nq;
766 queue = skb_get_queue_mapping(skb);
767 txq = fep->tx_queue[queue];
768 nq = netdev_get_tx_queue(ndev, queue);
771 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
773 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
777 entries_free = fec_enet_get_free_txdesc_num(txq);
778 if (entries_free <= txq->tx_stop_threshold)
779 netif_tx_stop_queue(nq);
784 /* Init RX & TX buffer descriptors
786 static void fec_enet_bd_init(struct net_device *dev)
788 struct fec_enet_private *fep = netdev_priv(dev);
789 struct fec_enet_priv_tx_q *txq;
790 struct fec_enet_priv_rx_q *rxq;
795 for (q = 0; q < fep->num_rx_queues; q++) {
796 /* Initialize the receive buffer descriptors. */
797 rxq = fep->rx_queue[q];
800 for (i = 0; i < rxq->bd.ring_size; i++) {
802 /* Initialize the BD for every fragment in the page. */
803 if (bdp->cbd_bufaddr)
804 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
806 bdp->cbd_sc = cpu_to_fec16(0);
807 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
810 /* Set the last buffer to wrap */
811 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
812 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
814 rxq->bd.cur = rxq->bd.base;
817 for (q = 0; q < fep->num_tx_queues; q++) {
818 /* ...and the same for transmit */
819 txq = fep->tx_queue[q];
823 for (i = 0; i < txq->bd.ring_size; i++) {
824 /* Initialize the BD for every fragment in the page. */
825 bdp->cbd_sc = cpu_to_fec16(0);
826 if (bdp->cbd_bufaddr &&
827 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
828 dma_unmap_single(&fep->pdev->dev,
829 fec32_to_cpu(bdp->cbd_bufaddr),
830 fec16_to_cpu(bdp->cbd_datlen),
832 if (txq->tx_skbuff[i]) {
833 dev_kfree_skb_any(txq->tx_skbuff[i]);
834 txq->tx_skbuff[i] = NULL;
836 bdp->cbd_bufaddr = cpu_to_fec32(0);
837 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
840 /* Set the last buffer to wrap */
841 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
842 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
847 static void fec_enet_active_rxring(struct net_device *ndev)
849 struct fec_enet_private *fep = netdev_priv(ndev);
852 for (i = 0; i < fep->num_rx_queues; i++)
853 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
856 static void fec_enet_enable_ring(struct net_device *ndev)
858 struct fec_enet_private *fep = netdev_priv(ndev);
859 struct fec_enet_priv_tx_q *txq;
860 struct fec_enet_priv_rx_q *rxq;
863 for (i = 0; i < fep->num_rx_queues; i++) {
864 rxq = fep->rx_queue[i];
865 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
866 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
870 writel(RCMR_MATCHEN | RCMR_CMP(i),
871 fep->hwp + FEC_RCMR(i));
874 for (i = 0; i < fep->num_tx_queues; i++) {
875 txq = fep->tx_queue[i];
876 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
880 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
881 fep->hwp + FEC_DMA_CFG(i));
885 static void fec_enet_reset_skb(struct net_device *ndev)
887 struct fec_enet_private *fep = netdev_priv(ndev);
888 struct fec_enet_priv_tx_q *txq;
891 for (i = 0; i < fep->num_tx_queues; i++) {
892 txq = fep->tx_queue[i];
894 for (j = 0; j < txq->bd.ring_size; j++) {
895 if (txq->tx_skbuff[j]) {
896 dev_kfree_skb_any(txq->tx_skbuff[j]);
897 txq->tx_skbuff[j] = NULL;
904 * This function is called to start or restart the FEC during a link
905 * change, transmit timeout, or to reconfigure the FEC. The network
906 * packet processing for this device must be stopped before this call.
909 fec_restart(struct net_device *ndev)
911 struct fec_enet_private *fep = netdev_priv(ndev);
914 u32 rcntl = OPT_FRAME_SIZE | 0x04;
915 u32 ecntl = 0x2; /* ETHEREN */
917 /* Whack a reset. We should wait for this.
918 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
919 * instead of reset MAC itself.
921 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
922 writel(0, fep->hwp + FEC_ECNTRL);
924 writel(1, fep->hwp + FEC_ECNTRL);
929 * enet-mac reset will reset mac address registers too,
930 * so need to reconfigure it.
932 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
933 writel((__force u32)cpu_to_be32(temp_mac[0]),
934 fep->hwp + FEC_ADDR_LOW);
935 writel((__force u32)cpu_to_be32(temp_mac[1]),
936 fep->hwp + FEC_ADDR_HIGH);
938 /* Clear any outstanding interrupt. */
939 writel(0xffffffff, fep->hwp + FEC_IEVENT);
941 fec_enet_bd_init(ndev);
943 fec_enet_enable_ring(ndev);
945 /* Reset tx SKB buffers. */
946 fec_enet_reset_skb(ndev);
948 /* Enable MII mode */
949 if (fep->full_duplex == DUPLEX_FULL) {
951 writel(0x04, fep->hwp + FEC_X_CNTRL);
955 writel(0x0, fep->hwp + FEC_X_CNTRL);
959 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
961 #if !defined(CONFIG_M5272)
962 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
963 val = readl(fep->hwp + FEC_RACC);
964 /* align IP header */
965 val |= FEC_RACC_SHIFT16;
966 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
967 /* set RX checksum */
968 val |= FEC_RACC_OPTIONS;
970 val &= ~FEC_RACC_OPTIONS;
971 writel(val, fep->hwp + FEC_RACC);
972 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
977 * The phy interface and speed need to get configured
978 * differently on enet-mac.
980 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
981 /* Enable flow control and length check */
982 rcntl |= 0x40000000 | 0x00000020;
984 /* RGMII, RMII or MII */
985 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
986 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
987 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
988 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
990 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
995 /* 1G, 100M or 10M */
997 if (ndev->phydev->speed == SPEED_1000)
999 else if (ndev->phydev->speed == SPEED_100)
1005 #ifdef FEC_MIIGSK_ENR
1006 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1008 /* disable the gasket and wait */
1009 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1010 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1014 * configure the gasket:
1015 * RMII, 50 MHz, no loopback, no echo
1016 * MII, 25 MHz, no loopback, no echo
1018 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1019 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1020 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1021 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1022 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1024 /* re-enable the gasket */
1025 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1030 #if !defined(CONFIG_M5272)
1031 /* enable pause frame*/
1032 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1033 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1034 ndev->phydev && ndev->phydev->pause)) {
1035 rcntl |= FEC_ENET_FCE;
1037 /* set FIFO threshold parameter to reduce overrun */
1038 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1039 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1040 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1041 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1044 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1046 rcntl &= ~FEC_ENET_FCE;
1048 #endif /* !defined(CONFIG_M5272) */
1050 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1052 /* Setup multicast filter. */
1053 set_multicast_list(ndev);
1054 #ifndef CONFIG_M5272
1055 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1056 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1059 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1060 /* enable ENET endian swap */
1062 /* enable ENET store and forward mode */
1063 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1066 if (fep->bufdesc_ex)
1069 #ifndef CONFIG_M5272
1070 /* Enable the MIB statistic event counters */
1071 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1074 /* And last, enable the transmit and receive processing */
1075 writel(ecntl, fep->hwp + FEC_ECNTRL);
1076 fec_enet_active_rxring(ndev);
1078 if (fep->bufdesc_ex)
1079 fec_ptp_start_cyclecounter(ndev);
1081 /* Enable interrupts we wish to service */
1083 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1085 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1087 /* Init the interrupt coalescing */
1088 fec_enet_itr_coal_init(ndev);
1093 fec_stop(struct net_device *ndev)
1095 struct fec_enet_private *fep = netdev_priv(ndev);
1096 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1097 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1100 /* We cannot expect a graceful transmit stop without link !!! */
1102 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1104 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1105 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1108 /* Whack a reset. We should wait for this.
1109 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1110 * instead of reset MAC itself.
1112 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1113 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1114 writel(0, fep->hwp + FEC_ECNTRL);
1116 writel(1, fep->hwp + FEC_ECNTRL);
1119 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1121 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1122 val = readl(fep->hwp + FEC_ECNTRL);
1123 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1124 writel(val, fep->hwp + FEC_ECNTRL);
1126 if (pdata && pdata->sleep_mode_enable)
1127 pdata->sleep_mode_enable(true);
1129 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1131 /* We have to keep ENET enabled to have MII interrupt stay working */
1132 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1133 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1134 writel(2, fep->hwp + FEC_ECNTRL);
1135 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1141 fec_timeout(struct net_device *ndev)
1143 struct fec_enet_private *fep = netdev_priv(ndev);
1147 ndev->stats.tx_errors++;
1149 schedule_work(&fep->tx_timeout_work);
1152 static void fec_enet_timeout_work(struct work_struct *work)
1154 struct fec_enet_private *fep =
1155 container_of(work, struct fec_enet_private, tx_timeout_work);
1156 struct net_device *ndev = fep->netdev;
1159 if (netif_device_present(ndev) || netif_running(ndev)) {
1160 napi_disable(&fep->napi);
1161 netif_tx_lock_bh(ndev);
1163 netif_tx_wake_all_queues(ndev);
1164 netif_tx_unlock_bh(ndev);
1165 napi_enable(&fep->napi);
1171 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1172 struct skb_shared_hwtstamps *hwtstamps)
1174 unsigned long flags;
1177 spin_lock_irqsave(&fep->tmreg_lock, flags);
1178 ns = timecounter_cyc2time(&fep->tc, ts);
1179 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1181 memset(hwtstamps, 0, sizeof(*hwtstamps));
1182 hwtstamps->hwtstamp = ns_to_ktime(ns);
1186 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1188 struct fec_enet_private *fep;
1189 struct bufdesc *bdp;
1190 unsigned short status;
1191 struct sk_buff *skb;
1192 struct fec_enet_priv_tx_q *txq;
1193 struct netdev_queue *nq;
1197 fep = netdev_priv(ndev);
1199 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1201 txq = fep->tx_queue[queue_id];
1202 /* get next bdp of dirty_tx */
1203 nq = netdev_get_tx_queue(ndev, queue_id);
1204 bdp = txq->dirty_tx;
1206 /* get next bdp of dirty_tx */
1207 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1209 while (bdp != READ_ONCE(txq->bd.cur)) {
1210 /* Order the load of bd.cur and cbd_sc */
1212 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1213 if (status & BD_ENET_TX_READY)
1216 index = fec_enet_get_bd_index(bdp, &txq->bd);
1218 skb = txq->tx_skbuff[index];
1219 txq->tx_skbuff[index] = NULL;
1220 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1221 dma_unmap_single(&fep->pdev->dev,
1222 fec32_to_cpu(bdp->cbd_bufaddr),
1223 fec16_to_cpu(bdp->cbd_datlen),
1225 bdp->cbd_bufaddr = cpu_to_fec32(0);
1229 /* Check for errors. */
1230 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1231 BD_ENET_TX_RL | BD_ENET_TX_UN |
1233 ndev->stats.tx_errors++;
1234 if (status & BD_ENET_TX_HB) /* No heartbeat */
1235 ndev->stats.tx_heartbeat_errors++;
1236 if (status & BD_ENET_TX_LC) /* Late collision */
1237 ndev->stats.tx_window_errors++;
1238 if (status & BD_ENET_TX_RL) /* Retrans limit */
1239 ndev->stats.tx_aborted_errors++;
1240 if (status & BD_ENET_TX_UN) /* Underrun */
1241 ndev->stats.tx_fifo_errors++;
1242 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1243 ndev->stats.tx_carrier_errors++;
1245 ndev->stats.tx_packets++;
1246 ndev->stats.tx_bytes += skb->len;
1249 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1251 struct skb_shared_hwtstamps shhwtstamps;
1252 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1254 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1255 skb_tstamp_tx(skb, &shhwtstamps);
1258 /* Deferred means some collisions occurred during transmit,
1259 * but we eventually sent the packet OK.
1261 if (status & BD_ENET_TX_DEF)
1262 ndev->stats.collisions++;
1264 /* Free the sk buffer associated with this last transmit */
1265 dev_kfree_skb_any(skb);
1267 /* Make sure the update to bdp and tx_skbuff are performed
1271 txq->dirty_tx = bdp;
1273 /* Update pointer to next buffer descriptor to be transmitted */
1274 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1276 /* Since we have freed up a buffer, the ring is no longer full
1278 if (netif_tx_queue_stopped(nq)) {
1279 entries_free = fec_enet_get_free_txdesc_num(txq);
1280 if (entries_free >= txq->tx_wake_threshold)
1281 netif_tx_wake_queue(nq);
1285 /* ERR006358: Keep the transmitter going */
1286 if (bdp != txq->bd.cur &&
1287 readl(txq->bd.reg_desc_active) == 0)
1288 writel(0, txq->bd.reg_desc_active);
1292 fec_enet_tx(struct net_device *ndev)
1294 struct fec_enet_private *fep = netdev_priv(ndev);
1296 /* First process class A queue, then Class B and Best Effort queue */
1297 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1298 clear_bit(queue_id, &fep->work_tx);
1299 fec_enet_tx_queue(ndev, queue_id);
1305 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1307 struct fec_enet_private *fep = netdev_priv(ndev);
1310 off = ((unsigned long)skb->data) & fep->rx_align;
1312 skb_reserve(skb, fep->rx_align + 1 - off);
1314 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1315 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1316 if (net_ratelimit())
1317 netdev_err(ndev, "Rx DMA memory map failed\n");
1324 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1325 struct bufdesc *bdp, u32 length, bool swap)
1327 struct fec_enet_private *fep = netdev_priv(ndev);
1328 struct sk_buff *new_skb;
1330 if (length > fep->rx_copybreak)
1333 new_skb = netdev_alloc_skb(ndev, length);
1337 dma_sync_single_for_cpu(&fep->pdev->dev,
1338 fec32_to_cpu(bdp->cbd_bufaddr),
1339 FEC_ENET_RX_FRSIZE - fep->rx_align,
1342 memcpy(new_skb->data, (*skb)->data, length);
1344 swap_buffer2(new_skb->data, (*skb)->data, length);
1350 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1351 * When we update through the ring, if the next incoming buffer has
1352 * not been given to the system, we just set the empty indicator,
1353 * effectively tossing the packet.
1356 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1358 struct fec_enet_private *fep = netdev_priv(ndev);
1359 struct fec_enet_priv_rx_q *rxq;
1360 struct bufdesc *bdp;
1361 unsigned short status;
1362 struct sk_buff *skb_new = NULL;
1363 struct sk_buff *skb;
1366 int pkt_received = 0;
1367 struct bufdesc_ex *ebdp = NULL;
1368 bool vlan_packet_rcvd = false;
1372 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1377 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1378 rxq = fep->rx_queue[queue_id];
1380 /* First, grab all of the stats for the incoming packet.
1381 * These get messed up if we get called due to a busy condition.
1385 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1387 if (pkt_received >= budget)
1391 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1393 /* Check for errors. */
1394 status ^= BD_ENET_RX_LAST;
1395 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1396 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1398 ndev->stats.rx_errors++;
1399 if (status & BD_ENET_RX_OV) {
1401 ndev->stats.rx_fifo_errors++;
1402 goto rx_processing_done;
1404 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1405 | BD_ENET_RX_LAST)) {
1406 /* Frame too long or too short. */
1407 ndev->stats.rx_length_errors++;
1408 if (status & BD_ENET_RX_LAST)
1409 netdev_err(ndev, "rcv is not +last\n");
1411 if (status & BD_ENET_RX_CR) /* CRC Error */
1412 ndev->stats.rx_crc_errors++;
1413 /* Report late collisions as a frame error. */
1414 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1415 ndev->stats.rx_frame_errors++;
1416 goto rx_processing_done;
1419 /* Process the incoming frame. */
1420 ndev->stats.rx_packets++;
1421 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1422 ndev->stats.rx_bytes += pkt_len;
1424 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1425 skb = rxq->rx_skbuff[index];
1427 /* The packet length includes FCS, but we don't want to
1428 * include that when passing upstream as it messes up
1429 * bridging applications.
1431 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1433 if (!is_copybreak) {
1434 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1435 if (unlikely(!skb_new)) {
1436 ndev->stats.rx_dropped++;
1437 goto rx_processing_done;
1439 dma_unmap_single(&fep->pdev->dev,
1440 fec32_to_cpu(bdp->cbd_bufaddr),
1441 FEC_ENET_RX_FRSIZE - fep->rx_align,
1445 prefetch(skb->data - NET_IP_ALIGN);
1446 skb_put(skb, pkt_len - 4);
1449 if (!is_copybreak && need_swap)
1450 swap_buffer(data, pkt_len);
1452 #if !defined(CONFIG_M5272)
1453 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1454 data = skb_pull_inline(skb, 2);
1457 /* Extract the enhanced buffer descriptor */
1459 if (fep->bufdesc_ex)
1460 ebdp = (struct bufdesc_ex *)bdp;
1462 /* If this is a VLAN packet remove the VLAN Tag */
1463 vlan_packet_rcvd = false;
1464 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1466 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1467 /* Push and remove the vlan tag */
1468 struct vlan_hdr *vlan_header =
1469 (struct vlan_hdr *) (data + ETH_HLEN);
1470 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1472 vlan_packet_rcvd = true;
1474 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1475 skb_pull(skb, VLAN_HLEN);
1478 skb->protocol = eth_type_trans(skb, ndev);
1480 /* Get receive timestamp from the skb */
1481 if (fep->hwts_rx_en && fep->bufdesc_ex)
1482 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1483 skb_hwtstamps(skb));
1485 if (fep->bufdesc_ex &&
1486 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1487 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1488 /* don't check it */
1489 skb->ip_summed = CHECKSUM_UNNECESSARY;
1491 skb_checksum_none_assert(skb);
1495 /* Handle received VLAN packets */
1496 if (vlan_packet_rcvd)
1497 __vlan_hwaccel_put_tag(skb,
1501 napi_gro_receive(&fep->napi, skb);
1504 dma_sync_single_for_device(&fep->pdev->dev,
1505 fec32_to_cpu(bdp->cbd_bufaddr),
1506 FEC_ENET_RX_FRSIZE - fep->rx_align,
1509 rxq->rx_skbuff[index] = skb_new;
1510 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1514 /* Clear the status flags for this buffer */
1515 status &= ~BD_ENET_RX_STATS;
1517 /* Mark the buffer empty */
1518 status |= BD_ENET_RX_EMPTY;
1520 if (fep->bufdesc_ex) {
1521 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1523 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1527 /* Make sure the updates to rest of the descriptor are
1528 * performed before transferring ownership.
1531 bdp->cbd_sc = cpu_to_fec16(status);
1533 /* Update BD pointer to next entry */
1534 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1536 /* Doing this here will keep the FEC running while we process
1537 * incoming frames. On a heavily loaded network, we should be
1538 * able to keep up at the expense of system resources.
1540 writel(0, rxq->bd.reg_desc_active);
1543 return pkt_received;
1547 fec_enet_rx(struct net_device *ndev, int budget)
1549 int pkt_received = 0;
1551 struct fec_enet_private *fep = netdev_priv(ndev);
1553 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1556 ret = fec_enet_rx_queue(ndev,
1557 budget - pkt_received, queue_id);
1559 if (ret < budget - pkt_received)
1560 clear_bit(queue_id, &fep->work_rx);
1562 pkt_received += ret;
1564 return pkt_received;
1568 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1570 if (int_events == 0)
1573 if (int_events & FEC_ENET_RXF_0)
1574 fep->work_rx |= (1 << 2);
1575 if (int_events & FEC_ENET_RXF_1)
1576 fep->work_rx |= (1 << 0);
1577 if (int_events & FEC_ENET_RXF_2)
1578 fep->work_rx |= (1 << 1);
1580 if (int_events & FEC_ENET_TXF_0)
1581 fep->work_tx |= (1 << 2);
1582 if (int_events & FEC_ENET_TXF_1)
1583 fep->work_tx |= (1 << 0);
1584 if (int_events & FEC_ENET_TXF_2)
1585 fep->work_tx |= (1 << 1);
1591 fec_enet_interrupt(int irq, void *dev_id)
1593 struct net_device *ndev = dev_id;
1594 struct fec_enet_private *fep = netdev_priv(ndev);
1596 irqreturn_t ret = IRQ_NONE;
1598 int_events = readl(fep->hwp + FEC_IEVENT);
1599 writel(int_events, fep->hwp + FEC_IEVENT);
1600 fec_enet_collect_events(fep, int_events);
1602 if ((fep->work_tx || fep->work_rx) && fep->link) {
1605 if (napi_schedule_prep(&fep->napi)) {
1606 /* Disable the NAPI interrupts */
1607 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1608 __napi_schedule(&fep->napi);
1612 if (int_events & FEC_ENET_MII) {
1614 complete(&fep->mdio_done);
1619 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1621 struct net_device *ndev = napi->dev;
1622 struct fec_enet_private *fep = netdev_priv(ndev);
1625 pkts = fec_enet_rx(ndev, budget);
1629 if (pkts < budget) {
1630 napi_complete_done(napi, pkts);
1631 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1636 /* ------------------------------------------------------------------------- */
1637 static void fec_get_mac(struct net_device *ndev)
1639 struct fec_enet_private *fep = netdev_priv(ndev);
1640 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1641 unsigned char *iap, tmpaddr[ETH_ALEN];
1644 * try to get mac address in following order:
1646 * 1) module parameter via kernel command line in form
1647 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1652 * 2) from device tree data
1654 if (!is_valid_ether_addr(iap)) {
1655 struct device_node *np = fep->pdev->dev.of_node;
1657 const char *mac = of_get_mac_address(np);
1659 iap = (unsigned char *) mac;
1664 * 3) from flash or fuse (via platform data)
1666 if (!is_valid_ether_addr(iap)) {
1669 iap = (unsigned char *)FEC_FLASHMAC;
1672 iap = (unsigned char *)&pdata->mac;
1677 * 4) FEC mac registers set by bootloader
1679 if (!is_valid_ether_addr(iap)) {
1680 *((__be32 *) &tmpaddr[0]) =
1681 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1682 *((__be16 *) &tmpaddr[4]) =
1683 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1688 * 5) random mac address
1690 if (!is_valid_ether_addr(iap)) {
1691 /* Report it and use a random ethernet address instead */
1692 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1693 eth_hw_addr_random(ndev);
1694 netdev_info(ndev, "Using random MAC address: %pM\n",
1699 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1701 /* Adjust MAC if using macaddr */
1703 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1706 /* ------------------------------------------------------------------------- */
1711 static void fec_enet_adjust_link(struct net_device *ndev)
1713 struct fec_enet_private *fep = netdev_priv(ndev);
1714 struct phy_device *phy_dev = ndev->phydev;
1715 int status_change = 0;
1717 /* Prevent a state halted on mii error */
1718 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1719 phy_dev->state = PHY_RESUMING;
1724 * If the netdev is down, or is going down, we're not interested
1725 * in link state events, so just mark our idea of the link as down
1726 * and ignore the event.
1728 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1730 } else if (phy_dev->link) {
1732 fep->link = phy_dev->link;
1736 if (fep->full_duplex != phy_dev->duplex) {
1737 fep->full_duplex = phy_dev->duplex;
1741 if (phy_dev->speed != fep->speed) {
1742 fep->speed = phy_dev->speed;
1746 /* if any of the above changed restart the FEC */
1747 if (status_change) {
1748 napi_disable(&fep->napi);
1749 netif_tx_lock_bh(ndev);
1751 netif_tx_wake_all_queues(ndev);
1752 netif_tx_unlock_bh(ndev);
1753 napi_enable(&fep->napi);
1757 napi_disable(&fep->napi);
1758 netif_tx_lock_bh(ndev);
1760 netif_tx_unlock_bh(ndev);
1761 napi_enable(&fep->napi);
1762 fep->link = phy_dev->link;
1768 phy_print_status(phy_dev);
1771 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1773 struct fec_enet_private *fep = bus->priv;
1774 struct device *dev = &fep->pdev->dev;
1775 unsigned long time_left;
1778 ret = pm_runtime_get_sync(dev);
1782 fep->mii_timeout = 0;
1783 reinit_completion(&fep->mdio_done);
1785 /* start a read op */
1786 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1787 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1788 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1790 /* wait for end of transfer */
1791 time_left = wait_for_completion_timeout(&fep->mdio_done,
1792 usecs_to_jiffies(FEC_MII_TIMEOUT));
1793 if (time_left == 0) {
1794 fep->mii_timeout = 1;
1795 netdev_err(fep->netdev, "MDIO read timeout\n");
1800 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1803 pm_runtime_mark_last_busy(dev);
1804 pm_runtime_put_autosuspend(dev);
1809 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1812 struct fec_enet_private *fep = bus->priv;
1813 struct device *dev = &fep->pdev->dev;
1814 unsigned long time_left;
1817 ret = pm_runtime_get_sync(dev);
1823 fep->mii_timeout = 0;
1824 reinit_completion(&fep->mdio_done);
1826 /* start a write op */
1827 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1828 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1829 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1830 fep->hwp + FEC_MII_DATA);
1832 /* wait for end of transfer */
1833 time_left = wait_for_completion_timeout(&fep->mdio_done,
1834 usecs_to_jiffies(FEC_MII_TIMEOUT));
1835 if (time_left == 0) {
1836 fep->mii_timeout = 1;
1837 netdev_err(fep->netdev, "MDIO write timeout\n");
1841 pm_runtime_mark_last_busy(dev);
1842 pm_runtime_put_autosuspend(dev);
1847 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1849 struct fec_enet_private *fep = netdev_priv(ndev);
1853 ret = clk_prepare_enable(fep->clk_ahb);
1857 ret = clk_prepare_enable(fep->clk_enet_out);
1859 goto failed_clk_enet_out;
1862 mutex_lock(&fep->ptp_clk_mutex);
1863 ret = clk_prepare_enable(fep->clk_ptp);
1865 mutex_unlock(&fep->ptp_clk_mutex);
1866 goto failed_clk_ptp;
1868 fep->ptp_clk_on = true;
1870 mutex_unlock(&fep->ptp_clk_mutex);
1873 ret = clk_prepare_enable(fep->clk_ref);
1875 goto failed_clk_ref;
1877 phy_reset_after_clk_enable(ndev->phydev);
1879 clk_disable_unprepare(fep->clk_ahb);
1880 clk_disable_unprepare(fep->clk_enet_out);
1882 mutex_lock(&fep->ptp_clk_mutex);
1883 clk_disable_unprepare(fep->clk_ptp);
1884 fep->ptp_clk_on = false;
1885 mutex_unlock(&fep->ptp_clk_mutex);
1887 clk_disable_unprepare(fep->clk_ref);
1894 clk_disable_unprepare(fep->clk_ref);
1896 if (fep->clk_enet_out)
1897 clk_disable_unprepare(fep->clk_enet_out);
1898 failed_clk_enet_out:
1899 clk_disable_unprepare(fep->clk_ahb);
1904 static int fec_enet_mii_probe(struct net_device *ndev)
1906 struct fec_enet_private *fep = netdev_priv(ndev);
1907 struct phy_device *phy_dev = NULL;
1908 char mdio_bus_id[MII_BUS_ID_SIZE];
1909 char phy_name[MII_BUS_ID_SIZE + 3];
1911 int dev_id = fep->dev_id;
1913 if (fep->phy_node) {
1914 phy_dev = of_phy_connect(ndev, fep->phy_node,
1915 &fec_enet_adjust_link, 0,
1916 fep->phy_interface);
1918 netdev_err(ndev, "Unable to connect to phy\n");
1922 /* check for attached phy */
1923 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1924 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1928 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1932 if (phy_id >= PHY_MAX_ADDR) {
1933 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1934 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1938 snprintf(phy_name, sizeof(phy_name),
1939 PHY_ID_FMT, mdio_bus_id, phy_id);
1940 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1941 fep->phy_interface);
1944 if (IS_ERR(phy_dev)) {
1945 netdev_err(ndev, "could not attach to PHY\n");
1946 return PTR_ERR(phy_dev);
1949 /* mask with MAC supported features */
1950 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1951 phy_dev->supported &= PHY_GBIT_FEATURES;
1952 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1953 #if !defined(CONFIG_M5272)
1954 phy_dev->supported |= SUPPORTED_Pause;
1958 phy_dev->supported &= PHY_BASIC_FEATURES;
1960 phy_dev->advertising = phy_dev->supported;
1963 fep->full_duplex = 0;
1965 phy_attached_info(phy_dev);
1970 static int fec_enet_mii_init(struct platform_device *pdev)
1972 static struct mii_bus *fec0_mii_bus;
1973 struct net_device *ndev = platform_get_drvdata(pdev);
1974 struct fec_enet_private *fep = netdev_priv(ndev);
1975 struct device_node *node;
1977 u32 mii_speed, holdtime;
1980 * The i.MX28 dual fec interfaces are not equal.
1981 * Here are the differences:
1983 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1984 * - fec0 acts as the 1588 time master while fec1 is slave
1985 * - external phys can only be configured by fec0
1987 * That is to say fec1 can not work independently. It only works
1988 * when fec0 is working. The reason behind this design is that the
1989 * second interface is added primarily for Switch mode.
1991 * Because of the last point above, both phys are attached on fec0
1992 * mdio interface in board design, and need to be configured by
1995 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1996 /* fec1 uses fec0 mii_bus */
1997 if (mii_cnt && fec0_mii_bus) {
1998 fep->mii_bus = fec0_mii_bus;
2005 fep->mii_timeout = 0;
2008 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2010 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2011 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2012 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2015 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2016 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2018 if (mii_speed > 63) {
2020 "fec clock (%lu) too fast to get right mii speed\n",
2021 clk_get_rate(fep->clk_ipg));
2027 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2028 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2029 * versions are RAZ there, so just ignore the difference and write the
2031 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2032 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2034 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2035 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2036 * holdtime cannot result in a value greater than 3.
2038 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2040 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2042 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2044 fep->mii_bus = mdiobus_alloc();
2045 if (fep->mii_bus == NULL) {
2050 fep->mii_bus->name = "fec_enet_mii_bus";
2051 fep->mii_bus->read = fec_enet_mdio_read;
2052 fep->mii_bus->write = fec_enet_mdio_write;
2053 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2054 pdev->name, fep->dev_id + 1);
2055 fep->mii_bus->priv = fep;
2056 fep->mii_bus->parent = &pdev->dev;
2058 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2059 err = of_mdiobus_register(fep->mii_bus, node);
2063 goto err_out_free_mdiobus;
2067 /* save fec0 mii_bus */
2068 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2069 fec0_mii_bus = fep->mii_bus;
2073 err_out_free_mdiobus:
2074 mdiobus_free(fep->mii_bus);
2079 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2081 if (--mii_cnt == 0) {
2082 mdiobus_unregister(fep->mii_bus);
2083 mdiobus_free(fep->mii_bus);
2087 static void fec_enet_get_drvinfo(struct net_device *ndev,
2088 struct ethtool_drvinfo *info)
2090 struct fec_enet_private *fep = netdev_priv(ndev);
2092 strlcpy(info->driver, fep->pdev->dev.driver->name,
2093 sizeof(info->driver));
2094 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2095 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2098 static int fec_enet_get_regs_len(struct net_device *ndev)
2100 struct fec_enet_private *fep = netdev_priv(ndev);
2104 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2106 s = resource_size(r);
2111 /* List of registers that can be safety be read to dump them with ethtool */
2112 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2113 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2114 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2115 static u32 fec_enet_register_offset[] = {
2116 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2117 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2118 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2119 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2120 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2121 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2122 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2123 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2124 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2125 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2126 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2127 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2128 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2129 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2130 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2131 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2132 RMON_T_P_GTE2048, RMON_T_OCTETS,
2133 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2134 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2135 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2136 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2137 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2138 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2139 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2140 RMON_R_P_GTE2048, RMON_R_OCTETS,
2141 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2142 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2145 static u32 fec_enet_register_offset[] = {
2146 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2147 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2148 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2149 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2150 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2151 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2152 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2153 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2154 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2158 static void fec_enet_get_regs(struct net_device *ndev,
2159 struct ethtool_regs *regs, void *regbuf)
2161 struct fec_enet_private *fep = netdev_priv(ndev);
2162 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2163 u32 *buf = (u32 *)regbuf;
2166 memset(buf, 0, regs->len);
2168 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2169 off = fec_enet_register_offset[i];
2171 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2172 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2176 buf[off] = readl(&theregs[off]);
2180 static int fec_enet_get_ts_info(struct net_device *ndev,
2181 struct ethtool_ts_info *info)
2183 struct fec_enet_private *fep = netdev_priv(ndev);
2185 if (fep->bufdesc_ex) {
2187 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2188 SOF_TIMESTAMPING_RX_SOFTWARE |
2189 SOF_TIMESTAMPING_SOFTWARE |
2190 SOF_TIMESTAMPING_TX_HARDWARE |
2191 SOF_TIMESTAMPING_RX_HARDWARE |
2192 SOF_TIMESTAMPING_RAW_HARDWARE;
2194 info->phc_index = ptp_clock_index(fep->ptp_clock);
2196 info->phc_index = -1;
2198 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2199 (1 << HWTSTAMP_TX_ON);
2201 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2202 (1 << HWTSTAMP_FILTER_ALL);
2205 return ethtool_op_get_ts_info(ndev, info);
2209 #if !defined(CONFIG_M5272)
2211 static void fec_enet_get_pauseparam(struct net_device *ndev,
2212 struct ethtool_pauseparam *pause)
2214 struct fec_enet_private *fep = netdev_priv(ndev);
2216 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2217 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2218 pause->rx_pause = pause->tx_pause;
2221 static int fec_enet_set_pauseparam(struct net_device *ndev,
2222 struct ethtool_pauseparam *pause)
2224 struct fec_enet_private *fep = netdev_priv(ndev);
2229 if (pause->tx_pause != pause->rx_pause) {
2231 "hardware only support enable/disable both tx and rx");
2235 fep->pause_flag = 0;
2237 /* tx pause must be same as rx pause */
2238 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2239 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2241 if (pause->rx_pause || pause->autoneg) {
2242 ndev->phydev->supported |= ADVERTISED_Pause;
2243 ndev->phydev->advertising |= ADVERTISED_Pause;
2245 ndev->phydev->supported &= ~ADVERTISED_Pause;
2246 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2249 if (pause->autoneg) {
2250 if (netif_running(ndev))
2252 phy_start_aneg(ndev->phydev);
2254 if (netif_running(ndev)) {
2255 napi_disable(&fep->napi);
2256 netif_tx_lock_bh(ndev);
2258 netif_tx_wake_all_queues(ndev);
2259 netif_tx_unlock_bh(ndev);
2260 napi_enable(&fep->napi);
2266 static const struct fec_stat {
2267 char name[ETH_GSTRING_LEN];
2271 { "tx_dropped", RMON_T_DROP },
2272 { "tx_packets", RMON_T_PACKETS },
2273 { "tx_broadcast", RMON_T_BC_PKT },
2274 { "tx_multicast", RMON_T_MC_PKT },
2275 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2276 { "tx_undersize", RMON_T_UNDERSIZE },
2277 { "tx_oversize", RMON_T_OVERSIZE },
2278 { "tx_fragment", RMON_T_FRAG },
2279 { "tx_jabber", RMON_T_JAB },
2280 { "tx_collision", RMON_T_COL },
2281 { "tx_64byte", RMON_T_P64 },
2282 { "tx_65to127byte", RMON_T_P65TO127 },
2283 { "tx_128to255byte", RMON_T_P128TO255 },
2284 { "tx_256to511byte", RMON_T_P256TO511 },
2285 { "tx_512to1023byte", RMON_T_P512TO1023 },
2286 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2287 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2288 { "tx_octets", RMON_T_OCTETS },
2291 { "IEEE_tx_drop", IEEE_T_DROP },
2292 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2293 { "IEEE_tx_1col", IEEE_T_1COL },
2294 { "IEEE_tx_mcol", IEEE_T_MCOL },
2295 { "IEEE_tx_def", IEEE_T_DEF },
2296 { "IEEE_tx_lcol", IEEE_T_LCOL },
2297 { "IEEE_tx_excol", IEEE_T_EXCOL },
2298 { "IEEE_tx_macerr", IEEE_T_MACERR },
2299 { "IEEE_tx_cserr", IEEE_T_CSERR },
2300 { "IEEE_tx_sqe", IEEE_T_SQE },
2301 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2302 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2305 { "rx_packets", RMON_R_PACKETS },
2306 { "rx_broadcast", RMON_R_BC_PKT },
2307 { "rx_multicast", RMON_R_MC_PKT },
2308 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2309 { "rx_undersize", RMON_R_UNDERSIZE },
2310 { "rx_oversize", RMON_R_OVERSIZE },
2311 { "rx_fragment", RMON_R_FRAG },
2312 { "rx_jabber", RMON_R_JAB },
2313 { "rx_64byte", RMON_R_P64 },
2314 { "rx_65to127byte", RMON_R_P65TO127 },
2315 { "rx_128to255byte", RMON_R_P128TO255 },
2316 { "rx_256to511byte", RMON_R_P256TO511 },
2317 { "rx_512to1023byte", RMON_R_P512TO1023 },
2318 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2319 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2320 { "rx_octets", RMON_R_OCTETS },
2323 { "IEEE_rx_drop", IEEE_R_DROP },
2324 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2325 { "IEEE_rx_crc", IEEE_R_CRC },
2326 { "IEEE_rx_align", IEEE_R_ALIGN },
2327 { "IEEE_rx_macerr", IEEE_R_MACERR },
2328 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2329 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2332 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2334 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2336 struct fec_enet_private *fep = netdev_priv(dev);
2339 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2340 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2343 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2344 struct ethtool_stats *stats, u64 *data)
2346 struct fec_enet_private *fep = netdev_priv(dev);
2348 if (netif_running(dev))
2349 fec_enet_update_ethtool_stats(dev);
2351 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2354 static void fec_enet_get_strings(struct net_device *netdev,
2355 u32 stringset, u8 *data)
2358 switch (stringset) {
2360 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2361 memcpy(data + i * ETH_GSTRING_LEN,
2362 fec_stats[i].name, ETH_GSTRING_LEN);
2367 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2371 return ARRAY_SIZE(fec_stats);
2377 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2379 struct fec_enet_private *fep = netdev_priv(dev);
2382 /* Disable MIB statistics counters */
2383 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2385 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2386 writel(0, fep->hwp + fec_stats[i].offset);
2388 /* Don't disable MIB statistics counters */
2389 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2392 #else /* !defined(CONFIG_M5272) */
2393 #define FEC_STATS_SIZE 0
2394 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2398 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2401 #endif /* !defined(CONFIG_M5272) */
2403 /* ITR clock source is enet system clock (clk_ahb).
2404 * TCTT unit is cycle_ns * 64 cycle
2405 * So, the ICTT value = X us / (cycle_ns * 64)
2407 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2409 struct fec_enet_private *fep = netdev_priv(ndev);
2411 return us * (fep->itr_clk_rate / 64000) / 1000;
2414 /* Set threshold for interrupt coalescing */
2415 static void fec_enet_itr_coal_set(struct net_device *ndev)
2417 struct fec_enet_private *fep = netdev_priv(ndev);
2420 /* Must be greater than zero to avoid unpredictable behavior */
2421 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2422 !fep->tx_time_itr || !fep->tx_pkts_itr)
2425 /* Select enet system clock as Interrupt Coalescing
2426 * timer Clock Source
2428 rx_itr = FEC_ITR_CLK_SEL;
2429 tx_itr = FEC_ITR_CLK_SEL;
2431 /* set ICFT and ICTT */
2432 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2433 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2434 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2435 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2437 rx_itr |= FEC_ITR_EN;
2438 tx_itr |= FEC_ITR_EN;
2440 writel(tx_itr, fep->hwp + FEC_TXIC0);
2441 writel(rx_itr, fep->hwp + FEC_RXIC0);
2442 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2443 writel(tx_itr, fep->hwp + FEC_TXIC1);
2444 writel(rx_itr, fep->hwp + FEC_RXIC1);
2445 writel(tx_itr, fep->hwp + FEC_TXIC2);
2446 writel(rx_itr, fep->hwp + FEC_RXIC2);
2451 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2453 struct fec_enet_private *fep = netdev_priv(ndev);
2455 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2458 ec->rx_coalesce_usecs = fep->rx_time_itr;
2459 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2461 ec->tx_coalesce_usecs = fep->tx_time_itr;
2462 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2468 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2470 struct fec_enet_private *fep = netdev_priv(ndev);
2473 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2476 if (ec->rx_max_coalesced_frames > 255) {
2477 pr_err("Rx coalesced frames exceed hardware limitation\n");
2481 if (ec->tx_max_coalesced_frames > 255) {
2482 pr_err("Tx coalesced frame exceed hardware limitation\n");
2486 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2487 if (cycle > 0xFFFF) {
2488 pr_err("Rx coalesced usec exceed hardware limitation\n");
2492 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2493 if (cycle > 0xFFFF) {
2494 pr_err("Rx coalesced usec exceed hardware limitation\n");
2498 fep->rx_time_itr = ec->rx_coalesce_usecs;
2499 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2501 fep->tx_time_itr = ec->tx_coalesce_usecs;
2502 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2504 fec_enet_itr_coal_set(ndev);
2509 static void fec_enet_itr_coal_init(struct net_device *ndev)
2511 struct ethtool_coalesce ec;
2513 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2514 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2516 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2517 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2519 fec_enet_set_coalesce(ndev, &ec);
2522 static int fec_enet_get_tunable(struct net_device *netdev,
2523 const struct ethtool_tunable *tuna,
2526 struct fec_enet_private *fep = netdev_priv(netdev);
2530 case ETHTOOL_RX_COPYBREAK:
2531 *(u32 *)data = fep->rx_copybreak;
2541 static int fec_enet_set_tunable(struct net_device *netdev,
2542 const struct ethtool_tunable *tuna,
2545 struct fec_enet_private *fep = netdev_priv(netdev);
2549 case ETHTOOL_RX_COPYBREAK:
2550 fep->rx_copybreak = *(u32 *)data;
2561 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2563 struct fec_enet_private *fep = netdev_priv(ndev);
2565 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2566 wol->supported = WAKE_MAGIC;
2567 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2569 wol->supported = wol->wolopts = 0;
2574 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2576 struct fec_enet_private *fep = netdev_priv(ndev);
2578 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2581 if (wol->wolopts & ~WAKE_MAGIC)
2584 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2585 if (device_may_wakeup(&ndev->dev)) {
2586 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2587 if (fep->irq[0] > 0)
2588 enable_irq_wake(fep->irq[0]);
2590 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2591 if (fep->irq[0] > 0)
2592 disable_irq_wake(fep->irq[0]);
2598 static const struct ethtool_ops fec_enet_ethtool_ops = {
2599 .get_drvinfo = fec_enet_get_drvinfo,
2600 .get_regs_len = fec_enet_get_regs_len,
2601 .get_regs = fec_enet_get_regs,
2602 .nway_reset = phy_ethtool_nway_reset,
2603 .get_link = ethtool_op_get_link,
2604 .get_coalesce = fec_enet_get_coalesce,
2605 .set_coalesce = fec_enet_set_coalesce,
2606 #ifndef CONFIG_M5272
2607 .get_pauseparam = fec_enet_get_pauseparam,
2608 .set_pauseparam = fec_enet_set_pauseparam,
2609 .get_strings = fec_enet_get_strings,
2610 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2611 .get_sset_count = fec_enet_get_sset_count,
2613 .get_ts_info = fec_enet_get_ts_info,
2614 .get_tunable = fec_enet_get_tunable,
2615 .set_tunable = fec_enet_set_tunable,
2616 .get_wol = fec_enet_get_wol,
2617 .set_wol = fec_enet_set_wol,
2618 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2619 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2622 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2624 struct fec_enet_private *fep = netdev_priv(ndev);
2625 struct phy_device *phydev = ndev->phydev;
2627 if (!netif_running(ndev))
2633 if (fep->bufdesc_ex) {
2634 if (cmd == SIOCSHWTSTAMP)
2635 return fec_ptp_set(ndev, rq);
2636 if (cmd == SIOCGHWTSTAMP)
2637 return fec_ptp_get(ndev, rq);
2640 return phy_mii_ioctl(phydev, rq, cmd);
2643 static void fec_enet_free_buffers(struct net_device *ndev)
2645 struct fec_enet_private *fep = netdev_priv(ndev);
2647 struct sk_buff *skb;
2648 struct bufdesc *bdp;
2649 struct fec_enet_priv_tx_q *txq;
2650 struct fec_enet_priv_rx_q *rxq;
2653 for (q = 0; q < fep->num_rx_queues; q++) {
2654 rxq = fep->rx_queue[q];
2656 for (i = 0; i < rxq->bd.ring_size; i++) {
2657 skb = rxq->rx_skbuff[i];
2658 rxq->rx_skbuff[i] = NULL;
2660 dma_unmap_single(&fep->pdev->dev,
2661 fec32_to_cpu(bdp->cbd_bufaddr),
2662 FEC_ENET_RX_FRSIZE - fep->rx_align,
2666 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2670 for (q = 0; q < fep->num_tx_queues; q++) {
2671 txq = fep->tx_queue[q];
2673 for (i = 0; i < txq->bd.ring_size; i++) {
2674 kfree(txq->tx_bounce[i]);
2675 txq->tx_bounce[i] = NULL;
2676 skb = txq->tx_skbuff[i];
2677 txq->tx_skbuff[i] = NULL;
2683 static void fec_enet_free_queue(struct net_device *ndev)
2685 struct fec_enet_private *fep = netdev_priv(ndev);
2687 struct fec_enet_priv_tx_q *txq;
2689 for (i = 0; i < fep->num_tx_queues; i++)
2690 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2691 txq = fep->tx_queue[i];
2692 dma_free_coherent(&fep->pdev->dev,
2693 txq->bd.ring_size * TSO_HEADER_SIZE,
2698 for (i = 0; i < fep->num_rx_queues; i++)
2699 kfree(fep->rx_queue[i]);
2700 for (i = 0; i < fep->num_tx_queues; i++)
2701 kfree(fep->tx_queue[i]);
2704 static int fec_enet_alloc_queue(struct net_device *ndev)
2706 struct fec_enet_private *fep = netdev_priv(ndev);
2709 struct fec_enet_priv_tx_q *txq;
2711 for (i = 0; i < fep->num_tx_queues; i++) {
2712 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2718 fep->tx_queue[i] = txq;
2719 txq->bd.ring_size = TX_RING_SIZE;
2720 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2722 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2723 txq->tx_wake_threshold =
2724 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2726 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2727 txq->bd.ring_size * TSO_HEADER_SIZE,
2730 if (!txq->tso_hdrs) {
2736 for (i = 0; i < fep->num_rx_queues; i++) {
2737 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2739 if (!fep->rx_queue[i]) {
2744 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2745 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2750 fec_enet_free_queue(ndev);
2755 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2757 struct fec_enet_private *fep = netdev_priv(ndev);
2759 struct sk_buff *skb;
2760 struct bufdesc *bdp;
2761 struct fec_enet_priv_rx_q *rxq;
2763 rxq = fep->rx_queue[queue];
2765 for (i = 0; i < rxq->bd.ring_size; i++) {
2766 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2770 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2775 rxq->rx_skbuff[i] = skb;
2776 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2778 if (fep->bufdesc_ex) {
2779 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2780 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2783 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2786 /* Set the last buffer to wrap. */
2787 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2788 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2792 fec_enet_free_buffers(ndev);
2797 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2799 struct fec_enet_private *fep = netdev_priv(ndev);
2801 struct bufdesc *bdp;
2802 struct fec_enet_priv_tx_q *txq;
2804 txq = fep->tx_queue[queue];
2806 for (i = 0; i < txq->bd.ring_size; i++) {
2807 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2808 if (!txq->tx_bounce[i])
2811 bdp->cbd_sc = cpu_to_fec16(0);
2812 bdp->cbd_bufaddr = cpu_to_fec32(0);
2814 if (fep->bufdesc_ex) {
2815 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2816 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2819 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2822 /* Set the last buffer to wrap. */
2823 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2824 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2829 fec_enet_free_buffers(ndev);
2833 static int fec_enet_alloc_buffers(struct net_device *ndev)
2835 struct fec_enet_private *fep = netdev_priv(ndev);
2838 for (i = 0; i < fep->num_rx_queues; i++)
2839 if (fec_enet_alloc_rxq_buffers(ndev, i))
2842 for (i = 0; i < fep->num_tx_queues; i++)
2843 if (fec_enet_alloc_txq_buffers(ndev, i))
2849 fec_enet_open(struct net_device *ndev)
2851 struct fec_enet_private *fep = netdev_priv(ndev);
2855 ret = pm_runtime_get_sync(&fep->pdev->dev);
2859 pinctrl_pm_select_default_state(&fep->pdev->dev);
2860 ret = fec_enet_clk_enable(ndev, true);
2864 /* During the first fec_enet_open call the PHY isn't probed at this
2865 * point. Therefore the phy_reset_after_clk_enable() call within
2866 * fec_enet_clk_enable() fails. As we need this reset in order to be
2867 * sure the PHY is working correctly we check if we need to reset again
2868 * later when the PHY is probed
2870 if (ndev->phydev && ndev->phydev->drv)
2871 reset_again = false;
2875 /* I should reset the ring buffers here, but I don't yet know
2876 * a simple way to do that.
2879 ret = fec_enet_alloc_buffers(ndev);
2881 goto err_enet_alloc;
2883 /* Init MAC prior to mii bus probe */
2886 /* Probe and connect to PHY when open the interface */
2887 ret = fec_enet_mii_probe(ndev);
2889 goto err_enet_mii_probe;
2891 /* Call phy_reset_after_clk_enable() again if it failed during
2892 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2895 phy_reset_after_clk_enable(ndev->phydev);
2897 if (fep->quirks & FEC_QUIRK_ERR006687)
2898 imx6q_cpuidle_fec_irqs_used();
2900 napi_enable(&fep->napi);
2901 phy_start(ndev->phydev);
2902 netif_tx_start_all_queues(ndev);
2904 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2905 FEC_WOL_FLAG_ENABLE);
2910 fec_enet_free_buffers(ndev);
2912 fec_enet_clk_enable(ndev, false);
2914 pm_runtime_mark_last_busy(&fep->pdev->dev);
2915 pm_runtime_put_autosuspend(&fep->pdev->dev);
2916 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2921 fec_enet_close(struct net_device *ndev)
2923 struct fec_enet_private *fep = netdev_priv(ndev);
2925 phy_stop(ndev->phydev);
2927 if (netif_device_present(ndev)) {
2928 napi_disable(&fep->napi);
2929 netif_tx_disable(ndev);
2933 phy_disconnect(ndev->phydev);
2935 if (fep->quirks & FEC_QUIRK_ERR006687)
2936 imx6q_cpuidle_fec_irqs_unused();
2938 fec_enet_update_ethtool_stats(ndev);
2940 fec_enet_clk_enable(ndev, false);
2941 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2942 pm_runtime_mark_last_busy(&fep->pdev->dev);
2943 pm_runtime_put_autosuspend(&fep->pdev->dev);
2945 fec_enet_free_buffers(ndev);
2950 /* Set or clear the multicast filter for this adaptor.
2951 * Skeleton taken from sunlance driver.
2952 * The CPM Ethernet implementation allows Multicast as well as individual
2953 * MAC address filtering. Some of the drivers check to make sure it is
2954 * a group multicast address, and discard those that are not. I guess I
2955 * will do the same for now, but just remove the test if you want
2956 * individual filtering as well (do the upper net layers want or support
2957 * this kind of feature?).
2960 #define FEC_HASH_BITS 6 /* #bits in hash */
2962 static void set_multicast_list(struct net_device *ndev)
2964 struct fec_enet_private *fep = netdev_priv(ndev);
2965 struct netdev_hw_addr *ha;
2966 unsigned int crc, tmp;
2968 unsigned int hash_high = 0, hash_low = 0;
2970 if (ndev->flags & IFF_PROMISC) {
2971 tmp = readl(fep->hwp + FEC_R_CNTRL);
2973 writel(tmp, fep->hwp + FEC_R_CNTRL);
2977 tmp = readl(fep->hwp + FEC_R_CNTRL);
2979 writel(tmp, fep->hwp + FEC_R_CNTRL);
2981 if (ndev->flags & IFF_ALLMULTI) {
2982 /* Catch all multicast addresses, so set the
2985 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2986 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2991 /* Add the addresses in hash register */
2992 netdev_for_each_mc_addr(ha, ndev) {
2993 /* calculate crc32 value of mac address */
2994 crc = ether_crc_le(ndev->addr_len, ha->addr);
2996 /* only upper 6 bits (FEC_HASH_BITS) are used
2997 * which point to specific bit in the hash registers
2999 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3002 hash_high |= 1 << (hash - 32);
3004 hash_low |= 1 << hash;
3007 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3008 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3011 /* Set a MAC change in hardware. */
3013 fec_set_mac_address(struct net_device *ndev, void *p)
3015 struct fec_enet_private *fep = netdev_priv(ndev);
3016 struct sockaddr *addr = p;
3019 if (!is_valid_ether_addr(addr->sa_data))
3020 return -EADDRNOTAVAIL;
3021 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3024 /* Add netif status check here to avoid system hang in below case:
3025 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3026 * After ethx down, fec all clocks are gated off and then register
3027 * access causes system hang.
3029 if (!netif_running(ndev))
3032 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3033 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3034 fep->hwp + FEC_ADDR_LOW);
3035 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3036 fep->hwp + FEC_ADDR_HIGH);
3040 #ifdef CONFIG_NET_POLL_CONTROLLER
3042 * fec_poll_controller - FEC Poll controller function
3043 * @dev: The FEC network adapter
3045 * Polled functionality used by netconsole and others in non interrupt mode
3048 static void fec_poll_controller(struct net_device *dev)
3051 struct fec_enet_private *fep = netdev_priv(dev);
3053 for (i = 0; i < FEC_IRQ_NUM; i++) {
3054 if (fep->irq[i] > 0) {
3055 disable_irq(fep->irq[i]);
3056 fec_enet_interrupt(fep->irq[i], dev);
3057 enable_irq(fep->irq[i]);
3063 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3064 netdev_features_t features)
3066 struct fec_enet_private *fep = netdev_priv(netdev);
3067 netdev_features_t changed = features ^ netdev->features;
3069 netdev->features = features;
3071 /* Receive checksum has been changed */
3072 if (changed & NETIF_F_RXCSUM) {
3073 if (features & NETIF_F_RXCSUM)
3074 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3076 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3080 static int fec_set_features(struct net_device *netdev,
3081 netdev_features_t features)
3083 struct fec_enet_private *fep = netdev_priv(netdev);
3084 netdev_features_t changed = features ^ netdev->features;
3086 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3087 napi_disable(&fep->napi);
3088 netif_tx_lock_bh(netdev);
3090 fec_enet_set_netdev_features(netdev, features);
3091 fec_restart(netdev);
3092 netif_tx_wake_all_queues(netdev);
3093 netif_tx_unlock_bh(netdev);
3094 napi_enable(&fep->napi);
3096 fec_enet_set_netdev_features(netdev, features);
3102 static const struct net_device_ops fec_netdev_ops = {
3103 .ndo_open = fec_enet_open,
3104 .ndo_stop = fec_enet_close,
3105 .ndo_start_xmit = fec_enet_start_xmit,
3106 .ndo_set_rx_mode = set_multicast_list,
3107 .ndo_validate_addr = eth_validate_addr,
3108 .ndo_tx_timeout = fec_timeout,
3109 .ndo_set_mac_address = fec_set_mac_address,
3110 .ndo_do_ioctl = fec_enet_ioctl,
3111 #ifdef CONFIG_NET_POLL_CONTROLLER
3112 .ndo_poll_controller = fec_poll_controller,
3114 .ndo_set_features = fec_set_features,
3117 static const unsigned short offset_des_active_rxq[] = {
3118 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3121 static const unsigned short offset_des_active_txq[] = {
3122 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3126 * XXX: We need to clean up on failure exits here.
3129 static int fec_enet_init(struct net_device *ndev)
3131 struct fec_enet_private *fep = netdev_priv(ndev);
3132 struct bufdesc *cbd_base;
3136 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3137 sizeof(struct bufdesc);
3138 unsigned dsize_log2 = __fls(dsize);
3141 WARN_ON(dsize != (1 << dsize_log2));
3142 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3143 fep->rx_align = 0xf;
3144 fep->tx_align = 0xf;
3146 fep->rx_align = 0x3;
3147 fep->tx_align = 0x3;
3150 /* Check mask of the streaming and coherent API */
3151 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3153 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3157 fec_enet_alloc_queue(ndev);
3159 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3161 /* Allocate memory for buffer descriptors. */
3162 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3168 memset(cbd_base, 0, bd_size);
3170 /* Get the Ethernet address */
3172 /* make sure MAC we just acquired is programmed into the hw */
3173 fec_set_mac_address(ndev, NULL);
3175 /* Set receive and transmit descriptor base. */
3176 for (i = 0; i < fep->num_rx_queues; i++) {
3177 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3178 unsigned size = dsize * rxq->bd.ring_size;
3181 rxq->bd.base = cbd_base;
3182 rxq->bd.cur = cbd_base;
3183 rxq->bd.dma = bd_dma;
3184 rxq->bd.dsize = dsize;
3185 rxq->bd.dsize_log2 = dsize_log2;
3186 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3188 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3189 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3192 for (i = 0; i < fep->num_tx_queues; i++) {
3193 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3194 unsigned size = dsize * txq->bd.ring_size;
3197 txq->bd.base = cbd_base;
3198 txq->bd.cur = cbd_base;
3199 txq->bd.dma = bd_dma;
3200 txq->bd.dsize = dsize;
3201 txq->bd.dsize_log2 = dsize_log2;
3202 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3204 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3205 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3209 /* The FEC Ethernet specific entries in the device structure */
3210 ndev->watchdog_timeo = TX_TIMEOUT;
3211 ndev->netdev_ops = &fec_netdev_ops;
3212 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3214 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3215 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3217 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3218 /* enable hw VLAN support */
3219 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3221 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3222 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3224 /* enable hw accelerator */
3225 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3226 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3227 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3230 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3232 fep->rx_align = 0x3f;
3235 ndev->hw_features = ndev->features;
3239 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3240 fec_enet_clear_ethtool_stats(ndev);
3242 fec_enet_update_ethtool_stats(ndev);
3248 static int fec_reset_phy(struct platform_device *pdev)
3251 bool active_high = false;
3252 int msec = 1, phy_post_delay = 0;
3253 struct device_node *np = pdev->dev.of_node;
3258 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3259 /* A sane reset duration should not be longer than 1s */
3260 if (!err && msec > 1000)
3263 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3264 if (phy_reset == -EPROBE_DEFER)
3266 else if (!gpio_is_valid(phy_reset))
3269 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3270 /* valid reset duration should be less than 1s */
3271 if (!err && phy_post_delay > 1000)
3274 active_high = of_property_read_bool(np, "phy-reset-active-high");
3276 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3277 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3280 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3287 usleep_range(msec * 1000, msec * 1000 + 1000);
3289 gpio_set_value_cansleep(phy_reset, !active_high);
3291 if (!phy_post_delay)
3294 if (phy_post_delay > 20)
3295 msleep(phy_post_delay);
3297 usleep_range(phy_post_delay * 1000,
3298 phy_post_delay * 1000 + 1000);
3302 #else /* CONFIG_OF */
3303 static int fec_reset_phy(struct platform_device *pdev)
3306 * In case of platform probe, the reset has been done
3311 #endif /* CONFIG_OF */
3314 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3316 struct device_node *np = pdev->dev.of_node;
3318 *num_tx = *num_rx = 1;
3320 if (!np || !of_device_is_available(np))
3323 /* parse the num of tx and rx queues */
3324 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3326 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3328 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3329 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3335 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3336 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3344 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3346 int irq_cnt = platform_irq_count(pdev);
3348 if (irq_cnt > FEC_IRQ_NUM)
3349 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3350 else if (irq_cnt == 2)
3351 irq_cnt = 1; /* last for pps */
3352 else if (irq_cnt <= 0)
3353 irq_cnt = 1; /* At least 1 irq is needed */
3358 fec_probe(struct platform_device *pdev)
3360 struct fec_enet_private *fep;
3361 struct fec_platform_data *pdata;
3362 struct net_device *ndev;
3363 int i, irq, ret = 0;
3365 const struct of_device_id *of_id;
3367 struct device_node *np = pdev->dev.of_node, *phy_node;
3373 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3375 /* Init network device */
3376 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3377 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3381 SET_NETDEV_DEV(ndev, &pdev->dev);
3383 /* setup board info structure */
3384 fep = netdev_priv(ndev);
3386 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3388 pdev->id_entry = of_id->data;
3389 fep->quirks = pdev->id_entry->driver_data;
3392 fep->num_rx_queues = num_rx_qs;
3393 fep->num_tx_queues = num_tx_qs;
3395 #if !defined(CONFIG_M5272)
3396 /* default enable pause frame auto negotiation */
3397 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3398 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3401 /* Select default pin state */
3402 pinctrl_pm_select_default_state(&pdev->dev);
3404 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3405 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3406 if (IS_ERR(fep->hwp)) {
3407 ret = PTR_ERR(fep->hwp);
3408 goto failed_ioremap;
3412 fep->dev_id = dev_id++;
3414 platform_set_drvdata(pdev, ndev);
3416 if ((of_machine_is_compatible("fsl,imx6q") ||
3417 of_machine_is_compatible("fsl,imx6dl")) &&
3418 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3419 fep->quirks |= FEC_QUIRK_ERR006687;
3421 if (of_get_property(np, "fsl,magic-packet", NULL))
3422 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3424 phy_node = of_parse_phandle(np, "phy-handle", 0);
3425 if (!phy_node && of_phy_is_fixed_link(np)) {
3426 ret = of_phy_register_fixed_link(np);
3429 "broken fixed-link specification\n");
3432 phy_node = of_node_get(np);
3434 fep->phy_node = phy_node;
3436 ret = of_get_phy_mode(pdev->dev.of_node);
3438 pdata = dev_get_platdata(&pdev->dev);
3440 fep->phy_interface = pdata->phy;
3442 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3444 fep->phy_interface = ret;
3447 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3448 if (IS_ERR(fep->clk_ipg)) {
3449 ret = PTR_ERR(fep->clk_ipg);
3453 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3454 if (IS_ERR(fep->clk_ahb)) {
3455 ret = PTR_ERR(fep->clk_ahb);
3459 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3461 /* enet_out is optional, depends on board */
3462 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3463 if (IS_ERR(fep->clk_enet_out))
3464 fep->clk_enet_out = NULL;
3466 fep->ptp_clk_on = false;
3467 mutex_init(&fep->ptp_clk_mutex);
3469 /* clk_ref is optional, depends on board */
3470 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3471 if (IS_ERR(fep->clk_ref))
3472 fep->clk_ref = NULL;
3474 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3475 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3476 if (IS_ERR(fep->clk_ptp)) {
3477 fep->clk_ptp = NULL;
3478 fep->bufdesc_ex = false;
3481 ret = fec_enet_clk_enable(ndev, true);
3485 ret = clk_prepare_enable(fep->clk_ipg);
3487 goto failed_clk_ipg;
3489 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3490 if (!IS_ERR(fep->reg_phy)) {
3491 ret = regulator_enable(fep->reg_phy);
3494 "Failed to enable phy regulator: %d\n", ret);
3495 clk_disable_unprepare(fep->clk_ipg);
3496 goto failed_regulator;
3499 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3500 ret = -EPROBE_DEFER;
3501 goto failed_regulator;
3503 fep->reg_phy = NULL;
3506 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3507 pm_runtime_use_autosuspend(&pdev->dev);
3508 pm_runtime_get_noresume(&pdev->dev);
3509 pm_runtime_set_active(&pdev->dev);
3510 pm_runtime_enable(&pdev->dev);
3512 ret = fec_reset_phy(pdev);
3516 irq_cnt = fec_enet_get_irq_cnt(pdev);
3517 if (fep->bufdesc_ex)
3518 fec_ptp_init(pdev, irq_cnt);
3520 ret = fec_enet_init(ndev);
3524 for (i = 0; i < irq_cnt; i++) {
3525 snprintf(irq_name, sizeof(irq_name), "int%d", i);
3526 irq = platform_get_irq_byname(pdev, irq_name);
3528 irq = platform_get_irq(pdev, i);
3533 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3534 0, pdev->name, ndev);
3541 init_completion(&fep->mdio_done);
3542 ret = fec_enet_mii_init(pdev);
3544 goto failed_mii_init;
3546 /* Carrier starts down, phylib will bring it up */
3547 netif_carrier_off(ndev);
3548 fec_enet_clk_enable(ndev, false);
3549 pinctrl_pm_select_sleep_state(&pdev->dev);
3551 ret = register_netdev(ndev);
3553 goto failed_register;
3555 device_init_wakeup(&ndev->dev, fep->wol_flag &
3556 FEC_WOL_HAS_MAGIC_PACKET);
3558 if (fep->bufdesc_ex && fep->ptp_clock)
3559 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3561 fep->rx_copybreak = COPYBREAK_DEFAULT;
3562 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3564 pm_runtime_mark_last_busy(&pdev->dev);
3565 pm_runtime_put_autosuspend(&pdev->dev);
3570 fec_enet_mii_remove(fep);
3576 regulator_disable(fep->reg_phy);
3578 pm_runtime_put(&pdev->dev);
3579 pm_runtime_disable(&pdev->dev);
3582 fec_enet_clk_enable(ndev, false);
3584 if (of_phy_is_fixed_link(np))
3585 of_phy_deregister_fixed_link(np);
3586 of_node_put(phy_node);
3596 fec_drv_remove(struct platform_device *pdev)
3598 struct net_device *ndev = platform_get_drvdata(pdev);
3599 struct fec_enet_private *fep = netdev_priv(ndev);
3600 struct device_node *np = pdev->dev.of_node;
3602 cancel_work_sync(&fep->tx_timeout_work);
3604 unregister_netdev(ndev);
3605 fec_enet_mii_remove(fep);
3607 regulator_disable(fep->reg_phy);
3608 pm_runtime_put(&pdev->dev);
3609 pm_runtime_disable(&pdev->dev);
3610 if (of_phy_is_fixed_link(np))
3611 of_phy_deregister_fixed_link(np);
3612 of_node_put(fep->phy_node);
3618 static int __maybe_unused fec_suspend(struct device *dev)
3620 struct net_device *ndev = dev_get_drvdata(dev);
3621 struct fec_enet_private *fep = netdev_priv(ndev);
3624 if (netif_running(ndev)) {
3625 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3626 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3627 phy_stop(ndev->phydev);
3628 napi_disable(&fep->napi);
3629 netif_tx_lock_bh(ndev);
3630 netif_device_detach(ndev);
3631 netif_tx_unlock_bh(ndev);
3633 fec_enet_clk_enable(ndev, false);
3634 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3635 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3639 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3640 regulator_disable(fep->reg_phy);
3642 /* SOC supply clock to phy, when clock is disabled, phy link down
3643 * SOC control phy regulator, when regulator is disabled, phy link down
3645 if (fep->clk_enet_out || fep->reg_phy)
3651 static int __maybe_unused fec_resume(struct device *dev)
3653 struct net_device *ndev = dev_get_drvdata(dev);
3654 struct fec_enet_private *fep = netdev_priv(ndev);
3655 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3659 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3660 ret = regulator_enable(fep->reg_phy);
3666 if (netif_running(ndev)) {
3667 ret = fec_enet_clk_enable(ndev, true);
3672 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3673 if (pdata && pdata->sleep_mode_enable)
3674 pdata->sleep_mode_enable(false);
3675 val = readl(fep->hwp + FEC_ECNTRL);
3676 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3677 writel(val, fep->hwp + FEC_ECNTRL);
3678 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3680 pinctrl_pm_select_default_state(&fep->pdev->dev);
3683 netif_tx_lock_bh(ndev);
3684 netif_device_attach(ndev);
3685 netif_tx_unlock_bh(ndev);
3686 napi_enable(&fep->napi);
3687 phy_start(ndev->phydev);
3695 regulator_disable(fep->reg_phy);
3699 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3701 struct net_device *ndev = dev_get_drvdata(dev);
3702 struct fec_enet_private *fep = netdev_priv(ndev);
3704 clk_disable_unprepare(fep->clk_ipg);
3709 static int __maybe_unused fec_runtime_resume(struct device *dev)
3711 struct net_device *ndev = dev_get_drvdata(dev);
3712 struct fec_enet_private *fep = netdev_priv(ndev);
3714 return clk_prepare_enable(fep->clk_ipg);
3717 static const struct dev_pm_ops fec_pm_ops = {
3718 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3719 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3722 static struct platform_driver fec_driver = {
3724 .name = DRIVER_NAME,
3726 .of_match_table = fec_dt_ids,
3728 .id_table = fec_devtype,
3730 .remove = fec_drv_remove,
3733 module_platform_driver(fec_driver);
3735 MODULE_ALIAS("platform:"DRIVER_NAME);
3736 MODULE_LICENSE("GPL");