drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2016 Broadcom
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 const char * const be_misconfig_evt_port_state[] = {
  23         "Physical Link is functional",
  24         "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
  25         "Optics of two types installed – Remove one optic or install matching pair of optics.",
  26         "Incompatible optics – Replace with compatible optics for card to function.",
  27         "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
  28         "Uncertified optics – Replace with Avago-certified optics to enable link operation."
  29 };
  30
  31 static char *be_port_misconfig_evt_severity[] = {
  32         "KERN_WARN",
  33         "KERN_INFO",
  34         "KERN_ERR",
  35         "KERN_WARN"
  36 };
  37
  38 static char *phy_state_oper_desc[] = {
  39         "Link is non-operational",
  40         "Link is operational",
  41         ""
  42 };
  43
  44 static struct be_cmd_priv_map cmd_priv_map[] = {
  45         {
  46                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  47                 CMD_SUBSYSTEM_ETH,
  48                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  49                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  50         },
  51         {
  52                 OPCODE_COMMON_GET_FLOW_CONTROL,
  53                 CMD_SUBSYSTEM_COMMON,
  54                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  55                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  56         },
  57         {
  58                 OPCODE_COMMON_SET_FLOW_CONTROL,
  59                 CMD_SUBSYSTEM_COMMON,
  60                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  61                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  62         },
  63         {
  64                 OPCODE_ETH_GET_PPORT_STATS,
  65                 CMD_SUBSYSTEM_ETH,
  66                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  67                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  68         },
  69         {
  70                 OPCODE_COMMON_GET_PHY_DETAILS,
  71                 CMD_SUBSYSTEM_COMMON,
  72                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  73                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  74         },
  75         {
  76                 OPCODE_LOWLEVEL_HOST_DDR_DMA,
  77                 CMD_SUBSYSTEM_LOWLEVEL,
  78                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  79         },
  80         {
  81                 OPCODE_LOWLEVEL_LOOPBACK_TEST,
  82                 CMD_SUBSYSTEM_LOWLEVEL,
  83                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  84         },
  85         {
  86                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
  87                 CMD_SUBSYSTEM_LOWLEVEL,
  88                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  89         },
  90         {
  91                 OPCODE_COMMON_SET_HSW_CONFIG,
  92                 CMD_SUBSYSTEM_COMMON,
  93                 BE_PRIV_DEVCFG | BE_PRIV_VHADM |
  94                 BE_PRIV_DEVSEC
  95         },
  96         {
  97                 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
  98                 CMD_SUBSYSTEM_COMMON,
  99                 BE_PRIV_DEVCFG
 100         }
 101 };
 102
 103 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
 104 {
 105         int i;
 106         int num_entries = ARRAY_SIZE(cmd_priv_map);
 107         u32 cmd_privileges = adapter->cmd_privileges;
 108
 109         for (i = 0; i < num_entries; i++)
 110                 if (opcode == cmd_priv_map[i].opcode &&
 111                     subsystem == cmd_priv_map[i].subsystem)
 112                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
 113                                 return false;
 114
 115         return true;
 116 }
 117
 118 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 119 {
 120         return wrb->payload.embedded_payload;
 121 }
 122
 123 static int be_mcc_notify(struct be_adapter *adapter)
 124 {
 125         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 126         u32 val = 0;
 127
 128         if (be_check_error(adapter, BE_ERROR_ANY))
 129                 return -EIO;
 130
 131         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 132         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 133
 134         wmb();
 135         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 136
 137         return 0;
 138 }
 139
 140 /* To check if valid bit is set, check the entire word as we don't know
 141  * the endianness of the data (old entry is host endian while a new entry is
 142  * little endian) */
 143 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 144 {
 145         u32 flags;
 146
 147         if (compl->flags != 0) {
 148                 flags = le32_to_cpu(compl->flags);
 149                 if (flags & CQE_FLAGS_VALID_MASK) {
 150                         compl->flags = flags;
 151                         return true;
 152                 }
 153         }
 154         return false;
 155 }
 156
 157 /* Need to reset the entire word that houses the valid bit */
 158 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 159 {
 160         compl->flags = 0;
 161 }
 162
 163 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 164 {
 165         unsigned long addr;
 166
 167         addr = tag1;
 168         addr = ((addr << 16) << 16) | tag0;
 169         return (void *)addr;
 170 }
 171
 172 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 173 {
 174         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 175             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 176             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 177             addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
 178             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 179             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 180              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 181                 return true;
 182         else
 183                 return false;
 184 }
 185
 186 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 187  * loop (has not issued be_mcc_notify_wait())
 188  */
 189 static void be_async_cmd_process(struct be_adapter *adapter,
 190                                  struct be_mcc_compl *compl,
 191                                  struct be_cmd_resp_hdr *resp_hdr)
 192 {
 193         enum mcc_base_status base_status = base_status(compl->status);
 194         u8 opcode = 0, subsystem = 0;
 195
 196         if (resp_hdr) {
 197                 opcode = resp_hdr->opcode;
 198                 subsystem = resp_hdr->subsystem;
 199         }
 200
 201         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 202             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 203                 complete(&adapter->et_cmd_compl);
 204                 return;
 205         }
 206
 207         if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
 208             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 209                 complete(&adapter->et_cmd_compl);
 210                 return;
 211         }
 212
 213         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 214              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 215             subsystem == CMD_SUBSYSTEM_COMMON) {
 216                 adapter->flash_status = compl->status;
 217                 complete(&adapter->et_cmd_compl);
 218                 return;
 219         }
 220
 221         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 222              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 223             subsystem == CMD_SUBSYSTEM_ETH &&
 224             base_status == MCC_STATUS_SUCCESS) {
 225                 be_parse_stats(adapter);
 226                 adapter->stats_cmd_sent = false;
 227                 return;
 228         }
 229
 230         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 231             subsystem == CMD_SUBSYSTEM_COMMON) {
 232                 if (base_status == MCC_STATUS_SUCCESS) {
 233                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 234                                                         (void *)resp_hdr;
 235                         adapter->hwmon_info.be_on_die_temp =
 236                                                 resp->on_die_temperature;
 237                 } else {
 238                         adapter->be_get_temp_freq = 0;
 239                         adapter->hwmon_info.be_on_die_temp =
 240                                                 BE_INVALID_DIE_TEMP;
 241                 }
 242                 return;
 243         }
 244 }
 245
 246 static int be_mcc_compl_process(struct be_adapter *adapter,
 247                                 struct be_mcc_compl *compl)
 248 {
 249         enum mcc_base_status base_status;
 250         enum mcc_addl_status addl_status;
 251         struct be_cmd_resp_hdr *resp_hdr;
 252         u8 opcode = 0, subsystem = 0;
 253
 254         /* Just swap the status to host endian; mcc tag is opaquely copied
 255          * from mcc_wrb */
 256         be_dws_le_to_cpu(compl, 4);
 257
 258         base_status = base_status(compl->status);
 259         addl_status = addl_status(compl->status);
 260
 261         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 262         if (resp_hdr) {
 263                 opcode = resp_hdr->opcode;
 264                 subsystem = resp_hdr->subsystem;
 265         }
 266
 267         be_async_cmd_process(adapter, compl, resp_hdr);
 268
 269         if (base_status != MCC_STATUS_SUCCESS &&
 270             !be_skip_err_log(opcode, base_status, addl_status)) {
 271                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
 272                     addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
 273                         dev_warn(&adapter->pdev->dev,
 274                                  "VF is not privileged to issue opcode %d-%d\n",
 275                                  opcode, subsystem);
 276                 } else {
 277                         dev_err(&adapter->pdev->dev,
 278                                 "opcode %d-%d failed:status %d-%d\n",
 279                                 opcode, subsystem, base_status, addl_status);
 280                 }
 281         }
 282         return compl->status;
 283 }
 284
 285 /* Link state evt is a string of bytes; no need for endian swapping */
 286 static void be_async_link_state_process(struct be_adapter *adapter,
 287                                         struct be_mcc_compl *compl)
 288 {
 289         struct be_async_event_link_state *evt =
 290                         (struct be_async_event_link_state *)compl;
 291
 292         /* When link status changes, link speed must be re-queried from FW */
 293         adapter->phy.link_speed = -1;
 294
 295         /* On BEx the FW does not send a separate link status
 296          * notification for physical and logical link.
 297          * On other chips just process the logical link
 298          * status notification
 299          */
 300         if (!BEx_chip(adapter) &&
 301             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 302                 return;
 303
 304         /* For the initial link status do not rely on the ASYNC event as
 305          * it may not be received in some cases.
 306          */
 307         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 308                 be_link_status_update(adapter,
 309                                       evt->port_link_status & LINK_STATUS_MASK);
 310 }
 311
 312 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 313                                                   struct be_mcc_compl *compl)
 314 {
 315         struct be_async_event_misconfig_port *evt =
 316                         (struct be_async_event_misconfig_port *)compl;
 317         u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
 318         u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
 319         u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
 320         struct device *dev = &adapter->pdev->dev;
 321         u8 msg_severity = DEFAULT_MSG_SEVERITY;
 322         u8 phy_state_info;
 323         u8 new_phy_state;
 324
 325         new_phy_state =
 326                 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
 327
 328         if (new_phy_state == adapter->phy_state)
 329                 return;
 330
 331         adapter->phy_state = new_phy_state;
 332
 333         /* for older fw that doesn't populate link effect data */
 334         if (!sfp_misconfig_evt_word2)
 335                 goto log_message;
 336
 337         phy_state_info =
 338                 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
 339
 340         if (phy_state_info & PHY_STATE_INFO_VALID) {
 341                 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
 342
 343                 if (be_phy_unqualified(new_phy_state))
 344                         phy_oper_state = (phy_state_info & PHY_STATE_OPER);
 345         }
 346
 347 log_message:
 348         /* Log an error message that would allow a user to determine
 349          * whether the SFPs have an issue
 350          */
 351         if (be_phy_state_unknown(new_phy_state))
 352                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 353                            "Port %c: Unrecognized Optics state: 0x%x. %s",
 354                            adapter->port_name,
 355                            new_phy_state,
 356                            phy_state_oper_desc[phy_oper_state]);
 357         else
 358                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 359                            "Port %c: %s %s",
 360                            adapter->port_name,
 361                            be_misconfig_evt_port_state[new_phy_state],
 362                            phy_state_oper_desc[phy_oper_state]);
 363
 364         /* Log Vendor name and part no. if a misconfigured SFP is detected */
 365         if (be_phy_misconfigured(new_phy_state))
 366                 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
 367 }
 368
 369 /* Grp5 CoS Priority evt */
 370 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 371                                                struct be_mcc_compl *compl)
 372 {
 373         struct be_async_event_grp5_cos_priority *evt =
 374                         (struct be_async_event_grp5_cos_priority *)compl;
 375
 376         if (evt->valid) {
 377                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 378                 adapter->recommended_prio_bits =
 379                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 380         }
 381 }
 382
 383 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 384 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 385                                             struct be_mcc_compl *compl)
 386 {
 387         struct be_async_event_grp5_qos_link_speed *evt =
 388                         (struct be_async_event_grp5_qos_link_speed *)compl;
 389
 390         if (adapter->phy.link_speed >= 0 &&
 391             evt->physical_port == adapter->port_num)
 392                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 393 }
 394
 395 /*Grp5 PVID evt*/
 396 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 397                                              struct be_mcc_compl *compl)
 398 {
 399         struct be_async_event_grp5_pvid_state *evt =
 400                         (struct be_async_event_grp5_pvid_state *)compl;
 401
 402         if (evt->enabled) {
 403                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 404                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 405         } else {
 406                 adapter->pvid = 0;
 407         }
 408 }
 409
 410 #define MGMT_ENABLE_MASK        0x4
 411 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
 412                                              struct be_mcc_compl *compl)
 413 {
 414         struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
 415         u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
 416
 417         if (evt_dw1 & MGMT_ENABLE_MASK) {
 418                 adapter->flags |= BE_FLAGS_OS2BMC;
 419                 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
 420         } else {
 421                 adapter->flags &= ~BE_FLAGS_OS2BMC;
 422         }
 423 }
 424
 425 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 426                                       struct be_mcc_compl *compl)
 427 {
 428         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 429                                 ASYNC_EVENT_TYPE_MASK;
 430
 431         switch (event_type) {
 432         case ASYNC_EVENT_COS_PRIORITY:
 433                 be_async_grp5_cos_priority_process(adapter, compl);
 434                 break;
 435         case ASYNC_EVENT_QOS_SPEED:
 436                 be_async_grp5_qos_speed_process(adapter, compl);
 437                 break;
 438         case ASYNC_EVENT_PVID_STATE:
 439                 be_async_grp5_pvid_state_process(adapter, compl);
 440                 break;
 441         /* Async event to disable/enable os2bmc and/or mac-learning */
 442         case ASYNC_EVENT_FW_CONTROL:
 443                 be_async_grp5_fw_control_process(adapter, compl);
 444                 break;
 445         default:
 446                 break;
 447         }
 448 }
 449
 450 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 451                                      struct be_mcc_compl *cmp)
 452 {
 453         u8 event_type = 0;
 454         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 455
 456         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 457                         ASYNC_EVENT_TYPE_MASK;
 458
 459         switch (event_type) {
 460         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 461                 if (evt->valid)
 462                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 463                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 464         break;
 465         default:
 466                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 467                          event_type);
 468         break;
 469         }
 470 }
 471
 472 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 473                                          struct be_mcc_compl *cmp)
 474 {
 475         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 476                         ASYNC_EVENT_TYPE_MASK;
 477
 478         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 479                 be_async_port_misconfig_event_process(adapter, cmp);
 480 }
 481
 482 static inline bool is_link_state_evt(u32 flags)
 483 {
 484         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 485                         ASYNC_EVENT_CODE_LINK_STATE;
 486 }
 487
 488 static inline bool is_grp5_evt(u32 flags)
 489 {
 490         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 491                         ASYNC_EVENT_CODE_GRP_5;
 492 }
 493
 494 static inline bool is_dbg_evt(u32 flags)
 495 {
 496         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 497                         ASYNC_EVENT_CODE_QNQ;
 498 }
 499
 500 static inline bool is_sliport_evt(u32 flags)
 501 {
 502         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 503                 ASYNC_EVENT_CODE_SLIPORT;
 504 }
 505
 506 static void be_mcc_event_process(struct be_adapter *adapter,
 507                                  struct be_mcc_compl *compl)
 508 {
 509         if (is_link_state_evt(compl->flags))
 510                 be_async_link_state_process(adapter, compl);
 511         else if (is_grp5_evt(compl->flags))
 512                 be_async_grp5_evt_process(adapter, compl);
 513         else if (is_dbg_evt(compl->flags))
 514                 be_async_dbg_evt_process(adapter, compl);
 515         else if (is_sliport_evt(compl->flags))
 516                 be_async_sliport_evt_process(adapter, compl);
 517 }
 518
 519 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 520 {
 521         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 522         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 523
 524         if (be_mcc_compl_is_new(compl)) {
 525                 queue_tail_inc(mcc_cq);
 526                 return compl;
 527         }
 528         return NULL;
 529 }
 530
 531 void be_async_mcc_enable(struct be_adapter *adapter)
 532 {
 533         spin_lock_bh(&adapter->mcc_cq_lock);
 534
 535         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 536         adapter->mcc_obj.rearm_cq = true;
 537
 538         spin_unlock_bh(&adapter->mcc_cq_lock);
 539 }
 540
 541 void be_async_mcc_disable(struct be_adapter *adapter)
 542 {
 543         spin_lock_bh(&adapter->mcc_cq_lock);
 544
 545         adapter->mcc_obj.rearm_cq = false;
 546         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 547
 548         spin_unlock_bh(&adapter->mcc_cq_lock);
 549 }
 550
 551 int be_process_mcc(struct be_adapter *adapter)
 552 {
 553         struct be_mcc_compl *compl;
 554         int num = 0, status = 0;
 555         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 556
 557         spin_lock(&adapter->mcc_cq_lock);
 558
 559         while ((compl = be_mcc_compl_get(adapter))) {
 560                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 561                         be_mcc_event_process(adapter, compl);
 562                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 563                         status = be_mcc_compl_process(adapter, compl);
 564                         atomic_dec(&mcc_obj->q.used);
 565                 }
 566                 be_mcc_compl_use(compl);
 567                 num++;
 568         }
 569
 570         if (num)
 571                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 572
 573         spin_unlock(&adapter->mcc_cq_lock);
 574         return status;
 575 }
 576
 577 /* Wait till no more pending mcc requests are present */
 578 static int be_mcc_wait_compl(struct be_adapter *adapter)
 579 {
 580 #define mcc_timeout             12000 /* 12s timeout */
 581         int i, status = 0;
 582         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 583
 584         for (i = 0; i < mcc_timeout; i++) {
 585                 if (be_check_error(adapter, BE_ERROR_ANY))
 586                         return -EIO;
 587
 588                 local_bh_disable();
 589                 status = be_process_mcc(adapter);
 590                 local_bh_enable();
 591
 592                 if (atomic_read(&mcc_obj->q.used) == 0)
 593                         break;
 594                 usleep_range(500, 1000);
 595         }
 596         if (i == mcc_timeout) {
 597                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 598                 be_set_error(adapter, BE_ERROR_FW);
 599                 return -EIO;
 600         }
 601         return status;
 602 }
 603
 604 /* Notify MCC requests and wait for completion */
 605 static int be_mcc_notify_wait(struct be_adapter *adapter)
 606 {
 607         int status;
 608         struct be_mcc_wrb *wrb;
 609         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 610         u32 index = mcc_obj->q.head;
 611         struct be_cmd_resp_hdr *resp;
 612
 613         index_dec(&index, mcc_obj->q.len);
 614         wrb = queue_index_node(&mcc_obj->q, index);
 615
 616         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 617
 618         status = be_mcc_notify(adapter);
 619         if (status)
 620                 goto out;
 621
 622         status = be_mcc_wait_compl(adapter);
 623         if (status == -EIO)
 624                 goto out;
 625
 626         status = (resp->base_status |
 627                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 628                    CQE_ADDL_STATUS_SHIFT));
 629 out:
 630         return status;
 631 }
 632
 633 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 634 {
 635         int msecs = 0;
 636         u32 ready;
 637
 638         do {
 639                 if (be_check_error(adapter, BE_ERROR_ANY))
 640                         return -EIO;
 641
 642                 ready = ioread32(db);
 643                 if (ready == 0xffffffff)
 644                         return -1;
 645
 646                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 647                 if (ready)
 648                         break;
 649
 650                 if (msecs > 4000) {
 651                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 652                         be_set_error(adapter, BE_ERROR_FW);
 653                         be_detect_error(adapter);
 654                         return -1;
 655                 }
 656
 657                 msleep(1);
 658                 msecs++;
 659         } while (true);
 660
 661         return 0;
 662 }
 663
 664 /*
 665  * Insert the mailbox address into the doorbell in two steps
 666  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 667  */
 668 static int be_mbox_notify_wait(struct be_adapter *adapter)
 669 {
 670         int status;
 671         u32 val = 0;
 672         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 673         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 674         struct be_mcc_mailbox *mbox = mbox_mem->va;
 675         struct be_mcc_compl *compl = &mbox->compl;
 676
 677         /* wait for ready to be set */
 678         status = be_mbox_db_ready_wait(adapter, db);
 679         if (status != 0)
 680                 return status;
 681
 682         val |= MPU_MAILBOX_DB_HI_MASK;
 683         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 684         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 685         iowrite32(val, db);
 686
 687         /* wait for ready to be set */
 688         status = be_mbox_db_ready_wait(adapter, db);
 689         if (status != 0)
 690                 return status;
 691
 692         val = 0;
 693         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 694         val |= (u32)(mbox_mem->dma >> 4) << 2;
 695         iowrite32(val, db);
 696
 697         status = be_mbox_db_ready_wait(adapter, db);
 698         if (status != 0)
 699                 return status;
 700
 701         /* A cq entry has been made now */
 702         if (be_mcc_compl_is_new(compl)) {
 703                 status = be_mcc_compl_process(adapter, &mbox->compl);
 704                 be_mcc_compl_use(compl);
 705                 if (status)
 706                         return status;
 707         } else {
 708                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 709                 return -1;
 710         }
 711         return 0;
 712 }
 713
 714 u16 be_POST_stage_get(struct be_adapter *adapter)
 715 {
 716         u32 sem;
 717
 718         if (BEx_chip(adapter))
 719                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 720         else
 721                 pci_read_config_dword(adapter->pdev,
 722                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 723
 724         return sem & POST_STAGE_MASK;
 725 }
 726
 727 static int lancer_wait_ready(struct be_adapter *adapter)
 728 {
 729 #define SLIPORT_READY_TIMEOUT 30
 730         u32 sliport_status;
 731         int i;
 732
 733         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 734                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 735                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 736                         return 0;
 737
 738                 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
 739                     !(sliport_status & SLIPORT_STATUS_RN_MASK))
 740                         return -EIO;
 741
 742                 msleep(1000);
 743         }
 744
 745         return sliport_status ? : -1;
 746 }
 747
 748 int be_fw_wait_ready(struct be_adapter *adapter)
 749 {
 750         u16 stage;
 751         int status, timeout = 0;
 752         struct device *dev = &adapter->pdev->dev;
 753
 754         if (lancer_chip(adapter)) {
 755                 status = lancer_wait_ready(adapter);
 756                 if (status) {
 757                         stage = status;
 758                         goto err;
 759                 }
 760                 return 0;
 761         }
 762
 763         do {
 764                 /* There's no means to poll POST state on BE2/3 VFs */
 765                 if (BEx_chip(adapter) && be_virtfn(adapter))
 766                         return 0;
 767
 768                 stage = be_POST_stage_get(adapter);
 769                 if (stage == POST_STAGE_ARMFW_RDY)
 770                         return 0;
 771
 772                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 773                 if (msleep_interruptible(2000)) {
 774                         dev_err(dev, "Waiting for POST aborted\n");
 775                         return -EINTR;
 776                 }
 777                 timeout += 2;
 778         } while (timeout < 60);
 779
 780 err:
 781         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 782         return -ETIMEDOUT;
 783 }
 784
 785 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 786 {
 787         return &wrb->payload.sgl[0];
 788 }
 789
 790 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 791 {
 792         wrb->tag0 = addr & 0xFFFFFFFF;
 793         wrb->tag1 = upper_32_bits(addr);
 794 }
 795
 796 /* Don't touch the hdr after it's prepared */
 797 /* mem will be NULL for embedded commands */
 798 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 799                                    u8 subsystem, u8 opcode, int cmd_len,
 800                                    struct be_mcc_wrb *wrb,
 801                                    struct be_dma_mem *mem)
 802 {
 803         struct be_sge *sge;
 804
 805         req_hdr->opcode = opcode;
 806         req_hdr->subsystem = subsystem;
 807         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 808         req_hdr->version = 0;
 809         fill_wrb_tags(wrb, (ulong) req_hdr);
 810         wrb->payload_length = cmd_len;
 811         if (mem) {
 812                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 813                         MCC_WRB_SGE_CNT_SHIFT;
 814                 sge = nonembedded_sgl(wrb);
 815                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 816                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 817                 sge->len = cpu_to_le32(mem->size);
 818         } else
 819                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 820         be_dws_cpu_to_le(wrb, 8);
 821 }
 822
 823 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 824                                       struct be_dma_mem *mem)
 825 {
 826         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 827         u64 dma = (u64)mem->dma;
 828
 829         for (i = 0; i < buf_pages; i++) {
 830                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 831                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 832                 dma += PAGE_SIZE_4K;
 833         }
 834 }
 835
 836 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 837 {
 838         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 839         struct be_mcc_wrb *wrb
 840                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 841         memset(wrb, 0, sizeof(*wrb));
 842         return wrb;
 843 }
 844
 845 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 846 {
 847         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 848         struct be_mcc_wrb *wrb;
 849
 850         if (!mccq->created)
 851                 return NULL;
 852
 853         if (atomic_read(&mccq->used) >= mccq->len)
 854                 return NULL;
 855
 856         wrb = queue_head_node(mccq);
 857         queue_head_inc(mccq);
 858         atomic_inc(&mccq->used);
 859         memset(wrb, 0, sizeof(*wrb));
 860         return wrb;
 861 }
 862
 863 static bool use_mcc(struct be_adapter *adapter)
 864 {
 865         return adapter->mcc_obj.q.created;
 866 }
 867
 868 /* Must be used only in process context */
 869 static int be_cmd_lock(struct be_adapter *adapter)
 870 {
 871         if (use_mcc(adapter)) {
 872                 mutex_lock(&adapter->mcc_lock);
 873                 return 0;
 874         } else {
 875                 return mutex_lock_interruptible(&adapter->mbox_lock);
 876         }
 877 }
 878
 879 /* Must be used only in process context */
 880 static void be_cmd_unlock(struct be_adapter *adapter)
 881 {
 882         if (use_mcc(adapter))
 883                 return mutex_unlock(&adapter->mcc_lock);
 884         else
 885                 return mutex_unlock(&adapter->mbox_lock);
 886 }
 887
 888 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 889                                       struct be_mcc_wrb *wrb)
 890 {
 891         struct be_mcc_wrb *dest_wrb;
 892
 893         if (use_mcc(adapter)) {
 894                 dest_wrb = wrb_from_mccq(adapter);
 895                 if (!dest_wrb)
 896                         return NULL;
 897         } else {
 898                 dest_wrb = wrb_from_mbox(adapter);
 899         }
 900
 901         memcpy(dest_wrb, wrb, sizeof(*wrb));
 902         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 903                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 904
 905         return dest_wrb;
 906 }
 907
 908 /* Must be used only in process context */
 909 static int be_cmd_notify_wait(struct be_adapter *adapter,
 910                               struct be_mcc_wrb *wrb)
 911 {
 912         struct be_mcc_wrb *dest_wrb;
 913         int status;
 914
 915         status = be_cmd_lock(adapter);
 916         if (status)
 917                 return status;
 918
 919         dest_wrb = be_cmd_copy(adapter, wrb);
 920         if (!dest_wrb) {
 921                 status = -EBUSY;
 922                 goto unlock;
 923         }
 924
 925         if (use_mcc(adapter))
 926                 status = be_mcc_notify_wait(adapter);
 927         else
 928                 status = be_mbox_notify_wait(adapter);
 929
 930         if (!status)
 931                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 932
 933 unlock:
 934         be_cmd_unlock(adapter);
 935         return status;
 936 }
 937
 938 /* Tell fw we're about to start firing cmds by writing a
 939  * special pattern across the wrb hdr; uses mbox
 940  */
 941 int be_cmd_fw_init(struct be_adapter *adapter)
 942 {
 943         u8 *wrb;
 944         int status;
 945
 946         if (lancer_chip(adapter))
 947                 return 0;
 948
 949         if (mutex_lock_interruptible(&adapter->mbox_lock))
 950                 return -1;
 951
 952         wrb = (u8 *)wrb_from_mbox(adapter);
 953         *wrb++ = 0xFF;
 954         *wrb++ = 0x12;
 955         *wrb++ = 0x34;
 956         *wrb++ = 0xFF;
 957         *wrb++ = 0xFF;
 958         *wrb++ = 0x56;
 959         *wrb++ = 0x78;
 960         *wrb = 0xFF;
 961
 962         status = be_mbox_notify_wait(adapter);
 963
 964         mutex_unlock(&adapter->mbox_lock);
 965         return status;
 966 }
 967
 968 /* Tell fw we're done with firing cmds by writing a
 969  * special pattern across the wrb hdr; uses mbox
 970  */
 971 int be_cmd_fw_clean(struct be_adapter *adapter)
 972 {
 973         u8 *wrb;
 974         int status;
 975
 976         if (lancer_chip(adapter))
 977                 return 0;
 978
 979         if (mutex_lock_interruptible(&adapter->mbox_lock))
 980                 return -1;
 981
 982         wrb = (u8 *)wrb_from_mbox(adapter);
 983         *wrb++ = 0xFF;
 984         *wrb++ = 0xAA;
 985         *wrb++ = 0xBB;
 986         *wrb++ = 0xFF;
 987         *wrb++ = 0xFF;
 988         *wrb++ = 0xCC;
 989         *wrb++ = 0xDD;
 990         *wrb = 0xFF;
 991
 992         status = be_mbox_notify_wait(adapter);
 993
 994         mutex_unlock(&adapter->mbox_lock);
 995         return status;
 996 }
 997
 998 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 999 {
1000         struct be_mcc_wrb *wrb;
1001         struct be_cmd_req_eq_create *req;
1002         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
1003         int status, ver = 0;
1004
1005         if (mutex_lock_interruptible(&adapter->mbox_lock))
1006                 return -1;
1007
1008         wrb = wrb_from_mbox(adapter);
1009         req = embedded_payload(wrb);
1010
1011         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1012                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1013                                NULL);
1014
1015         /* Support for EQ_CREATEv2 available only SH-R onwards */
1016         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1017                 ver = 2;
1018
1019         req->hdr.version = ver;
1020         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1021
1022         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1023         /* 4byte eqe*/
1024         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1025         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
1026                       __ilog2_u32(eqo->q.len / 256));
1027         be_dws_cpu_to_le(req->context, sizeof(req->context));
1028
1029         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1030
1031         status = be_mbox_notify_wait(adapter);
1032         if (!status) {
1033                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
1034
1035                 eqo->q.id = le16_to_cpu(resp->eq_id);
1036                 eqo->msix_idx =
1037                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1038                 eqo->q.created = true;
1039         }
1040
1041         mutex_unlock(&adapter->mbox_lock);
1042         return status;
1043 }
1044
1045 /* Use MCC */
1046 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1047                           bool permanent, u32 if_handle, u32 pmac_id)
1048 {
1049         struct be_mcc_wrb *wrb;
1050         struct be_cmd_req_mac_query *req;
1051         int status;
1052
1053         mutex_lock(&adapter->mcc_lock);
1054
1055         wrb = wrb_from_mccq(adapter);
1056         if (!wrb) {
1057                 status = -EBUSY;
1058                 goto err;
1059         }
1060         req = embedded_payload(wrb);
1061
1062         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1063                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1064                                NULL);
1065         req->type = MAC_ADDRESS_TYPE_NETWORK;
1066         if (permanent) {
1067                 req->permanent = 1;
1068         } else {
1069                 req->if_id = cpu_to_le16((u16)if_handle);
1070                 req->pmac_id = cpu_to_le32(pmac_id);
1071                 req->permanent = 0;
1072         }
1073
1074         status = be_mcc_notify_wait(adapter);
1075         if (!status) {
1076                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1077
1078                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1079         }
1080
1081 err:
1082         mutex_unlock(&adapter->mcc_lock);
1083         return status;
1084 }
1085
1086 /* Uses synchronous MCCQ */
1087 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1088                     u32 if_id, u32 *pmac_id, u32 domain)
1089 {
1090         struct be_mcc_wrb *wrb;
1091         struct be_cmd_req_pmac_add *req;
1092         int status;
1093
1094         mutex_lock(&adapter->mcc_lock);
1095
1096         wrb = wrb_from_mccq(adapter);
1097         if (!wrb) {
1098                 status = -EBUSY;
1099                 goto err;
1100         }
1101         req = embedded_payload(wrb);
1102
1103         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1104                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1105                                NULL);
1106
1107         req->hdr.domain = domain;
1108         req->if_id = cpu_to_le32(if_id);
1109         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1110
1111         status = be_mcc_notify_wait(adapter);
1112         if (!status) {
1113                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1114
1115                 *pmac_id = le32_to_cpu(resp->pmac_id);
1116         }
1117
1118 err:
1119         mutex_unlock(&adapter->mcc_lock);
1120
1121          if (base_status(status) == MCC_STATUS_UNAUTHORIZED_REQUEST)
1122                 status = -EPERM;
1123
1124         return status;
1125 }
1126
1127 /* Uses synchronous MCCQ */
1128 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1129 {
1130         struct be_mcc_wrb *wrb;
1131         struct be_cmd_req_pmac_del *req;
1132         int status;
1133
1134         if (pmac_id == -1)
1135                 return 0;
1136
1137         mutex_lock(&adapter->mcc_lock);
1138
1139         wrb = wrb_from_mccq(adapter);
1140         if (!wrb) {
1141                 status = -EBUSY;
1142                 goto err;
1143         }
1144         req = embedded_payload(wrb);
1145
1146         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1147                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1148                                wrb, NULL);
1149
1150         req->hdr.domain = dom;
1151         req->if_id = cpu_to_le32(if_id);
1152         req->pmac_id = cpu_to_le32(pmac_id);
1153
1154         status = be_mcc_notify_wait(adapter);
1155
1156 err:
1157         mutex_unlock(&adapter->mcc_lock);
1158         return status;
1159 }
1160
1161 /* Uses Mbox */
1162 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1163                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1164 {
1165         struct be_mcc_wrb *wrb;
1166         struct be_cmd_req_cq_create *req;
1167         struct be_dma_mem *q_mem = &cq->dma_mem;
1168         void *ctxt;
1169         int status;
1170
1171         if (mutex_lock_interruptible(&adapter->mbox_lock))
1172                 return -1;
1173
1174         wrb = wrb_from_mbox(adapter);
1175         req = embedded_payload(wrb);
1176         ctxt = &req->context;
1177
1178         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1179                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1180                                NULL);
1181
1182         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1183
1184         if (BEx_chip(adapter)) {
1185                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1186                               coalesce_wm);
1187                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1188                               ctxt, no_delay);
1189                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1190                               __ilog2_u32(cq->len / 256));
1191                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1192                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1193                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1194         } else {
1195                 req->hdr.version = 2;
1196                 req->page_size = 1; /* 1 for 4K */
1197
1198                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1199                  * Lancer uses COMMON_MODIFY_CQ to set this field
1200                  */
1201                 if (!lancer_chip(adapter))
1202                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1203                                       ctxt, coalesce_wm);
1204                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1205                               no_delay);
1206                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1207                               __ilog2_u32(cq->len / 256));
1208                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1209                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1210                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1211         }
1212
1213         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1214
1215         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1216
1217         status = be_mbox_notify_wait(adapter);
1218         if (!status) {
1219                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1220
1221                 cq->id = le16_to_cpu(resp->cq_id);
1222                 cq->created = true;
1223         }
1224
1225         mutex_unlock(&adapter->mbox_lock);
1226
1227         return status;
1228 }
1229
1230 static u32 be_encoded_q_len(int q_len)
1231 {
1232         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1233
1234         if (len_encoded == 16)
1235                 len_encoded = 0;
1236         return len_encoded;
1237 }
1238
1239 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1240                                   struct be_queue_info *mccq,
1241                                   struct be_queue_info *cq)
1242 {
1243         struct be_mcc_wrb *wrb;
1244         struct be_cmd_req_mcc_ext_create *req;
1245         struct be_dma_mem *q_mem = &mccq->dma_mem;
1246         void *ctxt;
1247         int status;
1248
1249         if (mutex_lock_interruptible(&adapter->mbox_lock))
1250                 return -1;
1251
1252         wrb = wrb_from_mbox(adapter);
1253         req = embedded_payload(wrb);
1254         ctxt = &req->context;
1255
1256         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1257                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1258                                NULL);
1259
1260         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1261         if (BEx_chip(adapter)) {
1262                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1263                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1264                               be_encoded_q_len(mccq->len));
1265                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1266         } else {
1267                 req->hdr.version = 1;
1268                 req->cq_id = cpu_to_le16(cq->id);
1269
1270                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1271                               be_encoded_q_len(mccq->len));
1272                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1273                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1274                               ctxt, cq->id);
1275                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1276                               ctxt, 1);
1277         }
1278
1279         /* Subscribe to Link State, Sliport Event and Group 5 Events
1280          * (bits 1, 5 and 17 set)
1281          */
1282         req->async_event_bitmap[0] =
1283                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1284                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1285                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1286                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1287
1288         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1289
1290         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1291
1292         status = be_mbox_notify_wait(adapter);
1293         if (!status) {
1294                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1295
1296                 mccq->id = le16_to_cpu(resp->id);
1297                 mccq->created = true;
1298         }
1299         mutex_unlock(&adapter->mbox_lock);
1300
1301         return status;
1302 }
1303
1304 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1305                                   struct be_queue_info *mccq,
1306                                   struct be_queue_info *cq)
1307 {
1308         struct be_mcc_wrb *wrb;
1309         struct be_cmd_req_mcc_create *req;
1310         struct be_dma_mem *q_mem = &mccq->dma_mem;
1311         void *ctxt;
1312         int status;
1313
1314         if (mutex_lock_interruptible(&adapter->mbox_lock))
1315                 return -1;
1316
1317         wrb = wrb_from_mbox(adapter);
1318         req = embedded_payload(wrb);
1319         ctxt = &req->context;
1320
1321         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1322                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1323                                NULL);
1324
1325         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1326
1327         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1328         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1329                       be_encoded_q_len(mccq->len));
1330         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1331
1332         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1333
1334         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1335
1336         status = be_mbox_notify_wait(adapter);
1337         if (!status) {
1338                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1339
1340                 mccq->id = le16_to_cpu(resp->id);
1341                 mccq->created = true;
1342         }
1343
1344         mutex_unlock(&adapter->mbox_lock);
1345         return status;
1346 }
1347
1348 int be_cmd_mccq_create(struct be_adapter *adapter,
1349                        struct be_queue_info *mccq, struct be_queue_info *cq)
1350 {
1351         int status;
1352
1353         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1354         if (status && BEx_chip(adapter)) {
1355                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1356                         "or newer to avoid conflicting priorities between NIC "
1357                         "and FCoE traffic");
1358                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1359         }
1360         return status;
1361 }
1362
1363 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1364 {
1365         struct be_mcc_wrb wrb = {0};
1366         struct be_cmd_req_eth_tx_create *req;
1367         struct be_queue_info *txq = &txo->q;
1368         struct be_queue_info *cq = &txo->cq;
1369         struct be_dma_mem *q_mem = &txq->dma_mem;
1370         int status, ver = 0;
1371
1372         req = embedded_payload(&wrb);
1373         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1374                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1375
1376         if (lancer_chip(adapter)) {
1377                 req->hdr.version = 1;
1378         } else if (BEx_chip(adapter)) {
1379                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1380                         req->hdr.version = 2;
1381         } else { /* For SH */
1382                 req->hdr.version = 2;
1383         }
1384
1385         if (req->hdr.version > 0)
1386                 req->if_id = cpu_to_le16(adapter->if_handle);
1387         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1388         req->ulp_num = BE_ULP1_NUM;
1389         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1390         req->cq_id = cpu_to_le16(cq->id);
1391         req->queue_size = be_encoded_q_len(txq->len);
1392         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1393         ver = req->hdr.version;
1394
1395         status = be_cmd_notify_wait(adapter, &wrb);
1396         if (!status) {
1397                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1398
1399                 txq->id = le16_to_cpu(resp->cid);
1400                 if (ver == 2)
1401                         txo->db_offset = le32_to_cpu(resp->db_offset);
1402                 else
1403                         txo->db_offset = DB_TXULP1_OFFSET;
1404                 txq->created = true;
1405         }
1406
1407         return status;
1408 }
1409
1410 /* Uses MCC */
1411 int be_cmd_rxq_create(struct be_adapter *adapter,
1412                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1413                       u32 if_id, u32 rss, u8 *rss_id)
1414 {
1415         struct be_mcc_wrb *wrb;
1416         struct be_cmd_req_eth_rx_create *req;
1417         struct be_dma_mem *q_mem = &rxq->dma_mem;
1418         int status;
1419
1420         mutex_lock(&adapter->mcc_lock);
1421
1422         wrb = wrb_from_mccq(adapter);
1423         if (!wrb) {
1424                 status = -EBUSY;
1425                 goto err;
1426         }
1427         req = embedded_payload(wrb);
1428
1429         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1430                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1431
1432         req->cq_id = cpu_to_le16(cq_id);
1433         req->frag_size = fls(frag_size) - 1;
1434         req->num_pages = 2;
1435         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1436         req->interface_id = cpu_to_le32(if_id);
1437         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1438         req->rss_queue = cpu_to_le32(rss);
1439
1440         status = be_mcc_notify_wait(adapter);
1441         if (!status) {
1442                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1443
1444                 rxq->id = le16_to_cpu(resp->id);
1445                 rxq->created = true;
1446                 *rss_id = resp->rss_id;
1447         }
1448
1449 err:
1450         mutex_unlock(&adapter->mcc_lock);
1451         return status;
1452 }
1453
1454 /* Generic destroyer function for all types of queues
1455  * Uses Mbox
1456  */
1457 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1458                      int queue_type)
1459 {
1460         struct be_mcc_wrb *wrb;
1461         struct be_cmd_req_q_destroy *req;
1462         u8 subsys = 0, opcode = 0;
1463         int status;
1464
1465         if (mutex_lock_interruptible(&adapter->mbox_lock))
1466                 return -1;
1467
1468         wrb = wrb_from_mbox(adapter);
1469         req = embedded_payload(wrb);
1470
1471         switch (queue_type) {
1472         case QTYPE_EQ:
1473                 subsys = CMD_SUBSYSTEM_COMMON;
1474                 opcode = OPCODE_COMMON_EQ_DESTROY;
1475                 break;
1476         case QTYPE_CQ:
1477                 subsys = CMD_SUBSYSTEM_COMMON;
1478                 opcode = OPCODE_COMMON_CQ_DESTROY;
1479                 break;
1480         case QTYPE_TXQ:
1481                 subsys = CMD_SUBSYSTEM_ETH;
1482                 opcode = OPCODE_ETH_TX_DESTROY;
1483                 break;
1484         case QTYPE_RXQ:
1485                 subsys = CMD_SUBSYSTEM_ETH;
1486                 opcode = OPCODE_ETH_RX_DESTROY;
1487                 break;
1488         case QTYPE_MCCQ:
1489                 subsys = CMD_SUBSYSTEM_COMMON;
1490                 opcode = OPCODE_COMMON_MCC_DESTROY;
1491                 break;
1492         default:
1493                 BUG();
1494         }
1495
1496         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1497                                NULL);
1498         req->id = cpu_to_le16(q->id);
1499
1500         status = be_mbox_notify_wait(adapter);
1501         q->created = false;
1502
1503         mutex_unlock(&adapter->mbox_lock);
1504         return status;
1505 }
1506
1507 /* Uses MCC */
1508 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1509 {
1510         struct be_mcc_wrb *wrb;
1511         struct be_cmd_req_q_destroy *req;
1512         int status;
1513
1514         mutex_lock(&adapter->mcc_lock);
1515
1516         wrb = wrb_from_mccq(adapter);
1517         if (!wrb) {
1518                 status = -EBUSY;
1519                 goto err;
1520         }
1521         req = embedded_payload(wrb);
1522
1523         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1524                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1525         req->id = cpu_to_le16(q->id);
1526
1527         status = be_mcc_notify_wait(adapter);
1528         q->created = false;
1529
1530 err:
1531         mutex_unlock(&adapter->mcc_lock);
1532         return status;
1533 }
1534
1535 /* Create an rx filtering policy configuration on an i/f
1536  * Will use MBOX only if MCCQ has not been created.
1537  */
1538 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1539                      u32 *if_handle, u32 domain)
1540 {
1541         struct be_mcc_wrb wrb = {0};
1542         struct be_cmd_req_if_create *req;
1543         int status;
1544
1545         req = embedded_payload(&wrb);
1546         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1547                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1548                                sizeof(*req), &wrb, NULL);
1549         req->hdr.domain = domain;
1550         req->capability_flags = cpu_to_le32(cap_flags);
1551         req->enable_flags = cpu_to_le32(en_flags);
1552         req->pmac_invalid = true;
1553
1554         status = be_cmd_notify_wait(adapter, &wrb);
1555         if (!status) {
1556                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1557
1558                 *if_handle = le32_to_cpu(resp->interface_id);
1559
1560                 /* Hack to retrieve VF's pmac-id on BE3 */
1561                 if (BE3_chip(adapter) && be_virtfn(adapter))
1562                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1563         }
1564         return status;
1565 }
1566
1567 /* Uses MCCQ if available else MBOX */
1568 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1569 {
1570         struct be_mcc_wrb wrb = {0};
1571         struct be_cmd_req_if_destroy *req;
1572         int status;
1573
1574         if (interface_id == -1)
1575                 return 0;
1576
1577         req = embedded_payload(&wrb);
1578
1579         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1580                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1581                                sizeof(*req), &wrb, NULL);
1582         req->hdr.domain = domain;
1583         req->interface_id = cpu_to_le32(interface_id);
1584
1585         status = be_cmd_notify_wait(adapter, &wrb);
1586         return status;
1587 }
1588
1589 /* Get stats is a non embedded command: the request is not embedded inside
1590  * WRB but is a separate dma memory block
1591  * Uses asynchronous MCC
1592  */
1593 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1594 {
1595         struct be_mcc_wrb *wrb;
1596         struct be_cmd_req_hdr *hdr;
1597         int status = 0;
1598
1599         mutex_lock(&adapter->mcc_lock);
1600
1601         wrb = wrb_from_mccq(adapter);
1602         if (!wrb) {
1603                 status = -EBUSY;
1604                 goto err;
1605         }
1606         hdr = nonemb_cmd->va;
1607
1608         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1609                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1610                                nonemb_cmd);
1611
1612         /* version 1 of the cmd is not supported only by BE2 */
1613         if (BE2_chip(adapter))
1614                 hdr->version = 0;
1615         if (BE3_chip(adapter) || lancer_chip(adapter))
1616                 hdr->version = 1;
1617         else
1618                 hdr->version = 2;
1619
1620         status = be_mcc_notify(adapter);
1621         if (status)
1622                 goto err;
1623
1624         adapter->stats_cmd_sent = true;
1625
1626 err:
1627         mutex_unlock(&adapter->mcc_lock);
1628         return status;
1629 }
1630
1631 /* Lancer Stats */
1632 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1633                                struct be_dma_mem *nonemb_cmd)
1634 {
1635         struct be_mcc_wrb *wrb;
1636         struct lancer_cmd_req_pport_stats *req;
1637         int status = 0;
1638
1639         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1640                             CMD_SUBSYSTEM_ETH))
1641                 return -EPERM;
1642
1643         mutex_lock(&adapter->mcc_lock);
1644
1645         wrb = wrb_from_mccq(adapter);
1646         if (!wrb) {
1647                 status = -EBUSY;
1648                 goto err;
1649         }
1650         req = nonemb_cmd->va;
1651
1652         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1653                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1654                                wrb, nonemb_cmd);
1655
1656         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1657         req->cmd_params.params.reset_stats = 0;
1658
1659         status = be_mcc_notify(adapter);
1660         if (status)
1661                 goto err;
1662
1663         adapter->stats_cmd_sent = true;
1664
1665 err:
1666         mutex_unlock(&adapter->mcc_lock);
1667         return status;
1668 }
1669
1670 static int be_mac_to_link_speed(int mac_speed)
1671 {
1672         switch (mac_speed) {
1673         case PHY_LINK_SPEED_ZERO:
1674                 return 0;
1675         case PHY_LINK_SPEED_10MBPS:
1676                 return 10;
1677         case PHY_LINK_SPEED_100MBPS:
1678                 return 100;
1679         case PHY_LINK_SPEED_1GBPS:
1680                 return 1000;
1681         case PHY_LINK_SPEED_10GBPS:
1682                 return 10000;
1683         case PHY_LINK_SPEED_20GBPS:
1684                 return 20000;
1685         case PHY_LINK_SPEED_25GBPS:
1686                 return 25000;
1687         case PHY_LINK_SPEED_40GBPS:
1688                 return 40000;
1689         }
1690         return 0;
1691 }
1692
1693 /* Uses synchronous mcc
1694  * Returns link_speed in Mbps
1695  */
1696 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1697                              u8 *link_status, u32 dom)
1698 {
1699         struct be_mcc_wrb *wrb;
1700         struct be_cmd_req_link_status *req;
1701         int status;
1702
1703         mutex_lock(&adapter->mcc_lock);
1704
1705         if (link_status)
1706                 *link_status = LINK_DOWN;
1707
1708         wrb = wrb_from_mccq(adapter);
1709         if (!wrb) {
1710                 status = -EBUSY;
1711                 goto err;
1712         }
1713         req = embedded_payload(wrb);
1714
1715         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1716                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1717                                sizeof(*req), wrb, NULL);
1718
1719         /* version 1 of the cmd is not supported only by BE2 */
1720         if (!BE2_chip(adapter))
1721                 req->hdr.version = 1;
1722
1723         req->hdr.domain = dom;
1724
1725         status = be_mcc_notify_wait(adapter);
1726         if (!status) {
1727                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1728
1729                 if (link_speed) {
1730                         *link_speed = resp->link_speed ?
1731                                       le16_to_cpu(resp->link_speed) * 10 :
1732                                       be_mac_to_link_speed(resp->mac_speed);
1733
1734                         if (!resp->logical_link_status)
1735                                 *link_speed = 0;
1736                 }
1737                 if (link_status)
1738                         *link_status = resp->logical_link_status;
1739         }
1740
1741 err:
1742         mutex_unlock(&adapter->mcc_lock);
1743         return status;
1744 }
1745
1746 /* Uses synchronous mcc */
1747 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1748 {
1749         struct be_mcc_wrb *wrb;
1750         struct be_cmd_req_get_cntl_addnl_attribs *req;
1751         int status = 0;
1752
1753         mutex_lock(&adapter->mcc_lock);
1754
1755         wrb = wrb_from_mccq(adapter);
1756         if (!wrb) {
1757                 status = -EBUSY;
1758                 goto err;
1759         }
1760         req = embedded_payload(wrb);
1761
1762         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1763                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1764                                sizeof(*req), wrb, NULL);
1765
1766         status = be_mcc_notify(adapter);
1767 err:
1768         mutex_unlock(&adapter->mcc_lock);
1769         return status;
1770 }
1771
1772 /* Uses synchronous mcc */
1773 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1774 {
1775         struct be_mcc_wrb wrb = {0};
1776         struct be_cmd_req_get_fat *req;
1777         int status;
1778
1779         req = embedded_payload(&wrb);
1780
1781         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1782                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1783                                &wrb, NULL);
1784         req->fat_operation = cpu_to_le32(QUERY_FAT);
1785         status = be_cmd_notify_wait(adapter, &wrb);
1786         if (!status) {
1787                 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1788
1789                 if (dump_size && resp->log_size)
1790                         *dump_size = le32_to_cpu(resp->log_size) -
1791                                         sizeof(u32);
1792         }
1793         return status;
1794 }
1795
1796 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1797 {
1798         struct be_dma_mem get_fat_cmd;
1799         struct be_mcc_wrb *wrb;
1800         struct be_cmd_req_get_fat *req;
1801         u32 offset = 0, total_size, buf_size,
1802                                 log_offset = sizeof(u32), payload_len;
1803         int status;
1804
1805         if (buf_len == 0)
1806                 return 0;
1807
1808         total_size = buf_len;
1809
1810         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1811         get_fat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
1812                                             get_fat_cmd.size,
1813                                             &get_fat_cmd.dma, GFP_ATOMIC);
1814         if (!get_fat_cmd.va)
1815                 return -ENOMEM;
1816
1817         mutex_lock(&adapter->mcc_lock);
1818
1819         while (total_size) {
1820                 buf_size = min(total_size, (u32)60*1024);
1821                 total_size -= buf_size;
1822
1823                 wrb = wrb_from_mccq(adapter);
1824                 if (!wrb) {
1825                         status = -EBUSY;
1826                         goto err;
1827                 }
1828                 req = get_fat_cmd.va;
1829
1830                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1831                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1832                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1833                                        wrb, &get_fat_cmd);
1834
1835                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1836                 req->read_log_offset = cpu_to_le32(log_offset);
1837                 req->read_log_length = cpu_to_le32(buf_size);
1838                 req->data_buffer_size = cpu_to_le32(buf_size);
1839
1840                 status = be_mcc_notify_wait(adapter);
1841                 if (!status) {
1842                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1843
1844                         memcpy(buf + offset,
1845                                resp->data_buffer,
1846                                le32_to_cpu(resp->read_log_length));
1847                 } else {
1848                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1849                         goto err;
1850                 }
1851                 offset += buf_size;
1852                 log_offset += buf_size;
1853         }
1854 err:
1855         dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1856                           get_fat_cmd.va, get_fat_cmd.dma);
1857         mutex_unlock(&adapter->mcc_lock);
1858         return status;
1859 }
1860
1861 /* Uses synchronous mcc */
1862 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1863 {
1864         struct be_mcc_wrb *wrb;
1865         struct be_cmd_req_get_fw_version *req;
1866         int status;
1867
1868         mutex_lock(&adapter->mcc_lock);
1869
1870         wrb = wrb_from_mccq(adapter);
1871         if (!wrb) {
1872                 status = -EBUSY;
1873                 goto err;
1874         }
1875
1876         req = embedded_payload(wrb);
1877
1878         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1879                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1880                                NULL);
1881         status = be_mcc_notify_wait(adapter);
1882         if (!status) {
1883                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1884
1885                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1886                         sizeof(adapter->fw_ver));
1887                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1888                         sizeof(adapter->fw_on_flash));
1889         }
1890 err:
1891         mutex_unlock(&adapter->mcc_lock);
1892         return status;
1893 }
1894
1895 /* set the EQ delay interval of an EQ to specified value
1896  * Uses async mcc
1897  */
1898 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1899                                struct be_set_eqd *set_eqd, int num)
1900 {
1901         struct be_mcc_wrb *wrb;
1902         struct be_cmd_req_modify_eq_delay *req;
1903         int status = 0, i;
1904
1905         mutex_lock(&adapter->mcc_lock);
1906
1907         wrb = wrb_from_mccq(adapter);
1908         if (!wrb) {
1909                 status = -EBUSY;
1910                 goto err;
1911         }
1912         req = embedded_payload(wrb);
1913
1914         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1915                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1916                                NULL);
1917
1918         req->num_eq = cpu_to_le32(num);
1919         for (i = 0; i < num; i++) {
1920                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1921                 req->set_eqd[i].phase = 0;
1922                 req->set_eqd[i].delay_multiplier =
1923                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1924         }
1925
1926         status = be_mcc_notify(adapter);
1927 err:
1928         mutex_unlock(&adapter->mcc_lock);
1929         return status;
1930 }
1931
1932 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1933                       int num)
1934 {
1935         int num_eqs, i = 0;
1936
1937         while (num) {
1938                 num_eqs = min(num, 8);
1939                 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1940                 i += num_eqs;
1941                 num -= num_eqs;
1942         }
1943
1944         return 0;
1945 }
1946
1947 /* Uses sycnhronous mcc */
1948 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1949                        u32 num, u32 domain)
1950 {
1951         struct be_mcc_wrb *wrb;
1952         struct be_cmd_req_vlan_config *req;
1953         int status;
1954
1955         mutex_lock(&adapter->mcc_lock);
1956
1957         wrb = wrb_from_mccq(adapter);
1958         if (!wrb) {
1959                 status = -EBUSY;
1960                 goto err;
1961         }
1962         req = embedded_payload(wrb);
1963
1964         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1965                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1966                                wrb, NULL);
1967         req->hdr.domain = domain;
1968
1969         req->interface_id = if_id;
1970         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1971         req->num_vlan = num;
1972         memcpy(req->normal_vlan, vtag_array,
1973                req->num_vlan * sizeof(vtag_array[0]));
1974
1975         status = be_mcc_notify_wait(adapter);
1976 err:
1977         mutex_unlock(&adapter->mcc_lock);
1978         return status;
1979 }
1980
1981 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1982 {
1983         struct be_mcc_wrb *wrb;
1984         struct be_dma_mem *mem = &adapter->rx_filter;
1985         struct be_cmd_req_rx_filter *req = mem->va;
1986         int status;
1987
1988         mutex_lock(&adapter->mcc_lock);
1989
1990         wrb = wrb_from_mccq(adapter);
1991         if (!wrb) {
1992                 status = -EBUSY;
1993                 goto err;
1994         }
1995         memset(req, 0, sizeof(*req));
1996         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1997                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1998                                wrb, mem);
1999
2000         req->if_id = cpu_to_le32(adapter->if_handle);
2001         req->if_flags_mask = cpu_to_le32(flags);
2002         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
2003
2004         if (flags & BE_IF_FLAGS_MULTICAST) {
2005                 int i;
2006
2007                 /* Reset mcast promisc mode if already set by setting mask
2008                  * and not setting flags field
2009                  */
2010                 req->if_flags_mask |=
2011                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
2012                                     be_if_cap_flags(adapter));
2013                 req->mcast_num = cpu_to_le32(adapter->mc_count);
2014                 for (i = 0; i < adapter->mc_count; i++)
2015                         ether_addr_copy(req->mcast_mac[i].byte,
2016                                         adapter->mc_list[i].mac);
2017         }
2018
2019         status = be_mcc_notify_wait(adapter);
2020 err:
2021         mutex_unlock(&adapter->mcc_lock);
2022         return status;
2023 }
2024
2025 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2026 {
2027         struct device *dev = &adapter->pdev->dev;
2028
2029         if ((flags & be_if_cap_flags(adapter)) != flags) {
2030                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2031                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2032                          be_if_cap_flags(adapter));
2033         }
2034         flags &= be_if_cap_flags(adapter);
2035         if (!flags)
2036                 return -ENOTSUPP;
2037
2038         return __be_cmd_rx_filter(adapter, flags, value);
2039 }
2040
2041 /* Uses synchrounous mcc */
2042 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2043 {
2044         struct be_mcc_wrb *wrb;
2045         struct be_cmd_req_set_flow_control *req;
2046         int status;
2047
2048         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2049                             CMD_SUBSYSTEM_COMMON))
2050                 return -EPERM;
2051
2052         mutex_lock(&adapter->mcc_lock);
2053
2054         wrb = wrb_from_mccq(adapter);
2055         if (!wrb) {
2056                 status = -EBUSY;
2057                 goto err;
2058         }
2059         req = embedded_payload(wrb);
2060
2061         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2062                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2063                                wrb, NULL);
2064
2065         req->hdr.version = 1;
2066         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2067         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2068
2069         status = be_mcc_notify_wait(adapter);
2070
2071 err:
2072         mutex_unlock(&adapter->mcc_lock);
2073
2074         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2075                 return  -EOPNOTSUPP;
2076
2077         return status;
2078 }
2079
2080 /* Uses sycn mcc */
2081 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2082 {
2083         struct be_mcc_wrb *wrb;
2084         struct be_cmd_req_get_flow_control *req;
2085         int status;
2086
2087         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2088                             CMD_SUBSYSTEM_COMMON))
2089                 return -EPERM;
2090
2091         mutex_lock(&adapter->mcc_lock);
2092
2093         wrb = wrb_from_mccq(adapter);
2094         if (!wrb) {
2095                 status = -EBUSY;
2096                 goto err;
2097         }
2098         req = embedded_payload(wrb);
2099
2100         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2101                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2102                                wrb, NULL);
2103
2104         status = be_mcc_notify_wait(adapter);
2105         if (!status) {
2106                 struct be_cmd_resp_get_flow_control *resp =
2107                                                 embedded_payload(wrb);
2108
2109                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2110                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2111         }
2112
2113 err:
2114         mutex_unlock(&adapter->mcc_lock);
2115         return status;
2116 }
2117
2118 /* Uses mbox */
2119 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2120 {
2121         struct be_mcc_wrb *wrb;
2122         struct be_cmd_req_query_fw_cfg *req;
2123         int status;
2124
2125         if (mutex_lock_interruptible(&adapter->mbox_lock))
2126                 return -1;
2127
2128         wrb = wrb_from_mbox(adapter);
2129         req = embedded_payload(wrb);
2130
2131         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2132                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2133                                sizeof(*req), wrb, NULL);
2134
2135         status = be_mbox_notify_wait(adapter);
2136         if (!status) {
2137                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2138
2139                 adapter->port_num = le32_to_cpu(resp->phys_port);
2140                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2141                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2142                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2143                 dev_info(&adapter->pdev->dev,
2144                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2145                          adapter->function_mode, adapter->function_caps);
2146         }
2147
2148         mutex_unlock(&adapter->mbox_lock);
2149         return status;
2150 }
2151
2152 /* Uses mbox */
2153 int be_cmd_reset_function(struct be_adapter *adapter)
2154 {
2155         struct be_mcc_wrb *wrb;
2156         struct be_cmd_req_hdr *req;
2157         int status;
2158
2159         if (lancer_chip(adapter)) {
2160                 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2161                           adapter->db + SLIPORT_CONTROL_OFFSET);
2162                 status = lancer_wait_ready(adapter);
2163                 if (status)
2164                         dev_err(&adapter->pdev->dev,
2165                                 "Adapter in non recoverable error\n");
2166                 return status;
2167         }
2168
2169         if (mutex_lock_interruptible(&adapter->mbox_lock))
2170                 return -1;
2171
2172         wrb = wrb_from_mbox(adapter);
2173         req = embedded_payload(wrb);
2174
2175         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2176                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2177                                NULL);
2178
2179         status = be_mbox_notify_wait(adapter);
2180
2181         mutex_unlock(&adapter->mbox_lock);
2182         return status;
2183 }
2184
2185 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2186                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2187 {
2188         struct be_mcc_wrb *wrb;
2189         struct be_cmd_req_rss_config *req;
2190         int status;
2191
2192         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2193                 return 0;
2194
2195         mutex_lock(&adapter->mcc_lock);
2196
2197         wrb = wrb_from_mccq(adapter);
2198         if (!wrb) {
2199                 status = -EBUSY;
2200                 goto err;
2201         }
2202         req = embedded_payload(wrb);
2203
2204         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2205                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2206
2207         req->if_id = cpu_to_le32(adapter->if_handle);
2208         req->enable_rss = cpu_to_le16(rss_hash_opts);
2209         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2210
2211         if (!BEx_chip(adapter))
2212                 req->hdr.version = 1;
2213
2214         memcpy(req->cpu_table, rsstable, table_size);
2215         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2216         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2217
2218         status = be_mcc_notify_wait(adapter);
2219 err:
2220         mutex_unlock(&adapter->mcc_lock);
2221         return status;
2222 }
2223
2224 /* Uses sync mcc */
2225 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2226                             u8 bcn, u8 sts, u8 state)
2227 {
2228         struct be_mcc_wrb *wrb;
2229         struct be_cmd_req_enable_disable_beacon *req;
2230         int status;
2231
2232         mutex_lock(&adapter->mcc_lock);
2233
2234         wrb = wrb_from_mccq(adapter);
2235         if (!wrb) {
2236                 status = -EBUSY;
2237                 goto err;
2238         }
2239         req = embedded_payload(wrb);
2240
2241         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2242                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2243                                sizeof(*req), wrb, NULL);
2244
2245         req->port_num = port_num;
2246         req->beacon_state = state;
2247         req->beacon_duration = bcn;
2248         req->status_duration = sts;
2249
2250         status = be_mcc_notify_wait(adapter);
2251
2252 err:
2253         mutex_unlock(&adapter->mcc_lock);
2254         return status;
2255 }
2256
2257 /* Uses sync mcc */
2258 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2259 {
2260         struct be_mcc_wrb *wrb;
2261         struct be_cmd_req_get_beacon_state *req;
2262         int status;
2263
2264         mutex_lock(&adapter->mcc_lock);
2265
2266         wrb = wrb_from_mccq(adapter);
2267         if (!wrb) {
2268                 status = -EBUSY;
2269                 goto err;
2270         }
2271         req = embedded_payload(wrb);
2272
2273         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2274                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2275                                wrb, NULL);
2276
2277         req->port_num = port_num;
2278
2279         status = be_mcc_notify_wait(adapter);
2280         if (!status) {
2281                 struct be_cmd_resp_get_beacon_state *resp =
2282                                                 embedded_payload(wrb);
2283
2284                 *state = resp->beacon_state;
2285         }
2286
2287 err:
2288         mutex_unlock(&adapter->mcc_lock);
2289         return status;
2290 }
2291
2292 /* Uses sync mcc */
2293 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2294                                       u8 page_num, u8 *data)
2295 {
2296         struct be_dma_mem cmd;
2297         struct be_mcc_wrb *wrb;
2298         struct be_cmd_req_port_type *req;
2299         int status;
2300
2301         if (page_num > TR_PAGE_A2)
2302                 return -EINVAL;
2303
2304         cmd.size = sizeof(struct be_cmd_resp_port_type);
2305         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2306                                     GFP_ATOMIC);
2307         if (!cmd.va) {
2308                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2309                 return -ENOMEM;
2310         }
2311
2312         mutex_lock(&adapter->mcc_lock);
2313
2314         wrb = wrb_from_mccq(adapter);
2315         if (!wrb) {
2316                 status = -EBUSY;
2317                 goto err;
2318         }
2319         req = cmd.va;
2320
2321         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2322                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2323                                cmd.size, wrb, &cmd);
2324
2325         req->port = cpu_to_le32(adapter->hba_port_num);
2326         req->page_num = cpu_to_le32(page_num);
2327         status = be_mcc_notify_wait(adapter);
2328         if (!status) {
2329                 struct be_cmd_resp_port_type *resp = cmd.va;
2330
2331                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2332         }
2333 err:
2334         mutex_unlock(&adapter->mcc_lock);
2335         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2336         return status;
2337 }
2338
2339 static int lancer_cmd_write_object(struct be_adapter *adapter,
2340                                    struct be_dma_mem *cmd, u32 data_size,
2341                                    u32 data_offset, const char *obj_name,
2342                                    u32 *data_written, u8 *change_status,
2343                                    u8 *addn_status)
2344 {
2345         struct be_mcc_wrb *wrb;
2346         struct lancer_cmd_req_write_object *req;
2347         struct lancer_cmd_resp_write_object *resp;
2348         void *ctxt = NULL;
2349         int status;
2350
2351         mutex_lock(&adapter->mcc_lock);
2352         adapter->flash_status = 0;
2353
2354         wrb = wrb_from_mccq(adapter);
2355         if (!wrb) {
2356                 status = -EBUSY;
2357                 goto err_unlock;
2358         }
2359
2360         req = embedded_payload(wrb);
2361
2362         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2363                                OPCODE_COMMON_WRITE_OBJECT,
2364                                sizeof(struct lancer_cmd_req_write_object), wrb,
2365                                NULL);
2366
2367         ctxt = &req->context;
2368         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2369                       write_length, ctxt, data_size);
2370
2371         if (data_size == 0)
2372                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2373                               eof, ctxt, 1);
2374         else
2375                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2376                               eof, ctxt, 0);
2377
2378         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2379         req->write_offset = cpu_to_le32(data_offset);
2380         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2381         req->descriptor_count = cpu_to_le32(1);
2382         req->buf_len = cpu_to_le32(data_size);
2383         req->addr_low = cpu_to_le32((cmd->dma +
2384                                      sizeof(struct lancer_cmd_req_write_object))
2385                                     & 0xFFFFFFFF);
2386         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2387                                 sizeof(struct lancer_cmd_req_write_object)));
2388
2389         status = be_mcc_notify(adapter);
2390         if (status)
2391                 goto err_unlock;
2392
2393         mutex_unlock(&adapter->mcc_lock);
2394
2395         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2396                                          msecs_to_jiffies(60000)))
2397                 status = -ETIMEDOUT;
2398         else
2399                 status = adapter->flash_status;
2400
2401         resp = embedded_payload(wrb);
2402         if (!status) {
2403                 *data_written = le32_to_cpu(resp->actual_write_len);
2404                 *change_status = resp->change_status;
2405         } else {
2406                 *addn_status = resp->additional_status;
2407         }
2408
2409         return status;
2410
2411 err_unlock:
2412         mutex_unlock(&adapter->mcc_lock);
2413         return status;
2414 }
2415
2416 int be_cmd_query_cable_type(struct be_adapter *adapter)
2417 {
2418         u8 page_data[PAGE_DATA_LEN];
2419         int status;
2420
2421         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2422                                                    page_data);
2423         if (!status) {
2424                 switch (adapter->phy.interface_type) {
2425                 case PHY_TYPE_QSFP:
2426                         adapter->phy.cable_type =
2427                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2428                         break;
2429                 case PHY_TYPE_SFP_PLUS_10GB:
2430                         adapter->phy.cable_type =
2431                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2432                         break;
2433                 default:
2434                         adapter->phy.cable_type = 0;
2435                         break;
2436                 }
2437         }
2438         return status;
2439 }
2440
2441 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2442 {
2443         u8 page_data[PAGE_DATA_LEN];
2444         int status;
2445
2446         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2447                                                    page_data);
2448         if (!status) {
2449                 strlcpy(adapter->phy.vendor_name, page_data +
2450                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2451                 strlcpy(adapter->phy.vendor_pn,
2452                         page_data + SFP_VENDOR_PN_OFFSET,
2453                         SFP_VENDOR_NAME_LEN - 1);
2454         }
2455
2456         return status;
2457 }
2458
2459 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2460                                     const char *obj_name)
2461 {
2462         struct lancer_cmd_req_delete_object *req;
2463         struct be_mcc_wrb *wrb;
2464         int status;
2465
2466         mutex_lock(&adapter->mcc_lock);
2467
2468         wrb = wrb_from_mccq(adapter);
2469         if (!wrb) {
2470                 status = -EBUSY;
2471                 goto err;
2472         }
2473
2474         req = embedded_payload(wrb);
2475
2476         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2477                                OPCODE_COMMON_DELETE_OBJECT,
2478                                sizeof(*req), wrb, NULL);
2479
2480         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2481
2482         status = be_mcc_notify_wait(adapter);
2483 err:
2484         mutex_unlock(&adapter->mcc_lock);
2485         return status;
2486 }
2487
2488 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2489                            u32 data_size, u32 data_offset, const char *obj_name,
2490                            u32 *data_read, u32 *eof, u8 *addn_status)
2491 {
2492         struct be_mcc_wrb *wrb;
2493         struct lancer_cmd_req_read_object *req;
2494         struct lancer_cmd_resp_read_object *resp;
2495         int status;
2496
2497         mutex_lock(&adapter->mcc_lock);
2498
2499         wrb = wrb_from_mccq(adapter);
2500         if (!wrb) {
2501                 status = -EBUSY;
2502                 goto err_unlock;
2503         }
2504
2505         req = embedded_payload(wrb);
2506
2507         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2508                                OPCODE_COMMON_READ_OBJECT,
2509                                sizeof(struct lancer_cmd_req_read_object), wrb,
2510                                NULL);
2511
2512         req->desired_read_len = cpu_to_le32(data_size);
2513         req->read_offset = cpu_to_le32(data_offset);
2514         strcpy(req->object_name, obj_name);
2515         req->descriptor_count = cpu_to_le32(1);
2516         req->buf_len = cpu_to_le32(data_size);
2517         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2518         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2519
2520         status = be_mcc_notify_wait(adapter);
2521
2522         resp = embedded_payload(wrb);
2523         if (!status) {
2524                 *data_read = le32_to_cpu(resp->actual_read_len);
2525                 *eof = le32_to_cpu(resp->eof);
2526         } else {
2527                 *addn_status = resp->additional_status;
2528         }
2529
2530 err_unlock:
2531         mutex_unlock(&adapter->mcc_lock);
2532         return status;
2533 }
2534
2535 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2536                                  struct be_dma_mem *cmd, u32 flash_type,
2537                                  u32 flash_opcode, u32 img_offset, u32 buf_size)
2538 {
2539         struct be_mcc_wrb *wrb;
2540         struct be_cmd_write_flashrom *req;
2541         int status;
2542
2543         mutex_lock(&adapter->mcc_lock);
2544         adapter->flash_status = 0;
2545
2546         wrb = wrb_from_mccq(adapter);
2547         if (!wrb) {
2548                 status = -EBUSY;
2549                 goto err_unlock;
2550         }
2551         req = cmd->va;
2552
2553         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2554                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2555                                cmd);
2556
2557         req->params.op_type = cpu_to_le32(flash_type);
2558         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2559                 req->params.offset = cpu_to_le32(img_offset);
2560
2561         req->params.op_code = cpu_to_le32(flash_opcode);
2562         req->params.data_buf_size = cpu_to_le32(buf_size);
2563
2564         status = be_mcc_notify(adapter);
2565         if (status)
2566                 goto err_unlock;
2567
2568         mutex_unlock(&adapter->mcc_lock);
2569
2570         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2571                                          msecs_to_jiffies(40000)))
2572                 status = -ETIMEDOUT;
2573         else
2574                 status = adapter->flash_status;
2575
2576         return status;
2577
2578 err_unlock:
2579         mutex_unlock(&adapter->mcc_lock);
2580         return status;
2581 }
2582
2583 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2584                                 u16 img_optype, u32 img_offset, u32 crc_offset)
2585 {
2586         struct be_cmd_read_flash_crc *req;
2587         struct be_mcc_wrb *wrb;
2588         int status;
2589
2590         mutex_lock(&adapter->mcc_lock);
2591
2592         wrb = wrb_from_mccq(adapter);
2593         if (!wrb) {
2594                 status = -EBUSY;
2595                 goto err;
2596         }
2597         req = embedded_payload(wrb);
2598
2599         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2600                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2601                                wrb, NULL);
2602
2603         req->params.op_type = cpu_to_le32(img_optype);
2604         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2605                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2606         else
2607                 req->params.offset = cpu_to_le32(crc_offset);
2608
2609         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2610         req->params.data_buf_size = cpu_to_le32(0x4);
2611
2612         status = be_mcc_notify_wait(adapter);
2613         if (!status)
2614                 memcpy(flashed_crc, req->crc, 4);
2615
2616 err:
2617         mutex_unlock(&adapter->mcc_lock);
2618         return status;
2619 }
2620
2621 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2622
2623 static bool phy_flashing_required(struct be_adapter *adapter)
2624 {
2625         return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2626                 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2627 }
2628
2629 static bool is_comp_in_ufi(struct be_adapter *adapter,
2630                            struct flash_section_info *fsec, int type)
2631 {
2632         int i = 0, img_type = 0;
2633         struct flash_section_info_g2 *fsec_g2 = NULL;
2634
2635         if (BE2_chip(adapter))
2636                 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2637
2638         for (i = 0; i < MAX_FLASH_COMP; i++) {
2639                 if (fsec_g2)
2640                         img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2641                 else
2642                         img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2643
2644                 if (img_type == type)
2645                         return true;
2646         }
2647         return false;
2648 }
2649
2650 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2651                                                 int header_size,
2652                                                 const struct firmware *fw)
2653 {
2654         struct flash_section_info *fsec = NULL;
2655         const u8 *p = fw->data;
2656
2657         p += header_size;
2658         while (p < (fw->data + fw->size)) {
2659                 fsec = (struct flash_section_info *)p;
2660                 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2661                         return fsec;
2662                 p += 32;
2663         }
2664         return NULL;
2665 }
2666
2667 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2668                               u32 img_offset, u32 img_size, int hdr_size,
2669                               u16 img_optype, bool *crc_match)
2670 {
2671         u32 crc_offset;
2672         int status;
2673         u8 crc[4];
2674
2675         status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2676                                       img_size - 4);
2677         if (status)
2678                 return status;
2679
2680         crc_offset = hdr_size + img_offset + img_size - 4;
2681
2682         /* Skip flashing, if crc of flashed region matches */
2683         if (!memcmp(crc, p + crc_offset, 4))
2684                 *crc_match = true;
2685         else
2686                 *crc_match = false;
2687
2688         return status;
2689 }
2690
2691 static int be_flash(struct be_adapter *adapter, const u8 *img,
2692                     struct be_dma_mem *flash_cmd, int optype, int img_size,
2693                     u32 img_offset)
2694 {
2695         u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2696         struct be_cmd_write_flashrom *req = flash_cmd->va;
2697         int status;
2698
2699         while (total_bytes) {
2700                 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2701
2702                 total_bytes -= num_bytes;
2703
2704                 if (!total_bytes) {
2705                         if (optype == OPTYPE_PHY_FW)
2706                                 flash_op = FLASHROM_OPER_PHY_FLASH;
2707                         else
2708                                 flash_op = FLASHROM_OPER_FLASH;
2709                 } else {
2710                         if (optype == OPTYPE_PHY_FW)
2711                                 flash_op = FLASHROM_OPER_PHY_SAVE;
2712                         else
2713                                 flash_op = FLASHROM_OPER_SAVE;
2714                 }
2715
2716                 memcpy(req->data_buf, img, num_bytes);
2717                 img += num_bytes;
2718                 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2719                                                flash_op, img_offset +
2720                                                bytes_sent, num_bytes);
2721                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2722                     optype == OPTYPE_PHY_FW)
2723                         break;
2724                 else if (status)
2725                         return status;
2726
2727                 bytes_sent += num_bytes;
2728         }
2729         return 0;
2730 }
2731
2732 #define NCSI_UPDATE_LOG "NCSI section update is not supported in FW ver %s\n"
2733 static bool be_fw_ncsi_supported(char *ver)
2734 {
2735         int v1[4] = {3, 102, 148, 0}; /* Min ver that supports NCSI FW */
2736         int v2[4];
2737         int i;
2738
2739         if (sscanf(ver, "%d.%d.%d.%d", &v2[0], &v2[1], &v2[2], &v2[3]) != 4)
2740                 return false;
2741
2742         for (i = 0; i < 4; i++) {
2743                 if (v1[i] < v2[i])
2744                         return true;
2745                 else if (v1[i] > v2[i])
2746                         return false;
2747         }
2748
2749         return true;
2750 }
2751
2752 /* For BE2, BE3 and BE3-R */
2753 static int be_flash_BEx(struct be_adapter *adapter,
2754                         const struct firmware *fw,
2755                         struct be_dma_mem *flash_cmd, int num_of_images)
2756 {
2757         int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2758         struct device *dev = &adapter->pdev->dev;
2759         struct flash_section_info *fsec = NULL;
2760         int status, i, filehdr_size, num_comp;
2761         const struct flash_comp *pflashcomp;
2762         bool crc_match;
2763         const u8 *p;
2764
2765         struct flash_comp gen3_flash_types[] = {
2766                 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2767                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2768                 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2769                         BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2770                 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2771                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2772                 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2773                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2774                 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2775                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2776                 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2777                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2778                 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2779                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2780                 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2781                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2782                 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2783                         BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2784                 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2785                         BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2786         };
2787
2788         struct flash_comp gen2_flash_types[] = {
2789                 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2790                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2791                 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2792                         BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2793                 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2794                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2795                 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2796                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2797                 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2798                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2799                 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2800                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2801                 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2802                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2803                 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2804                          BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2805         };
2806
2807         if (BE3_chip(adapter)) {
2808                 pflashcomp = gen3_flash_types;
2809                 filehdr_size = sizeof(struct flash_file_hdr_g3);
2810                 num_comp = ARRAY_SIZE(gen3_flash_types);
2811         } else {
2812                 pflashcomp = gen2_flash_types;
2813                 filehdr_size = sizeof(struct flash_file_hdr_g2);
2814                 num_comp = ARRAY_SIZE(gen2_flash_types);
2815                 img_hdrs_size = 0;
2816         }
2817
2818         /* Get flash section info*/
2819         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2820         if (!fsec) {
2821                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2822                 return -1;
2823         }
2824         for (i = 0; i < num_comp; i++) {
2825                 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2826                         continue;
2827
2828                 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2829                     !be_fw_ncsi_supported(adapter->fw_ver)) {
2830                         dev_info(dev, NCSI_UPDATE_LOG, adapter->fw_ver);
2831                         continue;
2832                 }
2833
2834                 if (pflashcomp[i].optype == OPTYPE_PHY_FW  &&
2835                     !phy_flashing_required(adapter))
2836                         continue;
2837
2838                 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2839                         status = be_check_flash_crc(adapter, fw->data,
2840                                                     pflashcomp[i].offset,
2841                                                     pflashcomp[i].size,
2842                                                     filehdr_size +
2843                                                     img_hdrs_size,
2844                                                     OPTYPE_REDBOOT, &crc_match);
2845                         if (status) {
2846                                 dev_err(dev,
2847                                         "Could not get CRC for 0x%x region\n",
2848                                         pflashcomp[i].optype);
2849                                 continue;
2850                         }
2851
2852                         if (crc_match)
2853                                 continue;
2854                 }
2855
2856                 p = fw->data + filehdr_size + pflashcomp[i].offset +
2857                         img_hdrs_size;
2858                 if (p + pflashcomp[i].size > fw->data + fw->size)
2859                         return -1;
2860
2861                 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2862                                   pflashcomp[i].size, 0);
2863                 if (status) {
2864                         dev_err(dev, "Flashing section type 0x%x failed\n",
2865                                 pflashcomp[i].img_type);
2866                         return status;
2867                 }
2868         }
2869         return 0;
2870 }
2871
2872 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2873 {
2874         u32 img_type = le32_to_cpu(fsec_entry.type);
2875         u16 img_optype = le16_to_cpu(fsec_entry.optype);
2876
2877         if (img_optype != 0xFFFF)
2878                 return img_optype;
2879
2880         switch (img_type) {
2881         case IMAGE_FIRMWARE_ISCSI:
2882                 img_optype = OPTYPE_ISCSI_ACTIVE;
2883                 break;
2884         case IMAGE_BOOT_CODE:
2885                 img_optype = OPTYPE_REDBOOT;
2886                 break;
2887         case IMAGE_OPTION_ROM_ISCSI:
2888                 img_optype = OPTYPE_BIOS;
2889                 break;
2890         case IMAGE_OPTION_ROM_PXE:
2891                 img_optype = OPTYPE_PXE_BIOS;
2892                 break;
2893         case IMAGE_OPTION_ROM_FCOE:
2894                 img_optype = OPTYPE_FCOE_BIOS;
2895                 break;
2896         case IMAGE_FIRMWARE_BACKUP_ISCSI:
2897                 img_optype = OPTYPE_ISCSI_BACKUP;
2898                 break;
2899         case IMAGE_NCSI:
2900                 img_optype = OPTYPE_NCSI_FW;
2901                 break;
2902         case IMAGE_FLASHISM_JUMPVECTOR:
2903                 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2904                 break;
2905         case IMAGE_FIRMWARE_PHY:
2906                 img_optype = OPTYPE_SH_PHY_FW;
2907                 break;
2908         case IMAGE_REDBOOT_DIR:
2909                 img_optype = OPTYPE_REDBOOT_DIR;
2910                 break;
2911         case IMAGE_REDBOOT_CONFIG:
2912                 img_optype = OPTYPE_REDBOOT_CONFIG;
2913                 break;
2914         case IMAGE_UFI_DIR:
2915                 img_optype = OPTYPE_UFI_DIR;
2916                 break;
2917         default:
2918                 break;
2919         }
2920
2921         return img_optype;
2922 }
2923
2924 static int be_flash_skyhawk(struct be_adapter *adapter,
2925                             const struct firmware *fw,
2926                             struct be_dma_mem *flash_cmd, int num_of_images)
2927 {
2928         int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2929         bool crc_match, old_fw_img, flash_offset_support = true;
2930         struct device *dev = &adapter->pdev->dev;
2931         struct flash_section_info *fsec = NULL;
2932         u32 img_offset, img_size, img_type;
2933         u16 img_optype, flash_optype;
2934         int status, i, filehdr_size;
2935         const u8 *p;
2936
2937         filehdr_size = sizeof(struct flash_file_hdr_g3);
2938         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2939         if (!fsec) {
2940                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2941                 return -EINVAL;
2942         }
2943
2944 retry_flash:
2945         for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2946                 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2947                 img_size   = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2948                 img_type   = le32_to_cpu(fsec->fsec_entry[i].type);
2949                 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2950                 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2951
2952                 if (img_optype == 0xFFFF)
2953                         continue;
2954
2955                 if (flash_offset_support)
2956                         flash_optype = OPTYPE_OFFSET_SPECIFIED;
2957                 else
2958                         flash_optype = img_optype;
2959
2960                 /* Don't bother verifying CRC if an old FW image is being
2961                  * flashed
2962                  */
2963                 if (old_fw_img)
2964                         goto flash;
2965
2966                 status = be_check_flash_crc(adapter, fw->data, img_offset,
2967                                             img_size, filehdr_size +
2968                                             img_hdrs_size, flash_optype,
2969                                             &crc_match);
2970                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2971                     base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2972                         /* The current FW image on the card does not support
2973                          * OFFSET based flashing. Retry using older mechanism
2974                          * of OPTYPE based flashing
2975                          */
2976                         if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2977                                 flash_offset_support = false;
2978                                 goto retry_flash;
2979                         }
2980
2981                         /* The current FW image on the card does not recognize
2982                          * the new FLASH op_type. The FW download is partially
2983                          * complete. Reboot the server now to enable FW image
2984                          * to recognize the new FLASH op_type. To complete the
2985                          * remaining process, download the same FW again after
2986                          * the reboot.
2987                          */
2988                         dev_err(dev, "Flash incomplete. Reset the server\n");
2989                         dev_err(dev, "Download FW image again after reset\n");
2990                         return -EAGAIN;
2991                 } else if (status) {
2992                         dev_err(dev, "Could not get CRC for 0x%x region\n",
2993                                 img_optype);
2994                         return -EFAULT;
2995                 }
2996
2997                 if (crc_match)
2998                         continue;
2999
3000 flash:
3001                 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
3002                 if (p + img_size > fw->data + fw->size)
3003                         return -1;
3004
3005                 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
3006                                   img_offset);
3007
3008                 /* The current FW image on the card does not support OFFSET
3009                  * based flashing. Retry using older mechanism of OPTYPE based
3010                  * flashing
3011                  */
3012                 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
3013                     flash_optype == OPTYPE_OFFSET_SPECIFIED) {
3014                         flash_offset_support = false;
3015                         goto retry_flash;
3016                 }
3017
3018                 /* For old FW images ignore ILLEGAL_FIELD error or errors on
3019                  * UFI_DIR region
3020                  */
3021                 if (old_fw_img &&
3022                     (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
3023                      (img_optype == OPTYPE_UFI_DIR &&
3024                       base_status(status) == MCC_STATUS_FAILED))) {
3025                         continue;
3026                 } else if (status) {
3027                         dev_err(dev, "Flashing section type 0x%x failed\n",
3028                                 img_type);
3029
3030                         switch (addl_status(status)) {
3031                         case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3032                                 dev_err(dev,
3033                                         "Digital signature missing in FW\n");
3034                                 return -EINVAL;
3035                         case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3036                                 dev_err(dev,
3037                                         "Invalid digital signature in FW\n");
3038                                 return -EINVAL;
3039                         default:
3040                                 return -EFAULT;
3041                         }
3042                 }
3043         }
3044         return 0;
3045 }
3046
3047 int lancer_fw_download(struct be_adapter *adapter,
3048                        const struct firmware *fw)
3049 {
3050         struct device *dev = &adapter->pdev->dev;
3051         struct be_dma_mem flash_cmd;
3052         const u8 *data_ptr = NULL;
3053         u8 *dest_image_ptr = NULL;
3054         size_t image_size = 0;
3055         u32 chunk_size = 0;
3056         u32 data_written = 0;
3057         u32 offset = 0;
3058         int status = 0;
3059         u8 add_status = 0;
3060         u8 change_status;
3061
3062         if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3063                 dev_err(dev, "FW image size should be multiple of 4\n");
3064                 return -EINVAL;
3065         }
3066
3067         flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3068                                 + LANCER_FW_DOWNLOAD_CHUNK;
3069         flash_cmd.va = dma_alloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3070                                           GFP_KERNEL);
3071         if (!flash_cmd.va)
3072                 return -ENOMEM;
3073
3074         dest_image_ptr = flash_cmd.va +
3075                                 sizeof(struct lancer_cmd_req_write_object);
3076         image_size = fw->size;
3077         data_ptr = fw->data;
3078
3079         while (image_size) {
3080                 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3081
3082                 /* Copy the image chunk content. */
3083                 memcpy(dest_image_ptr, data_ptr, chunk_size);
3084
3085                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3086                                                  chunk_size, offset,
3087                                                  LANCER_FW_DOWNLOAD_LOCATION,
3088                                                  &data_written, &change_status,
3089                                                  &add_status);
3090                 if (status)
3091                         break;
3092
3093                 offset += data_written;
3094                 data_ptr += data_written;
3095                 image_size -= data_written;
3096         }
3097
3098         if (!status) {
3099                 /* Commit the FW written */
3100                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3101                                                  0, offset,
3102                                                  LANCER_FW_DOWNLOAD_LOCATION,
3103                                                  &data_written, &change_status,
3104                                                  &add_status);
3105         }
3106
3107         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3108         if (status) {
3109                 dev_err(dev, "Firmware load error\n");
3110                 return be_cmd_status(status);
3111         }
3112
3113         dev_info(dev, "Firmware flashed successfully\n");
3114
3115         if (change_status == LANCER_FW_RESET_NEEDED) {
3116                 dev_info(dev, "Resetting adapter to activate new FW\n");
3117                 status = lancer_physdev_ctrl(adapter,
3118                                              PHYSDEV_CONTROL_FW_RESET_MASK);
3119                 if (status) {
3120                         dev_err(dev, "Adapter busy, could not reset FW\n");
3121                         dev_err(dev, "Reboot server to activate new FW\n");
3122                 }
3123         } else if (change_status != LANCER_NO_RESET_NEEDED) {
3124                 dev_info(dev, "Reboot server to activate new FW\n");
3125         }
3126
3127         return 0;
3128 }
3129
3130 /* Check if the flash image file is compatible with the adapter that
3131  * is being flashed.
3132  */
3133 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3134                                        struct flash_file_hdr_g3 *fhdr)
3135 {
3136         if (!fhdr) {
3137                 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3138                 return false;
3139         }
3140
3141         /* First letter of the build version is used to identify
3142          * which chip this image file is meant for.
3143          */
3144         switch (fhdr->build[0]) {
3145         case BLD_STR_UFI_TYPE_SH:
3146                 if (!skyhawk_chip(adapter))
3147                         return false;
3148                 break;
3149         case BLD_STR_UFI_TYPE_BE3:
3150                 if (!BE3_chip(adapter))
3151                         return false;
3152                 break;
3153         case BLD_STR_UFI_TYPE_BE2:
3154                 if (!BE2_chip(adapter))
3155                         return false;
3156                 break;
3157         default:
3158                 return false;
3159         }
3160
3161         /* In BE3 FW images the "asic_type_rev" field doesn't track the
3162          * asic_rev of the chips it is compatible with.
3163          * When asic_type_rev is 0 the image is compatible only with
3164          * pre-BE3-R chips (asic_rev < 0x10)
3165          */
3166         if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3167                 return adapter->asic_rev < 0x10;
3168         else
3169                 return (fhdr->asic_type_rev >= adapter->asic_rev);
3170 }
3171
3172 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3173 {
3174         struct device *dev = &adapter->pdev->dev;
3175         struct flash_file_hdr_g3 *fhdr3;
3176         struct image_hdr *img_hdr_ptr;
3177         int status = 0, i, num_imgs;
3178         struct be_dma_mem flash_cmd;
3179
3180         fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3181         if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3182                 dev_err(dev, "Flash image is not compatible with adapter\n");
3183                 return -EINVAL;
3184         }
3185
3186         flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3187         flash_cmd.va = dma_alloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3188                                           GFP_KERNEL);
3189         if (!flash_cmd.va)
3190                 return -ENOMEM;
3191
3192         num_imgs = le32_to_cpu(fhdr3->num_imgs);
3193         for (i = 0; i < num_imgs; i++) {
3194                 img_hdr_ptr = (struct image_hdr *)(fw->data +
3195                                 (sizeof(struct flash_file_hdr_g3) +
3196                                  i * sizeof(struct image_hdr)));
3197                 if (!BE2_chip(adapter) &&
3198                     le32_to_cpu(img_hdr_ptr->imageid) != 1)
3199                         continue;
3200
3201                 if (skyhawk_chip(adapter))
3202                         status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3203                                                   num_imgs);
3204                 else
3205                         status = be_flash_BEx(adapter, fw, &flash_cmd,
3206                                               num_imgs);
3207         }
3208
3209         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3210         if (!status)
3211                 dev_info(dev, "Firmware flashed successfully\n");
3212
3213         return status;
3214 }
3215
3216 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3217                             struct be_dma_mem *nonemb_cmd)
3218 {
3219         struct be_mcc_wrb *wrb;
3220         struct be_cmd_req_acpi_wol_magic_config *req;
3221         int status;
3222
3223         mutex_lock(&adapter->mcc_lock);
3224
3225         wrb = wrb_from_mccq(adapter);
3226         if (!wrb) {
3227                 status = -EBUSY;
3228                 goto err;
3229         }
3230         req = nonemb_cmd->va;
3231
3232         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3233                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3234                                wrb, nonemb_cmd);
3235         memcpy(req->magic_mac, mac, ETH_ALEN);
3236
3237         status = be_mcc_notify_wait(adapter);
3238
3239 err:
3240         mutex_unlock(&adapter->mcc_lock);
3241         return status;
3242 }
3243
3244 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3245                         u8 loopback_type, u8 enable)
3246 {
3247         struct be_mcc_wrb *wrb;
3248         struct be_cmd_req_set_lmode *req;
3249         int status;
3250
3251         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3252                             CMD_SUBSYSTEM_LOWLEVEL))
3253                 return -EPERM;
3254
3255         mutex_lock(&adapter->mcc_lock);
3256
3257         wrb = wrb_from_mccq(adapter);
3258         if (!wrb) {
3259                 status = -EBUSY;
3260                 goto err_unlock;
3261         }
3262
3263         req = embedded_payload(wrb);
3264
3265         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3266                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3267                                wrb, NULL);
3268
3269         req->src_port = port_num;
3270         req->dest_port = port_num;
3271         req->loopback_type = loopback_type;
3272         req->loopback_state = enable;
3273
3274         status = be_mcc_notify(adapter);
3275         if (status)
3276                 goto err_unlock;
3277
3278         mutex_unlock(&adapter->mcc_lock);
3279
3280         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3281                                          msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3282                 status = -ETIMEDOUT;
3283
3284         return status;
3285
3286 err_unlock:
3287         mutex_unlock(&adapter->mcc_lock);
3288         return status;
3289 }
3290
3291 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3292                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
3293                          u64 pattern)
3294 {
3295         struct be_mcc_wrb *wrb;
3296         struct be_cmd_req_loopback_test *req;
3297         struct be_cmd_resp_loopback_test *resp;
3298         int status;
3299
3300         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3301                             CMD_SUBSYSTEM_LOWLEVEL))
3302                 return -EPERM;
3303
3304         mutex_lock(&adapter->mcc_lock);
3305
3306         wrb = wrb_from_mccq(adapter);
3307         if (!wrb) {
3308                 status = -EBUSY;
3309                 goto err;
3310         }
3311
3312         req = embedded_payload(wrb);
3313
3314         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3315                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3316                                NULL);
3317
3318         req->hdr.timeout = cpu_to_le32(15);
3319         req->pattern = cpu_to_le64(pattern);
3320         req->src_port = cpu_to_le32(port_num);
3321         req->dest_port = cpu_to_le32(port_num);
3322         req->pkt_size = cpu_to_le32(pkt_size);
3323         req->num_pkts = cpu_to_le32(num_pkts);
3324         req->loopback_type = cpu_to_le32(loopback_type);
3325
3326         status = be_mcc_notify(adapter);
3327         if (status)
3328                 goto err;
3329
3330         mutex_unlock(&adapter->mcc_lock);
3331
3332         wait_for_completion(&adapter->et_cmd_compl);
3333         resp = embedded_payload(wrb);
3334         status = le32_to_cpu(resp->status);
3335
3336         return status;
3337 err:
3338         mutex_unlock(&adapter->mcc_lock);
3339         return status;
3340 }
3341
3342 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3343                         u32 byte_cnt, struct be_dma_mem *cmd)
3344 {
3345         struct be_mcc_wrb *wrb;
3346         struct be_cmd_req_ddrdma_test *req;
3347         int status;
3348         int i, j = 0;
3349
3350         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3351                             CMD_SUBSYSTEM_LOWLEVEL))
3352                 return -EPERM;
3353
3354         mutex_lock(&adapter->mcc_lock);
3355
3356         wrb = wrb_from_mccq(adapter);
3357         if (!wrb) {
3358                 status = -EBUSY;
3359                 goto err;
3360         }
3361         req = cmd->va;
3362         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3363                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3364                                cmd);
3365
3366         req->pattern = cpu_to_le64(pattern);
3367         req->byte_count = cpu_to_le32(byte_cnt);
3368         for (i = 0; i < byte_cnt; i++) {
3369                 req->snd_buff[i] = (u8)(pattern >> (j*8));
3370                 j++;
3371                 if (j > 7)
3372                         j = 0;
3373         }
3374
3375         status = be_mcc_notify_wait(adapter);
3376
3377         if (!status) {
3378                 struct be_cmd_resp_ddrdma_test *resp;
3379
3380                 resp = cmd->va;
3381                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3382                     resp->snd_err) {
3383                         status = -1;
3384                 }
3385         }
3386
3387 err:
3388         mutex_unlock(&adapter->mcc_lock);
3389         return status;
3390 }
3391
3392 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3393                             struct be_dma_mem *nonemb_cmd)
3394 {
3395         struct be_mcc_wrb *wrb;
3396         struct be_cmd_req_seeprom_read *req;
3397         int status;
3398
3399         mutex_lock(&adapter->mcc_lock);
3400
3401         wrb = wrb_from_mccq(adapter);
3402         if (!wrb) {
3403                 status = -EBUSY;
3404                 goto err;
3405         }
3406         req = nonemb_cmd->va;
3407
3408         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3409                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3410                                nonemb_cmd);
3411
3412         status = be_mcc_notify_wait(adapter);
3413
3414 err:
3415         mutex_unlock(&adapter->mcc_lock);
3416         return status;
3417 }
3418
3419 int be_cmd_get_phy_info(struct be_adapter *adapter)
3420 {
3421         struct be_mcc_wrb *wrb;
3422         struct be_cmd_req_get_phy_info *req;
3423         struct be_dma_mem cmd;
3424         int status;
3425
3426         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3427                             CMD_SUBSYSTEM_COMMON))
3428                 return -EPERM;
3429
3430         mutex_lock(&adapter->mcc_lock);
3431
3432         wrb = wrb_from_mccq(adapter);
3433         if (!wrb) {
3434                 status = -EBUSY;
3435                 goto err;
3436         }
3437         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3438         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3439                                     GFP_ATOMIC);
3440         if (!cmd.va) {
3441                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3442                 status = -ENOMEM;
3443                 goto err;
3444         }
3445
3446         req = cmd.va;
3447
3448         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3449                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3450                                wrb, &cmd);
3451
3452         status = be_mcc_notify_wait(adapter);
3453         if (!status) {
3454                 struct be_phy_info *resp_phy_info =
3455                                 cmd.va + sizeof(struct be_cmd_req_hdr);
3456
3457                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3458                 adapter->phy.interface_type =
3459                         le16_to_cpu(resp_phy_info->interface_type);
3460                 adapter->phy.auto_speeds_supported =
3461                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
3462                 adapter->phy.fixed_speeds_supported =
3463                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3464                 adapter->phy.misc_params =
3465                         le32_to_cpu(resp_phy_info->misc_params);
3466
3467                 if (BE2_chip(adapter)) {
3468                         adapter->phy.fixed_speeds_supported =
3469                                 BE_SUPPORTED_SPEED_10GBPS |
3470                                 BE_SUPPORTED_SPEED_1GBPS;
3471                 }
3472         }
3473         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3474 err:
3475         mutex_unlock(&adapter->mcc_lock);
3476         return status;
3477 }
3478
3479 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3480 {
3481         struct be_mcc_wrb *wrb;
3482         struct be_cmd_req_set_qos *req;
3483         int status;
3484
3485         mutex_lock(&adapter->mcc_lock);
3486
3487         wrb = wrb_from_mccq(adapter);
3488         if (!wrb) {
3489                 status = -EBUSY;
3490                 goto err;
3491         }
3492
3493         req = embedded_payload(wrb);
3494
3495         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3496                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3497
3498         req->hdr.domain = domain;
3499         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3500         req->max_bps_nic = cpu_to_le32(bps);
3501
3502         status = be_mcc_notify_wait(adapter);
3503
3504 err:
3505         mutex_unlock(&adapter->mcc_lock);
3506         return status;
3507 }
3508
3509 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3510 {
3511         struct be_mcc_wrb *wrb;
3512         struct be_cmd_req_cntl_attribs *req;
3513         struct be_cmd_resp_cntl_attribs *resp;
3514         int status, i;
3515         int payload_len = max(sizeof(*req), sizeof(*resp));
3516         struct mgmt_controller_attrib *attribs;
3517         struct be_dma_mem attribs_cmd;
3518         u32 *serial_num;
3519
3520         if (mutex_lock_interruptible(&adapter->mbox_lock))
3521                 return -1;
3522
3523         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3524         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3525         attribs_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
3526                                             attribs_cmd.size,
3527                                             &attribs_cmd.dma, GFP_ATOMIC);
3528         if (!attribs_cmd.va) {
3529                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3530                 status = -ENOMEM;
3531                 goto err;
3532         }
3533
3534         wrb = wrb_from_mbox(adapter);
3535         if (!wrb) {
3536                 status = -EBUSY;
3537                 goto err;
3538         }
3539         req = attribs_cmd.va;
3540
3541         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3542                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3543                                wrb, &attribs_cmd);
3544
3545         status = be_mbox_notify_wait(adapter);
3546         if (!status) {
3547                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3548                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3549                 serial_num = attribs->hba_attribs.controller_serial_number;
3550                 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3551                         adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3552                                 (BIT_MASK(16) - 1);
3553                 /* For BEx, since GET_FUNC_CONFIG command is not
3554                  * supported, we read funcnum here as a workaround.
3555                  */
3556                 if (BEx_chip(adapter))
3557                         adapter->pf_num = attribs->hba_attribs.pci_funcnum;
3558         }
3559
3560 err:
3561         mutex_unlock(&adapter->mbox_lock);
3562         if (attribs_cmd.va)
3563                 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3564                                   attribs_cmd.va, attribs_cmd.dma);
3565         return status;
3566 }
3567
3568 /* Uses mbox */
3569 int be_cmd_req_native_mode(struct be_adapter *adapter)
3570 {
3571         struct be_mcc_wrb *wrb;
3572         struct be_cmd_req_set_func_cap *req;
3573         int status;
3574
3575         if (mutex_lock_interruptible(&adapter->mbox_lock))
3576                 return -1;
3577
3578         wrb = wrb_from_mbox(adapter);
3579         if (!wrb) {
3580                 status = -EBUSY;
3581                 goto err;
3582         }
3583
3584         req = embedded_payload(wrb);
3585
3586         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3587                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3588                                sizeof(*req), wrb, NULL);
3589
3590         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3591                                 CAPABILITY_BE3_NATIVE_ERX_API);
3592         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3593
3594         status = be_mbox_notify_wait(adapter);
3595         if (!status) {
3596                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3597
3598                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3599                                         CAPABILITY_BE3_NATIVE_ERX_API;
3600                 if (!adapter->be3_native)
3601                         dev_warn(&adapter->pdev->dev,
3602                                  "adapter not in advanced mode\n");
3603         }
3604 err:
3605         mutex_unlock(&adapter->mbox_lock);
3606         return status;
3607 }
3608
3609 /* Get privilege(s) for a function */
3610 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3611                              u32 domain)
3612 {
3613         struct be_mcc_wrb *wrb;
3614         struct be_cmd_req_get_fn_privileges *req;
3615         int status;
3616
3617         mutex_lock(&adapter->mcc_lock);
3618
3619         wrb = wrb_from_mccq(adapter);
3620         if (!wrb) {
3621                 status = -EBUSY;
3622                 goto err;
3623         }
3624
3625         req = embedded_payload(wrb);
3626
3627         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3628                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3629                                wrb, NULL);
3630
3631         req->hdr.domain = domain;
3632
3633         status = be_mcc_notify_wait(adapter);
3634         if (!status) {
3635                 struct be_cmd_resp_get_fn_privileges *resp =
3636                                                 embedded_payload(wrb);
3637
3638                 *privilege = le32_to_cpu(resp->privilege_mask);
3639
3640                 /* In UMC mode FW does not return right privileges.
3641                  * Override with correct privilege equivalent to PF.
3642                  */
3643                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3644                     be_physfn(adapter))
3645                         *privilege = MAX_PRIVILEGES;
3646         }
3647
3648 err:
3649         mutex_unlock(&adapter->mcc_lock);
3650         return status;
3651 }
3652
3653 /* Set privilege(s) for a function */
3654 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3655                              u32 domain)
3656 {
3657         struct be_mcc_wrb *wrb;
3658         struct be_cmd_req_set_fn_privileges *req;
3659         int status;
3660
3661         mutex_lock(&adapter->mcc_lock);
3662
3663         wrb = wrb_from_mccq(adapter);
3664         if (!wrb) {
3665                 status = -EBUSY;
3666                 goto err;
3667         }
3668
3669         req = embedded_payload(wrb);
3670         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3671                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3672                                wrb, NULL);
3673         req->hdr.domain = domain;
3674         if (lancer_chip(adapter))
3675                 req->privileges_lancer = cpu_to_le32(privileges);
3676         else
3677                 req->privileges = cpu_to_le32(privileges);
3678
3679         status = be_mcc_notify_wait(adapter);
3680 err:
3681         mutex_unlock(&adapter->mcc_lock);
3682         return status;
3683 }
3684
3685 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3686  * pmac_id_valid: false => pmac_id or MAC address is requested.
3687  *                If pmac_id is returned, pmac_id_valid is returned as true
3688  */
3689 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3690                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3691                              u8 domain)
3692 {
3693         struct be_mcc_wrb *wrb;
3694         struct be_cmd_req_get_mac_list *req;
3695         int status;
3696         int mac_count;
3697         struct be_dma_mem get_mac_list_cmd;
3698         int i;
3699
3700         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3701         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3702         get_mac_list_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
3703                                                  get_mac_list_cmd.size,
3704                                                  &get_mac_list_cmd.dma,
3705                                                  GFP_ATOMIC);
3706
3707         if (!get_mac_list_cmd.va) {
3708                 dev_err(&adapter->pdev->dev,
3709                         "Memory allocation failure during GET_MAC_LIST\n");
3710                 return -ENOMEM;
3711         }
3712
3713         mutex_lock(&adapter->mcc_lock);
3714
3715         wrb = wrb_from_mccq(adapter);
3716         if (!wrb) {
3717                 status = -EBUSY;
3718                 goto out;
3719         }
3720
3721         req = get_mac_list_cmd.va;
3722
3723         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3724                                OPCODE_COMMON_GET_MAC_LIST,
3725                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3726         req->hdr.domain = domain;
3727         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3728         if (*pmac_id_valid) {
3729                 req->mac_id = cpu_to_le32(*pmac_id);
3730                 req->iface_id = cpu_to_le16(if_handle);
3731                 req->perm_override = 0;
3732         } else {
3733                 req->perm_override = 1;
3734         }
3735
3736         status = be_mcc_notify_wait(adapter);
3737         if (!status) {
3738                 struct be_cmd_resp_get_mac_list *resp =
3739                                                 get_mac_list_cmd.va;
3740
3741                 if (*pmac_id_valid) {
3742                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3743                                ETH_ALEN);
3744                         goto out;
3745                 }
3746
3747                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3748                 /* Mac list returned could contain one or more active mac_ids
3749                  * or one or more true or pseudo permanent mac addresses.
3750                  * If an active mac_id is present, return first active mac_id
3751                  * found.
3752                  */
3753                 for (i = 0; i < mac_count; i++) {
3754                         struct get_list_macaddr *mac_entry;
3755                         u16 mac_addr_size;
3756                         u32 mac_id;
3757
3758                         mac_entry = &resp->macaddr_list[i];
3759                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3760                         /* mac_id is a 32 bit value and mac_addr size
3761                          * is 6 bytes
3762                          */
3763                         if (mac_addr_size == sizeof(u32)) {
3764                                 *pmac_id_valid = true;
3765                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3766                                 *pmac_id = le32_to_cpu(mac_id);
3767                                 goto out;
3768                         }
3769                 }
3770                 /* If no active mac_id found, return first mac addr */
3771                 *pmac_id_valid = false;
3772                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3773                        ETH_ALEN);
3774         }
3775
3776 out:
3777         mutex_unlock(&adapter->mcc_lock);
3778         dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3779                           get_mac_list_cmd.va, get_mac_list_cmd.dma);
3780         return status;
3781 }
3782
3783 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3784                           u8 *mac, u32 if_handle, bool active, u32 domain)
3785 {
3786         if (!active)
3787                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3788                                          if_handle, domain);
3789         if (BEx_chip(adapter))
3790                 return be_cmd_mac_addr_query(adapter, mac, false,
3791                                              if_handle, curr_pmac_id);
3792         else
3793                 /* Fetch the MAC address using pmac_id */
3794                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3795                                                 &curr_pmac_id,
3796                                                 if_handle, domain);
3797 }
3798
3799 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3800 {
3801         int status;
3802         bool pmac_valid = false;
3803
3804         eth_zero_addr(mac);
3805
3806         if (BEx_chip(adapter)) {
3807                 if (be_physfn(adapter))
3808                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3809                                                        0);
3810                 else
3811                         status = be_cmd_mac_addr_query(adapter, mac, false,
3812                                                        adapter->if_handle, 0);
3813         } else {
3814                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3815                                                   NULL, adapter->if_handle, 0);
3816         }
3817
3818         return status;
3819 }
3820
3821 /* Uses synchronous MCCQ */
3822 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3823                         u8 mac_count, u32 domain)
3824 {
3825         struct be_mcc_wrb *wrb;
3826         struct be_cmd_req_set_mac_list *req;
3827         int status;
3828         struct be_dma_mem cmd;
3829
3830         memset(&cmd, 0, sizeof(struct be_dma_mem));
3831         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3832         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3833                                     GFP_KERNEL);
3834         if (!cmd.va)
3835                 return -ENOMEM;
3836
3837         mutex_lock(&adapter->mcc_lock);
3838
3839         wrb = wrb_from_mccq(adapter);
3840         if (!wrb) {
3841                 status = -EBUSY;
3842                 goto err;
3843         }
3844
3845         req = cmd.va;
3846         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3847                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3848                                wrb, &cmd);
3849
3850         req->hdr.domain = domain;
3851         req->mac_count = mac_count;
3852         if (mac_count)
3853                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3854
3855         status = be_mcc_notify_wait(adapter);
3856
3857 err:
3858         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3859         mutex_unlock(&adapter->mcc_lock);
3860         return status;
3861 }
3862
3863 /* Wrapper to delete any active MACs and provision the new mac.
3864  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3865  * current list are active.
3866  */
3867 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3868 {
3869         bool active_mac = false;
3870         u8 old_mac[ETH_ALEN];
3871         u32 pmac_id;
3872         int status;
3873
3874         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3875                                           &pmac_id, if_id, dom);
3876
3877         if (!status && active_mac)
3878                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3879
3880         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3881 }
3882
3883 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3884                           u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3885 {
3886         struct be_mcc_wrb *wrb;
3887         struct be_cmd_req_set_hsw_config *req;
3888         void *ctxt;
3889         int status;
3890
3891         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3892                             CMD_SUBSYSTEM_COMMON))
3893                 return -EPERM;
3894
3895         mutex_lock(&adapter->mcc_lock);
3896
3897         wrb = wrb_from_mccq(adapter);
3898         if (!wrb) {
3899                 status = -EBUSY;
3900                 goto err;
3901         }
3902
3903         req = embedded_payload(wrb);
3904         ctxt = &req->context;
3905
3906         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3907                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3908                                NULL);
3909
3910         req->hdr.domain = domain;
3911         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3912         if (pvid) {
3913                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3914                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3915         }
3916         if (hsw_mode) {
3917                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3918                               ctxt, adapter->hba_port_num);
3919                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3920                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3921                               ctxt, hsw_mode);
3922         }
3923
3924         /* Enable/disable both mac and vlan spoof checking */
3925         if (!BEx_chip(adapter) && spoofchk) {
3926                 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3927                               ctxt, spoofchk);
3928                 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3929                               ctxt, spoofchk);
3930         }
3931
3932         be_dws_cpu_to_le(req->context, sizeof(req->context));
3933         status = be_mcc_notify_wait(adapter);
3934
3935 err:
3936         mutex_unlock(&adapter->mcc_lock);
3937         return status;
3938 }
3939
3940 /* Get Hyper switch config */
3941 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3942                           u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3943 {
3944         struct be_mcc_wrb *wrb;
3945         struct be_cmd_req_get_hsw_config *req;
3946         void *ctxt;
3947         int status;
3948         u16 vid;
3949
3950         mutex_lock(&adapter->mcc_lock);
3951
3952         wrb = wrb_from_mccq(adapter);
3953         if (!wrb) {
3954                 status = -EBUSY;
3955                 goto err;
3956         }
3957
3958         req = embedded_payload(wrb);
3959         ctxt = &req->context;
3960
3961         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3962                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3963                                NULL);
3964
3965         req->hdr.domain = domain;
3966         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3967                       ctxt, intf_id);
3968         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3969
3970         if (!BEx_chip(adapter) && mode) {
3971                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3972                               ctxt, adapter->hba_port_num);
3973                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3974         }
3975         be_dws_cpu_to_le(req->context, sizeof(req->context));
3976
3977         status = be_mcc_notify_wait(adapter);
3978         if (!status) {
3979                 struct be_cmd_resp_get_hsw_config *resp =
3980                                                 embedded_payload(wrb);
3981
3982                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3983                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3984                                     pvid, &resp->context);
3985                 if (pvid)
3986                         *pvid = le16_to_cpu(vid);
3987                 if (mode)
3988                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3989                                               port_fwd_type, &resp->context);
3990                 if (spoofchk)
3991                         *spoofchk =
3992                                 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3993                                               spoofchk, &resp->context);
3994         }
3995
3996 err:
3997         mutex_unlock(&adapter->mcc_lock);
3998         return status;
3999 }
4000
4001 static bool be_is_wol_excluded(struct be_adapter *adapter)
4002 {
4003         struct pci_dev *pdev = adapter->pdev;
4004
4005         if (be_virtfn(adapter))
4006                 return true;
4007
4008         switch (pdev->subsystem_device) {
4009         case OC_SUBSYS_DEVICE_ID1:
4010         case OC_SUBSYS_DEVICE_ID2:
4011         case OC_SUBSYS_DEVICE_ID3:
4012         case OC_SUBSYS_DEVICE_ID4:
4013                 return true;
4014         default:
4015                 return false;
4016         }
4017 }
4018
4019 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
4020 {
4021         struct be_mcc_wrb *wrb;
4022         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
4023         int status = 0;
4024         struct be_dma_mem cmd;
4025
4026         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4027                             CMD_SUBSYSTEM_ETH))
4028                 return -EPERM;
4029
4030         if (be_is_wol_excluded(adapter))
4031                 return status;
4032
4033         if (mutex_lock_interruptible(&adapter->mbox_lock))
4034                 return -1;
4035
4036         memset(&cmd, 0, sizeof(struct be_dma_mem));
4037         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
4038         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4039                                     GFP_ATOMIC);
4040         if (!cmd.va) {
4041                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
4042                 status = -ENOMEM;
4043                 goto err;
4044         }
4045
4046         wrb = wrb_from_mbox(adapter);
4047         if (!wrb) {
4048                 status = -EBUSY;
4049                 goto err;
4050         }
4051
4052         req = cmd.va;
4053
4054         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4055                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4056                                sizeof(*req), wrb, &cmd);
4057
4058         req->hdr.version = 1;
4059         req->query_options = BE_GET_WOL_CAP;
4060
4061         status = be_mbox_notify_wait(adapter);
4062         if (!status) {
4063                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
4064
4065                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4066
4067                 adapter->wol_cap = resp->wol_settings;
4068
4069                 /* Non-zero macaddr indicates WOL is enabled */
4070                 if (adapter->wol_cap & BE_WOL_CAP &&
4071                     !is_zero_ether_addr(resp->magic_mac))
4072                         adapter->wol_en = true;
4073         }
4074 err:
4075         mutex_unlock(&adapter->mbox_lock);
4076         if (cmd.va)
4077                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4078                                   cmd.dma);
4079         return status;
4080
4081 }
4082
4083 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4084 {
4085         struct be_dma_mem extfat_cmd;
4086         struct be_fat_conf_params *cfgs;
4087         int status;
4088         int i, j;
4089
4090         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4091         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4092         extfat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
4093                                            extfat_cmd.size, &extfat_cmd.dma,
4094                                            GFP_ATOMIC);
4095         if (!extfat_cmd.va)
4096                 return -ENOMEM;
4097
4098         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4099         if (status)
4100                 goto err;
4101
4102         cfgs = (struct be_fat_conf_params *)
4103                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4104         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4105                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4106
4107                 for (j = 0; j < num_modes; j++) {
4108                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4109                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
4110                                                         cpu_to_le32(level);
4111                 }
4112         }
4113
4114         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4115 err:
4116         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4117                           extfat_cmd.dma);
4118         return status;
4119 }
4120
4121 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4122 {
4123         struct be_dma_mem extfat_cmd;
4124         struct be_fat_conf_params *cfgs;
4125         int status, j;
4126         int level = 0;
4127
4128         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4129         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4130         extfat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
4131                                            extfat_cmd.size, &extfat_cmd.dma,
4132                                            GFP_ATOMIC);
4133
4134         if (!extfat_cmd.va) {
4135                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4136                         __func__);
4137                 goto err;
4138         }
4139
4140         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4141         if (!status) {
4142                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4143                                                 sizeof(struct be_cmd_resp_hdr));
4144
4145                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4146                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4147                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4148                 }
4149         }
4150         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4151                           extfat_cmd.dma);
4152 err:
4153         return level;
4154 }
4155
4156 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4157                                    struct be_dma_mem *cmd)
4158 {
4159         struct be_mcc_wrb *wrb;
4160         struct be_cmd_req_get_ext_fat_caps *req;
4161         int status;
4162
4163         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4164                             CMD_SUBSYSTEM_COMMON))
4165                 return -EPERM;
4166
4167         if (mutex_lock_interruptible(&adapter->mbox_lock))
4168                 return -1;
4169
4170         wrb = wrb_from_mbox(adapter);
4171         if (!wrb) {
4172                 status = -EBUSY;
4173                 goto err;
4174         }
4175
4176         req = cmd->va;
4177         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4178                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4179                                cmd->size, wrb, cmd);
4180         req->parameter_type = cpu_to_le32(1);
4181
4182         status = be_mbox_notify_wait(adapter);
4183 err:
4184         mutex_unlock(&adapter->mbox_lock);
4185         return status;
4186 }
4187
4188 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4189                                    struct be_dma_mem *cmd,
4190                                    struct be_fat_conf_params *configs)
4191 {
4192         struct be_mcc_wrb *wrb;
4193         struct be_cmd_req_set_ext_fat_caps *req;
4194         int status;
4195
4196         mutex_lock(&adapter->mcc_lock);
4197
4198         wrb = wrb_from_mccq(adapter);
4199         if (!wrb) {
4200                 status = -EBUSY;
4201                 goto err;
4202         }
4203
4204         req = cmd->va;
4205         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4206         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4207                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES,
4208                                cmd->size, wrb, cmd);
4209
4210         status = be_mcc_notify_wait(adapter);
4211 err:
4212         mutex_unlock(&adapter->mcc_lock);
4213         return status;
4214 }
4215
4216 int be_cmd_query_port_name(struct be_adapter *adapter)
4217 {
4218         struct be_cmd_req_get_port_name *req;
4219         struct be_mcc_wrb *wrb;
4220         int status;
4221
4222         if (mutex_lock_interruptible(&adapter->mbox_lock))
4223                 return -1;
4224
4225         wrb = wrb_from_mbox(adapter);
4226         req = embedded_payload(wrb);
4227
4228         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4229                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4230                                NULL);
4231         if (!BEx_chip(adapter))
4232                 req->hdr.version = 1;
4233
4234         status = be_mbox_notify_wait(adapter);
4235         if (!status) {
4236                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4237
4238                 adapter->port_name = resp->port_name[adapter->hba_port_num];
4239         } else {
4240                 adapter->port_name = adapter->hba_port_num + '0';
4241         }
4242
4243         mutex_unlock(&adapter->mbox_lock);
4244         return status;
4245 }
4246
4247 /* When more than 1 NIC descriptor is present in the descriptor list,
4248  * the caller must specify the pf_num to obtain the NIC descriptor
4249  * corresponding to its pci function.
4250  * get_vft must be true when the caller wants the VF-template desc of the
4251  * PF-pool.
4252  * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4253  * that only it's NIC descriptor is present in the descriptor list.
4254  */
4255 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4256                                                bool get_vft, u8 pf_num)
4257 {
4258         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4259         struct be_nic_res_desc *nic;
4260         int i;
4261
4262         for (i = 0; i < desc_count; i++) {
4263                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4264                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4265                         nic = (struct be_nic_res_desc *)hdr;
4266
4267                         if ((pf_num == PF_NUM_IGNORE ||
4268                              nic->pf_num == pf_num) &&
4269                             (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4270                                 return nic;
4271                 }
4272                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4273                 hdr = (void *)hdr + hdr->desc_len;
4274         }
4275         return NULL;
4276 }
4277
4278 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4279                                                u8 pf_num)
4280 {
4281         return be_get_nic_desc(buf, desc_count, true, pf_num);
4282 }
4283
4284 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4285                                                     u8 pf_num)
4286 {
4287         return be_get_nic_desc(buf, desc_count, false, pf_num);
4288 }
4289
4290 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4291                                                  u8 pf_num)
4292 {
4293         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4294         struct be_pcie_res_desc *pcie;
4295         int i;
4296
4297         for (i = 0; i < desc_count; i++) {
4298                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4299                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4300                         pcie = (struct be_pcie_res_desc *)hdr;
4301                         if (pcie->pf_num == pf_num)
4302                                 return pcie;
4303                 }
4304
4305                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4306                 hdr = (void *)hdr + hdr->desc_len;
4307         }
4308         return NULL;
4309 }
4310
4311 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4312 {
4313         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4314         int i;
4315
4316         for (i = 0; i < desc_count; i++) {
4317                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4318                         return (struct be_port_res_desc *)hdr;
4319
4320                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4321                 hdr = (void *)hdr + hdr->desc_len;
4322         }
4323         return NULL;
4324 }
4325
4326 static void be_copy_nic_desc(struct be_resources *res,
4327                              struct be_nic_res_desc *desc)
4328 {
4329         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4330         res->max_vlans = le16_to_cpu(desc->vlan_count);
4331         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4332         res->max_tx_qs = le16_to_cpu(desc->txq_count);
4333         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4334         res->max_rx_qs = le16_to_cpu(desc->rq_count);
4335         res->max_evt_qs = le16_to_cpu(desc->eq_count);
4336         res->max_cq_count = le16_to_cpu(desc->cq_count);
4337         res->max_iface_count = le16_to_cpu(desc->iface_count);
4338         res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4339         /* Clear flags that driver is not interested in */
4340         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4341                                 BE_IF_CAP_FLAGS_WANT;
4342 }
4343
4344 /* Uses Mbox */
4345 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4346 {
4347         struct be_mcc_wrb *wrb;
4348         struct be_cmd_req_get_func_config *req;
4349         int status;
4350         struct be_dma_mem cmd;
4351
4352         if (mutex_lock_interruptible(&adapter->mbox_lock))
4353                 return -1;
4354
4355         memset(&cmd, 0, sizeof(struct be_dma_mem));
4356         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4357         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4358                                     GFP_ATOMIC);
4359         if (!cmd.va) {
4360                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4361                 status = -ENOMEM;
4362                 goto err;
4363         }
4364
4365         wrb = wrb_from_mbox(adapter);
4366         if (!wrb) {
4367                 status = -EBUSY;
4368                 goto err;
4369         }
4370
4371         req = cmd.va;
4372
4373         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4374                                OPCODE_COMMON_GET_FUNC_CONFIG,
4375                                cmd.size, wrb, &cmd);
4376
4377         if (skyhawk_chip(adapter))
4378                 req->hdr.version = 1;
4379
4380         status = be_mbox_notify_wait(adapter);
4381         if (!status) {
4382                 struct be_cmd_resp_get_func_config *resp = cmd.va;
4383                 u32 desc_count = le32_to_cpu(resp->desc_count);
4384                 struct be_nic_res_desc *desc;
4385
4386                 /* GET_FUNC_CONFIG returns resource descriptors of the
4387                  * current function only. So, pf_num should be set to
4388                  * PF_NUM_IGNORE.
4389                  */
4390                 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4391                                             PF_NUM_IGNORE);
4392                 if (!desc) {
4393                         status = -EINVAL;
4394                         goto err;
4395                 }
4396
4397                 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4398                 adapter->pf_num = desc->pf_num;
4399                 adapter->vf_num = desc->vf_num;
4400
4401                 if (res)
4402                         be_copy_nic_desc(res, desc);
4403         }
4404 err:
4405         mutex_unlock(&adapter->mbox_lock);
4406         if (cmd.va)
4407                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4408                                   cmd.dma);
4409         return status;
4410 }
4411
4412 /* This routine returns a list of all the NIC PF_nums in the adapter */
4413 static u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
4414 {
4415         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4416         struct be_pcie_res_desc *pcie = NULL;
4417         int i;
4418         u16 nic_pf_count = 0;
4419
4420         for (i = 0; i < desc_count; i++) {
4421                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4422                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4423                         pcie = (struct be_pcie_res_desc *)hdr;
4424                         if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4425                                                pcie->pf_type == MISSION_RDMA)) {
4426                                 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4427                         }
4428                 }
4429
4430                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4431                 hdr = (void *)hdr + hdr->desc_len;
4432         }
4433         return nic_pf_count;
4434 }
4435
4436 /* Will use MBOX only if MCCQ has not been created */
4437 int be_cmd_get_profile_config(struct be_adapter *adapter,
4438                               struct be_resources *res,
4439                               struct be_port_resources *port_res,
4440                               u8 profile_type, u8 query, u8 domain)
4441 {
4442         struct be_cmd_resp_get_profile_config *resp;
4443         struct be_cmd_req_get_profile_config *req;
4444         struct be_nic_res_desc *vf_res;
4445         struct be_pcie_res_desc *pcie;
4446         struct be_port_res_desc *port;
4447         struct be_nic_res_desc *nic;
4448         struct be_mcc_wrb wrb = {0};
4449         struct be_dma_mem cmd;
4450         u16 desc_count;
4451         int status;
4452
4453         memset(&cmd, 0, sizeof(struct be_dma_mem));
4454         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4455         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4456                                     GFP_ATOMIC);
4457         if (!cmd.va)
4458                 return -ENOMEM;
4459
4460         req = cmd.va;
4461         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4462                                OPCODE_COMMON_GET_PROFILE_CONFIG,
4463                                cmd.size, &wrb, &cmd);
4464
4465         if (!lancer_chip(adapter))
4466                 req->hdr.version = 1;
4467         req->type = profile_type;
4468         req->hdr.domain = domain;
4469
4470         /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4471          * descriptors with all bits set to "1" for the fields which can be
4472          * modified using SET_PROFILE_CONFIG cmd.
4473          */
4474         if (query == RESOURCE_MODIFIABLE)
4475                 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4476
4477         status = be_cmd_notify_wait(adapter, &wrb);
4478         if (status)
4479                 goto err;
4480
4481         resp = cmd.va;
4482         desc_count = le16_to_cpu(resp->desc_count);
4483
4484         if (port_res) {
4485                 u16 nic_pf_cnt = 0, i;
4486                 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4487
4488                 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4489                                                     desc_count,
4490                                                     nic_pf_num_list);
4491
4492                 for (i = 0; i < nic_pf_cnt; i++) {
4493                         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4494                                                    nic_pf_num_list[i]);
4495                         if (nic->link_param == adapter->port_num) {
4496                                 port_res->nic_pfs++;
4497                                 pcie = be_get_pcie_desc(resp->func_param,
4498                                                         desc_count,
4499                                                         nic_pf_num_list[i]);
4500                                 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4501                         }
4502                 }
4503                 goto err;
4504         }
4505
4506         pcie = be_get_pcie_desc(resp->func_param, desc_count,
4507                                 adapter->pf_num);
4508         if (pcie)
4509                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4510
4511         port = be_get_port_desc(resp->func_param, desc_count);
4512         if (port)
4513                 adapter->mc_type = port->mc_type;
4514
4515         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4516                                    adapter->pf_num);
4517         if (nic)
4518                 be_copy_nic_desc(res, nic);
4519
4520         vf_res = be_get_vft_desc(resp->func_param, desc_count,
4521                                  adapter->pf_num);
4522         if (vf_res)
4523                 res->vf_if_cap_flags = vf_res->cap_flags;
4524 err:
4525         if (cmd.va)
4526                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4527                                   cmd.dma);
4528         return status;
4529 }
4530
4531 /* Will use MBOX only if MCCQ has not been created */
4532 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4533                                      int size, int count, u8 version, u8 domain)
4534 {
4535         struct be_cmd_req_set_profile_config *req;
4536         struct be_mcc_wrb wrb = {0};
4537         struct be_dma_mem cmd;
4538         int status;
4539
4540         memset(&cmd, 0, sizeof(struct be_dma_mem));
4541         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4542         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4543                                     GFP_ATOMIC);
4544         if (!cmd.va)
4545                 return -ENOMEM;
4546
4547         req = cmd.va;
4548         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4549                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4550                                &wrb, &cmd);
4551         req->hdr.version = version;
4552         req->hdr.domain = domain;
4553         req->desc_count = cpu_to_le32(count);
4554         memcpy(req->desc, desc, size);
4555
4556         status = be_cmd_notify_wait(adapter, &wrb);
4557
4558         if (cmd.va)
4559                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4560                                   cmd.dma);
4561         return status;
4562 }
4563
4564 /* Mark all fields invalid */
4565 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4566 {
4567         memset(nic, 0, sizeof(*nic));
4568         nic->unicast_mac_count = 0xFFFF;
4569         nic->mcc_count = 0xFFFF;
4570         nic->vlan_count = 0xFFFF;
4571         nic->mcast_mac_count = 0xFFFF;
4572         nic->txq_count = 0xFFFF;
4573         nic->rq_count = 0xFFFF;
4574         nic->rssq_count = 0xFFFF;
4575         nic->lro_count = 0xFFFF;
4576         nic->cq_count = 0xFFFF;
4577         nic->toe_conn_count = 0xFFFF;
4578         nic->eq_count = 0xFFFF;
4579         nic->iface_count = 0xFFFF;
4580         nic->link_param = 0xFF;
4581         nic->channel_id_param = cpu_to_le16(0xF000);
4582         nic->acpi_params = 0xFF;
4583         nic->wol_param = 0x0F;
4584         nic->tunnel_iface_count = 0xFFFF;
4585         nic->direct_tenant_iface_count = 0xFFFF;
4586         nic->bw_min = 0xFFFFFFFF;
4587         nic->bw_max = 0xFFFFFFFF;
4588 }
4589
4590 /* Mark all fields invalid */
4591 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4592 {
4593         memset(pcie, 0, sizeof(*pcie));
4594         pcie->sriov_state = 0xFF;
4595         pcie->pf_state = 0xFF;
4596         pcie->pf_type = 0xFF;
4597         pcie->num_vfs = 0xFFFF;
4598 }
4599
4600 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4601                       u8 domain)
4602 {
4603         struct be_nic_res_desc nic_desc;
4604         u32 bw_percent;
4605         u16 version = 0;
4606
4607         if (BE3_chip(adapter))
4608                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4609
4610         be_reset_nic_desc(&nic_desc);
4611         nic_desc.pf_num = adapter->pf_num;
4612         nic_desc.vf_num = domain;
4613         nic_desc.bw_min = 0;
4614         if (lancer_chip(adapter)) {
4615                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4616                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4617                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4618                                         (1 << NOSV_SHIFT);
4619                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4620         } else {
4621                 version = 1;
4622                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4623                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4624                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4625                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4626                 nic_desc.bw_max = cpu_to_le32(bw_percent);
4627         }
4628
4629         return be_cmd_set_profile_config(adapter, &nic_desc,
4630                                          nic_desc.hdr.desc_len,
4631                                          1, version, domain);
4632 }
4633
4634 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4635                             struct be_resources pool_res, u16 num_vfs,
4636                             struct be_resources *vft_res)
4637 {
4638         struct {
4639                 struct be_pcie_res_desc pcie;
4640                 struct be_nic_res_desc nic_vft;
4641         } __packed desc;
4642
4643         /* PF PCIE descriptor */
4644         be_reset_pcie_desc(&desc.pcie);
4645         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4646         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4647         desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4648         desc.pcie.pf_num = adapter->pdev->devfn;
4649         desc.pcie.sriov_state = num_vfs ? 1 : 0;
4650         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4651
4652         /* VF NIC Template descriptor */
4653         be_reset_nic_desc(&desc.nic_vft);
4654         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4655         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4656         desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4657                              BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4658         desc.nic_vft.pf_num = adapter->pdev->devfn;
4659         desc.nic_vft.vf_num = 0;
4660         desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4661         desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4662         desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4663         desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4664         desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4665
4666         if (vft_res->max_uc_mac)
4667                 desc.nic_vft.unicast_mac_count =
4668                                         cpu_to_le16(vft_res->max_uc_mac);
4669         if (vft_res->max_vlans)
4670                 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4671         if (vft_res->max_iface_count)
4672                 desc.nic_vft.iface_count =
4673                                 cpu_to_le16(vft_res->max_iface_count);
4674         if (vft_res->max_mcc_count)
4675                 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
4676
4677         return be_cmd_set_profile_config(adapter, &desc,
4678                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4679 }
4680
4681 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4682 {
4683         struct be_mcc_wrb *wrb;
4684         struct be_cmd_req_manage_iface_filters *req;
4685         int status;
4686
4687         if (iface == 0xFFFFFFFF)
4688                 return -1;
4689
4690         mutex_lock(&adapter->mcc_lock);
4691
4692         wrb = wrb_from_mccq(adapter);
4693         if (!wrb) {
4694                 status = -EBUSY;
4695                 goto err;
4696         }
4697         req = embedded_payload(wrb);
4698
4699         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4700                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4701                                wrb, NULL);
4702         req->op = op;
4703         req->target_iface_id = cpu_to_le32(iface);
4704
4705         status = be_mcc_notify_wait(adapter);
4706 err:
4707         mutex_unlock(&adapter->mcc_lock);
4708         return status;
4709 }
4710
4711 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4712 {
4713         struct be_port_res_desc port_desc;
4714
4715         memset(&port_desc, 0, sizeof(port_desc));
4716         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4717         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4718         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4719         port_desc.link_num = adapter->hba_port_num;
4720         if (port) {
4721                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4722                                         (1 << RCVID_SHIFT);
4723                 port_desc.nv_port = swab16(port);
4724         } else {
4725                 port_desc.nv_flags = NV_TYPE_DISABLED;
4726                 port_desc.nv_port = 0;
4727         }
4728
4729         return be_cmd_set_profile_config(adapter, &port_desc,
4730                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4731 }
4732
4733 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4734                      int vf_num)
4735 {
4736         struct be_mcc_wrb *wrb;
4737         struct be_cmd_req_get_iface_list *req;
4738         struct be_cmd_resp_get_iface_list *resp;
4739         int status;
4740
4741         mutex_lock(&adapter->mcc_lock);
4742
4743         wrb = wrb_from_mccq(adapter);
4744         if (!wrb) {
4745                 status = -EBUSY;
4746                 goto err;
4747         }
4748         req = embedded_payload(wrb);
4749
4750         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4751                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4752                                wrb, NULL);
4753         req->hdr.domain = vf_num + 1;
4754
4755         status = be_mcc_notify_wait(adapter);
4756         if (!status) {
4757                 resp = (struct be_cmd_resp_get_iface_list *)req;
4758                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4759         }
4760
4761 err:
4762         mutex_unlock(&adapter->mcc_lock);
4763         return status;
4764 }
4765
4766 static int lancer_wait_idle(struct be_adapter *adapter)
4767 {
4768 #define SLIPORT_IDLE_TIMEOUT 30
4769         u32 reg_val;
4770         int status = 0, i;
4771
4772         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4773                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4774                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4775                         break;
4776
4777                 ssleep(1);
4778         }
4779
4780         if (i == SLIPORT_IDLE_TIMEOUT)
4781                 status = -1;
4782
4783         return status;
4784 }
4785
4786 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4787 {
4788         int status = 0;
4789
4790         status = lancer_wait_idle(adapter);
4791         if (status)
4792                 return status;
4793
4794         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4795
4796         return status;
4797 }
4798
4799 /* Routine to check whether dump image is present or not */
4800 bool dump_present(struct be_adapter *adapter)
4801 {
4802         u32 sliport_status = 0;
4803
4804         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4805         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4806 }
4807
4808 int lancer_initiate_dump(struct be_adapter *adapter)
4809 {
4810         struct device *dev = &adapter->pdev->dev;
4811         int status;
4812
4813         if (dump_present(adapter)) {
4814                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4815                 return -EEXIST;
4816         }
4817
4818         /* give firmware reset and diagnostic dump */
4819         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4820                                      PHYSDEV_CONTROL_DD_MASK);
4821         if (status < 0) {
4822                 dev_err(dev, "FW reset failed\n");
4823                 return status;
4824         }
4825
4826         status = lancer_wait_idle(adapter);
4827         if (status)
4828                 return status;
4829
4830         if (!dump_present(adapter)) {
4831                 dev_err(dev, "FW dump not generated\n");
4832                 return -EIO;
4833         }
4834
4835         return 0;
4836 }
4837
4838 int lancer_delete_dump(struct be_adapter *adapter)
4839 {
4840         int status;
4841
4842         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4843         return be_cmd_status(status);
4844 }
4845
4846 /* Uses sync mcc */
4847 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4848 {
4849         struct be_mcc_wrb *wrb;
4850         struct be_cmd_enable_disable_vf *req;
4851         int status;
4852
4853         if (BEx_chip(adapter))
4854                 return 0;
4855
4856         mutex_lock(&adapter->mcc_lock);
4857
4858         wrb = wrb_from_mccq(adapter);
4859         if (!wrb) {
4860                 status = -EBUSY;
4861                 goto err;
4862         }
4863
4864         req = embedded_payload(wrb);
4865
4866         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4867                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4868                                wrb, NULL);
4869
4870         req->hdr.domain = domain;
4871         req->enable = 1;
4872         status = be_mcc_notify_wait(adapter);
4873 err:
4874         mutex_unlock(&adapter->mcc_lock);
4875         return status;
4876 }
4877
4878 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4879 {
4880         struct be_mcc_wrb *wrb;
4881         struct be_cmd_req_intr_set *req;
4882         int status;
4883
4884         if (mutex_lock_interruptible(&adapter->mbox_lock))
4885                 return -1;
4886
4887         wrb = wrb_from_mbox(adapter);
4888
4889         req = embedded_payload(wrb);
4890
4891         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4892                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4893                                wrb, NULL);
4894
4895         req->intr_enabled = intr_enable;
4896
4897         status = be_mbox_notify_wait(adapter);
4898
4899         mutex_unlock(&adapter->mbox_lock);
4900         return status;
4901 }
4902
4903 /* Uses MBOX */
4904 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4905 {
4906         struct be_cmd_req_get_active_profile *req;
4907         struct be_mcc_wrb *wrb;
4908         int status;
4909
4910         if (mutex_lock_interruptible(&adapter->mbox_lock))
4911                 return -1;
4912
4913         wrb = wrb_from_mbox(adapter);
4914         if (!wrb) {
4915                 status = -EBUSY;
4916                 goto err;
4917         }
4918
4919         req = embedded_payload(wrb);
4920
4921         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4922                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4923                                wrb, NULL);
4924
4925         status = be_mbox_notify_wait(adapter);
4926         if (!status) {
4927                 struct be_cmd_resp_get_active_profile *resp =
4928                                                         embedded_payload(wrb);
4929
4930                 *profile_id = le16_to_cpu(resp->active_profile_id);
4931         }
4932
4933 err:
4934         mutex_unlock(&adapter->mbox_lock);
4935         return status;
4936 }
4937
4938 static int
4939 __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4940                                  int link_state, int version, u8 domain)
4941 {
4942         struct be_cmd_req_set_ll_link *req;
4943         struct be_mcc_wrb *wrb;
4944         u32 link_config = 0;
4945         int status;
4946
4947         mutex_lock(&adapter->mcc_lock);
4948
4949         wrb = wrb_from_mccq(adapter);
4950         if (!wrb) {
4951                 status = -EBUSY;
4952                 goto err;
4953         }
4954
4955         req = embedded_payload(wrb);
4956
4957         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4958                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4959                                sizeof(*req), wrb, NULL);
4960
4961         req->hdr.version = version;
4962         req->hdr.domain = domain;
4963
4964         if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4965             link_state == IFLA_VF_LINK_STATE_AUTO)
4966                 link_config |= PLINK_ENABLE;
4967
4968         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4969                 link_config |= PLINK_TRACK;
4970
4971         req->link_config = cpu_to_le32(link_config);
4972
4973         status = be_mcc_notify_wait(adapter);
4974 err:
4975         mutex_unlock(&adapter->mcc_lock);
4976         return status;
4977 }
4978
4979 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4980                                    int link_state, u8 domain)
4981 {
4982         int status;
4983
4984         if (BE2_chip(adapter))
4985                 return -EOPNOTSUPP;
4986
4987         status = __be_cmd_set_logical_link_config(adapter, link_state,
4988                                                   2, domain);
4989
4990         /* Version 2 of the command will not be recognized by older FW.
4991          * On such a failure issue version 1 of the command.
4992          */
4993         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4994                 status = __be_cmd_set_logical_link_config(adapter, link_state,
4995                                                           1, domain);
4996         return status;
4997 }
4998
4999 int be_cmd_set_features(struct be_adapter *adapter)
5000 {
5001         struct be_cmd_resp_set_features *resp;
5002         struct be_cmd_req_set_features *req;
5003         struct be_mcc_wrb *wrb;
5004         int status;
5005
5006         if (mutex_lock_interruptible(&adapter->mcc_lock))
5007                 return -1;
5008
5009         wrb = wrb_from_mccq(adapter);
5010         if (!wrb) {
5011                 status = -EBUSY;
5012                 goto err;
5013         }
5014
5015         req = embedded_payload(wrb);
5016
5017         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
5018                                OPCODE_COMMON_SET_FEATURES,
5019                                sizeof(*req), wrb, NULL);
5020
5021         req->features = cpu_to_le32(BE_FEATURE_UE_RECOVERY);
5022         req->parameter_len = cpu_to_le32(sizeof(struct be_req_ue_recovery));
5023         req->parameter.req.uer = cpu_to_le32(BE_UE_RECOVERY_UER_MASK);
5024
5025         status = be_mcc_notify_wait(adapter);
5026         if (status)
5027                 goto err;
5028
5029         resp = embedded_payload(wrb);
5030
5031         adapter->error_recovery.ue_to_poll_time =
5032                 le16_to_cpu(resp->parameter.resp.ue2rp);
5033         adapter->error_recovery.ue_to_reset_time =
5034                 le16_to_cpu(resp->parameter.resp.ue2sr);
5035         adapter->error_recovery.recovery_supported = true;
5036 err:
5037         /* Checking "MCC_STATUS_INVALID_LENGTH" for SKH as FW
5038          * returns this error in older firmware versions
5039          */
5040         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
5041             base_status(status) == MCC_STATUS_INVALID_LENGTH)
5042                 dev_info(&adapter->pdev->dev,
5043                          "Adapter does not support HW error recovery\n");
5044
5045         mutex_unlock(&adapter->mcc_lock);
5046         return status;
5047 }
5048
5049 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
5050                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
5051 {
5052         struct be_adapter *adapter = netdev_priv(netdev_handle);
5053         struct be_mcc_wrb *wrb;
5054         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
5055         struct be_cmd_req_hdr *req;
5056         struct be_cmd_resp_hdr *resp;
5057         int status;
5058
5059         mutex_lock(&adapter->mcc_lock);
5060
5061         wrb = wrb_from_mccq(adapter);
5062         if (!wrb) {
5063                 status = -EBUSY;
5064                 goto err;
5065         }
5066         req = embedded_payload(wrb);
5067         resp = embedded_payload(wrb);
5068
5069         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
5070                                hdr->opcode, wrb_payload_size, wrb, NULL);
5071         memcpy(req, wrb_payload, wrb_payload_size);
5072         be_dws_cpu_to_le(req, wrb_payload_size);
5073
5074         status = be_mcc_notify_wait(adapter);
5075         if (cmd_status)
5076                 *cmd_status = (status & 0xffff);
5077         if (ext_status)
5078                 *ext_status = 0;
5079         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
5080         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
5081 err:
5082         mutex_unlock(&adapter->mcc_lock);
5083         return status;
5084 }
5085 EXPORT_SYMBOL(be_roce_mcc_cmd);