2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/delay.h>
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
56 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
57 int polarity, int attempts, int delay, u32 *valp)
60 u32 val = t4_read_reg(adapter, reg);
62 if (!!(val & mask) == polarity) {
74 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
75 int polarity, int attempts, int delay)
77 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
88 * Sets a register field specified by the supplied mask to the
91 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
94 u32 v = t4_read_reg(adapter, addr) & ~mask;
96 t4_write_reg(adapter, addr, v | val);
97 (void) t4_read_reg(adapter, addr); /* flush */
101 * t4_read_indirect - read indirectly addressed registers
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
109 * Reads registers that are accessed indirectly through an address/data
112 static void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
113 unsigned int data_reg, u32 *vals,
114 unsigned int nregs, unsigned int start_idx)
117 t4_write_reg(adap, addr_reg, start_idx);
118 *vals++ = t4_read_reg(adap, data_reg);
124 * t4_write_indirect - write indirectly addressed registers
126 * @addr_reg: register holding the indirect addresses
127 * @data_reg: register holding the value for the indirect registers
128 * @vals: values to write
129 * @nregs: how many indirect registers to write
130 * @start_idx: address of first indirect register to write
132 * Writes a sequential block of registers that are accessed indirectly
133 * through an address/data register pair.
135 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
136 unsigned int data_reg, const u32 *vals,
137 unsigned int nregs, unsigned int start_idx)
140 t4_write_reg(adap, addr_reg, start_idx++);
141 t4_write_reg(adap, data_reg, *vals++);
146 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
148 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
151 for ( ; nflit; nflit--, mbox_addr += 8)
152 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
156 * Handle a FW assertion reported in a mailbox.
158 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
160 struct fw_debug_cmd asrt;
162 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
163 dev_alert(adap->pdev_dev,
164 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
165 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
166 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
169 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
171 dev_err(adap->pdev_dev,
172 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
173 (unsigned long long)t4_read_reg64(adap, data_reg),
174 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
175 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
176 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
177 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
178 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
179 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
180 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
184 * t4_wr_mbox_meat - send a command to FW through the given mailbox
186 * @mbox: index of the mailbox to use
187 * @cmd: the command to write
188 * @size: command length in bytes
189 * @rpl: where to optionally store the reply
190 * @sleep_ok: if true we may sleep while awaiting command completion
192 * Sends the given command to FW through the selected mailbox and waits
193 * for the FW to execute the command. If @rpl is not %NULL it is used to
194 * store the FW's reply to the command. The command and its optional
195 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
196 * to respond. @sleep_ok determines whether we may sleep while awaiting
197 * the response. If sleeping is allowed we use progressive backoff
200 * The return value is 0 on success or a negative errno on failure. A
201 * failure can happen either because we are not able to execute the
202 * command or FW executes it but signals an error. In the latter case
203 * the return value is the error code indicated by FW (negated).
205 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
206 void *rpl, bool sleep_ok)
208 static const int delay[] = {
209 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
214 int i, ms, delay_idx;
215 const __be64 *p = cmd;
216 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
217 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
219 if ((size & 15) || size > MBOX_LEN)
223 * If the device is off-line, as in EEH, commands will time out.
224 * Fail them early so we don't waste time waiting.
226 if (adap->pdev->error_state != pci_channel_io_normal)
229 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
230 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
231 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
233 if (v != MBOX_OWNER_DRV)
234 return v ? -EBUSY : -ETIMEDOUT;
236 for (i = 0; i < size; i += 8)
237 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
239 t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
240 t4_read_reg(adap, ctl_reg); /* flush write */
245 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
247 ms = delay[delay_idx]; /* last element may repeat */
248 if (delay_idx < ARRAY_SIZE(delay) - 1)
254 v = t4_read_reg(adap, ctl_reg);
255 if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
256 if (!(v & MBMSGVALID)) {
257 t4_write_reg(adap, ctl_reg, 0);
261 res = t4_read_reg64(adap, data_reg);
262 if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) {
263 fw_asrt(adap, data_reg);
264 res = FW_CMD_RETVAL(EIO);
266 get_mbox_rpl(adap, rpl, size / 8, data_reg);
268 if (FW_CMD_RETVAL_GET((int)res))
269 dump_mbox(adap, mbox, data_reg);
270 t4_write_reg(adap, ctl_reg, 0);
271 return -FW_CMD_RETVAL_GET((int)res);
275 dump_mbox(adap, mbox, data_reg);
276 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
277 *(const u8 *)cmd, mbox);
282 * t4_mc_read - read from MC through backdoor accesses
284 * @addr: address of first byte requested
285 * @data: 64 bytes of data containing the requested address
286 * @ecc: where to store the corresponding 64-bit ECC word
288 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
289 * that covers the requested address @addr. If @parity is not %NULL it
290 * is assigned the 64-bit ECC word for the read data.
292 int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc)
296 if (t4_read_reg(adap, MC_BIST_CMD) & START_BIST)
298 t4_write_reg(adap, MC_BIST_CMD_ADDR, addr & ~0x3fU);
299 t4_write_reg(adap, MC_BIST_CMD_LEN, 64);
300 t4_write_reg(adap, MC_BIST_DATA_PATTERN, 0xc);
301 t4_write_reg(adap, MC_BIST_CMD, BIST_OPCODE(1) | START_BIST |
303 i = t4_wait_op_done(adap, MC_BIST_CMD, START_BIST, 0, 10, 1);
307 #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
309 for (i = 15; i >= 0; i--)
310 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
312 *ecc = t4_read_reg64(adap, MC_DATA(16));
318 * t4_edc_read - read from EDC through backdoor accesses
320 * @idx: which EDC to access
321 * @addr: address of first byte requested
322 * @data: 64 bytes of data containing the requested address
323 * @ecc: where to store the corresponding 64-bit ECC word
325 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
326 * that covers the requested address @addr. If @parity is not %NULL it
327 * is assigned the 64-bit ECC word for the read data.
329 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
334 if (t4_read_reg(adap, EDC_BIST_CMD + idx) & START_BIST)
336 t4_write_reg(adap, EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU);
337 t4_write_reg(adap, EDC_BIST_CMD_LEN + idx, 64);
338 t4_write_reg(adap, EDC_BIST_DATA_PATTERN + idx, 0xc);
339 t4_write_reg(adap, EDC_BIST_CMD + idx,
340 BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
341 i = t4_wait_op_done(adap, EDC_BIST_CMD + idx, START_BIST, 0, 10, 1);
345 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
347 for (i = 15; i >= 0; i--)
348 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
350 *ecc = t4_read_reg64(adap, EDC_DATA(16));
356 * t4_mem_win_rw - read/write memory through PCIE memory window
358 * @addr: address of first byte requested
359 * @data: MEMWIN0_APERTURE bytes of data containing the requested address
360 * @dir: direction of transfer 1 => read, 0 => write
362 * Read/write MEMWIN0_APERTURE bytes of data from MC starting at a
363 * MEMWIN0_APERTURE-byte-aligned address that covers the requested
366 static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
371 * Setup offset into PCIE memory window. Address must be a
372 * MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to
373 * ensure that changes propagate before we attempt to use the new
376 t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
377 addr & ~(MEMWIN0_APERTURE - 1));
378 t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
380 /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
381 for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
383 *data++ = (__force __be32) t4_read_reg(adap,
386 t4_write_reg(adap, (MEMWIN0_BASE + i),
387 (__force u32) *data++);
394 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
396 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
397 * @addr: address within indicated memory type
398 * @len: amount of memory to transfer
399 * @buf: host memory buffer
400 * @dir: direction of transfer 1 => read, 0 => write
402 * Reads/writes an [almost] arbitrary memory region in the firmware: the
403 * firmware memory address, length and host buffer must be aligned on
404 * 32-bit boudaries. The memory is transferred as a raw byte sequence
405 * from/to the firmware's memory. If this memory contains data
406 * structures which contain multi-byte integers, it's the callers
407 * responsibility to perform appropriate byte order conversions.
409 static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
410 __be32 *buf, int dir)
412 u32 pos, start, end, offset, memoffset;
417 * Argument sanity checks ...
419 if ((addr & 0x3) || (len & 0x3))
422 data = vmalloc(MEMWIN0_APERTURE);
427 * Offset into the region of memory which is being accessed
432 memoffset = (mtype * (5 * 1024 * 1024));
434 /* Determine the PCIE_MEM_ACCESS_OFFSET */
435 addr = addr + memoffset;
438 * The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes
439 * at a time so we need to round down the start and round up the end.
440 * We'll start copying out of the first line at (addr - start) a word
443 start = addr & ~(MEMWIN0_APERTURE-1);
444 end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1);
445 offset = (addr - start)/sizeof(__be32);
447 for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) {
450 * If we're writing, copy the data from the caller's memory
455 * If we're doing a partial write, then we need to do
456 * a read-modify-write ...
458 if (offset || len < MEMWIN0_APERTURE) {
459 ret = t4_mem_win_rw(adap, pos, data, 1);
463 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
465 data[offset++] = *buf++;
466 len -= sizeof(__be32);
471 * Transfer a block of memory and bail if there's an error.
473 ret = t4_mem_win_rw(adap, pos, data, dir);
478 * If we're reading, copy the data into the caller's memory
482 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
484 *buf++ = data[offset++];
485 len -= sizeof(__be32);
493 int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
496 return t4_memory_rw(adap, mtype, addr, len, buf, 0);
499 #define EEPROM_STAT_ADDR 0x7bfc
504 * t4_seeprom_wp - enable/disable EEPROM write protection
505 * @adapter: the adapter
506 * @enable: whether to enable or disable write protection
508 * Enables or disables write protection on the serial EEPROM.
510 int t4_seeprom_wp(struct adapter *adapter, bool enable)
512 unsigned int v = enable ? 0xc : 0;
513 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
514 return ret < 0 ? ret : 0;
518 * get_vpd_params - read VPD parameters from VPD EEPROM
519 * @adapter: adapter to read
520 * @p: where to store the parameters
522 * Reads card parameters stored in VPD EEPROM.
524 int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
526 u32 cclk_param, cclk_val;
530 unsigned int vpdr_len, kw_offset, id_len;
532 vpd = vmalloc(VPD_LEN);
536 ret = pci_read_vpd(adapter->pdev, VPD_BASE, VPD_LEN, vpd);
540 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
541 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
546 id_len = pci_vpd_lrdt_size(vpd);
550 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
552 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
557 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
558 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
559 if (vpdr_len + kw_offset > VPD_LEN) {
560 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
565 #define FIND_VPD_KW(var, name) do { \
566 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
568 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
572 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
575 FIND_VPD_KW(i, "RV");
576 for (csum = 0; i >= 0; i--)
580 dev_err(adapter->pdev_dev,
581 "corrupted VPD EEPROM, actual csum %u\n", csum);
586 FIND_VPD_KW(ec, "EC");
587 FIND_VPD_KW(sn, "SN");
590 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
592 memcpy(p->ec, vpd + ec, EC_LEN);
594 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
595 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
599 * Ask firmware for the Core Clock since it knows how to translate the
600 * Reference Clock ('V2') VPD field into a Core Clock value ...
602 cclk_param = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
603 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
604 ret = t4_query_params(adapter, adapter->mbox, 0, 0,
605 1, &cclk_param, &cclk_val);
616 /* serial flash and firmware constants */
618 SF_ATTEMPTS = 10, /* max retries for SF operations */
620 /* flash command opcodes */
621 SF_PROG_PAGE = 2, /* program page */
622 SF_WR_DISABLE = 4, /* disable writes */
623 SF_RD_STATUS = 5, /* read status register */
624 SF_WR_ENABLE = 6, /* enable writes */
625 SF_RD_DATA_FAST = 0xb, /* read flash */
626 SF_RD_ID = 0x9f, /* read ID */
627 SF_ERASE_SECTOR = 0xd8, /* erase sector */
629 FW_MAX_SIZE = 512 * 1024,
633 * sf1_read - read data from the serial flash
634 * @adapter: the adapter
635 * @byte_cnt: number of bytes to read
636 * @cont: whether another operation will be chained
637 * @lock: whether to lock SF for PL access only
638 * @valp: where to store the read data
640 * Reads up to 4 bytes of data from the serial flash. The location of
641 * the read needs to be specified prior to calling this by issuing the
642 * appropriate commands to the serial flash.
644 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
649 if (!byte_cnt || byte_cnt > 4)
651 if (t4_read_reg(adapter, SF_OP) & BUSY)
653 cont = cont ? SF_CONT : 0;
654 lock = lock ? SF_LOCK : 0;
655 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
656 ret = t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5);
658 *valp = t4_read_reg(adapter, SF_DATA);
663 * sf1_write - write data to the serial flash
664 * @adapter: the adapter
665 * @byte_cnt: number of bytes to write
666 * @cont: whether another operation will be chained
667 * @lock: whether to lock SF for PL access only
668 * @val: value to write
670 * Writes up to 4 bytes of data to the serial flash. The location of
671 * the write needs to be specified prior to calling this by issuing the
672 * appropriate commands to the serial flash.
674 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
677 if (!byte_cnt || byte_cnt > 4)
679 if (t4_read_reg(adapter, SF_OP) & BUSY)
681 cont = cont ? SF_CONT : 0;
682 lock = lock ? SF_LOCK : 0;
683 t4_write_reg(adapter, SF_DATA, val);
684 t4_write_reg(adapter, SF_OP, lock |
685 cont | BYTECNT(byte_cnt - 1) | OP_WR);
686 return t4_wait_op_done(adapter, SF_OP, BUSY, 0, SF_ATTEMPTS, 5);
690 * flash_wait_op - wait for a flash operation to complete
691 * @adapter: the adapter
692 * @attempts: max number of polls of the status register
693 * @delay: delay between polls in ms
695 * Wait for a flash operation to complete by polling the status register.
697 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
703 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
704 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
716 * t4_read_flash - read words from serial flash
717 * @adapter: the adapter
718 * @addr: the start address for the read
719 * @nwords: how many 32-bit words to read
720 * @data: where to store the read data
721 * @byte_oriented: whether to store data as bytes or as words
723 * Read the specified number of 32-bit words from the serial flash.
724 * If @byte_oriented is set the read data is stored as a byte array
725 * (i.e., big-endian), otherwise as 32-bit words in the platform's
728 static int t4_read_flash(struct adapter *adapter, unsigned int addr,
729 unsigned int nwords, u32 *data, int byte_oriented)
733 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
736 addr = swab32(addr) | SF_RD_DATA_FAST;
738 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
739 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
742 for ( ; nwords; nwords--, data++) {
743 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
745 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
749 *data = (__force __u32) (htonl(*data));
755 * t4_write_flash - write up to a page of data to the serial flash
756 * @adapter: the adapter
757 * @addr: the start address to write
758 * @n: length of data to write in bytes
759 * @data: the data to write
761 * Writes up to a page of data (256 bytes) to the serial flash starting
762 * at the given address. All the data must be written to the same page.
764 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
765 unsigned int n, const u8 *data)
769 unsigned int i, c, left, val, offset = addr & 0xff;
771 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
774 val = swab32(addr) | SF_PROG_PAGE;
776 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
777 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
780 for (left = n; left; left -= c) {
782 for (val = 0, i = 0; i < c; ++i)
783 val = (val << 8) + *data++;
785 ret = sf1_write(adapter, c, c != left, 1, val);
789 ret = flash_wait_op(adapter, 8, 1);
793 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
795 /* Read the page to verify the write succeeded */
796 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
800 if (memcmp(data - n, (u8 *)buf + offset, n)) {
801 dev_err(adapter->pdev_dev,
802 "failed to correctly write the flash page at %#x\n",
809 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
814 * get_fw_version - read the firmware version
815 * @adapter: the adapter
816 * @vers: where to place the version
818 * Reads the FW version from flash.
820 static int get_fw_version(struct adapter *adapter, u32 *vers)
822 return t4_read_flash(adapter, adapter->params.sf_fw_start +
823 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
827 * get_tp_version - read the TP microcode version
828 * @adapter: the adapter
829 * @vers: where to place the version
831 * Reads the TP microcode version from flash.
833 static int get_tp_version(struct adapter *adapter, u32 *vers)
835 return t4_read_flash(adapter, adapter->params.sf_fw_start +
836 offsetof(struct fw_hdr, tp_microcode_ver),
841 * t4_check_fw_version - check if the FW is compatible with this driver
842 * @adapter: the adapter
844 * Checks if an adapter's FW is compatible with the driver. Returns 0
845 * if there's exact match, a negative error if the version could not be
846 * read or there's a major version mismatch, and a positive value if the
847 * expected major version is found but there's a minor version mismatch.
849 int t4_check_fw_version(struct adapter *adapter)
852 int ret, major, minor, micro;
854 ret = get_fw_version(adapter, &adapter->params.fw_vers);
856 ret = get_tp_version(adapter, &adapter->params.tp_vers);
858 ret = t4_read_flash(adapter, adapter->params.sf_fw_start +
859 offsetof(struct fw_hdr, intfver_nic),
864 major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers);
865 minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers);
866 micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers);
867 memcpy(adapter->params.api_vers, api_vers,
868 sizeof(adapter->params.api_vers));
870 if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */
871 dev_err(adapter->pdev_dev,
872 "card FW has major version %u, driver wants %u\n",
873 major, FW_VERSION_MAJOR);
877 if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO)
878 return 0; /* perfect match */
880 /* Minor/micro version mismatch. Report it but often it's OK. */
885 * t4_flash_erase_sectors - erase a range of flash sectors
886 * @adapter: the adapter
887 * @start: the first sector to erase
888 * @end: the last sector to erase
890 * Erases the sectors in the given inclusive range.
892 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
896 while (start <= end) {
897 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
898 (ret = sf1_write(adapter, 4, 0, 1,
899 SF_ERASE_SECTOR | (start << 8))) != 0 ||
900 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
901 dev_err(adapter->pdev_dev,
902 "erase of flash sector %d failed, error %d\n",
908 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
913 * t4_flash_cfg_addr - return the address of the flash configuration file
914 * @adapter: the adapter
916 * Return the address within the flash where the Firmware Configuration
919 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
921 if (adapter->params.sf_size == 0x100000)
922 return FLASH_FPGA_CFG_START;
924 return FLASH_CFG_START;
928 * t4_load_cfg - download config file
930 * @cfg_data: the cfg text file to write
931 * @size: text file size
933 * Write the supplied config text file to the card's serial flash.
935 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
939 unsigned int flash_cfg_start_sec;
940 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
942 addr = t4_flash_cfg_addr(adap);
943 flash_cfg_start_sec = addr / SF_SEC_SIZE;
945 if (size > FLASH_CFG_MAX_SIZE) {
946 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
951 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
953 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
954 flash_cfg_start_sec + i - 1);
956 * If size == 0 then we're simply erasing the FLASH sectors associated
957 * with the on-adapter Firmware Configuration File.
959 if (ret || size == 0)
962 /* this will write to the flash up to SF_PAGE_SIZE at a time */
963 for (i = 0; i < size; i += SF_PAGE_SIZE) {
964 if ((size - i) < SF_PAGE_SIZE)
968 ret = t4_write_flash(adap, addr, n, cfg_data);
972 addr += SF_PAGE_SIZE;
973 cfg_data += SF_PAGE_SIZE;
978 dev_err(adap->pdev_dev, "config file %s failed %d\n",
979 (size == 0 ? "clear" : "download"), ret);
984 * t4_load_fw - download firmware
986 * @fw_data: the firmware image to write
989 * Write the supplied firmware image to the card's serial flash.
991 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
996 u8 first_page[SF_PAGE_SIZE];
997 const __be32 *p = (const __be32 *)fw_data;
998 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
999 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1000 unsigned int fw_img_start = adap->params.sf_fw_start;
1001 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
1004 dev_err(adap->pdev_dev, "FW image has no data\n");
1008 dev_err(adap->pdev_dev,
1009 "FW image size not multiple of 512 bytes\n");
1012 if (ntohs(hdr->len512) * 512 != size) {
1013 dev_err(adap->pdev_dev,
1014 "FW image size differs from size in FW header\n");
1017 if (size > FW_MAX_SIZE) {
1018 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
1023 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1024 csum += ntohl(p[i]);
1026 if (csum != 0xffffffff) {
1027 dev_err(adap->pdev_dev,
1028 "corrupted firmware image, checksum %#x\n", csum);
1032 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
1033 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
1038 * We write the correct version at the end so the driver can see a bad
1039 * version if the FW write fails. Start by writing a copy of the
1040 * first page with a bad version.
1042 memcpy(first_page, fw_data, SF_PAGE_SIZE);
1043 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
1044 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
1048 addr = fw_img_start;
1049 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
1050 addr += SF_PAGE_SIZE;
1051 fw_data += SF_PAGE_SIZE;
1052 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
1057 ret = t4_write_flash(adap,
1058 fw_img_start + offsetof(struct fw_hdr, fw_ver),
1059 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
1062 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
1067 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1068 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG)
1071 * t4_link_start - apply link configuration to MAC/PHY
1072 * @phy: the PHY to setup
1073 * @mac: the MAC to setup
1074 * @lc: the requested link configuration
1076 * Set up a port's MAC and PHY according to a desired link configuration.
1077 * - If the PHY can auto-negotiate first decide what to advertise, then
1078 * enable/disable auto-negotiation as desired, and reset.
1079 * - If the PHY does not auto-negotiate just reset it.
1080 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1081 * otherwise do it later based on the outcome of auto-negotiation.
1083 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1084 struct link_config *lc)
1086 struct fw_port_cmd c;
1087 unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
1090 if (lc->requested_fc & PAUSE_RX)
1091 fc |= FW_PORT_CAP_FC_RX;
1092 if (lc->requested_fc & PAUSE_TX)
1093 fc |= FW_PORT_CAP_FC_TX;
1095 memset(&c, 0, sizeof(c));
1096 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1097 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1098 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1101 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1102 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
1103 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1104 } else if (lc->autoneg == AUTONEG_DISABLE) {
1105 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
1106 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1108 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
1110 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1114 * t4_restart_aneg - restart autonegotiation
1115 * @adap: the adapter
1116 * @mbox: mbox to use for the FW command
1117 * @port: the port id
1119 * Restarts autonegotiation for the selected port.
1121 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
1123 struct fw_port_cmd c;
1125 memset(&c, 0, sizeof(c));
1126 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1127 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1128 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1130 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
1131 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1134 typedef void (*int_handler_t)(struct adapter *adap);
1137 unsigned int mask; /* bits to check in interrupt status */
1138 const char *msg; /* message to print or NULL */
1139 short stat_idx; /* stat counter to increment or -1 */
1140 unsigned short fatal; /* whether the condition reported is fatal */
1141 int_handler_t int_handler; /* platform-specific int handler */
1145 * t4_handle_intr_status - table driven interrupt handler
1146 * @adapter: the adapter that generated the interrupt
1147 * @reg: the interrupt status register to process
1148 * @acts: table of interrupt actions
1150 * A table driven interrupt handler that applies a set of masks to an
1151 * interrupt status word and performs the corresponding actions if the
1152 * interrupts described by the mask have occurred. The actions include
1153 * optionally emitting a warning or alert message. The table is terminated
1154 * by an entry specifying mask 0. Returns the number of fatal interrupt
1157 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
1158 const struct intr_info *acts)
1161 unsigned int mask = 0;
1162 unsigned int status = t4_read_reg(adapter, reg);
1164 for ( ; acts->mask; ++acts) {
1165 if (!(status & acts->mask))
1169 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1170 status & acts->mask);
1171 } else if (acts->msg && printk_ratelimit())
1172 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1173 status & acts->mask);
1174 if (acts->int_handler)
1175 acts->int_handler(adapter);
1179 if (status) /* clear processed interrupts */
1180 t4_write_reg(adapter, reg, status);
1185 * Interrupt handler for the PCIE module.
1187 static void pcie_intr_handler(struct adapter *adapter)
1189 static const struct intr_info sysbus_intr_info[] = {
1190 { RNPP, "RXNP array parity error", -1, 1 },
1191 { RPCP, "RXPC array parity error", -1, 1 },
1192 { RCIP, "RXCIF array parity error", -1, 1 },
1193 { RCCP, "Rx completions control array parity error", -1, 1 },
1194 { RFTP, "RXFT array parity error", -1, 1 },
1197 static const struct intr_info pcie_port_intr_info[] = {
1198 { TPCP, "TXPC array parity error", -1, 1 },
1199 { TNPP, "TXNP array parity error", -1, 1 },
1200 { TFTP, "TXFT array parity error", -1, 1 },
1201 { TCAP, "TXCA array parity error", -1, 1 },
1202 { TCIP, "TXCIF array parity error", -1, 1 },
1203 { RCAP, "RXCA array parity error", -1, 1 },
1204 { OTDD, "outbound request TLP discarded", -1, 1 },
1205 { RDPE, "Rx data parity error", -1, 1 },
1206 { TDUE, "Tx uncorrectable data error", -1, 1 },
1209 static const struct intr_info pcie_intr_info[] = {
1210 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
1211 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
1212 { MSIDATAPERR, "MSI data parity error", -1, 1 },
1213 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1214 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1215 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1216 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1217 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
1218 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
1219 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1220 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
1221 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1222 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1223 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
1224 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1225 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1226 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
1227 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1228 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1229 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1230 { FIDPERR, "PCI FID parity error", -1, 1 },
1231 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
1232 { MATAGPERR, "PCI MA tag parity error", -1, 1 },
1233 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1234 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
1235 { RXWRPERR, "PCI Rx write parity error", -1, 1 },
1236 { RPLPERR, "PCI replay buffer parity error", -1, 1 },
1237 { PCIESINT, "PCI core secondary fault", -1, 1 },
1238 { PCIEPINT, "PCI core primary fault", -1, 1 },
1239 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
1245 fat = t4_handle_intr_status(adapter,
1246 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
1248 t4_handle_intr_status(adapter,
1249 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
1250 pcie_port_intr_info) +
1251 t4_handle_intr_status(adapter, PCIE_INT_CAUSE, pcie_intr_info);
1253 t4_fatal_err(adapter);
1257 * TP interrupt handler.
1259 static void tp_intr_handler(struct adapter *adapter)
1261 static const struct intr_info tp_intr_info[] = {
1262 { 0x3fffffff, "TP parity error", -1, 1 },
1263 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1267 if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
1268 t4_fatal_err(adapter);
1272 * SGE interrupt handler.
1274 static void sge_intr_handler(struct adapter *adapter)
1278 static const struct intr_info sge_intr_info[] = {
1279 { ERR_CPL_EXCEED_IQE_SIZE,
1280 "SGE received CPL exceeding IQE size", -1, 1 },
1281 { ERR_INVALID_CIDX_INC,
1282 "SGE GTS CIDX increment too large", -1, 0 },
1283 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
1284 { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
1285 { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
1286 { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
1287 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
1288 "SGE IQID > 1023 received CPL for FL", -1, 0 },
1289 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
1291 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
1293 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
1295 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
1297 { ERR_ING_CTXT_PRIO,
1298 "SGE too many priority ingress contexts", -1, 0 },
1299 { ERR_EGR_CTXT_PRIO,
1300 "SGE too many priority egress contexts", -1, 0 },
1301 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
1302 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
1306 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
1307 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
1309 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
1310 (unsigned long long)v);
1311 t4_write_reg(adapter, SGE_INT_CAUSE1, v);
1312 t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
1315 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
1317 t4_fatal_err(adapter);
1321 * CIM interrupt handler.
1323 static void cim_intr_handler(struct adapter *adapter)
1325 static const struct intr_info cim_intr_info[] = {
1326 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
1327 { OBQPARERR, "CIM OBQ parity error", -1, 1 },
1328 { IBQPARERR, "CIM IBQ parity error", -1, 1 },
1329 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
1330 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
1331 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
1332 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
1335 static const struct intr_info cim_upintr_info[] = {
1336 { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
1337 { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
1338 { ILLWRINT, "CIM illegal write", -1, 1 },
1339 { ILLRDINT, "CIM illegal read", -1, 1 },
1340 { ILLRDBEINT, "CIM illegal read BE", -1, 1 },
1341 { ILLWRBEINT, "CIM illegal write BE", -1, 1 },
1342 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
1343 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
1344 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
1345 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
1346 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1347 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1348 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
1349 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
1350 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
1351 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
1352 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
1353 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
1354 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
1355 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
1356 { SGLRDPLINT , "CIM single read from PL space", -1, 1 },
1357 { SGLWRPLINT , "CIM single write to PL space", -1, 1 },
1358 { BLKRDPLINT , "CIM block read from PL space", -1, 1 },
1359 { BLKWRPLINT , "CIM block write to PL space", -1, 1 },
1360 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
1361 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
1362 { TIMEOUTINT , "CIM PIF timeout", -1, 1 },
1363 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
1369 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
1371 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
1374 t4_fatal_err(adapter);
1378 * ULP RX interrupt handler.
1380 static void ulprx_intr_handler(struct adapter *adapter)
1382 static const struct intr_info ulprx_intr_info[] = {
1383 { 0x1800000, "ULPRX context error", -1, 1 },
1384 { 0x7fffff, "ULPRX parity error", -1, 1 },
1388 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
1389 t4_fatal_err(adapter);
1393 * ULP TX interrupt handler.
1395 static void ulptx_intr_handler(struct adapter *adapter)
1397 static const struct intr_info ulptx_intr_info[] = {
1398 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
1400 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
1402 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
1404 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
1406 { 0xfffffff, "ULPTX parity error", -1, 1 },
1410 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
1411 t4_fatal_err(adapter);
1415 * PM TX interrupt handler.
1417 static void pmtx_intr_handler(struct adapter *adapter)
1419 static const struct intr_info pmtx_intr_info[] = {
1420 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
1421 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
1422 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
1423 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
1424 { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
1425 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
1426 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
1427 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
1428 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
1432 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
1433 t4_fatal_err(adapter);
1437 * PM RX interrupt handler.
1439 static void pmrx_intr_handler(struct adapter *adapter)
1441 static const struct intr_info pmrx_intr_info[] = {
1442 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
1443 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
1444 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
1445 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
1446 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
1447 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
1451 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
1452 t4_fatal_err(adapter);
1456 * CPL switch interrupt handler.
1458 static void cplsw_intr_handler(struct adapter *adapter)
1460 static const struct intr_info cplsw_intr_info[] = {
1461 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
1462 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
1463 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
1464 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
1465 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
1466 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
1470 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
1471 t4_fatal_err(adapter);
1475 * LE interrupt handler.
1477 static void le_intr_handler(struct adapter *adap)
1479 static const struct intr_info le_intr_info[] = {
1480 { LIPMISS, "LE LIP miss", -1, 0 },
1481 { LIP0, "LE 0 LIP error", -1, 0 },
1482 { PARITYERR, "LE parity error", -1, 1 },
1483 { UNKNOWNCMD, "LE unknown command", -1, 1 },
1484 { REQQPARERR, "LE request queue parity error", -1, 1 },
1488 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
1493 * MPS interrupt handler.
1495 static void mps_intr_handler(struct adapter *adapter)
1497 static const struct intr_info mps_rx_intr_info[] = {
1498 { 0xffffff, "MPS Rx parity error", -1, 1 },
1501 static const struct intr_info mps_tx_intr_info[] = {
1502 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
1503 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1504 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
1505 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
1506 { BUBBLE, "MPS Tx underflow", -1, 1 },
1507 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
1508 { FRMERR, "MPS Tx framing error", -1, 1 },
1511 static const struct intr_info mps_trc_intr_info[] = {
1512 { FILTMEM, "MPS TRC filter parity error", -1, 1 },
1513 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
1514 { MISCPERR, "MPS TRC misc parity error", -1, 1 },
1517 static const struct intr_info mps_stat_sram_intr_info[] = {
1518 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1521 static const struct intr_info mps_stat_tx_intr_info[] = {
1522 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1525 static const struct intr_info mps_stat_rx_intr_info[] = {
1526 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1529 static const struct intr_info mps_cls_intr_info[] = {
1530 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
1531 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
1532 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
1538 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
1540 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
1542 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
1543 mps_trc_intr_info) +
1544 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
1545 mps_stat_sram_intr_info) +
1546 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
1547 mps_stat_tx_intr_info) +
1548 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
1549 mps_stat_rx_intr_info) +
1550 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
1553 t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
1554 RXINT | TXINT | STATINT);
1555 t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
1557 t4_fatal_err(adapter);
1560 #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
1563 * EDC/MC interrupt handler.
1565 static void mem_intr_handler(struct adapter *adapter, int idx)
1567 static const char name[3][5] = { "EDC0", "EDC1", "MC" };
1569 unsigned int addr, cnt_addr, v;
1571 if (idx <= MEM_EDC1) {
1572 addr = EDC_REG(EDC_INT_CAUSE, idx);
1573 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
1575 addr = MC_INT_CAUSE;
1576 cnt_addr = MC_ECC_STATUS;
1579 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
1580 if (v & PERR_INT_CAUSE)
1581 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
1583 if (v & ECC_CE_INT_CAUSE) {
1584 u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
1586 t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
1587 if (printk_ratelimit())
1588 dev_warn(adapter->pdev_dev,
1589 "%u %s correctable ECC data error%s\n",
1590 cnt, name[idx], cnt > 1 ? "s" : "");
1592 if (v & ECC_UE_INT_CAUSE)
1593 dev_alert(adapter->pdev_dev,
1594 "%s uncorrectable ECC data error\n", name[idx]);
1596 t4_write_reg(adapter, addr, v);
1597 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
1598 t4_fatal_err(adapter);
1602 * MA interrupt handler.
1604 static void ma_intr_handler(struct adapter *adap)
1606 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
1608 if (status & MEM_PERR_INT_CAUSE)
1609 dev_alert(adap->pdev_dev,
1610 "MA parity error, parity status %#x\n",
1611 t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
1612 if (status & MEM_WRAP_INT_CAUSE) {
1613 v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
1614 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
1615 "client %u to address %#x\n",
1616 MEM_WRAP_CLIENT_NUM_GET(v),
1617 MEM_WRAP_ADDRESS_GET(v) << 4);
1619 t4_write_reg(adap, MA_INT_CAUSE, status);
1624 * SMB interrupt handler.
1626 static void smb_intr_handler(struct adapter *adap)
1628 static const struct intr_info smb_intr_info[] = {
1629 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
1630 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
1631 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
1635 if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
1640 * NC-SI interrupt handler.
1642 static void ncsi_intr_handler(struct adapter *adap)
1644 static const struct intr_info ncsi_intr_info[] = {
1645 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
1646 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
1647 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
1648 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
1652 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
1657 * XGMAC interrupt handler.
1659 static void xgmac_intr_handler(struct adapter *adap, int port)
1661 u32 v = t4_read_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE));
1663 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
1667 if (v & TXFIFO_PRTY_ERR)
1668 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1670 if (v & RXFIFO_PRTY_ERR)
1671 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1673 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
1678 * PL interrupt handler.
1680 static void pl_intr_handler(struct adapter *adap)
1682 static const struct intr_info pl_intr_info[] = {
1683 { FATALPERR, "T4 fatal parity error", -1, 1 },
1684 { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
1688 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
1692 #define PF_INTR_MASK (PFSW)
1693 #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
1694 EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
1695 CPL_SWITCH | SGE | ULP_TX)
1698 * t4_slow_intr_handler - control path interrupt handler
1699 * @adapter: the adapter
1701 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1702 * The designation 'slow' is because it involves register reads, while
1703 * data interrupts typically don't involve any MMIOs.
1705 int t4_slow_intr_handler(struct adapter *adapter)
1707 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
1709 if (!(cause & GLBL_INTR_MASK))
1712 cim_intr_handler(adapter);
1714 mps_intr_handler(adapter);
1716 ncsi_intr_handler(adapter);
1718 pl_intr_handler(adapter);
1720 smb_intr_handler(adapter);
1722 xgmac_intr_handler(adapter, 0);
1724 xgmac_intr_handler(adapter, 1);
1725 if (cause & XGMAC_KR0)
1726 xgmac_intr_handler(adapter, 2);
1727 if (cause & XGMAC_KR1)
1728 xgmac_intr_handler(adapter, 3);
1730 pcie_intr_handler(adapter);
1732 mem_intr_handler(adapter, MEM_MC);
1734 mem_intr_handler(adapter, MEM_EDC0);
1736 mem_intr_handler(adapter, MEM_EDC1);
1738 le_intr_handler(adapter);
1740 tp_intr_handler(adapter);
1742 ma_intr_handler(adapter);
1744 pmtx_intr_handler(adapter);
1746 pmrx_intr_handler(adapter);
1748 ulprx_intr_handler(adapter);
1749 if (cause & CPL_SWITCH)
1750 cplsw_intr_handler(adapter);
1752 sge_intr_handler(adapter);
1754 ulptx_intr_handler(adapter);
1756 /* Clear the interrupts just processed for which we are the master. */
1757 t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
1758 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
1763 * t4_intr_enable - enable interrupts
1764 * @adapter: the adapter whose interrupts should be enabled
1766 * Enable PF-specific interrupts for the calling function and the top-level
1767 * interrupt concentrator for global interrupts. Interrupts are already
1768 * enabled at each module, here we just enable the roots of the interrupt
1771 * Note: this function should be called only when the driver manages
1772 * non PF-specific interrupts from the various HW modules. Only one PCI
1773 * function at a time should be doing this.
1775 void t4_intr_enable(struct adapter *adapter)
1777 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1779 t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
1780 ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
1781 ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
1782 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
1783 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
1784 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
1785 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
1786 DBFIFO_HP_INT | DBFIFO_LP_INT |
1788 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
1789 t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
1793 * t4_intr_disable - disable interrupts
1794 * @adapter: the adapter whose interrupts should be disabled
1796 * Disable interrupts. We only disable the top-level interrupt
1797 * concentrators. The caller must be a PCI function managing global
1800 void t4_intr_disable(struct adapter *adapter)
1802 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1804 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
1805 t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
1809 * hash_mac_addr - return the hash value of a MAC address
1810 * @addr: the 48-bit Ethernet MAC address
1812 * Hashes a MAC address according to the hash function used by HW inexact
1813 * (hash) address matching.
1815 static int hash_mac_addr(const u8 *addr)
1817 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1818 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1826 * t4_config_rss_range - configure a portion of the RSS mapping table
1827 * @adapter: the adapter
1828 * @mbox: mbox to use for the FW command
1829 * @viid: virtual interface whose RSS subtable is to be written
1830 * @start: start entry in the table to write
1831 * @n: how many table entries to write
1832 * @rspq: values for the response queue lookup table
1833 * @nrspq: number of values in @rspq
1835 * Programs the selected part of the VI's RSS mapping table with the
1836 * provided values. If @nrspq < @n the supplied values are used repeatedly
1837 * until the full table range is populated.
1839 * The caller must ensure the values in @rspq are in the range allowed for
1842 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1843 int start, int n, const u16 *rspq, unsigned int nrspq)
1846 const u16 *rsp = rspq;
1847 const u16 *rsp_end = rspq + nrspq;
1848 struct fw_rss_ind_tbl_cmd cmd;
1850 memset(&cmd, 0, sizeof(cmd));
1851 cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1852 FW_CMD_REQUEST | FW_CMD_WRITE |
1853 FW_RSS_IND_TBL_CMD_VIID(viid));
1854 cmd.retval_len16 = htonl(FW_LEN16(cmd));
1856 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
1858 int nq = min(n, 32);
1859 __be32 *qp = &cmd.iq0_to_iq2;
1861 cmd.niqid = htons(nq);
1862 cmd.startidx = htons(start);
1870 v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
1871 if (++rsp >= rsp_end)
1873 v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
1874 if (++rsp >= rsp_end)
1876 v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
1877 if (++rsp >= rsp_end)
1884 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
1892 * t4_config_glbl_rss - configure the global RSS mode
1893 * @adapter: the adapter
1894 * @mbox: mbox to use for the FW command
1895 * @mode: global RSS mode
1896 * @flags: mode-specific flags
1898 * Sets the global RSS mode.
1900 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1903 struct fw_rss_glb_config_cmd c;
1905 memset(&c, 0, sizeof(c));
1906 c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
1907 FW_CMD_REQUEST | FW_CMD_WRITE);
1908 c.retval_len16 = htonl(FW_LEN16(c));
1909 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
1910 c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
1911 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
1912 c.u.basicvirtual.mode_pkd =
1913 htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
1914 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
1917 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
1921 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
1922 * @adap: the adapter
1923 * @v4: holds the TCP/IP counter values
1924 * @v6: holds the TCP/IPv6 counter values
1926 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
1927 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
1929 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1930 struct tp_tcp_stats *v6)
1932 u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
1934 #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
1935 #define STAT(x) val[STAT_IDX(x)]
1936 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
1939 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
1940 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
1941 v4->tcpOutRsts = STAT(OUT_RST);
1942 v4->tcpInSegs = STAT64(IN_SEG);
1943 v4->tcpOutSegs = STAT64(OUT_SEG);
1944 v4->tcpRetransSegs = STAT64(RXT_SEG);
1947 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
1948 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
1949 v6->tcpOutRsts = STAT(OUT_RST);
1950 v6->tcpInSegs = STAT64(IN_SEG);
1951 v6->tcpOutSegs = STAT64(OUT_SEG);
1952 v6->tcpRetransSegs = STAT64(RXT_SEG);
1960 * t4_read_mtu_tbl - returns the values in the HW path MTU table
1961 * @adap: the adapter
1962 * @mtus: where to store the MTU values
1963 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
1965 * Reads the HW path MTU table.
1967 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
1972 for (i = 0; i < NMTUS; ++i) {
1973 t4_write_reg(adap, TP_MTU_TABLE,
1974 MTUINDEX(0xff) | MTUVALUE(i));
1975 v = t4_read_reg(adap, TP_MTU_TABLE);
1976 mtus[i] = MTUVALUE_GET(v);
1978 mtu_log[i] = MTUWIDTH_GET(v);
1983 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
1984 * @adap: the adapter
1985 * @addr: the indirect TP register address
1986 * @mask: specifies the field within the register to modify
1987 * @val: new value for the field
1989 * Sets a field of an indirect TP register to the given value.
1991 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1992 unsigned int mask, unsigned int val)
1994 t4_write_reg(adap, TP_PIO_ADDR, addr);
1995 val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask;
1996 t4_write_reg(adap, TP_PIO_DATA, val);
2000 * init_cong_ctrl - initialize congestion control parameters
2001 * @a: the alpha values for congestion control
2002 * @b: the beta values for congestion control
2004 * Initialize the congestion control parameters.
2006 static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b)
2008 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2033 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2036 b[13] = b[14] = b[15] = b[16] = 3;
2037 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2038 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2043 /* The minimum additive increment value for the congestion control table */
2044 #define CC_MIN_INCR 2U
2047 * t4_load_mtus - write the MTU and congestion control HW tables
2048 * @adap: the adapter
2049 * @mtus: the values for the MTU table
2050 * @alpha: the values for the congestion control alpha parameter
2051 * @beta: the values for the congestion control beta parameter
2053 * Write the HW MTU table with the supplied MTUs and the high-speed
2054 * congestion control table with the supplied alpha, beta, and MTUs.
2055 * We write the two tables together because the additive increments
2056 * depend on the MTUs.
2058 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2059 const unsigned short *alpha, const unsigned short *beta)
2061 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2062 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2063 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2064 28672, 40960, 57344, 81920, 114688, 163840, 229376
2069 for (i = 0; i < NMTUS; ++i) {
2070 unsigned int mtu = mtus[i];
2071 unsigned int log2 = fls(mtu);
2073 if (!(mtu & ((1 << log2) >> 2))) /* round */
2075 t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
2076 MTUWIDTH(log2) | MTUVALUE(mtu));
2078 for (w = 0; w < NCCTRL_WIN; ++w) {
2081 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2084 t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
2085 (w << 16) | (beta[w] << 13) | inc);
2091 * get_mps_bg_map - return the buffer groups associated with a port
2092 * @adap: the adapter
2093 * @idx: the port index
2095 * Returns a bitmap indicating which MPS buffer groups are associated
2096 * with the given port. Bit i is set if buffer group i is used by the
2099 static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2101 u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
2104 return idx == 0 ? 0xf : 0;
2106 return idx < 2 ? (3 << (2 * idx)) : 0;
2111 * t4_get_port_stats - collect port statistics
2112 * @adap: the adapter
2113 * @idx: the port index
2114 * @p: the stats structure to fill
2116 * Collect statistics related to the given port from HW.
2118 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2120 u32 bgmap = get_mps_bg_map(adap, idx);
2122 #define GET_STAT(name) \
2123 t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_##name##_L))
2124 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2126 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2127 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2128 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2129 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2130 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2131 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2132 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2133 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2134 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2135 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2136 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2137 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2138 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2139 p->tx_drop = GET_STAT(TX_PORT_DROP);
2140 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2141 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2142 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2143 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2144 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2145 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2146 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2147 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2148 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2150 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2151 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2152 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2153 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2154 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2155 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2156 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2157 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2158 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2159 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2160 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2161 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2162 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2163 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2164 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2165 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2166 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2167 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2168 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2169 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2170 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2171 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2172 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2173 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2174 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2175 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2176 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2178 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2179 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2180 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2181 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2182 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2183 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2184 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2185 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2192 * t4_wol_magic_enable - enable/disable magic packet WoL
2193 * @adap: the adapter
2194 * @port: the physical port index
2195 * @addr: MAC address expected in magic packets, %NULL to disable
2197 * Enables/disables magic packet wake-on-LAN for the selected port.
2199 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2203 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO),
2204 (addr[2] << 24) | (addr[3] << 16) |
2205 (addr[4] << 8) | addr[5]);
2206 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI),
2207 (addr[0] << 8) | addr[1]);
2209 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), MAGICEN,
2210 addr ? MAGICEN : 0);
2214 * t4_wol_pat_enable - enable/disable pattern-based WoL
2215 * @adap: the adapter
2216 * @port: the physical port index
2217 * @map: bitmap of which HW pattern filters to set
2218 * @mask0: byte mask for bytes 0-63 of a packet
2219 * @mask1: byte mask for bytes 64-127 of a packet
2220 * @crc: Ethernet CRC for selected bytes
2221 * @enable: enable/disable switch
2223 * Sets the pattern filters indicated in @map to mask out the bytes
2224 * specified in @mask0/@mask1 in received packets and compare the CRC of
2225 * the resulting packet against @crc. If @enable is %true pattern-based
2226 * WoL is enabled, otherwise disabled.
2228 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2229 u64 mask0, u64 mask1, unsigned int crc, bool enable)
2234 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2),
2241 #define EPIO_REG(name) PORT_REG(port, XGMAC_PORT_EPIO_##name)
2243 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2244 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
2245 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
2247 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
2251 /* write byte masks */
2252 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2253 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
2254 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2255 if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY)
2259 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2260 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
2261 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2262 if (t4_read_reg(adap, EPIO_REG(OP)) & BUSY)
2267 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
2271 #define INIT_CMD(var, cmd, rd_wr) do { \
2272 (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \
2273 FW_CMD_REQUEST | FW_CMD_##rd_wr); \
2274 (var).retval_len16 = htonl(FW_LEN16(var)); \
2277 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2280 struct fw_ldst_cmd c;
2282 memset(&c, 0, sizeof(c));
2283 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2285 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE));
2286 c.cycles_to_len16 = htonl(FW_LEN16(c));
2287 c.u.addrval.addr = htonl(addr);
2288 c.u.addrval.val = htonl(val);
2290 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2294 * t4_mem_win_read_len - read memory through PCIE memory window
2295 * @adap: the adapter
2296 * @addr: address of first byte requested aligned on 32b.
2297 * @data: len bytes to hold the data read
2298 * @len: amount of data to read from window. Must be <=
2299 * MEMWIN0_APERATURE after adjusting for 16B alignment
2300 * requirements of the the memory window.
2302 * Read len bytes of data from MC starting at @addr.
2304 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
2310 * Align on a 16B boundary.
2313 if ((addr & 3) || (len + off) > MEMWIN0_APERTURE)
2316 t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, addr & ~15);
2317 t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
2319 for (i = 0; i < len; i += 4)
2320 *data++ = (__force __be32) t4_read_reg(adap,
2321 (MEMWIN0_BASE + off + i));
2327 * t4_mdio_rd - read a PHY register through MDIO
2328 * @adap: the adapter
2329 * @mbox: mailbox to use for the FW command
2330 * @phy_addr: the PHY address
2331 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2332 * @reg: the register to read
2333 * @valp: where to store the value
2335 * Issues a FW command through the given mailbox to read a PHY register.
2337 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2338 unsigned int mmd, unsigned int reg, u16 *valp)
2341 struct fw_ldst_cmd c;
2343 memset(&c, 0, sizeof(c));
2344 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2345 FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2346 c.cycles_to_len16 = htonl(FW_LEN16(c));
2347 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2348 FW_LDST_CMD_MMD(mmd));
2349 c.u.mdio.raddr = htons(reg);
2351 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2353 *valp = ntohs(c.u.mdio.rval);
2358 * t4_mdio_wr - write a PHY register through MDIO
2359 * @adap: the adapter
2360 * @mbox: mailbox to use for the FW command
2361 * @phy_addr: the PHY address
2362 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2363 * @reg: the register to write
2364 * @valp: value to write
2366 * Issues a FW command through the given mailbox to write a PHY register.
2368 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2369 unsigned int mmd, unsigned int reg, u16 val)
2371 struct fw_ldst_cmd c;
2373 memset(&c, 0, sizeof(c));
2374 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2375 FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2376 c.cycles_to_len16 = htonl(FW_LEN16(c));
2377 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2378 FW_LDST_CMD_MMD(mmd));
2379 c.u.mdio.raddr = htons(reg);
2380 c.u.mdio.rval = htons(val);
2382 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2386 * t4_fw_hello - establish communication with FW
2387 * @adap: the adapter
2388 * @mbox: mailbox to use for the FW command
2389 * @evt_mbox: mailbox to receive async FW events
2390 * @master: specifies the caller's willingness to be the device master
2391 * @state: returns the current device state (if non-NULL)
2393 * Issues a command to establish communication with FW. Returns either
2394 * an error (negative integer) or the mailbox of the Master PF.
2396 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2397 enum dev_master master, enum dev_state *state)
2400 struct fw_hello_cmd c;
2402 unsigned int master_mbox;
2403 int retries = FW_CMD_HELLO_RETRIES;
2406 memset(&c, 0, sizeof(c));
2407 INIT_CMD(c, HELLO, WRITE);
2408 c.err_to_mbasyncnot = htonl(
2409 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2410 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2411 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2412 FW_HELLO_CMD_MBMASTER_MASK) |
2413 FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2414 FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
2415 FW_HELLO_CMD_CLEARINIT);
2418 * Issue the HELLO command to the firmware. If it's not successful
2419 * but indicates that we got a "busy" or "timeout" condition, retry
2420 * the HELLO until we exhaust our retry limit.
2422 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2424 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2429 v = ntohl(c.err_to_mbasyncnot);
2430 master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
2432 if (v & FW_HELLO_CMD_ERR)
2433 *state = DEV_STATE_ERR;
2434 else if (v & FW_HELLO_CMD_INIT)
2435 *state = DEV_STATE_INIT;
2437 *state = DEV_STATE_UNINIT;
2441 * If we're not the Master PF then we need to wait around for the
2442 * Master PF Driver to finish setting up the adapter.
2444 * Note that we also do this wait if we're a non-Master-capable PF and
2445 * there is no current Master PF; a Master PF may show up momentarily
2446 * and we wouldn't want to fail pointlessly. (This can happen when an
2447 * OS loads lots of different drivers rapidly at the same time). In
2448 * this case, the Master PF returned by the firmware will be
2449 * FW_PCIE_FW_MASTER_MASK so the test below will work ...
2451 if ((v & (FW_HELLO_CMD_ERR|FW_HELLO_CMD_INIT)) == 0 &&
2452 master_mbox != mbox) {
2453 int waiting = FW_CMD_HELLO_TIMEOUT;
2456 * Wait for the firmware to either indicate an error or
2457 * initialized state. If we see either of these we bail out
2458 * and report the issue to the caller. If we exhaust the
2459 * "hello timeout" and we haven't exhausted our retries, try
2460 * again. Otherwise bail with a timeout error.
2469 * If neither Error nor Initialialized are indicated
2470 * by the firmware keep waiting till we exaust our
2471 * timeout ... and then retry if we haven't exhausted
2474 pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
2475 if (!(pcie_fw & (FW_PCIE_FW_ERR|FW_PCIE_FW_INIT))) {
2486 * We either have an Error or Initialized condition
2487 * report errors preferentially.
2490 if (pcie_fw & FW_PCIE_FW_ERR)
2491 *state = DEV_STATE_ERR;
2492 else if (pcie_fw & FW_PCIE_FW_INIT)
2493 *state = DEV_STATE_INIT;
2497 * If we arrived before a Master PF was selected and
2498 * there's not a valid Master PF, grab its identity
2501 if (master_mbox == FW_PCIE_FW_MASTER_MASK &&
2502 (pcie_fw & FW_PCIE_FW_MASTER_VLD))
2503 master_mbox = FW_PCIE_FW_MASTER_GET(pcie_fw);
2512 * t4_fw_bye - end communication with FW
2513 * @adap: the adapter
2514 * @mbox: mailbox to use for the FW command
2516 * Issues a command to terminate communication with FW.
2518 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2520 struct fw_bye_cmd c;
2522 memset(&c, 0, sizeof(c));
2523 INIT_CMD(c, BYE, WRITE);
2524 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2528 * t4_init_cmd - ask FW to initialize the device
2529 * @adap: the adapter
2530 * @mbox: mailbox to use for the FW command
2532 * Issues a command to FW to partially initialize the device. This
2533 * performs initialization that generally doesn't depend on user input.
2535 int t4_early_init(struct adapter *adap, unsigned int mbox)
2537 struct fw_initialize_cmd c;
2539 memset(&c, 0, sizeof(c));
2540 INIT_CMD(c, INITIALIZE, WRITE);
2541 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2545 * t4_fw_reset - issue a reset to FW
2546 * @adap: the adapter
2547 * @mbox: mailbox to use for the FW command
2548 * @reset: specifies the type of reset to perform
2550 * Issues a reset command of the specified type to FW.
2552 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2554 struct fw_reset_cmd c;
2556 memset(&c, 0, sizeof(c));
2557 INIT_CMD(c, RESET, WRITE);
2558 c.val = htonl(reset);
2559 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2563 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2564 * @adap: the adapter
2565 * @mbox: mailbox to use for the FW RESET command (if desired)
2566 * @force: force uP into RESET even if FW RESET command fails
2568 * Issues a RESET command to firmware (if desired) with a HALT indication
2569 * and then puts the microprocessor into RESET state. The RESET command
2570 * will only be issued if a legitimate mailbox is provided (mbox <=
2571 * FW_PCIE_FW_MASTER_MASK).
2573 * This is generally used in order for the host to safely manipulate the
2574 * adapter without fear of conflicting with whatever the firmware might
2575 * be doing. The only way out of this state is to RESTART the firmware
2578 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2583 * If a legitimate mailbox is provided, issue a RESET command
2584 * with a HALT indication.
2586 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2587 struct fw_reset_cmd c;
2589 memset(&c, 0, sizeof(c));
2590 INIT_CMD(c, RESET, WRITE);
2591 c.val = htonl(PIORST | PIORSTMODE);
2592 c.halt_pkd = htonl(FW_RESET_CMD_HALT(1U));
2593 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2597 * Normally we won't complete the operation if the firmware RESET
2598 * command fails but if our caller insists we'll go ahead and put the
2599 * uP into RESET. This can be useful if the firmware is hung or even
2600 * missing ... We'll have to take the risk of putting the uP into
2601 * RESET without the cooperation of firmware in that case.
2603 * We also force the firmware's HALT flag to be on in case we bypassed
2604 * the firmware RESET command above or we're dealing with old firmware
2605 * which doesn't have the HALT capability. This will serve as a flag
2606 * for the incoming firmware to know that it's coming out of a HALT
2607 * rather than a RESET ... if it's new enough to understand that ...
2609 if (ret == 0 || force) {
2610 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
2611 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT,
2616 * And we always return the result of the firmware RESET command
2617 * even when we force the uP into RESET ...
2623 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2624 * @adap: the adapter
2625 * @reset: if we want to do a RESET to restart things
2627 * Restart firmware previously halted by t4_fw_halt(). On successful
2628 * return the previous PF Master remains as the new PF Master and there
2629 * is no need to issue a new HELLO command, etc.
2631 * We do this in two ways:
2633 * 1. If we're dealing with newer firmware we'll simply want to take
2634 * the chip's microprocessor out of RESET. This will cause the
2635 * firmware to start up from its start vector. And then we'll loop
2636 * until the firmware indicates it's started again (PCIE_FW.HALT
2637 * reset to 0) or we timeout.
2639 * 2. If we're dealing with older firmware then we'll need to RESET
2640 * the chip since older firmware won't recognize the PCIE_FW.HALT
2641 * flag and automatically RESET itself on startup.
2643 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2647 * Since we're directing the RESET instead of the firmware
2648 * doing it automatically, we need to clear the PCIE_FW.HALT
2651 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT, 0);
2654 * If we've been given a valid mailbox, first try to get the
2655 * firmware to do the RESET. If that works, great and we can
2656 * return success. Otherwise, if we haven't been given a
2657 * valid mailbox or the RESET command failed, fall back to
2658 * hitting the chip with a hammer.
2660 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2661 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
2663 if (t4_fw_reset(adap, mbox,
2664 PIORST | PIORSTMODE) == 0)
2668 t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE);
2673 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
2674 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2675 if (!(t4_read_reg(adap, PCIE_FW) & FW_PCIE_FW_HALT))
2686 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
2687 * @adap: the adapter
2688 * @mbox: mailbox to use for the FW RESET command (if desired)
2689 * @fw_data: the firmware image to write
2691 * @force: force upgrade even if firmware doesn't cooperate
2693 * Perform all of the steps necessary for upgrading an adapter's
2694 * firmware image. Normally this requires the cooperation of the
2695 * existing firmware in order to halt all existing activities
2696 * but if an invalid mailbox token is passed in we skip that step
2697 * (though we'll still put the adapter microprocessor into RESET in
2700 * On successful return the new firmware will have been loaded and
2701 * the adapter will have been fully RESET losing all previous setup
2702 * state. On unsuccessful return the adapter may be completely hosed ...
2703 * positive errno indicates that the adapter is ~probably~ intact, a
2704 * negative errno indicates that things are looking bad ...
2706 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
2707 const u8 *fw_data, unsigned int size, int force)
2709 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
2712 ret = t4_fw_halt(adap, mbox, force);
2713 if (ret < 0 && !force)
2716 ret = t4_load_fw(adap, fw_data, size);
2721 * Older versions of the firmware don't understand the new
2722 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
2723 * restart. So for newly loaded older firmware we'll have to do the
2724 * RESET for it so it starts up on a clean slate. We can tell if
2725 * the newly loaded firmware will handle this right by checking
2726 * its header flags to see if it advertises the capability.
2728 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
2729 return t4_fw_restart(adap, mbox, reset);
2734 * t4_fw_config_file - setup an adapter via a Configuration File
2735 * @adap: the adapter
2736 * @mbox: mailbox to use for the FW command
2737 * @mtype: the memory type where the Configuration File is located
2738 * @maddr: the memory address where the Configuration File is located
2739 * @finiver: return value for CF [fini] version
2740 * @finicsum: return value for CF [fini] checksum
2741 * @cfcsum: return value for CF computed checksum
2743 * Issue a command to get the firmware to process the Configuration
2744 * File located at the specified mtype/maddress. If the Configuration
2745 * File is processed successfully and return value pointers are
2746 * provided, the Configuration File "[fini] section version and
2747 * checksum values will be returned along with the computed checksum.
2748 * It's up to the caller to decide how it wants to respond to the
2749 * checksums not matching but it recommended that a prominant warning
2750 * be emitted in order to help people rapidly identify changed or
2751 * corrupted Configuration Files.
2753 * Also note that it's possible to modify things like "niccaps",
2754 * "toecaps",etc. between processing the Configuration File and telling
2755 * the firmware to use the new configuration. Callers which want to
2756 * do this will need to "hand-roll" their own CAPS_CONFIGS commands for
2757 * Configuration Files if they want to do this.
2759 int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
2760 unsigned int mtype, unsigned int maddr,
2761 u32 *finiver, u32 *finicsum, u32 *cfcsum)
2763 struct fw_caps_config_cmd caps_cmd;
2767 * Tell the firmware to process the indicated Configuration File.
2768 * If there are no errors and the caller has provided return value
2769 * pointers for the [fini] section version, checksum and computed
2770 * checksum, pass those back to the caller.
2772 memset(&caps_cmd, 0, sizeof(caps_cmd));
2773 caps_cmd.op_to_write =
2774 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2777 caps_cmd.retval_len16 =
2778 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
2779 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2780 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
2781 FW_LEN16(caps_cmd));
2782 ret = t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), &caps_cmd);
2787 *finiver = ntohl(caps_cmd.finiver);
2789 *finicsum = ntohl(caps_cmd.finicsum);
2791 *cfcsum = ntohl(caps_cmd.cfcsum);
2794 * And now tell the firmware to use the configuration we just loaded.
2796 caps_cmd.op_to_write =
2797 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2800 caps_cmd.retval_len16 = htonl(FW_LEN16(caps_cmd));
2801 return t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), NULL);
2805 * t4_fixup_host_params - fix up host-dependent parameters
2806 * @adap: the adapter
2807 * @page_size: the host's Base Page Size
2808 * @cache_line_size: the host's Cache Line Size
2810 * Various registers in T4 contain values which are dependent on the
2811 * host's Base Page and Cache Line Sizes. This function will fix all of
2812 * those registers with the appropriate values as passed in ...
2814 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
2815 unsigned int cache_line_size)
2817 unsigned int page_shift = fls(page_size) - 1;
2818 unsigned int sge_hps = page_shift - 10;
2819 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
2820 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
2821 unsigned int fl_align_log = fls(fl_align) - 1;
2823 t4_write_reg(adap, SGE_HOST_PAGE_SIZE,
2824 HOSTPAGESIZEPF0(sge_hps) |
2825 HOSTPAGESIZEPF1(sge_hps) |
2826 HOSTPAGESIZEPF2(sge_hps) |
2827 HOSTPAGESIZEPF3(sge_hps) |
2828 HOSTPAGESIZEPF4(sge_hps) |
2829 HOSTPAGESIZEPF5(sge_hps) |
2830 HOSTPAGESIZEPF6(sge_hps) |
2831 HOSTPAGESIZEPF7(sge_hps));
2833 t4_set_reg_field(adap, SGE_CONTROL,
2834 INGPADBOUNDARY_MASK |
2835 EGRSTATUSPAGESIZE_MASK,
2836 INGPADBOUNDARY(fl_align_log - 5) |
2837 EGRSTATUSPAGESIZE(stat_len != 64));
2840 * Adjust various SGE Free List Host Buffer Sizes.
2842 * This is something of a crock since we're using fixed indices into
2843 * the array which are also known by the sge.c code and the T4
2844 * Firmware Configuration File. We need to come up with a much better
2845 * approach to managing this array. For now, the first four entries
2850 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
2851 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
2853 * For the single-MTU buffers in unpacked mode we need to include
2854 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
2855 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
2856 * Padding boundry. All of these are accommodated in the Factory
2857 * Default Firmware Configuration File but we need to adjust it for
2858 * this host's cache line size.
2860 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);
2861 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,
2862 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)
2864 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,
2865 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)
2868 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
2874 * t4_fw_initialize - ask FW to initialize the device
2875 * @adap: the adapter
2876 * @mbox: mailbox to use for the FW command
2878 * Issues a command to FW to partially initialize the device. This
2879 * performs initialization that generally doesn't depend on user input.
2881 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
2883 struct fw_initialize_cmd c;
2885 memset(&c, 0, sizeof(c));
2886 INIT_CMD(c, INITIALIZE, WRITE);
2887 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2891 * t4_query_params - query FW or device parameters
2892 * @adap: the adapter
2893 * @mbox: mailbox to use for the FW command
2896 * @nparams: the number of parameters
2897 * @params: the parameter names
2898 * @val: the parameter values
2900 * Reads the value of FW or device parameters. Up to 7 parameters can be
2903 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2904 unsigned int vf, unsigned int nparams, const u32 *params,
2908 struct fw_params_cmd c;
2909 __be32 *p = &c.param[0].mnem;
2914 memset(&c, 0, sizeof(c));
2915 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
2916 FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) |
2917 FW_PARAMS_CMD_VFN(vf));
2918 c.retval_len16 = htonl(FW_LEN16(c));
2919 for (i = 0; i < nparams; i++, p += 2)
2920 *p = htonl(*params++);
2922 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2924 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
2930 * t4_set_params - sets FW or device parameters
2931 * @adap: the adapter
2932 * @mbox: mailbox to use for the FW command
2935 * @nparams: the number of parameters
2936 * @params: the parameter names
2937 * @val: the parameter values
2939 * Sets the value of FW or device parameters. Up to 7 parameters can be
2940 * specified at once.
2942 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2943 unsigned int vf, unsigned int nparams, const u32 *params,
2946 struct fw_params_cmd c;
2947 __be32 *p = &c.param[0].mnem;
2952 memset(&c, 0, sizeof(c));
2953 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
2954 FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) |
2955 FW_PARAMS_CMD_VFN(vf));
2956 c.retval_len16 = htonl(FW_LEN16(c));
2958 *p++ = htonl(*params++);
2959 *p++ = htonl(*val++);
2962 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2966 * t4_cfg_pfvf - configure PF/VF resource limits
2967 * @adap: the adapter
2968 * @mbox: mailbox to use for the FW command
2969 * @pf: the PF being configured
2970 * @vf: the VF being configured
2971 * @txq: the max number of egress queues
2972 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
2973 * @rxqi: the max number of interrupt-capable ingress queues
2974 * @rxq: the max number of interruptless ingress queues
2975 * @tc: the PCI traffic class
2976 * @vi: the max number of virtual interfaces
2977 * @cmask: the channel access rights mask for the PF/VF
2978 * @pmask: the port access rights mask for the PF/VF
2979 * @nexact: the maximum number of exact MPS filters
2980 * @rcaps: read capabilities
2981 * @wxcaps: write/execute capabilities
2983 * Configures resource limits and capabilities for a physical or virtual
2986 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
2987 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
2988 unsigned int rxqi, unsigned int rxq, unsigned int tc,
2989 unsigned int vi, unsigned int cmask, unsigned int pmask,
2990 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
2992 struct fw_pfvf_cmd c;
2994 memset(&c, 0, sizeof(c));
2995 c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST |
2996 FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) |
2997 FW_PFVF_CMD_VFN(vf));
2998 c.retval_len16 = htonl(FW_LEN16(c));
2999 c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
3000 FW_PFVF_CMD_NIQ(rxq));
3001 c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
3002 FW_PFVF_CMD_PMASK(pmask) |
3003 FW_PFVF_CMD_NEQ(txq));
3004 c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
3005 FW_PFVF_CMD_NEXACTF(nexact));
3006 c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
3007 FW_PFVF_CMD_WX_CAPS(wxcaps) |
3008 FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
3009 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3013 * t4_alloc_vi - allocate a virtual interface
3014 * @adap: the adapter
3015 * @mbox: mailbox to use for the FW command
3016 * @port: physical port associated with the VI
3017 * @pf: the PF owning the VI
3018 * @vf: the VF owning the VI
3019 * @nmac: number of MAC addresses needed (1 to 5)
3020 * @mac: the MAC addresses of the VI
3021 * @rss_size: size of RSS table slice associated with this VI
3023 * Allocates a virtual interface for the given physical port. If @mac is
3024 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3025 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3026 * stored consecutively so the space needed is @nmac * 6 bytes.
3027 * Returns a negative error number or the non-negative VI id.
3029 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3030 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3031 unsigned int *rss_size)
3036 memset(&c, 0, sizeof(c));
3037 c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
3038 FW_CMD_WRITE | FW_CMD_EXEC |
3039 FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
3040 c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
3041 c.portid_pkd = FW_VI_CMD_PORTID(port);
3044 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3049 memcpy(mac, c.mac, sizeof(c.mac));
3052 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3054 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3056 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3058 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3062 *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
3063 return FW_VI_CMD_VIID_GET(ntohs(c.type_viid));
3067 * t4_set_rxmode - set Rx properties of a virtual interface
3068 * @adap: the adapter
3069 * @mbox: mailbox to use for the FW command
3071 * @mtu: the new MTU or -1
3072 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3073 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3074 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3075 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
3076 * @sleep_ok: if true we may sleep while awaiting command completion
3078 * Sets Rx properties of a virtual interface.
3080 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3081 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3084 struct fw_vi_rxmode_cmd c;
3086 /* convert to FW values */
3088 mtu = FW_RXMODE_MTU_NO_CHG;
3090 promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
3092 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
3094 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
3096 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
3098 memset(&c, 0, sizeof(c));
3099 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST |
3100 FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid));
3101 c.retval_len16 = htonl(FW_LEN16(c));
3102 c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
3103 FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3104 FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3105 FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3106 FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3107 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3111 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
3112 * @adap: the adapter
3113 * @mbox: mailbox to use for the FW command
3115 * @free: if true any existing filters for this VI id are first removed
3116 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
3117 * @addr: the MAC address(es)
3118 * @idx: where to store the index of each allocated filter
3119 * @hash: pointer to hash address filter bitmap
3120 * @sleep_ok: call is allowed to sleep
3122 * Allocates an exact-match filter for each of the supplied addresses and
3123 * sets it to the corresponding address. If @idx is not %NULL it should
3124 * have at least @naddr entries, each of which will be set to the index of
3125 * the filter allocated for the corresponding MAC address. If a filter
3126 * could not be allocated for an address its index is set to 0xffff.
3127 * If @hash is not %NULL addresses that fail to allocate an exact filter
3128 * are hashed and update the hash filter bitmap pointed at by @hash.
3130 * Returns a negative error number or the number of filters allocated.
3132 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
3133 unsigned int viid, bool free, unsigned int naddr,
3134 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
3137 struct fw_vi_mac_cmd c;
3138 struct fw_vi_mac_exact *p;
3143 memset(&c, 0, sizeof(c));
3144 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3145 FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) |
3146 FW_VI_MAC_CMD_VIID(viid));
3147 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
3148 FW_CMD_LEN16((naddr + 2) / 2));
3150 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3151 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3152 FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
3153 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
3156 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
3160 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3161 u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3164 idx[i] = index >= NEXACT_MAC ? 0xffff : index;
3165 if (index < NEXACT_MAC)
3168 *hash |= (1ULL << hash_mac_addr(addr[i]));
3174 * t4_change_mac - modifies the exact-match filter for a MAC address
3175 * @adap: the adapter
3176 * @mbox: mailbox to use for the FW command
3178 * @idx: index of existing filter for old value of MAC address, or -1
3179 * @addr: the new MAC address value
3180 * @persist: whether a new MAC allocation should be persistent
3181 * @add_smt: if true also add the address to the HW SMT
3183 * Modifies an exact-match filter and sets it to the new MAC address.
3184 * Note that in general it is not possible to modify the value of a given
3185 * filter so the generic way to modify an address filter is to free the one
3186 * being used by the old address value and allocate a new filter for the
3187 * new address value. @idx can be -1 if the address is a new addition.
3189 * Returns a negative error number or the index of the filter with the new
3192 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3193 int idx, const u8 *addr, bool persist, bool add_smt)
3196 struct fw_vi_mac_cmd c;
3197 struct fw_vi_mac_exact *p = c.u.exact;
3199 if (idx < 0) /* new allocation */
3200 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3201 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3203 memset(&c, 0, sizeof(c));
3204 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3205 FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid));
3206 c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1));
3207 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3208 FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3209 FW_VI_MAC_CMD_IDX(idx));
3210 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3212 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3214 ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3215 if (ret >= NEXACT_MAC)
3222 * t4_set_addr_hash - program the MAC inexact-match hash filter
3223 * @adap: the adapter
3224 * @mbox: mailbox to use for the FW command
3226 * @ucast: whether the hash filter should also match unicast addresses
3227 * @vec: the value to be written to the hash filter
3228 * @sleep_ok: call is allowed to sleep
3230 * Sets the 64-bit inexact-match hash filter for a virtual interface.
3232 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
3233 bool ucast, u64 vec, bool sleep_ok)
3235 struct fw_vi_mac_cmd c;
3237 memset(&c, 0, sizeof(c));
3238 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3239 FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid));
3240 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
3241 FW_VI_MAC_CMD_HASHUNIEN(ucast) |
3243 c.u.hash.hashvec = cpu_to_be64(vec);
3244 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3248 * t4_enable_vi - enable/disable a virtual interface
3249 * @adap: the adapter
3250 * @mbox: mailbox to use for the FW command
3252 * @rx_en: 1=enable Rx, 0=disable Rx
3253 * @tx_en: 1=enable Tx, 0=disable Tx
3255 * Enables/disables a virtual interface.
3257 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3258 bool rx_en, bool tx_en)
3260 struct fw_vi_enable_cmd c;
3262 memset(&c, 0, sizeof(c));
3263 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3264 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3265 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
3266 FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c));
3267 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3271 * t4_identify_port - identify a VI's port by blinking its LED
3272 * @adap: the adapter
3273 * @mbox: mailbox to use for the FW command
3275 * @nblinks: how many times to blink LED at 2.5 Hz
3277 * Identifies a VI's port by blinking its LED.
3279 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
3280 unsigned int nblinks)
3282 struct fw_vi_enable_cmd c;
3284 memset(&c, 0, sizeof(c));
3285 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3286 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3287 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
3288 c.blinkdur = htons(nblinks);
3289 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3293 * t4_iq_free - free an ingress queue and its FLs
3294 * @adap: the adapter
3295 * @mbox: mailbox to use for the FW command
3296 * @pf: the PF owning the queues
3297 * @vf: the VF owning the queues
3298 * @iqtype: the ingress queue type
3299 * @iqid: ingress queue id
3300 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3301 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3303 * Frees an ingress queue and its associated FLs, if any.
3305 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3306 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3307 unsigned int fl0id, unsigned int fl1id)
3311 memset(&c, 0, sizeof(c));
3312 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
3313 FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
3315 c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
3316 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
3317 c.iqid = htons(iqid);
3318 c.fl0id = htons(fl0id);
3319 c.fl1id = htons(fl1id);
3320 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3324 * t4_eth_eq_free - free an Ethernet egress queue
3325 * @adap: the adapter
3326 * @mbox: mailbox to use for the FW command
3327 * @pf: the PF owning the queue
3328 * @vf: the VF owning the queue
3329 * @eqid: egress queue id
3331 * Frees an Ethernet egress queue.
3333 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3334 unsigned int vf, unsigned int eqid)
3336 struct fw_eq_eth_cmd c;
3338 memset(&c, 0, sizeof(c));
3339 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
3340 FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) |
3341 FW_EQ_ETH_CMD_VFN(vf));
3342 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3343 c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
3344 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3348 * t4_ctrl_eq_free - free a control egress queue
3349 * @adap: the adapter
3350 * @mbox: mailbox to use for the FW command
3351 * @pf: the PF owning the queue
3352 * @vf: the VF owning the queue
3353 * @eqid: egress queue id
3355 * Frees a control egress queue.
3357 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3358 unsigned int vf, unsigned int eqid)
3360 struct fw_eq_ctrl_cmd c;
3362 memset(&c, 0, sizeof(c));
3363 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
3364 FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) |
3365 FW_EQ_CTRL_CMD_VFN(vf));
3366 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
3367 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
3368 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3372 * t4_ofld_eq_free - free an offload egress queue
3373 * @adap: the adapter
3374 * @mbox: mailbox to use for the FW command
3375 * @pf: the PF owning the queue
3376 * @vf: the VF owning the queue
3377 * @eqid: egress queue id
3379 * Frees a control egress queue.
3381 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3382 unsigned int vf, unsigned int eqid)
3384 struct fw_eq_ofld_cmd c;
3386 memset(&c, 0, sizeof(c));
3387 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
3388 FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) |
3389 FW_EQ_OFLD_CMD_VFN(vf));
3390 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
3391 c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
3392 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3396 * t4_handle_fw_rpl - process a FW reply message
3397 * @adap: the adapter
3398 * @rpl: start of the FW message
3400 * Processes a FW message, such as link state change messages.
3402 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3404 u8 opcode = *(const u8 *)rpl;
3406 if (opcode == FW_PORT_CMD) { /* link/module state change message */
3407 int speed = 0, fc = 0;
3408 const struct fw_port_cmd *p = (void *)rpl;
3409 int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
3410 int port = adap->chan_map[chan];
3411 struct port_info *pi = adap2pinfo(adap, port);
3412 struct link_config *lc = &pi->link_cfg;
3413 u32 stat = ntohl(p->u.info.lstatus_to_modtype);
3414 int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
3415 u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
3417 if (stat & FW_PORT_CMD_RXPAUSE)
3419 if (stat & FW_PORT_CMD_TXPAUSE)
3421 if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3423 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3425 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3426 speed = SPEED_10000;
3428 if (link_ok != lc->link_ok || speed != lc->speed ||
3429 fc != lc->fc) { /* something changed */
3430 lc->link_ok = link_ok;
3433 t4_os_link_changed(adap, port, link_ok);
3435 if (mod != pi->mod_type) {
3437 t4_os_portmod_changed(adap, port);
3443 static void __devinit get_pci_mode(struct adapter *adapter,
3444 struct pci_params *p)
3448 if (pci_is_pcie(adapter->pdev)) {
3449 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
3450 p->speed = val & PCI_EXP_LNKSTA_CLS;
3451 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
3456 * init_link_config - initialize a link's SW state
3457 * @lc: structure holding the link state
3458 * @caps: link capabilities
3460 * Initializes the SW state maintained for each link, including the link's
3461 * capabilities and default speed/flow-control/autonegotiation settings.
3463 static void __devinit init_link_config(struct link_config *lc,
3466 lc->supported = caps;
3467 lc->requested_speed = 0;
3469 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3470 if (lc->supported & FW_PORT_CAP_ANEG) {
3471 lc->advertising = lc->supported & ADVERT_MASK;
3472 lc->autoneg = AUTONEG_ENABLE;
3473 lc->requested_fc |= PAUSE_AUTONEG;
3475 lc->advertising = 0;
3476 lc->autoneg = AUTONEG_DISABLE;
3480 int t4_wait_dev_ready(struct adapter *adap)
3482 if (t4_read_reg(adap, PL_WHOAMI) != 0xffffffff)
3485 return t4_read_reg(adap, PL_WHOAMI) != 0xffffffff ? 0 : -EIO;
3488 static int __devinit get_flash_params(struct adapter *adap)
3493 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
3495 ret = sf1_read(adap, 3, 0, 1, &info);
3496 t4_write_reg(adap, SF_OP, 0); /* unlock SF */
3500 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3502 info >>= 16; /* log2 of size */
3503 if (info >= 0x14 && info < 0x18)
3504 adap->params.sf_nsec = 1 << (info - 16);
3505 else if (info == 0x18)
3506 adap->params.sf_nsec = 64;
3509 adap->params.sf_size = 1 << info;
3510 adap->params.sf_fw_start =
3511 t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK;
3516 * t4_prep_adapter - prepare SW and HW for operation
3517 * @adapter: the adapter
3518 * @reset: if true perform a HW reset
3520 * Initialize adapter SW state for the various HW modules, set initial
3521 * values for some adapter tunables, take PHYs out of reset, and
3522 * initialize the MDIO interface.
3524 int __devinit t4_prep_adapter(struct adapter *adapter)
3528 ret = t4_wait_dev_ready(adapter);
3532 get_pci_mode(adapter, &adapter->params.pci);
3533 adapter->params.rev = t4_read_reg(adapter, PL_REV);
3535 ret = get_flash_params(adapter);
3537 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
3541 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3544 * Default port for debugging in case we can't reach FW.
3546 adapter->params.nports = 1;
3547 adapter->params.portvec = 1;
3548 adapter->params.vpd.cclk = 50000;
3552 int __devinit t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3556 struct fw_port_cmd c;
3557 struct fw_rss_vi_config_cmd rvc;
3559 memset(&c, 0, sizeof(c));
3560 memset(&rvc, 0, sizeof(rvc));
3562 for_each_port(adap, i) {
3563 unsigned int rss_size;
3564 struct port_info *p = adap2pinfo(adap, i);
3566 while ((adap->params.portvec & (1 << j)) == 0)
3569 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) |
3570 FW_CMD_REQUEST | FW_CMD_READ |
3571 FW_PORT_CMD_PORTID(j));
3572 c.action_to_len16 = htonl(
3573 FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
3575 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3579 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3586 p->rss_size = rss_size;
3587 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
3588 memcpy(adap->port[i]->perm_addr, addr, ETH_ALEN);
3589 adap->port[i]->dev_id = j;
3591 ret = ntohl(c.u.info.lstatus_to_modtype);
3592 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
3593 FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
3594 p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
3595 p->mod_type = FW_PORT_MOD_TYPE_NA;
3597 rvc.op_to_viid = htonl(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3598 FW_CMD_REQUEST | FW_CMD_READ |
3599 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3600 rvc.retval_len16 = htonl(FW_LEN16(rvc));
3601 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3604 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3606 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));