2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/rhashtable.h>
50 #include <linux/etherdevice.h>
51 #include <linux/net_tstamp.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/ptp_classify.h>
54 #include <linux/crash_dump.h>
55 #include <linux/thermal.h>
57 #include "t4_chip_type.h"
58 #include "cxgb4_uld.h"
60 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
61 extern struct list_head adapter_list;
62 extern struct mutex uld_mutex;
64 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
65 * This is the same as calc_tx_descs() for a TSO packet with
66 * nr_frags == MAX_SKB_FRAGS.
68 #define ETHTXQ_STOP_THRES \
69 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
72 MAX_NPORTS = 4, /* max # of ports */
73 SERNUM_LEN = 24, /* Serial # length */
74 EC_LEN = 16, /* E/C length */
75 ID_LEN = 16, /* ID length */
76 PN_LEN = 16, /* Part Number length */
77 MACADDR_LEN = 12, /* MAC Address length */
81 T4_REGMAP_SIZE = (160 * 1024),
82 T5_REGMAP_SIZE = (332 * 1024),
95 MEMWIN0_APERTURE = 2048,
96 MEMWIN0_BASE = 0x1b800,
97 MEMWIN1_APERTURE = 32768,
98 MEMWIN1_BASE = 0x28000,
99 MEMWIN1_BASE_T5 = 0x52000,
100 MEMWIN2_APERTURE = 65536,
101 MEMWIN2_BASE = 0x30000,
102 MEMWIN2_APERTURE_T5 = 131072,
103 MEMWIN2_BASE_T5 = 0x60000,
121 PAUSE_AUTONEG = 1 << 2
125 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
126 FEC_RS = 1 << 1, /* Reed-Solomon */
127 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
131 u64 tx_octets; /* total # of octets in good frames */
132 u64 tx_frames; /* all good frames */
133 u64 tx_bcast_frames; /* all broadcast frames */
134 u64 tx_mcast_frames; /* all multicast frames */
135 u64 tx_ucast_frames; /* all unicast frames */
136 u64 tx_error_frames; /* all error frames */
138 u64 tx_frames_64; /* # of Tx frames in a particular range */
139 u64 tx_frames_65_127;
140 u64 tx_frames_128_255;
141 u64 tx_frames_256_511;
142 u64 tx_frames_512_1023;
143 u64 tx_frames_1024_1518;
144 u64 tx_frames_1519_max;
146 u64 tx_drop; /* # of dropped Tx frames */
147 u64 tx_pause; /* # of transmitted pause frames */
148 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
149 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
150 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
151 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
152 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
153 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
154 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
155 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
157 u64 rx_octets; /* total # of octets in good frames */
158 u64 rx_frames; /* all good frames */
159 u64 rx_bcast_frames; /* all broadcast frames */
160 u64 rx_mcast_frames; /* all multicast frames */
161 u64 rx_ucast_frames; /* all unicast frames */
162 u64 rx_too_long; /* # of frames exceeding MTU */
163 u64 rx_jabber; /* # of jabber frames */
164 u64 rx_fcs_err; /* # of received frames with bad FCS */
165 u64 rx_len_err; /* # of received frames with length error */
166 u64 rx_symbol_err; /* symbol errors */
167 u64 rx_runt; /* # of short frames */
169 u64 rx_frames_64; /* # of Rx frames in a particular range */
170 u64 rx_frames_65_127;
171 u64 rx_frames_128_255;
172 u64 rx_frames_256_511;
173 u64 rx_frames_512_1023;
174 u64 rx_frames_1024_1518;
175 u64 rx_frames_1519_max;
177 u64 rx_pause; /* # of received pause frames */
178 u64 rx_ppp0; /* # of received PPP prio 0 frames */
179 u64 rx_ppp1; /* # of received PPP prio 1 frames */
180 u64 rx_ppp2; /* # of received PPP prio 2 frames */
181 u64 rx_ppp3; /* # of received PPP prio 3 frames */
182 u64 rx_ppp4; /* # of received PPP prio 4 frames */
183 u64 rx_ppp5; /* # of received PPP prio 5 frames */
184 u64 rx_ppp6; /* # of received PPP prio 6 frames */
185 u64 rx_ppp7; /* # of received PPP prio 7 frames */
187 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
188 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
189 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
190 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
191 u64 rx_trunc0; /* buffer-group 0 truncated packets */
192 u64 rx_trunc1; /* buffer-group 1 truncated packets */
193 u64 rx_trunc2; /* buffer-group 2 truncated packets */
194 u64 rx_trunc3; /* buffer-group 3 truncated packets */
197 struct lb_port_stats {
210 u64 frames_1024_1518;
225 struct tp_tcp_stats {
229 u64 tcp_retrans_segs;
232 struct tp_usm_stats {
238 struct tp_fcoe_stats {
244 struct tp_err_stats {
248 u32 tnl_cong_drops[4];
249 u32 ofld_chan_drops[4];
251 u32 ofld_vlan_drops[4];
257 struct tp_cpl_stats {
262 struct tp_rdma_stats {
268 u32 hps; /* host page size for our PF/VF */
269 u32 eq_qpp; /* egress queues/page for our PF/VF */
270 u32 iq_qpp; /* egress queues/page for our PF/VF */
274 unsigned int tre; /* log2 of core clocks per TP tick */
275 unsigned int la_mask; /* what events are recorded by TP LA */
276 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
279 uint32_t dack_re; /* DACK timer resolution */
280 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
282 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
283 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
285 /* cached TP_OUT_CONFIG compressed error vector
286 * and passing outer header info for encapsulated packets.
290 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
291 * subset of the set of fields which may be present in the Compressed
292 * Filter Tuple portion of filters and TCP TCB connections. The
293 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
294 * Since a variable number of fields may or may not be present, their
295 * shifted field positions within the Compressed Filter Tuple may
296 * vary, or not even be present if the field isn't selected in
297 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
298 * places we store their offsets here, or a -1 if the field isn't
312 u64 hash_filter_mask;
318 u8 sn[SERNUM_LEN + 1];
321 u8 na[MACADDR_LEN + 1];
324 /* Maximum resources provisioned for a PCI PF.
326 struct pf_resources {
327 unsigned int nvi; /* N virtual interfaces */
328 unsigned int neq; /* N egress Qs */
329 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
330 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
331 unsigned int niq; /* N ingress Qs */
332 unsigned int tc; /* PCI-E traffic class */
333 unsigned int pmask; /* port access rights mask */
334 unsigned int nexactf; /* N exact MPS filters */
335 unsigned int r_caps; /* read capabilities */
336 unsigned int wx_caps; /* write/execute capabilities */
340 unsigned int vpd_cap_addr;
345 struct devlog_params {
346 u32 memtype; /* which memory (EDC0, EDC1, MC) */
347 u32 start; /* start of log in firmware memory */
348 u32 size; /* size of log */
351 /* Stores chip specific parameters */
352 struct arch_specific_params {
355 u8 cng_ch_bits_log; /* congestion channel map bits width */
362 struct adapter_params {
363 struct sge_params sge;
365 struct vpd_params vpd;
366 struct pf_resources pfres;
367 struct pci_params pci;
368 struct devlog_params devlog;
369 enum pcie_memwin drv_memwin;
371 unsigned int cim_la_size;
373 unsigned int sf_size; /* serial flash size in bytes */
374 unsigned int sf_nsec; /* # of flash sectors */
376 unsigned int fw_vers; /* firmware version */
377 unsigned int bs_vers; /* bootstrap version */
378 unsigned int tp_vers; /* TP microcode version */
379 unsigned int er_vers; /* expansion ROM version */
380 unsigned int scfg_vers; /* Serial Configuration version */
381 unsigned int vpd_vers; /* VPD Version */
384 unsigned short mtus[NMTUS];
385 unsigned short a_wnd[NCCTRL_WIN];
386 unsigned short b_wnd[NCCTRL_WIN];
388 unsigned char nports; /* # of ethernet ports */
389 unsigned char portvec;
390 enum chip_type chip; /* chip code */
391 struct arch_specific_params arch; /* chip specific params */
392 unsigned char offload;
393 unsigned char crypto; /* HW capability for crypto */
395 unsigned char bypass;
396 unsigned char hash_filter;
398 unsigned int ofldq_wr_cred;
399 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
401 unsigned int nsched_cls; /* number of traffic classes */
402 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
403 unsigned int max_ird_adapter; /* Max read depth per adapter */
404 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
405 u8 fw_caps_support; /* 32-bit Port Capabilities */
406 bool filter2_wr_support; /* FW support for FILTER2_WR */
408 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
411 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
412 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
413 bool write_cmpl_support; /* FW supports WRITE_CMPL */
416 /* State needed to monitor the forward progress of SGE Ingress DMA activities
417 * and possible hangs.
419 struct sge_idma_monitor_state {
420 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
421 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
422 unsigned int idma_state[2]; /* IDMA Hang detect state */
423 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
424 unsigned int idma_warn[2]; /* time to warning in HZ */
427 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
428 * The access and execute times are signed in order to accommodate negative
432 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
433 u64 timestamp; /* OS-dependent timestamp */
434 u32 seqno; /* sequence number */
435 s16 access; /* time (ms) to access mailbox */
436 s16 execute; /* time (ms) to execute */
439 struct mbox_cmd_log {
440 unsigned int size; /* number of entries in the log */
441 unsigned int cursor; /* next position in the log to write */
442 u32 seqno; /* next sequence number */
443 /* variable length mailbox command log starts here */
446 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
447 * return a pointer to the specified entry.
449 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
450 unsigned int entry_idx)
452 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
455 #include "t4fw_api.h"
457 #define FW_VERSION(chip) ( \
458 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
459 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
460 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
461 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
462 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
468 struct fw_hdr fw_hdr;
471 struct trace_params {
472 u32 data[TRACE_LEN / 4];
473 u32 mask[TRACE_LEN / 4];
474 unsigned short snap_len;
475 unsigned short min_len;
476 unsigned char skip_ofst;
477 unsigned char skip_len;
478 unsigned char invert;
482 /* Firmware Port Capabilities types. */
484 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
485 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
488 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
489 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
490 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
494 fw_port_cap32_t pcaps; /* link capabilities */
495 fw_port_cap32_t def_acaps; /* default advertised capabilities */
496 fw_port_cap32_t acaps; /* advertised capabilities */
497 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
499 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
500 unsigned int speed; /* actual link speed (Mb/s) */
502 enum cc_pause requested_fc; /* flow control user has requested */
503 enum cc_pause fc; /* actual link flow control */
505 enum cc_fec requested_fec; /* Forward Error Correction: */
506 enum cc_fec fec; /* requested and actual in use */
508 unsigned char autoneg; /* autonegotiating? */
510 unsigned char link_ok; /* link up? */
511 unsigned char link_down_rc; /* link down reason */
513 bool new_module; /* ->OS Transceiver Module inserted */
514 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
517 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
520 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
521 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
522 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
526 MAX_TXQ_ENTRIES = 16384,
527 MAX_CTRL_TXQ_ENTRIES = 1024,
528 MAX_RSPQ_ENTRIES = 16384,
529 MAX_RX_BUFFERS = 16384,
530 MIN_TXQ_ENTRIES = 32,
531 MIN_CTRL_TXQ_ENTRIES = 32,
532 MIN_RSPQ_ENTRIES = 128,
537 MAX_TXQ_DESC_SIZE = 64,
538 MAX_RXQ_DESC_SIZE = 128,
539 MAX_FL_DESC_SIZE = 8,
540 MAX_CTRL_TXQ_DESC_SIZE = 64,
544 INGQ_EXTRAS = 2, /* firmware event queue and */
545 /* forwarded interrupts */
546 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
550 PRIV_FLAG_PORT_TX_VM_BIT,
553 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
555 #define PRIV_FLAGS_ADAP 0
556 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
561 #include "cxgb4_dcb.h"
563 #ifdef CONFIG_CHELSIO_T4_FCOE
564 #include "cxgb4_fcoe.h"
565 #endif /* CONFIG_CHELSIO_T4_FCOE */
568 struct adapter *adapter;
570 s16 xact_addr_filt; /* index of exact MAC address filter */
571 u16 rss_size; /* size of VI's RSS table slice */
573 enum fw_port_type port_type;
577 u8 lport; /* associated offload logical port */
578 u8 nqsets; /* # of qsets */
579 u8 first_qset; /* index of first qset */
581 struct link_config link_cfg;
583 struct port_stats stats_base;
584 #ifdef CONFIG_CHELSIO_T4_DCB
585 struct port_dcb_info dcb; /* Data Center Bridging support */
587 #ifdef CONFIG_CHELSIO_T4_FCOE
588 struct cxgb_fcoe fcoe;
589 #endif /* CONFIG_CHELSIO_T4_FCOE */
590 bool rxtstamp; /* Enable TS */
591 struct hwtstamp_config tstamp_config;
593 struct sched_table *sched_tbl;
600 enum { /* adapter flags */
601 FULL_INIT_DONE = (1 << 0),
602 DEV_ENABLED = (1 << 1),
603 USING_MSI = (1 << 2),
604 USING_MSIX = (1 << 3),
606 RSS_TNLALLLOOKUP = (1 << 5),
607 USING_SOFT_PARAMS = (1 << 6),
608 MASTER_PF = (1 << 7),
609 FW_OFLD_CONN = (1 << 9),
610 ROOT_NO_RELAXED_ORDERING = (1 << 10),
611 SHUTTING_DOWN = (1 << 11),
615 ULP_CRYPTO_LOOKASIDE = 1 << 0,
616 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
621 struct sge_fl { /* SGE free-buffer queue state */
622 unsigned int avail; /* # of available Rx buffers */
623 unsigned int pend_cred; /* new buffers since last FL DB ring */
624 unsigned int cidx; /* consumer index */
625 unsigned int pidx; /* producer index */
626 unsigned long alloc_failed; /* # of times buffer allocation failed */
627 unsigned long large_alloc_failed;
628 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
629 unsigned long low; /* # of times momentarily starving */
630 unsigned long starving;
632 unsigned int cntxt_id; /* SGE context id for the free list */
633 unsigned int size; /* capacity of free list */
634 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
635 __be64 *desc; /* address of HW Rx descriptor ring */
636 dma_addr_t addr; /* bus address of HW ring start */
637 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
638 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
641 /* A packet gather list */
643 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
644 struct page_frag frags[MAX_SKB_FRAGS];
645 void *va; /* virtual address of first byte */
646 unsigned int nfrags; /* # of fragments */
647 unsigned int tot_len; /* total length of fragments */
650 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
651 const struct pkt_gl *gl);
652 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
653 /* LRO related declarations for ULD */
655 #define MAX_LRO_SESSIONS 64
656 u8 lro_session_cnt; /* # of sessions to aggregate */
657 unsigned long lro_pkts; /* # of LRO super packets */
658 unsigned long lro_merged; /* # of wire packets merged by LRO */
659 struct sk_buff_head lroq; /* list of aggregated sessions */
662 struct sge_rspq { /* state for an SGE response queue */
663 struct napi_struct napi;
664 const __be64 *cur_desc; /* current descriptor in queue */
665 unsigned int cidx; /* consumer index */
666 u8 gen; /* current generation bit */
667 u8 intr_params; /* interrupt holdoff parameters */
668 u8 next_intr_params; /* holdoff params for next interrupt */
670 u8 pktcnt_idx; /* interrupt packet threshold */
671 u8 uld; /* ULD handling this queue */
672 u8 idx; /* queue index within its group */
673 int offset; /* offset into current Rx buffer */
674 u16 cntxt_id; /* SGE context id for the response q */
675 u16 abs_id; /* absolute SGE id for the response q */
676 __be64 *desc; /* address of HW response ring */
677 dma_addr_t phys_addr; /* physical address of the ring */
678 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
679 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
680 unsigned int iqe_len; /* entry size */
681 unsigned int size; /* capacity of response queue */
682 struct adapter *adap;
683 struct net_device *netdev; /* associated net device */
684 rspq_handler_t handler;
685 rspq_flush_handler_t flush_handler;
686 struct t4_lro_mgr lro_mgr;
689 struct sge_eth_stats { /* Ethernet queue statistics */
690 unsigned long pkts; /* # of ethernet packets */
691 unsigned long lro_pkts; /* # of LRO super packets */
692 unsigned long lro_merged; /* # of wire packets merged by LRO */
693 unsigned long rx_cso; /* # of Rx checksum offloads */
694 unsigned long vlan_ex; /* # of Rx VLAN extractions */
695 unsigned long rx_drops; /* # of packets dropped due to no mem */
696 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */
699 struct sge_eth_rxq { /* SW Ethernet Rx queue */
700 struct sge_rspq rspq;
702 struct sge_eth_stats stats;
703 } ____cacheline_aligned_in_smp;
705 struct sge_ofld_stats { /* offload queue statistics */
706 unsigned long pkts; /* # of packets */
707 unsigned long imm; /* # of immediate-data packets */
708 unsigned long an; /* # of asynchronous notifications */
709 unsigned long nomem; /* # of responses deferred due to no mem */
712 struct sge_ofld_rxq { /* SW offload Rx queue */
713 struct sge_rspq rspq;
715 struct sge_ofld_stats stats;
716 } ____cacheline_aligned_in_smp;
725 unsigned int in_use; /* # of in-use Tx descriptors */
726 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
727 unsigned int size; /* # of descriptors */
728 unsigned int cidx; /* SW consumer index */
729 unsigned int pidx; /* producer index */
730 unsigned long stops; /* # of times q has been stopped */
731 unsigned long restarts; /* # of queue restarts */
732 unsigned int cntxt_id; /* SGE context id for the Tx q */
733 struct tx_desc *desc; /* address of HW Tx descriptor ring */
734 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
735 struct sge_qstat *stat; /* queue status entry */
736 dma_addr_t phys_addr; /* physical address of the ring */
739 unsigned short db_pidx;
740 unsigned short db_pidx_inc;
741 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
742 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
745 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
747 struct netdev_queue *txq; /* associated netdev TX queue */
748 #ifdef CONFIG_CHELSIO_T4_DCB
749 u8 dcb_prio; /* DCB Priority bound to queue */
751 unsigned long tso; /* # of TSO requests */
752 unsigned long tx_cso; /* # of Tx checksum offloads */
753 unsigned long vlan_ins; /* # of Tx VLAN insertions */
754 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
755 } ____cacheline_aligned_in_smp;
757 struct sge_uld_txq { /* state for an SGE offload Tx queue */
759 struct adapter *adap;
760 struct sk_buff_head sendq; /* list of backpressured packets */
761 struct tasklet_struct qresume_tsk; /* restarts the queue */
762 bool service_ofldq_running; /* service_ofldq() is processing sendq */
763 u8 full; /* the Tx ring is full */
764 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
765 } ____cacheline_aligned_in_smp;
767 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
769 struct adapter *adap;
770 struct sk_buff_head sendq; /* list of backpressured packets */
771 struct tasklet_struct qresume_tsk; /* restarts the queue */
772 u8 full; /* the Tx ring is full */
773 } ____cacheline_aligned_in_smp;
775 struct sge_uld_rxq_info {
776 char name[IFNAMSIZ]; /* name of ULD driver */
777 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
778 u16 *msix_tbl; /* msix_tbl for uld */
779 u16 *rspq_id; /* response queue id's of rxq */
780 u16 nrxq; /* # of ingress uld queues */
781 u16 nciq; /* # of completion queues */
782 u8 uld; /* uld type */
785 struct sge_uld_txq_info {
786 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
787 atomic_t users; /* num users */
788 u16 ntxq; /* # of egress uld queues */
792 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
793 struct sge_eth_txq ptptxq;
794 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
796 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
797 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
798 struct sge_uld_rxq_info **uld_rxq_info;
799 struct sge_uld_txq_info **uld_txq_info;
801 struct sge_rspq intrq ____cacheline_aligned_in_smp;
802 spinlock_t intrq_lock;
804 u16 max_ethqsets; /* # of available Ethernet queue sets */
805 u16 ethqsets; /* # of active Ethernet queue sets */
806 u16 ethtxq_rover; /* Tx queue to clean up next */
807 u16 ofldqsets; /* # of active ofld queue sets */
808 u16 nqs_per_uld; /* # of Rx queues per ULD */
809 u16 timer_val[SGE_NTIMERS];
810 u8 counter_val[SGE_NCOUNTERS];
811 u32 fl_pg_order; /* large page allocation size */
812 u32 stat_len; /* length of status page at ring end */
813 u32 pktshift; /* padding between CPL & packet data */
814 u32 fl_align; /* response queue message alignment */
815 u32 fl_starve_thres; /* Free List starvation threshold */
817 struct sge_idma_monitor_state idma_monitor;
818 unsigned int egr_start;
820 unsigned int ingr_start;
821 unsigned int ingr_sz;
822 void **egr_map; /* qid->queue egress queue map */
823 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
824 unsigned long *starving_fl;
825 unsigned long *txq_maperr;
826 unsigned long *blocked_fl;
827 struct timer_list rx_timer; /* refills starving FLs */
828 struct timer_list tx_timer; /* checks Tx queues */
831 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
832 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
836 #ifdef CONFIG_PCI_IOV
838 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
839 * Configuration initialization for T5 only has SR-IOV functionality enabled
840 * on PF0-3 in order to simplify everything.
842 #define NUM_OF_PF_WITH_SRIOV 4
846 struct doorbell_stats {
852 struct hash_mac_addr {
853 struct list_head list;
857 struct uld_msix_bmap {
858 unsigned long *msix_bmap;
859 unsigned int mapsize;
860 spinlock_t lock; /* lock for acquiring bitmap */
863 struct uld_msix_info {
865 char desc[IFNAMSIZ + 10];
870 unsigned char vf_mac_addr[ETH_ALEN];
871 unsigned int tx_rate;
877 HMA_DMA_MAPPED_FLAG = 1
882 struct sg_table *sgt;
883 dma_addr_t *phy_addr; /* physical address of the page */
887 struct list_head list;
890 struct mps_encap_entry {
894 #if IS_ENABLED(CONFIG_THERMAL)
896 struct thermal_zone_device *tzdev;
906 struct pci_dev *pdev;
907 struct device *pdev_dev;
912 unsigned int adap_idx;
922 struct adapter_params params;
923 struct cxgb4_virt_res vres;
928 char desc[IFNAMSIZ + 10];
929 } msix_info[MAX_INGQ + 1];
930 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
931 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
934 struct doorbell_stats db_stats;
937 struct net_device *port[MAX_NPORTS];
938 u8 chan_map[NCHAN]; /* channel -> port map */
940 struct vf_info *vfinfo;
944 unsigned int l2t_start;
945 unsigned int l2t_end;
946 struct l2t_data *l2t;
947 unsigned int clipt_start;
948 unsigned int clipt_end;
949 struct clip_tbl *clipt;
950 unsigned int rawf_start;
951 unsigned int rawf_cnt;
952 struct smt_data *smt;
953 struct mps_encap_entry *mps_encap;
954 struct cxgb4_uld_info *uld;
955 void *uld_handle[CXGB4_ULD_MAX];
956 unsigned int num_uld;
957 unsigned int num_ofld_uld;
958 struct list_head list_node;
959 struct list_head rcu_node;
960 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
964 struct tid_info tids;
965 void **tid_release_head;
966 spinlock_t tid_release_lock;
967 struct workqueue_struct *workq;
968 struct work_struct tid_release_task;
969 struct work_struct db_full_task;
970 struct work_struct db_drop_task;
971 struct work_struct fatal_err_notify_task;
972 bool tid_release_task_busy;
974 /* lock for mailbox cmd list */
975 spinlock_t mbox_lock;
976 struct mbox_list mlist;
978 /* support for mailbox command/reply logging */
979 #define T4_OS_LOG_MBOX_CMDS 256
980 struct mbox_cmd_log *mbox_log;
982 struct mutex uld_mutex;
984 struct dentry *debugfs_root;
985 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
986 bool trace_rss; /* 1 implies that different RSS flit per filter is
987 * used per filter else if 0 default RSS flit is
988 * used for all 4 filters.
991 struct ptp_clock *ptp_clock;
992 struct ptp_clock_info ptp_clock_info;
993 struct sk_buff *ptp_tx_skb;
996 spinlock_t stats_lock;
997 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1000 struct cxgb4_tc_u32_table *tc_u32;
1001 struct chcr_stats_debug chcr_stats;
1003 /* TC flower offload */
1004 bool tc_flower_initialized;
1005 struct rhashtable flower_tbl;
1006 struct rhashtable_params flower_ht_params;
1007 struct timer_list flower_stats_timer;
1008 struct work_struct flower_stats_work;
1011 struct ethtool_dump eth_dump;
1014 struct hma_data hma;
1016 struct srq_data *srq;
1018 /* Dump buffer for collecting logs in kdump kernel */
1019 struct vmcoredd_data vmcoredd;
1020 #if IS_ENABLED(CONFIG_THERMAL)
1021 struct ch_thermal ch_thermal;
1025 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1026 * programmed with various parameters.
1028 struct ch_sched_params {
1029 s8 type; /* packet or flow */
1032 s8 level; /* scheduler hierarchy level */
1033 s8 mode; /* per-class or per-flow */
1034 s8 rateunit; /* bit or packet rate */
1035 s8 ratemode; /* %port relative or kbps absolute */
1036 s8 channel; /* scheduler channel [0..N] */
1037 s8 class; /* scheduler class [0..N] */
1038 s32 minrate; /* minimum rate */
1039 s32 maxrate; /* maximum rate */
1040 s16 weight; /* percent weight */
1041 s16 pktsize; /* average packet size */
1047 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
1051 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
1055 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1059 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
1063 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
1066 struct tx_sw_desc { /* SW state per Tx descriptor */
1067 struct sk_buff *skb;
1068 struct ulptx_sgl *sgl;
1071 /* Support for "sched_queue" command to allow one or more NIC TX Queues
1072 * to be bound to a TX Scheduling Class.
1074 struct ch_sched_queue {
1075 s8 queue; /* queue index */
1076 s8 class; /* class index */
1079 /* Defined bit width of user definable filter tuples
1081 #define ETHTYPE_BITWIDTH 16
1082 #define FRAG_BITWIDTH 1
1083 #define MACIDX_BITWIDTH 9
1084 #define FCOE_BITWIDTH 1
1085 #define IPORT_BITWIDTH 3
1086 #define MATCHTYPE_BITWIDTH 3
1087 #define PROTO_BITWIDTH 8
1088 #define TOS_BITWIDTH 8
1089 #define PF_BITWIDTH 8
1090 #define VF_BITWIDTH 8
1091 #define IVLAN_BITWIDTH 16
1092 #define OVLAN_BITWIDTH 16
1093 #define ENCAP_VNI_BITWIDTH 24
1095 /* Filter matching rules. These consist of a set of ingress packet field
1096 * (value, mask) tuples. The associated ingress packet field matches the
1097 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
1098 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
1099 * matches an ingress packet when all of the individual individual field
1100 * matching rules are true.
1102 * Partial field masks are always valid, however, while it may be easy to
1103 * understand their meanings for some fields (e.g. IP address to match a
1104 * subnet), for others making sensible partial masks is less intuitive (e.g.
1105 * MPS match type) ...
1107 * Most of the following data structures are modeled on T4 capabilities.
1108 * Drivers for earlier chips use the subsets which make sense for those chips.
1109 * We really need to come up with a hardware-independent mechanism to
1110 * represent hardware filter capabilities ...
1112 struct ch_filter_tuple {
1113 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1114 * register selects which of these fields will participate in the
1115 * filter match rules -- up to a maximum of 36 bits. Because
1116 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1119 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1120 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1121 uint32_t ivlan_vld:1; /* inner VLAN valid */
1122 uint32_t ovlan_vld:1; /* outer VLAN valid */
1123 uint32_t pfvf_vld:1; /* PF/VF valid */
1124 uint32_t encap_vld:1; /* Encapsulation valid */
1125 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1126 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1127 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1128 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1129 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1130 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1131 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1132 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1133 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1134 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
1135 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
1137 /* Uncompressed header matching field rules. These are always
1138 * available for field rules.
1140 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1141 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1142 uint16_t lport; /* local port */
1143 uint16_t fport; /* foreign port */
1146 /* A filter ioctl command.
1148 struct ch_filter_specification {
1149 /* Administrative fields for filter.
1151 uint32_t hitcnts:1; /* count filter hits in TCB */
1152 uint32_t prio:1; /* filter has priority over active/server */
1154 /* Fundamental filter typing. This is the one element of filter
1155 * matching that doesn't exist as a (value, mask) tuple.
1157 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
1158 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
1160 /* Packet dispatch information. Ingress packets which match the
1161 * filter rules will be dropped, passed to the host or switched back
1162 * out as egress packets.
1164 uint32_t action:2; /* drop, pass, switch */
1166 uint32_t rpttid:1; /* report TID in RSS hash field */
1168 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1169 uint32_t iq:10; /* ingress queue */
1171 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1172 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1173 /* 1 => TCB contains IQ ID */
1175 /* Switch proxy/rewrite fields. An ingress packet which matches a
1176 * filter with "switch" set will be looped back out as an egress
1177 * packet -- potentially with some Ethernet header rewriting.
1179 uint32_t eport:2; /* egress port to switch packet out */
1180 uint32_t newdmac:1; /* rewrite destination MAC address */
1181 uint32_t newsmac:1; /* rewrite source MAC address */
1182 uint32_t newvlan:2; /* rewrite VLAN Tag */
1183 uint32_t nat_mode:3; /* specify NAT operation mode */
1184 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1185 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1186 uint16_t vlan; /* VLAN Tag to insert */
1188 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1189 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1190 u16 nat_lport; /* local port to use after NAT'ing */
1191 u16 nat_fport; /* foreign port to use after NAT'ing */
1193 /* reservation for future additions */
1196 /* Filter rule value/mask pairs.
1198 struct ch_filter_tuple val;
1199 struct ch_filter_tuple mask;
1203 FILTER_PASS = 0, /* default */
1209 VLAN_NOCHANGE = 0, /* default */
1216 NAT_MODE_NONE = 0, /* No NAT performed */
1217 NAT_MODE_DIP, /* NAT on Dst IP */
1218 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
1219 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
1220 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
1221 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
1222 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
1223 NAT_MODE_ALL /* NAT on entire 4-tuple */
1226 /* Host shadow copy of ingress filter entry. This is in host native format
1227 * and doesn't match the ordering or bit order, etc. of the hardware of the
1228 * firmware command. The use of bit-field structure elements is purely to
1229 * remind ourselves of the field size limitations and save memory in the case
1230 * where the filter table is large.
1232 struct filter_entry {
1233 /* Administrative fields for filter. */
1234 u32 valid:1; /* filter allocated and valid */
1235 u32 locked:1; /* filter is administratively locked */
1237 u32 pending:1; /* filter action is pending firmware reply */
1238 struct filter_ctx *ctx; /* Caller's completion hook */
1239 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
1240 struct smt_entry *smt; /* Source Mac Table entry for smac */
1241 struct net_device *dev; /* Associated net device */
1242 u32 tid; /* This will store the actual tid */
1244 /* The filter itself. Most of this is a straight copy of information
1245 * provided by the extended ioctl(). Some fields are translated to
1246 * internal forms -- for instance the Ingress Queue ID passed in from
1247 * the ioctl() is translated into the Absolute Ingress Queue ID.
1249 struct ch_filter_specification fs;
1252 static inline int is_offload(const struct adapter *adap)
1254 return adap->params.offload;
1257 static inline int is_hashfilter(const struct adapter *adap)
1259 return adap->params.hash_filter;
1262 static inline int is_pci_uld(const struct adapter *adap)
1264 return adap->params.crypto;
1267 static inline int is_uld(const struct adapter *adap)
1269 return (adap->params.offload || adap->params.crypto);
1272 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1274 return readl(adap->regs + reg_addr);
1277 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1279 writel(val, adap->regs + reg_addr);
1283 static inline u64 readq(const volatile void __iomem *addr)
1285 return readl(addr) + ((u64)readl(addr + 4) << 32);
1288 static inline void writeq(u64 val, volatile void __iomem *addr)
1291 writel(val >> 32, addr + 4);
1295 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1297 return readq(adap->regs + reg_addr);
1300 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1302 writeq(val, adap->regs + reg_addr);
1306 * t4_set_hw_addr - store a port's MAC address in SW
1307 * @adapter: the adapter
1308 * @port_idx: the port index
1309 * @hw_addr: the Ethernet address
1311 * Store the Ethernet address of the given port in SW. Called by the common
1312 * code when it retrieves a port's Ethernet address from EEPROM.
1314 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1317 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1318 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1322 * netdev2pinfo - return the port_info structure associated with a net_device
1325 * Return the struct port_info associated with a net_device
1327 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1329 return netdev_priv(dev);
1333 * adap2pinfo - return the port_info of a port
1334 * @adap: the adapter
1335 * @idx: the port index
1337 * Return the port_info structure for the port of the given index.
1339 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1341 return netdev_priv(adap->port[idx]);
1345 * netdev2adap - return the adapter structure associated with a net_device
1348 * Return the struct adapter associated with a net_device
1350 static inline struct adapter *netdev2adap(const struct net_device *dev)
1352 return netdev2pinfo(dev)->adapter;
1355 /* Return a version number to identify the type of adapter. The scheme is:
1356 * - bits 0..9: chip version
1357 * - bits 10..15: chip revision
1358 * - bits 16..23: register dump version
1360 static inline unsigned int mk_adap_vers(struct adapter *ap)
1362 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1363 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1366 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1367 static inline unsigned int qtimer_val(const struct adapter *adap,
1368 const struct sge_rspq *q)
1370 unsigned int idx = q->intr_params >> 1;
1372 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1375 /* driver version & name used for ethtool_drvinfo */
1376 extern char cxgb4_driver_name[];
1377 extern const char cxgb4_driver_version[];
1379 void t4_os_portmod_changed(struct adapter *adap, int port_id);
1380 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1382 void t4_free_sge_resources(struct adapter *adap);
1383 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1384 irq_handler_t t4_intr_handler(struct adapter *adap);
1385 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1386 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1387 const struct pkt_gl *gl);
1388 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1389 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1390 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1391 struct net_device *dev, int intr_idx,
1392 struct sge_fl *fl, rspq_handler_t hnd,
1393 rspq_flush_handler_t flush_handler, int cong);
1394 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1395 struct net_device *dev, struct netdev_queue *netdevq,
1397 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1398 struct net_device *dev, unsigned int iqid,
1399 unsigned int cmplqid);
1400 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1401 unsigned int cmplqid);
1402 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1403 struct net_device *dev, unsigned int iqid,
1404 unsigned int uld_type);
1405 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1406 int t4_sge_init(struct adapter *adap);
1407 void t4_sge_start(struct adapter *adap);
1408 void t4_sge_stop(struct adapter *adap);
1409 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1410 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1411 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1412 extern int dbfifo_int_thresh;
1414 #define for_each_port(adapter, iter) \
1415 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1417 static inline int is_bypass(struct adapter *adap)
1419 return adap->params.bypass;
1422 static inline int is_bypass_device(int device)
1424 /* this should be set based upon device capabilities */
1434 static inline int is_10gbt_device(int device)
1436 /* this should be set based upon device capabilities */
1447 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1449 return adap->params.vpd.cclk / 1000;
1452 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1455 return (us * adap->params.vpd.cclk) / 1000;
1458 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1461 /* add Core Clock / 2 to round ticks to nearest uS */
1462 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1463 adapter->params.vpd.cclk);
1466 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1469 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1472 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1475 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1476 int size, void *rpl, bool sleep_ok, int timeout);
1477 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1478 void *rpl, bool sleep_ok);
1480 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1481 const void *cmd, int size, void *rpl,
1484 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1488 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1489 int size, void *rpl)
1491 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1494 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1495 int size, void *rpl)
1497 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1501 * hash_mac_addr - return the hash value of a MAC address
1502 * @addr: the 48-bit Ethernet MAC address
1504 * Hashes a MAC address according to the hash function used by HW inexact
1505 * (hash) address matching.
1507 static inline int hash_mac_addr(const u8 *addr)
1509 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1510 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1518 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1520 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1521 unsigned int us, unsigned int cnt,
1522 unsigned int size, unsigned int iqe_size)
1525 cxgb4_set_rspq_intr_params(q, us, cnt);
1526 q->iqe_len = iqe_size;
1531 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1532 * @fw_mod_type: the Firmware Mofule Type
1534 * Return whether the Firmware Module Type represents a real Transceiver
1535 * Module/Cable Module Type which has been inserted.
1537 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1539 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1540 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1541 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1542 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1545 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1546 unsigned int data_reg, const u32 *vals,
1547 unsigned int nregs, unsigned int start_idx);
1548 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1549 unsigned int data_reg, u32 *vals, unsigned int nregs,
1550 unsigned int start_idx);
1551 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1553 struct fw_filter_wr;
1555 void t4_intr_enable(struct adapter *adapter);
1556 void t4_intr_disable(struct adapter *adapter);
1557 int t4_slow_intr_handler(struct adapter *adapter);
1559 int t4_wait_dev_ready(void __iomem *regs);
1561 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1562 unsigned int port, struct link_config *lc,
1563 bool sleep_ok, int timeout);
1565 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1566 unsigned int port, struct link_config *lc)
1568 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1569 true, FW_CMD_MAX_TIMEOUT);
1572 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1573 unsigned int port, struct link_config *lc)
1575 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1576 false, FW_CMD_MAX_TIMEOUT);
1579 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1581 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1582 u32 t4_get_util_window(struct adapter *adap);
1583 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1585 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1586 u32 *mem_base, u32 *mem_aperture);
1587 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1588 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1590 #define T4_MEMORY_WRITE 0
1591 #define T4_MEMORY_READ 1
1592 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1593 void *buf, int dir);
1594 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1595 u32 len, __be32 *buf)
1597 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1600 unsigned int t4_get_regs_len(struct adapter *adapter);
1601 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1603 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1604 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1605 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1606 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1607 int t4_get_pfres(struct adapter *adapter);
1608 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1609 unsigned int nwords, u32 *data, int byte_oriented);
1610 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1611 int t4_load_phy_fw(struct adapter *adap,
1612 int win, spinlock_t *lock,
1613 int (*phy_fw_version)(const u8 *, size_t),
1614 const u8 *phy_fw_data, size_t phy_fw_size);
1615 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1616 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1617 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1618 const u8 *fw_data, unsigned int size, int force);
1619 int t4_fl_pkt_align(struct adapter *adap);
1620 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1621 int t4_check_fw_version(struct adapter *adap);
1622 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1623 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1624 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1625 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1626 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1627 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1628 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1629 int t4_get_version_info(struct adapter *adapter);
1630 void t4_dump_version_info(struct adapter *adapter);
1631 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1632 const u8 *fw_data, unsigned int fw_size,
1633 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1634 int t4_prep_adapter(struct adapter *adapter);
1635 int t4_shutdown_adapter(struct adapter *adapter);
1637 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1638 int t4_bar2_sge_qregs(struct adapter *adapter,
1640 enum t4_bar2_qtype qtype,
1643 unsigned int *pbar2_qid);
1645 unsigned int qtimer_val(const struct adapter *adap,
1646 const struct sge_rspq *q);
1648 int t4_init_devlog_params(struct adapter *adapter);
1649 int t4_init_sge_params(struct adapter *adapter);
1650 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1651 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1652 int t4_init_rss_mode(struct adapter *adap, int mbox);
1653 int t4_init_portinfo(struct port_info *pi, int mbox,
1654 int port, int pf, int vf, u8 mac[]);
1655 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1656 void t4_fatal_err(struct adapter *adapter);
1657 unsigned int t4_chip_rss_size(struct adapter *adapter);
1658 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1659 int start, int n, const u16 *rspq, unsigned int nrspq);
1660 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1661 unsigned int flags);
1662 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1663 unsigned int flags, unsigned int defq);
1664 int t4_read_rss(struct adapter *adapter, u16 *entries);
1665 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1666 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1668 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1669 u32 *valp, bool sleep_ok);
1670 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1671 u32 *vfl, u32 *vfh, bool sleep_ok);
1672 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1673 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1675 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1676 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1677 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1678 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1679 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1681 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1683 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1684 unsigned int *valp);
1685 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1686 const unsigned int *valp);
1687 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1688 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1689 unsigned int *pif_req_wrptr,
1690 unsigned int *pif_rsp_wrptr);
1691 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1692 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1693 const char *t4_get_port_type_description(enum fw_port_type port_type);
1694 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1695 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1696 struct port_stats *stats,
1697 struct port_stats *offset);
1698 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1699 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1700 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1701 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1702 unsigned int mask, unsigned int val);
1703 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1704 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1706 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1708 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1710 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1712 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1713 struct tp_tcp_stats *v6, bool sleep_ok);
1714 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1715 struct tp_fcoe_stats *st, bool sleep_ok);
1716 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1717 const unsigned short *alpha, const unsigned short *beta);
1719 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1721 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1722 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1724 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1726 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1727 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1729 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1730 enum dev_master master, enum dev_state *state);
1731 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1732 int t4_early_init(struct adapter *adap, unsigned int mbox);
1733 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1734 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1735 unsigned int cache_line_size);
1736 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1737 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1738 unsigned int vf, unsigned int nparams, const u32 *params,
1740 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1741 unsigned int vf, unsigned int nparams, const u32 *params,
1743 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1744 unsigned int vf, unsigned int nparams, const u32 *params,
1745 u32 *val, int rw, bool sleep_ok);
1746 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1747 unsigned int pf, unsigned int vf,
1748 unsigned int nparams, const u32 *params,
1749 const u32 *val, int timeout);
1750 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1751 unsigned int vf, unsigned int nparams, const u32 *params,
1753 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1754 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1755 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1756 unsigned int vi, unsigned int cmask, unsigned int pmask,
1757 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1758 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1759 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1760 unsigned int *rss_size);
1761 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1762 unsigned int pf, unsigned int vf,
1764 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1765 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1767 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1768 const u8 *addr, const u8 *mask, unsigned int idx,
1769 u8 lookup_type, u8 port_id, bool sleep_ok);
1770 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1772 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1773 const u8 *addr, const u8 *mask, unsigned int vni,
1774 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1776 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1777 const u8 *addr, const u8 *mask, unsigned int idx,
1778 u8 lookup_type, u8 port_id, bool sleep_ok);
1779 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1780 unsigned int viid, bool free, unsigned int naddr,
1781 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1782 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1783 unsigned int viid, unsigned int naddr,
1784 const u8 **addr, bool sleep_ok);
1785 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1786 int idx, const u8 *addr, bool persist, bool add_smt);
1787 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1788 bool ucast, u64 vec, bool sleep_ok);
1789 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1790 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1791 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1792 struct port_info *pi,
1793 bool rx_en, bool tx_en, bool dcb_en);
1794 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1795 bool rx_en, bool tx_en);
1796 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1797 unsigned int nblinks);
1798 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1799 unsigned int mmd, unsigned int reg, u16 *valp);
1800 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1801 unsigned int mmd, unsigned int reg, u16 val);
1802 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1803 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1804 unsigned int fl0id, unsigned int fl1id);
1805 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1806 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1807 unsigned int fl0id, unsigned int fl1id);
1808 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1809 unsigned int vf, unsigned int eqid);
1810 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1811 unsigned int vf, unsigned int eqid);
1812 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1813 unsigned int vf, unsigned int eqid);
1814 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1815 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1816 int t4_update_port_info(struct port_info *pi);
1817 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1818 unsigned int *speedp, unsigned int *mtup);
1819 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1820 void t4_db_full(struct adapter *adapter);
1821 void t4_db_dropped(struct adapter *adapter);
1822 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1823 int filter_index, int enable);
1824 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1825 int filter_index, int *enabled);
1826 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1828 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1829 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1830 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1831 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1832 enum ctxt_type ctype, u32 *data);
1833 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1834 enum ctxt_type ctype, u32 *data);
1835 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1836 int rateunit, int ratemode, int channel, int class,
1837 int minrate, int maxrate, int weight, int pktsize);
1838 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1839 void t4_idma_monitor_init(struct adapter *adapter,
1840 struct sge_idma_monitor_state *idma);
1841 void t4_idma_monitor(struct adapter *adapter,
1842 struct sge_idma_monitor_state *idma,
1844 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1845 unsigned int naddr, u8 *addr);
1846 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1847 u32 start_index, bool sleep_ok);
1848 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1849 u32 start_index, bool sleep_ok);
1850 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1851 u32 start_index, bool sleep_ok);
1853 void t4_uld_mem_free(struct adapter *adap);
1854 int t4_uld_mem_alloc(struct adapter *adap);
1855 void t4_uld_clean_up(struct adapter *adap);
1856 void t4_register_netevent_notifier(void);
1857 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1858 unsigned int devid, unsigned int offset,
1859 unsigned int len, u8 *buf);
1860 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1861 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1862 unsigned int n, bool unmap);
1863 void free_txq(struct adapter *adap, struct sge_txq *q);
1864 void cxgb4_reclaim_completed_tx(struct adapter *adap,
1865 struct sge_txq *q, bool unmap);
1866 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1868 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1870 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1871 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1872 const dma_addr_t *addr);
1873 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
1874 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1876 int cxgb4_dcb_enabled(const struct net_device *dev);
1878 int cxgb4_thermal_init(struct adapter *adap);
1879 int cxgb4_thermal_remove(struct adapter *adap);
1881 #endif /* __CXGB4_H__ */