drivers/net/ethernet/cavium/thunder/thunder_bgx.h

   1 /*
   2  * Copyright (C) 2015 Cavium, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef THUNDER_BGX_H
  10 #define THUNDER_BGX_H
  11
  12 /* PCI device ID */
  13 #define PCI_DEVICE_ID_THUNDER_BGX               0xA026
  14 #define PCI_DEVICE_ID_THUNDER_RGX               0xA054
  15
  16 /* Subsystem device IDs */
  17 #define PCI_SUBSYS_DEVID_88XX_BGX               0xA126
  18 #define PCI_SUBSYS_DEVID_81XX_BGX               0xA226
  19 #define PCI_SUBSYS_DEVID_83XX_BGX               0xA326
  20
  21 #define    MAX_BGX_THUNDER                      8 /* Max 2 nodes, 4 per node */
  22 #define    MAX_BGX_PER_CN88XX                   2
  23 #define    MAX_BGX_PER_CN81XX                   3 /* 2 BGXs + 1 RGX */
  24 #define    MAX_BGX_PER_CN83XX                   4
  25 #define    MAX_LMAC_PER_BGX                     4
  26 #define    MAX_BGX_CHANS_PER_LMAC               16
  27 #define    MAX_DMAC_PER_LMAC                    8
  28 #define    MAX_FRAME_SIZE                       9216
  29 #define    DEFAULT_PAUSE_TIME                   0xFFFF
  30
  31 #define    BGX_ID_MASK                          0x3
  32
  33 #define    MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE    2
  34
  35 /* Registers */
  36 #define BGX_CMRX_CFG                    0x00
  37 #define  CMR_PKT_TX_EN                          BIT_ULL(13)
  38 #define  CMR_PKT_RX_EN                          BIT_ULL(14)
  39 #define  CMR_EN                                 BIT_ULL(15)
  40 #define BGX_CMR_GLOBAL_CFG              0x08
  41 #define  CMR_GLOBAL_CFG_FCS_STRIP               BIT_ULL(6)
  42 #define BGX_CMRX_RX_ID_MAP              0x60
  43 #define BGX_CMRX_RX_STAT0               0x70
  44 #define BGX_CMRX_RX_STAT1               0x78
  45 #define BGX_CMRX_RX_STAT2               0x80
  46 #define BGX_CMRX_RX_STAT3               0x88
  47 #define BGX_CMRX_RX_STAT4               0x90
  48 #define BGX_CMRX_RX_STAT5               0x98
  49 #define BGX_CMRX_RX_STAT6               0xA0
  50 #define BGX_CMRX_RX_STAT7               0xA8
  51 #define BGX_CMRX_RX_STAT8               0xB0
  52 #define BGX_CMRX_RX_STAT9               0xB8
  53 #define BGX_CMRX_RX_STAT10              0xC0
  54 #define BGX_CMRX_RX_BP_DROP             0xC8
  55 #define BGX_CMRX_RX_DMAC_CTL            0x0E8
  56 #define BGX_CMRX_RX_FIFO_LEN            0x108
  57 #define BGX_CMR_RX_DMACX_CAM            0x200
  58 #define  RX_DMACX_CAM_EN                        BIT_ULL(48)
  59 #define  RX_DMACX_CAM_LMACID(x)                 (x << 49)
  60 #define  RX_DMAC_COUNT                          32
  61 #define BGX_CMR_RX_STREERING            0x300
  62 #define  RX_TRAFFIC_STEER_RULE_COUNT            8
  63 #define BGX_CMR_CHAN_MSK_AND            0x450
  64 #define BGX_CMR_BIST_STATUS             0x460
  65 #define BGX_CMR_RX_LMACS                0x468
  66 #define BGX_CMRX_TX_FIFO_LEN            0x518
  67 #define BGX_CMRX_TX_STAT0               0x600
  68 #define BGX_CMRX_TX_STAT1               0x608
  69 #define BGX_CMRX_TX_STAT2               0x610
  70 #define BGX_CMRX_TX_STAT3               0x618
  71 #define BGX_CMRX_TX_STAT4               0x620
  72 #define BGX_CMRX_TX_STAT5               0x628
  73 #define BGX_CMRX_TX_STAT6               0x630
  74 #define BGX_CMRX_TX_STAT7               0x638
  75 #define BGX_CMRX_TX_STAT8               0x640
  76 #define BGX_CMRX_TX_STAT9               0x648
  77 #define BGX_CMRX_TX_STAT10              0x650
  78 #define BGX_CMRX_TX_STAT11              0x658
  79 #define BGX_CMRX_TX_STAT12              0x660
  80 #define BGX_CMRX_TX_STAT13              0x668
  81 #define BGX_CMRX_TX_STAT14              0x670
  82 #define BGX_CMRX_TX_STAT15              0x678
  83 #define BGX_CMRX_TX_STAT16              0x680
  84 #define BGX_CMRX_TX_STAT17              0x688
  85 #define BGX_CMR_TX_LMACS                0x1000
  86
  87 #define BGX_SPUX_CONTROL1               0x10000
  88 #define  SPU_CTL_LOW_POWER                      BIT_ULL(11)
  89 #define  SPU_CTL_LOOPBACK                       BIT_ULL(14)
  90 #define  SPU_CTL_RESET                          BIT_ULL(15)
  91 #define BGX_SPUX_STATUS1                0x10008
  92 #define  SPU_STATUS1_RCV_LNK                    BIT_ULL(2)
  93 #define BGX_SPUX_STATUS2                0x10020
  94 #define  SPU_STATUS2_RCVFLT                     BIT_ULL(10)
  95 #define BGX_SPUX_BX_STATUS              0x10028
  96 #define  SPU_BX_STATUS_RX_ALIGN                 BIT_ULL(12)
  97 #define BGX_SPUX_BR_STATUS1             0x10030
  98 #define  SPU_BR_STATUS_BLK_LOCK                 BIT_ULL(0)
  99 #define  SPU_BR_STATUS_RCV_LNK                  BIT_ULL(12)
 100 #define BGX_SPUX_BR_PMD_CRTL            0x10068
 101 #define  SPU_PMD_CRTL_TRAIN_EN                  BIT_ULL(1)
 102 #define BGX_SPUX_BR_PMD_LP_CUP          0x10078
 103 #define BGX_SPUX_BR_PMD_LD_CUP          0x10088
 104 #define BGX_SPUX_BR_PMD_LD_REP          0x10090
 105 #define BGX_SPUX_FEC_CONTROL            0x100A0
 106 #define  SPU_FEC_CTL_FEC_EN                     BIT_ULL(0)
 107 #define  SPU_FEC_CTL_ERR_EN                     BIT_ULL(1)
 108 #define BGX_SPUX_AN_CONTROL             0x100C8
 109 #define  SPU_AN_CTL_AN_EN                       BIT_ULL(12)
 110 #define  SPU_AN_CTL_XNP_EN                      BIT_ULL(13)
 111 #define BGX_SPUX_AN_ADV                 0x100D8
 112 #define BGX_SPUX_MISC_CONTROL           0x10218
 113 #define  SPU_MISC_CTL_INTLV_RDISP               BIT_ULL(10)
 114 #define  SPU_MISC_CTL_RX_DIS                    BIT_ULL(12)
 115 #define BGX_SPUX_INT                    0x10220 /* +(0..3) << 20 */
 116 #define BGX_SPUX_INT_W1S                0x10228
 117 #define BGX_SPUX_INT_ENA_W1C            0x10230
 118 #define BGX_SPUX_INT_ENA_W1S            0x10238
 119 #define BGX_SPU_DBG_CONTROL             0x10300
 120 #define  SPU_DBG_CTL_AN_ARB_LINK_CHK_EN         BIT_ULL(18)
 121 #define  SPU_DBG_CTL_AN_NONCE_MCT_DIS           BIT_ULL(29)
 122
 123 #define BGX_SMUX_RX_INT                 0x20000
 124 #define BGX_SMUX_RX_JABBER              0x20030
 125 #define BGX_SMUX_RX_CTL                 0x20048
 126 #define  SMU_RX_CTL_STATUS                      (3ull << 0)
 127 #define BGX_SMUX_TX_APPEND              0x20100
 128 #define  SMU_TX_APPEND_FCS_D                    BIT_ULL(2)
 129 #define BGX_SMUX_TX_PAUSE_PKT_TIME      0x20110
 130 #define BGX_SMUX_TX_MIN_PKT             0x20118
 131 #define BGX_SMUX_TX_PAUSE_PKT_INTERVAL  0x20120
 132 #define BGX_SMUX_TX_PAUSE_ZERO          0x20138
 133 #define BGX_SMUX_TX_INT                 0x20140
 134 #define BGX_SMUX_TX_CTL                 0x20178
 135 #define  SMU_TX_CTL_DIC_EN                      BIT_ULL(0)
 136 #define  SMU_TX_CTL_UNI_EN                      BIT_ULL(1)
 137 #define  SMU_TX_CTL_LNK_STATUS                  (3ull << 4)
 138 #define BGX_SMUX_TX_THRESH              0x20180
 139 #define BGX_SMUX_CTL                    0x20200
 140 #define  SMU_CTL_RX_IDLE                        BIT_ULL(0)
 141 #define  SMU_CTL_TX_IDLE                        BIT_ULL(1)
 142 #define BGX_SMUX_CBFC_CTL               0x20218
 143 #define RX_EN                                   BIT_ULL(0)
 144 #define TX_EN                                   BIT_ULL(1)
 145 #define BCK_EN                                  BIT_ULL(2)
 146 #define DRP_EN                                  BIT_ULL(3)
 147
 148 #define BGX_GMP_PCS_MRX_CTL             0x30000
 149 #define  PCS_MRX_CTL_RST_AN                     BIT_ULL(9)
 150 #define  PCS_MRX_CTL_PWR_DN                     BIT_ULL(11)
 151 #define  PCS_MRX_CTL_AN_EN                      BIT_ULL(12)
 152 #define  PCS_MRX_CTL_LOOPBACK1                  BIT_ULL(14)
 153 #define  PCS_MRX_CTL_RESET                      BIT_ULL(15)
 154 #define BGX_GMP_PCS_MRX_STATUS          0x30008
 155 #define  PCS_MRX_STATUS_LINK                    BIT_ULL(2)
 156 #define  PCS_MRX_STATUS_AN_CPT                  BIT_ULL(5)
 157 #define BGX_GMP_PCS_ANX_ADV             0x30010
 158 #define BGX_GMP_PCS_ANX_AN_RESULTS      0x30020
 159 #define BGX_GMP_PCS_LINKX_TIMER         0x30040
 160 #define PCS_LINKX_TIMER_COUNT                   0x1E84
 161 #define BGX_GMP_PCS_SGM_AN_ADV          0x30068
 162 #define BGX_GMP_PCS_MISCX_CTL           0x30078
 163 #define  PCS_MISC_CTL_MODE                      BIT_ULL(8)
 164 #define  PCS_MISC_CTL_DISP_EN                   BIT_ULL(13)
 165 #define  PCS_MISC_CTL_GMX_ENO                   BIT_ULL(11)
 166 #define  PCS_MISC_CTL_SAMP_PT_MASK      0x7Full
 167 #define BGX_GMP_GMI_PRTX_CFG            0x38020
 168 #define  GMI_PORT_CFG_SPEED                     BIT_ULL(1)
 169 #define  GMI_PORT_CFG_DUPLEX                    BIT_ULL(2)
 170 #define  GMI_PORT_CFG_SLOT_TIME                 BIT_ULL(3)
 171 #define  GMI_PORT_CFG_SPEED_MSB                 BIT_ULL(8)
 172 #define BGX_GMP_GMI_RXX_JABBER          0x38038
 173 #define BGX_GMP_GMI_TXX_THRESH          0x38210
 174 #define BGX_GMP_GMI_TXX_APPEND          0x38218
 175 #define BGX_GMP_GMI_TXX_SLOT            0x38220
 176 #define BGX_GMP_GMI_TXX_BURST           0x38228
 177 #define BGX_GMP_GMI_TXX_MIN_PKT         0x38240
 178 #define BGX_GMP_GMI_TXX_SGMII_CTL       0x38300
 179
 180 #define BGX_MSIX_VEC_0_29_ADDR          0x400000 /* +(0..29) << 4 */
 181 #define BGX_MSIX_VEC_0_29_CTL           0x400008
 182 #define BGX_MSIX_PBA_0                  0x4F0000
 183
 184 /* MSI-X interrupts */
 185 #define BGX_MSIX_VECTORS        30
 186 #define BGX_LMAC_VEC_OFFSET     7
 187 #define BGX_MSIX_VEC_SHIFT      4
 188
 189 #define CMRX_INT                0
 190 #define SPUX_INT                1
 191 #define SMUX_RX_INT             2
 192 #define SMUX_TX_INT             3
 193 #define GMPX_PCS_INT            4
 194 #define GMPX_GMI_RX_INT         5
 195 #define GMPX_GMI_TX_INT         6
 196 #define CMR_MEM_INT             28
 197 #define SPU_MEM_INT             29
 198
 199 #define LMAC_INTR_LINK_UP       BIT(0)
 200 #define LMAC_INTR_LINK_DOWN     BIT(1)
 201
 202 /*  RX_DMAC_CTL configuration*/
 203 enum MCAST_MODE {
 204                 MCAST_MODE_REJECT,
 205                 MCAST_MODE_ACCEPT,
 206                 MCAST_MODE_CAM_FILTER,
 207                 RSVD
 208 };
 209
 210 #define BCAST_ACCEPT    1
 211 #define CAM_ACCEPT      1
 212
 213 void octeon_mdiobus_force_mod_depencency(void);
 214 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable);
 215 void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac);
 216 unsigned bgx_get_map(int node);
 217 int bgx_get_lmac_count(int node, int bgx);
 218 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid);
 219 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac);
 220 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status);
 221 void bgx_lmac_internal_loopback(int node, int bgx_idx,
 222                                 int lmac_idx, bool enable);
 223 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause);
 224 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause);
 225
 226 void xcv_init_hw(void);
 227 void xcv_setup_link(bool link_up, int link_speed);
 228
 229 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx);
 230 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx);
 231 #define BGX_RX_STATS_COUNT 11
 232 #define BGX_TX_STATS_COUNT 18
 233
 234 struct bgx_stats {
 235         u64 rx_stats[BGX_RX_STATS_COUNT];
 236         u64 tx_stats[BGX_TX_STATS_COUNT];
 237 };
 238
 239 enum LMAC_TYPE {
 240         BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */
 241         BGX_MODE_XAUI = 1,  /* 4 lanes, 3.125 Gbaud */
 242         BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */
 243         BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */
 244         BGX_MODE_XFI = 3,   /* 1 lane, 10.3125 Gbaud */
 245         BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */
 246         BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */
 247         BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */
 248         BGX_MODE_RGMII = 5,
 249         BGX_MODE_QSGMII = 6,
 250         BGX_MODE_INVALID = 7,
 251 };
 252
 253 #endif /* THUNDER_BGX_H */