2 * Atmel MACB Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #include <linux/phy.h>
14 #include <linux/ptp_clock_kernel.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/interrupt.h>
18 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
22 #define MACB_GREGS_NBR 16
23 #define MACB_GREGS_VERSION 2
24 #define MACB_MAX_QUEUES 8
26 /* MACB register offsets */
27 #define MACB_NCR 0x0000 /* Network Control */
28 #define MACB_NCFGR 0x0004 /* Network Config */
29 #define MACB_NSR 0x0008 /* Network Status */
30 #define MACB_TAR 0x000c /* AT91RM9200 only */
31 #define MACB_TCR 0x0010 /* AT91RM9200 only */
32 #define MACB_TSR 0x0014 /* Transmit Status */
33 #define MACB_RBQP 0x0018 /* RX Q Base Address */
34 #define MACB_TBQP 0x001c /* TX Q Base Address */
35 #define MACB_RSR 0x0020 /* Receive Status */
36 #define MACB_ISR 0x0024 /* Interrupt Status */
37 #define MACB_IER 0x0028 /* Interrupt Enable */
38 #define MACB_IDR 0x002c /* Interrupt Disable */
39 #define MACB_IMR 0x0030 /* Interrupt Mask */
40 #define MACB_MAN 0x0034 /* PHY Maintenance */
41 #define MACB_PTR 0x0038
42 #define MACB_PFR 0x003c
43 #define MACB_FTO 0x0040
44 #define MACB_SCF 0x0044
45 #define MACB_MCF 0x0048
46 #define MACB_FRO 0x004c
47 #define MACB_FCSE 0x0050
48 #define MACB_ALE 0x0054
49 #define MACB_DTF 0x0058
50 #define MACB_LCOL 0x005c
51 #define MACB_EXCOL 0x0060
52 #define MACB_TUND 0x0064
53 #define MACB_CSE 0x0068
54 #define MACB_RRE 0x006c
55 #define MACB_ROVR 0x0070
56 #define MACB_RSE 0x0074
57 #define MACB_ELE 0x0078
58 #define MACB_RJA 0x007c
59 #define MACB_USF 0x0080
60 #define MACB_STE 0x0084
61 #define MACB_RLE 0x0088
62 #define MACB_TPF 0x008c
63 #define MACB_HRB 0x0090
64 #define MACB_HRT 0x0094
65 #define MACB_SA1B 0x0098
66 #define MACB_SA1T 0x009c
67 #define MACB_SA2B 0x00a0
68 #define MACB_SA2T 0x00a4
69 #define MACB_SA3B 0x00a8
70 #define MACB_SA3T 0x00ac
71 #define MACB_SA4B 0x00b0
72 #define MACB_SA4T 0x00b4
73 #define MACB_TID 0x00b8
74 #define MACB_TPQ 0x00bc
75 #define MACB_USRIO 0x00c0
76 #define MACB_WOL 0x00c4
77 #define MACB_MID 0x00fc
78 #define MACB_TBQPH 0x04C8
79 #define MACB_RBQPH 0x04D4
81 /* GEM register offsets. */
82 #define GEM_NCFGR 0x0004 /* Network Config */
83 #define GEM_USRIO 0x000c /* User IO */
84 #define GEM_DMACFG 0x0010 /* DMA Configuration */
85 #define GEM_JML 0x0048 /* Jumbo Max Length */
86 #define GEM_HRB 0x0080 /* Hash Bottom */
87 #define GEM_HRT 0x0084 /* Hash Top */
88 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
89 #define GEM_SA1T 0x008C /* Specific1 Top */
90 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
91 #define GEM_SA2T 0x0094 /* Specific2 Top */
92 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
93 #define GEM_SA3T 0x009C /* Specific3 Top */
94 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
95 #define GEM_SA4T 0x00A4 /* Specific4 Top */
96 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
97 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
98 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
99 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
100 #define GEM_OTX 0x0100 /* Octets transmitted */
101 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
102 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
103 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
104 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
105 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
106 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
107 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
108 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
109 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
110 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
111 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
112 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
113 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
114 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
115 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
116 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
117 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
118 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
119 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
120 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
121 #define GEM_ORX 0x0150 /* Octets received */
122 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
123 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
124 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
125 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
126 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
127 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
128 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
129 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
130 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
131 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
132 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
133 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
134 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
135 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
136 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
137 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
138 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
139 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
140 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
141 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
142 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
143 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
144 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
145 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
146 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
147 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
148 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
149 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
150 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
151 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
152 #define GEM_TI 0x01dc /* 1588 Timer Increment */
153 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
154 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
155 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
156 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
157 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
158 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
159 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
160 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
161 #define GEM_DCFG1 0x0280 /* Design Config 1 */
162 #define GEM_DCFG2 0x0284 /* Design Config 2 */
163 #define GEM_DCFG3 0x0288 /* Design Config 3 */
164 #define GEM_DCFG4 0x028c /* Design Config 4 */
165 #define GEM_DCFG5 0x0290 /* Design Config 5 */
166 #define GEM_DCFG6 0x0294 /* Design Config 6 */
167 #define GEM_DCFG7 0x0298 /* Design Config 7 */
168 #define GEM_DCFG8 0x029C /* Design Config 8 */
169 #define GEM_DCFG10 0x02A4 /* Design Config 10 */
171 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
172 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
174 /* Screener Type 2 match registers */
175 #define GEM_SCRT2 0x540
177 /* EtherType registers */
178 #define GEM_ETHT 0x06E0
180 /* Type 2 compare registers */
181 #define GEM_T2CMPW0 0x0700
182 #define GEM_T2CMPW1 0x0704
183 #define T2CMP_OFST(t2idx) (t2idx * 2)
185 /* type 2 compare registers
186 * each location requires 3 compare regs
188 #define GEM_IP4SRC_CMP(idx) (idx * 3)
189 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
190 #define GEM_PORT_CMP(idx) (idx * 3 + 2)
192 /* Which screening type 2 EtherType register will be used (0 - 7) */
195 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
196 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
197 #define GEM_TBQPH(hw_q) (0x04C8)
198 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
199 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
200 #define GEM_RBQPH(hw_q) (0x04D4)
201 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
202 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
203 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
205 /* Bitfields in NCR */
206 #define MACB_LB_OFFSET 0 /* reserved */
207 #define MACB_LB_SIZE 1
208 #define MACB_LLB_OFFSET 1 /* Loop back local */
209 #define MACB_LLB_SIZE 1
210 #define MACB_RE_OFFSET 2 /* Receive enable */
211 #define MACB_RE_SIZE 1
212 #define MACB_TE_OFFSET 3 /* Transmit enable */
213 #define MACB_TE_SIZE 1
214 #define MACB_MPE_OFFSET 4 /* Management port enable */
215 #define MACB_MPE_SIZE 1
216 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
217 #define MACB_CLRSTAT_SIZE 1
218 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
219 #define MACB_INCSTAT_SIZE 1
220 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
221 #define MACB_WESTAT_SIZE 1
222 #define MACB_BP_OFFSET 8 /* Back pressure */
223 #define MACB_BP_SIZE 1
224 #define MACB_TSTART_OFFSET 9 /* Start transmission */
225 #define MACB_TSTART_SIZE 1
226 #define MACB_THALT_OFFSET 10 /* Transmit halt */
227 #define MACB_THALT_SIZE 1
228 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
229 #define MACB_NCR_TPF_SIZE 1
230 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
231 #define MACB_TZQ_SIZE 1
232 #define MACB_SRTSM_OFFSET 15
233 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
234 #define MACB_OSSMODE_SIZE 1
236 /* Bitfields in NCFGR */
237 #define MACB_SPD_OFFSET 0 /* Speed */
238 #define MACB_SPD_SIZE 1
239 #define MACB_FD_OFFSET 1 /* Full duplex */
240 #define MACB_FD_SIZE 1
241 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
242 #define MACB_BIT_RATE_SIZE 1
243 #define MACB_JFRAME_OFFSET 3 /* reserved */
244 #define MACB_JFRAME_SIZE 1
245 #define MACB_CAF_OFFSET 4 /* Copy all frames */
246 #define MACB_CAF_SIZE 1
247 #define MACB_NBC_OFFSET 5 /* No broadcast */
248 #define MACB_NBC_SIZE 1
249 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
250 #define MACB_NCFGR_MTI_SIZE 1
251 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
252 #define MACB_UNI_SIZE 1
253 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
254 #define MACB_BIG_SIZE 1
255 #define MACB_EAE_OFFSET 9 /* External address match enable */
256 #define MACB_EAE_SIZE 1
257 #define MACB_CLK_OFFSET 10
258 #define MACB_CLK_SIZE 2
259 #define MACB_RTY_OFFSET 12 /* Retry test */
260 #define MACB_RTY_SIZE 1
261 #define MACB_PAE_OFFSET 13 /* Pause enable */
262 #define MACB_PAE_SIZE 1
263 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
264 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
265 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
266 #define MACB_RBOF_SIZE 2
267 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
268 #define MACB_RLCE_SIZE 1
269 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
270 #define MACB_DRFCS_SIZE 1
271 #define MACB_EFRHD_OFFSET 18
272 #define MACB_EFRHD_SIZE 1
273 #define MACB_IRXFCS_OFFSET 19
274 #define MACB_IRXFCS_SIZE 1
276 /* GEM specific NCFGR bitfields. */
277 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
278 #define GEM_GBE_SIZE 1
279 #define GEM_PCSSEL_OFFSET 11
280 #define GEM_PCSSEL_SIZE 1
281 #define GEM_CLK_OFFSET 18 /* MDC clock division */
282 #define GEM_CLK_SIZE 3
283 #define GEM_DBW_OFFSET 21 /* Data bus width */
284 #define GEM_DBW_SIZE 2
285 #define GEM_RXCOEN_OFFSET 24
286 #define GEM_RXCOEN_SIZE 1
287 #define GEM_SGMIIEN_OFFSET 27
288 #define GEM_SGMIIEN_SIZE 1
291 /* Constants for data bus width. */
292 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
293 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
294 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
296 /* Bitfields in DMACFG. */
297 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
298 #define GEM_FBLDO_SIZE 5
299 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
300 #define GEM_ENDIA_DESC_SIZE 1
301 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
302 #define GEM_ENDIA_PKT_SIZE 1
303 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
304 #define GEM_RXBMS_SIZE 2
305 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
306 #define GEM_TXPBMS_SIZE 1
307 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
308 #define GEM_TXCOEN_SIZE 1
309 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
310 #define GEM_RXBS_SIZE 8
311 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
312 #define GEM_DDRP_SIZE 1
313 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
314 #define GEM_RXEXT_SIZE 1
315 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
316 #define GEM_TXEXT_SIZE 1
317 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
318 #define GEM_ADDR64_SIZE 1
321 /* Bitfields in NSR */
322 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
323 #define MACB_NSR_LINK_SIZE 1
324 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
325 #define MACB_MDIO_SIZE 1
326 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
327 #define MACB_IDLE_SIZE 1
329 /* Bitfields in TSR */
330 #define MACB_UBR_OFFSET 0 /* Used bit read */
331 #define MACB_UBR_SIZE 1
332 #define MACB_COL_OFFSET 1 /* Collision occurred */
333 #define MACB_COL_SIZE 1
334 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
335 #define MACB_TSR_RLE_SIZE 1
336 #define MACB_TGO_OFFSET 3 /* Transmit go */
337 #define MACB_TGO_SIZE 1
338 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
339 #define MACB_BEX_SIZE 1
340 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
341 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
342 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
343 #define MACB_COMP_SIZE 1
344 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
345 #define MACB_UND_SIZE 1
347 /* Bitfields in RSR */
348 #define MACB_BNA_OFFSET 0 /* Buffer not available */
349 #define MACB_BNA_SIZE 1
350 #define MACB_REC_OFFSET 1 /* Frame received */
351 #define MACB_REC_SIZE 1
352 #define MACB_OVR_OFFSET 2 /* Receive overrun */
353 #define MACB_OVR_SIZE 1
355 /* Bitfields in ISR/IER/IDR/IMR */
356 #define MACB_MFD_OFFSET 0 /* Management frame sent */
357 #define MACB_MFD_SIZE 1
358 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
359 #define MACB_RCOMP_SIZE 1
360 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
361 #define MACB_RXUBR_SIZE 1
362 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
363 #define MACB_TXUBR_SIZE 1
364 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
365 #define MACB_ISR_TUND_SIZE 1
366 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
367 #define MACB_ISR_RLE_SIZE 1
368 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
369 #define MACB_TXERR_SIZE 1
370 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
371 #define MACB_TCOMP_SIZE 1
372 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
373 #define MACB_ISR_LINK_SIZE 1
374 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
375 #define MACB_ISR_ROVR_SIZE 1
376 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
377 #define MACB_HRESP_SIZE 1
378 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
379 #define MACB_PFR_SIZE 1
380 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
381 #define MACB_PTZ_SIZE 1
382 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
383 #define MACB_WOL_SIZE 1
384 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
385 #define MACB_DRQFR_SIZE 1
386 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
387 #define MACB_SFR_SIZE 1
388 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
389 #define MACB_DRQFT_SIZE 1
390 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
391 #define MACB_SFT_SIZE 1
392 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
393 #define MACB_PDRQFR_SIZE 1
394 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
395 #define MACB_PDRSFR_SIZE 1
396 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
397 #define MACB_PDRQFT_SIZE 1
398 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
399 #define MACB_PDRSFT_SIZE 1
400 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
401 #define MACB_SRI_SIZE 1
403 /* Timer increment fields */
404 #define MACB_TI_CNS_OFFSET 0
405 #define MACB_TI_CNS_SIZE 8
406 #define MACB_TI_ACNS_OFFSET 8
407 #define MACB_TI_ACNS_SIZE 8
408 #define MACB_TI_NIT_OFFSET 16
409 #define MACB_TI_NIT_SIZE 8
411 /* Bitfields in MAN */
412 #define MACB_DATA_OFFSET 0 /* data */
413 #define MACB_DATA_SIZE 16
414 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
415 #define MACB_CODE_SIZE 2
416 #define MACB_REGA_OFFSET 18 /* Register address */
417 #define MACB_REGA_SIZE 5
418 #define MACB_PHYA_OFFSET 23 /* PHY address */
419 #define MACB_PHYA_SIZE 5
420 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
421 #define MACB_RW_SIZE 2
422 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
423 #define MACB_SOF_SIZE 2
425 /* Bitfields in USRIO (AVR32) */
426 #define MACB_MII_OFFSET 0
427 #define MACB_MII_SIZE 1
428 #define MACB_EAM_OFFSET 1
429 #define MACB_EAM_SIZE 1
430 #define MACB_TX_PAUSE_OFFSET 2
431 #define MACB_TX_PAUSE_SIZE 1
432 #define MACB_TX_PAUSE_ZERO_OFFSET 3
433 #define MACB_TX_PAUSE_ZERO_SIZE 1
435 /* Bitfields in USRIO (AT91) */
436 #define MACB_RMII_OFFSET 0
437 #define MACB_RMII_SIZE 1
438 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
439 #define GEM_RGMII_SIZE 1
440 #define MACB_CLKEN_OFFSET 1
441 #define MACB_CLKEN_SIZE 1
443 /* Bitfields in WOL */
444 #define MACB_IP_OFFSET 0
445 #define MACB_IP_SIZE 16
446 #define MACB_MAG_OFFSET 16
447 #define MACB_MAG_SIZE 1
448 #define MACB_ARP_OFFSET 17
449 #define MACB_ARP_SIZE 1
450 #define MACB_SA1_OFFSET 18
451 #define MACB_SA1_SIZE 1
452 #define MACB_WOL_MTI_OFFSET 19
453 #define MACB_WOL_MTI_SIZE 1
455 /* Bitfields in MID */
456 #define MACB_IDNUM_OFFSET 16
457 #define MACB_IDNUM_SIZE 12
458 #define MACB_REV_OFFSET 0
459 #define MACB_REV_SIZE 16
461 /* Bitfields in DCFG1. */
462 #define GEM_IRQCOR_OFFSET 23
463 #define GEM_IRQCOR_SIZE 1
464 #define GEM_DBWDEF_OFFSET 25
465 #define GEM_DBWDEF_SIZE 3
467 /* Bitfields in DCFG2. */
468 #define GEM_RX_PKT_BUFF_OFFSET 20
469 #define GEM_RX_PKT_BUFF_SIZE 1
470 #define GEM_TX_PKT_BUFF_OFFSET 21
471 #define GEM_TX_PKT_BUFF_SIZE 1
474 /* Bitfields in DCFG5. */
475 #define GEM_TSU_OFFSET 8
476 #define GEM_TSU_SIZE 1
478 /* Bitfields in DCFG6. */
479 #define GEM_PBUF_LSO_OFFSET 27
480 #define GEM_PBUF_LSO_SIZE 1
481 #define GEM_DAW64_OFFSET 23
482 #define GEM_DAW64_SIZE 1
484 /* Bitfields in DCFG8. */
485 #define GEM_T1SCR_OFFSET 24
486 #define GEM_T1SCR_SIZE 8
487 #define GEM_T2SCR_OFFSET 16
488 #define GEM_T2SCR_SIZE 8
489 #define GEM_SCR2ETH_OFFSET 8
490 #define GEM_SCR2ETH_SIZE 8
491 #define GEM_SCR2CMP_OFFSET 0
492 #define GEM_SCR2CMP_SIZE 8
494 /* Bitfields in DCFG10 */
495 #define GEM_TXBD_RDBUFF_OFFSET 12
496 #define GEM_TXBD_RDBUFF_SIZE 4
497 #define GEM_RXBD_RDBUFF_OFFSET 8
498 #define GEM_RXBD_RDBUFF_SIZE 4
500 /* Bitfields in TISUBN */
501 #define GEM_SUBNSINCR_OFFSET 0
502 #define GEM_SUBNSINCR_SIZE 16
504 /* Bitfields in TI */
505 #define GEM_NSINCR_OFFSET 0
506 #define GEM_NSINCR_SIZE 8
508 /* Bitfields in TSH */
509 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
510 #define GEM_TSH_SIZE 16
512 /* Bitfields in TSL */
513 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
514 #define GEM_TSL_SIZE 32
516 /* Bitfields in TN */
517 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
518 #define GEM_TN_SIZE 30
520 /* Bitfields in TXBDCTRL */
521 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
522 #define GEM_TXTSMODE_SIZE 2
524 /* Bitfields in RXBDCTRL */
525 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
526 #define GEM_RXTSMODE_SIZE 2
528 /* Bitfields in SCRT2 */
529 #define GEM_QUEUE_OFFSET 0 /* Queue Number */
530 #define GEM_QUEUE_SIZE 4
531 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
532 #define GEM_VLANPR_SIZE 3
533 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
534 #define GEM_VLANEN_SIZE 1
535 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
536 #define GEM_ETHT2IDX_SIZE 3
537 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
538 #define GEM_ETHTEN_SIZE 1
539 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
540 #define GEM_CMPA_SIZE 5
541 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
542 #define GEM_CMPAEN_SIZE 1
543 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
544 #define GEM_CMPB_SIZE 5
545 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
546 #define GEM_CMPBEN_SIZE 1
547 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
548 #define GEM_CMPC_SIZE 5
549 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
550 #define GEM_CMPCEN_SIZE 1
552 /* Bitfields in ETHT */
553 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
554 #define GEM_ETHTCMP_SIZE 16
556 /* Bitfields in T2CMPW0 */
557 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
558 #define GEM_T2CMP_SIZE 16
559 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
560 #define GEM_T2MASK_SIZE 16
562 /* Bitfields in T2CMPW1 */
563 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
564 #define GEM_T2DISMSK_SIZE 1
565 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
566 #define GEM_T2CMPOFST_SIZE 2
567 #define GEM_T2OFST_OFFSET 0 /* offset value */
568 #define GEM_T2OFST_SIZE 7
570 /* Offset for screener type 2 compare values (T2CMPOFST).
571 * Note the offset is applied after the specified point,
572 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
573 * of 12 bytes from this would be the source IP address in an IP header
575 #define GEM_T2COMPOFST_SOF 0
576 #define GEM_T2COMPOFST_ETYPE 1
577 #define GEM_T2COMPOFST_IPHDR 2
578 #define GEM_T2COMPOFST_TCPUDP 3
580 /* offset from EtherType to IP address */
581 #define ETYPE_SRCIP_OFFSET 12
582 #define ETYPE_DSTIP_OFFSET 16
584 /* offset from IP header to port */
585 #define IPHDR_SRCPORT_OFFSET 0
586 #define IPHDR_DSTPORT_OFFSET 2
588 /* Transmit DMA buffer descriptor Word 1 */
589 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
590 #define GEM_DMA_TXVALID_SIZE 1
592 /* Receive DMA buffer descriptor Word 0 */
593 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
594 #define GEM_DMA_RXVALID_SIZE 1
596 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
597 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
598 #define GEM_DMA_SECL_SIZE 2
599 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
600 #define GEM_DMA_NSEC_SIZE 30
602 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
604 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
605 * Old hardware supports only 6 bit precision but it is enough for PTP.
606 * Less accuracy is used always instead of checking hardware version.
608 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
609 #define GEM_DMA_SECH_SIZE 4
610 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
611 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
612 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
614 /* Bitfields in ADJ */
615 #define GEM_ADDSUB_OFFSET 31
616 #define GEM_ADDSUB_SIZE 1
617 /* Constants for CLK */
618 #define MACB_CLK_DIV8 0
619 #define MACB_CLK_DIV16 1
620 #define MACB_CLK_DIV32 2
621 #define MACB_CLK_DIV64 3
623 /* GEM specific constants for CLK. */
624 #define GEM_CLK_DIV8 0
625 #define GEM_CLK_DIV16 1
626 #define GEM_CLK_DIV32 2
627 #define GEM_CLK_DIV48 3
628 #define GEM_CLK_DIV64 4
629 #define GEM_CLK_DIV96 5
631 /* Constants for MAN register */
632 #define MACB_MAN_SOF 1
633 #define MACB_MAN_WRITE 1
634 #define MACB_MAN_READ 2
635 #define MACB_MAN_CODE 2
637 /* Capability mask bits */
638 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
639 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
640 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
641 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
642 #define MACB_CAPS_USRIO_DISABLED 0x00000010
643 #define MACB_CAPS_JUMBO 0x00000020
644 #define MACB_CAPS_GEM_HAS_PTP 0x00000040
645 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
646 #define MACB_CAPS_FIFO_MODE 0x10000000
647 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
648 #define MACB_CAPS_SG_DISABLED 0x40000000
649 #define MACB_CAPS_MACB_IS_GEM 0x80000000
652 #define MACB_LSO_UFO_ENABLE 0x01
653 #define MACB_LSO_TSO_ENABLE 0x02
655 /* Bit manipulation macros */
656 #define MACB_BIT(name) \
657 (1 << MACB_##name##_OFFSET)
658 #define MACB_BF(name,value) \
659 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
660 << MACB_##name##_OFFSET)
661 #define MACB_BFEXT(name,value)\
662 (((value) >> MACB_##name##_OFFSET) \
663 & ((1 << MACB_##name##_SIZE) - 1))
664 #define MACB_BFINS(name,value,old) \
665 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
666 << MACB_##name##_OFFSET)) \
667 | MACB_BF(name,value))
669 #define GEM_BIT(name) \
670 (1 << GEM_##name##_OFFSET)
671 #define GEM_BF(name, value) \
672 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
673 << GEM_##name##_OFFSET)
674 #define GEM_BFEXT(name, value)\
675 (((value) >> GEM_##name##_OFFSET) \
676 & ((1 << GEM_##name##_SIZE) - 1))
677 #define GEM_BFINS(name, value, old) \
678 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
679 << GEM_##name##_OFFSET)) \
680 | GEM_BF(name, value))
682 /* Register access macros */
683 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
684 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
685 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
686 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
687 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
688 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
689 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
690 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
692 #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
694 /* Conditional GEM/MACB macros. These perform the operation to the correct
695 * register dependent on whether the device is a GEM or a MACB. For registers
696 * and bitfields that are common across both devices, use macb_{read,write}l
697 * to avoid the cost of the conditional.
699 #define macb_or_gem_writel(__bp, __reg, __value) \
701 if (macb_is_gem((__bp))) \
702 gem_writel((__bp), __reg, __value); \
704 macb_writel((__bp), __reg, __value); \
707 #define macb_or_gem_readl(__bp, __reg) \
710 if (macb_is_gem((__bp))) \
711 __v = gem_readl((__bp), __reg); \
713 __v = macb_readl((__bp), __reg); \
717 /* struct macb_dma_desc - Hardware DMA descriptor
718 * @addr: DMA address of data buffer
719 * @ctrl: Control and status bits
721 struct macb_dma_desc {
727 #define HW_DMA_CAP_32B 0
728 #define HW_DMA_CAP_64B (1 << 0)
729 #define HW_DMA_CAP_PTP (1 << 1)
730 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
732 struct macb_dma_desc_64 {
737 struct macb_dma_desc_ptp {
744 struct macb_dma_desc_ptp desc_ptp;
748 /* DMA descriptor bitfields */
749 #define MACB_RX_USED_OFFSET 0
750 #define MACB_RX_USED_SIZE 1
751 #define MACB_RX_WRAP_OFFSET 1
752 #define MACB_RX_WRAP_SIZE 1
753 #define MACB_RX_WADDR_OFFSET 2
754 #define MACB_RX_WADDR_SIZE 30
756 #define MACB_RX_FRMLEN_OFFSET 0
757 #define MACB_RX_FRMLEN_SIZE 12
758 #define MACB_RX_OFFSET_OFFSET 12
759 #define MACB_RX_OFFSET_SIZE 2
760 #define MACB_RX_SOF_OFFSET 14
761 #define MACB_RX_SOF_SIZE 1
762 #define MACB_RX_EOF_OFFSET 15
763 #define MACB_RX_EOF_SIZE 1
764 #define MACB_RX_CFI_OFFSET 16
765 #define MACB_RX_CFI_SIZE 1
766 #define MACB_RX_VLAN_PRI_OFFSET 17
767 #define MACB_RX_VLAN_PRI_SIZE 3
768 #define MACB_RX_PRI_TAG_OFFSET 20
769 #define MACB_RX_PRI_TAG_SIZE 1
770 #define MACB_RX_VLAN_TAG_OFFSET 21
771 #define MACB_RX_VLAN_TAG_SIZE 1
772 #define MACB_RX_TYPEID_MATCH_OFFSET 22
773 #define MACB_RX_TYPEID_MATCH_SIZE 1
774 #define MACB_RX_SA4_MATCH_OFFSET 23
775 #define MACB_RX_SA4_MATCH_SIZE 1
776 #define MACB_RX_SA3_MATCH_OFFSET 24
777 #define MACB_RX_SA3_MATCH_SIZE 1
778 #define MACB_RX_SA2_MATCH_OFFSET 25
779 #define MACB_RX_SA2_MATCH_SIZE 1
780 #define MACB_RX_SA1_MATCH_OFFSET 26
781 #define MACB_RX_SA1_MATCH_SIZE 1
782 #define MACB_RX_EXT_MATCH_OFFSET 28
783 #define MACB_RX_EXT_MATCH_SIZE 1
784 #define MACB_RX_UHASH_MATCH_OFFSET 29
785 #define MACB_RX_UHASH_MATCH_SIZE 1
786 #define MACB_RX_MHASH_MATCH_OFFSET 30
787 #define MACB_RX_MHASH_MATCH_SIZE 1
788 #define MACB_RX_BROADCAST_OFFSET 31
789 #define MACB_RX_BROADCAST_SIZE 1
791 #define MACB_RX_FRMLEN_MASK 0xFFF
792 #define MACB_RX_JFRMLEN_MASK 0x3FFF
794 /* RX checksum offload disabled: bit 24 clear in NCFGR */
795 #define GEM_RX_TYPEID_MATCH_OFFSET 22
796 #define GEM_RX_TYPEID_MATCH_SIZE 2
798 /* RX checksum offload enabled: bit 24 set in NCFGR */
799 #define GEM_RX_CSUM_OFFSET 22
800 #define GEM_RX_CSUM_SIZE 2
802 #define MACB_TX_FRMLEN_OFFSET 0
803 #define MACB_TX_FRMLEN_SIZE 11
804 #define MACB_TX_LAST_OFFSET 15
805 #define MACB_TX_LAST_SIZE 1
806 #define MACB_TX_NOCRC_OFFSET 16
807 #define MACB_TX_NOCRC_SIZE 1
808 #define MACB_MSS_MFS_OFFSET 16
809 #define MACB_MSS_MFS_SIZE 14
810 #define MACB_TX_LSO_OFFSET 17
811 #define MACB_TX_LSO_SIZE 2
812 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
813 #define MACB_TX_TCP_SEQ_SRC_SIZE 1
814 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
815 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
816 #define MACB_TX_UNDERRUN_OFFSET 28
817 #define MACB_TX_UNDERRUN_SIZE 1
818 #define MACB_TX_ERROR_OFFSET 29
819 #define MACB_TX_ERROR_SIZE 1
820 #define MACB_TX_WRAP_OFFSET 30
821 #define MACB_TX_WRAP_SIZE 1
822 #define MACB_TX_USED_OFFSET 31
823 #define MACB_TX_USED_SIZE 1
825 #define GEM_TX_FRMLEN_OFFSET 0
826 #define GEM_TX_FRMLEN_SIZE 14
828 /* Buffer descriptor constants */
829 #define GEM_RX_CSUM_NONE 0
830 #define GEM_RX_CSUM_IP_ONLY 1
831 #define GEM_RX_CSUM_IP_TCP 2
832 #define GEM_RX_CSUM_IP_UDP 3
834 /* limit RX checksum offload to TCP and UDP packets */
835 #define GEM_RX_CSUM_CHECKED_MASK 2
837 /* struct macb_tx_skb - data about an skb which is being transmitted
838 * @skb: skb currently being transmitted, only set for the last buffer
840 * @mapping: DMA address of the skb's fragment buffer
841 * @size: size of the DMA mapped buffer
842 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
843 * false when buffer was mapped with dma_map_single()
852 /* Hardware-collected statistics. Used when updating the network
853 * device stats by a periodic timer.
859 u32 tx_multiple_cols;
865 u32 tx_excessive_cols;
867 u32 tx_carrier_errors;
868 u32 rx_resource_errors;
870 u32 rx_symbol_errors;
871 u32 rx_oversize_pkts;
873 u32 rx_undersize_pkts;
875 u32 rx_length_mismatch;
883 u32 tx_broadcast_frames;
884 u32 tx_multicast_frames;
886 u32 tx_64_byte_frames;
887 u32 tx_65_127_byte_frames;
888 u32 tx_128_255_byte_frames;
889 u32 tx_256_511_byte_frames;
890 u32 tx_512_1023_byte_frames;
891 u32 tx_1024_1518_byte_frames;
892 u32 tx_greater_than_1518_byte_frames;
894 u32 tx_single_collision_frames;
895 u32 tx_multiple_collision_frames;
896 u32 tx_excessive_collisions;
897 u32 tx_late_collisions;
898 u32 tx_deferred_frames;
899 u32 tx_carrier_sense_errors;
903 u32 rx_broadcast_frames;
904 u32 rx_multicast_frames;
906 u32 rx_64_byte_frames;
907 u32 rx_65_127_byte_frames;
908 u32 rx_128_255_byte_frames;
909 u32 rx_256_511_byte_frames;
910 u32 rx_512_1023_byte_frames;
911 u32 rx_1024_1518_byte_frames;
912 u32 rx_greater_than_1518_byte_frames;
913 u32 rx_undersized_frames;
914 u32 rx_oversize_frames;
916 u32 rx_frame_check_sequence_errors;
917 u32 rx_length_field_frame_errors;
918 u32 rx_symbol_errors;
919 u32 rx_alignment_errors;
920 u32 rx_resource_errors;
922 u32 rx_ip_header_checksum_errors;
923 u32 rx_tcp_checksum_errors;
924 u32 rx_udp_checksum_errors;
927 /* Describes the name and offset of an individual statistic register, as
928 * returned by `ethtool -S`. Also describes which net_device_stats statistics
929 * this register should contribute to.
931 struct gem_statistic {
932 char stat_string[ETH_GSTRING_LEN];
937 /* Bitfield defs for net_device_stat statistics */
938 #define GEM_NDS_RXERR_OFFSET 0
939 #define GEM_NDS_RXLENERR_OFFSET 1
940 #define GEM_NDS_RXOVERERR_OFFSET 2
941 #define GEM_NDS_RXCRCERR_OFFSET 3
942 #define GEM_NDS_RXFRAMEERR_OFFSET 4
943 #define GEM_NDS_RXFIFOERR_OFFSET 5
944 #define GEM_NDS_TXERR_OFFSET 6
945 #define GEM_NDS_TXABORTEDERR_OFFSET 7
946 #define GEM_NDS_TXCARRIERERR_OFFSET 8
947 #define GEM_NDS_TXFIFOERR_OFFSET 9
948 #define GEM_NDS_COLLISIONS_OFFSET 10
950 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
951 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
952 .stat_string = title, \
953 .offset = GEM_##name, \
957 /* list of gem statistic registers. The names MUST match the
958 * corresponding GEM_* definitions.
960 static const struct gem_statistic gem_statistics[] = {
961 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
962 GEM_STAT_TITLE(TXCNT, "tx_frames"),
963 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
964 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
965 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
966 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
967 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
968 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
969 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
970 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
971 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
972 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
973 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
974 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
975 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
976 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
977 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
978 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
979 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
981 GEM_BIT(NDS_TXABORTEDERR)|
982 GEM_BIT(NDS_COLLISIONS)),
983 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
984 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
985 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
986 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
987 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
988 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
989 GEM_STAT_TITLE(RXCNT, "rx_frames"),
990 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
991 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
992 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
993 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
994 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
995 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
996 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
997 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
998 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
999 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1000 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1001 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1002 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1003 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1004 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1005 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1006 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1007 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1008 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1009 GEM_BIT(NDS_RXERR)),
1010 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1011 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1012 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1013 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1014 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1015 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1016 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1017 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1018 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1019 GEM_BIT(NDS_RXERR)),
1020 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1021 GEM_BIT(NDS_RXERR)),
1022 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1023 GEM_BIT(NDS_RXERR)),
1026 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1028 #define QUEUE_STAT_TITLE(title) { \
1029 .stat_string = title, \
1032 /* per queue statistics, each should be unsigned long type */
1033 struct queue_stats {
1035 unsigned long first;
1036 unsigned long rx_packets;
1038 unsigned long rx_bytes;
1039 unsigned long rx_dropped;
1040 unsigned long tx_packets;
1041 unsigned long tx_bytes;
1042 unsigned long tx_dropped;
1045 static const struct gem_statistic queue_statistics[] = {
1046 QUEUE_STAT_TITLE("rx_packets"),
1047 QUEUE_STAT_TITLE("rx_bytes"),
1048 QUEUE_STAT_TITLE("rx_dropped"),
1049 QUEUE_STAT_TITLE("tx_packets"),
1050 QUEUE_STAT_TITLE("tx_bytes"),
1051 QUEUE_STAT_TITLE("tx_dropped"),
1054 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1059 struct macb_or_gem_ops {
1060 int (*mog_alloc_rx_buffers)(struct macb *bp);
1061 void (*mog_free_rx_buffers)(struct macb *bp);
1062 void (*mog_init_rings)(struct macb *bp);
1063 int (*mog_rx)(struct macb_queue *queue, int budget);
1066 /* MACB-PTP interface: adapt to platform needs. */
1067 struct macb_ptp_info {
1068 void (*ptp_init)(struct net_device *ndev);
1069 void (*ptp_remove)(struct net_device *ndev);
1070 s32 (*get_ptp_max_adj)(void);
1071 unsigned int (*get_tsu_rate)(struct macb *bp);
1072 int (*get_ts_info)(struct net_device *dev,
1073 struct ethtool_ts_info *info);
1074 int (*get_hwtst)(struct net_device *netdev,
1076 int (*set_hwtst)(struct net_device *netdev,
1077 struct ifreq *ifr, int cmd);
1080 struct macb_config {
1082 unsigned int dma_burst_length;
1083 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1084 struct clk **hclk, struct clk **tx_clk,
1085 struct clk **rx_clk);
1086 int (*init)(struct platform_device *pdev);
1109 unsigned int tx_head, tx_tail;
1110 struct macb_dma_desc *tx_ring;
1111 struct macb_tx_skb *tx_skb;
1112 dma_addr_t tx_ring_dma;
1113 struct work_struct tx_error_task;
1115 dma_addr_t rx_ring_dma;
1116 dma_addr_t rx_buffers_dma;
1117 unsigned int rx_tail;
1118 unsigned int rx_prepared_head;
1119 struct macb_dma_desc *rx_ring;
1120 struct sk_buff **rx_skbuff;
1122 struct napi_struct napi;
1123 struct queue_stats stats;
1125 #ifdef CONFIG_MACB_USE_HWSTAMP
1126 struct work_struct tx_ts_task;
1127 unsigned int tx_ts_head, tx_ts_tail;
1128 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
1132 struct ethtool_rx_fs_item {
1133 struct ethtool_rx_flow_spec fs;
1134 struct list_head list;
1137 struct ethtool_rx_fs_list {
1138 struct list_head list;
1146 /* hardware IO accessors */
1147 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1148 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1150 size_t rx_buffer_size;
1152 unsigned int rx_ring_size;
1153 unsigned int tx_ring_size;
1155 unsigned int num_queues;
1156 unsigned int queue_mask;
1157 struct macb_queue queues[MACB_MAX_QUEUES];
1160 struct platform_device *pdev;
1165 struct net_device *dev;
1167 struct macb_stats macb;
1168 struct gem_stats gem;
1171 struct macb_or_gem_ops macbgem_ops;
1173 struct mii_bus *mii_bus;
1174 struct device_node *phy_node;
1180 unsigned int dma_burst_length;
1182 phy_interface_t phy_interface;
1184 /* AT91RM9200 transmit */
1185 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
1186 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
1187 int skb_length; /* saved skb length for pci_unmap_single */
1188 unsigned int max_tx_length;
1190 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1192 unsigned int rx_frm_len_mask;
1193 unsigned int jumbo_max_len;
1197 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1198 #ifdef MACB_EXT_DESC
1201 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1202 unsigned int tsu_rate;
1203 struct ptp_clock *ptp_clock;
1204 struct ptp_clock_info ptp_clock_info;
1205 struct tsu_incr tsu_incr;
1206 struct hwtstamp_config tstamp_config;
1208 /* RX queue filer rule set*/
1209 struct ethtool_rx_fs_list rx_fs_list;
1210 spinlock_t rx_fs_lock;
1211 unsigned int max_tuples;
1213 struct tasklet_struct hresp_err_tasklet;
1215 int rx_bd_rd_prefetch;
1216 int tx_bd_rd_prefetch;
1219 #ifdef CONFIG_MACB_USE_HWSTAMP
1220 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1221 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1222 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1224 enum macb_bd_control {
1226 TSTAMP_FRAME_PTP_EVENT_ONLY,
1227 TSTAMP_ALL_PTP_FRAMES,
1231 void gem_ptp_init(struct net_device *ndev);
1232 void gem_ptp_remove(struct net_device *ndev);
1233 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1234 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1235 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1237 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1240 return gem_ptp_txstamp(queue, skb, desc);
1243 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1245 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1248 gem_ptp_rxstamp(bp, skb, desc);
1250 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1251 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1253 static inline void gem_ptp_init(struct net_device *ndev) { }
1254 static inline void gem_ptp_remove(struct net_device *ndev) { }
1256 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1261 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1264 static inline bool macb_is_gem(struct macb *bp)
1266 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1269 static inline bool gem_has_ptp(struct macb *bp)
1271 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1274 #endif /* _MACB_H */
git.samba.org / sfrench / cifs-2.6.git / blob