1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
10 * DO NOT MODIFY!!! This file is automatically generated.
16 /* hwrm_cmd_hdr (size:128b/16B) */
25 /* hwrm_resp_hdr (size:64b/8B) */
26 struct hwrm_resp_hdr {
33 #define CMD_DISCR_TLV_ENCAP 0x8000UL
34 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
37 #define TLV_TYPE_HWRM_REQUEST 0x1UL
38 #define TLV_TYPE_HWRM_RESPONSE 0x2UL
39 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
40 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
41 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
42 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
43 #define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL
44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
47 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL
48 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL
49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
50 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
53 /* tlv (size:64b/8B) */
58 #define TLV_FLAGS_MORE 0x1UL
59 #define TLV_FLAGS_MORE_LAST 0x0UL
60 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
61 #define TLV_FLAGS_REQUIRED 0x2UL
62 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
63 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
64 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
69 /* input (size:128b/16B) */
78 /* output (size:64b/8B) */
86 /* hwrm_short_input (size:128b/16B) */
87 struct hwrm_short_input {
90 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
91 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
97 /* cmd_nums (size:64b/8B) */
100 #define HWRM_VER_GET 0x0UL
101 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
102 #define HWRM_FUNC_BUF_UNRGTR 0xeUL
103 #define HWRM_FUNC_VF_CFG 0xfUL
104 #define HWRM_RESERVED1 0x10UL
105 #define HWRM_FUNC_RESET 0x11UL
106 #define HWRM_FUNC_GETFID 0x12UL
107 #define HWRM_FUNC_VF_ALLOC 0x13UL
108 #define HWRM_FUNC_VF_FREE 0x14UL
109 #define HWRM_FUNC_QCAPS 0x15UL
110 #define HWRM_FUNC_QCFG 0x16UL
111 #define HWRM_FUNC_CFG 0x17UL
112 #define HWRM_FUNC_QSTATS 0x18UL
113 #define HWRM_FUNC_CLR_STATS 0x19UL
114 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
115 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
116 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
117 #define HWRM_FUNC_DRV_RGTR 0x1dUL
118 #define HWRM_FUNC_DRV_QVER 0x1eUL
119 #define HWRM_FUNC_BUF_RGTR 0x1fUL
120 #define HWRM_PORT_PHY_CFG 0x20UL
121 #define HWRM_PORT_MAC_CFG 0x21UL
122 #define HWRM_PORT_TS_QUERY 0x22UL
123 #define HWRM_PORT_QSTATS 0x23UL
124 #define HWRM_PORT_LPBK_QSTATS 0x24UL
125 #define HWRM_PORT_CLR_STATS 0x25UL
126 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
127 #define HWRM_PORT_PHY_QCFG 0x27UL
128 #define HWRM_PORT_MAC_QCFG 0x28UL
129 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
130 #define HWRM_PORT_PHY_QCAPS 0x2aUL
131 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
132 #define HWRM_PORT_PHY_I2C_READ 0x2cUL
133 #define HWRM_PORT_LED_CFG 0x2dUL
134 #define HWRM_PORT_LED_QCFG 0x2eUL
135 #define HWRM_PORT_LED_QCAPS 0x2fUL
136 #define HWRM_QUEUE_QPORTCFG 0x30UL
137 #define HWRM_QUEUE_QCFG 0x31UL
138 #define HWRM_QUEUE_CFG 0x32UL
139 #define HWRM_FUNC_VLAN_CFG 0x33UL
140 #define HWRM_FUNC_VLAN_QCFG 0x34UL
141 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
142 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
143 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
144 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
145 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
146 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
147 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
148 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
149 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
150 #define HWRM_VNIC_ALLOC 0x40UL
151 #define HWRM_VNIC_FREE 0x41UL
152 #define HWRM_VNIC_CFG 0x42UL
153 #define HWRM_VNIC_QCFG 0x43UL
154 #define HWRM_VNIC_TPA_CFG 0x44UL
155 #define HWRM_VNIC_TPA_QCFG 0x45UL
156 #define HWRM_VNIC_RSS_CFG 0x46UL
157 #define HWRM_VNIC_RSS_QCFG 0x47UL
158 #define HWRM_VNIC_PLCMODES_CFG 0x48UL
159 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
160 #define HWRM_VNIC_QCAPS 0x4aUL
161 #define HWRM_RING_ALLOC 0x50UL
162 #define HWRM_RING_FREE 0x51UL
163 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
164 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
165 #define HWRM_RING_AGGINT_QCAPS 0x54UL
166 #define HWRM_RING_RESET 0x5eUL
167 #define HWRM_RING_GRP_ALLOC 0x60UL
168 #define HWRM_RING_GRP_FREE 0x61UL
169 #define HWRM_RESERVED5 0x64UL
170 #define HWRM_RESERVED6 0x65UL
171 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
172 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
173 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
174 #define HWRM_CFA_L2_FILTER_FREE 0x91UL
175 #define HWRM_CFA_L2_FILTER_CFG 0x92UL
176 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
177 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
178 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
179 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
180 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
181 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
183 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
184 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
185 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
186 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
187 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
188 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
189 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
190 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
191 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL
192 #define HWRM_STAT_CTX_ALLOC 0xb0UL
193 #define HWRM_STAT_CTX_FREE 0xb1UL
194 #define HWRM_STAT_CTX_QUERY 0xb2UL
195 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
196 #define HWRM_PORT_QSTATS_EXT 0xb4UL
197 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
198 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL
199 #define HWRM_FW_RESET 0xc0UL
200 #define HWRM_FW_QSTATUS 0xc1UL
201 #define HWRM_FW_HEALTH_CHECK 0xc2UL
202 #define HWRM_FW_SYNC 0xc3UL
203 #define HWRM_FW_SET_TIME 0xc8UL
204 #define HWRM_FW_GET_TIME 0xc9UL
205 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
206 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
207 #define HWRM_FW_IPC_MAILBOX 0xccUL
208 #define HWRM_EXEC_FWD_RESP 0xd0UL
209 #define HWRM_REJECT_FWD_RESP 0xd1UL
210 #define HWRM_FWD_RESP 0xd2UL
211 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
212 #define HWRM_OEM_CMD 0xd4UL
213 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
214 #define HWRM_WOL_FILTER_ALLOC 0xf0UL
215 #define HWRM_WOL_FILTER_FREE 0xf1UL
216 #define HWRM_WOL_FILTER_QCFG 0xf2UL
217 #define HWRM_WOL_REASON_QCFG 0xf3UL
218 #define HWRM_CFA_METER_QCAPS 0xf4UL
219 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
220 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
221 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
222 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
223 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
224 #define HWRM_CFA_VFR_ALLOC 0xfdUL
225 #define HWRM_CFA_VFR_FREE 0xfeUL
226 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
227 #define HWRM_CFA_VF_PAIR_FREE 0x101UL
228 #define HWRM_CFA_VF_PAIR_INFO 0x102UL
229 #define HWRM_CFA_FLOW_ALLOC 0x103UL
230 #define HWRM_CFA_FLOW_FREE 0x104UL
231 #define HWRM_CFA_FLOW_FLUSH 0x105UL
232 #define HWRM_CFA_FLOW_STATS 0x106UL
233 #define HWRM_CFA_FLOW_INFO 0x107UL
234 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
235 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
236 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
237 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
238 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
239 #define HWRM_CFA_PAIR_ALLOC 0x10dUL
240 #define HWRM_CFA_PAIR_FREE 0x10eUL
241 #define HWRM_CFA_PAIR_INFO 0x10fUL
242 #define HWRM_FW_IPC_MSG 0x110UL
243 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
244 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
245 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
246 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
247 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
248 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
249 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL
250 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
251 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL
252 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
253 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL
254 #define HWRM_CFA_COUNTER_CFG 0x11cUL
255 #define HWRM_CFA_COUNTER_QCFG 0x11dUL
256 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL
257 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
258 #define HWRM_CFA_EEM_QCAPS 0x120UL
259 #define HWRM_CFA_EEM_CFG 0x121UL
260 #define HWRM_CFA_EEM_QCFG 0x122UL
261 #define HWRM_CFA_EEM_OP 0x123UL
262 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
263 #define HWRM_ENGINE_CKV_HELLO 0x12dUL
264 #define HWRM_ENGINE_CKV_STATUS 0x12eUL
265 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
266 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
267 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
268 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
269 #define HWRM_ENGINE_CKV_FLUSH 0x133UL
270 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
271 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
272 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
273 #define HWRM_ENGINE_QG_QUERY 0x13dUL
274 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
275 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
276 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
277 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
278 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
279 #define HWRM_ENGINE_QG_METER_BIND 0x143UL
280 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
281 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
282 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
283 #define HWRM_ENGINE_SG_QUERY 0x147UL
284 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
285 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
286 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
287 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
288 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
289 #define HWRM_ENGINE_STATS_CONFIG 0x155UL
290 #define HWRM_ENGINE_STATS_CLEAR 0x156UL
291 #define HWRM_ENGINE_STATS_QUERY 0x157UL
292 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
293 #define HWRM_ENGINE_RQ_FREE 0x15fUL
294 #define HWRM_ENGINE_CQ_ALLOC 0x160UL
295 #define HWRM_ENGINE_CQ_FREE 0x161UL
296 #define HWRM_ENGINE_NQ_ALLOC 0x162UL
297 #define HWRM_ENGINE_NQ_FREE 0x163UL
298 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
299 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
300 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
301 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
302 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
303 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
304 #define HWRM_FUNC_VF_BW_CFG 0x195UL
305 #define HWRM_FUNC_VF_BW_QCFG 0x196UL
306 #define HWRM_SELFTEST_QLIST 0x200UL
307 #define HWRM_SELFTEST_EXEC 0x201UL
308 #define HWRM_SELFTEST_IRQ 0x202UL
309 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
310 #define HWRM_PCIE_QSTATS 0x204UL
311 #define HWRM_DBG_READ_DIRECT 0xff10UL
312 #define HWRM_DBG_READ_INDIRECT 0xff11UL
313 #define HWRM_DBG_WRITE_DIRECT 0xff12UL
314 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
315 #define HWRM_DBG_DUMP 0xff14UL
316 #define HWRM_DBG_ERASE_NVM 0xff15UL
317 #define HWRM_DBG_CFG 0xff16UL
318 #define HWRM_DBG_COREDUMP_LIST 0xff17UL
319 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
320 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
321 #define HWRM_DBG_FW_CLI 0xff1aUL
322 #define HWRM_DBG_I2C_CMD 0xff1bUL
323 #define HWRM_DBG_RING_INFO_GET 0xff1cUL
324 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
325 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
326 #define HWRM_NVM_FLUSH 0xfff0UL
327 #define HWRM_NVM_GET_VARIABLE 0xfff1UL
328 #define HWRM_NVM_SET_VARIABLE 0xfff2UL
329 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
330 #define HWRM_NVM_MODIFY 0xfff4UL
331 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
332 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
333 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
334 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
335 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
336 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
337 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
338 #define HWRM_NVM_RAW_DUMP 0xfffcUL
339 #define HWRM_NVM_READ 0xfffdUL
340 #define HWRM_NVM_WRITE 0xfffeUL
341 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
342 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
346 /* ret_codes (size:64b/8B) */
349 #define HWRM_ERR_CODE_SUCCESS 0x0UL
350 #define HWRM_ERR_CODE_FAIL 0x1UL
351 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
352 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
353 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
354 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
355 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
356 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
357 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
358 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
359 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
360 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
361 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
362 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
363 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
364 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
365 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
369 /* hwrm_err_output (size:128b/16B) */
370 struct hwrm_err_output {
380 #define HWRM_NA_SIGNATURE ((__le32)(-1))
381 #define HWRM_MAX_REQ_LEN 128
382 #define HWRM_MAX_RESP_LEN 280
383 #define HW_HASH_INDEX_SIZE 0x80
384 #define HW_HASH_KEY_SIZE 40
385 #define HWRM_RESP_VALID_KEY 1
386 #define HWRM_VERSION_MAJOR 1
387 #define HWRM_VERSION_MINOR 10
388 #define HWRM_VERSION_UPDATE 0
389 #define HWRM_VERSION_RSVD 33
390 #define HWRM_VERSION_STR "1.10.0.33"
392 /* hwrm_ver_get_input (size:192b/24B) */
393 struct hwrm_ver_get_input {
405 /* hwrm_ver_get_output (size:1408b/176B) */
406 struct hwrm_ver_get_output {
414 u8 hwrm_intf_rsvd_8b;
423 u8 netctrl_fw_maj_8b;
424 u8 netctrl_fw_min_8b;
425 u8 netctrl_fw_bld_8b;
426 u8 netctrl_fw_rsvd_8b;
428 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
429 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
430 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
431 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
432 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
433 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
434 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
435 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
436 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
437 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
438 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
439 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
440 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
445 char hwrm_fw_name[16];
446 char mgmt_fw_name[16];
447 char netctrl_fw_name[16];
449 char roce_fw_name[16];
454 u8 chip_platform_type;
455 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
456 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
457 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
458 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
459 __le16 max_req_win_len;
461 __le16 def_req_timeout;
463 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
464 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
467 __le16 hwrm_intf_major;
468 __le16 hwrm_intf_minor;
469 __le16 hwrm_intf_build;
470 __le16 hwrm_intf_patch;
471 __le16 hwrm_fw_major;
472 __le16 hwrm_fw_minor;
473 __le16 hwrm_fw_build;
474 __le16 hwrm_fw_patch;
475 __le16 mgmt_fw_major;
476 __le16 mgmt_fw_minor;
477 __le16 mgmt_fw_build;
478 __le16 mgmt_fw_patch;
479 __le16 netctrl_fw_major;
480 __le16 netctrl_fw_minor;
481 __le16 netctrl_fw_build;
482 __le16 netctrl_fw_patch;
483 __le16 roce_fw_major;
484 __le16 roce_fw_minor;
485 __le16 roce_fw_build;
486 __le16 roce_fw_patch;
487 __le16 max_ext_req_len;
492 /* eject_cmpl (size:128b/16B) */
495 #define EJECT_CMPL_TYPE_MASK 0x3fUL
496 #define EJECT_CMPL_TYPE_SFT 0
497 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
498 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
499 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
500 #define EJECT_CMPL_FLAGS_SFT 6
501 #define EJECT_CMPL_FLAGS_ERROR 0x40UL
505 #define EJECT_CMPL_V 0x1UL
506 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
507 #define EJECT_CMPL_ERRORS_SFT 1
508 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
509 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
510 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
511 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
512 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
513 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
514 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
519 /* hwrm_cmpl (size:128b/16B) */
522 #define CMPL_TYPE_MASK 0x3fUL
523 #define CMPL_TYPE_SFT 0
524 #define CMPL_TYPE_HWRM_DONE 0x20UL
525 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
533 /* hwrm_fwd_req_cmpl (size:128b/16B) */
534 struct hwrm_fwd_req_cmpl {
536 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
537 #define FWD_REQ_CMPL_TYPE_SFT 0
538 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
539 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
540 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
541 #define FWD_REQ_CMPL_REQ_LEN_SFT 6
544 __le32 req_buf_addr_v[2];
545 #define FWD_REQ_CMPL_V 0x1UL
546 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
547 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
550 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
551 struct hwrm_fwd_resp_cmpl {
553 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
554 #define FWD_RESP_CMPL_TYPE_SFT 0
555 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
556 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
560 __le32 resp_buf_addr_v[2];
561 #define FWD_RESP_CMPL_V 0x1UL
562 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
563 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
566 /* hwrm_async_event_cmpl (size:128b/16B) */
567 struct hwrm_async_event_cmpl {
569 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
570 #define ASYNC_EVENT_CMPL_TYPE_SFT 0
571 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
572 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
574 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
575 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
576 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
577 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
578 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
579 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
580 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
581 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
582 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
583 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
584 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
585 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
586 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
587 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
588 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
589 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
590 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
591 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
592 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
593 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
594 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
595 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
596 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
597 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
598 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
599 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
600 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
603 #define ASYNC_EVENT_CMPL_V 0x1UL
604 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
605 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
611 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
612 struct hwrm_async_event_cmpl_link_status_change {
614 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
615 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
616 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
617 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
619 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
620 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
623 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
624 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
625 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
629 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
630 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
631 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
632 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
633 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
634 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
635 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
636 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
637 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
638 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
641 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
642 struct hwrm_async_event_cmpl_port_conn_not_allowed {
644 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
645 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
646 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
647 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
649 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
650 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
653 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
654 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
655 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
659 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
660 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
661 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
662 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
663 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
664 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
665 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
666 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
667 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
670 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
671 struct hwrm_async_event_cmpl_link_speed_cfg_change {
673 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
674 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
675 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
676 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
678 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
679 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
682 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
683 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
684 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
688 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
689 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
690 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
691 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
694 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
695 struct hwrm_async_event_cmpl_reset_notify {
697 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
698 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
699 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
700 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
702 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
703 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
706 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
707 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
708 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
712 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
713 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
714 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
715 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
716 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
717 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
718 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
719 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
720 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
721 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
722 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
723 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
724 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
727 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
728 struct hwrm_async_event_cmpl_vf_cfg_change {
730 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
731 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
732 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
733 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
735 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
736 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
739 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
740 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
741 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
745 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
746 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
747 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
748 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
749 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
752 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
753 struct hwrm_async_event_cmpl_hw_flow_aged {
755 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
756 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
757 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
758 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
760 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
761 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
764 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
765 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
766 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
770 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
771 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
772 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
773 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
774 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
775 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
778 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
779 struct hwrm_async_event_cmpl_eem_cache_flush_req {
781 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
782 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
783 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
784 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
786 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
787 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
790 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
791 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
792 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
798 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
799 struct hwrm_async_event_cmpl_eem_cache_flush_done {
801 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
802 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
803 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
804 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
806 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
807 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
810 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
811 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
812 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
816 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
817 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
820 /* hwrm_func_reset_input (size:192b/24B) */
821 struct hwrm_func_reset_input {
828 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
831 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
832 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
833 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
834 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
835 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
839 /* hwrm_func_reset_output (size:128b/16B) */
840 struct hwrm_func_reset_output {
849 /* hwrm_func_getfid_input (size:192b/24B) */
850 struct hwrm_func_getfid_input {
857 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
862 /* hwrm_func_getfid_output (size:128b/16B) */
863 struct hwrm_func_getfid_output {
873 /* hwrm_func_vf_alloc_input (size:192b/24B) */
874 struct hwrm_func_vf_alloc_input {
881 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
886 /* hwrm_func_vf_alloc_output (size:128b/16B) */
887 struct hwrm_func_vf_alloc_output {
897 /* hwrm_func_vf_free_input (size:192b/24B) */
898 struct hwrm_func_vf_free_input {
905 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
910 /* hwrm_func_vf_free_output (size:128b/16B) */
911 struct hwrm_func_vf_free_output {
920 /* hwrm_func_vf_cfg_input (size:448b/56B) */
921 struct hwrm_func_vf_cfg_input {
928 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
929 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
930 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
931 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
932 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
933 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
934 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
935 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
936 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
937 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
938 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
939 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
942 __le16 async_event_cr;
945 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
946 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
947 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
948 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
949 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
950 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
951 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
952 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
953 __le16 num_rsscos_ctxs;
954 __le16 num_cmpl_rings;
959 __le16 num_stat_ctxs;
960 __le16 num_hw_ring_grps;
964 /* hwrm_func_vf_cfg_output (size:128b/16B) */
965 struct hwrm_func_vf_cfg_output {
974 /* hwrm_func_qcaps_input (size:192b/24B) */
975 struct hwrm_func_qcaps_input {
985 /* hwrm_func_qcaps_output (size:640b/80B) */
986 struct hwrm_func_qcaps_output {
994 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
995 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
996 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
997 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
998 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
999 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1000 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1001 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1002 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1003 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1004 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1005 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1006 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1007 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1008 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1009 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1010 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1011 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1012 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1013 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1014 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1015 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1016 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1018 __le16 max_rsscos_ctx;
1019 __le16 max_cmpl_rings;
1020 __le16 max_tx_rings;
1021 __le16 max_rx_rings;
1026 __le16 max_stat_ctx;
1027 __le32 max_encap_records;
1028 __le32 max_decap_records;
1029 __le32 max_tx_em_flows;
1030 __le32 max_tx_wm_flows;
1031 __le32 max_rx_em_flows;
1032 __le32 max_rx_wm_flows;
1033 __le32 max_mcast_filters;
1035 __le32 max_hw_ring_grps;
1036 __le16 max_sp_tx_rings;
1041 /* hwrm_func_qcfg_input (size:192b/24B) */
1042 struct hwrm_func_qcfg_input {
1052 /* hwrm_func_qcfg_output (size:704b/88B) */
1053 struct hwrm_func_qcfg_output {
1062 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1063 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1064 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1065 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1066 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1067 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1068 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1069 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
1072 __le16 alloc_rsscos_ctx;
1073 __le16 alloc_cmpl_rings;
1074 __le16 alloc_tx_rings;
1075 __le16 alloc_rx_rings;
1076 __le16 alloc_l2_ctx;
1081 u8 port_partition_type;
1082 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
1083 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
1084 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1085 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1086 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1087 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1088 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1090 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1091 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1092 __le16 dflt_vnic_id;
1093 __le16 max_mtu_configured;
1095 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1096 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
1097 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
1098 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
1099 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
1100 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1101 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1102 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
1103 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1104 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1105 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1106 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1107 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1108 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1109 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1111 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1112 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
1113 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
1114 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
1115 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
1116 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1117 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1118 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
1119 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1120 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1121 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1122 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1123 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1124 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1125 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1127 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1128 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
1129 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
1130 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
1132 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1133 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
1134 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1135 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1136 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1137 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1138 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
1139 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1140 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1141 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1142 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1143 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
1144 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
1146 __le32 alloc_mcast_filters;
1147 __le32 alloc_hw_ring_grps;
1148 __le16 alloc_sp_tx_rings;
1149 __le16 alloc_stat_ctx;
1151 __le16 registered_vfs;
1154 __le32 reset_addr_poll;
1159 /* hwrm_func_cfg_input (size:704b/88B) */
1160 struct hwrm_func_cfg_input {
1169 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1170 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1171 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1172 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1173 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1174 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1175 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1176 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1177 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1178 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1179 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1180 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1181 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1182 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1183 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1184 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1185 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1186 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1188 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1189 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1190 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1191 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1192 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1193 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1194 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1195 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1196 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1197 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1198 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1199 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1200 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1201 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1202 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1203 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1204 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1205 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1206 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1207 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1208 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1209 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1210 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1213 __le16 num_rsscos_ctxs;
1214 __le16 num_cmpl_rings;
1215 __le16 num_tx_rings;
1216 __le16 num_rx_rings;
1219 __le16 num_stat_ctxs;
1220 __le16 num_hw_ring_grps;
1221 u8 dflt_mac_addr[6];
1223 __be32 dflt_ip_addr[4];
1225 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1226 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
1227 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
1228 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
1229 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
1230 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1231 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1232 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1233 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1234 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1235 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1236 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1237 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1238 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1239 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1241 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1242 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1243 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1244 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1245 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1246 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1247 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1248 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1249 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1250 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1251 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1252 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1253 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1254 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1255 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1256 __le16 async_event_cr;
1257 u8 vlan_antispoof_mode;
1258 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
1259 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
1260 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
1261 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1262 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1263 u8 allowed_vlan_pris;
1265 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1266 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
1267 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1268 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1270 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1271 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
1272 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1273 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1274 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1275 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1276 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
1277 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1278 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1279 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1280 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1281 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1282 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1283 __le16 num_mcast_filters;
1286 /* hwrm_func_cfg_output (size:128b/16B) */
1287 struct hwrm_func_cfg_output {
1296 /* hwrm_func_qstats_input (size:192b/24B) */
1297 struct hwrm_func_qstats_input {
1307 /* hwrm_func_qstats_output (size:1408b/176B) */
1308 struct hwrm_func_qstats_output {
1313 __le64 tx_ucast_pkts;
1314 __le64 tx_mcast_pkts;
1315 __le64 tx_bcast_pkts;
1316 __le64 tx_discard_pkts;
1317 __le64 tx_drop_pkts;
1318 __le64 tx_ucast_bytes;
1319 __le64 tx_mcast_bytes;
1320 __le64 tx_bcast_bytes;
1321 __le64 rx_ucast_pkts;
1322 __le64 rx_mcast_pkts;
1323 __le64 rx_bcast_pkts;
1324 __le64 rx_discard_pkts;
1325 __le64 rx_drop_pkts;
1326 __le64 rx_ucast_bytes;
1327 __le64 rx_mcast_bytes;
1328 __le64 rx_bcast_bytes;
1330 __le64 rx_agg_bytes;
1331 __le64 rx_agg_events;
1332 __le64 rx_agg_aborts;
1337 /* hwrm_func_clr_stats_input (size:192b/24B) */
1338 struct hwrm_func_clr_stats_input {
1348 /* hwrm_func_clr_stats_output (size:128b/16B) */
1349 struct hwrm_func_clr_stats_output {
1358 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
1359 struct hwrm_func_vf_resc_free_input {
1369 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
1370 struct hwrm_func_vf_resc_free_output {
1379 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
1380 struct hwrm_func_drv_rgtr_input {
1387 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1388 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1389 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
1390 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
1391 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
1393 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1394 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1395 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1396 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1397 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1399 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
1400 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
1401 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
1402 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
1403 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
1404 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
1405 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
1406 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
1407 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
1408 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1409 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
1410 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1417 __le32 vf_req_fwd[8];
1418 __le32 async_event_fwd[8];
1425 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
1426 struct hwrm_func_drv_rgtr_output {
1432 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
1437 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1438 struct hwrm_func_drv_unrgtr_input {
1445 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1449 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1450 struct hwrm_func_drv_unrgtr_output {
1459 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1460 struct hwrm_func_buf_rgtr_input {
1467 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1468 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1470 __le16 req_buf_num_pages;
1471 __le16 req_buf_page_size;
1472 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1473 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
1474 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
1475 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1476 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
1477 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
1478 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
1479 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1481 __le16 resp_buf_len;
1483 __le64 req_buf_page_addr0;
1484 __le64 req_buf_page_addr1;
1485 __le64 req_buf_page_addr2;
1486 __le64 req_buf_page_addr3;
1487 __le64 req_buf_page_addr4;
1488 __le64 req_buf_page_addr5;
1489 __le64 req_buf_page_addr6;
1490 __le64 req_buf_page_addr7;
1491 __le64 req_buf_page_addr8;
1492 __le64 req_buf_page_addr9;
1493 __le64 error_buf_addr;
1494 __le64 resp_buf_addr;
1497 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
1498 struct hwrm_func_buf_rgtr_output {
1507 /* hwrm_func_drv_qver_input (size:192b/24B) */
1508 struct hwrm_func_drv_qver_input {
1519 /* hwrm_func_drv_qver_output (size:256b/32B) */
1520 struct hwrm_func_drv_qver_output {
1526 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
1527 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
1528 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
1529 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
1530 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
1531 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
1532 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
1533 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
1534 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
1535 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1536 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
1537 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1550 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
1551 struct hwrm_func_resource_qcaps_input {
1561 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
1562 struct hwrm_func_resource_qcaps_output {
1569 __le16 vf_reservation_strategy;
1570 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
1571 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
1572 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
1573 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
1574 __le16 min_rsscos_ctx;
1575 __le16 max_rsscos_ctx;
1576 __le16 min_cmpl_rings;
1577 __le16 max_cmpl_rings;
1578 __le16 min_tx_rings;
1579 __le16 max_tx_rings;
1580 __le16 min_rx_rings;
1581 __le16 max_rx_rings;
1586 __le16 min_stat_ctx;
1587 __le16 max_stat_ctx;
1588 __le16 min_hw_ring_grps;
1589 __le16 max_hw_ring_grps;
1590 __le16 max_tx_scheduler_inputs;
1592 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
1597 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1598 struct hwrm_func_vf_resource_cfg_input {
1606 __le16 min_rsscos_ctx;
1607 __le16 max_rsscos_ctx;
1608 __le16 min_cmpl_rings;
1609 __le16 max_cmpl_rings;
1610 __le16 min_tx_rings;
1611 __le16 max_tx_rings;
1612 __le16 min_rx_rings;
1613 __le16 max_rx_rings;
1618 __le16 min_stat_ctx;
1619 __le16 max_stat_ctx;
1620 __le16 min_hw_ring_grps;
1621 __le16 max_hw_ring_grps;
1623 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
1627 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
1628 struct hwrm_func_vf_resource_cfg_output {
1633 __le16 reserved_rsscos_ctx;
1634 __le16 reserved_cmpl_rings;
1635 __le16 reserved_tx_rings;
1636 __le16 reserved_rx_rings;
1637 __le16 reserved_l2_ctxs;
1638 __le16 reserved_vnics;
1639 __le16 reserved_stat_ctx;
1640 __le16 reserved_hw_ring_grps;
1645 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
1646 struct hwrm_func_backing_store_qcaps_input {
1654 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
1655 struct hwrm_func_backing_store_qcaps_output {
1660 __le32 qp_max_entries;
1661 __le16 qp_min_qp1_entries;
1662 __le16 qp_max_l2_entries;
1663 __le16 qp_entry_size;
1664 __le16 srq_max_l2_entries;
1665 __le32 srq_max_entries;
1666 __le16 srq_entry_size;
1667 __le16 cq_max_l2_entries;
1668 __le32 cq_max_entries;
1669 __le16 cq_entry_size;
1670 __le16 vnic_max_vnic_entries;
1671 __le16 vnic_max_ring_table_entries;
1672 __le16 vnic_entry_size;
1673 __le32 stat_max_entries;
1674 __le16 stat_entry_size;
1675 __le16 tqm_entry_size;
1676 __le32 tqm_min_entries_per_ring;
1677 __le32 tqm_max_entries_per_ring;
1678 __le32 mrav_max_entries;
1679 __le16 mrav_entry_size;
1680 __le16 tim_entry_size;
1681 __le32 tim_max_entries;
1683 u8 tqm_entries_multiple;
1687 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
1688 struct hwrm_func_backing_store_cfg_input {
1695 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
1697 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
1698 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
1699 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
1700 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
1701 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
1702 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
1703 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
1704 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
1705 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
1706 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
1707 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
1708 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
1709 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
1710 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
1711 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
1712 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
1713 u8 qpc_pg_size_qpc_lvl;
1714 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
1715 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
1716 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
1717 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
1718 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
1719 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
1720 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
1721 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
1722 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
1723 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
1724 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
1725 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
1726 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
1727 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
1728 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
1729 u8 srq_pg_size_srq_lvl;
1730 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
1731 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
1732 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
1733 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
1734 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
1735 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
1736 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
1737 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
1738 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
1739 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
1740 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
1741 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
1742 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
1743 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
1744 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
1745 u8 cq_pg_size_cq_lvl;
1746 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
1747 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
1748 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
1749 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
1750 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
1751 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
1752 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
1753 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
1754 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
1755 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
1756 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
1757 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
1758 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
1759 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
1760 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
1761 u8 vnic_pg_size_vnic_lvl;
1762 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
1763 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
1764 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
1765 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
1766 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
1767 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
1768 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
1769 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
1770 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
1771 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
1772 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
1773 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
1774 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
1775 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
1776 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
1777 u8 stat_pg_size_stat_lvl;
1778 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
1779 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
1780 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
1781 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
1782 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
1783 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
1784 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
1785 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
1786 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
1787 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
1788 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
1789 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
1790 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
1791 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
1792 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
1793 u8 tqm_sp_pg_size_tqm_sp_lvl;
1794 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
1795 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
1796 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
1797 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
1798 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
1799 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
1800 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
1801 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
1802 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
1803 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
1804 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
1805 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
1806 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
1807 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
1808 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
1809 u8 tqm_ring0_pg_size_tqm_ring0_lvl;
1810 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
1811 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
1812 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
1813 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
1814 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
1815 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
1816 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
1817 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
1818 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
1819 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
1820 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
1821 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
1822 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
1823 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
1824 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
1825 u8 tqm_ring1_pg_size_tqm_ring1_lvl;
1826 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
1827 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
1828 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
1829 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
1830 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
1831 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
1832 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
1833 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
1834 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
1835 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
1836 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
1837 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
1838 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
1839 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
1840 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
1841 u8 tqm_ring2_pg_size_tqm_ring2_lvl;
1842 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
1843 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
1844 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
1845 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
1846 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
1847 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
1848 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
1849 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
1850 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
1851 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
1852 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
1853 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
1854 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
1855 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
1856 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
1857 u8 tqm_ring3_pg_size_tqm_ring3_lvl;
1858 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
1859 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
1860 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
1861 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
1862 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
1863 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
1864 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
1865 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
1866 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
1867 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
1868 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
1869 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
1870 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
1871 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
1872 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
1873 u8 tqm_ring4_pg_size_tqm_ring4_lvl;
1874 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
1875 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
1876 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
1877 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
1878 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
1879 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
1880 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
1881 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
1882 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
1883 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
1884 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
1885 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
1886 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
1887 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
1888 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
1889 u8 tqm_ring5_pg_size_tqm_ring5_lvl;
1890 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
1891 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
1892 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
1893 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
1894 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
1895 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
1896 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
1897 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
1898 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
1899 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
1900 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
1901 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
1902 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
1903 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
1904 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
1905 u8 tqm_ring6_pg_size_tqm_ring6_lvl;
1906 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
1907 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
1908 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
1909 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
1910 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
1911 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
1912 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
1913 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
1914 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
1915 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
1916 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
1917 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
1918 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
1919 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
1920 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
1921 u8 tqm_ring7_pg_size_tqm_ring7_lvl;
1922 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
1923 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
1924 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
1925 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
1926 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
1927 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
1928 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
1929 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
1930 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
1931 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
1932 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
1933 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
1934 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
1935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
1936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
1937 u8 mrav_pg_size_mrav_lvl;
1938 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
1939 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
1940 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
1941 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
1942 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
1943 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
1944 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
1945 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
1946 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
1947 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
1948 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
1949 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
1950 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
1951 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
1952 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
1953 u8 tim_pg_size_tim_lvl;
1954 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
1955 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
1956 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
1957 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
1958 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
1959 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
1960 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
1961 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
1962 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
1963 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
1964 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
1965 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
1966 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
1967 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
1968 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
1969 __le64 qpc_page_dir;
1970 __le64 srq_page_dir;
1972 __le64 vnic_page_dir;
1973 __le64 stat_page_dir;
1974 __le64 tqm_sp_page_dir;
1975 __le64 tqm_ring0_page_dir;
1976 __le64 tqm_ring1_page_dir;
1977 __le64 tqm_ring2_page_dir;
1978 __le64 tqm_ring3_page_dir;
1979 __le64 tqm_ring4_page_dir;
1980 __le64 tqm_ring5_page_dir;
1981 __le64 tqm_ring6_page_dir;
1982 __le64 tqm_ring7_page_dir;
1983 __le64 mrav_page_dir;
1984 __le64 tim_page_dir;
1985 __le32 qp_num_entries;
1986 __le32 srq_num_entries;
1987 __le32 cq_num_entries;
1988 __le32 stat_num_entries;
1989 __le32 tqm_sp_num_entries;
1990 __le32 tqm_ring0_num_entries;
1991 __le32 tqm_ring1_num_entries;
1992 __le32 tqm_ring2_num_entries;
1993 __le32 tqm_ring3_num_entries;
1994 __le32 tqm_ring4_num_entries;
1995 __le32 tqm_ring5_num_entries;
1996 __le32 tqm_ring6_num_entries;
1997 __le32 tqm_ring7_num_entries;
1998 __le32 mrav_num_entries;
1999 __le32 tim_num_entries;
2000 __le16 qp_num_qp1_entries;
2001 __le16 qp_num_l2_entries;
2002 __le16 qp_entry_size;
2003 __le16 srq_num_l2_entries;
2004 __le16 srq_entry_size;
2005 __le16 cq_num_l2_entries;
2006 __le16 cq_entry_size;
2007 __le16 vnic_num_vnic_entries;
2008 __le16 vnic_num_ring_table_entries;
2009 __le16 vnic_entry_size;
2010 __le16 stat_entry_size;
2011 __le16 tqm_entry_size;
2012 __le16 mrav_entry_size;
2013 __le16 tim_entry_size;
2016 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
2017 struct hwrm_func_backing_store_cfg_output {
2026 /* hwrm_func_drv_if_change_input (size:192b/24B) */
2027 struct hwrm_func_drv_if_change_input {
2034 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
2038 /* hwrm_func_drv_if_change_output (size:128b/16B) */
2039 struct hwrm_func_drv_if_change_output {
2045 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
2046 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
2051 /* hwrm_port_phy_cfg_input (size:448b/56B) */
2052 struct hwrm_port_phy_cfg_input {
2059 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
2060 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
2061 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
2062 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
2063 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
2064 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
2065 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
2066 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
2067 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
2068 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
2069 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
2070 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
2071 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
2072 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
2073 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
2075 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
2076 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
2077 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
2078 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
2079 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
2080 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
2081 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
2082 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
2083 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
2084 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
2085 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
2087 __le16 force_link_speed;
2088 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
2089 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
2090 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
2091 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
2092 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
2093 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
2094 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
2095 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
2096 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
2097 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
2098 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL
2099 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
2100 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
2102 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
2103 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
2104 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
2105 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
2106 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
2107 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
2109 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
2110 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
2111 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
2112 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
2114 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
2115 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
2116 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
2118 __le16 auto_link_speed;
2119 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
2120 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
2121 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
2122 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
2123 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
2124 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
2125 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
2126 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
2127 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
2128 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
2129 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL
2130 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
2131 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
2132 __le16 auto_link_speed_mask;
2133 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
2134 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
2135 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
2136 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
2137 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
2138 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
2139 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
2140 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
2141 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
2142 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
2143 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
2144 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
2145 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
2146 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
2147 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
2149 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
2150 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
2151 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
2153 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
2154 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
2155 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
2156 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
2157 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
2159 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
2160 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
2163 __le16 eee_link_speed_mask;
2164 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2165 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
2166 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2167 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
2168 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2169 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2170 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
2172 __le32 tx_lpi_timer;
2173 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
2174 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
2178 /* hwrm_port_phy_cfg_output (size:128b/16B) */
2179 struct hwrm_port_phy_cfg_output {
2188 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
2189 struct hwrm_port_phy_cfg_cmd_err {
2191 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
2192 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
2193 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
2194 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
2198 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
2199 struct hwrm_port_phy_qcfg_input {
2209 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
2210 struct hwrm_port_phy_qcfg_output {
2216 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
2217 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
2218 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
2219 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
2222 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
2223 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
2224 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
2225 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
2226 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
2227 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
2228 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
2229 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
2230 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
2231 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
2232 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
2233 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
2234 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
2236 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
2237 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
2238 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
2240 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
2241 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
2242 __le16 support_speeds;
2243 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
2244 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
2245 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
2246 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
2247 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
2248 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
2249 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
2250 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
2251 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
2252 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
2253 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
2254 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
2255 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
2256 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
2257 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL
2258 __le16 force_link_speed;
2259 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
2260 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
2261 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
2262 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
2263 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
2264 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
2265 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
2266 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
2267 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
2268 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
2269 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL
2270 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
2271 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
2273 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
2274 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
2275 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
2276 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
2277 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
2278 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
2280 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
2281 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
2282 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
2283 __le16 auto_link_speed;
2284 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
2285 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
2286 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
2287 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
2288 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
2289 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
2290 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
2291 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
2292 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
2293 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
2294 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL
2295 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
2296 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
2297 __le16 auto_link_speed_mask;
2298 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
2299 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
2300 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
2301 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
2302 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
2303 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
2304 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
2305 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
2306 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
2307 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
2308 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
2309 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
2310 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
2311 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
2312 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
2314 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
2315 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
2316 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
2318 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
2319 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
2320 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
2321 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
2322 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
2324 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
2325 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
2327 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
2328 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
2329 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
2330 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
2331 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
2332 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
2333 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
2339 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
2340 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
2341 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
2342 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
2343 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
2344 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
2345 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
2346 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
2347 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
2348 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
2349 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
2350 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
2351 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
2352 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
2353 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
2354 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
2355 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
2356 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
2357 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
2358 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
2359 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
2360 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
2361 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
2362 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
2363 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
2364 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
2365 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
2366 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
2367 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
2368 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
2369 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
2370 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
2371 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
2373 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
2374 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
2375 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
2376 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
2377 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
2379 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
2380 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
2381 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
2382 u8 eee_config_phy_addr;
2383 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
2384 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
2385 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
2386 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
2387 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
2388 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
2389 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
2391 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
2392 __le16 link_partner_adv_speeds;
2393 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
2394 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
2395 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
2396 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
2397 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
2398 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
2399 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
2400 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
2401 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
2402 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
2403 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
2404 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
2405 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
2406 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
2407 u8 link_partner_adv_auto_mode;
2408 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
2409 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
2410 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
2411 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
2412 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
2413 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
2414 u8 link_partner_adv_pause;
2415 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
2416 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
2417 __le16 adv_eee_link_speed_mask;
2418 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2419 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2420 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2421 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2422 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2423 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2424 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2425 __le16 link_partner_adv_eee_link_speed_mask;
2426 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2427 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2428 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2429 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2430 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2431 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2432 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2433 __le32 xcvr_identifier_type_tx_lpi_timer;
2434 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
2435 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
2436 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
2437 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
2438 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
2439 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
2440 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
2441 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
2442 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
2443 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
2445 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
2446 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
2447 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
2448 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
2449 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
2450 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
2451 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
2453 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
2454 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
2455 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
2457 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
2458 char phy_vendor_name[16];
2459 char phy_vendor_partnumber[16];
2464 /* hwrm_port_mac_cfg_input (size:320b/40B) */
2465 struct hwrm_port_mac_cfg_input {
2472 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
2473 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
2474 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
2475 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
2476 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
2477 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
2478 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
2479 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
2480 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
2481 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
2482 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
2483 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
2484 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
2486 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
2487 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
2488 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
2489 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
2490 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
2491 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
2492 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
2493 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
2497 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
2498 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
2499 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
2500 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
2501 u8 vlan_pri2cos_map_pri;
2503 u8 tunnel_pri2cos_map_pri;
2504 u8 dscp2pri_map_pri;
2505 __le16 rx_ts_capture_ptp_msg_type;
2506 __le16 tx_ts_capture_ptp_msg_type;
2508 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
2509 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
2510 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
2511 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
2512 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
2513 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
2514 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
2515 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
2516 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
2517 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
2518 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
2519 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
2520 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
2521 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
2522 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
2523 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
2524 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
2528 /* hwrm_port_mac_cfg_output (size:128b/16B) */
2529 struct hwrm_port_mac_cfg_output {
2538 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
2539 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
2540 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
2541 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
2546 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
2547 struct hwrm_port_mac_ptp_qcfg_input {
2557 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
2558 struct hwrm_port_mac_ptp_qcfg_output {
2564 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
2565 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL
2567 __le32 rx_ts_reg_off_lower;
2568 __le32 rx_ts_reg_off_upper;
2569 __le32 rx_ts_reg_off_seq_id;
2570 __le32 rx_ts_reg_off_src_id_0;
2571 __le32 rx_ts_reg_off_src_id_1;
2572 __le32 rx_ts_reg_off_src_id_2;
2573 __le32 rx_ts_reg_off_domain_id;
2574 __le32 rx_ts_reg_off_fifo;
2575 __le32 rx_ts_reg_off_fifo_adv;
2576 __le32 rx_ts_reg_off_granularity;
2577 __le32 tx_ts_reg_off_lower;
2578 __le32 tx_ts_reg_off_upper;
2579 __le32 tx_ts_reg_off_seq_id;
2580 __le32 tx_ts_reg_off_fifo;
2581 __le32 tx_ts_reg_off_granularity;
2586 /* tx_port_stats (size:3264b/408B) */
2587 struct tx_port_stats {
2588 __le64 tx_64b_frames;
2589 __le64 tx_65b_127b_frames;
2590 __le64 tx_128b_255b_frames;
2591 __le64 tx_256b_511b_frames;
2592 __le64 tx_512b_1023b_frames;
2593 __le64 tx_1024b_1518b_frames;
2594 __le64 tx_good_vlan_frames;
2595 __le64 tx_1519b_2047b_frames;
2596 __le64 tx_2048b_4095b_frames;
2597 __le64 tx_4096b_9216b_frames;
2598 __le64 tx_9217b_16383b_frames;
2599 __le64 tx_good_frames;
2600 __le64 tx_total_frames;
2601 __le64 tx_ucast_frames;
2602 __le64 tx_mcast_frames;
2603 __le64 tx_bcast_frames;
2604 __le64 tx_pause_frames;
2605 __le64 tx_pfc_frames;
2606 __le64 tx_jabber_frames;
2607 __le64 tx_fcs_err_frames;
2608 __le64 tx_control_frames;
2609 __le64 tx_oversz_frames;
2610 __le64 tx_single_dfrl_frames;
2611 __le64 tx_multi_dfrl_frames;
2612 __le64 tx_single_coll_frames;
2613 __le64 tx_multi_coll_frames;
2614 __le64 tx_late_coll_frames;
2615 __le64 tx_excessive_coll_frames;
2616 __le64 tx_frag_frames;
2618 __le64 tx_tagged_frames;
2619 __le64 tx_dbl_tagged_frames;
2620 __le64 tx_runt_frames;
2621 __le64 tx_fifo_underruns;
2622 __le64 tx_pfc_ena_frames_pri0;
2623 __le64 tx_pfc_ena_frames_pri1;
2624 __le64 tx_pfc_ena_frames_pri2;
2625 __le64 tx_pfc_ena_frames_pri3;
2626 __le64 tx_pfc_ena_frames_pri4;
2627 __le64 tx_pfc_ena_frames_pri5;
2628 __le64 tx_pfc_ena_frames_pri6;
2629 __le64 tx_pfc_ena_frames_pri7;
2630 __le64 tx_eee_lpi_events;
2631 __le64 tx_eee_lpi_duration;
2632 __le64 tx_llfc_logical_msgs;
2633 __le64 tx_hcfc_msgs;
2634 __le64 tx_total_collisions;
2636 __le64 tx_xthol_frames;
2637 __le64 tx_stat_discard;
2638 __le64 tx_stat_error;
2641 /* rx_port_stats (size:4224b/528B) */
2642 struct rx_port_stats {
2643 __le64 rx_64b_frames;
2644 __le64 rx_65b_127b_frames;
2645 __le64 rx_128b_255b_frames;
2646 __le64 rx_256b_511b_frames;
2647 __le64 rx_512b_1023b_frames;
2648 __le64 rx_1024b_1518b_frames;
2649 __le64 rx_good_vlan_frames;
2650 __le64 rx_1519b_2047b_frames;
2651 __le64 rx_2048b_4095b_frames;
2652 __le64 rx_4096b_9216b_frames;
2653 __le64 rx_9217b_16383b_frames;
2654 __le64 rx_total_frames;
2655 __le64 rx_ucast_frames;
2656 __le64 rx_mcast_frames;
2657 __le64 rx_bcast_frames;
2658 __le64 rx_fcs_err_frames;
2659 __le64 rx_ctrl_frames;
2660 __le64 rx_pause_frames;
2661 __le64 rx_pfc_frames;
2662 __le64 rx_unsupported_opcode_frames;
2663 __le64 rx_unsupported_da_pausepfc_frames;
2664 __le64 rx_wrong_sa_frames;
2665 __le64 rx_align_err_frames;
2666 __le64 rx_oor_len_frames;
2667 __le64 rx_code_err_frames;
2668 __le64 rx_false_carrier_frames;
2669 __le64 rx_ovrsz_frames;
2670 __le64 rx_jbr_frames;
2671 __le64 rx_mtu_err_frames;
2672 __le64 rx_match_crc_frames;
2673 __le64 rx_promiscuous_frames;
2674 __le64 rx_tagged_frames;
2675 __le64 rx_double_tagged_frames;
2676 __le64 rx_trunc_frames;
2677 __le64 rx_good_frames;
2678 __le64 rx_pfc_xon2xoff_frames_pri0;
2679 __le64 rx_pfc_xon2xoff_frames_pri1;
2680 __le64 rx_pfc_xon2xoff_frames_pri2;
2681 __le64 rx_pfc_xon2xoff_frames_pri3;
2682 __le64 rx_pfc_xon2xoff_frames_pri4;
2683 __le64 rx_pfc_xon2xoff_frames_pri5;
2684 __le64 rx_pfc_xon2xoff_frames_pri6;
2685 __le64 rx_pfc_xon2xoff_frames_pri7;
2686 __le64 rx_pfc_ena_frames_pri0;
2687 __le64 rx_pfc_ena_frames_pri1;
2688 __le64 rx_pfc_ena_frames_pri2;
2689 __le64 rx_pfc_ena_frames_pri3;
2690 __le64 rx_pfc_ena_frames_pri4;
2691 __le64 rx_pfc_ena_frames_pri5;
2692 __le64 rx_pfc_ena_frames_pri6;
2693 __le64 rx_pfc_ena_frames_pri7;
2694 __le64 rx_sch_crc_err_frames;
2695 __le64 rx_undrsz_frames;
2696 __le64 rx_frag_frames;
2697 __le64 rx_eee_lpi_events;
2698 __le64 rx_eee_lpi_duration;
2699 __le64 rx_llfc_physical_msgs;
2700 __le64 rx_llfc_logical_msgs;
2701 __le64 rx_llfc_msgs_with_crc_err;
2702 __le64 rx_hcfc_msgs;
2703 __le64 rx_hcfc_msgs_with_crc_err;
2705 __le64 rx_runt_bytes;
2706 __le64 rx_runt_frames;
2707 __le64 rx_stat_discard;
2711 /* hwrm_port_qstats_input (size:320b/40B) */
2712 struct hwrm_port_qstats_input {
2720 __le64 tx_stat_host_addr;
2721 __le64 rx_stat_host_addr;
2724 /* hwrm_port_qstats_output (size:128b/16B) */
2725 struct hwrm_port_qstats_output {
2730 __le16 tx_stat_size;
2731 __le16 rx_stat_size;
2736 /* tx_port_stats_ext (size:2048b/256B) */
2737 struct tx_port_stats_ext {
2738 __le64 tx_bytes_cos0;
2739 __le64 tx_bytes_cos1;
2740 __le64 tx_bytes_cos2;
2741 __le64 tx_bytes_cos3;
2742 __le64 tx_bytes_cos4;
2743 __le64 tx_bytes_cos5;
2744 __le64 tx_bytes_cos6;
2745 __le64 tx_bytes_cos7;
2746 __le64 tx_packets_cos0;
2747 __le64 tx_packets_cos1;
2748 __le64 tx_packets_cos2;
2749 __le64 tx_packets_cos3;
2750 __le64 tx_packets_cos4;
2751 __le64 tx_packets_cos5;
2752 __le64 tx_packets_cos6;
2753 __le64 tx_packets_cos7;
2754 __le64 pfc_pri0_tx_duration_us;
2755 __le64 pfc_pri0_tx_transitions;
2756 __le64 pfc_pri1_tx_duration_us;
2757 __le64 pfc_pri1_tx_transitions;
2758 __le64 pfc_pri2_tx_duration_us;
2759 __le64 pfc_pri2_tx_transitions;
2760 __le64 pfc_pri3_tx_duration_us;
2761 __le64 pfc_pri3_tx_transitions;
2762 __le64 pfc_pri4_tx_duration_us;
2763 __le64 pfc_pri4_tx_transitions;
2764 __le64 pfc_pri5_tx_duration_us;
2765 __le64 pfc_pri5_tx_transitions;
2766 __le64 pfc_pri6_tx_duration_us;
2767 __le64 pfc_pri6_tx_transitions;
2768 __le64 pfc_pri7_tx_duration_us;
2769 __le64 pfc_pri7_tx_transitions;
2772 /* rx_port_stats_ext (size:2368b/296B) */
2773 struct rx_port_stats_ext {
2774 __le64 link_down_events;
2775 __le64 continuous_pause_events;
2776 __le64 resume_pause_events;
2777 __le64 continuous_roce_pause_events;
2778 __le64 resume_roce_pause_events;
2779 __le64 rx_bytes_cos0;
2780 __le64 rx_bytes_cos1;
2781 __le64 rx_bytes_cos2;
2782 __le64 rx_bytes_cos3;
2783 __le64 rx_bytes_cos4;
2784 __le64 rx_bytes_cos5;
2785 __le64 rx_bytes_cos6;
2786 __le64 rx_bytes_cos7;
2787 __le64 rx_packets_cos0;
2788 __le64 rx_packets_cos1;
2789 __le64 rx_packets_cos2;
2790 __le64 rx_packets_cos3;
2791 __le64 rx_packets_cos4;
2792 __le64 rx_packets_cos5;
2793 __le64 rx_packets_cos6;
2794 __le64 rx_packets_cos7;
2795 __le64 pfc_pri0_rx_duration_us;
2796 __le64 pfc_pri0_rx_transitions;
2797 __le64 pfc_pri1_rx_duration_us;
2798 __le64 pfc_pri1_rx_transitions;
2799 __le64 pfc_pri2_rx_duration_us;
2800 __le64 pfc_pri2_rx_transitions;
2801 __le64 pfc_pri3_rx_duration_us;
2802 __le64 pfc_pri3_rx_transitions;
2803 __le64 pfc_pri4_rx_duration_us;
2804 __le64 pfc_pri4_rx_transitions;
2805 __le64 pfc_pri5_rx_duration_us;
2806 __le64 pfc_pri5_rx_transitions;
2807 __le64 pfc_pri6_rx_duration_us;
2808 __le64 pfc_pri6_rx_transitions;
2809 __le64 pfc_pri7_rx_duration_us;
2810 __le64 pfc_pri7_rx_transitions;
2813 /* hwrm_port_qstats_ext_input (size:320b/40B) */
2814 struct hwrm_port_qstats_ext_input {
2821 __le16 tx_stat_size;
2822 __le16 rx_stat_size;
2824 __le64 tx_stat_host_addr;
2825 __le64 rx_stat_host_addr;
2828 /* hwrm_port_qstats_ext_output (size:128b/16B) */
2829 struct hwrm_port_qstats_ext_output {
2834 __le16 tx_stat_size;
2835 __le16 rx_stat_size;
2836 __le16 total_active_cos_queues;
2838 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
2842 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
2843 struct hwrm_port_lpbk_qstats_input {
2851 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
2852 struct hwrm_port_lpbk_qstats_output {
2857 __le64 lpbk_ucast_frames;
2858 __le64 lpbk_mcast_frames;
2859 __le64 lpbk_bcast_frames;
2860 __le64 lpbk_ucast_bytes;
2861 __le64 lpbk_mcast_bytes;
2862 __le64 lpbk_bcast_bytes;
2863 __le64 tx_stat_discard;
2864 __le64 tx_stat_error;
2865 __le64 rx_stat_discard;
2866 __le64 rx_stat_error;
2871 /* hwrm_port_clr_stats_input (size:192b/24B) */
2872 struct hwrm_port_clr_stats_input {
2880 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
2884 /* hwrm_port_clr_stats_output (size:128b/16B) */
2885 struct hwrm_port_clr_stats_output {
2894 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
2895 struct hwrm_port_lpbk_clr_stats_input {
2903 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
2904 struct hwrm_port_lpbk_clr_stats_output {
2913 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
2914 struct hwrm_port_phy_qcaps_input {
2924 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
2925 struct hwrm_port_phy_qcaps_output {
2931 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
2932 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
2933 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL
2934 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2
2936 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
2937 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
2938 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
2939 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
2940 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
2941 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4
2942 __le16 supported_speeds_force_mode;
2943 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
2944 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
2945 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
2946 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
2947 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
2948 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
2949 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
2950 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
2951 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
2952 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
2953 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
2954 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
2955 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
2956 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
2957 __le16 supported_speeds_auto_mode;
2958 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
2959 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
2960 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
2961 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
2962 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
2963 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
2964 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
2965 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
2966 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
2967 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
2968 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
2969 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
2970 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
2971 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
2972 __le16 supported_speeds_eee_mode;
2973 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
2974 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
2975 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
2976 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
2977 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
2978 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
2979 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
2980 __le32 tx_lpi_timer_low;
2981 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
2982 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
2983 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
2984 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
2985 __le32 valid_tx_lpi_timer_high;
2986 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
2987 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
2988 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
2989 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
2992 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
2993 struct hwrm_port_phy_i2c_read_input {
3001 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
3011 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
3012 struct hwrm_port_phy_i2c_read_output {
3022 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
3023 struct hwrm_port_phy_mdio_write_input {
3039 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
3040 struct hwrm_port_phy_mdio_write_output {
3049 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
3050 struct hwrm_port_phy_mdio_read_input {
3065 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
3066 struct hwrm_port_phy_mdio_read_output {
3076 /* hwrm_port_led_cfg_input (size:512b/64B) */
3077 struct hwrm_port_led_cfg_input {
3084 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
3085 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
3086 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
3087 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
3088 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
3089 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
3090 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
3091 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
3092 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
3093 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
3094 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
3095 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
3096 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
3097 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
3098 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
3099 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
3100 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
3101 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
3102 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
3103 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
3104 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
3105 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
3106 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
3107 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
3113 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
3114 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
3115 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
3116 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
3117 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
3118 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
3120 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
3121 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
3122 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
3123 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
3124 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
3126 __le16 led0_blink_on;
3127 __le16 led0_blink_off;
3132 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
3133 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
3134 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
3135 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
3136 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
3137 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
3139 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
3140 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
3141 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
3142 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
3143 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
3145 __le16 led1_blink_on;
3146 __le16 led1_blink_off;
3151 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
3152 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
3153 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
3154 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
3155 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
3156 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
3158 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
3159 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
3160 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
3161 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
3162 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
3164 __le16 led2_blink_on;
3165 __le16 led2_blink_off;
3170 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
3171 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
3172 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
3173 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
3174 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
3175 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
3177 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
3178 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
3179 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
3180 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
3181 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
3183 __le16 led3_blink_on;
3184 __le16 led3_blink_off;
3189 /* hwrm_port_led_cfg_output (size:128b/16B) */
3190 struct hwrm_port_led_cfg_output {
3199 /* hwrm_port_led_qcfg_input (size:192b/24B) */
3200 struct hwrm_port_led_qcfg_input {
3210 /* hwrm_port_led_qcfg_output (size:448b/56B) */
3211 struct hwrm_port_led_qcfg_output {
3219 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
3220 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
3221 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
3222 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
3224 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
3225 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
3226 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
3227 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
3228 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
3229 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
3231 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
3232 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
3233 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
3234 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
3235 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
3237 __le16 led0_blink_on;
3238 __le16 led0_blink_off;
3242 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
3243 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
3244 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
3245 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
3247 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
3248 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
3249 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
3250 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
3251 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
3252 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
3254 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
3255 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
3256 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
3257 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
3258 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
3260 __le16 led1_blink_on;
3261 __le16 led1_blink_off;
3265 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
3266 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
3267 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
3268 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
3270 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
3271 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
3272 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
3273 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
3274 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
3275 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
3277 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
3278 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
3279 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
3280 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
3281 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
3283 __le16 led2_blink_on;
3284 __le16 led2_blink_off;
3288 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
3289 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
3290 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
3291 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
3293 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
3294 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
3295 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
3296 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
3297 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
3298 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
3300 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
3301 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
3302 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
3303 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
3304 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
3306 __le16 led3_blink_on;
3307 __le16 led3_blink_off;
3313 /* hwrm_port_led_qcaps_input (size:192b/24B) */
3314 struct hwrm_port_led_qcaps_input {
3324 /* hwrm_port_led_qcaps_output (size:384b/48B) */
3325 struct hwrm_port_led_qcaps_output {
3334 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
3335 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
3336 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
3337 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
3340 __le16 led0_state_caps;
3341 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
3342 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
3343 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
3344 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3345 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3346 __le16 led0_color_caps;
3347 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
3348 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3349 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3352 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
3353 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
3354 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
3355 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
3358 __le16 led1_state_caps;
3359 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
3360 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
3361 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
3362 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3363 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3364 __le16 led1_color_caps;
3365 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
3366 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3367 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3370 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
3371 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
3372 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
3373 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
3376 __le16 led2_state_caps;
3377 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
3378 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
3379 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
3380 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3381 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3382 __le16 led2_color_caps;
3383 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
3384 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3385 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3388 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
3389 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
3390 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
3391 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
3394 __le16 led3_state_caps;
3395 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
3396 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
3397 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
3398 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3399 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3400 __le16 led3_color_caps;
3401 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
3402 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3403 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3408 /* hwrm_queue_qportcfg_input (size:192b/24B) */
3409 struct hwrm_queue_qportcfg_input {
3416 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
3417 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
3418 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
3419 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
3422 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
3423 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
3424 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
3428 /* hwrm_queue_qportcfg_output (size:256b/32B) */
3429 struct hwrm_queue_qportcfg_output {
3434 u8 max_configurable_queues;
3435 u8 max_configurable_lossless_queues;
3436 u8 queue_cfg_allowed;
3438 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
3439 u8 queue_pfcenable_cfg_allowed;
3440 u8 queue_pri2cos_cfg_allowed;
3441 u8 queue_cos2bw_cfg_allowed;
3443 u8 queue_id0_service_profile;
3444 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
3445 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
3446 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3447 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3448 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3449 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
3450 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
3452 u8 queue_id1_service_profile;
3453 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
3454 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
3455 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3456 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3457 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3458 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
3459 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
3461 u8 queue_id2_service_profile;
3462 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
3463 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
3464 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3465 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3466 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3467 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
3468 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
3470 u8 queue_id3_service_profile;
3471 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
3472 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
3473 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3474 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3475 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3476 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
3477 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
3479 u8 queue_id4_service_profile;
3480 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
3481 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
3482 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3483 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3484 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3485 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
3486 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
3488 u8 queue_id5_service_profile;
3489 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
3490 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
3491 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3492 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3493 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3494 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
3495 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
3497 u8 queue_id6_service_profile;
3498 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
3499 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
3500 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3501 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3502 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3503 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
3504 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
3506 u8 queue_id7_service_profile;
3507 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
3508 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
3509 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3510 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3511 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3512 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
3513 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
3517 /* hwrm_queue_cfg_input (size:320b/40B) */
3518 struct hwrm_queue_cfg_input {
3525 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3526 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
3527 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
3528 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
3529 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
3530 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
3532 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
3533 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
3537 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
3538 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
3539 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
3540 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
3544 /* hwrm_queue_cfg_output (size:128b/16B) */
3545 struct hwrm_queue_cfg_output {
3554 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
3555 struct hwrm_queue_pfcenable_qcfg_input {
3565 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
3566 struct hwrm_queue_pfcenable_qcfg_output {
3572 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
3573 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
3574 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
3575 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
3576 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
3577 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
3578 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
3579 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
3584 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
3585 struct hwrm_queue_pfcenable_cfg_input {
3592 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
3593 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
3594 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
3595 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
3596 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
3597 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
3598 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
3599 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
3604 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
3605 struct hwrm_queue_pfcenable_cfg_output {
3614 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
3615 struct hwrm_queue_pri2cos_qcfg_input {
3622 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
3623 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
3624 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
3625 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
3626 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
3631 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
3632 struct hwrm_queue_pri2cos_qcfg_output {
3637 u8 pri0_cos_queue_id;
3638 u8 pri1_cos_queue_id;
3639 u8 pri2_cos_queue_id;
3640 u8 pri3_cos_queue_id;
3641 u8 pri4_cos_queue_id;
3642 u8 pri5_cos_queue_id;
3643 u8 pri6_cos_queue_id;
3644 u8 pri7_cos_queue_id;
3646 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
3651 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
3652 struct hwrm_queue_pri2cos_cfg_input {
3659 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3660 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
3661 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
3662 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
3663 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
3664 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
3665 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
3667 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
3668 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
3669 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
3670 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
3671 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
3672 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
3673 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
3674 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
3676 u8 pri0_cos_queue_id;
3677 u8 pri1_cos_queue_id;
3678 u8 pri2_cos_queue_id;
3679 u8 pri3_cos_queue_id;
3680 u8 pri4_cos_queue_id;
3681 u8 pri5_cos_queue_id;
3682 u8 pri6_cos_queue_id;
3683 u8 pri7_cos_queue_id;
3687 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
3688 struct hwrm_queue_pri2cos_cfg_output {
3697 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
3698 struct hwrm_queue_cos2bw_qcfg_input {
3708 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
3709 struct hwrm_queue_cos2bw_qcfg_output {
3717 __le32 queue_id0_min_bw;
3718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
3720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
3721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
3722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
3723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
3724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
3726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
3733 __le32 queue_id0_max_bw;
3734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
3736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
3737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
3738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
3739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
3740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
3742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
3749 u8 queue_id0_tsa_assign;
3750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
3751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
3752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
3754 u8 queue_id0_pri_lvl;
3755 u8 queue_id0_bw_weight;
3757 __le32 queue_id1_min_bw;
3758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
3760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
3761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
3762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
3763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
3764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
3766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
3773 __le32 queue_id1_max_bw;
3774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
3776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
3777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
3778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
3779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
3780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
3782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
3789 u8 queue_id1_tsa_assign;
3790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
3791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
3792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
3794 u8 queue_id1_pri_lvl;
3795 u8 queue_id1_bw_weight;
3797 __le32 queue_id2_min_bw;
3798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
3800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
3801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
3802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
3803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
3804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
3806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
3813 __le32 queue_id2_max_bw;
3814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
3816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
3817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
3818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
3819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
3820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
3822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
3829 u8 queue_id2_tsa_assign;
3830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
3831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
3832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
3834 u8 queue_id2_pri_lvl;
3835 u8 queue_id2_bw_weight;
3837 __le32 queue_id3_min_bw;
3838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
3840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
3841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
3842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
3843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
3844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
3846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
3853 __le32 queue_id3_max_bw;
3854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
3856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
3857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
3858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
3859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
3860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
3862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
3869 u8 queue_id3_tsa_assign;
3870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
3871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
3872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
3874 u8 queue_id3_pri_lvl;
3875 u8 queue_id3_bw_weight;
3877 __le32 queue_id4_min_bw;
3878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
3880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
3881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
3882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
3883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
3884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
3886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
3893 __le32 queue_id4_max_bw;
3894 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3895 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
3896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
3897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
3898 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
3899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
3900 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3901 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
3902 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3903 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
3909 u8 queue_id4_tsa_assign;
3910 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
3911 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
3912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
3914 u8 queue_id4_pri_lvl;
3915 u8 queue_id4_bw_weight;
3917 __le32 queue_id5_min_bw;
3918 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3919 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
3920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
3921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
3922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
3923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
3924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
3926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
3933 __le32 queue_id5_max_bw;
3934 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3935 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
3936 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
3937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
3938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
3939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
3940 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3941 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
3942 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3943 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
3949 u8 queue_id5_tsa_assign;
3950 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
3951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
3952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
3954 u8 queue_id5_pri_lvl;
3955 u8 queue_id5_bw_weight;
3957 __le32 queue_id6_min_bw;
3958 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3959 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
3960 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
3961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
3962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
3963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
3964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
3966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3971 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
3973 __le32 queue_id6_max_bw;
3974 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3975 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
3976 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
3977 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
3978 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
3979 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
3980 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3981 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
3982 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3983 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
3989 u8 queue_id6_tsa_assign;
3990 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
3991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
3992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
3994 u8 queue_id6_pri_lvl;
3995 u8 queue_id6_bw_weight;
3997 __le32 queue_id7_min_bw;
3998 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3999 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
4000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
4001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
4002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
4003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
4004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
4006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4013 __le32 queue_id7_max_bw;
4014 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4015 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
4016 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
4017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
4018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
4019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
4020 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4021 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
4022 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4023 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4029 u8 queue_id7_tsa_assign;
4030 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
4031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
4032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
4034 u8 queue_id7_pri_lvl;
4035 u8 queue_id7_bw_weight;
4040 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
4041 struct hwrm_queue_cos2bw_cfg_input {
4049 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
4050 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
4051 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
4052 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
4053 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
4054 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
4055 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
4056 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
4060 __le32 queue_id0_min_bw;
4061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
4063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
4064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
4065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
4066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
4067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
4069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
4076 __le32 queue_id0_max_bw;
4077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
4079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
4080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
4081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
4082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
4083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
4085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4092 u8 queue_id0_tsa_assign;
4093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
4094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
4095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
4097 u8 queue_id0_pri_lvl;
4098 u8 queue_id0_bw_weight;
4100 __le32 queue_id1_min_bw;
4101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
4103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
4104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
4105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
4106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
4107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
4109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4116 __le32 queue_id1_max_bw;
4117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
4119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
4120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
4121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
4122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
4123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
4125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4132 u8 queue_id1_tsa_assign;
4133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
4134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
4135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
4137 u8 queue_id1_pri_lvl;
4138 u8 queue_id1_bw_weight;
4140 __le32 queue_id2_min_bw;
4141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
4143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
4144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
4145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
4146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
4147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
4149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4152 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
4156 __le32 queue_id2_max_bw;
4157 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4158 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
4159 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
4160 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
4161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
4162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
4163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
4165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
4172 u8 queue_id2_tsa_assign;
4173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
4174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
4175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4176 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
4177 u8 queue_id2_pri_lvl;
4178 u8 queue_id2_bw_weight;
4180 __le32 queue_id3_min_bw;
4181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
4183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
4184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
4185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
4186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
4187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
4189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4192 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
4196 __le32 queue_id3_max_bw;
4197 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4198 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
4199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
4200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
4201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
4202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
4203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
4205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
4212 u8 queue_id3_tsa_assign;
4213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
4214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
4215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
4217 u8 queue_id3_pri_lvl;
4218 u8 queue_id3_bw_weight;
4220 __le32 queue_id4_min_bw;
4221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
4223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
4224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
4225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
4226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
4227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
4229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
4236 __le32 queue_id4_max_bw;
4237 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4238 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
4239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
4240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
4241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
4242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
4243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
4245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4246 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4252 u8 queue_id4_tsa_assign;
4253 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
4254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
4255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
4257 u8 queue_id4_pri_lvl;
4258 u8 queue_id4_bw_weight;
4260 __le32 queue_id5_min_bw;
4261 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4262 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
4263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
4264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
4265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
4266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
4267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
4269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4276 __le32 queue_id5_max_bw;
4277 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
4279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
4280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
4281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
4282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
4283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
4285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4292 u8 queue_id5_tsa_assign;
4293 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
4294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
4295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
4297 u8 queue_id5_pri_lvl;
4298 u8 queue_id5_bw_weight;
4300 __le32 queue_id6_min_bw;
4301 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4302 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
4303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
4304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
4305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
4306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
4307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
4309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4314 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4316 __le32 queue_id6_max_bw;
4317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4318 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
4319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
4320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
4321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
4322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
4323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
4325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4332 u8 queue_id6_tsa_assign;
4333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
4334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
4335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
4337 u8 queue_id6_pri_lvl;
4338 u8 queue_id6_bw_weight;
4340 __le32 queue_id7_min_bw;
4341 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4342 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
4343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
4344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
4345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
4346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
4347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
4349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4356 __le32 queue_id7_max_bw;
4357 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
4359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
4360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
4361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
4362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
4363 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
4365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4372 u8 queue_id7_tsa_assign;
4373 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
4374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
4375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
4377 u8 queue_id7_pri_lvl;
4378 u8 queue_id7_bw_weight;
4382 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
4383 struct hwrm_queue_cos2bw_cfg_output {
4392 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
4393 struct hwrm_queue_dscp_qcaps_input {
4403 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
4404 struct hwrm_queue_dscp_qcaps_output {
4416 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
4417 struct hwrm_queue_dscp2pri_qcfg_input {
4423 __le64 dest_data_addr;
4426 __le16 dest_data_buffer_size;
4430 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
4431 struct hwrm_queue_dscp2pri_qcfg_output {
4442 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
4443 struct hwrm_queue_dscp2pri_cfg_input {
4449 __le64 src_data_addr;
4451 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
4453 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
4460 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
4461 struct hwrm_queue_dscp2pri_cfg_output {
4470 /* hwrm_vnic_alloc_input (size:192b/24B) */
4471 struct hwrm_vnic_alloc_input {
4478 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
4482 /* hwrm_vnic_alloc_output (size:128b/16B) */
4483 struct hwrm_vnic_alloc_output {
4493 /* hwrm_vnic_free_input (size:192b/24B) */
4494 struct hwrm_vnic_free_input {
4504 /* hwrm_vnic_free_output (size:128b/16B) */
4505 struct hwrm_vnic_free_output {
4514 /* hwrm_vnic_cfg_input (size:320b/40B) */
4515 struct hwrm_vnic_cfg_input {
4522 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
4523 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
4524 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
4525 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
4526 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
4527 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
4528 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
4530 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
4531 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
4532 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
4533 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
4534 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
4535 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
4536 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
4538 __le16 dflt_ring_grp;
4543 __le16 default_rx_ring_id;
4544 __le16 default_cmpl_ring_id;
4547 /* hwrm_vnic_cfg_output (size:128b/16B) */
4548 struct hwrm_vnic_cfg_output {
4557 /* hwrm_vnic_qcaps_input (size:192b/24B) */
4558 struct hwrm_vnic_qcaps_input {
4568 /* hwrm_vnic_qcaps_output (size:192b/24B) */
4569 struct hwrm_vnic_qcaps_output {
4577 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
4578 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
4579 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
4580 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
4581 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
4582 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
4583 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
4584 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
4589 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
4590 struct hwrm_vnic_tpa_cfg_input {
4597 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
4598 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
4599 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
4600 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
4601 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
4602 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
4603 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
4604 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
4606 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
4607 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
4608 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
4609 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
4611 __le16 max_agg_segs;
4612 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
4613 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
4614 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
4615 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
4616 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
4617 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
4619 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
4620 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
4621 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
4622 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
4623 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
4624 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
4625 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
4627 __le32 max_agg_timer;
4631 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
4632 struct hwrm_vnic_tpa_cfg_output {
4641 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
4642 struct hwrm_vnic_tpa_qcfg_input {
4652 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
4653 struct hwrm_vnic_tpa_qcfg_output {
4659 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
4660 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
4661 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
4662 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
4663 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
4664 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
4665 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
4666 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
4667 __le16 max_agg_segs;
4668 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
4669 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
4670 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
4671 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
4672 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
4673 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
4675 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
4676 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
4677 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
4678 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
4679 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
4680 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
4681 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
4682 __le32 max_agg_timer;
4688 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
4689 struct hwrm_vnic_rss_cfg_input {
4696 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
4697 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
4698 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
4699 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
4700 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
4701 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
4703 u8 ring_table_pair_index;
4705 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
4706 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
4707 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
4708 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
4709 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
4710 __le64 ring_grp_tbl_addr;
4711 __le64 hash_key_tbl_addr;
4716 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
4717 struct hwrm_vnic_rss_cfg_output {
4726 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
4727 struct hwrm_vnic_plcmodes_cfg_input {
4734 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
4735 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
4736 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
4737 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
4738 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
4739 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
4741 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
4742 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
4743 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
4745 __le16 jumbo_thresh;
4747 __le16 hds_threshold;
4751 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
4752 struct hwrm_vnic_plcmodes_cfg_output {
4761 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
4762 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
4770 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
4771 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
4776 __le16 rss_cos_lb_ctx_id;
4781 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
4782 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
4788 __le16 rss_cos_lb_ctx_id;
4792 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
4793 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
4802 /* hwrm_ring_alloc_input (size:704b/88B) */
4803 struct hwrm_ring_alloc_input {
4810 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
4811 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
4812 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
4813 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
4814 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
4815 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
4817 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
4818 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
4819 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
4820 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
4821 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
4822 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
4823 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
4826 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
4827 __le64 page_tbl_addr;
4834 __le16 cmpl_ring_id;
4839 __le16 ring_arb_cfg;
4840 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
4841 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
4842 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
4843 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
4844 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
4845 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
4846 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
4847 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
4848 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
4854 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4855 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
4856 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
4857 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
4858 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
4859 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
4860 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4861 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
4862 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4863 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4864 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4865 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4866 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4867 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4868 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
4870 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
4871 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
4872 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
4873 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
4874 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
4879 /* hwrm_ring_alloc_output (size:128b/16B) */
4880 struct hwrm_ring_alloc_output {
4886 __le16 logical_ring_id;
4891 /* hwrm_ring_free_input (size:192b/24B) */
4892 struct hwrm_ring_free_input {
4899 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
4900 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
4901 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
4902 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
4903 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
4904 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
4905 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
4911 /* hwrm_ring_free_output (size:128b/16B) */
4912 struct hwrm_ring_free_output {
4921 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
4922 struct hwrm_ring_aggint_qcaps_input {
4930 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
4931 struct hwrm_ring_aggint_qcaps_output {
4937 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
4938 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
4939 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
4940 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
4941 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
4942 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
4943 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
4944 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
4945 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
4947 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
4948 __le16 num_cmpl_dma_aggr_min;
4949 __le16 num_cmpl_dma_aggr_max;
4950 __le16 num_cmpl_dma_aggr_during_int_min;
4951 __le16 num_cmpl_dma_aggr_during_int_max;
4952 __le16 cmpl_aggr_dma_tmr_min;
4953 __le16 cmpl_aggr_dma_tmr_max;
4954 __le16 cmpl_aggr_dma_tmr_during_int_min;
4955 __le16 cmpl_aggr_dma_tmr_during_int_max;
4956 __le16 int_lat_tmr_min_min;
4957 __le16 int_lat_tmr_min_max;
4958 __le16 int_lat_tmr_max_min;
4959 __le16 int_lat_tmr_max_max;
4960 __le16 num_cmpl_aggr_int_min;
4961 __le16 num_cmpl_aggr_int_max;
4967 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
4968 struct hwrm_ring_cmpl_ring_qaggint_params_input {
4978 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
4979 struct hwrm_ring_cmpl_ring_qaggint_params_output {
4985 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
4986 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
4987 __le16 num_cmpl_dma_aggr;
4988 __le16 num_cmpl_dma_aggr_during_int;
4989 __le16 cmpl_aggr_dma_tmr;
4990 __le16 cmpl_aggr_dma_tmr_during_int;
4991 __le16 int_lat_tmr_min;
4992 __le16 int_lat_tmr_max;
4993 __le16 num_cmpl_aggr_int;
4998 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
4999 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
5007 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
5008 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
5009 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
5010 __le16 num_cmpl_dma_aggr;
5011 __le16 num_cmpl_dma_aggr_during_int;
5012 __le16 cmpl_aggr_dma_tmr;
5013 __le16 cmpl_aggr_dma_tmr_during_int;
5014 __le16 int_lat_tmr_min;
5015 __le16 int_lat_tmr_max;
5016 __le16 num_cmpl_aggr_int;
5018 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
5019 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
5020 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
5021 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
5022 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
5023 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
5027 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
5028 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
5037 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
5038 struct hwrm_ring_grp_alloc_input {
5050 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
5051 struct hwrm_ring_grp_alloc_output {
5056 __le32 ring_group_id;
5061 /* hwrm_ring_grp_free_input (size:192b/24B) */
5062 struct hwrm_ring_grp_free_input {
5068 __le32 ring_group_id;
5072 /* hwrm_ring_grp_free_output (size:128b/16B) */
5073 struct hwrm_ring_grp_free_output {
5081 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
5082 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
5083 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
5084 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
5086 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
5087 struct hwrm_cfa_l2_filter_alloc_input {
5094 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
5095 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
5096 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
5097 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
5098 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
5099 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
5100 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
5101 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
5102 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
5103 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
5104 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
5105 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
5106 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
5108 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
5109 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
5110 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
5111 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
5112 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
5113 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
5114 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
5115 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
5116 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
5117 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
5118 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
5119 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
5120 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
5121 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
5122 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
5123 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
5124 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
5129 __le16 l2_ovlan_mask;
5131 __le16 l2_ivlan_mask;
5135 u8 t_l2_addr_mask[6];
5137 __le16 t_l2_ovlan_mask;
5139 __le16 t_l2_ivlan_mask;
5141 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
5142 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
5143 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
5144 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
5145 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
5146 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
5147 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
5148 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
5149 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
5153 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5154 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5155 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5156 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5157 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5158 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5159 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5160 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5161 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5162 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5163 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5164 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5165 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5166 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5167 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5170 __le16 mirror_vnic_id;
5172 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5173 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
5174 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
5175 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
5176 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
5177 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
5180 __le64 l2_filter_id_hint;
5183 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
5184 struct hwrm_cfa_l2_filter_alloc_output {
5189 __le64 l2_filter_id;
5195 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
5196 struct hwrm_cfa_l2_filter_free_input {
5202 __le64 l2_filter_id;
5205 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
5206 struct hwrm_cfa_l2_filter_free_output {
5215 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
5216 struct hwrm_cfa_l2_filter_cfg_input {
5223 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
5224 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
5225 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
5226 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
5227 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
5228 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
5229 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
5230 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
5231 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
5232 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
5233 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
5235 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
5236 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
5237 __le64 l2_filter_id;
5239 __le32 new_mirror_vnic_id;
5242 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
5243 struct hwrm_cfa_l2_filter_cfg_output {
5252 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
5253 struct hwrm_cfa_l2_set_rx_mask_input {
5261 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
5262 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
5263 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
5264 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
5265 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
5266 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
5267 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
5268 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
5270 __le32 num_mc_entries;
5272 __le64 vlan_tag_tbl_addr;
5273 __le32 num_vlan_tags;
5277 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
5278 struct hwrm_cfa_l2_set_rx_mask_output {
5287 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
5288 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
5290 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
5291 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
5292 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
5296 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
5297 struct hwrm_cfa_tunnel_filter_alloc_input {
5304 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5306 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
5307 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
5308 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
5309 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
5310 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
5311 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
5312 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
5313 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
5314 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
5315 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
5316 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
5317 __le64 l2_filter_id;
5321 __le32 t_l3_addr[4];
5325 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5326 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5327 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5328 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5329 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5330 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5331 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5332 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5333 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5334 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5335 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5336 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5337 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5338 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5339 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5341 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
5342 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
5343 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
5346 __le32 mirror_vnic_id;
5349 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
5350 struct hwrm_cfa_tunnel_filter_alloc_output {
5355 __le64 tunnel_filter_id;
5361 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
5362 struct hwrm_cfa_tunnel_filter_free_input {
5368 __le64 tunnel_filter_id;
5371 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
5372 struct hwrm_cfa_tunnel_filter_free_output {
5381 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
5382 struct hwrm_vxlan_ipv4_hdr {
5384 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
5385 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
5386 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
5387 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
5390 __be16 flags_frag_offset;
5394 __be32 dest_ip_addr;
5397 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
5398 struct hwrm_vxlan_ipv6_hdr {
5399 __be32 ver_tc_flow_label;
5400 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
5401 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
5402 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
5403 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
5404 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
5405 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
5406 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
5410 __be32 src_ip_addr[4];
5411 __be32 dest_ip_addr[4];
5414 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
5415 struct hwrm_cfa_encap_data_vxlan {
5426 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
5427 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
5428 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
5429 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
5439 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
5440 struct hwrm_cfa_encap_record_alloc_input {
5447 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5449 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
5450 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
5451 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
5452 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
5453 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
5454 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
5455 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
5456 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
5457 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
5458 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
5459 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
5460 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE
5462 __le32 encap_data[20];
5465 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
5466 struct hwrm_cfa_encap_record_alloc_output {
5471 __le32 encap_record_id;
5476 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
5477 struct hwrm_cfa_encap_record_free_input {
5483 __le32 encap_record_id;
5487 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
5488 struct hwrm_cfa_encap_record_free_output {
5497 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
5498 struct hwrm_cfa_ntuple_filter_alloc_input {
5505 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5506 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
5507 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
5509 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
5510 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
5511 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
5512 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
5513 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
5514 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
5515 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
5516 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
5517 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
5518 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
5519 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
5520 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
5521 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
5522 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
5523 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
5524 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
5525 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
5526 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
5527 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
5528 __le64 l2_filter_id;
5532 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
5533 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
5534 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
5535 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
5537 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
5538 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
5539 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
5540 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
5542 __le16 mirror_vnic_id;
5544 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5545 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5546 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5547 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5548 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5549 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5550 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5551 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5552 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5553 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5554 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5555 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5556 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5557 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5558 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5560 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5561 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
5562 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
5563 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
5564 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
5565 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
5566 __be32 src_ipaddr[4];
5567 __be32 src_ipaddr_mask[4];
5568 __be32 dst_ipaddr[4];
5569 __be32 dst_ipaddr_mask[4];
5571 __be16 src_port_mask;
5573 __be16 dst_port_mask;
5574 __le64 ntuple_filter_id_hint;
5577 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
5578 struct hwrm_cfa_ntuple_filter_alloc_output {
5583 __le64 ntuple_filter_id;
5589 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
5590 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
5592 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
5593 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
5594 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
5598 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
5599 struct hwrm_cfa_ntuple_filter_free_input {
5605 __le64 ntuple_filter_id;
5608 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
5609 struct hwrm_cfa_ntuple_filter_free_output {
5618 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
5619 struct hwrm_cfa_ntuple_filter_cfg_input {
5626 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
5627 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
5628 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
5630 __le64 ntuple_filter_id;
5632 __le32 new_mirror_vnic_id;
5633 __le16 new_meter_instance_id;
5634 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
5635 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
5639 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
5640 struct hwrm_cfa_ntuple_filter_cfg_output {
5649 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
5650 struct hwrm_cfa_decap_filter_alloc_input {
5657 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
5659 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
5660 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
5661 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
5662 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
5663 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
5664 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
5665 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
5666 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
5667 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
5668 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
5669 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
5670 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
5671 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
5672 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
5673 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
5674 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
5675 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
5678 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5679 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5680 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5681 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5682 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5683 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5684 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5685 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5686 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5687 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5688 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5689 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5690 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5691 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5692 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5704 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
5705 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
5706 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
5707 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
5709 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
5710 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
5711 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
5712 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
5715 __be32 src_ipaddr[4];
5716 __be32 dst_ipaddr[4];
5720 __le16 l2_ctxt_ref_id;
5723 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
5724 struct hwrm_cfa_decap_filter_alloc_output {
5729 __le32 decap_filter_id;
5734 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
5735 struct hwrm_cfa_decap_filter_free_input {
5741 __le32 decap_filter_id;
5745 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
5746 struct hwrm_cfa_decap_filter_free_output {
5755 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
5756 struct hwrm_cfa_flow_alloc_input {
5763 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
5764 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
5765 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
5766 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
5767 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
5768 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
5769 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
5770 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
5771 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
5772 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
5773 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
5774 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
5775 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
5776 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
5777 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
5778 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
5779 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL
5781 __le32 tunnel_handle;
5782 __le16 action_flags;
5783 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
5784 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
5785 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
5786 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
5787 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
5788 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
5789 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
5790 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
5791 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
5792 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
5793 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
5794 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
5795 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL
5797 __be16 l2_rewrite_vlan_tpid;
5798 __be16 l2_rewrite_vlan_tci;
5799 __le16 act_meter_id;
5800 __le16 ref_flow_handle;
5802 __be16 outer_vlan_tci;
5804 __be16 inner_vlan_tci;
5811 __be16 l4_src_port_mask;
5813 __be16 l4_dst_port_mask;
5814 __be32 nat_ip_address[4];
5815 __be16 l2_rewrite_dmac[3];
5817 __be16 l2_rewrite_smac[3];
5820 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5821 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5822 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5823 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5824 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5825 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5826 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5827 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5828 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5829 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5830 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5831 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5832 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5833 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5834 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5837 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
5838 struct hwrm_cfa_flow_alloc_output {
5846 __le64 ext_flow_handle;
5847 __le32 flow_counter_id;
5852 /* hwrm_cfa_flow_free_input (size:256b/32B) */
5853 struct hwrm_cfa_flow_free_input {
5861 __le64 ext_flow_handle;
5864 /* hwrm_cfa_flow_free_output (size:256b/32B) */
5865 struct hwrm_cfa_flow_free_output {
5876 /* hwrm_cfa_flow_info_input (size:256b/32B) */
5877 struct hwrm_cfa_flow_info_input {
5884 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
5885 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0
5886 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
5887 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
5888 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
5889 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
5891 __le64 ext_flow_handle;
5894 /* hwrm_cfa_flow_info_output (size:448b/56B) */
5895 struct hwrm_cfa_flow_info_output {
5907 __le64 vfp_tcam_info;
5910 __le32 tunnel_handle;
5916 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
5917 struct hwrm_cfa_flow_stats_input {
5924 __le16 flow_handle_0;
5925 __le16 flow_handle_1;
5926 __le16 flow_handle_2;
5927 __le16 flow_handle_3;
5928 __le16 flow_handle_4;
5929 __le16 flow_handle_5;
5930 __le16 flow_handle_6;
5931 __le16 flow_handle_7;
5932 __le16 flow_handle_8;
5933 __le16 flow_handle_9;
5947 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
5948 struct hwrm_cfa_flow_stats_output {
5977 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
5978 struct hwrm_cfa_vfr_alloc_input {
5990 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
5991 struct hwrm_cfa_vfr_alloc_output {
5997 __le16 tx_cfa_action;
6002 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
6003 struct hwrm_cfa_vfr_free_input {
6012 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
6013 struct hwrm_cfa_vfr_free_output {
6022 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
6023 struct hwrm_cfa_eem_qcaps_input {
6030 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL
6031 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL
6032 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6036 /* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
6037 struct hwrm_cfa_eem_qcaps_output {
6043 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL
6044 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL
6047 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL
6048 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL
6049 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL
6050 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL
6051 __le32 max_entries_supported;
6052 __le16 key_entry_size;
6053 __le16 record_entry_size;
6054 __le16 efc_entry_size;
6059 /* hwrm_cfa_eem_cfg_input (size:320b/40B) */
6060 struct hwrm_cfa_eem_cfg_input {
6067 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL
6068 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL
6069 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6075 __le16 record_ctx_id;
6079 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
6080 struct hwrm_cfa_eem_cfg_output {
6089 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
6090 struct hwrm_cfa_eem_qcfg_input {
6097 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL
6098 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL
6102 /* hwrm_cfa_eem_qcfg_output (size:128b/16B) */
6103 struct hwrm_cfa_eem_qcfg_output {
6109 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL
6110 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL
6111 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL
6115 /* hwrm_cfa_eem_op_input (size:192b/24B) */
6116 struct hwrm_cfa_eem_op_input {
6123 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL
6124 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL
6127 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL
6128 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
6129 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL
6130 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
6131 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP
6134 /* hwrm_cfa_eem_op_output (size:128b/16B) */
6135 struct hwrm_cfa_eem_op_output {
6144 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
6145 struct hwrm_tunnel_dst_port_query_input {
6152 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6153 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6154 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6155 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6156 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6157 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6158 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6162 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
6163 struct hwrm_tunnel_dst_port_query_output {
6168 __le16 tunnel_dst_port_id;
6169 __be16 tunnel_dst_port_val;
6174 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
6175 struct hwrm_tunnel_dst_port_alloc_input {
6182 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6183 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6184 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6185 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6186 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6187 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6188 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6190 __be16 tunnel_dst_port_val;
6194 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
6195 struct hwrm_tunnel_dst_port_alloc_output {
6200 __le16 tunnel_dst_port_id;
6205 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
6206 struct hwrm_tunnel_dst_port_free_input {
6213 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6214 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6215 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6216 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6217 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6218 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6219 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6221 __le16 tunnel_dst_port_id;
6225 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
6226 struct hwrm_tunnel_dst_port_free_output {
6235 /* ctx_hw_stats (size:1280b/160B) */
6236 struct ctx_hw_stats {
6237 __le64 rx_ucast_pkts;
6238 __le64 rx_mcast_pkts;
6239 __le64 rx_bcast_pkts;
6240 __le64 rx_discard_pkts;
6241 __le64 rx_drop_pkts;
6242 __le64 rx_ucast_bytes;
6243 __le64 rx_mcast_bytes;
6244 __le64 rx_bcast_bytes;
6245 __le64 tx_ucast_pkts;
6246 __le64 tx_mcast_pkts;
6247 __le64 tx_bcast_pkts;
6248 __le64 tx_discard_pkts;
6249 __le64 tx_drop_pkts;
6250 __le64 tx_ucast_bytes;
6251 __le64 tx_mcast_bytes;
6252 __le64 tx_bcast_bytes;
6259 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
6260 struct hwrm_stat_ctx_alloc_input {
6266 __le64 stats_dma_addr;
6267 __le32 update_period_ms;
6269 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
6273 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
6274 struct hwrm_stat_ctx_alloc_output {
6284 /* hwrm_stat_ctx_free_input (size:192b/24B) */
6285 struct hwrm_stat_ctx_free_input {
6295 /* hwrm_stat_ctx_free_output (size:128b/16B) */
6296 struct hwrm_stat_ctx_free_output {
6306 /* hwrm_stat_ctx_query_input (size:192b/24B) */
6307 struct hwrm_stat_ctx_query_input {
6317 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
6318 struct hwrm_stat_ctx_query_output {
6323 __le64 tx_ucast_pkts;
6324 __le64 tx_mcast_pkts;
6325 __le64 tx_bcast_pkts;
6327 __le64 tx_drop_pkts;
6328 __le64 tx_ucast_bytes;
6329 __le64 tx_mcast_bytes;
6330 __le64 tx_bcast_bytes;
6331 __le64 rx_ucast_pkts;
6332 __le64 rx_mcast_pkts;
6333 __le64 rx_bcast_pkts;
6335 __le64 rx_drop_pkts;
6336 __le64 rx_ucast_bytes;
6337 __le64 rx_mcast_bytes;
6338 __le64 rx_bcast_bytes;
6340 __le64 rx_agg_bytes;
6341 __le64 rx_agg_events;
6342 __le64 rx_agg_aborts;
6347 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
6348 struct hwrm_stat_ctx_clr_stats_input {
6358 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
6359 struct hwrm_stat_ctx_clr_stats_output {
6368 /* hwrm_pcie_qstats_input (size:256b/32B) */
6369 struct hwrm_pcie_qstats_input {
6375 __le16 pcie_stat_size;
6377 __le64 pcie_stat_host_addr;
6380 /* hwrm_pcie_qstats_output (size:128b/16B) */
6381 struct hwrm_pcie_qstats_output {
6386 __le16 pcie_stat_size;
6391 /* pcie_ctx_hw_stats (size:768b/96B) */
6392 struct pcie_ctx_hw_stats {
6393 __le64 pcie_pl_signal_integrity;
6394 __le64 pcie_dl_signal_integrity;
6395 __le64 pcie_tl_signal_integrity;
6396 __le64 pcie_link_integrity;
6397 __le64 pcie_tx_traffic_rate;
6398 __le64 pcie_rx_traffic_rate;
6399 __le64 pcie_tx_dllp_statistics;
6400 __le64 pcie_rx_dllp_statistics;
6401 __le64 pcie_equalization_time;
6402 __le32 pcie_ltssm_histogram[4];
6403 __le64 pcie_recovery_histogram;
6406 /* hwrm_fw_reset_input (size:192b/24B) */
6407 struct hwrm_fw_reset_input {
6413 u8 embedded_proc_type;
6414 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
6415 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
6416 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
6417 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
6418 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
6419 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
6420 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
6421 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
6422 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
6424 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
6425 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
6426 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
6427 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
6428 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
6431 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
6435 /* hwrm_fw_reset_output (size:128b/16B) */
6436 struct hwrm_fw_reset_output {
6442 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
6443 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
6444 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
6445 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
6446 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
6451 /* hwrm_fw_qstatus_input (size:192b/24B) */
6452 struct hwrm_fw_qstatus_input {
6458 u8 embedded_proc_type;
6459 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
6460 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
6461 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
6462 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
6463 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
6464 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
6465 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
6466 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
6470 /* hwrm_fw_qstatus_output (size:128b/16B) */
6471 struct hwrm_fw_qstatus_output {
6477 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
6478 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
6479 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
6480 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST
6485 /* hwrm_fw_set_time_input (size:256b/32B) */
6486 struct hwrm_fw_set_time_input {
6493 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
6494 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
6503 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL
6504 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL
6505 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
6509 /* hwrm_fw_set_time_output (size:128b/16B) */
6510 struct hwrm_fw_set_time_output {
6519 /* hwrm_struct_hdr (size:128b/16B) */
6520 struct hwrm_struct_hdr {
6522 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
6523 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
6524 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
6525 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
6526 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
6527 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
6528 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
6529 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
6530 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
6531 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
6532 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
6533 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2
6539 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
6543 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
6544 struct hwrm_struct_data_dcbx_app {
6546 u8 protocol_selector;
6547 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
6548 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
6549 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
6550 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
6551 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
6557 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
6558 struct hwrm_fw_set_structured_data_input {
6564 __le64 src_data_addr;
6570 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
6571 struct hwrm_fw_set_structured_data_output {
6580 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
6581 struct hwrm_fw_set_structured_data_cmd_err {
6583 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
6584 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
6585 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
6586 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
6587 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
6591 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
6592 struct hwrm_fw_get_structured_data_input {
6598 __le64 dest_data_addr;
6600 __le16 structure_id;
6602 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
6603 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
6604 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
6605 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
6606 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
6607 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
6608 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
6609 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
6610 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
6611 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
6616 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
6617 struct hwrm_fw_get_structured_data_output {
6627 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
6628 struct hwrm_fw_get_structured_data_cmd_err {
6630 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
6631 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
6632 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
6636 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
6637 struct hwrm_exec_fwd_resp_input {
6643 __le32 encap_request[26];
6644 __le16 encap_resp_target_id;
6648 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
6649 struct hwrm_exec_fwd_resp_output {
6658 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
6659 struct hwrm_reject_fwd_resp_input {
6665 __le32 encap_request[26];
6666 __le16 encap_resp_target_id;
6670 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
6671 struct hwrm_reject_fwd_resp_output {
6680 /* hwrm_fwd_resp_input (size:1024b/128B) */
6681 struct hwrm_fwd_resp_input {
6687 __le16 encap_resp_target_id;
6688 __le16 encap_resp_cmpl_ring;
6689 __le16 encap_resp_len;
6692 __le64 encap_resp_addr;
6693 __le32 encap_resp[24];
6696 /* hwrm_fwd_resp_output (size:128b/16B) */
6697 struct hwrm_fwd_resp_output {
6706 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
6707 struct hwrm_fwd_async_event_cmpl_input {
6713 __le16 encap_async_event_target_id;
6715 __le32 encap_async_event_cmpl[4];
6718 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
6719 struct hwrm_fwd_async_event_cmpl_output {
6728 /* hwrm_temp_monitor_query_input (size:128b/16B) */
6729 struct hwrm_temp_monitor_query_input {
6737 /* hwrm_temp_monitor_query_output (size:128b/16B) */
6738 struct hwrm_temp_monitor_query_output {
6748 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
6749 struct hwrm_wol_filter_alloc_input {
6757 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
6758 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
6759 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
6760 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
6761 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
6762 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
6765 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
6766 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
6767 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
6768 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
6771 __le16 pattern_offset;
6772 __le16 pattern_buf_size;
6773 __le16 pattern_mask_size;
6775 __le64 pattern_buf_addr;
6776 __le64 pattern_mask_addr;
6779 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
6780 struct hwrm_wol_filter_alloc_output {
6790 /* hwrm_wol_filter_free_input (size:256b/32B) */
6791 struct hwrm_wol_filter_free_input {
6798 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
6800 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
6806 /* hwrm_wol_filter_free_output (size:128b/16B) */
6807 struct hwrm_wol_filter_free_output {
6816 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
6817 struct hwrm_wol_filter_qcfg_input {
6826 __le64 pattern_buf_addr;
6827 __le16 pattern_buf_size;
6829 __le64 pattern_mask_addr;
6830 __le16 pattern_mask_size;
6834 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
6835 struct hwrm_wol_filter_qcfg_output {
6843 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
6844 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
6845 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
6846 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
6849 __le16 pattern_offset;
6850 __le16 pattern_size;
6851 __le16 pattern_mask_size;
6856 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
6857 struct hwrm_wol_reason_qcfg_input {
6865 __le64 wol_pkt_buf_addr;
6866 __le16 wol_pkt_buf_size;
6870 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
6871 struct hwrm_wol_reason_qcfg_output {
6878 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
6879 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
6880 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
6881 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
6887 /* coredump_segment_record (size:128b/16B) */
6888 struct coredump_segment_record {
6889 __le16 component_id;
6891 __le16 max_instances;
6898 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
6899 struct hwrm_dbg_coredump_list_input {
6905 __le64 host_dest_addr;
6906 __le32 host_buf_len;
6911 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
6912 struct hwrm_dbg_coredump_list_output {
6918 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
6920 __le16 total_segments;
6926 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
6927 struct hwrm_dbg_coredump_initiate_input {
6933 __le16 component_id;
6941 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
6942 struct hwrm_dbg_coredump_initiate_output {
6951 /* coredump_data_hdr (size:128b/16B) */
6952 struct coredump_data_hdr {
6954 __le32 flags_length;
6959 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
6960 struct hwrm_dbg_coredump_retrieve_input {
6966 __le64 host_dest_addr;
6967 __le32 host_buf_len;
6969 __le16 component_id;
6981 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
6982 struct hwrm_dbg_coredump_retrieve_output {
6988 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
6995 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
6996 struct hwrm_dbg_ring_info_get_input {
7003 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
7004 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
7005 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
7006 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX
7011 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
7012 struct hwrm_dbg_ring_info_get_output {
7017 __le32 producer_index;
7018 __le32 consumer_index;
7023 /* hwrm_nvm_read_input (size:320b/40B) */
7024 struct hwrm_nvm_read_input {
7030 __le64 host_dest_addr;
7038 /* hwrm_nvm_read_output (size:128b/16B) */
7039 struct hwrm_nvm_read_output {
7048 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
7049 struct hwrm_nvm_get_dir_entries_input {
7055 __le64 host_dest_addr;
7058 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
7059 struct hwrm_nvm_get_dir_entries_output {
7068 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
7069 struct hwrm_nvm_get_dir_info_input {
7077 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
7078 struct hwrm_nvm_get_dir_info_output {
7084 __le32 entry_length;
7089 /* hwrm_nvm_write_input (size:384b/48B) */
7090 struct hwrm_nvm_write_input {
7096 __le64 host_src_addr;
7101 __le32 dir_data_length;
7104 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
7105 __le32 dir_item_length;
7109 /* hwrm_nvm_write_output (size:128b/16B) */
7110 struct hwrm_nvm_write_output {
7115 __le32 dir_item_length;
7121 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
7122 struct hwrm_nvm_write_cmd_err {
7124 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
7125 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
7126 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
7127 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
7131 /* hwrm_nvm_modify_input (size:320b/40B) */
7132 struct hwrm_nvm_modify_input {
7138 __le64 host_src_addr;
7146 /* hwrm_nvm_modify_output (size:128b/16B) */
7147 struct hwrm_nvm_modify_output {
7156 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
7157 struct hwrm_nvm_find_dir_entry_input {
7164 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
7170 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
7171 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
7172 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
7173 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
7174 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
7175 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
7179 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
7180 struct hwrm_nvm_find_dir_entry_output {
7185 __le32 dir_item_length;
7186 __le32 dir_data_length;
7194 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
7195 struct hwrm_nvm_erase_dir_entry_input {
7205 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
7206 struct hwrm_nvm_erase_dir_entry_output {
7215 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
7216 struct hwrm_nvm_get_dev_info_input {
7224 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
7225 struct hwrm_nvm_get_dev_info_output {
7230 __le16 manufacturer_id;
7234 __le32 reserved_size;
7235 __le32 available_size;
7240 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
7241 struct hwrm_nvm_mod_dir_entry_input {
7248 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
7256 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
7257 struct hwrm_nvm_mod_dir_entry_output {
7266 /* hwrm_nvm_verify_update_input (size:192b/24B) */
7267 struct hwrm_nvm_verify_update_input {
7279 /* hwrm_nvm_verify_update_output (size:128b/16B) */
7280 struct hwrm_nvm_verify_update_output {
7289 /* hwrm_nvm_install_update_input (size:192b/24B) */
7290 struct hwrm_nvm_install_update_input {
7296 __le32 install_type;
7297 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
7298 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
7299 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
7301 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
7302 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
7303 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
7307 /* hwrm_nvm_install_update_output (size:192b/24B) */
7308 struct hwrm_nvm_install_update_output {
7313 __le64 installed_items;
7315 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
7316 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
7318 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
7319 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
7320 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
7322 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
7323 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
7324 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
7325 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
7330 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
7331 struct hwrm_nvm_install_update_cmd_err {
7333 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
7334 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
7335 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
7336 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
7340 /* hwrm_nvm_get_variable_input (size:320b/40B) */
7341 struct hwrm_nvm_get_variable_input {
7347 __le64 dest_data_addr;
7350 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
7351 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
7352 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
7359 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
7363 /* hwrm_nvm_get_variable_output (size:128b/16B) */
7364 struct hwrm_nvm_get_variable_output {
7371 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
7372 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
7373 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
7378 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
7379 struct hwrm_nvm_get_variable_cmd_err {
7381 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
7382 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
7383 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
7384 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
7385 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
7389 /* hwrm_nvm_set_variable_input (size:320b/40B) */
7390 struct hwrm_nvm_set_variable_input {
7396 __le64 src_data_addr;
7399 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
7400 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
7401 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
7408 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
7409 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
7410 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
7411 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
7412 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
7413 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
7414 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
7415 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
7419 /* hwrm_nvm_set_variable_output (size:128b/16B) */
7420 struct hwrm_nvm_set_variable_output {
7429 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
7430 struct hwrm_nvm_set_variable_cmd_err {
7432 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
7433 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
7434 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
7435 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
7439 /* hwrm_selftest_qlist_input (size:128b/16B) */
7440 struct hwrm_selftest_qlist_input {
7448 /* hwrm_selftest_qlist_output (size:2240b/280B) */
7449 struct hwrm_selftest_qlist_output {
7456 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
7457 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
7458 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
7459 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
7460 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
7461 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
7463 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
7464 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
7465 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
7466 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
7467 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
7468 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
7470 __le16 test_timeout;
7472 char test0_name[32];
7473 char test1_name[32];
7474 char test2_name[32];
7475 char test3_name[32];
7476 char test4_name[32];
7477 char test5_name[32];
7478 char test6_name[32];
7479 char test7_name[32];
7484 /* hwrm_selftest_exec_input (size:192b/24B) */
7485 struct hwrm_selftest_exec_input {
7492 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
7493 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
7494 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
7495 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
7496 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
7497 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
7501 /* hwrm_selftest_exec_output (size:128b/16B) */
7502 struct hwrm_selftest_exec_output {
7508 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
7509 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
7510 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
7511 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
7512 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
7513 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
7515 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
7516 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
7517 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
7518 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
7519 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
7520 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
7525 /* hwrm_selftest_irq_input (size:128b/16B) */
7526 struct hwrm_selftest_irq_input {
7534 /* hwrm_selftest_irq_output (size:128b/16B) */
7535 struct hwrm_selftest_irq_output {
7544 #endif /* _BNXT_HSI_H_ */