1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
15 #define DRV_MODULE_VERSION "1.8.0"
21 #include <linux/interrupt.h>
22 #include <net/devlink.h>
23 #include <net/dst_metadata.h>
24 #include <net/switchdev.h>
27 __le32 tx_bd_len_flags_type;
28 #define TX_BD_TYPE (0x3f << 0)
29 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
30 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
31 #define TX_BD_FLAGS_PACKET_END (1 << 6)
32 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
33 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
34 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
35 #define TX_BD_FLAGS_LHINT (3 << 13)
36 #define TX_BD_FLAGS_LHINT_SHIFT 13
37 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
38 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
39 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
40 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
41 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
42 #define TX_BD_LEN (0xffff << 16)
43 #define TX_BD_LEN_SHIFT 16
50 __le32 tx_bd_hsize_lflags;
51 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
52 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
53 #define TX_BD_FLAGS_NO_CRC (1 << 2)
54 #define TX_BD_FLAGS_STAMP (1 << 3)
55 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
56 #define TX_BD_FLAGS_LSO (1 << 5)
57 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
58 #define TX_BD_FLAGS_T_IPID (1 << 7)
59 #define TX_BD_HSIZE (0xff << 16)
60 #define TX_BD_HSIZE_SHIFT 16
63 __le32 tx_bd_cfa_action;
64 #define TX_BD_CFA_ACTION (0xffff << 16)
65 #define TX_BD_CFA_ACTION_SHIFT 16
67 __le32 tx_bd_cfa_meta;
68 #define TX_BD_CFA_META_MASK 0xfffffff
69 #define TX_BD_CFA_META_VID_MASK 0xfff
70 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
71 #define TX_BD_CFA_META_PRI_SHIFT 12
72 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
73 #define TX_BD_CFA_META_TPID_SHIFT 16
74 #define TX_BD_CFA_META_KEY (0xf << 28)
75 #define TX_BD_CFA_META_KEY_SHIFT 28
76 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
80 __le32 rx_bd_len_flags_type;
81 #define RX_BD_TYPE (0x3f << 0)
82 #define RX_BD_TYPE_RX_PACKET_BD 0x4
83 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
84 #define RX_BD_TYPE_RX_AGG_BD 0x6
85 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
86 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
87 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
88 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
89 #define RX_BD_FLAGS_SOP (1 << 6)
90 #define RX_BD_FLAGS_EOP (1 << 7)
91 #define RX_BD_FLAGS_BUFFERS (3 << 8)
92 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
93 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
94 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
95 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
96 #define RX_BD_LEN (0xffff << 16)
97 #define RX_BD_LEN_SHIFT 16
104 __le32 tx_cmp_flags_type;
105 #define CMP_TYPE (0x3f << 0)
106 #define CMP_TYPE_TX_L2_CMP 0
107 #define CMP_TYPE_RX_L2_CMP 17
108 #define CMP_TYPE_RX_AGG_CMP 18
109 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
110 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
111 #define CMP_TYPE_STATUS_CMP 32
112 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
113 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
114 #define CMP_TYPE_ERROR_STATUS 48
115 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
116 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
117 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
118 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
119 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
121 #define TX_CMP_FLAGS_ERROR (1 << 6)
122 #define TX_CMP_FLAGS_PUSH (1 << 7)
125 __le32 tx_cmp_errors_v;
126 #define TX_CMP_V (1 << 0)
127 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
128 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
129 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
130 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
131 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
132 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
133 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
134 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
135 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
137 __le32 tx_cmp_unsed_3;
141 __le32 rx_cmp_len_flags_type;
142 #define RX_CMP_CMP_TYPE (0x3f << 0)
143 #define RX_CMP_FLAGS_ERROR (1 << 6)
144 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
145 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
146 #define RX_CMP_FLAGS_UNUSED (1 << 11)
147 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
148 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
149 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
150 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
151 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
152 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
153 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
154 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
155 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
156 #define RX_CMP_LEN (0xffff << 16)
157 #define RX_CMP_LEN_SHIFT 16
160 __le32 rx_cmp_misc_v1;
161 #define RX_CMP_V1 (1 << 0)
162 #define RX_CMP_AGG_BUFS (0x1f << 1)
163 #define RX_CMP_AGG_BUFS_SHIFT 1
164 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
165 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
166 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
167 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
169 __le32 rx_cmp_rss_hash;
172 #define RX_CMP_HASH_VALID(rxcmp) \
173 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
175 #define RSS_PROFILE_ID_MASK 0x1f
177 #define RX_CMP_HASH_TYPE(rxcmp) \
178 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
179 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
182 __le32 rx_cmp_flags2;
183 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
184 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
185 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
186 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
187 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
188 __le32 rx_cmp_meta_data;
189 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
190 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
191 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
192 __le32 rx_cmp_cfa_code_errors_v2;
193 #define RX_CMP_V (1 << 0)
194 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
195 #define RX_CMPL_ERRORS_SFT 1
196 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
197 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
198 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
199 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
200 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
201 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
202 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
203 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
204 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
205 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
206 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
207 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
208 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
209 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
210 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
211 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
214 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
215 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
216 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
217 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
218 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
219 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
220 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
221 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
225 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
226 #define RX_CMPL_CFA_CODE_SFT 16
228 __le32 rx_cmp_unused3;
231 #define RX_CMP_L2_ERRORS \
232 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
234 #define RX_CMP_L4_CS_BITS \
235 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
237 #define RX_CMP_L4_CS_ERR_BITS \
238 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
240 #define RX_CMP_L4_CS_OK(rxcmp1) \
241 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
242 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
244 #define RX_CMP_ENCAP(rxcmp1) \
245 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
246 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
248 #define RX_CMP_CFA_CODE(rxcmpl1) \
249 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
250 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
253 __le32 rx_agg_cmp_len_flags_type;
254 #define RX_AGG_CMP_TYPE (0x3f << 0)
255 #define RX_AGG_CMP_LEN (0xffff << 16)
256 #define RX_AGG_CMP_LEN_SHIFT 16
257 u32 rx_agg_cmp_opaque;
259 #define RX_AGG_CMP_V (1 << 0)
260 __le32 rx_agg_cmp_unused;
263 struct rx_tpa_start_cmp {
264 __le32 rx_tpa_start_cmp_len_flags_type;
265 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
266 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
267 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
268 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
269 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
270 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
271 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
274 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
275 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
276 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
277 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
278 #define RX_TPA_START_CMP_LEN (0xffff << 16)
279 #define RX_TPA_START_CMP_LEN_SHIFT 16
281 u32 rx_tpa_start_cmp_opaque;
282 __le32 rx_tpa_start_cmp_misc_v1;
283 #define RX_TPA_START_CMP_V1 (0x1 << 0)
284 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
285 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
286 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
287 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
289 __le32 rx_tpa_start_cmp_rss_hash;
292 #define TPA_START_HASH_VALID(rx_tpa_start) \
293 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
294 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
296 #define TPA_START_HASH_TYPE(rx_tpa_start) \
297 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
298 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
299 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
301 #define TPA_START_AGG_ID(rx_tpa_start) \
302 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
303 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
305 struct rx_tpa_start_cmp_ext {
306 __le32 rx_tpa_start_cmp_flags2;
307 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
308 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
309 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
310 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
311 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
313 __le32 rx_tpa_start_cmp_metadata;
314 __le32 rx_tpa_start_cmp_cfa_code_v2;
315 #define RX_TPA_START_CMP_V2 (0x1 << 0)
316 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
317 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
318 __le32 rx_tpa_start_cmp_hdr_info;
321 #define TPA_START_CFA_CODE(rx_tpa_start) \
322 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
323 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
325 struct rx_tpa_end_cmp {
326 __le32 rx_tpa_end_cmp_len_flags_type;
327 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
328 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
329 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
330 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
331 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
332 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
333 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
334 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
335 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
336 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
337 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
338 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
339 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
340 #define RX_TPA_END_CMP_LEN (0xffff << 16)
341 #define RX_TPA_END_CMP_LEN_SHIFT 16
343 u32 rx_tpa_end_cmp_opaque;
344 __le32 rx_tpa_end_cmp_misc_v1;
345 #define RX_TPA_END_CMP_V1 (0x1 << 0)
346 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
347 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
348 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
349 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
350 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
351 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
352 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
353 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
355 __le32 rx_tpa_end_cmp_tsdelta;
356 #define RX_TPA_END_GRO_TS (0x1 << 31)
359 #define TPA_END_AGG_ID(rx_tpa_end) \
360 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
361 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
363 #define TPA_END_TPA_SEGS(rx_tpa_end) \
364 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
365 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
367 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
368 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
369 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
371 #define TPA_END_GRO(rx_tpa_end) \
372 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
373 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
375 #define TPA_END_GRO_TS(rx_tpa_end) \
376 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
377 cpu_to_le32(RX_TPA_END_GRO_TS)))
379 struct rx_tpa_end_cmp_ext {
380 __le32 rx_tpa_end_cmp_dup_acks;
381 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
383 __le32 rx_tpa_end_cmp_seg_len;
384 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
386 __le32 rx_tpa_end_cmp_errors_v2;
387 #define RX_TPA_END_CMP_V2 (0x1 << 0)
388 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
389 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
391 u32 rx_tpa_end_cmp_start_opaque;
394 #define TPA_END_ERRORS(rx_tpa_end_ext) \
395 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
396 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
398 #define DB_IDX_MASK 0xffffff
399 #define DB_IDX_VALID (0x1 << 26)
400 #define DB_IRQ_DIS (0x1 << 27)
401 #define DB_KEY_TX (0x0 << 28)
402 #define DB_KEY_RX (0x1 << 28)
403 #define DB_KEY_CP (0x2 << 28)
404 #define DB_KEY_ST (0x3 << 28)
405 #define DB_KEY_TX_PUSH (0x4 << 28)
406 #define DB_LONG_TX_PUSH (0x2 << 24)
408 #define BNXT_MIN_ROCE_CP_RINGS 2
409 #define BNXT_MIN_ROCE_STAT_CTXS 1
411 #define INVALID_HW_RING_ID ((u16)-1)
413 /* The hardware supports certain page sizes. Use the supported page sizes
414 * to allocate the rings.
416 #if (PAGE_SHIFT < 12)
417 #define BNXT_PAGE_SHIFT 12
418 #elif (PAGE_SHIFT <= 13)
419 #define BNXT_PAGE_SHIFT PAGE_SHIFT
420 #elif (PAGE_SHIFT < 16)
421 #define BNXT_PAGE_SHIFT 13
423 #define BNXT_PAGE_SHIFT 16
426 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
428 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
429 #if (PAGE_SHIFT > 15)
430 #define BNXT_RX_PAGE_SHIFT 15
432 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
435 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
437 #define BNXT_MAX_MTU 9500
438 #define BNXT_MAX_PAGE_MODE_MTU \
439 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
442 #define BNXT_MIN_PKT_SIZE 52
444 #define BNXT_DEFAULT_RX_RING_SIZE 511
445 #define BNXT_DEFAULT_TX_RING_SIZE 511
449 #if (BNXT_PAGE_SHIFT == 16)
450 #define MAX_RX_PAGES 1
451 #define MAX_RX_AGG_PAGES 4
452 #define MAX_TX_PAGES 1
453 #define MAX_CP_PAGES 8
455 #define MAX_RX_PAGES 8
456 #define MAX_RX_AGG_PAGES 32
457 #define MAX_TX_PAGES 8
458 #define MAX_CP_PAGES 64
461 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
462 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
463 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
465 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
466 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
468 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
470 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
471 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
473 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
475 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
476 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
477 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
479 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
480 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
482 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
483 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
485 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
486 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
488 #define TX_CMP_VALID(txcmp, raw_cons) \
489 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
490 !((raw_cons) & bp->cp_bit))
492 #define RX_CMP_VALID(rxcmp1, raw_cons) \
493 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
494 !((raw_cons) & bp->cp_bit))
496 #define RX_AGG_CMP_VALID(agg, raw_cons) \
497 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
498 !((raw_cons) & bp->cp_bit))
500 #define TX_CMP_TYPE(txcmp) \
501 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
503 #define RX_CMP_TYPE(rxcmp) \
504 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
506 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
508 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
510 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
512 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
513 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
514 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
515 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
517 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
518 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
519 #define DFLT_HWRM_CMD_TIMEOUT 500
520 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
521 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
522 #define HWRM_RESP_ERR_CODE_MASK 0xffff
523 #define HWRM_RESP_LEN_OFFSET 4
524 #define HWRM_RESP_LEN_MASK 0xffff0000
525 #define HWRM_RESP_LEN_SFT 16
526 #define HWRM_RESP_VALID_MASK 0xff000000
527 #define HWRM_SEQ_ID_INVALID -1
528 #define BNXT_HWRM_REQ_MAX_SIZE 128
529 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
530 BNXT_HWRM_REQ_MAX_SIZE)
532 #define BNXT_RX_EVENT 1
533 #define BNXT_AGG_EVENT 2
534 #define BNXT_TX_EVENT 4
536 struct bnxt_sw_tx_bd {
538 DEFINE_DMA_UNMAP_ADDR(mapping);
542 unsigned short nr_frags;
547 struct bnxt_sw_rx_bd {
553 struct bnxt_sw_rx_agg_bd {
559 struct bnxt_ring_struct {
566 dma_addr_t pg_tbl_map;
571 u16 fw_ring_id; /* Ring id filled by Chimp FW */
577 __le32 tx_bd_len_flags_type;
579 struct tx_bd_ext txbd2;
582 struct tx_push_buffer {
583 struct tx_push_bd push_bd;
587 struct bnxt_tx_ring_info {
588 struct bnxt_napi *bnapi;
592 void __iomem *tx_doorbell;
594 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
595 struct bnxt_sw_tx_bd *tx_buf_ring;
597 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
599 struct tx_push_buffer *tx_push;
600 dma_addr_t tx_push_mapping;
603 #define BNXT_DEV_STATE_CLOSING 0x1
606 struct bnxt_ring_struct tx_ring_struct;
609 struct bnxt_tpa_info {
614 unsigned short gso_type;
617 enum pkt_hash_types hash_type;
621 #define BNXT_TPA_L4_SIZE(hdr_info) \
622 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
624 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
625 (((hdr_info) >> 18) & 0x1ff)
627 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
628 (((hdr_info) >> 9) & 0x1ff)
630 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
633 u16 cfa_code; /* cfa_code in TPA start compl */
636 struct bnxt_rx_ring_info {
637 struct bnxt_napi *bnapi;
642 void __iomem *rx_doorbell;
643 void __iomem *rx_agg_doorbell;
645 struct bpf_prog *xdp_prog;
647 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
648 struct bnxt_sw_rx_bd *rx_buf_ring;
650 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
651 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
653 unsigned long *rx_agg_bmap;
654 u16 rx_agg_bmap_size;
656 struct page *rx_page;
657 unsigned int rx_page_offset;
659 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
660 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
662 struct bnxt_tpa_info *rx_tpa;
664 struct bnxt_ring_struct rx_ring_struct;
665 struct bnxt_ring_struct rx_agg_ring_struct;
668 struct bnxt_cp_ring_info {
670 void __iomem *cp_doorbell;
672 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
674 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
676 struct ctx_hw_stats *hw_stats;
677 dma_addr_t hw_stats_map;
679 u64 rx_l4_csum_errors;
681 struct bnxt_ring_struct cp_ring_struct;
685 struct napi_struct napi;
689 struct bnxt_cp_ring_info cp_ring;
690 struct bnxt_rx_ring_info *rx_ring;
691 struct bnxt_tx_ring_info *tx_ring;
693 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
696 #define BNXT_NAPI_FLAG_XDP 0x1
702 irq_handler_t handler;
705 char name[IFNAMSIZ + 2];
708 #define HWRM_RING_ALLOC_TX 0x1
709 #define HWRM_RING_ALLOC_RX 0x2
710 #define HWRM_RING_ALLOC_AGG 0x4
711 #define HWRM_RING_ALLOC_CMPL 0x8
713 #define INVALID_STATS_CTX_ID -1
715 struct bnxt_ring_grp_info {
723 struct bnxt_vnic_info {
724 u16 fw_vnic_id; /* returned by Chimp during alloc */
725 #define BNXT_MAX_CTX_PER_VNIC 2
726 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
728 #define BNXT_MAX_UC_ADDRS 4
729 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
730 /* index 0 always dev_addr */
735 dma_addr_t rss_table_dma_addr;
737 dma_addr_t rss_hash_key_dma_addr;
744 dma_addr_t mc_list_mapping;
745 #define BNXT_MAX_MC_ADDRS 16
748 #define BNXT_VNIC_RSS_FLAG 1
749 #define BNXT_VNIC_RFS_FLAG 2
750 #define BNXT_VNIC_MCAST_FLAG 4
751 #define BNXT_VNIC_UCAST_FLAG 8
752 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
755 #if defined(CONFIG_BNXT_SRIOV)
756 struct bnxt_vf_info {
758 u8 mac_addr[ETH_ALEN];
763 u16 max_hw_ring_grps;
770 #define BNXT_VF_QOS 0x1
771 #define BNXT_VF_SPOOFCHK 0x2
772 #define BNXT_VF_LINK_FORCED 0x4
773 #define BNXT_VF_LINK_UP 0x8
774 u32 func_flags; /* func cfg flags */
777 void *hwrm_cmd_req_addr;
778 dma_addr_t hwrm_cmd_req_dma_addr;
782 struct bnxt_pf_info {
783 #define BNXT_FIRST_PF_FID 1
784 #define BNXT_FIRST_VF_FID 128
787 u8 mac_addr[ETH_ALEN];
790 u16 max_tx_rings; /* HW assigned max tx rings for this PF */
791 u16 max_rx_rings; /* HW assigned max rx rings for this PF */
792 u16 max_hw_ring_grps;
800 u32 max_encap_records;
801 u32 max_decap_records;
806 unsigned long *vf_event_bmap;
807 u16 hwrm_cmd_req_pages;
808 void *hwrm_cmd_req_addr[4];
809 dma_addr_t hwrm_cmd_req_dma_addr[4];
810 struct bnxt_vf_info *vf;
813 struct bnxt_ntuple_filter {
814 struct hlist_node hash;
815 u8 dst_mac_addr[ETH_ALEN];
816 u8 src_mac_addr[ETH_ALEN];
817 struct flow_keys fkeys;
824 #define BNXT_FLTR_VALID 0
825 #define BNXT_FLTR_UPDATE 1
828 struct bnxt_link_info {
834 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
835 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
836 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
841 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
842 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
844 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
845 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
846 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
847 PORT_PHY_QCFG_RESP_PAUSE_TX)
849 u8 auto_pause_setting;
850 u8 force_pause_setting;
853 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
854 (mode) <= BNXT_LINK_AUTO_MSK)
855 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
856 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
857 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
858 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
859 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
860 #define PHY_VER_LEN 3
861 u8 phy_ver[PHY_VER_LEN];
863 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
864 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
865 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
866 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
867 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
868 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
869 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
870 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
871 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
872 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
874 u16 auto_link_speeds; /* fw adv setting */
875 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
876 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
877 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
878 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
879 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
880 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
881 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
882 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
883 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
884 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
885 u16 support_auto_speeds;
886 u16 lp_auto_link_speeds;
887 u16 force_link_speed;
891 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
892 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
893 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
895 /* copy of requested setting from ethtool cmd */
897 #define BNXT_AUTONEG_SPEED 1
898 #define BNXT_AUTONEG_FLOW_CTRL 2
902 u16 advertising; /* user adv setting */
903 bool force_link_chng;
905 /* a copy of phy_qcfg output used to report link
908 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
911 #define BNXT_MAX_QUEUE 8
913 struct bnxt_queue_info {
918 #define BNXT_MAX_LED 4
920 struct bnxt_led_info {
925 __le16 led_state_caps;
926 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
927 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
929 __le16 led_color_caps;
932 #define BNXT_MAX_TEST 8
934 struct bnxt_test_info {
937 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
940 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
941 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
942 #define BNXT_CAG_REG_BASE 0x300000
944 struct bnxt_vf_rep_stats {
952 struct net_device *dev;
953 struct metadata_dst *dst;
958 struct bnxt_vf_rep_stats rx_stats;
959 struct bnxt_vf_rep_stats tx_stats;
969 #define CHIP_NUM_57301 0x16c8
970 #define CHIP_NUM_57302 0x16c9
971 #define CHIP_NUM_57304 0x16ca
972 #define CHIP_NUM_58700 0x16cd
973 #define CHIP_NUM_57402 0x16d0
974 #define CHIP_NUM_57404 0x16d1
975 #define CHIP_NUM_57406 0x16d2
976 #define CHIP_NUM_57407 0x16d5
978 #define CHIP_NUM_57311 0x16ce
979 #define CHIP_NUM_57312 0x16cf
980 #define CHIP_NUM_57314 0x16df
981 #define CHIP_NUM_57317 0x16e0
982 #define CHIP_NUM_57412 0x16d6
983 #define CHIP_NUM_57414 0x16d7
984 #define CHIP_NUM_57416 0x16d8
985 #define CHIP_NUM_57417 0x16d9
986 #define CHIP_NUM_57412L 0x16da
987 #define CHIP_NUM_57414L 0x16db
989 #define CHIP_NUM_5745X 0xd730
991 #define BNXT_CHIP_NUM_5730X(chip_num) \
992 ((chip_num) >= CHIP_NUM_57301 && \
993 (chip_num) <= CHIP_NUM_57304)
995 #define BNXT_CHIP_NUM_5740X(chip_num) \
996 (((chip_num) >= CHIP_NUM_57402 && \
997 (chip_num) <= CHIP_NUM_57406) || \
998 (chip_num) == CHIP_NUM_57407)
1000 #define BNXT_CHIP_NUM_5731X(chip_num) \
1001 ((chip_num) == CHIP_NUM_57311 || \
1002 (chip_num) == CHIP_NUM_57312 || \
1003 (chip_num) == CHIP_NUM_57314 || \
1004 (chip_num) == CHIP_NUM_57317)
1006 #define BNXT_CHIP_NUM_5741X(chip_num) \
1007 ((chip_num) >= CHIP_NUM_57412 && \
1008 (chip_num) <= CHIP_NUM_57414L)
1010 #define BNXT_CHIP_NUM_58700(chip_num) \
1011 ((chip_num) == CHIP_NUM_58700)
1013 #define BNXT_CHIP_NUM_5745X(chip_num) \
1014 ((chip_num) == CHIP_NUM_5745X)
1016 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1017 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1019 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1020 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1022 struct net_device *dev;
1023 struct pci_dev *pdev;
1028 #define BNXT_FLAG_DCB_ENABLED 0x1
1029 #define BNXT_FLAG_VF 0x2
1030 #define BNXT_FLAG_LRO 0x4
1032 #define BNXT_FLAG_GRO 0x8
1034 /* Cannot support hardware GRO if CONFIG_INET is not set */
1035 #define BNXT_FLAG_GRO 0x0
1037 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1038 #define BNXT_FLAG_JUMBO 0x10
1039 #define BNXT_FLAG_STRIP_VLAN 0x20
1040 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1042 #define BNXT_FLAG_USING_MSIX 0x40
1043 #define BNXT_FLAG_MSIX_CAP 0x80
1044 #define BNXT_FLAG_RFS 0x100
1045 #define BNXT_FLAG_SHARED_RINGS 0x200
1046 #define BNXT_FLAG_PORT_STATS 0x400
1047 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1048 #define BNXT_FLAG_EEE_CAP 0x1000
1049 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1050 #define BNXT_FLAG_WOL_CAP 0x4000
1051 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1052 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1053 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1054 BNXT_FLAG_ROCEV2_CAP)
1055 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1056 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1057 #define BNXT_FLAG_FW_LLDP_AGENT 0x80000
1058 #define BNXT_FLAG_MULTI_HOST 0x100000
1059 #define BNXT_FLAG_SHORT_CMD 0x200000
1060 #define BNXT_FLAG_DOUBLE_DB 0x400000
1061 #define BNXT_FLAG_FW_DCBX_AGENT 0x800000
1062 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1064 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1066 BNXT_FLAG_STRIP_VLAN)
1068 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1069 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1070 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1071 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1072 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1073 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1074 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1076 /* Chip class phase 4 and later */
1077 #define BNXT_CHIP_P4_PLUS(bp) \
1078 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1079 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1080 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1081 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1083 struct bnxt_en_dev *edev;
1084 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1086 struct bnxt_napi **bnapi;
1088 struct bnxt_rx_ring_info *rx_ring;
1089 struct bnxt_tx_ring_info *tx_ring;
1092 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1095 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1096 struct bnxt_rx_ring_info *,
1097 u16, void *, u8 *, dma_addr_t,
1101 u32 rx_buf_use_size; /* useable size */
1104 enum dma_data_direction rx_dir;
1106 u32 rx_agg_ring_size;
1109 u32 rx_agg_ring_mask;
1111 int rx_agg_nr_pages;
1119 int tx_nr_rings_per_tc;
1120 int tx_nr_rings_xdp;
1121 int tx_reserved_rings;
1135 /* grp_info indexed by completion ring index */
1136 struct bnxt_ring_grp_info *grp_info;
1137 struct bnxt_vnic_info *vnic_info;
1142 u8 max_lltc; /* lossless TCs */
1143 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1145 unsigned int current_interval;
1146 #define BNXT_TIMER_INTERVAL HZ
1148 struct timer_list timer;
1150 unsigned long state;
1151 #define BNXT_STATE_OPEN 0
1152 #define BNXT_STATE_IN_SP_TASK 1
1153 #define BNXT_STATE_READ_STATS 2
1155 struct bnxt_irq *irq_tbl;
1157 u8 mac_addr[ETH_ALEN];
1159 #ifdef CONFIG_BNXT_DCB
1160 struct ieee_pfc *ieee_pfc;
1161 struct ieee_ets *ieee_ets;
1164 #endif /* CONFIG_BNXT_DCB */
1170 u32 hwrm_intr_seq_id;
1171 void *hwrm_short_cmd_req_addr;
1172 dma_addr_t hwrm_short_cmd_req_dma_addr;
1173 void *hwrm_cmd_resp_addr;
1174 dma_addr_t hwrm_cmd_resp_dma_addr;
1175 void *hwrm_dbg_resp_addr;
1176 dma_addr_t hwrm_dbg_resp_dma_addr;
1177 #define HWRM_DBG_REG_BUF_SIZE 128
1179 struct rx_port_stats *hw_rx_port_stats;
1180 struct tx_port_stats *hw_tx_port_stats;
1181 dma_addr_t hw_rx_port_stats_map;
1182 dma_addr_t hw_tx_port_stats_map;
1183 int hw_port_stats_size;
1185 u16 hwrm_max_req_len;
1186 int hwrm_cmd_timeout;
1187 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1188 struct hwrm_ver_get_output ver_resp;
1189 #define FW_VER_STR_LEN 32
1190 #define BC_HWRM_STR_LEN 21
1191 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1192 char fw_ver_str[FW_VER_STR_LEN];
1195 __le16 vxlan_fw_dst_port_id;
1198 __le16 nge_fw_dst_port_id;
1199 u8 port_partition_type;
1203 u16 rx_coal_ticks_irq;
1205 u16 rx_coal_bufs_irq;
1207 u16 tx_coal_ticks_irq;
1209 u16 tx_coal_bufs_irq;
1211 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
1213 u32 stats_coal_ticks;
1214 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1215 #define BNXT_MIN_STATS_COAL_TICKS 250000
1216 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1218 struct work_struct sp_task;
1219 unsigned long sp_event;
1220 #define BNXT_RX_MASK_SP_EVENT 0
1221 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1222 #define BNXT_LINK_CHNG_SP_EVENT 2
1223 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1224 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1225 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1226 #define BNXT_RESET_TASK_SP_EVENT 6
1227 #define BNXT_RST_RING_SP_EVENT 7
1228 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1229 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1230 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1231 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1232 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1233 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1234 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1236 struct bnxt_pf_info pf;
1237 #ifdef CONFIG_BNXT_SRIOV
1239 struct bnxt_vf_info vf;
1240 wait_queue_head_t sriov_cfg_wait;
1242 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1244 /* lock to protect VF-rep creation/cleanup via
1245 * multiple paths such as ->sriov_configure() and
1246 * devlink ->eswitch_mode_set()
1248 struct mutex sriov_lock;
1251 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1252 #define BNXT_NTP_FLTR_HASH_SIZE 512
1253 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1254 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1255 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1257 unsigned long *ntp_fltr_bmap;
1260 struct bnxt_link_info link_info;
1261 struct ethtool_eee eee;
1266 struct bnxt_test_info *test_info;
1272 struct bnxt_led_info leds[BNXT_MAX_LED];
1274 struct bpf_prog *xdp_prog;
1276 /* devlink interface and vf-rep structs */
1278 enum devlink_eswitch_mode eswitch_mode;
1279 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
1280 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
1283 #define BNXT_RX_STATS_OFFSET(counter) \
1284 (offsetof(struct rx_port_stats, counter) / 8)
1286 #define BNXT_TX_STATS_OFFSET(counter) \
1287 ((offsetof(struct tx_port_stats, counter) + \
1288 sizeof(struct rx_port_stats) + 512) / 8)
1290 #define I2C_DEV_ADDR_A0 0xa0
1291 #define I2C_DEV_ADDR_A2 0xa2
1292 #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
1293 #define SFP_EEPROM_SFF_8472_COMP_SIZE 1
1294 #define SFF_MODULE_ID_SFP 0x3
1295 #define SFF_MODULE_ID_QSFP 0xc
1296 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1297 #define SFF_MODULE_ID_QSFP28 0x11
1298 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1300 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1302 /* Tell compiler to fetch tx indices from memory. */
1305 return bp->tx_ring_size -
1306 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1309 /* For TX and RX ring doorbells */
1310 static inline void bnxt_db_write(struct bnxt *bp, void __iomem *db, u32 val)
1313 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1317 extern const u16 bnxt_lhint_arr[];
1319 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1320 u16 prod, gfp_t gfp);
1321 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1322 void bnxt_set_tpa_flags(struct bnxt *bp);
1323 void bnxt_set_ring_params(struct bnxt *);
1324 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1325 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1326 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1327 int hwrm_send_message(struct bnxt *, void *, u32, int);
1328 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1329 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1331 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1332 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1333 int bnxt_hwrm_set_coal(struct bnxt *);
1334 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1335 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max);
1336 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1337 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max);
1338 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max);
1339 void bnxt_tx_disable(struct bnxt *bp);
1340 void bnxt_tx_enable(struct bnxt *bp);
1341 int bnxt_hwrm_set_pause(struct bnxt *);
1342 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1343 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1344 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1345 int bnxt_hwrm_fw_set_time(struct bnxt *);
1346 int bnxt_open_nic(struct bnxt *, bool, bool);
1347 int bnxt_half_open_nic(struct bnxt *bp);
1348 void bnxt_half_close_nic(struct bnxt *bp);
1349 int bnxt_close_nic(struct bnxt *, bool, bool);
1350 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1352 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1353 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1354 void bnxt_restore_pf_fw_resources(struct bnxt *bp);
1355 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr);