1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
54 #include <linux/hwmon.h>
55 #include <linux/hwmon-sysfs.h>
60 #include "bnxt_sriov.h"
61 #include "bnxt_ethtool.h"
66 #include "bnxt_devlink.h"
67 #include "bnxt_debugfs.h"
69 #define BNXT_TX_TIMEOUT (5 * HZ)
71 static const char version[] =
72 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
74 MODULE_LICENSE("GPL");
75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
76 MODULE_VERSION(DRV_MODULE_VERSION);
78 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
79 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
80 #define BNXT_RX_COPY_THRESH 256
82 #define BNXT_TX_PUSH_THRESH 164
124 /* indexed by enum above */
125 static const struct {
128 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
129 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
130 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
131 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
132 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
133 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
134 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
135 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
136 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
137 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
139 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
140 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
141 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
142 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
143 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
144 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
145 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
146 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
147 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
148 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
149 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
150 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
151 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
152 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
153 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
154 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
155 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
156 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
157 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
158 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
159 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
160 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
161 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
162 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
163 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
164 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
167 static const struct pci_device_id bnxt_pci_tbl[] = {
168 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
169 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
170 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
171 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
172 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
173 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
174 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
175 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
176 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
177 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
178 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
179 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
180 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
181 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
182 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
183 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
184 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
185 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
186 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
187 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
188 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
190 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
191 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
192 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
193 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
194 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
195 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
196 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
197 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
198 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
199 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
200 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
201 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
202 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
203 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
204 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
205 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
206 #ifdef CONFIG_BNXT_SRIOV
207 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
208 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
209 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
210 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
211 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
212 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
213 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
214 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
215 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
216 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
221 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
223 static const u16 bnxt_vf_req_snif[] = {
227 HWRM_CFA_L2_FILTER_ALLOC,
230 static const u16 bnxt_async_events_arr[] = {
231 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
232 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
233 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
234 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
235 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
238 static struct workqueue_struct *bnxt_pf_wq;
240 static bool bnxt_vf_pciid(enum board_idx idx)
242 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
243 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
246 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
247 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
248 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
250 #define BNXT_CP_DB_IRQ_DIS(db) \
251 writel(DB_CP_IRQ_DIS_FLAGS, db)
253 #define BNXT_DB_CQ(db, idx) \
254 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
256 #define BNXT_DB_NQ_P5(db, idx) \
257 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
259 #define BNXT_DB_CQ_ARM(db, idx) \
260 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
262 #define BNXT_DB_NQ_ARM_P5(db, idx) \
263 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
265 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
267 if (bp->flags & BNXT_FLAG_CHIP_P5)
268 BNXT_DB_NQ_P5(db, idx);
273 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
275 if (bp->flags & BNXT_FLAG_CHIP_P5)
276 BNXT_DB_NQ_ARM_P5(db, idx);
278 BNXT_DB_CQ_ARM(db, idx);
281 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
283 if (bp->flags & BNXT_FLAG_CHIP_P5)
284 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
290 const u16 bnxt_lhint_arr[] = {
291 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
292 TX_BD_FLAGS_LHINT_512_TO_1023,
293 TX_BD_FLAGS_LHINT_1024_TO_2047,
294 TX_BD_FLAGS_LHINT_1024_TO_2047,
295 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
296 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
297 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
298 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
299 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
300 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
301 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
302 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
303 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
304 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
305 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
306 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
307 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
308 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
309 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
312 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
314 struct metadata_dst *md_dst = skb_metadata_dst(skb);
316 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
319 return md_dst->u.port_info.port_id;
322 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
324 struct bnxt *bp = netdev_priv(dev);
326 struct tx_bd_ext *txbd1;
327 struct netdev_queue *txq;
330 unsigned int length, pad = 0;
331 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
333 struct pci_dev *pdev = bp->pdev;
334 struct bnxt_tx_ring_info *txr;
335 struct bnxt_sw_tx_bd *tx_buf;
337 i = skb_get_queue_mapping(skb);
338 if (unlikely(i >= bp->tx_nr_rings)) {
339 dev_kfree_skb_any(skb);
343 txq = netdev_get_tx_queue(dev, i);
344 txr = &bp->tx_ring[bp->tx_ring_map[i]];
347 free_size = bnxt_tx_avail(bp, txr);
348 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
349 netif_tx_stop_queue(txq);
350 return NETDEV_TX_BUSY;
354 len = skb_headlen(skb);
355 last_frag = skb_shinfo(skb)->nr_frags;
357 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
359 txbd->tx_bd_opaque = prod;
361 tx_buf = &txr->tx_buf_ring[prod];
363 tx_buf->nr_frags = last_frag;
366 cfa_action = bnxt_xmit_get_cfa_action(skb);
367 if (skb_vlan_tag_present(skb)) {
368 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
369 skb_vlan_tag_get(skb);
370 /* Currently supports 8021Q, 8021AD vlan offloads
371 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
373 if (skb->vlan_proto == htons(ETH_P_8021Q))
374 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
377 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
378 struct tx_push_buffer *tx_push_buf = txr->tx_push;
379 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
380 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
381 void __iomem *db = txr->tx_db.doorbell;
382 void *pdata = tx_push_buf->data;
386 /* Set COAL_NOW to be ready quickly for the next push */
387 tx_push->tx_bd_len_flags_type =
388 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
389 TX_BD_TYPE_LONG_TX_BD |
390 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
391 TX_BD_FLAGS_COAL_NOW |
392 TX_BD_FLAGS_PACKET_END |
393 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
395 if (skb->ip_summed == CHECKSUM_PARTIAL)
396 tx_push1->tx_bd_hsize_lflags =
397 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
399 tx_push1->tx_bd_hsize_lflags = 0;
401 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
402 tx_push1->tx_bd_cfa_action =
403 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
405 end = pdata + length;
406 end = PTR_ALIGN(end, 8) - 1;
409 skb_copy_from_linear_data(skb, pdata, len);
411 for (j = 0; j < last_frag; j++) {
412 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
415 fptr = skb_frag_address_safe(frag);
419 memcpy(pdata, fptr, skb_frag_size(frag));
420 pdata += skb_frag_size(frag);
423 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
424 txbd->tx_bd_haddr = txr->data_mapping;
425 prod = NEXT_TX(prod);
426 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
427 memcpy(txbd, tx_push1, sizeof(*txbd));
428 prod = NEXT_TX(prod);
430 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
434 netdev_tx_sent_queue(txq, skb->len);
435 wmb(); /* Sync is_push and byte queue before pushing data */
437 push_len = (length + sizeof(*tx_push) + 7) / 8;
439 __iowrite64_copy(db, tx_push_buf, 16);
440 __iowrite32_copy(db + 4, tx_push_buf + 1,
441 (push_len - 16) << 1);
443 __iowrite64_copy(db, tx_push_buf, push_len);
450 if (length < BNXT_MIN_PKT_SIZE) {
451 pad = BNXT_MIN_PKT_SIZE - length;
452 if (skb_pad(skb, pad)) {
453 /* SKB already freed. */
457 length = BNXT_MIN_PKT_SIZE;
460 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
462 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
463 dev_kfree_skb_any(skb);
468 dma_unmap_addr_set(tx_buf, mapping, mapping);
469 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
470 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
472 txbd->tx_bd_haddr = cpu_to_le64(mapping);
474 prod = NEXT_TX(prod);
475 txbd1 = (struct tx_bd_ext *)
476 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
478 txbd1->tx_bd_hsize_lflags = 0;
479 if (skb_is_gso(skb)) {
482 if (skb->encapsulation)
483 hdr_len = skb_inner_network_offset(skb) +
484 skb_inner_network_header_len(skb) +
485 inner_tcp_hdrlen(skb);
487 hdr_len = skb_transport_offset(skb) +
490 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
492 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
493 length = skb_shinfo(skb)->gso_size;
494 txbd1->tx_bd_mss = cpu_to_le32(length);
496 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
497 txbd1->tx_bd_hsize_lflags =
498 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
499 txbd1->tx_bd_mss = 0;
503 flags |= bnxt_lhint_arr[length];
504 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
506 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
507 txbd1->tx_bd_cfa_action =
508 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
509 for (i = 0; i < last_frag; i++) {
510 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
512 prod = NEXT_TX(prod);
513 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
515 len = skb_frag_size(frag);
516 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
519 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
522 tx_buf = &txr->tx_buf_ring[prod];
523 dma_unmap_addr_set(tx_buf, mapping, mapping);
525 txbd->tx_bd_haddr = cpu_to_le64(mapping);
527 flags = len << TX_BD_LEN_SHIFT;
528 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
532 txbd->tx_bd_len_flags_type =
533 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
534 TX_BD_FLAGS_PACKET_END);
536 netdev_tx_sent_queue(txq, skb->len);
538 /* Sync BD data before updating doorbell */
541 prod = NEXT_TX(prod);
544 if (!skb->xmit_more || netif_xmit_stopped(txq))
545 bnxt_db_write(bp, &txr->tx_db, prod);
551 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
552 if (skb->xmit_more && !tx_buf->is_push)
553 bnxt_db_write(bp, &txr->tx_db, prod);
555 netif_tx_stop_queue(txq);
557 /* netif_tx_stop_queue() must be done before checking
558 * tx index in bnxt_tx_avail() below, because in
559 * bnxt_tx_int(), we update tx index before checking for
560 * netif_tx_queue_stopped().
563 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
564 netif_tx_wake_queue(txq);
571 /* start back at beginning and unmap skb */
573 tx_buf = &txr->tx_buf_ring[prod];
575 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
576 skb_headlen(skb), PCI_DMA_TODEVICE);
577 prod = NEXT_TX(prod);
579 /* unmap remaining mapped pages */
580 for (i = 0; i < last_frag; i++) {
581 prod = NEXT_TX(prod);
582 tx_buf = &txr->tx_buf_ring[prod];
583 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
584 skb_frag_size(&skb_shinfo(skb)->frags[i]),
588 dev_kfree_skb_any(skb);
592 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
594 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
595 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
596 u16 cons = txr->tx_cons;
597 struct pci_dev *pdev = bp->pdev;
599 unsigned int tx_bytes = 0;
601 for (i = 0; i < nr_pkts; i++) {
602 struct bnxt_sw_tx_bd *tx_buf;
606 tx_buf = &txr->tx_buf_ring[cons];
607 cons = NEXT_TX(cons);
611 if (tx_buf->is_push) {
616 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
617 skb_headlen(skb), PCI_DMA_TODEVICE);
618 last = tx_buf->nr_frags;
620 for (j = 0; j < last; j++) {
621 cons = NEXT_TX(cons);
622 tx_buf = &txr->tx_buf_ring[cons];
625 dma_unmap_addr(tx_buf, mapping),
626 skb_frag_size(&skb_shinfo(skb)->frags[j]),
631 cons = NEXT_TX(cons);
633 tx_bytes += skb->len;
634 dev_kfree_skb_any(skb);
637 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
640 /* Need to make the tx_cons update visible to bnxt_start_xmit()
641 * before checking for netif_tx_queue_stopped(). Without the
642 * memory barrier, there is a small possibility that bnxt_start_xmit()
643 * will miss it and cause the queue to be stopped forever.
647 if (unlikely(netif_tx_queue_stopped(txq)) &&
648 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
649 __netif_tx_lock(txq, smp_processor_id());
650 if (netif_tx_queue_stopped(txq) &&
651 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
652 txr->dev_state != BNXT_DEV_STATE_CLOSING)
653 netif_tx_wake_queue(txq);
654 __netif_tx_unlock(txq);
658 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
661 struct device *dev = &bp->pdev->dev;
664 page = alloc_page(gfp);
668 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
669 DMA_ATTR_WEAK_ORDERING);
670 if (dma_mapping_error(dev, *mapping)) {
674 *mapping += bp->rx_dma_offset;
678 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
682 struct pci_dev *pdev = bp->pdev;
684 data = kmalloc(bp->rx_buf_size, gfp);
688 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
689 bp->rx_buf_use_size, bp->rx_dir,
690 DMA_ATTR_WEAK_ORDERING);
692 if (dma_mapping_error(&pdev->dev, *mapping)) {
699 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
702 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
703 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
706 if (BNXT_RX_PAGE_MODE(bp)) {
707 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
713 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
715 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
721 rx_buf->data_ptr = data + bp->rx_offset;
723 rx_buf->mapping = mapping;
725 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
729 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
731 u16 prod = rxr->rx_prod;
732 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
733 struct rx_bd *cons_bd, *prod_bd;
735 prod_rx_buf = &rxr->rx_buf_ring[prod];
736 cons_rx_buf = &rxr->rx_buf_ring[cons];
738 prod_rx_buf->data = data;
739 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
741 prod_rx_buf->mapping = cons_rx_buf->mapping;
743 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
744 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
746 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
749 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
751 u16 next, max = rxr->rx_agg_bmap_size;
753 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
755 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
759 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
760 struct bnxt_rx_ring_info *rxr,
764 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
765 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
766 struct pci_dev *pdev = bp->pdev;
769 u16 sw_prod = rxr->rx_sw_agg_prod;
770 unsigned int offset = 0;
772 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
775 page = alloc_page(gfp);
779 rxr->rx_page_offset = 0;
781 offset = rxr->rx_page_offset;
782 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
783 if (rxr->rx_page_offset == PAGE_SIZE)
788 page = alloc_page(gfp);
793 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
794 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
795 DMA_ATTR_WEAK_ORDERING);
796 if (dma_mapping_error(&pdev->dev, mapping)) {
801 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
802 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
804 __set_bit(sw_prod, rxr->rx_agg_bmap);
805 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
806 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
808 rx_agg_buf->page = page;
809 rx_agg_buf->offset = offset;
810 rx_agg_buf->mapping = mapping;
811 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
812 rxbd->rx_bd_opaque = sw_prod;
816 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
819 struct bnxt_napi *bnapi = cpr->bnapi;
820 struct bnxt *bp = bnapi->bp;
821 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
822 u16 prod = rxr->rx_agg_prod;
823 u16 sw_prod = rxr->rx_sw_agg_prod;
826 for (i = 0; i < agg_bufs; i++) {
828 struct rx_agg_cmp *agg;
829 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
830 struct rx_bd *prod_bd;
833 agg = (struct rx_agg_cmp *)
834 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
835 cons = agg->rx_agg_cmp_opaque;
836 __clear_bit(cons, rxr->rx_agg_bmap);
838 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
839 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
841 __set_bit(sw_prod, rxr->rx_agg_bmap);
842 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
843 cons_rx_buf = &rxr->rx_agg_ring[cons];
845 /* It is possible for sw_prod to be equal to cons, so
846 * set cons_rx_buf->page to NULL first.
848 page = cons_rx_buf->page;
849 cons_rx_buf->page = NULL;
850 prod_rx_buf->page = page;
851 prod_rx_buf->offset = cons_rx_buf->offset;
853 prod_rx_buf->mapping = cons_rx_buf->mapping;
855 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
857 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
858 prod_bd->rx_bd_opaque = sw_prod;
860 prod = NEXT_RX_AGG(prod);
861 sw_prod = NEXT_RX_AGG(sw_prod);
862 cp_cons = NEXT_CMP(cp_cons);
864 rxr->rx_agg_prod = prod;
865 rxr->rx_sw_agg_prod = sw_prod;
868 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
869 struct bnxt_rx_ring_info *rxr,
870 u16 cons, void *data, u8 *data_ptr,
872 unsigned int offset_and_len)
874 unsigned int payload = offset_and_len >> 16;
875 unsigned int len = offset_and_len & 0xffff;
876 struct skb_frag_struct *frag;
877 struct page *page = data;
878 u16 prod = rxr->rx_prod;
882 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
884 bnxt_reuse_rx_data(rxr, cons, data);
887 dma_addr -= bp->rx_dma_offset;
888 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
889 DMA_ATTR_WEAK_ORDERING);
891 if (unlikely(!payload))
892 payload = eth_get_headlen(data_ptr, len);
894 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
900 off = (void *)data_ptr - page_address(page);
901 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
902 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
903 payload + NET_IP_ALIGN);
905 frag = &skb_shinfo(skb)->frags[0];
906 skb_frag_size_sub(frag, payload);
907 frag->page_offset += payload;
908 skb->data_len -= payload;
909 skb->tail += payload;
914 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
915 struct bnxt_rx_ring_info *rxr, u16 cons,
916 void *data, u8 *data_ptr,
918 unsigned int offset_and_len)
920 u16 prod = rxr->rx_prod;
924 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
926 bnxt_reuse_rx_data(rxr, cons, data);
930 skb = build_skb(data, 0);
931 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
932 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
938 skb_reserve(skb, bp->rx_offset);
939 skb_put(skb, offset_and_len & 0xffff);
943 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
944 struct bnxt_cp_ring_info *cpr,
945 struct sk_buff *skb, u16 cp_cons,
948 struct bnxt_napi *bnapi = cpr->bnapi;
949 struct pci_dev *pdev = bp->pdev;
950 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
951 u16 prod = rxr->rx_agg_prod;
954 for (i = 0; i < agg_bufs; i++) {
956 struct rx_agg_cmp *agg;
957 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
961 agg = (struct rx_agg_cmp *)
962 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
963 cons = agg->rx_agg_cmp_opaque;
964 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
965 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
967 cons_rx_buf = &rxr->rx_agg_ring[cons];
968 skb_fill_page_desc(skb, i, cons_rx_buf->page,
969 cons_rx_buf->offset, frag_len);
970 __clear_bit(cons, rxr->rx_agg_bmap);
972 /* It is possible for bnxt_alloc_rx_page() to allocate
973 * a sw_prod index that equals the cons index, so we
974 * need to clear the cons entry now.
976 mapping = cons_rx_buf->mapping;
977 page = cons_rx_buf->page;
978 cons_rx_buf->page = NULL;
980 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
981 struct skb_shared_info *shinfo;
982 unsigned int nr_frags;
984 shinfo = skb_shinfo(skb);
985 nr_frags = --shinfo->nr_frags;
986 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
990 cons_rx_buf->page = page;
992 /* Update prod since possibly some pages have been
995 rxr->rx_agg_prod = prod;
996 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1000 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1002 DMA_ATTR_WEAK_ORDERING);
1004 skb->data_len += frag_len;
1005 skb->len += frag_len;
1006 skb->truesize += PAGE_SIZE;
1008 prod = NEXT_RX_AGG(prod);
1009 cp_cons = NEXT_CMP(cp_cons);
1011 rxr->rx_agg_prod = prod;
1015 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1016 u8 agg_bufs, u32 *raw_cons)
1019 struct rx_agg_cmp *agg;
1021 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1022 last = RING_CMP(*raw_cons);
1023 agg = (struct rx_agg_cmp *)
1024 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1025 return RX_AGG_CMP_VALID(agg, *raw_cons);
1028 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1032 struct bnxt *bp = bnapi->bp;
1033 struct pci_dev *pdev = bp->pdev;
1034 struct sk_buff *skb;
1036 skb = napi_alloc_skb(&bnapi->napi, len);
1040 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1043 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1044 len + NET_IP_ALIGN);
1046 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1053 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1054 u32 *raw_cons, void *cmp)
1056 struct rx_cmp *rxcmp = cmp;
1057 u32 tmp_raw_cons = *raw_cons;
1058 u8 cmp_type, agg_bufs = 0;
1060 cmp_type = RX_CMP_TYPE(rxcmp);
1062 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1063 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1065 RX_CMP_AGG_BUFS_SHIFT;
1066 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1067 struct rx_tpa_end_cmp *tpa_end = cmp;
1069 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1070 RX_TPA_END_CMP_AGG_BUFS) >>
1071 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1075 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1078 *raw_cons = tmp_raw_cons;
1082 static void bnxt_queue_sp_work(struct bnxt *bp)
1085 queue_work(bnxt_pf_wq, &bp->sp_task);
1087 schedule_work(&bp->sp_task);
1090 static void bnxt_cancel_sp_work(struct bnxt *bp)
1093 flush_workqueue(bnxt_pf_wq);
1095 cancel_work_sync(&bp->sp_task);
1098 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1100 if (!rxr->bnapi->in_reset) {
1101 rxr->bnapi->in_reset = true;
1102 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1103 bnxt_queue_sp_work(bp);
1105 rxr->rx_next_cons = 0xffff;
1108 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1109 struct rx_tpa_start_cmp *tpa_start,
1110 struct rx_tpa_start_cmp_ext *tpa_start1)
1112 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1114 struct bnxt_tpa_info *tpa_info;
1115 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1116 struct rx_bd *prod_bd;
1119 cons = tpa_start->rx_tpa_start_cmp_opaque;
1120 prod = rxr->rx_prod;
1121 cons_rx_buf = &rxr->rx_buf_ring[cons];
1122 prod_rx_buf = &rxr->rx_buf_ring[prod];
1123 tpa_info = &rxr->rx_tpa[agg_id];
1125 if (unlikely(cons != rxr->rx_next_cons)) {
1126 bnxt_sched_reset(bp, rxr);
1129 /* Store cfa_code in tpa_info to use in tpa_end
1130 * completion processing.
1132 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1133 prod_rx_buf->data = tpa_info->data;
1134 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1136 mapping = tpa_info->mapping;
1137 prod_rx_buf->mapping = mapping;
1139 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1141 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1143 tpa_info->data = cons_rx_buf->data;
1144 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1145 cons_rx_buf->data = NULL;
1146 tpa_info->mapping = cons_rx_buf->mapping;
1149 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1150 RX_TPA_START_CMP_LEN_SHIFT;
1151 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1152 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1154 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1155 tpa_info->gso_type = SKB_GSO_TCPV4;
1156 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1157 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1158 tpa_info->gso_type = SKB_GSO_TCPV6;
1159 tpa_info->rss_hash =
1160 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1162 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1163 tpa_info->gso_type = 0;
1164 if (netif_msg_rx_err(bp))
1165 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1167 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1168 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1169 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1171 rxr->rx_prod = NEXT_RX(prod);
1172 cons = NEXT_RX(cons);
1173 rxr->rx_next_cons = NEXT_RX(cons);
1174 cons_rx_buf = &rxr->rx_buf_ring[cons];
1176 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1177 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1178 cons_rx_buf->data = NULL;
1181 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1185 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1188 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1189 int payload_off, int tcp_ts,
1190 struct sk_buff *skb)
1195 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1196 u32 hdr_info = tpa_info->hdr_info;
1197 bool loopback = false;
1199 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1200 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1201 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1203 /* If the packet is an internal loopback packet, the offsets will
1204 * have an extra 4 bytes.
1206 if (inner_mac_off == 4) {
1208 } else if (inner_mac_off > 4) {
1209 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1212 /* We only support inner iPv4/ipv6. If we don't see the
1213 * correct protocol ID, it must be a loopback packet where
1214 * the offsets are off by 4.
1216 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1220 /* internal loopback packet, subtract all offsets by 4 */
1226 nw_off = inner_ip_off - ETH_HLEN;
1227 skb_set_network_header(skb, nw_off);
1228 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1229 struct ipv6hdr *iph = ipv6_hdr(skb);
1231 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1232 len = skb->len - skb_transport_offset(skb);
1234 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1236 struct iphdr *iph = ip_hdr(skb);
1238 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1239 len = skb->len - skb_transport_offset(skb);
1241 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1244 if (inner_mac_off) { /* tunnel */
1245 struct udphdr *uh = NULL;
1246 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1249 if (proto == htons(ETH_P_IP)) {
1250 struct iphdr *iph = (struct iphdr *)skb->data;
1252 if (iph->protocol == IPPROTO_UDP)
1253 uh = (struct udphdr *)(iph + 1);
1255 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1257 if (iph->nexthdr == IPPROTO_UDP)
1258 uh = (struct udphdr *)(iph + 1);
1262 skb_shinfo(skb)->gso_type |=
1263 SKB_GSO_UDP_TUNNEL_CSUM;
1265 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1272 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1273 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1275 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1276 int payload_off, int tcp_ts,
1277 struct sk_buff *skb)
1281 int len, nw_off, tcp_opt_len = 0;
1286 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1289 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1291 skb_set_network_header(skb, nw_off);
1293 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1294 len = skb->len - skb_transport_offset(skb);
1296 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1297 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1298 struct ipv6hdr *iph;
1300 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1302 skb_set_network_header(skb, nw_off);
1303 iph = ipv6_hdr(skb);
1304 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1305 len = skb->len - skb_transport_offset(skb);
1307 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1309 dev_kfree_skb_any(skb);
1313 if (nw_off) { /* tunnel */
1314 struct udphdr *uh = NULL;
1316 if (skb->protocol == htons(ETH_P_IP)) {
1317 struct iphdr *iph = (struct iphdr *)skb->data;
1319 if (iph->protocol == IPPROTO_UDP)
1320 uh = (struct udphdr *)(iph + 1);
1322 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1324 if (iph->nexthdr == IPPROTO_UDP)
1325 uh = (struct udphdr *)(iph + 1);
1329 skb_shinfo(skb)->gso_type |=
1330 SKB_GSO_UDP_TUNNEL_CSUM;
1332 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1339 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1340 struct bnxt_tpa_info *tpa_info,
1341 struct rx_tpa_end_cmp *tpa_end,
1342 struct rx_tpa_end_cmp_ext *tpa_end1,
1343 struct sk_buff *skb)
1349 segs = TPA_END_TPA_SEGS(tpa_end);
1353 NAPI_GRO_CB(skb)->count = segs;
1354 skb_shinfo(skb)->gso_size =
1355 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1356 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1357 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1358 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1359 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1360 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1362 tcp_gro_complete(skb);
1367 /* Given the cfa_code of a received packet determine which
1368 * netdev (vf-rep or PF) the packet is destined to.
1370 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1372 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1374 /* if vf-rep dev is NULL, the must belongs to the PF */
1375 return dev ? dev : bp->dev;
1378 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1379 struct bnxt_cp_ring_info *cpr,
1381 struct rx_tpa_end_cmp *tpa_end,
1382 struct rx_tpa_end_cmp_ext *tpa_end1,
1385 struct bnxt_napi *bnapi = cpr->bnapi;
1386 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1387 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1388 u8 *data_ptr, agg_bufs;
1389 u16 cp_cons = RING_CMP(*raw_cons);
1391 struct bnxt_tpa_info *tpa_info;
1393 struct sk_buff *skb;
1396 if (unlikely(bnapi->in_reset)) {
1397 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1400 return ERR_PTR(-EBUSY);
1404 tpa_info = &rxr->rx_tpa[agg_id];
1405 data = tpa_info->data;
1406 data_ptr = tpa_info->data_ptr;
1408 len = tpa_info->len;
1409 mapping = tpa_info->mapping;
1411 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1412 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1415 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1416 return ERR_PTR(-EBUSY);
1418 *event |= BNXT_AGG_EVENT;
1419 cp_cons = NEXT_CMP(cp_cons);
1422 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1423 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1424 if (agg_bufs > MAX_SKB_FRAGS)
1425 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1426 agg_bufs, (int)MAX_SKB_FRAGS);
1430 if (len <= bp->rx_copy_thresh) {
1431 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1433 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1438 dma_addr_t new_mapping;
1440 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1442 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1446 tpa_info->data = new_data;
1447 tpa_info->data_ptr = new_data + bp->rx_offset;
1448 tpa_info->mapping = new_mapping;
1450 skb = build_skb(data, 0);
1451 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1452 bp->rx_buf_use_size, bp->rx_dir,
1453 DMA_ATTR_WEAK_ORDERING);
1457 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1460 skb_reserve(skb, bp->rx_offset);
1465 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1467 /* Page reuse already handled by bnxt_rx_pages(). */
1473 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1475 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1476 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1478 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1479 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1480 u16 vlan_proto = tpa_info->metadata >>
1481 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1482 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1484 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1487 skb_checksum_none_assert(skb);
1488 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1489 skb->ip_summed = CHECKSUM_UNNECESSARY;
1491 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1494 if (TPA_END_GRO(tpa_end))
1495 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1500 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1501 struct sk_buff *skb)
1503 if (skb->dev != bp->dev) {
1504 /* this packet belongs to a vf-rep */
1505 bnxt_vf_rep_rx(bp, skb);
1508 skb_record_rx_queue(skb, bnapi->index);
1509 napi_gro_receive(&bnapi->napi, skb);
1512 /* returns the following:
1513 * 1 - 1 packet successfully received
1514 * 0 - successful TPA_START, packet not completed yet
1515 * -EBUSY - completion ring does not have all the agg buffers yet
1516 * -ENOMEM - packet aborted due to out of memory
1517 * -EIO - packet aborted due to hw error indicated in BD
1519 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1520 u32 *raw_cons, u8 *event)
1522 struct bnxt_napi *bnapi = cpr->bnapi;
1523 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1524 struct net_device *dev = bp->dev;
1525 struct rx_cmp *rxcmp;
1526 struct rx_cmp_ext *rxcmp1;
1527 u32 tmp_raw_cons = *raw_cons;
1528 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1529 struct bnxt_sw_rx_bd *rx_buf;
1531 u8 *data_ptr, agg_bufs, cmp_type;
1532 dma_addr_t dma_addr;
1533 struct sk_buff *skb;
1538 rxcmp = (struct rx_cmp *)
1539 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1541 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1542 cp_cons = RING_CMP(tmp_raw_cons);
1543 rxcmp1 = (struct rx_cmp_ext *)
1544 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1546 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1549 cmp_type = RX_CMP_TYPE(rxcmp);
1551 prod = rxr->rx_prod;
1553 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1554 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1555 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1557 *event |= BNXT_RX_EVENT;
1558 goto next_rx_no_prod_no_len;
1560 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1561 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1562 (struct rx_tpa_end_cmp *)rxcmp,
1563 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1570 bnxt_deliver_skb(bp, bnapi, skb);
1573 *event |= BNXT_RX_EVENT;
1574 goto next_rx_no_prod_no_len;
1577 cons = rxcmp->rx_cmp_opaque;
1578 rx_buf = &rxr->rx_buf_ring[cons];
1579 data = rx_buf->data;
1580 data_ptr = rx_buf->data_ptr;
1581 if (unlikely(cons != rxr->rx_next_cons)) {
1582 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1584 bnxt_sched_reset(bp, rxr);
1589 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1590 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1593 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1596 cp_cons = NEXT_CMP(cp_cons);
1597 *event |= BNXT_AGG_EVENT;
1599 *event |= BNXT_RX_EVENT;
1601 rx_buf->data = NULL;
1602 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1603 bnxt_reuse_rx_data(rxr, cons, data);
1605 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1611 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1612 dma_addr = rx_buf->mapping;
1614 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1619 if (len <= bp->rx_copy_thresh) {
1620 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1621 bnxt_reuse_rx_data(rxr, cons, data);
1629 if (rx_buf->data_ptr == data_ptr)
1630 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1633 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1642 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1649 if (RX_CMP_HASH_VALID(rxcmp)) {
1650 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1651 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1653 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1654 if (hash_type != 1 && hash_type != 3)
1655 type = PKT_HASH_TYPE_L3;
1656 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1659 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1660 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1662 if ((rxcmp1->rx_cmp_flags2 &
1663 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1664 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1665 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1666 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1667 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1669 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1672 skb_checksum_none_assert(skb);
1673 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1674 if (dev->features & NETIF_F_RXCSUM) {
1675 skb->ip_summed = CHECKSUM_UNNECESSARY;
1676 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1679 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1680 if (dev->features & NETIF_F_RXCSUM)
1681 bnapi->cp_ring.rx_l4_csum_errors++;
1685 bnxt_deliver_skb(bp, bnapi, skb);
1689 rxr->rx_prod = NEXT_RX(prod);
1690 rxr->rx_next_cons = NEXT_RX(cons);
1692 cpr->rx_packets += 1;
1693 cpr->rx_bytes += len;
1695 next_rx_no_prod_no_len:
1696 *raw_cons = tmp_raw_cons;
1701 /* In netpoll mode, if we are using a combined completion ring, we need to
1702 * discard the rx packets and recycle the buffers.
1704 static int bnxt_force_rx_discard(struct bnxt *bp,
1705 struct bnxt_cp_ring_info *cpr,
1706 u32 *raw_cons, u8 *event)
1708 u32 tmp_raw_cons = *raw_cons;
1709 struct rx_cmp_ext *rxcmp1;
1710 struct rx_cmp *rxcmp;
1714 cp_cons = RING_CMP(tmp_raw_cons);
1715 rxcmp = (struct rx_cmp *)
1716 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1718 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1719 cp_cons = RING_CMP(tmp_raw_cons);
1720 rxcmp1 = (struct rx_cmp_ext *)
1721 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1723 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1726 cmp_type = RX_CMP_TYPE(rxcmp);
1727 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1728 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1729 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1730 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1731 struct rx_tpa_end_cmp_ext *tpa_end1;
1733 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1734 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1735 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1737 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1740 #define BNXT_GET_EVENT_PORT(data) \
1742 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1744 static int bnxt_async_event_process(struct bnxt *bp,
1745 struct hwrm_async_event_cmpl *cmpl)
1747 u16 event_id = le16_to_cpu(cmpl->event_id);
1749 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1751 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1752 u32 data1 = le32_to_cpu(cmpl->event_data1);
1753 struct bnxt_link_info *link_info = &bp->link_info;
1756 goto async_event_process_exit;
1758 /* print unsupported speed warning in forced speed mode only */
1759 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1760 (data1 & 0x20000)) {
1761 u16 fw_speed = link_info->force_link_speed;
1762 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1764 if (speed != SPEED_UNKNOWN)
1765 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1768 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1771 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1772 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1774 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1775 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1777 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1778 u32 data1 = le32_to_cpu(cmpl->event_data1);
1779 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1784 if (bp->pf.port_id != port_id)
1787 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1790 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1792 goto async_event_process_exit;
1793 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1796 goto async_event_process_exit;
1798 bnxt_queue_sp_work(bp);
1799 async_event_process_exit:
1800 bnxt_ulp_async_events(bp, cmpl);
1804 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1806 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1807 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1808 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1809 (struct hwrm_fwd_req_cmpl *)txcmp;
1811 switch (cmpl_type) {
1812 case CMPL_BASE_TYPE_HWRM_DONE:
1813 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1814 if (seq_id == bp->hwrm_intr_seq_id)
1815 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1817 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1820 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1821 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1823 if ((vf_id < bp->pf.first_vf_id) ||
1824 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1825 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1830 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1831 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1832 bnxt_queue_sp_work(bp);
1835 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1836 bnxt_async_event_process(bp,
1837 (struct hwrm_async_event_cmpl *)txcmp);
1846 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1848 struct bnxt_napi *bnapi = dev_instance;
1849 struct bnxt *bp = bnapi->bp;
1850 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1851 u32 cons = RING_CMP(cpr->cp_raw_cons);
1854 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1855 napi_schedule(&bnapi->napi);
1859 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1861 u32 raw_cons = cpr->cp_raw_cons;
1862 u16 cons = RING_CMP(raw_cons);
1863 struct tx_cmp *txcmp;
1865 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1867 return TX_CMP_VALID(txcmp, raw_cons);
1870 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1872 struct bnxt_napi *bnapi = dev_instance;
1873 struct bnxt *bp = bnapi->bp;
1874 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1875 u32 cons = RING_CMP(cpr->cp_raw_cons);
1878 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1880 if (!bnxt_has_work(bp, cpr)) {
1881 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1882 /* return if erroneous interrupt */
1883 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1887 /* disable ring IRQ */
1888 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1890 /* Return here if interrupt is shared and is disabled. */
1891 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1894 napi_schedule(&bnapi->napi);
1898 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1901 struct bnxt_napi *bnapi = cpr->bnapi;
1902 u32 raw_cons = cpr->cp_raw_cons;
1907 struct tx_cmp *txcmp;
1909 cpr->has_more_work = 0;
1913 cons = RING_CMP(raw_cons);
1914 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1916 if (!TX_CMP_VALID(txcmp, raw_cons))
1919 /* The valid test of the entry must be done first before
1920 * reading any further.
1923 cpr->had_work_done = 1;
1924 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1926 /* return full budget so NAPI will complete. */
1927 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1929 raw_cons = NEXT_RAW_CMP(raw_cons);
1931 cpr->has_more_work = 1;
1934 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1936 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1938 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1940 if (likely(rc >= 0))
1942 /* Increment rx_pkts when rc is -ENOMEM to count towards
1943 * the NAPI budget. Otherwise, we may potentially loop
1944 * here forever if we consistently cannot allocate
1947 else if (rc == -ENOMEM && budget)
1949 else if (rc == -EBUSY) /* partial completion */
1951 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1952 CMPL_BASE_TYPE_HWRM_DONE) ||
1953 (TX_CMP_TYPE(txcmp) ==
1954 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1955 (TX_CMP_TYPE(txcmp) ==
1956 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1957 bnxt_hwrm_handler(bp, txcmp);
1959 raw_cons = NEXT_RAW_CMP(raw_cons);
1961 if (rx_pkts && rx_pkts == budget) {
1962 cpr->has_more_work = 1;
1967 if (event & BNXT_TX_EVENT) {
1968 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1969 u16 prod = txr->tx_prod;
1971 /* Sync BD data before updating doorbell */
1974 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
1977 cpr->cp_raw_cons = raw_cons;
1978 bnapi->tx_pkts += tx_pkts;
1979 bnapi->events |= event;
1983 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
1985 if (bnapi->tx_pkts) {
1986 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
1990 if (bnapi->events & BNXT_RX_EVENT) {
1991 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1993 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
1994 if (bnapi->events & BNXT_AGG_EVENT)
1995 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2000 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2003 struct bnxt_napi *bnapi = cpr->bnapi;
2006 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2008 /* ACK completion ring before freeing tx ring and producing new
2009 * buffers in rx/agg rings to prevent overflowing the completion
2012 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2014 __bnxt_poll_work_done(bp, bnapi);
2018 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2020 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2021 struct bnxt *bp = bnapi->bp;
2022 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2023 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2024 struct tx_cmp *txcmp;
2025 struct rx_cmp_ext *rxcmp1;
2026 u32 cp_cons, tmp_raw_cons;
2027 u32 raw_cons = cpr->cp_raw_cons;
2034 cp_cons = RING_CMP(raw_cons);
2035 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2037 if (!TX_CMP_VALID(txcmp, raw_cons))
2040 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2041 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2042 cp_cons = RING_CMP(tmp_raw_cons);
2043 rxcmp1 = (struct rx_cmp_ext *)
2044 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2046 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2049 /* force an error to recycle the buffer */
2050 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2051 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2053 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2054 if (likely(rc == -EIO) && budget)
2056 else if (rc == -EBUSY) /* partial completion */
2058 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2059 CMPL_BASE_TYPE_HWRM_DONE)) {
2060 bnxt_hwrm_handler(bp, txcmp);
2063 "Invalid completion received on special ring\n");
2065 raw_cons = NEXT_RAW_CMP(raw_cons);
2067 if (rx_pkts == budget)
2071 cpr->cp_raw_cons = raw_cons;
2072 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2073 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2075 if (event & BNXT_AGG_EVENT)
2076 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2078 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2079 napi_complete_done(napi, rx_pkts);
2080 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2085 static int bnxt_poll(struct napi_struct *napi, int budget)
2087 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2088 struct bnxt *bp = bnapi->bp;
2089 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2093 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2095 if (work_done >= budget) {
2097 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2101 if (!bnxt_has_work(bp, cpr)) {
2102 if (napi_complete_done(napi, work_done))
2103 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2107 if (bp->flags & BNXT_FLAG_DIM) {
2108 struct net_dim_sample dim_sample;
2110 net_dim_sample(cpr->event_ctr,
2114 net_dim(&cpr->dim, dim_sample);
2120 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2122 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2123 int i, work_done = 0;
2125 for (i = 0; i < 2; i++) {
2126 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2129 work_done += __bnxt_poll_work(bp, cpr2,
2130 budget - work_done);
2131 cpr->has_more_work |= cpr2->has_more_work;
2137 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2138 u64 dbr_type, bool all)
2140 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2143 for (i = 0; i < 2; i++) {
2144 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2145 struct bnxt_db_info *db;
2147 if (cpr2 && (all || cpr2->had_work_done)) {
2149 writeq(db->db_key64 | dbr_type |
2150 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2151 cpr2->had_work_done = 0;
2154 __bnxt_poll_work_done(bp, bnapi);
2157 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2159 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2160 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2161 u32 raw_cons = cpr->cp_raw_cons;
2162 struct bnxt *bp = bnapi->bp;
2163 struct nqe_cn *nqcmp;
2167 if (cpr->has_more_work) {
2168 cpr->has_more_work = 0;
2169 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2170 if (cpr->has_more_work) {
2171 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2174 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2175 if (napi_complete_done(napi, work_done))
2176 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2180 cons = RING_CMP(raw_cons);
2181 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2183 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2184 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2186 cpr->cp_raw_cons = raw_cons;
2187 if (napi_complete_done(napi, work_done))
2188 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2193 /* The valid test of the entry must be done first before
2194 * reading any further.
2198 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2199 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2200 struct bnxt_cp_ring_info *cpr2;
2202 cpr2 = cpr->cp_ring_arr[idx];
2203 work_done += __bnxt_poll_work(bp, cpr2,
2204 budget - work_done);
2205 cpr->has_more_work = cpr2->has_more_work;
2207 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2209 raw_cons = NEXT_RAW_CMP(raw_cons);
2210 if (cpr->has_more_work)
2213 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2214 cpr->cp_raw_cons = raw_cons;
2218 static void bnxt_free_tx_skbs(struct bnxt *bp)
2221 struct pci_dev *pdev = bp->pdev;
2226 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2227 for (i = 0; i < bp->tx_nr_rings; i++) {
2228 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2231 for (j = 0; j < max_idx;) {
2232 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2233 struct sk_buff *skb = tx_buf->skb;
2243 if (tx_buf->is_push) {
2249 dma_unmap_single(&pdev->dev,
2250 dma_unmap_addr(tx_buf, mapping),
2254 last = tx_buf->nr_frags;
2256 for (k = 0; k < last; k++, j++) {
2257 int ring_idx = j & bp->tx_ring_mask;
2258 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2260 tx_buf = &txr->tx_buf_ring[ring_idx];
2263 dma_unmap_addr(tx_buf, mapping),
2264 skb_frag_size(frag), PCI_DMA_TODEVICE);
2268 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2272 static void bnxt_free_rx_skbs(struct bnxt *bp)
2274 int i, max_idx, max_agg_idx;
2275 struct pci_dev *pdev = bp->pdev;
2280 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2281 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2282 for (i = 0; i < bp->rx_nr_rings; i++) {
2283 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2287 for (j = 0; j < MAX_TPA; j++) {
2288 struct bnxt_tpa_info *tpa_info =
2290 u8 *data = tpa_info->data;
2295 dma_unmap_single_attrs(&pdev->dev,
2297 bp->rx_buf_use_size,
2299 DMA_ATTR_WEAK_ORDERING);
2301 tpa_info->data = NULL;
2307 for (j = 0; j < max_idx; j++) {
2308 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2309 dma_addr_t mapping = rx_buf->mapping;
2310 void *data = rx_buf->data;
2315 rx_buf->data = NULL;
2317 if (BNXT_RX_PAGE_MODE(bp)) {
2318 mapping -= bp->rx_dma_offset;
2319 dma_unmap_page_attrs(&pdev->dev, mapping,
2320 PAGE_SIZE, bp->rx_dir,
2321 DMA_ATTR_WEAK_ORDERING);
2324 dma_unmap_single_attrs(&pdev->dev, mapping,
2325 bp->rx_buf_use_size,
2327 DMA_ATTR_WEAK_ORDERING);
2332 for (j = 0; j < max_agg_idx; j++) {
2333 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2334 &rxr->rx_agg_ring[j];
2335 struct page *page = rx_agg_buf->page;
2340 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2343 DMA_ATTR_WEAK_ORDERING);
2345 rx_agg_buf->page = NULL;
2346 __clear_bit(j, rxr->rx_agg_bmap);
2351 __free_page(rxr->rx_page);
2352 rxr->rx_page = NULL;
2357 static void bnxt_free_skbs(struct bnxt *bp)
2359 bnxt_free_tx_skbs(bp);
2360 bnxt_free_rx_skbs(bp);
2363 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2365 struct pci_dev *pdev = bp->pdev;
2368 for (i = 0; i < rmem->nr_pages; i++) {
2369 if (!rmem->pg_arr[i])
2372 dma_free_coherent(&pdev->dev, rmem->page_size,
2373 rmem->pg_arr[i], rmem->dma_arr[i]);
2375 rmem->pg_arr[i] = NULL;
2378 size_t pg_tbl_size = rmem->nr_pages * 8;
2380 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2381 pg_tbl_size = rmem->page_size;
2382 dma_free_coherent(&pdev->dev, pg_tbl_size,
2383 rmem->pg_tbl, rmem->pg_tbl_map);
2384 rmem->pg_tbl = NULL;
2386 if (rmem->vmem_size && *rmem->vmem) {
2392 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2394 struct pci_dev *pdev = bp->pdev;
2398 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2399 valid_bit = PTU_PTE_VALID;
2400 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2401 size_t pg_tbl_size = rmem->nr_pages * 8;
2403 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2404 pg_tbl_size = rmem->page_size;
2405 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2412 for (i = 0; i < rmem->nr_pages; i++) {
2413 u64 extra_bits = valid_bit;
2415 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2419 if (!rmem->pg_arr[i])
2422 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2423 if (i == rmem->nr_pages - 2 &&
2424 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2425 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2426 else if (i == rmem->nr_pages - 1 &&
2427 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2428 extra_bits |= PTU_PTE_LAST;
2430 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2434 if (rmem->vmem_size) {
2435 *rmem->vmem = vzalloc(rmem->vmem_size);
2442 static void bnxt_free_rx_rings(struct bnxt *bp)
2449 for (i = 0; i < bp->rx_nr_rings; i++) {
2450 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2451 struct bnxt_ring_struct *ring;
2454 bpf_prog_put(rxr->xdp_prog);
2456 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2457 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2462 kfree(rxr->rx_agg_bmap);
2463 rxr->rx_agg_bmap = NULL;
2465 ring = &rxr->rx_ring_struct;
2466 bnxt_free_ring(bp, &ring->ring_mem);
2468 ring = &rxr->rx_agg_ring_struct;
2469 bnxt_free_ring(bp, &ring->ring_mem);
2473 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2475 int i, rc, agg_rings = 0, tpa_rings = 0;
2480 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2483 if (bp->flags & BNXT_FLAG_TPA)
2486 for (i = 0; i < bp->rx_nr_rings; i++) {
2487 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2488 struct bnxt_ring_struct *ring;
2490 ring = &rxr->rx_ring_struct;
2492 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2496 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2504 ring = &rxr->rx_agg_ring_struct;
2505 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2510 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2511 mem_size = rxr->rx_agg_bmap_size / 8;
2512 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2513 if (!rxr->rx_agg_bmap)
2517 rxr->rx_tpa = kcalloc(MAX_TPA,
2518 sizeof(struct bnxt_tpa_info),
2528 static void bnxt_free_tx_rings(struct bnxt *bp)
2531 struct pci_dev *pdev = bp->pdev;
2536 for (i = 0; i < bp->tx_nr_rings; i++) {
2537 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2538 struct bnxt_ring_struct *ring;
2541 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2542 txr->tx_push, txr->tx_push_mapping);
2543 txr->tx_push = NULL;
2546 ring = &txr->tx_ring_struct;
2548 bnxt_free_ring(bp, &ring->ring_mem);
2552 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2555 struct pci_dev *pdev = bp->pdev;
2557 bp->tx_push_size = 0;
2558 if (bp->tx_push_thresh) {
2561 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2562 bp->tx_push_thresh);
2564 if (push_size > 256) {
2566 bp->tx_push_thresh = 0;
2569 bp->tx_push_size = push_size;
2572 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2573 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2574 struct bnxt_ring_struct *ring;
2577 ring = &txr->tx_ring_struct;
2579 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2583 ring->grp_idx = txr->bnapi->index;
2584 if (bp->tx_push_size) {
2587 /* One pre-allocated DMA buffer to backup
2590 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2592 &txr->tx_push_mapping,
2598 mapping = txr->tx_push_mapping +
2599 sizeof(struct tx_push_bd);
2600 txr->data_mapping = cpu_to_le64(mapping);
2602 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2604 qidx = bp->tc_to_qidx[j];
2605 ring->queue_id = bp->q_info[qidx].queue_id;
2606 if (i < bp->tx_nr_rings_xdp)
2608 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2614 static void bnxt_free_cp_rings(struct bnxt *bp)
2621 for (i = 0; i < bp->cp_nr_rings; i++) {
2622 struct bnxt_napi *bnapi = bp->bnapi[i];
2623 struct bnxt_cp_ring_info *cpr;
2624 struct bnxt_ring_struct *ring;
2630 cpr = &bnapi->cp_ring;
2631 ring = &cpr->cp_ring_struct;
2633 bnxt_free_ring(bp, &ring->ring_mem);
2635 for (j = 0; j < 2; j++) {
2636 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2639 ring = &cpr2->cp_ring_struct;
2640 bnxt_free_ring(bp, &ring->ring_mem);
2642 cpr->cp_ring_arr[j] = NULL;
2648 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2650 struct bnxt_ring_mem_info *rmem;
2651 struct bnxt_ring_struct *ring;
2652 struct bnxt_cp_ring_info *cpr;
2655 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2659 ring = &cpr->cp_ring_struct;
2660 rmem = &ring->ring_mem;
2661 rmem->nr_pages = bp->cp_nr_pages;
2662 rmem->page_size = HW_CMPD_RING_SIZE;
2663 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2664 rmem->dma_arr = cpr->cp_desc_mapping;
2665 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2666 rc = bnxt_alloc_ring(bp, rmem);
2668 bnxt_free_ring(bp, rmem);
2675 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2677 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2678 int i, rc, ulp_base_vec, ulp_msix;
2680 ulp_msix = bnxt_get_ulp_msix_num(bp);
2681 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2682 for (i = 0; i < bp->cp_nr_rings; i++) {
2683 struct bnxt_napi *bnapi = bp->bnapi[i];
2684 struct bnxt_cp_ring_info *cpr;
2685 struct bnxt_ring_struct *ring;
2690 cpr = &bnapi->cp_ring;
2692 ring = &cpr->cp_ring_struct;
2694 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2698 if (ulp_msix && i >= ulp_base_vec)
2699 ring->map_idx = i + ulp_msix;
2703 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2706 if (i < bp->rx_nr_rings) {
2707 struct bnxt_cp_ring_info *cpr2 =
2708 bnxt_alloc_cp_sub_ring(bp);
2710 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2713 cpr2->bnapi = bnapi;
2715 if ((sh && i < bp->tx_nr_rings) ||
2716 (!sh && i >= bp->rx_nr_rings)) {
2717 struct bnxt_cp_ring_info *cpr2 =
2718 bnxt_alloc_cp_sub_ring(bp);
2720 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2723 cpr2->bnapi = bnapi;
2729 static void bnxt_init_ring_struct(struct bnxt *bp)
2733 for (i = 0; i < bp->cp_nr_rings; i++) {
2734 struct bnxt_napi *bnapi = bp->bnapi[i];
2735 struct bnxt_ring_mem_info *rmem;
2736 struct bnxt_cp_ring_info *cpr;
2737 struct bnxt_rx_ring_info *rxr;
2738 struct bnxt_tx_ring_info *txr;
2739 struct bnxt_ring_struct *ring;
2744 cpr = &bnapi->cp_ring;
2745 ring = &cpr->cp_ring_struct;
2746 rmem = &ring->ring_mem;
2747 rmem->nr_pages = bp->cp_nr_pages;
2748 rmem->page_size = HW_CMPD_RING_SIZE;
2749 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2750 rmem->dma_arr = cpr->cp_desc_mapping;
2751 rmem->vmem_size = 0;
2753 rxr = bnapi->rx_ring;
2757 ring = &rxr->rx_ring_struct;
2758 rmem = &ring->ring_mem;
2759 rmem->nr_pages = bp->rx_nr_pages;
2760 rmem->page_size = HW_RXBD_RING_SIZE;
2761 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2762 rmem->dma_arr = rxr->rx_desc_mapping;
2763 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2764 rmem->vmem = (void **)&rxr->rx_buf_ring;
2766 ring = &rxr->rx_agg_ring_struct;
2767 rmem = &ring->ring_mem;
2768 rmem->nr_pages = bp->rx_agg_nr_pages;
2769 rmem->page_size = HW_RXBD_RING_SIZE;
2770 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2771 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2772 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2773 rmem->vmem = (void **)&rxr->rx_agg_ring;
2776 txr = bnapi->tx_ring;
2780 ring = &txr->tx_ring_struct;
2781 rmem = &ring->ring_mem;
2782 rmem->nr_pages = bp->tx_nr_pages;
2783 rmem->page_size = HW_RXBD_RING_SIZE;
2784 rmem->pg_arr = (void **)txr->tx_desc_ring;
2785 rmem->dma_arr = txr->tx_desc_mapping;
2786 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2787 rmem->vmem = (void **)&txr->tx_buf_ring;
2791 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2795 struct rx_bd **rx_buf_ring;
2797 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2798 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2802 rxbd = rx_buf_ring[i];
2806 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2807 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2808 rxbd->rx_bd_opaque = prod;
2813 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2815 struct net_device *dev = bp->dev;
2816 struct bnxt_rx_ring_info *rxr;
2817 struct bnxt_ring_struct *ring;
2821 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2822 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2824 if (NET_IP_ALIGN == 2)
2825 type |= RX_BD_FLAGS_SOP;
2827 rxr = &bp->rx_ring[ring_nr];
2828 ring = &rxr->rx_ring_struct;
2829 bnxt_init_rxbd_pages(ring, type);
2831 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2832 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2833 if (IS_ERR(rxr->xdp_prog)) {
2834 int rc = PTR_ERR(rxr->xdp_prog);
2836 rxr->xdp_prog = NULL;
2840 prod = rxr->rx_prod;
2841 for (i = 0; i < bp->rx_ring_size; i++) {
2842 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2843 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2844 ring_nr, i, bp->rx_ring_size);
2847 prod = NEXT_RX(prod);
2849 rxr->rx_prod = prod;
2850 ring->fw_ring_id = INVALID_HW_RING_ID;
2852 ring = &rxr->rx_agg_ring_struct;
2853 ring->fw_ring_id = INVALID_HW_RING_ID;
2855 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2858 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2859 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2861 bnxt_init_rxbd_pages(ring, type);
2863 prod = rxr->rx_agg_prod;
2864 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2865 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2866 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2867 ring_nr, i, bp->rx_ring_size);
2870 prod = NEXT_RX_AGG(prod);
2872 rxr->rx_agg_prod = prod;
2874 if (bp->flags & BNXT_FLAG_TPA) {
2879 for (i = 0; i < MAX_TPA; i++) {
2880 data = __bnxt_alloc_rx_data(bp, &mapping,
2885 rxr->rx_tpa[i].data = data;
2886 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2887 rxr->rx_tpa[i].mapping = mapping;
2890 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2898 static void bnxt_init_cp_rings(struct bnxt *bp)
2902 for (i = 0; i < bp->cp_nr_rings; i++) {
2903 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2904 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2906 ring->fw_ring_id = INVALID_HW_RING_ID;
2907 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2908 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2909 for (j = 0; j < 2; j++) {
2910 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2915 ring = &cpr2->cp_ring_struct;
2916 ring->fw_ring_id = INVALID_HW_RING_ID;
2917 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2918 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2923 static int bnxt_init_rx_rings(struct bnxt *bp)
2927 if (BNXT_RX_PAGE_MODE(bp)) {
2928 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2929 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2931 bp->rx_offset = BNXT_RX_OFFSET;
2932 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2935 for (i = 0; i < bp->rx_nr_rings; i++) {
2936 rc = bnxt_init_one_rx_ring(bp, i);
2944 static int bnxt_init_tx_rings(struct bnxt *bp)
2948 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2951 for (i = 0; i < bp->tx_nr_rings; i++) {
2952 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2953 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2955 ring->fw_ring_id = INVALID_HW_RING_ID;
2961 static void bnxt_free_ring_grps(struct bnxt *bp)
2963 kfree(bp->grp_info);
2964 bp->grp_info = NULL;
2967 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2972 bp->grp_info = kcalloc(bp->cp_nr_rings,
2973 sizeof(struct bnxt_ring_grp_info),
2978 for (i = 0; i < bp->cp_nr_rings; i++) {
2980 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2981 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2982 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2983 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2984 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2989 static void bnxt_free_vnics(struct bnxt *bp)
2991 kfree(bp->vnic_info);
2992 bp->vnic_info = NULL;
2996 static int bnxt_alloc_vnics(struct bnxt *bp)
3000 #ifdef CONFIG_RFS_ACCEL
3001 if (bp->flags & BNXT_FLAG_RFS)
3002 num_vnics += bp->rx_nr_rings;
3005 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3008 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3013 bp->nr_vnics = num_vnics;
3017 static void bnxt_init_vnics(struct bnxt *bp)
3021 for (i = 0; i < bp->nr_vnics; i++) {
3022 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3025 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3026 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3027 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3029 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3031 if (bp->vnic_info[i].rss_hash_key) {
3033 prandom_bytes(vnic->rss_hash_key,
3036 memcpy(vnic->rss_hash_key,
3037 bp->vnic_info[0].rss_hash_key,
3043 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3047 pages = ring_size / desc_per_pg;
3054 while (pages & (pages - 1))
3060 void bnxt_set_tpa_flags(struct bnxt *bp)
3062 bp->flags &= ~BNXT_FLAG_TPA;
3063 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3065 if (bp->dev->features & NETIF_F_LRO)
3066 bp->flags |= BNXT_FLAG_LRO;
3067 else if (bp->dev->features & NETIF_F_GRO_HW)
3068 bp->flags |= BNXT_FLAG_GRO;
3071 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3074 void bnxt_set_ring_params(struct bnxt *bp)
3076 u32 ring_size, rx_size, rx_space;
3077 u32 agg_factor = 0, agg_ring_size = 0;
3079 /* 8 for CRC and VLAN */
3080 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3082 rx_space = rx_size + NET_SKB_PAD +
3083 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3085 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3086 ring_size = bp->rx_ring_size;
3087 bp->rx_agg_ring_size = 0;
3088 bp->rx_agg_nr_pages = 0;
3090 if (bp->flags & BNXT_FLAG_TPA)
3091 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3093 bp->flags &= ~BNXT_FLAG_JUMBO;
3094 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3097 bp->flags |= BNXT_FLAG_JUMBO;
3098 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3099 if (jumbo_factor > agg_factor)
3100 agg_factor = jumbo_factor;
3102 agg_ring_size = ring_size * agg_factor;
3104 if (agg_ring_size) {
3105 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3107 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3108 u32 tmp = agg_ring_size;
3110 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3111 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3112 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3113 tmp, agg_ring_size);
3115 bp->rx_agg_ring_size = agg_ring_size;
3116 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3117 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3118 rx_space = rx_size + NET_SKB_PAD +
3119 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3122 bp->rx_buf_use_size = rx_size;
3123 bp->rx_buf_size = rx_space;
3125 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3126 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3128 ring_size = bp->tx_ring_size;
3129 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3130 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3132 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3133 bp->cp_ring_size = ring_size;
3135 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3136 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3137 bp->cp_nr_pages = MAX_CP_PAGES;
3138 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3139 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3140 ring_size, bp->cp_ring_size);
3142 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3143 bp->cp_ring_mask = bp->cp_bit - 1;
3146 /* Changing allocation mode of RX rings.
3147 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3149 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3152 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3155 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3156 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3157 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3158 bp->rx_dir = DMA_BIDIRECTIONAL;
3159 bp->rx_skb_func = bnxt_rx_page_skb;
3160 /* Disable LRO or GRO_HW */
3161 netdev_update_features(bp->dev);
3163 bp->dev->max_mtu = bp->max_mtu;
3164 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3165 bp->rx_dir = DMA_FROM_DEVICE;
3166 bp->rx_skb_func = bnxt_rx_skb;
3171 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3174 struct bnxt_vnic_info *vnic;
3175 struct pci_dev *pdev = bp->pdev;
3180 for (i = 0; i < bp->nr_vnics; i++) {
3181 vnic = &bp->vnic_info[i];
3183 kfree(vnic->fw_grp_ids);
3184 vnic->fw_grp_ids = NULL;
3186 kfree(vnic->uc_list);
3187 vnic->uc_list = NULL;
3189 if (vnic->mc_list) {
3190 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3191 vnic->mc_list, vnic->mc_list_mapping);
3192 vnic->mc_list = NULL;
3195 if (vnic->rss_table) {
3196 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3198 vnic->rss_table_dma_addr);
3199 vnic->rss_table = NULL;
3202 vnic->rss_hash_key = NULL;
3207 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3209 int i, rc = 0, size;
3210 struct bnxt_vnic_info *vnic;
3211 struct pci_dev *pdev = bp->pdev;
3214 for (i = 0; i < bp->nr_vnics; i++) {
3215 vnic = &bp->vnic_info[i];
3217 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3218 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3221 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3222 if (!vnic->uc_list) {
3229 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3230 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3232 dma_alloc_coherent(&pdev->dev,
3234 &vnic->mc_list_mapping,
3236 if (!vnic->mc_list) {
3242 if (bp->flags & BNXT_FLAG_CHIP_P5)
3243 goto vnic_skip_grps;
3245 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3246 max_rings = bp->rx_nr_rings;
3250 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3251 if (!vnic->fw_grp_ids) {
3256 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3257 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3260 /* Allocate rss table and hash key */
3261 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3262 &vnic->rss_table_dma_addr,
3264 if (!vnic->rss_table) {
3269 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3271 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3272 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3280 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3282 struct pci_dev *pdev = bp->pdev;
3284 if (bp->hwrm_cmd_resp_addr) {
3285 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3286 bp->hwrm_cmd_resp_dma_addr);
3287 bp->hwrm_cmd_resp_addr = NULL;
3290 if (bp->hwrm_cmd_kong_resp_addr) {
3291 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3292 bp->hwrm_cmd_kong_resp_addr,
3293 bp->hwrm_cmd_kong_resp_dma_addr);
3294 bp->hwrm_cmd_kong_resp_addr = NULL;
3298 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3300 struct pci_dev *pdev = bp->pdev;
3302 bp->hwrm_cmd_kong_resp_addr =
3303 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3304 &bp->hwrm_cmd_kong_resp_dma_addr,
3306 if (!bp->hwrm_cmd_kong_resp_addr)
3312 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3314 struct pci_dev *pdev = bp->pdev;
3316 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3317 &bp->hwrm_cmd_resp_dma_addr,
3319 if (!bp->hwrm_cmd_resp_addr)
3325 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3327 if (bp->hwrm_short_cmd_req_addr) {
3328 struct pci_dev *pdev = bp->pdev;
3330 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3331 bp->hwrm_short_cmd_req_addr,
3332 bp->hwrm_short_cmd_req_dma_addr);
3333 bp->hwrm_short_cmd_req_addr = NULL;
3337 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3339 struct pci_dev *pdev = bp->pdev;
3341 bp->hwrm_short_cmd_req_addr =
3342 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3343 &bp->hwrm_short_cmd_req_dma_addr,
3345 if (!bp->hwrm_short_cmd_req_addr)
3351 static void bnxt_free_port_stats(struct bnxt *bp)
3353 struct pci_dev *pdev = bp->pdev;
3355 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3356 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3358 if (bp->hw_rx_port_stats) {
3359 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3360 bp->hw_rx_port_stats,
3361 bp->hw_rx_port_stats_map);
3362 bp->hw_rx_port_stats = NULL;
3365 if (bp->hw_tx_port_stats_ext) {
3366 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3367 bp->hw_tx_port_stats_ext,
3368 bp->hw_tx_port_stats_ext_map);
3369 bp->hw_tx_port_stats_ext = NULL;
3372 if (bp->hw_rx_port_stats_ext) {
3373 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3374 bp->hw_rx_port_stats_ext,
3375 bp->hw_rx_port_stats_ext_map);
3376 bp->hw_rx_port_stats_ext = NULL;
3380 static void bnxt_free_ring_stats(struct bnxt *bp)
3382 struct pci_dev *pdev = bp->pdev;
3388 size = sizeof(struct ctx_hw_stats);
3390 for (i = 0; i < bp->cp_nr_rings; i++) {
3391 struct bnxt_napi *bnapi = bp->bnapi[i];
3392 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3394 if (cpr->hw_stats) {
3395 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3397 cpr->hw_stats = NULL;
3402 static int bnxt_alloc_stats(struct bnxt *bp)
3405 struct pci_dev *pdev = bp->pdev;
3407 size = sizeof(struct ctx_hw_stats);
3409 for (i = 0; i < bp->cp_nr_rings; i++) {
3410 struct bnxt_napi *bnapi = bp->bnapi[i];
3411 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3413 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3419 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3422 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3423 if (bp->hw_rx_port_stats)
3424 goto alloc_ext_stats;
3426 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3427 sizeof(struct tx_port_stats) + 1024;
3429 bp->hw_rx_port_stats =
3430 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3431 &bp->hw_rx_port_stats_map,
3433 if (!bp->hw_rx_port_stats)
3436 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3438 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3439 sizeof(struct rx_port_stats) + 512;
3440 bp->flags |= BNXT_FLAG_PORT_STATS;
3443 /* Display extended statistics only if FW supports it */
3444 if (bp->hwrm_spec_code < 0x10804 ||
3445 bp->hwrm_spec_code == 0x10900)
3448 if (bp->hw_rx_port_stats_ext)
3449 goto alloc_tx_ext_stats;
3451 bp->hw_rx_port_stats_ext =
3452 dma_alloc_coherent(&pdev->dev,
3453 sizeof(struct rx_port_stats_ext),
3454 &bp->hw_rx_port_stats_ext_map,
3456 if (!bp->hw_rx_port_stats_ext)
3460 if (bp->hw_tx_port_stats_ext)
3463 if (bp->hwrm_spec_code >= 0x10902) {
3464 bp->hw_tx_port_stats_ext =
3465 dma_alloc_coherent(&pdev->dev,
3466 sizeof(struct tx_port_stats_ext),
3467 &bp->hw_tx_port_stats_ext_map,
3470 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3475 static void bnxt_clear_ring_indices(struct bnxt *bp)
3482 for (i = 0; i < bp->cp_nr_rings; i++) {
3483 struct bnxt_napi *bnapi = bp->bnapi[i];
3484 struct bnxt_cp_ring_info *cpr;
3485 struct bnxt_rx_ring_info *rxr;
3486 struct bnxt_tx_ring_info *txr;
3491 cpr = &bnapi->cp_ring;
3492 cpr->cp_raw_cons = 0;
3494 txr = bnapi->tx_ring;
3500 rxr = bnapi->rx_ring;
3503 rxr->rx_agg_prod = 0;
3504 rxr->rx_sw_agg_prod = 0;
3505 rxr->rx_next_cons = 0;
3510 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3512 #ifdef CONFIG_RFS_ACCEL
3515 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3516 * safe to delete the hash table.
3518 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3519 struct hlist_head *head;
3520 struct hlist_node *tmp;
3521 struct bnxt_ntuple_filter *fltr;
3523 head = &bp->ntp_fltr_hash_tbl[i];
3524 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3525 hlist_del(&fltr->hash);
3530 kfree(bp->ntp_fltr_bmap);
3531 bp->ntp_fltr_bmap = NULL;
3533 bp->ntp_fltr_count = 0;
3537 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3539 #ifdef CONFIG_RFS_ACCEL
3542 if (!(bp->flags & BNXT_FLAG_RFS))
3545 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3546 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3548 bp->ntp_fltr_count = 0;
3549 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3553 if (!bp->ntp_fltr_bmap)
3562 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3564 bnxt_free_vnic_attributes(bp);
3565 bnxt_free_tx_rings(bp);
3566 bnxt_free_rx_rings(bp);
3567 bnxt_free_cp_rings(bp);
3568 bnxt_free_ntp_fltrs(bp, irq_re_init);
3570 bnxt_free_ring_stats(bp);
3571 bnxt_free_ring_grps(bp);
3572 bnxt_free_vnics(bp);
3573 kfree(bp->tx_ring_map);
3574 bp->tx_ring_map = NULL;
3582 bnxt_clear_ring_indices(bp);
3586 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3588 int i, j, rc, size, arr_size;
3592 /* Allocate bnapi mem pointer array and mem block for
3595 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3597 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3598 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3604 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3605 bp->bnapi[i] = bnapi;
3606 bp->bnapi[i]->index = i;
3607 bp->bnapi[i]->bp = bp;
3608 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3609 struct bnxt_cp_ring_info *cpr =
3610 &bp->bnapi[i]->cp_ring;
3612 cpr->cp_ring_struct.ring_mem.flags =
3613 BNXT_RMEM_RING_PTE_FLAG;
3617 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3618 sizeof(struct bnxt_rx_ring_info),
3623 for (i = 0; i < bp->rx_nr_rings; i++) {
3624 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3626 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3627 rxr->rx_ring_struct.ring_mem.flags =
3628 BNXT_RMEM_RING_PTE_FLAG;
3629 rxr->rx_agg_ring_struct.ring_mem.flags =
3630 BNXT_RMEM_RING_PTE_FLAG;
3632 rxr->bnapi = bp->bnapi[i];
3633 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3636 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3637 sizeof(struct bnxt_tx_ring_info),
3642 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3645 if (!bp->tx_ring_map)
3648 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3651 j = bp->rx_nr_rings;
3653 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3654 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3656 if (bp->flags & BNXT_FLAG_CHIP_P5)
3657 txr->tx_ring_struct.ring_mem.flags =
3658 BNXT_RMEM_RING_PTE_FLAG;
3659 txr->bnapi = bp->bnapi[j];
3660 bp->bnapi[j]->tx_ring = txr;
3661 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3662 if (i >= bp->tx_nr_rings_xdp) {
3663 txr->txq_index = i - bp->tx_nr_rings_xdp;
3664 bp->bnapi[j]->tx_int = bnxt_tx_int;
3666 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3667 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3671 rc = bnxt_alloc_stats(bp);
3675 rc = bnxt_alloc_ntp_fltrs(bp);
3679 rc = bnxt_alloc_vnics(bp);
3684 bnxt_init_ring_struct(bp);
3686 rc = bnxt_alloc_rx_rings(bp);
3690 rc = bnxt_alloc_tx_rings(bp);
3694 rc = bnxt_alloc_cp_rings(bp);
3698 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3699 BNXT_VNIC_UCAST_FLAG;
3700 rc = bnxt_alloc_vnic_attributes(bp);
3706 bnxt_free_mem(bp, true);
3710 static void bnxt_disable_int(struct bnxt *bp)
3717 for (i = 0; i < bp->cp_nr_rings; i++) {
3718 struct bnxt_napi *bnapi = bp->bnapi[i];
3719 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3720 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3722 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3723 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3727 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3729 struct bnxt_napi *bnapi = bp->bnapi[n];
3730 struct bnxt_cp_ring_info *cpr;
3732 cpr = &bnapi->cp_ring;
3733 return cpr->cp_ring_struct.map_idx;
3736 static void bnxt_disable_int_sync(struct bnxt *bp)
3740 atomic_inc(&bp->intr_sem);
3742 bnxt_disable_int(bp);
3743 for (i = 0; i < bp->cp_nr_rings; i++) {
3744 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3746 synchronize_irq(bp->irq_tbl[map_idx].vector);
3750 static void bnxt_enable_int(struct bnxt *bp)
3754 atomic_set(&bp->intr_sem, 0);
3755 for (i = 0; i < bp->cp_nr_rings; i++) {
3756 struct bnxt_napi *bnapi = bp->bnapi[i];
3757 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3759 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3763 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3764 u16 cmpl_ring, u16 target_id)
3766 struct input *req = request;
3768 req->req_type = cpu_to_le16(req_type);
3769 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3770 req->target_id = cpu_to_le16(target_id);
3771 if (bnxt_kong_hwrm_message(bp, req))
3772 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3774 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3777 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3778 int timeout, bool silent)
3780 int i, intr_process, rc, tmo_count;
3781 struct input *req = msg;
3785 u16 cp_ring_id, len = 0;
3786 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3787 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3788 struct hwrm_short_input short_input = {0};
3789 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3790 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3791 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3792 u16 dst = BNXT_HWRM_CHNL_CHIMP;
3794 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3795 if (msg_len > bp->hwrm_max_ext_req_len ||
3796 !bp->hwrm_short_cmd_req_addr)
3800 if (bnxt_hwrm_kong_chnl(bp, req)) {
3801 dst = BNXT_HWRM_CHNL_KONG;
3802 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3803 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3804 resp = bp->hwrm_cmd_kong_resp_addr;
3805 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3808 memset(resp, 0, PAGE_SIZE);
3809 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3810 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3812 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3813 /* currently supports only one outstanding message */
3815 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3817 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3818 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3819 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3822 /* Set boundary for maximum extended request length for short
3823 * cmd format. If passed up from device use the max supported
3824 * internal req length.
3826 max_msg_len = bp->hwrm_max_ext_req_len;
3828 memcpy(short_cmd_req, req, msg_len);
3829 if (msg_len < max_msg_len)
3830 memset(short_cmd_req + msg_len, 0,
3831 max_msg_len - msg_len);
3833 short_input.req_type = req->req_type;
3834 short_input.signature =
3835 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3836 short_input.size = cpu_to_le16(msg_len);
3837 short_input.req_addr =
3838 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3840 data = (u32 *)&short_input;
3841 msg_len = sizeof(short_input);
3843 /* Sync memory write before updating doorbell */
3846 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3849 /* Write request msg to hwrm channel */
3850 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3852 for (i = msg_len; i < max_req_len; i += 4)
3853 writel(0, bp->bar0 + bar_offset + i);
3855 /* Ring channel doorbell */
3856 writel(1, bp->bar0 + doorbell_offset);
3859 timeout = DFLT_HWRM_CMD_TIMEOUT;
3860 /* convert timeout to usec */
3864 /* Short timeout for the first few iterations:
3865 * number of loops = number of loops for short timeout +
3866 * number of loops for standard timeout.
3868 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3869 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3870 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3871 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3874 u16 seq_id = bp->hwrm_intr_seq_id;
3876 /* Wait until hwrm response cmpl interrupt is processed */
3877 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3879 /* on first few passes, just barely sleep */
3880 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3881 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3882 HWRM_SHORT_MAX_TIMEOUT);
3884 usleep_range(HWRM_MIN_TIMEOUT,
3888 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3889 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3890 le16_to_cpu(req->req_type));
3893 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3895 valid = resp_addr + len - 1;
3899 /* Check if response len is updated */
3900 for (i = 0; i < tmo_count; i++) {
3901 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3905 /* on first few passes, just barely sleep */
3906 if (i < DFLT_HWRM_CMD_TIMEOUT)
3907 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3908 HWRM_SHORT_MAX_TIMEOUT);
3910 usleep_range(HWRM_MIN_TIMEOUT,
3914 if (i >= tmo_count) {
3915 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3916 HWRM_TOTAL_TIMEOUT(i),
3917 le16_to_cpu(req->req_type),
3918 le16_to_cpu(req->seq_id), len);
3922 /* Last byte of resp contains valid bit */
3923 valid = resp_addr + len - 1;
3924 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3925 /* make sure we read from updated DMA memory */
3932 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3933 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3934 HWRM_TOTAL_TIMEOUT(i),
3935 le16_to_cpu(req->req_type),
3936 le16_to_cpu(req->seq_id), len, *valid);
3941 /* Zero valid bit for compatibility. Valid bit in an older spec
3942 * may become a new field in a newer spec. We must make sure that
3943 * a new field not implemented by old spec will read zero.
3946 rc = le16_to_cpu(resp->error_code);
3948 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3949 le16_to_cpu(resp->req_type),
3950 le16_to_cpu(resp->seq_id), rc);
3954 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3956 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3959 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3962 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3965 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3969 mutex_lock(&bp->hwrm_cmd_lock);
3970 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3971 mutex_unlock(&bp->hwrm_cmd_lock);
3975 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3980 mutex_lock(&bp->hwrm_cmd_lock);
3981 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3982 mutex_unlock(&bp->hwrm_cmd_lock);
3986 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3989 struct hwrm_func_drv_rgtr_input req = {0};
3990 DECLARE_BITMAP(async_events_bmap, 256);
3991 u32 *events = (u32 *)async_events_bmap;
3994 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3997 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3999 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4000 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4001 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4003 if (bmap && bmap_size) {
4004 for (i = 0; i < bmap_size; i++) {
4005 if (test_bit(i, bmap))
4006 __set_bit(i, async_events_bmap);
4010 for (i = 0; i < 8; i++)
4011 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4013 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4016 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4018 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4019 struct hwrm_func_drv_rgtr_input req = {0};
4022 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4025 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4026 FUNC_DRV_RGTR_REQ_ENABLES_VER);
4028 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4029 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4030 req.ver_maj_8b = DRV_VER_MAJ;
4031 req.ver_min_8b = DRV_VER_MIN;
4032 req.ver_upd_8b = DRV_VER_UPD;
4033 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4034 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4035 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4041 memset(data, 0, sizeof(data));
4042 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4043 u16 cmd = bnxt_vf_req_snif[i];
4044 unsigned int bit, idx;
4048 data[idx] |= 1 << bit;
4051 for (i = 0; i < 8; i++)
4052 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4055 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4058 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4059 req.flags |= cpu_to_le32(
4060 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4062 mutex_lock(&bp->hwrm_cmd_lock);
4063 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4066 else if (resp->flags &
4067 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4068 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4069 mutex_unlock(&bp->hwrm_cmd_lock);
4073 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4075 struct hwrm_func_drv_unrgtr_input req = {0};
4077 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4078 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4081 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4084 struct hwrm_tunnel_dst_port_free_input req = {0};
4086 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4087 req.tunnel_type = tunnel_type;
4089 switch (tunnel_type) {
4090 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4091 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4093 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4094 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4100 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4102 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4107 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4111 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4112 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4114 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4116 req.tunnel_type = tunnel_type;
4117 req.tunnel_dst_port_val = port;
4119 mutex_lock(&bp->hwrm_cmd_lock);
4120 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4122 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4127 switch (tunnel_type) {
4128 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4129 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4131 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4132 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4139 mutex_unlock(&bp->hwrm_cmd_lock);
4143 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4145 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4146 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4148 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4149 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4151 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4152 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4153 req.mask = cpu_to_le32(vnic->rx_mask);
4154 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4157 #ifdef CONFIG_RFS_ACCEL
4158 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4159 struct bnxt_ntuple_filter *fltr)
4161 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4163 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4164 req.ntuple_filter_id = fltr->filter_id;
4165 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4168 #define BNXT_NTP_FLTR_FLAGS \
4169 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4170 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4171 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4172 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4173 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4174 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4175 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4176 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4177 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4178 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4179 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4180 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4181 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4182 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4184 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4185 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4187 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4188 struct bnxt_ntuple_filter *fltr)
4190 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
4191 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4192 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4193 struct flow_keys *keys = &fltr->fkeys;
4196 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4197 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4199 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4201 req.ethertype = htons(ETH_P_IP);
4202 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4203 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4204 req.ip_protocol = keys->basic.ip_proto;
4206 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4209 req.ethertype = htons(ETH_P_IPV6);
4211 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4212 *(struct in6_addr *)&req.src_ipaddr[0] =
4213 keys->addrs.v6addrs.src;
4214 *(struct in6_addr *)&req.dst_ipaddr[0] =
4215 keys->addrs.v6addrs.dst;
4216 for (i = 0; i < 4; i++) {
4217 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4218 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4221 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4222 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4223 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4224 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4226 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4227 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4229 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4232 req.src_port = keys->ports.src;
4233 req.src_port_mask = cpu_to_be16(0xffff);
4234 req.dst_port = keys->ports.dst;
4235 req.dst_port_mask = cpu_to_be16(0xffff);
4237 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4238 mutex_lock(&bp->hwrm_cmd_lock);
4239 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4241 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4242 fltr->filter_id = resp->ntuple_filter_id;
4244 mutex_unlock(&bp->hwrm_cmd_lock);
4249 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4253 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4254 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4256 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4257 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4258 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4260 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4261 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4263 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4264 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4265 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4266 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4267 req.l2_addr_mask[0] = 0xff;
4268 req.l2_addr_mask[1] = 0xff;
4269 req.l2_addr_mask[2] = 0xff;
4270 req.l2_addr_mask[3] = 0xff;
4271 req.l2_addr_mask[4] = 0xff;
4272 req.l2_addr_mask[5] = 0xff;
4274 mutex_lock(&bp->hwrm_cmd_lock);
4275 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4277 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4279 mutex_unlock(&bp->hwrm_cmd_lock);
4283 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4285 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4288 /* Any associated ntuple filters will also be cleared by firmware. */
4289 mutex_lock(&bp->hwrm_cmd_lock);
4290 for (i = 0; i < num_of_vnics; i++) {
4291 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4293 for (j = 0; j < vnic->uc_filter_count; j++) {
4294 struct hwrm_cfa_l2_filter_free_input req = {0};
4296 bnxt_hwrm_cmd_hdr_init(bp, &req,
4297 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4299 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4301 rc = _hwrm_send_message(bp, &req, sizeof(req),
4304 vnic->uc_filter_count = 0;
4306 mutex_unlock(&bp->hwrm_cmd_lock);
4311 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4313 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4314 struct hwrm_vnic_tpa_cfg_input req = {0};
4316 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4319 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4322 u16 mss = bp->dev->mtu - 40;
4323 u32 nsegs, n, segs = 0, flags;
4325 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4326 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4327 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4328 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4329 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4330 if (tpa_flags & BNXT_FLAG_GRO)
4331 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4333 req.flags = cpu_to_le32(flags);
4336 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4337 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4338 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4340 /* Number of segs are log2 units, and first packet is not
4341 * included as part of this units.
4343 if (mss <= BNXT_RX_PAGE_SIZE) {
4344 n = BNXT_RX_PAGE_SIZE / mss;
4345 nsegs = (MAX_SKB_FRAGS - 1) * n;
4347 n = mss / BNXT_RX_PAGE_SIZE;
4348 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4350 nsegs = (MAX_SKB_FRAGS - n) / n;
4353 segs = ilog2(nsegs);
4354 req.max_agg_segs = cpu_to_le16(segs);
4355 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4357 req.min_agg_len = cpu_to_le32(512);
4359 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4361 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4364 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4366 struct bnxt_ring_grp_info *grp_info;
4368 grp_info = &bp->grp_info[ring->grp_idx];
4369 return grp_info->cp_fw_ring_id;
4372 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4374 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4375 struct bnxt_napi *bnapi = rxr->bnapi;
4376 struct bnxt_cp_ring_info *cpr;
4378 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4379 return cpr->cp_ring_struct.fw_ring_id;
4381 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4385 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4387 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4388 struct bnxt_napi *bnapi = txr->bnapi;
4389 struct bnxt_cp_ring_info *cpr;
4391 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4392 return cpr->cp_ring_struct.fw_ring_id;
4394 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4398 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4400 u32 i, j, max_rings;
4401 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4402 struct hwrm_vnic_rss_cfg_input req = {0};
4404 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4405 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4408 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4410 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4411 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4412 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4413 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4414 max_rings = bp->rx_nr_rings - 1;
4416 max_rings = bp->rx_nr_rings;
4421 /* Fill the RSS indirection table with ring group ids */
4422 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4425 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4428 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4429 req.hash_key_tbl_addr =
4430 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4432 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4433 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4436 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4438 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4439 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4440 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4441 struct hwrm_vnic_rss_cfg_input req = {0};
4443 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4444 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4446 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4449 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4450 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4451 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4452 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4453 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4454 for (i = 0, k = 0; i < nr_ctxs; i++) {
4455 __le16 *ring_tbl = vnic->rss_table;
4458 req.ring_table_pair_index = i;
4459 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4460 for (j = 0; j < 64; j++) {
4463 ring_id = rxr->rx_ring_struct.fw_ring_id;
4464 *ring_tbl++ = cpu_to_le16(ring_id);
4465 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4466 *ring_tbl++ = cpu_to_le16(ring_id);
4469 if (k == max_rings) {
4471 rxr = &bp->rx_ring[0];
4474 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4481 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4483 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4484 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4486 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4487 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4488 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4489 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4491 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4492 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4493 /* thresholds not implemented in firmware yet */
4494 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4495 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4496 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4497 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4500 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4503 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4505 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4506 req.rss_cos_lb_ctx_id =
4507 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4509 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4510 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4513 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4517 for (i = 0; i < bp->nr_vnics; i++) {
4518 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4520 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4521 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4522 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4525 bp->rsscos_nr_ctxs = 0;
4528 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4531 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4532 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4533 bp->hwrm_cmd_resp_addr;
4535 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4538 mutex_lock(&bp->hwrm_cmd_lock);
4539 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4541 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4542 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4543 mutex_unlock(&bp->hwrm_cmd_lock);
4548 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4550 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4551 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4552 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4555 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4557 unsigned int ring = 0, grp_idx;
4558 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4559 struct hwrm_vnic_cfg_input req = {0};
4562 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4564 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4565 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4567 req.default_rx_ring_id =
4568 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4569 req.default_cmpl_ring_id =
4570 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4572 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4573 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4576 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4577 /* Only RSS support for now TBD: COS & LB */
4578 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4579 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4580 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4581 VNIC_CFG_REQ_ENABLES_MRU);
4582 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4584 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4585 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4586 VNIC_CFG_REQ_ENABLES_MRU);
4587 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4589 req.rss_rule = cpu_to_le16(0xffff);
4592 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4593 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4594 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4595 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4597 req.cos_rule = cpu_to_le16(0xffff);
4600 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4602 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4604 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4605 ring = bp->rx_nr_rings - 1;
4607 grp_idx = bp->rx_ring[ring].bnapi->index;
4608 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4609 req.lb_rule = cpu_to_le16(0xffff);
4611 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4614 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4615 #ifdef CONFIG_BNXT_SRIOV
4617 def_vlan = bp->vf.vlan;
4619 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4620 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4621 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4622 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4624 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4627 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4631 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4632 struct hwrm_vnic_free_input req = {0};
4634 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4636 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4638 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4641 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4646 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4650 for (i = 0; i < bp->nr_vnics; i++)
4651 bnxt_hwrm_vnic_free_one(bp, i);
4654 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4655 unsigned int start_rx_ring_idx,
4656 unsigned int nr_rings)
4659 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4660 struct hwrm_vnic_alloc_input req = {0};
4661 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4662 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4664 if (bp->flags & BNXT_FLAG_CHIP_P5)
4665 goto vnic_no_ring_grps;
4667 /* map ring groups to this vnic */
4668 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4669 grp_idx = bp->rx_ring[i].bnapi->index;
4670 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4671 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4675 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4679 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4680 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4682 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4684 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4686 mutex_lock(&bp->hwrm_cmd_lock);
4687 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4689 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4690 mutex_unlock(&bp->hwrm_cmd_lock);
4694 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4696 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4697 struct hwrm_vnic_qcaps_input req = {0};
4700 if (bp->hwrm_spec_code < 0x10600)
4703 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4704 mutex_lock(&bp->hwrm_cmd_lock);
4705 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4707 u32 flags = le32_to_cpu(resp->flags);
4709 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4710 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4711 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4713 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4714 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4716 mutex_unlock(&bp->hwrm_cmd_lock);
4720 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4725 if (bp->flags & BNXT_FLAG_CHIP_P5)
4728 mutex_lock(&bp->hwrm_cmd_lock);
4729 for (i = 0; i < bp->rx_nr_rings; i++) {
4730 struct hwrm_ring_grp_alloc_input req = {0};
4731 struct hwrm_ring_grp_alloc_output *resp =
4732 bp->hwrm_cmd_resp_addr;
4733 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4735 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4737 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4738 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4739 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4740 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4742 rc = _hwrm_send_message(bp, &req, sizeof(req),
4747 bp->grp_info[grp_idx].fw_grp_id =
4748 le32_to_cpu(resp->ring_group_id);
4750 mutex_unlock(&bp->hwrm_cmd_lock);
4754 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4758 struct hwrm_ring_grp_free_input req = {0};
4760 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4763 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4765 mutex_lock(&bp->hwrm_cmd_lock);
4766 for (i = 0; i < bp->cp_nr_rings; i++) {
4767 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4770 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4772 rc = _hwrm_send_message(bp, &req, sizeof(req),
4776 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4778 mutex_unlock(&bp->hwrm_cmd_lock);
4782 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4783 struct bnxt_ring_struct *ring,
4784 u32 ring_type, u32 map_index)
4786 int rc = 0, err = 0;
4787 struct hwrm_ring_alloc_input req = {0};
4788 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4789 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4790 struct bnxt_ring_grp_info *grp_info;
4793 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4796 if (rmem->nr_pages > 1) {
4797 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4798 /* Page size is in log2 units */
4799 req.page_size = BNXT_PAGE_SHIFT;
4800 req.page_tbl_depth = 1;
4802 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
4805 /* Association of ring index with doorbell index and MSIX number */
4806 req.logical_id = cpu_to_le16(map_index);
4808 switch (ring_type) {
4809 case HWRM_RING_ALLOC_TX: {
4810 struct bnxt_tx_ring_info *txr;
4812 txr = container_of(ring, struct bnxt_tx_ring_info,
4814 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4815 /* Association of transmit ring with completion ring */
4816 grp_info = &bp->grp_info[ring->grp_idx];
4817 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4818 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4819 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4820 req.queue_id = cpu_to_le16(ring->queue_id);
4823 case HWRM_RING_ALLOC_RX:
4824 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4825 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4826 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4829 /* Association of rx ring with stats context */
4830 grp_info = &bp->grp_info[ring->grp_idx];
4831 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4832 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4833 req.enables |= cpu_to_le32(
4834 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4835 if (NET_IP_ALIGN == 2)
4836 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4837 req.flags = cpu_to_le16(flags);
4840 case HWRM_RING_ALLOC_AGG:
4841 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4842 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4843 /* Association of agg ring with rx ring */
4844 grp_info = &bp->grp_info[ring->grp_idx];
4845 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4846 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4847 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4848 req.enables |= cpu_to_le32(
4849 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4850 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4852 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4854 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4856 case HWRM_RING_ALLOC_CMPL:
4857 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4858 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4859 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4860 /* Association of cp ring with nq */
4861 grp_info = &bp->grp_info[map_index];
4862 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4863 req.cq_handle = cpu_to_le64(ring->handle);
4864 req.enables |= cpu_to_le32(
4865 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4866 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4867 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4870 case HWRM_RING_ALLOC_NQ:
4871 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4872 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4873 if (bp->flags & BNXT_FLAG_USING_MSIX)
4874 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4877 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4882 mutex_lock(&bp->hwrm_cmd_lock);
4883 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4884 err = le16_to_cpu(resp->error_code);
4885 ring_id = le16_to_cpu(resp->ring_id);
4886 mutex_unlock(&bp->hwrm_cmd_lock);
4889 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4890 ring_type, rc, err);
4893 ring->fw_ring_id = ring_id;
4897 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4902 struct hwrm_func_cfg_input req = {0};
4904 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4905 req.fid = cpu_to_le16(0xffff);
4906 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4907 req.async_event_cr = cpu_to_le16(idx);
4908 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4910 struct hwrm_func_vf_cfg_input req = {0};
4912 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4914 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4915 req.async_event_cr = cpu_to_le16(idx);
4916 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4921 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4922 u32 map_idx, u32 xid)
4924 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4926 db->doorbell = bp->bar1 + 0x10000;
4928 db->doorbell = bp->bar1 + 0x4000;
4929 switch (ring_type) {
4930 case HWRM_RING_ALLOC_TX:
4931 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4933 case HWRM_RING_ALLOC_RX:
4934 case HWRM_RING_ALLOC_AGG:
4935 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4937 case HWRM_RING_ALLOC_CMPL:
4938 db->db_key64 = DBR_PATH_L2;
4940 case HWRM_RING_ALLOC_NQ:
4941 db->db_key64 = DBR_PATH_L2;
4944 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4946 db->doorbell = bp->bar1 + map_idx * 0x80;
4947 switch (ring_type) {
4948 case HWRM_RING_ALLOC_TX:
4949 db->db_key32 = DB_KEY_TX;
4951 case HWRM_RING_ALLOC_RX:
4952 case HWRM_RING_ALLOC_AGG:
4953 db->db_key32 = DB_KEY_RX;
4955 case HWRM_RING_ALLOC_CMPL:
4956 db->db_key32 = DB_KEY_CP;
4962 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4967 if (bp->flags & BNXT_FLAG_CHIP_P5)
4968 type = HWRM_RING_ALLOC_NQ;
4970 type = HWRM_RING_ALLOC_CMPL;
4971 for (i = 0; i < bp->cp_nr_rings; i++) {
4972 struct bnxt_napi *bnapi = bp->bnapi[i];
4973 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4974 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4975 u32 map_idx = ring->map_idx;
4977 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
4980 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
4981 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4982 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4985 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4987 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4991 type = HWRM_RING_ALLOC_TX;
4992 for (i = 0; i < bp->tx_nr_rings; i++) {
4993 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4994 struct bnxt_ring_struct *ring;
4997 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4998 struct bnxt_napi *bnapi = txr->bnapi;
4999 struct bnxt_cp_ring_info *cpr, *cpr2;
5000 u32 type2 = HWRM_RING_ALLOC_CMPL;
5002 cpr = &bnapi->cp_ring;
5003 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5004 ring = &cpr2->cp_ring_struct;
5005 ring->handle = BNXT_TX_HDL;
5006 map_idx = bnapi->index;
5007 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5010 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5012 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5014 ring = &txr->tx_ring_struct;
5016 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5019 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5022 type = HWRM_RING_ALLOC_RX;
5023 for (i = 0; i < bp->rx_nr_rings; i++) {
5024 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5025 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5026 struct bnxt_napi *bnapi = rxr->bnapi;
5027 u32 map_idx = bnapi->index;
5029 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5032 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5033 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5034 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5035 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5036 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5037 u32 type2 = HWRM_RING_ALLOC_CMPL;
5038 struct bnxt_cp_ring_info *cpr2;
5040 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5041 ring = &cpr2->cp_ring_struct;
5042 ring->handle = BNXT_RX_HDL;
5043 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5046 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5048 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5052 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5053 type = HWRM_RING_ALLOC_AGG;
5054 for (i = 0; i < bp->rx_nr_rings; i++) {
5055 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5056 struct bnxt_ring_struct *ring =
5057 &rxr->rx_agg_ring_struct;
5058 u32 grp_idx = ring->grp_idx;
5059 u32 map_idx = grp_idx + bp->rx_nr_rings;
5061 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5065 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5067 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5068 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5075 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5076 struct bnxt_ring_struct *ring,
5077 u32 ring_type, int cmpl_ring_id)
5080 struct hwrm_ring_free_input req = {0};
5081 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5084 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5085 req.ring_type = ring_type;
5086 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5088 mutex_lock(&bp->hwrm_cmd_lock);
5089 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5090 error_code = le16_to_cpu(resp->error_code);
5091 mutex_unlock(&bp->hwrm_cmd_lock);
5093 if (rc || error_code) {
5094 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5095 ring_type, rc, error_code);
5101 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5109 for (i = 0; i < bp->tx_nr_rings; i++) {
5110 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5111 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5114 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5115 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5116 hwrm_ring_free_send_msg(bp, ring,
5117 RING_FREE_REQ_RING_TYPE_TX,
5118 close_path ? cmpl_ring_id :
5119 INVALID_HW_RING_ID);
5120 ring->fw_ring_id = INVALID_HW_RING_ID;
5124 for (i = 0; i < bp->rx_nr_rings; i++) {
5125 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5126 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5127 u32 grp_idx = rxr->bnapi->index;
5130 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5131 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5132 hwrm_ring_free_send_msg(bp, ring,
5133 RING_FREE_REQ_RING_TYPE_RX,
5134 close_path ? cmpl_ring_id :
5135 INVALID_HW_RING_ID);
5136 ring->fw_ring_id = INVALID_HW_RING_ID;
5137 bp->grp_info[grp_idx].rx_fw_ring_id =
5142 if (bp->flags & BNXT_FLAG_CHIP_P5)
5143 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5145 type = RING_FREE_REQ_RING_TYPE_RX;
5146 for (i = 0; i < bp->rx_nr_rings; i++) {
5147 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5148 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5149 u32 grp_idx = rxr->bnapi->index;
5152 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5153 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5154 hwrm_ring_free_send_msg(bp, ring, type,
5155 close_path ? cmpl_ring_id :
5156 INVALID_HW_RING_ID);
5157 ring->fw_ring_id = INVALID_HW_RING_ID;
5158 bp->grp_info[grp_idx].agg_fw_ring_id =
5163 /* The completion rings are about to be freed. After that the
5164 * IRQ doorbell will not work anymore. So we need to disable
5167 bnxt_disable_int_sync(bp);
5169 if (bp->flags & BNXT_FLAG_CHIP_P5)
5170 type = RING_FREE_REQ_RING_TYPE_NQ;
5172 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5173 for (i = 0; i < bp->cp_nr_rings; i++) {
5174 struct bnxt_napi *bnapi = bp->bnapi[i];
5175 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5176 struct bnxt_ring_struct *ring;
5179 for (j = 0; j < 2; j++) {
5180 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5183 ring = &cpr2->cp_ring_struct;
5184 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5186 hwrm_ring_free_send_msg(bp, ring,
5187 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5188 INVALID_HW_RING_ID);
5189 ring->fw_ring_id = INVALID_HW_RING_ID;
5192 ring = &cpr->cp_ring_struct;
5193 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5194 hwrm_ring_free_send_msg(bp, ring, type,
5195 INVALID_HW_RING_ID);
5196 ring->fw_ring_id = INVALID_HW_RING_ID;
5197 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5202 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5205 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5207 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5208 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5209 struct hwrm_func_qcfg_input req = {0};
5212 if (bp->hwrm_spec_code < 0x10601)
5215 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5216 req.fid = cpu_to_le16(0xffff);
5217 mutex_lock(&bp->hwrm_cmd_lock);
5218 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5220 mutex_unlock(&bp->hwrm_cmd_lock);
5224 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5225 if (BNXT_NEW_RM(bp)) {
5228 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5229 hw_resc->resv_hw_ring_grps =
5230 le32_to_cpu(resp->alloc_hw_ring_grps);
5231 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5232 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5233 stats = le16_to_cpu(resp->alloc_stat_ctx);
5234 hw_resc->resv_irqs = cp;
5235 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5236 int rx = hw_resc->resv_rx_rings;
5237 int tx = hw_resc->resv_tx_rings;
5239 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5241 if (cp < (rx + tx)) {
5242 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5243 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5245 hw_resc->resv_rx_rings = rx;
5246 hw_resc->resv_tx_rings = tx;
5248 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5249 hw_resc->resv_hw_ring_grps = rx;
5251 hw_resc->resv_cp_rings = cp;
5252 hw_resc->resv_stat_ctxs = stats;
5254 mutex_unlock(&bp->hwrm_cmd_lock);
5258 /* Caller must hold bp->hwrm_cmd_lock */
5259 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5261 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5262 struct hwrm_func_qcfg_input req = {0};
5265 if (bp->hwrm_spec_code < 0x10601)
5268 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5269 req.fid = cpu_to_le16(fid);
5270 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5272 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5277 static bool bnxt_rfs_supported(struct bnxt *bp);
5280 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5281 int tx_rings, int rx_rings, int ring_grps,
5282 int cp_rings, int stats, int vnics)
5286 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5287 req->fid = cpu_to_le16(0xffff);
5288 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5289 req->num_tx_rings = cpu_to_le16(tx_rings);
5290 if (BNXT_NEW_RM(bp)) {
5291 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5292 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5293 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5294 enables |= tx_rings + ring_grps ?
5295 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5296 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5297 enables |= rx_rings ?
5298 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5300 enables |= cp_rings ?
5301 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5302 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5303 enables |= ring_grps ?
5304 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5305 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5307 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5309 req->num_rx_rings = cpu_to_le16(rx_rings);
5310 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5311 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5312 req->num_msix = cpu_to_le16(cp_rings);
5313 req->num_rsscos_ctxs =
5314 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5316 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5317 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5318 req->num_rsscos_ctxs = cpu_to_le16(1);
5319 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5320 bnxt_rfs_supported(bp))
5321 req->num_rsscos_ctxs =
5322 cpu_to_le16(ring_grps + 1);
5324 req->num_stat_ctxs = cpu_to_le16(stats);
5325 req->num_vnics = cpu_to_le16(vnics);
5327 req->enables = cpu_to_le32(enables);
5331 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5332 struct hwrm_func_vf_cfg_input *req, int tx_rings,
5333 int rx_rings, int ring_grps, int cp_rings,
5334 int stats, int vnics)
5338 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5339 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5340 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5341 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5342 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5343 enables |= tx_rings + ring_grps ?
5344 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5345 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5347 enables |= cp_rings ?
5348 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
5349 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5350 enables |= ring_grps ?
5351 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5353 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5354 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5356 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5357 req->num_tx_rings = cpu_to_le16(tx_rings);
5358 req->num_rx_rings = cpu_to_le16(rx_rings);
5359 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5360 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5361 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5363 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5364 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5365 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5367 req->num_stat_ctxs = cpu_to_le16(stats);
5368 req->num_vnics = cpu_to_le16(vnics);
5370 req->enables = cpu_to_le32(enables);
5374 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5375 int ring_grps, int cp_rings, int stats, int vnics)
5377 struct hwrm_func_cfg_input req = {0};
5380 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5381 cp_rings, stats, vnics);
5385 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5389 if (bp->hwrm_spec_code < 0x10601)
5390 bp->hw_resc.resv_tx_rings = tx_rings;
5392 rc = bnxt_hwrm_get_rings(bp);
5397 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5398 int ring_grps, int cp_rings, int stats, int vnics)
5400 struct hwrm_func_vf_cfg_input req = {0};
5403 if (!BNXT_NEW_RM(bp)) {
5404 bp->hw_resc.resv_tx_rings = tx_rings;
5408 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5409 cp_rings, stats, vnics);
5410 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5414 rc = bnxt_hwrm_get_rings(bp);
5418 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5419 int cp, int stat, int vnic)
5422 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5425 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5429 int bnxt_nq_rings_in_use(struct bnxt *bp)
5431 int cp = bp->cp_nr_rings;
5432 int ulp_msix, ulp_base;
5434 ulp_msix = bnxt_get_ulp_msix_num(bp);
5436 ulp_base = bnxt_get_ulp_msix_base(bp);
5438 if ((ulp_base + ulp_msix) > cp)
5439 cp = ulp_base + ulp_msix;
5444 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5448 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5449 return bnxt_nq_rings_in_use(bp);
5451 cp = bp->tx_nr_rings + bp->rx_nr_rings;
5455 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5457 return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp);
5460 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5462 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5463 int cp = bnxt_cp_rings_in_use(bp);
5464 int nq = bnxt_nq_rings_in_use(bp);
5465 int rx = bp->rx_nr_rings, stat;
5466 int vnic = 1, grp = rx;
5468 if (bp->hwrm_spec_code < 0x10601)
5471 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5474 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5476 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5478 stat = bnxt_get_func_stat_ctxs(bp);
5479 if (BNXT_NEW_RM(bp) &&
5480 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5481 hw_resc->resv_irqs < nq || hw_resc->resv_vnics != vnic ||
5482 hw_resc->resv_stat_ctxs != stat ||
5483 (hw_resc->resv_hw_ring_grps != grp &&
5484 !(bp->flags & BNXT_FLAG_CHIP_P5))))
5489 static int __bnxt_reserve_rings(struct bnxt *bp)
5491 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5492 int cp = bnxt_nq_rings_in_use(bp);
5493 int tx = bp->tx_nr_rings;
5494 int rx = bp->rx_nr_rings;
5495 int grp, rx_rings, rc;
5499 if (!bnxt_need_reserve_rings(bp))
5502 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5504 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5506 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5508 grp = bp->rx_nr_rings;
5509 stat = bnxt_get_func_stat_ctxs(bp);
5511 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5515 tx = hw_resc->resv_tx_rings;
5516 if (BNXT_NEW_RM(bp)) {
5517 rx = hw_resc->resv_rx_rings;
5518 cp = hw_resc->resv_irqs;
5519 grp = hw_resc->resv_hw_ring_grps;
5520 vnic = hw_resc->resv_vnics;
5521 stat = hw_resc->resv_stat_ctxs;
5525 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5529 if (netif_running(bp->dev))
5532 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5533 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5534 bp->dev->hw_features &= ~NETIF_F_LRO;
5535 bp->dev->features &= ~NETIF_F_LRO;
5536 bnxt_set_ring_params(bp);
5539 rx_rings = min_t(int, rx_rings, grp);
5540 cp = min_t(int, cp, bp->cp_nr_rings);
5541 if (stat > bnxt_get_ulp_stat_ctxs(bp))
5542 stat -= bnxt_get_ulp_stat_ctxs(bp);
5543 cp = min_t(int, cp, stat);
5544 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5545 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5547 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5548 bp->tx_nr_rings = tx;
5549 bp->rx_nr_rings = rx_rings;
5550 bp->cp_nr_rings = cp;
5552 if (!tx || !rx || !cp || !grp || !vnic || !stat)
5558 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5559 int ring_grps, int cp_rings, int stats,
5562 struct hwrm_func_vf_cfg_input req = {0};
5566 if (!BNXT_NEW_RM(bp))
5569 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5570 cp_rings, stats, vnics);
5571 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5572 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5573 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5574 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5575 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5576 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5577 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5578 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5580 req.flags = cpu_to_le32(flags);
5581 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5587 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5588 int ring_grps, int cp_rings, int stats,
5591 struct hwrm_func_cfg_input req = {0};
5595 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5596 cp_rings, stats, vnics);
5597 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5598 if (BNXT_NEW_RM(bp)) {
5599 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5600 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5601 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5602 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5603 if (bp->flags & BNXT_FLAG_CHIP_P5)
5604 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5606 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5609 req.flags = cpu_to_le32(flags);
5610 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5616 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5617 int ring_grps, int cp_rings, int stats,
5620 if (bp->hwrm_spec_code < 0x10801)
5624 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5625 ring_grps, cp_rings, stats,
5628 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5629 cp_rings, stats, vnics);
5632 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5634 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5635 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5636 struct hwrm_ring_aggint_qcaps_input req = {0};
5639 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5640 coal_cap->num_cmpl_dma_aggr_max = 63;
5641 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5642 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5643 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5644 coal_cap->int_lat_tmr_min_max = 65535;
5645 coal_cap->int_lat_tmr_max_max = 65535;
5646 coal_cap->num_cmpl_aggr_int_max = 65535;
5647 coal_cap->timer_units = 80;
5649 if (bp->hwrm_spec_code < 0x10902)
5652 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5653 mutex_lock(&bp->hwrm_cmd_lock);
5654 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5656 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5657 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5658 coal_cap->num_cmpl_dma_aggr_max =
5659 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5660 coal_cap->num_cmpl_dma_aggr_during_int_max =
5661 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5662 coal_cap->cmpl_aggr_dma_tmr_max =
5663 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5664 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5665 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5666 coal_cap->int_lat_tmr_min_max =
5667 le16_to_cpu(resp->int_lat_tmr_min_max);
5668 coal_cap->int_lat_tmr_max_max =
5669 le16_to_cpu(resp->int_lat_tmr_max_max);
5670 coal_cap->num_cmpl_aggr_int_max =
5671 le16_to_cpu(resp->num_cmpl_aggr_int_max);
5672 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5674 mutex_unlock(&bp->hwrm_cmd_lock);
5677 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5679 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5681 return usec * 1000 / coal_cap->timer_units;
5684 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5685 struct bnxt_coal *hw_coal,
5686 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5688 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5689 u32 cmpl_params = coal_cap->cmpl_params;
5690 u16 val, tmr, max, flags = 0;
5692 max = hw_coal->bufs_per_record * 128;
5693 if (hw_coal->budget)
5694 max = hw_coal->bufs_per_record * hw_coal->budget;
5695 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5697 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5698 req->num_cmpl_aggr_int = cpu_to_le16(val);
5700 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5701 req->num_cmpl_dma_aggr = cpu_to_le16(val);
5703 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5704 coal_cap->num_cmpl_dma_aggr_during_int_max);
5705 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5707 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5708 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5709 req->int_lat_tmr_max = cpu_to_le16(tmr);
5711 /* min timer set to 1/2 of interrupt timer */
5712 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5714 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5715 req->int_lat_tmr_min = cpu_to_le16(val);
5716 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5719 /* buf timer set to 1/4 of interrupt timer */
5720 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5721 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5724 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5725 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5726 val = clamp_t(u16, tmr, 1,
5727 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5728 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5730 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5733 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5734 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5735 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5736 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5737 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5738 req->flags = cpu_to_le16(flags);
5739 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5742 /* Caller holds bp->hwrm_cmd_lock */
5743 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5744 struct bnxt_coal *hw_coal)
5746 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5747 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5748 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5749 u32 nq_params = coal_cap->nq_params;
5752 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5755 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5757 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5759 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5761 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5762 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5763 req.int_lat_tmr_min = cpu_to_le16(tmr);
5764 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5765 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5768 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5770 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5771 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5772 struct bnxt_coal coal;
5774 /* Tick values in micro seconds.
5775 * 1 coal_buf x bufs_per_record = 1 completion record.
5777 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5779 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5780 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5782 if (!bnapi->rx_ring)
5785 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5786 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5788 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5790 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5792 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5796 int bnxt_hwrm_set_coal(struct bnxt *bp)
5799 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5802 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5803 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5804 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5805 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5807 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5808 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5810 mutex_lock(&bp->hwrm_cmd_lock);
5811 for (i = 0; i < bp->cp_nr_rings; i++) {
5812 struct bnxt_napi *bnapi = bp->bnapi[i];
5813 struct bnxt_coal *hw_coal;
5817 if (!bnapi->rx_ring) {
5818 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5821 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5823 req->ring_id = cpu_to_le16(ring_id);
5825 rc = _hwrm_send_message(bp, req, sizeof(*req),
5830 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5833 if (bnapi->rx_ring && bnapi->tx_ring) {
5835 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5836 req->ring_id = cpu_to_le16(ring_id);
5837 rc = _hwrm_send_message(bp, req, sizeof(*req),
5843 hw_coal = &bp->rx_coal;
5845 hw_coal = &bp->tx_coal;
5846 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5848 mutex_unlock(&bp->hwrm_cmd_lock);
5852 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5855 struct hwrm_stat_ctx_free_input req = {0};
5860 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5863 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5865 mutex_lock(&bp->hwrm_cmd_lock);
5866 for (i = 0; i < bp->cp_nr_rings; i++) {
5867 struct bnxt_napi *bnapi = bp->bnapi[i];
5868 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5870 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5871 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5873 rc = _hwrm_send_message(bp, &req, sizeof(req),
5878 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5881 mutex_unlock(&bp->hwrm_cmd_lock);
5885 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5888 struct hwrm_stat_ctx_alloc_input req = {0};
5889 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5891 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5894 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5896 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5898 mutex_lock(&bp->hwrm_cmd_lock);
5899 for (i = 0; i < bp->cp_nr_rings; i++) {
5900 struct bnxt_napi *bnapi = bp->bnapi[i];
5901 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5903 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5905 rc = _hwrm_send_message(bp, &req, sizeof(req),
5910 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5912 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5914 mutex_unlock(&bp->hwrm_cmd_lock);
5918 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5920 struct hwrm_func_qcfg_input req = {0};
5921 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5925 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5926 req.fid = cpu_to_le16(0xffff);
5927 mutex_lock(&bp->hwrm_cmd_lock);
5928 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5930 goto func_qcfg_exit;
5932 #ifdef CONFIG_BNXT_SRIOV
5934 struct bnxt_vf_info *vf = &bp->vf;
5936 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5939 flags = le16_to_cpu(resp->flags);
5940 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5941 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5942 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5943 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5944 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5946 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5947 bp->flags |= BNXT_FLAG_MULTI_HOST;
5949 switch (resp->port_partition_type) {
5950 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5951 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5952 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5953 bp->port_partition_type = resp->port_partition_type;
5956 if (bp->hwrm_spec_code < 0x10707 ||
5957 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5958 bp->br_mode = BRIDGE_MODE_VEB;
5959 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5960 bp->br_mode = BRIDGE_MODE_VEPA;
5962 bp->br_mode = BRIDGE_MODE_UNDEF;
5964 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5966 bp->max_mtu = BNXT_MAX_MTU;
5969 mutex_unlock(&bp->hwrm_cmd_lock);
5973 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5975 struct hwrm_func_backing_store_qcaps_input req = {0};
5976 struct hwrm_func_backing_store_qcaps_output *resp =
5977 bp->hwrm_cmd_resp_addr;
5980 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
5983 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
5984 mutex_lock(&bp->hwrm_cmd_lock);
5985 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5987 struct bnxt_ctx_pg_info *ctx_pg;
5988 struct bnxt_ctx_mem_info *ctx;
5991 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
5996 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6002 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6003 ctx->tqm_mem[i] = ctx_pg;
6006 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6007 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6008 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6009 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6010 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6011 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6012 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6013 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6014 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6015 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6016 ctx->vnic_max_vnic_entries =
6017 le16_to_cpu(resp->vnic_max_vnic_entries);
6018 ctx->vnic_max_ring_table_entries =
6019 le16_to_cpu(resp->vnic_max_ring_table_entries);
6020 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6021 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6022 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6023 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6024 ctx->tqm_min_entries_per_ring =
6025 le32_to_cpu(resp->tqm_min_entries_per_ring);
6026 ctx->tqm_max_entries_per_ring =
6027 le32_to_cpu(resp->tqm_max_entries_per_ring);
6028 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6029 if (!ctx->tqm_entries_multiple)
6030 ctx->tqm_entries_multiple = 1;
6031 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6032 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6033 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6034 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6039 mutex_unlock(&bp->hwrm_cmd_lock);
6043 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6048 if (BNXT_PAGE_SHIFT == 13)
6050 else if (BNXT_PAGE_SIZE == 16)
6054 if (rmem->depth >= 1) {
6055 if (rmem->depth == 2)
6059 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6061 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6065 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6066 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6067 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6068 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6069 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6070 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6072 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6074 struct hwrm_func_backing_store_cfg_input req = {0};
6075 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6076 struct bnxt_ctx_pg_info *ctx_pg;
6077 __le32 *num_entries;
6086 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6087 req.enables = cpu_to_le32(enables);
6089 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6090 ctx_pg = &ctx->qp_mem;
6091 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6092 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6093 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6094 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6095 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6096 &req.qpc_pg_size_qpc_lvl,
6099 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6100 ctx_pg = &ctx->srq_mem;
6101 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6102 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6103 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6104 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6105 &req.srq_pg_size_srq_lvl,
6108 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6109 ctx_pg = &ctx->cq_mem;
6110 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6111 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6112 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6113 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6116 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6117 ctx_pg = &ctx->vnic_mem;
6118 req.vnic_num_vnic_entries =
6119 cpu_to_le16(ctx->vnic_max_vnic_entries);
6120 req.vnic_num_ring_table_entries =
6121 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6122 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6123 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6124 &req.vnic_pg_size_vnic_lvl,
6125 &req.vnic_page_dir);
6127 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6128 ctx_pg = &ctx->stat_mem;
6129 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6130 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6131 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6132 &req.stat_pg_size_stat_lvl,
6133 &req.stat_page_dir);
6135 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6136 ctx_pg = &ctx->mrav_mem;
6137 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6138 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6139 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6140 &req.mrav_pg_size_mrav_lvl,
6141 &req.mrav_page_dir);
6143 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6144 ctx_pg = &ctx->tim_mem;
6145 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6146 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6147 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6148 &req.tim_pg_size_tim_lvl,
6151 for (i = 0, num_entries = &req.tqm_sp_num_entries,
6152 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6153 pg_dir = &req.tqm_sp_page_dir,
6154 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6155 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6156 if (!(enables & ena))
6159 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6160 ctx_pg = ctx->tqm_mem[i];
6161 *num_entries = cpu_to_le32(ctx_pg->entries);
6162 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6164 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6170 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6171 struct bnxt_ctx_pg_info *ctx_pg)
6173 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6175 rmem->page_size = BNXT_PAGE_SIZE;
6176 rmem->pg_arr = ctx_pg->ctx_pg_arr;
6177 rmem->dma_arr = ctx_pg->ctx_dma_arr;
6178 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6179 if (rmem->depth >= 1)
6180 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6181 return bnxt_alloc_ring(bp, rmem);
6184 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6185 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6188 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6194 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6195 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6196 ctx_pg->nr_pages = 0;
6199 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6203 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6205 if (!ctx_pg->ctx_pg_tbl)
6207 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6208 rmem->nr_pages = nr_tbls;
6209 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6212 for (i = 0; i < nr_tbls; i++) {
6213 struct bnxt_ctx_pg_info *pg_tbl;
6215 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6218 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6219 rmem = &pg_tbl->ring_mem;
6220 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6221 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6223 rmem->nr_pages = MAX_CTX_PAGES;
6224 if (i == (nr_tbls - 1))
6225 rmem->nr_pages = ctx_pg->nr_pages %
6227 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6232 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6233 if (rmem->nr_pages > 1 || depth)
6235 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6240 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6241 struct bnxt_ctx_pg_info *ctx_pg)
6243 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6245 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6246 ctx_pg->ctx_pg_tbl) {
6247 int i, nr_tbls = rmem->nr_pages;
6249 for (i = 0; i < nr_tbls; i++) {
6250 struct bnxt_ctx_pg_info *pg_tbl;
6251 struct bnxt_ring_mem_info *rmem2;
6253 pg_tbl = ctx_pg->ctx_pg_tbl[i];
6256 rmem2 = &pg_tbl->ring_mem;
6257 bnxt_free_ring(bp, rmem2);
6258 ctx_pg->ctx_pg_arr[i] = NULL;
6260 ctx_pg->ctx_pg_tbl[i] = NULL;
6262 kfree(ctx_pg->ctx_pg_tbl);
6263 ctx_pg->ctx_pg_tbl = NULL;
6265 bnxt_free_ring(bp, rmem);
6266 ctx_pg->nr_pages = 0;
6269 static void bnxt_free_ctx_mem(struct bnxt *bp)
6271 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6277 if (ctx->tqm_mem[0]) {
6278 for (i = 0; i < bp->max_q + 1; i++)
6279 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6280 kfree(ctx->tqm_mem[0]);
6281 ctx->tqm_mem[0] = NULL;
6284 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6285 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6286 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6287 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6288 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6289 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6290 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6291 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6294 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6296 struct bnxt_ctx_pg_info *ctx_pg;
6297 struct bnxt_ctx_mem_info *ctx;
6298 u32 mem_size, ena, entries;
6304 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6306 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6311 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6314 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
6320 ctx_pg = &ctx->qp_mem;
6321 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6323 mem_size = ctx->qp_entry_size * ctx_pg->entries;
6324 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6328 ctx_pg = &ctx->srq_mem;
6329 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6330 mem_size = ctx->srq_entry_size * ctx_pg->entries;
6331 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6335 ctx_pg = &ctx->cq_mem;
6336 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6337 mem_size = ctx->cq_entry_size * ctx_pg->entries;
6338 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6342 ctx_pg = &ctx->vnic_mem;
6343 ctx_pg->entries = ctx->vnic_max_vnic_entries +
6344 ctx->vnic_max_ring_table_entries;
6345 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6346 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6350 ctx_pg = &ctx->stat_mem;
6351 ctx_pg->entries = ctx->stat_max_entries;
6352 mem_size = ctx->stat_entry_size * ctx_pg->entries;
6353 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6358 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6361 ctx_pg = &ctx->mrav_mem;
6362 ctx_pg->entries = extra_qps * 4;
6363 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6364 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6367 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6369 ctx_pg = &ctx->tim_mem;
6370 ctx_pg->entries = ctx->qp_mem.entries;
6371 mem_size = ctx->tim_entry_size * ctx_pg->entries;
6372 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6375 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6378 entries = ctx->qp_max_l2_entries + extra_qps;
6379 entries = roundup(entries, ctx->tqm_entries_multiple);
6380 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6381 ctx->tqm_max_entries_per_ring);
6382 for (i = 0; i < bp->max_q + 1; i++) {
6383 ctx_pg = ctx->tqm_mem[i];
6384 ctx_pg->entries = entries;
6385 mem_size = ctx->tqm_entry_size * entries;
6386 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6389 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6391 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6392 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6394 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6397 ctx->flags |= BNXT_CTX_FLAG_INITED;
6402 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6404 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6405 struct hwrm_func_resource_qcaps_input req = {0};
6406 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6409 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6410 req.fid = cpu_to_le16(0xffff);
6412 mutex_lock(&bp->hwrm_cmd_lock);
6413 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6417 goto hwrm_func_resc_qcaps_exit;
6420 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6422 goto hwrm_func_resc_qcaps_exit;
6424 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6425 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6426 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6427 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6428 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6429 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6430 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6431 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6432 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6433 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6434 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6435 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6436 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6437 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6438 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6439 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6441 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6442 u16 max_msix = le16_to_cpu(resp->max_msix);
6444 hw_resc->max_nqs = max_msix;
6445 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6449 struct bnxt_pf_info *pf = &bp->pf;
6451 pf->vf_resv_strategy =
6452 le16_to_cpu(resp->vf_reservation_strategy);
6453 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6454 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6456 hwrm_func_resc_qcaps_exit:
6457 mutex_unlock(&bp->hwrm_cmd_lock);
6461 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6464 struct hwrm_func_qcaps_input req = {0};
6465 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6466 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6469 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6470 req.fid = cpu_to_le16(0xffff);
6472 mutex_lock(&bp->hwrm_cmd_lock);
6473 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6475 goto hwrm_func_qcaps_exit;
6477 flags = le32_to_cpu(resp->flags);
6478 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6479 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6480 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6481 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6483 bp->tx_push_thresh = 0;
6484 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6485 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6487 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6488 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6489 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6490 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6491 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6492 if (!hw_resc->max_hw_ring_grps)
6493 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6494 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6495 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6496 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6499 struct bnxt_pf_info *pf = &bp->pf;
6501 pf->fw_fid = le16_to_cpu(resp->fid);
6502 pf->port_id = le16_to_cpu(resp->port_id);
6503 bp->dev->dev_port = pf->port_id;
6504 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6505 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6506 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6507 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6508 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6509 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6510 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6511 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6512 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6513 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6514 bp->flags |= BNXT_FLAG_WOL_CAP;
6516 #ifdef CONFIG_BNXT_SRIOV
6517 struct bnxt_vf_info *vf = &bp->vf;
6519 vf->fw_fid = le16_to_cpu(resp->fid);
6520 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6524 hwrm_func_qcaps_exit:
6525 mutex_unlock(&bp->hwrm_cmd_lock);
6529 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6531 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6535 rc = __bnxt_hwrm_func_qcaps(bp);
6538 rc = bnxt_hwrm_queue_qportcfg(bp);
6540 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6543 if (bp->hwrm_spec_code >= 0x10803) {
6544 rc = bnxt_alloc_ctx_mem(bp);
6547 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6549 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6554 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6556 struct hwrm_func_reset_input req = {0};
6558 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6561 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6564 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6567 struct hwrm_queue_qportcfg_input req = {0};
6568 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6572 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6574 mutex_lock(&bp->hwrm_cmd_lock);
6575 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6579 if (!resp->max_configurable_queues) {
6583 bp->max_tc = resp->max_configurable_queues;
6584 bp->max_lltc = resp->max_configurable_lossless_queues;
6585 if (bp->max_tc > BNXT_MAX_QUEUE)
6586 bp->max_tc = BNXT_MAX_QUEUE;
6588 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6589 qptr = &resp->queue_id0;
6590 for (i = 0, j = 0; i < bp->max_tc; i++) {
6591 bp->q_info[j].queue_id = *qptr;
6592 bp->q_ids[i] = *qptr++;
6593 bp->q_info[j].queue_profile = *qptr++;
6594 bp->tc_to_qidx[j] = j;
6595 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6596 (no_rdma && BNXT_PF(bp)))
6599 bp->max_q = bp->max_tc;
6600 bp->max_tc = max_t(u8, j, 1);
6602 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6605 if (bp->max_lltc > bp->max_tc)
6606 bp->max_lltc = bp->max_tc;
6609 mutex_unlock(&bp->hwrm_cmd_lock);
6613 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6616 struct hwrm_ver_get_input req = {0};
6617 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6620 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6621 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6622 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6623 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6624 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6625 mutex_lock(&bp->hwrm_cmd_lock);
6626 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6628 goto hwrm_ver_get_exit;
6630 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6632 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6633 resp->hwrm_intf_min_8b << 8 |
6634 resp->hwrm_intf_upd_8b;
6635 if (resp->hwrm_intf_maj_8b < 1) {
6636 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6637 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6638 resp->hwrm_intf_upd_8b);
6639 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6641 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6642 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6643 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6645 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6646 if (!bp->hwrm_cmd_timeout)
6647 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6649 if (resp->hwrm_intf_maj_8b >= 1) {
6650 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6651 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6653 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6654 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6656 bp->chip_num = le16_to_cpu(resp->chip_num);
6657 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6659 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6661 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6662 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6663 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6664 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6666 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6667 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6670 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6671 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6674 mutex_unlock(&bp->hwrm_cmd_lock);
6678 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6680 struct hwrm_fw_set_time_input req = {0};
6682 time64_t now = ktime_get_real_seconds();
6684 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6685 bp->hwrm_spec_code < 0x10400)
6688 time64_to_tm(now, 0, &tm);
6689 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6690 req.year = cpu_to_le16(1900 + tm.tm_year);
6691 req.month = 1 + tm.tm_mon;
6692 req.day = tm.tm_mday;
6693 req.hour = tm.tm_hour;
6694 req.minute = tm.tm_min;
6695 req.second = tm.tm_sec;
6696 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6699 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6702 struct bnxt_pf_info *pf = &bp->pf;
6703 struct hwrm_port_qstats_input req = {0};
6705 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6708 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6709 req.port_id = cpu_to_le16(pf->port_id);
6710 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6711 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6712 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6716 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6718 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6719 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6720 struct hwrm_port_qstats_ext_input req = {0};
6721 struct bnxt_pf_info *pf = &bp->pf;
6724 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6727 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6728 req.port_id = cpu_to_le16(pf->port_id);
6729 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6730 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6731 req.tx_stat_size = cpu_to_le16(sizeof(struct tx_port_stats_ext));
6732 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6733 mutex_lock(&bp->hwrm_cmd_lock);
6734 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6736 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6737 bp->fw_tx_stats_ext_size = le16_to_cpu(resp->tx_stat_size) / 8;
6739 bp->fw_rx_stats_ext_size = 0;
6740 bp->fw_tx_stats_ext_size = 0;
6742 if (bp->fw_tx_stats_ext_size <=
6743 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6744 mutex_unlock(&bp->hwrm_cmd_lock);
6745 bp->pri2cos_valid = 0;
6749 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6750 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6752 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6754 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6758 resp2 = bp->hwrm_cmd_resp_addr;
6759 pri2cos = &resp2->pri0_cos_queue_id;
6760 for (i = 0; i < 8; i++) {
6761 u8 queue_id = pri2cos[i];
6763 for (j = 0; j < bp->max_q; j++) {
6764 if (bp->q_ids[j] == queue_id)
6768 bp->pri2cos_valid = 1;
6770 mutex_unlock(&bp->hwrm_cmd_lock);
6774 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6776 if (bp->vxlan_port_cnt) {
6777 bnxt_hwrm_tunnel_dst_port_free(
6778 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6780 bp->vxlan_port_cnt = 0;
6781 if (bp->nge_port_cnt) {
6782 bnxt_hwrm_tunnel_dst_port_free(
6783 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6785 bp->nge_port_cnt = 0;
6788 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6794 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6795 for (i = 0; i < bp->nr_vnics; i++) {
6796 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6798 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6806 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6810 for (i = 0; i < bp->nr_vnics; i++)
6811 bnxt_hwrm_vnic_set_rss(bp, i, false);
6814 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6817 if (bp->vnic_info) {
6818 bnxt_hwrm_clear_vnic_filter(bp);
6819 /* clear all RSS setting before free vnic ctx */
6820 bnxt_hwrm_clear_vnic_rss(bp);
6821 bnxt_hwrm_vnic_ctx_free(bp);
6822 /* before free the vnic, undo the vnic tpa settings */
6823 if (bp->flags & BNXT_FLAG_TPA)
6824 bnxt_set_tpa(bp, false);
6825 bnxt_hwrm_vnic_free(bp);
6827 bnxt_hwrm_ring_free(bp, close_path);
6828 bnxt_hwrm_ring_grp_free(bp);
6830 bnxt_hwrm_stat_ctx_free(bp);
6831 bnxt_hwrm_free_tunnel_ports(bp);
6835 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6837 struct hwrm_func_cfg_input req = {0};
6840 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6841 req.fid = cpu_to_le16(0xffff);
6842 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6843 if (br_mode == BRIDGE_MODE_VEB)
6844 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6845 else if (br_mode == BRIDGE_MODE_VEPA)
6846 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6849 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6855 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
6857 struct hwrm_func_cfg_input req = {0};
6860 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
6863 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6864 req.fid = cpu_to_le16(0xffff);
6865 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
6866 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
6868 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
6870 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6876 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6878 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
6881 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
6884 /* allocate context for vnic */
6885 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
6887 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
6889 goto vnic_setup_err;
6891 bp->rsscos_nr_ctxs++;
6893 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6894 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
6896 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
6898 goto vnic_setup_err;
6900 bp->rsscos_nr_ctxs++;
6904 /* configure default vnic, ring grp */
6905 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6907 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6909 goto vnic_setup_err;
6912 /* Enable RSS hashing on vnic */
6913 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
6915 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
6917 goto vnic_setup_err;
6920 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6921 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6923 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6932 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
6936 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
6937 for (i = 0; i < nr_ctxs; i++) {
6938 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
6940 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
6944 bp->rsscos_nr_ctxs++;
6949 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
6951 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
6955 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
6957 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
6961 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6962 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
6964 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
6971 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
6973 if (bp->flags & BNXT_FLAG_CHIP_P5)
6974 return __bnxt_setup_vnic_p5(bp, vnic_id);
6976 return __bnxt_setup_vnic(bp, vnic_id);
6979 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
6981 #ifdef CONFIG_RFS_ACCEL
6984 for (i = 0; i < bp->rx_nr_rings; i++) {
6985 struct bnxt_vnic_info *vnic;
6986 u16 vnic_id = i + 1;
6989 if (vnic_id >= bp->nr_vnics)
6992 vnic = &bp->vnic_info[vnic_id];
6993 vnic->flags |= BNXT_VNIC_RFS_FLAG;
6994 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6995 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
6996 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
6998 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7002 rc = bnxt_setup_vnic(bp, vnic_id);
7012 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7013 static bool bnxt_promisc_ok(struct bnxt *bp)
7015 #ifdef CONFIG_BNXT_SRIOV
7016 if (BNXT_VF(bp) && !bp->vf.vlan)
7022 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7024 unsigned int rc = 0;
7026 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7028 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7033 rc = bnxt_hwrm_vnic_cfg(bp, 1);
7035 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7042 static int bnxt_cfg_rx_mode(struct bnxt *);
7043 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7045 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7047 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7049 unsigned int rx_nr_rings = bp->rx_nr_rings;
7052 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7054 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7060 rc = bnxt_hwrm_ring_alloc(bp);
7062 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7066 rc = bnxt_hwrm_ring_grp_alloc(bp);
7068 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7072 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7075 /* default vnic 0 */
7076 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7078 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7082 rc = bnxt_setup_vnic(bp, 0);
7086 if (bp->flags & BNXT_FLAG_RFS) {
7087 rc = bnxt_alloc_rfs_vnics(bp);
7092 if (bp->flags & BNXT_FLAG_TPA) {
7093 rc = bnxt_set_tpa(bp, true);
7099 bnxt_update_vf_mac(bp);
7101 /* Filter for default vnic 0 */
7102 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7104 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7107 vnic->uc_filter_count = 1;
7110 if (bp->dev->flags & IFF_BROADCAST)
7111 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7113 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7114 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7116 if (bp->dev->flags & IFF_ALLMULTI) {
7117 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7118 vnic->mc_list_count = 0;
7122 bnxt_mc_list_updated(bp, &mask);
7123 vnic->rx_mask |= mask;
7126 rc = bnxt_cfg_rx_mode(bp);
7130 rc = bnxt_hwrm_set_coal(bp);
7132 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7135 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7136 rc = bnxt_setup_nitroa0_vnic(bp);
7138 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7143 bnxt_hwrm_func_qcfg(bp);
7144 netdev_update_features(bp->dev);
7150 bnxt_hwrm_resource_free(bp, 0, true);
7155 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7157 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7161 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7163 bnxt_init_cp_rings(bp);
7164 bnxt_init_rx_rings(bp);
7165 bnxt_init_tx_rings(bp);
7166 bnxt_init_ring_grps(bp, irq_re_init);
7167 bnxt_init_vnics(bp);
7169 return bnxt_init_chip(bp, irq_re_init);
7172 static int bnxt_set_real_num_queues(struct bnxt *bp)
7175 struct net_device *dev = bp->dev;
7177 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7178 bp->tx_nr_rings_xdp);
7182 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7186 #ifdef CONFIG_RFS_ACCEL
7187 if (bp->flags & BNXT_FLAG_RFS)
7188 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7194 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7197 int _rx = *rx, _tx = *tx;
7200 *rx = min_t(int, _rx, max);
7201 *tx = min_t(int, _tx, max);
7206 while (_rx + _tx > max) {
7207 if (_rx > _tx && _rx > 1)
7218 static void bnxt_setup_msix(struct bnxt *bp)
7220 const int len = sizeof(bp->irq_tbl[0].name);
7221 struct net_device *dev = bp->dev;
7224 tcs = netdev_get_num_tc(dev);
7228 for (i = 0; i < tcs; i++) {
7229 count = bp->tx_nr_rings_per_tc;
7231 netdev_set_tc_queue(dev, i, count, off);
7235 for (i = 0; i < bp->cp_nr_rings; i++) {
7236 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7239 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7241 else if (i < bp->rx_nr_rings)
7246 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7248 bp->irq_tbl[map_idx].handler = bnxt_msix;
7252 static void bnxt_setup_inta(struct bnxt *bp)
7254 const int len = sizeof(bp->irq_tbl[0].name);
7256 if (netdev_get_num_tc(bp->dev))
7257 netdev_reset_tc(bp->dev);
7259 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7261 bp->irq_tbl[0].handler = bnxt_inta;
7264 static int bnxt_setup_int_mode(struct bnxt *bp)
7268 if (bp->flags & BNXT_FLAG_USING_MSIX)
7269 bnxt_setup_msix(bp);
7271 bnxt_setup_inta(bp);
7273 rc = bnxt_set_real_num_queues(bp);
7277 #ifdef CONFIG_RFS_ACCEL
7278 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7280 return bp->hw_resc.max_rsscos_ctxs;
7283 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7285 return bp->hw_resc.max_vnics;
7289 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7291 return bp->hw_resc.max_stat_ctxs;
7294 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7296 return bp->hw_resc.max_cp_rings;
7299 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7301 unsigned int cp = bp->hw_resc.max_cp_rings;
7303 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7304 cp -= bnxt_get_ulp_msix_num(bp);
7309 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7311 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7313 if (bp->flags & BNXT_FLAG_CHIP_P5)
7314 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7316 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7319 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7321 bp->hw_resc.max_irqs = max_irqs;
7324 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7328 cp = bnxt_get_max_func_cp_rings_for_en(bp);
7329 if (bp->flags & BNXT_FLAG_CHIP_P5)
7330 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7332 return cp - bp->cp_nr_rings;
7335 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7339 stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp);
7340 stat -= bp->cp_nr_rings;
7344 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7346 int max_cp = bnxt_get_max_func_cp_rings(bp);
7347 int max_irq = bnxt_get_max_func_irqs(bp);
7348 int total_req = bp->cp_nr_rings + num;
7349 int max_idx, avail_msix;
7351 max_idx = bp->total_irqs;
7352 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7353 max_idx = min_t(int, bp->total_irqs, max_cp);
7354 avail_msix = max_idx - bp->cp_nr_rings;
7355 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7358 if (max_irq < total_req) {
7359 num = max_irq - bp->cp_nr_rings;
7366 static int bnxt_get_num_msix(struct bnxt *bp)
7368 if (!BNXT_NEW_RM(bp))
7369 return bnxt_get_max_func_irqs(bp);
7371 return bnxt_nq_rings_in_use(bp);
7374 static int bnxt_init_msix(struct bnxt *bp)
7376 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7377 struct msix_entry *msix_ent;
7379 total_vecs = bnxt_get_num_msix(bp);
7380 max = bnxt_get_max_func_irqs(bp);
7381 if (total_vecs > max)
7387 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7391 for (i = 0; i < total_vecs; i++) {
7392 msix_ent[i].entry = i;
7393 msix_ent[i].vector = 0;
7396 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7399 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7400 ulp_msix = bnxt_get_ulp_msix_num(bp);
7401 if (total_vecs < 0 || total_vecs < ulp_msix) {
7403 goto msix_setup_exit;
7406 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7408 for (i = 0; i < total_vecs; i++)
7409 bp->irq_tbl[i].vector = msix_ent[i].vector;
7411 bp->total_irqs = total_vecs;
7412 /* Trim rings based upon num of vectors allocated */
7413 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7414 total_vecs - ulp_msix, min == 1);
7416 goto msix_setup_exit;
7418 bp->cp_nr_rings = (min == 1) ?
7419 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7420 bp->tx_nr_rings + bp->rx_nr_rings;
7424 goto msix_setup_exit;
7426 bp->flags |= BNXT_FLAG_USING_MSIX;
7431 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7434 pci_disable_msix(bp->pdev);
7439 static int bnxt_init_inta(struct bnxt *bp)
7441 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7446 bp->rx_nr_rings = 1;
7447 bp->tx_nr_rings = 1;
7448 bp->cp_nr_rings = 1;
7449 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7450 bp->irq_tbl[0].vector = bp->pdev->irq;
7454 static int bnxt_init_int_mode(struct bnxt *bp)
7458 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7459 rc = bnxt_init_msix(bp);
7461 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7462 /* fallback to INTA */
7463 rc = bnxt_init_inta(bp);
7468 static void bnxt_clear_int_mode(struct bnxt *bp)
7470 if (bp->flags & BNXT_FLAG_USING_MSIX)
7471 pci_disable_msix(bp->pdev);
7475 bp->flags &= ~BNXT_FLAG_USING_MSIX;
7478 int bnxt_reserve_rings(struct bnxt *bp)
7480 int tcs = netdev_get_num_tc(bp->dev);
7481 bool reinit_irq = false;
7484 if (!bnxt_need_reserve_rings(bp))
7487 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
7488 bnxt_ulp_irq_stop(bp);
7489 bnxt_clear_int_mode(bp);
7492 rc = __bnxt_reserve_rings(bp);
7495 rc = bnxt_init_int_mode(bp);
7496 bnxt_ulp_irq_restart(bp, rc);
7499 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7502 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7503 netdev_err(bp->dev, "tx ring reservation failure\n");
7504 netdev_reset_tc(bp->dev);
7505 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7511 static void bnxt_free_irq(struct bnxt *bp)
7513 struct bnxt_irq *irq;
7516 #ifdef CONFIG_RFS_ACCEL
7517 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7518 bp->dev->rx_cpu_rmap = NULL;
7520 if (!bp->irq_tbl || !bp->bnapi)
7523 for (i = 0; i < bp->cp_nr_rings; i++) {
7524 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7526 irq = &bp->irq_tbl[map_idx];
7527 if (irq->requested) {
7528 if (irq->have_cpumask) {
7529 irq_set_affinity_hint(irq->vector, NULL);
7530 free_cpumask_var(irq->cpu_mask);
7531 irq->have_cpumask = 0;
7533 free_irq(irq->vector, bp->bnapi[i]);
7540 static int bnxt_request_irq(struct bnxt *bp)
7543 unsigned long flags = 0;
7544 #ifdef CONFIG_RFS_ACCEL
7545 struct cpu_rmap *rmap;
7548 rc = bnxt_setup_int_mode(bp);
7550 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7554 #ifdef CONFIG_RFS_ACCEL
7555 rmap = bp->dev->rx_cpu_rmap;
7557 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7558 flags = IRQF_SHARED;
7560 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7561 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7562 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7564 #ifdef CONFIG_RFS_ACCEL
7565 if (rmap && bp->bnapi[i]->rx_ring) {
7566 rc = irq_cpu_rmap_add(rmap, irq->vector);
7568 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7573 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7580 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7581 int numa_node = dev_to_node(&bp->pdev->dev);
7583 irq->have_cpumask = 1;
7584 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7586 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7588 netdev_warn(bp->dev,
7589 "Set affinity failed, IRQ = %d\n",
7598 static void bnxt_del_napi(struct bnxt *bp)
7605 for (i = 0; i < bp->cp_nr_rings; i++) {
7606 struct bnxt_napi *bnapi = bp->bnapi[i];
7608 napi_hash_del(&bnapi->napi);
7609 netif_napi_del(&bnapi->napi);
7611 /* We called napi_hash_del() before netif_napi_del(), we need
7612 * to respect an RCU grace period before freeing napi structures.
7617 static void bnxt_init_napi(struct bnxt *bp)
7620 unsigned int cp_nr_rings = bp->cp_nr_rings;
7621 struct bnxt_napi *bnapi;
7623 if (bp->flags & BNXT_FLAG_USING_MSIX) {
7624 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7626 if (bp->flags & BNXT_FLAG_CHIP_P5)
7627 poll_fn = bnxt_poll_p5;
7628 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7630 for (i = 0; i < cp_nr_rings; i++) {
7631 bnapi = bp->bnapi[i];
7632 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7634 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7635 bnapi = bp->bnapi[cp_nr_rings];
7636 netif_napi_add(bp->dev, &bnapi->napi,
7637 bnxt_poll_nitroa0, 64);
7640 bnapi = bp->bnapi[0];
7641 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7645 static void bnxt_disable_napi(struct bnxt *bp)
7652 for (i = 0; i < bp->cp_nr_rings; i++) {
7653 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7655 if (bp->bnapi[i]->rx_ring)
7656 cancel_work_sync(&cpr->dim.work);
7658 napi_disable(&bp->bnapi[i]->napi);
7662 static void bnxt_enable_napi(struct bnxt *bp)
7666 for (i = 0; i < bp->cp_nr_rings; i++) {
7667 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7668 bp->bnapi[i]->in_reset = false;
7670 if (bp->bnapi[i]->rx_ring) {
7671 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7672 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7674 napi_enable(&bp->bnapi[i]->napi);
7678 void bnxt_tx_disable(struct bnxt *bp)
7681 struct bnxt_tx_ring_info *txr;
7684 for (i = 0; i < bp->tx_nr_rings; i++) {
7685 txr = &bp->tx_ring[i];
7686 txr->dev_state = BNXT_DEV_STATE_CLOSING;
7689 /* Stop all TX queues */
7690 netif_tx_disable(bp->dev);
7691 netif_carrier_off(bp->dev);
7694 void bnxt_tx_enable(struct bnxt *bp)
7697 struct bnxt_tx_ring_info *txr;
7699 for (i = 0; i < bp->tx_nr_rings; i++) {
7700 txr = &bp->tx_ring[i];
7703 netif_tx_wake_all_queues(bp->dev);
7704 if (bp->link_info.link_up)
7705 netif_carrier_on(bp->dev);
7708 static void bnxt_report_link(struct bnxt *bp)
7710 if (bp->link_info.link_up) {
7712 const char *flow_ctrl;
7716 netif_carrier_on(bp->dev);
7717 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7721 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7722 flow_ctrl = "ON - receive & transmit";
7723 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7724 flow_ctrl = "ON - transmit";
7725 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7726 flow_ctrl = "ON - receive";
7729 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7730 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7731 speed, duplex, flow_ctrl);
7732 if (bp->flags & BNXT_FLAG_EEE_CAP)
7733 netdev_info(bp->dev, "EEE is %s\n",
7734 bp->eee.eee_active ? "active" :
7736 fec = bp->link_info.fec_cfg;
7737 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7738 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7739 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7740 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7741 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7743 netif_carrier_off(bp->dev);
7744 netdev_err(bp->dev, "NIC Link is Down\n");
7748 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7751 struct hwrm_port_phy_qcaps_input req = {0};
7752 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7753 struct bnxt_link_info *link_info = &bp->link_info;
7755 if (bp->hwrm_spec_code < 0x10201)
7758 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7760 mutex_lock(&bp->hwrm_cmd_lock);
7761 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7763 goto hwrm_phy_qcaps_exit;
7765 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7766 struct ethtool_eee *eee = &bp->eee;
7767 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7769 bp->flags |= BNXT_FLAG_EEE_CAP;
7770 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7771 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7772 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7773 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7774 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7776 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7778 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7780 if (resp->supported_speeds_auto_mode)
7781 link_info->support_auto_speeds =
7782 le16_to_cpu(resp->supported_speeds_auto_mode);
7784 bp->port_count = resp->port_cnt;
7786 hwrm_phy_qcaps_exit:
7787 mutex_unlock(&bp->hwrm_cmd_lock);
7791 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7794 struct bnxt_link_info *link_info = &bp->link_info;
7795 struct hwrm_port_phy_qcfg_input req = {0};
7796 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7797 u8 link_up = link_info->link_up;
7800 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7802 mutex_lock(&bp->hwrm_cmd_lock);
7803 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7805 mutex_unlock(&bp->hwrm_cmd_lock);
7809 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7810 link_info->phy_link_status = resp->link;
7811 link_info->duplex = resp->duplex_cfg;
7812 if (bp->hwrm_spec_code >= 0x10800)
7813 link_info->duplex = resp->duplex_state;
7814 link_info->pause = resp->pause;
7815 link_info->auto_mode = resp->auto_mode;
7816 link_info->auto_pause_setting = resp->auto_pause;
7817 link_info->lp_pause = resp->link_partner_adv_pause;
7818 link_info->force_pause_setting = resp->force_pause;
7819 link_info->duplex_setting = resp->duplex_cfg;
7820 if (link_info->phy_link_status == BNXT_LINK_LINK)
7821 link_info->link_speed = le16_to_cpu(resp->link_speed);
7823 link_info->link_speed = 0;
7824 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
7825 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7826 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
7827 link_info->lp_auto_link_speeds =
7828 le16_to_cpu(resp->link_partner_adv_speeds);
7829 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7830 link_info->phy_ver[0] = resp->phy_maj;
7831 link_info->phy_ver[1] = resp->phy_min;
7832 link_info->phy_ver[2] = resp->phy_bld;
7833 link_info->media_type = resp->media_type;
7834 link_info->phy_type = resp->phy_type;
7835 link_info->transceiver = resp->xcvr_pkg_type;
7836 link_info->phy_addr = resp->eee_config_phy_addr &
7837 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
7838 link_info->module_status = resp->module_status;
7840 if (bp->flags & BNXT_FLAG_EEE_CAP) {
7841 struct ethtool_eee *eee = &bp->eee;
7844 eee->eee_active = 0;
7845 if (resp->eee_config_phy_addr &
7846 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7847 eee->eee_active = 1;
7848 fw_speeds = le16_to_cpu(
7849 resp->link_partner_adv_eee_link_speed_mask);
7850 eee->lp_advertised =
7851 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7854 /* Pull initial EEE config */
7855 if (!chng_link_state) {
7856 if (resp->eee_config_phy_addr &
7857 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
7858 eee->eee_enabled = 1;
7860 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
7862 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7864 if (resp->eee_config_phy_addr &
7865 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
7868 eee->tx_lpi_enabled = 1;
7869 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
7870 eee->tx_lpi_timer = le32_to_cpu(tmr) &
7871 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
7876 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
7877 if (bp->hwrm_spec_code >= 0x10504)
7878 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
7880 /* TODO: need to add more logic to report VF link */
7881 if (chng_link_state) {
7882 if (link_info->phy_link_status == BNXT_LINK_LINK)
7883 link_info->link_up = 1;
7885 link_info->link_up = 0;
7886 if (link_up != link_info->link_up)
7887 bnxt_report_link(bp);
7889 /* alwasy link down if not require to update link state */
7890 link_info->link_up = 0;
7892 mutex_unlock(&bp->hwrm_cmd_lock);
7894 if (!BNXT_SINGLE_PF(bp))
7897 diff = link_info->support_auto_speeds ^ link_info->advertising;
7898 if ((link_info->support_auto_speeds | diff) !=
7899 link_info->support_auto_speeds) {
7900 /* An advertised speed is no longer supported, so we need to
7901 * update the advertisement settings. Caller holds RTNL
7902 * so we can modify link settings.
7904 link_info->advertising = link_info->support_auto_speeds;
7905 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
7906 bnxt_hwrm_set_link_setting(bp, true, false);
7911 static void bnxt_get_port_module_status(struct bnxt *bp)
7913 struct bnxt_link_info *link_info = &bp->link_info;
7914 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
7917 if (bnxt_update_link(bp, true))
7920 module_status = link_info->module_status;
7921 switch (module_status) {
7922 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
7923 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
7924 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
7925 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
7927 if (bp->hwrm_spec_code >= 0x10201) {
7928 netdev_warn(bp->dev, "Module part number %s\n",
7929 resp->phy_vendor_partnumber);
7931 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
7932 netdev_warn(bp->dev, "TX is disabled\n");
7933 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
7934 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
7939 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
7941 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
7942 if (bp->hwrm_spec_code >= 0x10201)
7944 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
7945 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7946 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
7947 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7948 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
7950 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7952 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
7953 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
7954 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
7955 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
7957 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
7958 if (bp->hwrm_spec_code >= 0x10201) {
7959 req->auto_pause = req->force_pause;
7960 req->enables |= cpu_to_le32(
7961 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
7966 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
7967 struct hwrm_port_phy_cfg_input *req)
7969 u8 autoneg = bp->link_info.autoneg;
7970 u16 fw_link_speed = bp->link_info.req_link_speed;
7971 u16 advertising = bp->link_info.advertising;
7973 if (autoneg & BNXT_AUTONEG_SPEED) {
7975 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
7977 req->enables |= cpu_to_le32(
7978 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
7979 req->auto_link_speed_mask = cpu_to_le16(advertising);
7981 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
7983 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
7985 req->force_link_speed = cpu_to_le16(fw_link_speed);
7986 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
7989 /* tell chimp that the setting takes effect immediately */
7990 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
7993 int bnxt_hwrm_set_pause(struct bnxt *bp)
7995 struct hwrm_port_phy_cfg_input req = {0};
7998 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
7999 bnxt_hwrm_set_pause_common(bp, &req);
8001 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8002 bp->link_info.force_link_chng)
8003 bnxt_hwrm_set_link_common(bp, &req);
8005 mutex_lock(&bp->hwrm_cmd_lock);
8006 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8007 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8008 /* since changing of pause setting doesn't trigger any link
8009 * change event, the driver needs to update the current pause
8010 * result upon successfully return of the phy_cfg command
8012 bp->link_info.pause =
8013 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8014 bp->link_info.auto_pause_setting = 0;
8015 if (!bp->link_info.force_link_chng)
8016 bnxt_report_link(bp);
8018 bp->link_info.force_link_chng = false;
8019 mutex_unlock(&bp->hwrm_cmd_lock);
8023 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8024 struct hwrm_port_phy_cfg_input *req)
8026 struct ethtool_eee *eee = &bp->eee;
8028 if (eee->eee_enabled) {
8030 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8032 if (eee->tx_lpi_enabled)
8033 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8035 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8037 req->flags |= cpu_to_le32(flags);
8038 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8039 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8040 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8042 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8046 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8048 struct hwrm_port_phy_cfg_input req = {0};
8050 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8052 bnxt_hwrm_set_pause_common(bp, &req);
8054 bnxt_hwrm_set_link_common(bp, &req);
8057 bnxt_hwrm_set_eee(bp, &req);
8058 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8061 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8063 struct hwrm_port_phy_cfg_input req = {0};
8065 if (!BNXT_SINGLE_PF(bp))
8068 if (pci_num_vf(bp->pdev))
8071 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8072 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8073 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8076 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8078 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8079 struct hwrm_func_drv_if_change_input req = {0};
8080 bool resc_reinit = false;
8083 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8086 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8088 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8089 mutex_lock(&bp->hwrm_cmd_lock);
8090 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8091 if (!rc && (resp->flags &
8092 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8094 mutex_unlock(&bp->hwrm_cmd_lock);
8096 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8097 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8099 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8100 hw_resc->resv_cp_rings = 0;
8101 hw_resc->resv_stat_ctxs = 0;
8102 hw_resc->resv_irqs = 0;
8103 hw_resc->resv_tx_rings = 0;
8104 hw_resc->resv_rx_rings = 0;
8105 hw_resc->resv_hw_ring_grps = 0;
8106 hw_resc->resv_vnics = 0;
8107 bp->tx_nr_rings = 0;
8108 bp->rx_nr_rings = 0;
8113 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8115 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8116 struct hwrm_port_led_qcaps_input req = {0};
8117 struct bnxt_pf_info *pf = &bp->pf;
8120 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8123 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8124 req.port_id = cpu_to_le16(pf->port_id);
8125 mutex_lock(&bp->hwrm_cmd_lock);
8126 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8128 mutex_unlock(&bp->hwrm_cmd_lock);
8131 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8134 bp->num_leds = resp->num_leds;
8135 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8137 for (i = 0; i < bp->num_leds; i++) {
8138 struct bnxt_led_info *led = &bp->leds[i];
8139 __le16 caps = led->led_state_caps;
8141 if (!led->led_group_id ||
8142 !BNXT_LED_ALT_BLINK_CAP(caps)) {
8148 mutex_unlock(&bp->hwrm_cmd_lock);
8152 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8154 struct hwrm_wol_filter_alloc_input req = {0};
8155 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8158 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8159 req.port_id = cpu_to_le16(bp->pf.port_id);
8160 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8161 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8162 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8163 mutex_lock(&bp->hwrm_cmd_lock);
8164 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8166 bp->wol_filter_id = resp->wol_filter_id;
8167 mutex_unlock(&bp->hwrm_cmd_lock);
8171 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8173 struct hwrm_wol_filter_free_input req = {0};
8176 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8177 req.port_id = cpu_to_le16(bp->pf.port_id);
8178 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8179 req.wol_filter_id = bp->wol_filter_id;
8180 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8184 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8186 struct hwrm_wol_filter_qcfg_input req = {0};
8187 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8188 u16 next_handle = 0;
8191 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8192 req.port_id = cpu_to_le16(bp->pf.port_id);
8193 req.handle = cpu_to_le16(handle);
8194 mutex_lock(&bp->hwrm_cmd_lock);
8195 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8197 next_handle = le16_to_cpu(resp->next_handle);
8198 if (next_handle != 0) {
8199 if (resp->wol_type ==
8200 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8202 bp->wol_filter_id = resp->wol_filter_id;
8206 mutex_unlock(&bp->hwrm_cmd_lock);
8210 static void bnxt_get_wol_settings(struct bnxt *bp)
8214 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8218 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8219 } while (handle && handle != 0xffff);
8222 #ifdef CONFIG_BNXT_HWMON
8223 static ssize_t bnxt_show_temp(struct device *dev,
8224 struct device_attribute *devattr, char *buf)
8226 struct hwrm_temp_monitor_query_input req = {0};
8227 struct hwrm_temp_monitor_query_output *resp;
8228 struct bnxt *bp = dev_get_drvdata(dev);
8231 resp = bp->hwrm_cmd_resp_addr;
8232 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8233 mutex_lock(&bp->hwrm_cmd_lock);
8234 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8235 temp = resp->temp * 1000; /* display millidegree */
8236 mutex_unlock(&bp->hwrm_cmd_lock);
8238 return sprintf(buf, "%u\n", temp);
8240 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8242 static struct attribute *bnxt_attrs[] = {
8243 &sensor_dev_attr_temp1_input.dev_attr.attr,
8246 ATTRIBUTE_GROUPS(bnxt);
8248 static void bnxt_hwmon_close(struct bnxt *bp)
8250 if (bp->hwmon_dev) {
8251 hwmon_device_unregister(bp->hwmon_dev);
8252 bp->hwmon_dev = NULL;
8256 static void bnxt_hwmon_open(struct bnxt *bp)
8258 struct pci_dev *pdev = bp->pdev;
8260 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8261 DRV_MODULE_NAME, bp,
8263 if (IS_ERR(bp->hwmon_dev)) {
8264 bp->hwmon_dev = NULL;
8265 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8269 static void bnxt_hwmon_close(struct bnxt *bp)
8273 static void bnxt_hwmon_open(struct bnxt *bp)
8278 static bool bnxt_eee_config_ok(struct bnxt *bp)
8280 struct ethtool_eee *eee = &bp->eee;
8281 struct bnxt_link_info *link_info = &bp->link_info;
8283 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8286 if (eee->eee_enabled) {
8288 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8290 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8291 eee->eee_enabled = 0;
8294 if (eee->advertised & ~advertising) {
8295 eee->advertised = advertising & eee->supported;
8302 static int bnxt_update_phy_setting(struct bnxt *bp)
8305 bool update_link = false;
8306 bool update_pause = false;
8307 bool update_eee = false;
8308 struct bnxt_link_info *link_info = &bp->link_info;
8310 rc = bnxt_update_link(bp, true);
8312 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8316 if (!BNXT_SINGLE_PF(bp))
8319 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8320 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8321 link_info->req_flow_ctrl)
8322 update_pause = true;
8323 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8324 link_info->force_pause_setting != link_info->req_flow_ctrl)
8325 update_pause = true;
8326 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8327 if (BNXT_AUTO_MODE(link_info->auto_mode))
8329 if (link_info->req_link_speed != link_info->force_link_speed)
8331 if (link_info->req_duplex != link_info->duplex_setting)
8334 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8336 if (link_info->advertising != link_info->auto_link_speeds)
8340 /* The last close may have shutdown the link, so need to call
8341 * PHY_CFG to bring it back up.
8343 if (!netif_carrier_ok(bp->dev))
8346 if (!bnxt_eee_config_ok(bp))
8350 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8351 else if (update_pause)
8352 rc = bnxt_hwrm_set_pause(bp);
8354 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8362 /* Common routine to pre-map certain register block to different GRC window.
8363 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8364 * in PF and 3 windows in VF that can be customized to map in different
8367 static void bnxt_preset_reg_win(struct bnxt *bp)
8370 /* CAG registers map to GRC window #4 */
8371 writel(BNXT_CAG_REG_BASE,
8372 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8376 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8378 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8382 bnxt_preset_reg_win(bp);
8383 netif_carrier_off(bp->dev);
8385 /* Reserve rings now if none were reserved at driver probe. */
8386 rc = bnxt_init_dflt_ring_mode(bp);
8388 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8392 rc = bnxt_reserve_rings(bp);
8395 if ((bp->flags & BNXT_FLAG_RFS) &&
8396 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8397 /* disable RFS if falling back to INTA */
8398 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8399 bp->flags &= ~BNXT_FLAG_RFS;
8402 rc = bnxt_alloc_mem(bp, irq_re_init);
8404 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8405 goto open_err_free_mem;
8410 rc = bnxt_request_irq(bp);
8412 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8417 bnxt_enable_napi(bp);
8418 bnxt_debug_dev_init(bp);
8420 rc = bnxt_init_nic(bp, irq_re_init);
8422 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8427 mutex_lock(&bp->link_lock);
8428 rc = bnxt_update_phy_setting(bp);
8429 mutex_unlock(&bp->link_lock);
8431 netdev_warn(bp->dev, "failed to update phy settings\n");
8432 if (BNXT_SINGLE_PF(bp)) {
8433 bp->link_info.phy_retry = true;
8434 bp->link_info.phy_retry_expires =
8441 udp_tunnel_get_rx_info(bp->dev);
8443 set_bit(BNXT_STATE_OPEN, &bp->state);
8444 bnxt_enable_int(bp);
8445 /* Enable TX queues */
8447 mod_timer(&bp->timer, jiffies + bp->current_interval);
8448 /* Poll link status and check for SFP+ module status */
8449 bnxt_get_port_module_status(bp);
8451 /* VF-reps may need to be re-opened after the PF is re-opened */
8453 bnxt_vf_reps_open(bp);
8457 bnxt_debug_dev_exit(bp);
8458 bnxt_disable_napi(bp);
8466 bnxt_free_mem(bp, true);
8470 /* rtnl_lock held */
8471 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8475 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8477 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8483 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8484 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
8487 int bnxt_half_open_nic(struct bnxt *bp)
8491 rc = bnxt_alloc_mem(bp, false);
8493 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8496 rc = bnxt_init_nic(bp, false);
8498 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8505 bnxt_free_mem(bp, false);
8510 /* rtnl_lock held, this call can only be made after a previous successful
8511 * call to bnxt_half_open_nic().
8513 void bnxt_half_close_nic(struct bnxt *bp)
8515 bnxt_hwrm_resource_free(bp, false, false);
8517 bnxt_free_mem(bp, false);
8520 static int bnxt_open(struct net_device *dev)
8522 struct bnxt *bp = netdev_priv(dev);
8525 bnxt_hwrm_if_change(bp, true);
8526 rc = __bnxt_open_nic(bp, true, true);
8528 bnxt_hwrm_if_change(bp, false);
8530 bnxt_hwmon_open(bp);
8535 static bool bnxt_drv_busy(struct bnxt *bp)
8537 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8538 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8541 static void bnxt_get_ring_stats(struct bnxt *bp,
8542 struct rtnl_link_stats64 *stats);
8544 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8547 /* Close the VF-reps before closing PF */
8549 bnxt_vf_reps_close(bp);
8551 /* Change device state to avoid TX queue wake up's */
8552 bnxt_tx_disable(bp);
8554 clear_bit(BNXT_STATE_OPEN, &bp->state);
8555 smp_mb__after_atomic();
8556 while (bnxt_drv_busy(bp))
8559 /* Flush rings and and disable interrupts */
8560 bnxt_shutdown_nic(bp, irq_re_init);
8562 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8564 bnxt_debug_dev_exit(bp);
8565 bnxt_disable_napi(bp);
8566 del_timer_sync(&bp->timer);
8569 /* Save ring stats before shutdown */
8571 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8576 bnxt_free_mem(bp, irq_re_init);
8579 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8583 #ifdef CONFIG_BNXT_SRIOV
8584 if (bp->sriov_cfg) {
8585 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8587 BNXT_SRIOV_CFG_WAIT_TMO);
8589 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8592 __bnxt_close_nic(bp, irq_re_init, link_re_init);
8596 static int bnxt_close(struct net_device *dev)
8598 struct bnxt *bp = netdev_priv(dev);
8600 bnxt_hwmon_close(bp);
8601 bnxt_close_nic(bp, true, true);
8602 bnxt_hwrm_shutdown_link(bp);
8603 bnxt_hwrm_if_change(bp, false);
8607 /* rtnl_lock held */
8608 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8614 if (!netif_running(dev))
8621 if (!netif_running(dev))
8633 static void bnxt_get_ring_stats(struct bnxt *bp,
8634 struct rtnl_link_stats64 *stats)
8639 for (i = 0; i < bp->cp_nr_rings; i++) {
8640 struct bnxt_napi *bnapi = bp->bnapi[i];
8641 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8642 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8644 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8645 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8646 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8648 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8649 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8650 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8652 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8653 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8654 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8656 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8657 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8658 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8660 stats->rx_missed_errors +=
8661 le64_to_cpu(hw_stats->rx_discard_pkts);
8663 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8665 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8669 static void bnxt_add_prev_stats(struct bnxt *bp,
8670 struct rtnl_link_stats64 *stats)
8672 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8674 stats->rx_packets += prev_stats->rx_packets;
8675 stats->tx_packets += prev_stats->tx_packets;
8676 stats->rx_bytes += prev_stats->rx_bytes;
8677 stats->tx_bytes += prev_stats->tx_bytes;
8678 stats->rx_missed_errors += prev_stats->rx_missed_errors;
8679 stats->multicast += prev_stats->multicast;
8680 stats->tx_dropped += prev_stats->tx_dropped;
8684 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8686 struct bnxt *bp = netdev_priv(dev);
8688 set_bit(BNXT_STATE_READ_STATS, &bp->state);
8689 /* Make sure bnxt_close_nic() sees that we are reading stats before
8690 * we check the BNXT_STATE_OPEN flag.
8692 smp_mb__after_atomic();
8693 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8694 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8695 *stats = bp->net_stats_prev;
8699 bnxt_get_ring_stats(bp, stats);
8700 bnxt_add_prev_stats(bp, stats);
8702 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8703 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8704 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8706 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8707 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8708 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8709 le64_to_cpu(rx->rx_ovrsz_frames) +
8710 le64_to_cpu(rx->rx_runt_frames);
8711 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8712 le64_to_cpu(rx->rx_jbr_frames);
8713 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8714 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8715 stats->tx_errors = le64_to_cpu(tx->tx_err);
8717 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8720 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8722 struct net_device *dev = bp->dev;
8723 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8724 struct netdev_hw_addr *ha;
8727 bool update = false;
8730 netdev_for_each_mc_addr(ha, dev) {
8731 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8732 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8733 vnic->mc_list_count = 0;
8737 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8738 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8745 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8747 if (mc_count != vnic->mc_list_count) {
8748 vnic->mc_list_count = mc_count;
8754 static bool bnxt_uc_list_updated(struct bnxt *bp)
8756 struct net_device *dev = bp->dev;
8757 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8758 struct netdev_hw_addr *ha;
8761 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8764 netdev_for_each_uc_addr(ha, dev) {
8765 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8773 static void bnxt_set_rx_mode(struct net_device *dev)
8775 struct bnxt *bp = netdev_priv(dev);
8776 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8777 u32 mask = vnic->rx_mask;
8778 bool mc_update = false;
8781 if (!netif_running(dev))
8784 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8785 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
8786 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
8787 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
8789 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8790 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8792 uc_update = bnxt_uc_list_updated(bp);
8794 if (dev->flags & IFF_BROADCAST)
8795 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8796 if (dev->flags & IFF_ALLMULTI) {
8797 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8798 vnic->mc_list_count = 0;
8800 mc_update = bnxt_mc_list_updated(bp, &mask);
8803 if (mask != vnic->rx_mask || uc_update || mc_update) {
8804 vnic->rx_mask = mask;
8806 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
8807 bnxt_queue_sp_work(bp);
8811 static int bnxt_cfg_rx_mode(struct bnxt *bp)
8813 struct net_device *dev = bp->dev;
8814 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8815 struct netdev_hw_addr *ha;
8819 netif_addr_lock_bh(dev);
8820 uc_update = bnxt_uc_list_updated(bp);
8821 netif_addr_unlock_bh(dev);
8826 mutex_lock(&bp->hwrm_cmd_lock);
8827 for (i = 1; i < vnic->uc_filter_count; i++) {
8828 struct hwrm_cfa_l2_filter_free_input req = {0};
8830 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
8833 req.l2_filter_id = vnic->fw_l2_filter_id[i];
8835 rc = _hwrm_send_message(bp, &req, sizeof(req),
8838 mutex_unlock(&bp->hwrm_cmd_lock);
8840 vnic->uc_filter_count = 1;
8842 netif_addr_lock_bh(dev);
8843 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
8844 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8846 netdev_for_each_uc_addr(ha, dev) {
8847 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
8849 vnic->uc_filter_count++;
8852 netif_addr_unlock_bh(dev);
8854 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
8855 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
8857 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
8859 vnic->uc_filter_count = i;
8865 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
8867 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
8873 static bool bnxt_can_reserve_rings(struct bnxt *bp)
8875 #ifdef CONFIG_BNXT_SRIOV
8876 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
8877 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8879 /* No minimum rings were provisioned by the PF. Don't
8880 * reserve rings by default when device is down.
8882 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
8885 if (!netif_running(bp->dev))
8892 /* If the chip and firmware supports RFS */
8893 static bool bnxt_rfs_supported(struct bnxt *bp)
8895 if (bp->flags & BNXT_FLAG_CHIP_P5)
8897 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
8899 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8904 /* If runtime conditions support RFS */
8905 static bool bnxt_rfs_capable(struct bnxt *bp)
8907 #ifdef CONFIG_RFS_ACCEL
8908 int vnics, max_vnics, max_rss_ctxs;
8910 if (bp->flags & BNXT_FLAG_CHIP_P5)
8912 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
8915 vnics = 1 + bp->rx_nr_rings;
8916 max_vnics = bnxt_get_max_func_vnics(bp);
8917 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
8919 /* RSS contexts not a limiting factor */
8920 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8921 max_rss_ctxs = max_vnics;
8922 if (vnics > max_vnics || vnics > max_rss_ctxs) {
8923 if (bp->rx_nr_rings > 1)
8924 netdev_warn(bp->dev,
8925 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
8926 min(max_rss_ctxs - 1, max_vnics - 1));
8930 if (!BNXT_NEW_RM(bp))
8933 if (vnics == bp->hw_resc.resv_vnics)
8936 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
8937 if (vnics <= bp->hw_resc.resv_vnics)
8940 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
8941 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
8948 static netdev_features_t bnxt_fix_features(struct net_device *dev,
8949 netdev_features_t features)
8951 struct bnxt *bp = netdev_priv(dev);
8953 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
8954 features &= ~NETIF_F_NTUPLE;
8956 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
8957 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8959 if (!(features & NETIF_F_GRO))
8960 features &= ~NETIF_F_GRO_HW;
8962 if (features & NETIF_F_GRO_HW)
8963 features &= ~NETIF_F_LRO;
8965 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
8966 * turned on or off together.
8968 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
8969 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
8970 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
8971 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
8972 NETIF_F_HW_VLAN_STAG_RX);
8974 features |= NETIF_F_HW_VLAN_CTAG_RX |
8975 NETIF_F_HW_VLAN_STAG_RX;
8977 #ifdef CONFIG_BNXT_SRIOV
8980 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
8981 NETIF_F_HW_VLAN_STAG_RX);
8988 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
8990 struct bnxt *bp = netdev_priv(dev);
8991 u32 flags = bp->flags;
8994 bool re_init = false;
8995 bool update_tpa = false;
8997 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
8998 if (features & NETIF_F_GRO_HW)
8999 flags |= BNXT_FLAG_GRO;
9000 else if (features & NETIF_F_LRO)
9001 flags |= BNXT_FLAG_LRO;
9003 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9004 flags &= ~BNXT_FLAG_TPA;
9006 if (features & NETIF_F_HW_VLAN_CTAG_RX)
9007 flags |= BNXT_FLAG_STRIP_VLAN;
9009 if (features & NETIF_F_NTUPLE)
9010 flags |= BNXT_FLAG_RFS;
9012 changes = flags ^ bp->flags;
9013 if (changes & BNXT_FLAG_TPA) {
9015 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9016 (flags & BNXT_FLAG_TPA) == 0)
9020 if (changes & ~BNXT_FLAG_TPA)
9023 if (flags != bp->flags) {
9024 u32 old_flags = bp->flags;
9028 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9030 bnxt_set_ring_params(bp);
9035 bnxt_close_nic(bp, false, false);
9037 bnxt_set_ring_params(bp);
9039 return bnxt_open_nic(bp, false, false);
9042 rc = bnxt_set_tpa(bp,
9043 (flags & BNXT_FLAG_TPA) ?
9046 bp->flags = old_flags;
9052 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9053 u32 ring_id, u32 *prod, u32 *cons)
9055 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9056 struct hwrm_dbg_ring_info_get_input req = {0};
9059 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9060 req.ring_type = ring_type;
9061 req.fw_ring_id = cpu_to_le32(ring_id);
9062 mutex_lock(&bp->hwrm_cmd_lock);
9063 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9065 *prod = le32_to_cpu(resp->producer_index);
9066 *cons = le32_to_cpu(resp->consumer_index);
9068 mutex_unlock(&bp->hwrm_cmd_lock);
9072 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9074 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9075 int i = bnapi->index;
9080 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9081 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9085 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9087 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9088 int i = bnapi->index;
9093 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9094 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9095 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9096 rxr->rx_sw_agg_prod);
9099 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9101 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9102 int i = bnapi->index;
9104 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9105 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9108 static void bnxt_dbg_dump_states(struct bnxt *bp)
9111 struct bnxt_napi *bnapi;
9113 for (i = 0; i < bp->cp_nr_rings; i++) {
9114 bnapi = bp->bnapi[i];
9115 if (netif_msg_drv(bp)) {
9116 bnxt_dump_tx_sw_state(bnapi);
9117 bnxt_dump_rx_sw_state(bnapi);
9118 bnxt_dump_cp_sw_state(bnapi);
9123 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9126 bnxt_dbg_dump_states(bp);
9127 if (netif_running(bp->dev)) {
9132 bnxt_close_nic(bp, false, false);
9133 rc = bnxt_open_nic(bp, false, false);
9139 static void bnxt_tx_timeout(struct net_device *dev)
9141 struct bnxt *bp = netdev_priv(dev);
9143 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
9144 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9145 bnxt_queue_sp_work(bp);
9148 static void bnxt_timer(struct timer_list *t)
9150 struct bnxt *bp = from_timer(bp, t, timer);
9151 struct net_device *dev = bp->dev;
9153 if (!netif_running(dev))
9156 if (atomic_read(&bp->intr_sem) != 0)
9157 goto bnxt_restart_timer;
9159 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9160 bp->stats_coal_ticks) {
9161 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9162 bnxt_queue_sp_work(bp);
9165 if (bnxt_tc_flower_enabled(bp)) {
9166 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9167 bnxt_queue_sp_work(bp);
9170 if (bp->link_info.phy_retry) {
9171 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9172 bp->link_info.phy_retry = 0;
9173 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9175 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9176 bnxt_queue_sp_work(bp);
9180 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9181 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9182 bnxt_queue_sp_work(bp);
9185 mod_timer(&bp->timer, jiffies + bp->current_interval);
9188 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9190 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9191 * set. If the device is being closed, bnxt_close() may be holding
9192 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
9193 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9195 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9199 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9201 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9205 /* Only called from bnxt_sp_task() */
9206 static void bnxt_reset(struct bnxt *bp, bool silent)
9208 bnxt_rtnl_lock_sp(bp);
9209 if (test_bit(BNXT_STATE_OPEN, &bp->state))
9210 bnxt_reset_task(bp, silent);
9211 bnxt_rtnl_unlock_sp(bp);
9214 static void bnxt_chk_missed_irq(struct bnxt *bp)
9218 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9221 for (i = 0; i < bp->cp_nr_rings; i++) {
9222 struct bnxt_napi *bnapi = bp->bnapi[i];
9223 struct bnxt_cp_ring_info *cpr;
9230 cpr = &bnapi->cp_ring;
9231 for (j = 0; j < 2; j++) {
9232 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9235 if (!cpr2 || cpr2->has_more_work ||
9236 !bnxt_has_work(bp, cpr2))
9239 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9240 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9243 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9244 bnxt_dbg_hwrm_ring_info_get(bp,
9245 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9246 fw_ring_id, &val[0], &val[1]);
9252 static void bnxt_cfg_ntp_filters(struct bnxt *);
9254 static void bnxt_sp_task(struct work_struct *work)
9256 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9258 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9259 smp_mb__after_atomic();
9260 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9261 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9265 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9266 bnxt_cfg_rx_mode(bp);
9268 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9269 bnxt_cfg_ntp_filters(bp);
9270 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9271 bnxt_hwrm_exec_fwd_req(bp);
9272 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9273 bnxt_hwrm_tunnel_dst_port_alloc(
9275 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9277 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9278 bnxt_hwrm_tunnel_dst_port_free(
9279 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9281 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9282 bnxt_hwrm_tunnel_dst_port_alloc(
9284 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9286 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9287 bnxt_hwrm_tunnel_dst_port_free(
9288 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9290 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9291 bnxt_hwrm_port_qstats(bp);
9292 bnxt_hwrm_port_qstats_ext(bp);
9295 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9298 mutex_lock(&bp->link_lock);
9299 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9301 bnxt_hwrm_phy_qcaps(bp);
9303 rc = bnxt_update_link(bp, true);
9304 mutex_unlock(&bp->link_lock);
9306 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9309 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9312 mutex_lock(&bp->link_lock);
9313 rc = bnxt_update_phy_setting(bp);
9314 mutex_unlock(&bp->link_lock);
9316 netdev_warn(bp->dev, "update phy settings retry failed\n");
9318 bp->link_info.phy_retry = false;
9319 netdev_info(bp->dev, "update phy settings retry succeeded\n");
9322 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9323 mutex_lock(&bp->link_lock);
9324 bnxt_get_port_module_status(bp);
9325 mutex_unlock(&bp->link_lock);
9328 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9329 bnxt_tc_flow_stats_work(bp);
9331 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9332 bnxt_chk_missed_irq(bp);
9334 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
9335 * must be the last functions to be called before exiting.
9337 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9338 bnxt_reset(bp, false);
9340 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9341 bnxt_reset(bp, true);
9343 smp_mb__before_atomic();
9344 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9347 /* Under rtnl_lock */
9348 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9351 int max_rx, max_tx, tx_sets = 1;
9352 int tx_rings_needed, stats;
9359 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9366 tx_rings_needed = tx * tx_sets + tx_xdp;
9367 if (max_tx < tx_rings_needed)
9371 if (bp->flags & BNXT_FLAG_RFS)
9374 if (bp->flags & BNXT_FLAG_AGG_RINGS)
9376 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9378 if (BNXT_NEW_RM(bp)) {
9379 cp += bnxt_get_ulp_msix_num(bp);
9380 stats += bnxt_get_ulp_stat_ctxs(bp);
9382 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9386 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9389 pci_iounmap(pdev, bp->bar2);
9394 pci_iounmap(pdev, bp->bar1);
9399 pci_iounmap(pdev, bp->bar0);
9404 static void bnxt_cleanup_pci(struct bnxt *bp)
9406 bnxt_unmap_bars(bp, bp->pdev);
9407 pci_release_regions(bp->pdev);
9408 pci_disable_device(bp->pdev);
9411 static void bnxt_init_dflt_coal(struct bnxt *bp)
9413 struct bnxt_coal *coal;
9415 /* Tick values in micro seconds.
9416 * 1 coal_buf x bufs_per_record = 1 completion record.
9418 coal = &bp->rx_coal;
9419 coal->coal_ticks = 10;
9420 coal->coal_bufs = 30;
9421 coal->coal_ticks_irq = 1;
9422 coal->coal_bufs_irq = 2;
9423 coal->idle_thresh = 50;
9424 coal->bufs_per_record = 2;
9425 coal->budget = 64; /* NAPI budget */
9427 coal = &bp->tx_coal;
9428 coal->coal_ticks = 28;
9429 coal->coal_bufs = 30;
9430 coal->coal_ticks_irq = 2;
9431 coal->coal_bufs_irq = 2;
9432 coal->bufs_per_record = 1;
9434 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9437 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9440 struct bnxt *bp = netdev_priv(dev);
9442 SET_NETDEV_DEV(dev, &pdev->dev);
9444 /* enable device (incl. PCI PM wakeup), and bus-mastering */
9445 rc = pci_enable_device(pdev);
9447 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9451 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9453 "Cannot find PCI device base address, aborting\n");
9455 goto init_err_disable;
9458 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9460 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9461 goto init_err_disable;
9464 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9465 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9466 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9467 goto init_err_disable;
9470 pci_set_master(pdev);
9475 bp->bar0 = pci_ioremap_bar(pdev, 0);
9477 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9479 goto init_err_release;
9482 bp->bar1 = pci_ioremap_bar(pdev, 2);
9484 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9486 goto init_err_release;
9489 bp->bar2 = pci_ioremap_bar(pdev, 4);
9491 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9493 goto init_err_release;
9496 pci_enable_pcie_error_reporting(pdev);
9498 INIT_WORK(&bp->sp_task, bnxt_sp_task);
9500 spin_lock_init(&bp->ntp_fltr_lock);
9501 #if BITS_PER_LONG == 32
9502 spin_lock_init(&bp->db_lock);
9505 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9506 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9508 bnxt_init_dflt_coal(bp);
9510 timer_setup(&bp->timer, bnxt_timer, 0);
9511 bp->current_interval = BNXT_TIMER_INTERVAL;
9513 clear_bit(BNXT_STATE_OPEN, &bp->state);
9517 bnxt_unmap_bars(bp, pdev);
9518 pci_release_regions(pdev);
9521 pci_disable_device(pdev);
9527 /* rtnl_lock held */
9528 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9530 struct sockaddr *addr = p;
9531 struct bnxt *bp = netdev_priv(dev);
9534 if (!is_valid_ether_addr(addr->sa_data))
9535 return -EADDRNOTAVAIL;
9537 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9540 rc = bnxt_approve_mac(bp, addr->sa_data, true);
9544 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9545 if (netif_running(dev)) {
9546 bnxt_close_nic(bp, false, false);
9547 rc = bnxt_open_nic(bp, false, false);
9553 /* rtnl_lock held */
9554 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9556 struct bnxt *bp = netdev_priv(dev);
9558 if (netif_running(dev))
9559 bnxt_close_nic(bp, false, false);
9562 bnxt_set_ring_params(bp);
9564 if (netif_running(dev))
9565 return bnxt_open_nic(bp, false, false);
9570 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9572 struct bnxt *bp = netdev_priv(dev);
9576 if (tc > bp->max_tc) {
9577 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9582 if (netdev_get_num_tc(dev) == tc)
9585 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9588 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9589 sh, tc, bp->tx_nr_rings_xdp);
9593 /* Needs to close the device and do hw resource re-allocations */
9594 if (netif_running(bp->dev))
9595 bnxt_close_nic(bp, true, false);
9598 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9599 netdev_set_num_tc(dev, tc);
9601 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9602 netdev_reset_tc(dev);
9604 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9605 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9606 bp->tx_nr_rings + bp->rx_nr_rings;
9608 if (netif_running(bp->dev))
9609 return bnxt_open_nic(bp, true, false);
9614 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9617 struct bnxt *bp = cb_priv;
9619 if (!bnxt_tc_flower_enabled(bp) ||
9620 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9624 case TC_SETUP_CLSFLOWER:
9625 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9631 static int bnxt_setup_tc_block(struct net_device *dev,
9632 struct tc_block_offload *f)
9634 struct bnxt *bp = netdev_priv(dev);
9636 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9639 switch (f->command) {
9641 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9643 case TC_BLOCK_UNBIND:
9644 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9651 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9655 case TC_SETUP_BLOCK:
9656 return bnxt_setup_tc_block(dev, type_data);
9657 case TC_SETUP_QDISC_MQPRIO: {
9658 struct tc_mqprio_qopt *mqprio = type_data;
9660 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9662 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9669 #ifdef CONFIG_RFS_ACCEL
9670 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9671 struct bnxt_ntuple_filter *f2)
9673 struct flow_keys *keys1 = &f1->fkeys;
9674 struct flow_keys *keys2 = &f2->fkeys;
9676 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9677 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9678 keys1->ports.ports == keys2->ports.ports &&
9679 keys1->basic.ip_proto == keys2->basic.ip_proto &&
9680 keys1->basic.n_proto == keys2->basic.n_proto &&
9681 keys1->control.flags == keys2->control.flags &&
9682 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9683 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9689 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9690 u16 rxq_index, u32 flow_id)
9692 struct bnxt *bp = netdev_priv(dev);
9693 struct bnxt_ntuple_filter *fltr, *new_fltr;
9694 struct flow_keys *fkeys;
9695 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9696 int rc = 0, idx, bit_id, l2_idx = 0;
9697 struct hlist_head *head;
9699 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9700 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9703 netif_addr_lock_bh(dev);
9704 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9705 if (ether_addr_equal(eth->h_dest,
9706 vnic->uc_list + off)) {
9711 netif_addr_unlock_bh(dev);
9715 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9719 fkeys = &new_fltr->fkeys;
9720 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9721 rc = -EPROTONOSUPPORT;
9725 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9726 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9727 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9728 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9729 rc = -EPROTONOSUPPORT;
9732 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9733 bp->hwrm_spec_code < 0x10601) {
9734 rc = -EPROTONOSUPPORT;
9737 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9738 bp->hwrm_spec_code < 0x10601) {
9739 rc = -EPROTONOSUPPORT;
9743 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
9744 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9746 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9747 head = &bp->ntp_fltr_hash_tbl[idx];
9749 hlist_for_each_entry_rcu(fltr, head, hash) {
9750 if (bnxt_fltr_match(fltr, new_fltr)) {
9758 spin_lock_bh(&bp->ntp_fltr_lock);
9759 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9760 BNXT_NTP_FLTR_MAX_FLTR, 0);
9762 spin_unlock_bh(&bp->ntp_fltr_lock);
9767 new_fltr->sw_id = (u16)bit_id;
9768 new_fltr->flow_id = flow_id;
9769 new_fltr->l2_fltr_idx = l2_idx;
9770 new_fltr->rxq = rxq_index;
9771 hlist_add_head_rcu(&new_fltr->hash, head);
9772 bp->ntp_fltr_count++;
9773 spin_unlock_bh(&bp->ntp_fltr_lock);
9775 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
9776 bnxt_queue_sp_work(bp);
9778 return new_fltr->sw_id;
9785 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9789 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
9790 struct hlist_head *head;
9791 struct hlist_node *tmp;
9792 struct bnxt_ntuple_filter *fltr;
9795 head = &bp->ntp_fltr_hash_tbl[i];
9796 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
9799 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
9800 if (rps_may_expire_flow(bp->dev, fltr->rxq,
9803 bnxt_hwrm_cfa_ntuple_filter_free(bp,
9808 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
9813 set_bit(BNXT_FLTR_VALID, &fltr->state);
9817 spin_lock_bh(&bp->ntp_fltr_lock);
9818 hlist_del_rcu(&fltr->hash);
9819 bp->ntp_fltr_count--;
9820 spin_unlock_bh(&bp->ntp_fltr_lock);
9822 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
9827 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
9828 netdev_info(bp->dev, "Receive PF driver unload event!");
9833 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
9837 #endif /* CONFIG_RFS_ACCEL */
9839 static void bnxt_udp_tunnel_add(struct net_device *dev,
9840 struct udp_tunnel_info *ti)
9842 struct bnxt *bp = netdev_priv(dev);
9844 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9847 if (!netif_running(dev))
9851 case UDP_TUNNEL_TYPE_VXLAN:
9852 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
9855 bp->vxlan_port_cnt++;
9856 if (bp->vxlan_port_cnt == 1) {
9857 bp->vxlan_port = ti->port;
9858 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
9859 bnxt_queue_sp_work(bp);
9862 case UDP_TUNNEL_TYPE_GENEVE:
9863 if (bp->nge_port_cnt && bp->nge_port != ti->port)
9867 if (bp->nge_port_cnt == 1) {
9868 bp->nge_port = ti->port;
9869 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
9876 bnxt_queue_sp_work(bp);
9879 static void bnxt_udp_tunnel_del(struct net_device *dev,
9880 struct udp_tunnel_info *ti)
9882 struct bnxt *bp = netdev_priv(dev);
9884 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
9887 if (!netif_running(dev))
9891 case UDP_TUNNEL_TYPE_VXLAN:
9892 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
9894 bp->vxlan_port_cnt--;
9896 if (bp->vxlan_port_cnt != 0)
9899 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
9901 case UDP_TUNNEL_TYPE_GENEVE:
9902 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
9906 if (bp->nge_port_cnt != 0)
9909 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
9915 bnxt_queue_sp_work(bp);
9918 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9919 struct net_device *dev, u32 filter_mask,
9922 struct bnxt *bp = netdev_priv(dev);
9924 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
9925 nlflags, filter_mask, NULL);
9928 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
9929 u16 flags, struct netlink_ext_ack *extack)
9931 struct bnxt *bp = netdev_priv(dev);
9932 struct nlattr *attr, *br_spec;
9935 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
9938 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9942 nla_for_each_nested(attr, br_spec, rem) {
9945 if (nla_type(attr) != IFLA_BRIDGE_MODE)
9948 if (nla_len(attr) < sizeof(mode))
9951 mode = nla_get_u16(attr);
9952 if (mode == bp->br_mode)
9955 rc = bnxt_hwrm_set_br_mode(bp, mode);
9963 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
9966 struct bnxt *bp = netdev_priv(dev);
9969 /* The PF and it's VF-reps only support the switchdev framework */
9973 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
9980 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
9982 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
9985 /* The PF and it's VF-reps only support the switchdev framework */
9990 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
9991 attr->u.ppid.id_len = sizeof(bp->switch_id);
9992 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
10000 static int bnxt_swdev_port_attr_get(struct net_device *dev,
10001 struct switchdev_attr *attr)
10003 return bnxt_port_attr_get(netdev_priv(dev), attr);
10006 static const struct switchdev_ops bnxt_switchdev_ops = {
10007 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
10010 static const struct net_device_ops bnxt_netdev_ops = {
10011 .ndo_open = bnxt_open,
10012 .ndo_start_xmit = bnxt_start_xmit,
10013 .ndo_stop = bnxt_close,
10014 .ndo_get_stats64 = bnxt_get_stats64,
10015 .ndo_set_rx_mode = bnxt_set_rx_mode,
10016 .ndo_do_ioctl = bnxt_ioctl,
10017 .ndo_validate_addr = eth_validate_addr,
10018 .ndo_set_mac_address = bnxt_change_mac_addr,
10019 .ndo_change_mtu = bnxt_change_mtu,
10020 .ndo_fix_features = bnxt_fix_features,
10021 .ndo_set_features = bnxt_set_features,
10022 .ndo_tx_timeout = bnxt_tx_timeout,
10023 #ifdef CONFIG_BNXT_SRIOV
10024 .ndo_get_vf_config = bnxt_get_vf_config,
10025 .ndo_set_vf_mac = bnxt_set_vf_mac,
10026 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
10027 .ndo_set_vf_rate = bnxt_set_vf_bw,
10028 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
10029 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
10030 .ndo_set_vf_trust = bnxt_set_vf_trust,
10032 .ndo_setup_tc = bnxt_setup_tc,
10033 #ifdef CONFIG_RFS_ACCEL
10034 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
10036 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
10037 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
10038 .ndo_bpf = bnxt_xdp,
10039 .ndo_bridge_getlink = bnxt_bridge_getlink,
10040 .ndo_bridge_setlink = bnxt_bridge_setlink,
10041 .ndo_get_phys_port_name = bnxt_get_phys_port_name
10044 static void bnxt_remove_one(struct pci_dev *pdev)
10046 struct net_device *dev = pci_get_drvdata(pdev);
10047 struct bnxt *bp = netdev_priv(dev);
10050 bnxt_sriov_disable(bp);
10051 bnxt_dl_unregister(bp);
10054 pci_disable_pcie_error_reporting(pdev);
10055 unregister_netdev(dev);
10056 bnxt_shutdown_tc(bp);
10057 bnxt_cancel_sp_work(bp);
10060 bnxt_clear_int_mode(bp);
10061 bnxt_hwrm_func_drv_unrgtr(bp);
10062 bnxt_free_hwrm_resources(bp);
10063 bnxt_free_hwrm_short_cmd_req(bp);
10064 bnxt_ethtool_free(bp);
10068 bnxt_free_ctx_mem(bp);
10071 bnxt_cleanup_pci(bp);
10072 bnxt_free_port_stats(bp);
10076 static int bnxt_probe_phy(struct bnxt *bp)
10079 struct bnxt_link_info *link_info = &bp->link_info;
10081 rc = bnxt_hwrm_phy_qcaps(bp);
10083 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10087 mutex_init(&bp->link_lock);
10089 rc = bnxt_update_link(bp, false);
10091 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10096 /* Older firmware does not have supported_auto_speeds, so assume
10097 * that all supported speeds can be autonegotiated.
10099 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10100 link_info->support_auto_speeds = link_info->support_speeds;
10102 /*initialize the ethool setting copy with NVM settings */
10103 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10104 link_info->autoneg = BNXT_AUTONEG_SPEED;
10105 if (bp->hwrm_spec_code >= 0x10201) {
10106 if (link_info->auto_pause_setting &
10107 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10108 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10110 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10112 link_info->advertising = link_info->auto_link_speeds;
10114 link_info->req_link_speed = link_info->force_link_speed;
10115 link_info->req_duplex = link_info->duplex_setting;
10117 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10118 link_info->req_flow_ctrl =
10119 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10121 link_info->req_flow_ctrl = link_info->force_pause_setting;
10125 static int bnxt_get_max_irq(struct pci_dev *pdev)
10129 if (!pdev->msix_cap)
10132 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10133 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10136 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10139 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10140 int max_ring_grps = 0, max_irq;
10142 *max_tx = hw_resc->max_tx_rings;
10143 *max_rx = hw_resc->max_rx_rings;
10144 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10145 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10146 bnxt_get_ulp_msix_num(bp),
10147 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10148 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10149 *max_cp = min_t(int, *max_cp, max_irq);
10150 max_ring_grps = hw_resc->max_hw_ring_grps;
10151 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10155 if (bp->flags & BNXT_FLAG_AGG_RINGS)
10157 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10158 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10159 /* On P5 chips, max_cp output param should be available NQs */
10162 *max_rx = min_t(int, *max_rx, max_ring_grps);
10165 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10169 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10172 if (!rx || !tx || !cp)
10175 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10178 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10183 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10184 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10185 /* Not enough rings, try disabling agg rings. */
10186 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10187 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10189 /* set BNXT_FLAG_AGG_RINGS back for consistency */
10190 bp->flags |= BNXT_FLAG_AGG_RINGS;
10193 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10194 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10195 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10196 bnxt_set_ring_params(bp);
10199 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10200 int max_cp, max_stat, max_irq;
10202 /* Reserve minimum resources for RoCE */
10203 max_cp = bnxt_get_max_func_cp_rings(bp);
10204 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10205 max_irq = bnxt_get_max_func_irqs(bp);
10206 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10207 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10208 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10211 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10212 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10213 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10214 max_cp = min_t(int, max_cp, max_irq);
10215 max_cp = min_t(int, max_cp, max_stat);
10216 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10223 /* In initial default shared ring setting, each shared ring must have a
10226 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10228 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10229 bp->rx_nr_rings = bp->cp_nr_rings;
10230 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10231 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10234 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10236 int dflt_rings, max_rx_rings, max_tx_rings, rc;
10238 if (!bnxt_can_reserve_rings(bp))
10242 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10243 dflt_rings = netif_get_num_default_rss_queues();
10244 /* Reduce default rings on multi-port cards so that total default
10245 * rings do not exceed CPU count.
10247 if (bp->port_count > 1) {
10249 max_t(int, num_online_cpus() / bp->port_count, 1);
10251 dflt_rings = min_t(int, dflt_rings, max_rings);
10253 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10256 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10257 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10259 bnxt_trim_dflt_sh_rings(bp);
10261 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10262 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10264 rc = __bnxt_reserve_rings(bp);
10266 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10267 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10269 bnxt_trim_dflt_sh_rings(bp);
10271 /* Rings may have been trimmed, re-reserve the trimmed rings. */
10272 if (bnxt_need_reserve_rings(bp)) {
10273 rc = __bnxt_reserve_rings(bp);
10275 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10276 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10278 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10285 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10289 if (bp->tx_nr_rings)
10292 bnxt_ulp_irq_stop(bp);
10293 bnxt_clear_int_mode(bp);
10294 rc = bnxt_set_dflt_rings(bp, true);
10296 netdev_err(bp->dev, "Not enough rings available.\n");
10297 goto init_dflt_ring_err;
10299 rc = bnxt_init_int_mode(bp);
10301 goto init_dflt_ring_err;
10303 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10304 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10305 bp->flags |= BNXT_FLAG_RFS;
10306 bp->dev->features |= NETIF_F_NTUPLE;
10308 init_dflt_ring_err:
10309 bnxt_ulp_irq_restart(bp, rc);
10313 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10318 bnxt_hwrm_func_qcaps(bp);
10320 if (netif_running(bp->dev))
10321 __bnxt_close_nic(bp, true, false);
10323 bnxt_ulp_irq_stop(bp);
10324 bnxt_clear_int_mode(bp);
10325 rc = bnxt_init_int_mode(bp);
10326 bnxt_ulp_irq_restart(bp, rc);
10328 if (netif_running(bp->dev)) {
10330 dev_close(bp->dev);
10332 rc = bnxt_open_nic(bp, true, false);
10338 static int bnxt_init_mac_addr(struct bnxt *bp)
10343 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10345 #ifdef CONFIG_BNXT_SRIOV
10346 struct bnxt_vf_info *vf = &bp->vf;
10347 bool strict_approval = true;
10349 if (is_valid_ether_addr(vf->mac_addr)) {
10350 /* overwrite netdev dev_addr with admin VF MAC */
10351 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10352 /* Older PF driver or firmware may not approve this
10355 strict_approval = false;
10357 eth_hw_addr_random(bp->dev);
10359 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10365 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10367 static int version_printed;
10368 struct net_device *dev;
10372 if (pci_is_bridge(pdev))
10375 if (version_printed++ == 0)
10376 pr_info("%s", version);
10378 max_irqs = bnxt_get_max_irq(pdev);
10379 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10383 bp = netdev_priv(dev);
10384 bnxt_set_max_func_irqs(bp, max_irqs);
10386 if (bnxt_vf_pciid(ent->driver_data))
10387 bp->flags |= BNXT_FLAG_VF;
10389 if (pdev->msix_cap)
10390 bp->flags |= BNXT_FLAG_MSIX_CAP;
10392 rc = bnxt_init_board(pdev, dev);
10394 goto init_err_free;
10396 dev->netdev_ops = &bnxt_netdev_ops;
10397 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10398 dev->ethtool_ops = &bnxt_ethtool_ops;
10399 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
10400 pci_set_drvdata(pdev, dev);
10402 rc = bnxt_alloc_hwrm_resources(bp);
10404 goto init_err_pci_clean;
10406 mutex_init(&bp->hwrm_cmd_lock);
10407 rc = bnxt_hwrm_ver_get(bp);
10409 goto init_err_pci_clean;
10411 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10412 rc = bnxt_alloc_kong_hwrm_resources(bp);
10414 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10417 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10418 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10419 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10421 goto init_err_pci_clean;
10424 if (BNXT_CHIP_P5(bp))
10425 bp->flags |= BNXT_FLAG_CHIP_P5;
10427 rc = bnxt_hwrm_func_reset(bp);
10429 goto init_err_pci_clean;
10431 bnxt_hwrm_fw_set_time(bp);
10433 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10434 NETIF_F_TSO | NETIF_F_TSO6 |
10435 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10436 NETIF_F_GSO_IPXIP4 |
10437 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10438 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10439 NETIF_F_RXCSUM | NETIF_F_GRO;
10441 if (BNXT_SUPPORTS_TPA(bp))
10442 dev->hw_features |= NETIF_F_LRO;
10444 dev->hw_enc_features =
10445 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10446 NETIF_F_TSO | NETIF_F_TSO6 |
10447 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10448 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10449 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10450 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10451 NETIF_F_GSO_GRE_CSUM;
10452 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10453 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10454 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10455 if (BNXT_SUPPORTS_TPA(bp))
10456 dev->hw_features |= NETIF_F_GRO_HW;
10457 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10458 if (dev->features & NETIF_F_GRO_HW)
10459 dev->features &= ~NETIF_F_LRO;
10460 dev->priv_flags |= IFF_UNICAST_FLT;
10462 #ifdef CONFIG_BNXT_SRIOV
10463 init_waitqueue_head(&bp->sriov_cfg_wait);
10464 mutex_init(&bp->sriov_lock);
10466 if (BNXT_SUPPORTS_TPA(bp)) {
10467 bp->gro_func = bnxt_gro_func_5730x;
10468 if (BNXT_CHIP_P4(bp))
10469 bp->gro_func = bnxt_gro_func_5731x;
10471 if (!BNXT_CHIP_P4_PLUS(bp))
10472 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10474 rc = bnxt_hwrm_func_drv_rgtr(bp);
10476 goto init_err_pci_clean;
10478 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10480 goto init_err_pci_clean;
10482 bp->ulp_probe = bnxt_ulp_probe;
10484 rc = bnxt_hwrm_queue_qportcfg(bp);
10486 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10489 goto init_err_pci_clean;
10491 /* Get the MAX capabilities for this function */
10492 rc = bnxt_hwrm_func_qcaps(bp);
10494 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10497 goto init_err_pci_clean;
10499 rc = bnxt_init_mac_addr(bp);
10501 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10502 rc = -EADDRNOTAVAIL;
10503 goto init_err_pci_clean;
10506 bnxt_hwrm_func_qcfg(bp);
10507 bnxt_hwrm_vnic_qcaps(bp);
10508 bnxt_hwrm_port_led_qcaps(bp);
10509 bnxt_ethtool_init(bp);
10512 /* MTU range: 60 - FW defined max */
10513 dev->min_mtu = ETH_ZLEN;
10514 dev->max_mtu = bp->max_mtu;
10516 rc = bnxt_probe_phy(bp);
10518 goto init_err_pci_clean;
10520 bnxt_set_rx_skb_mode(bp, false);
10521 bnxt_set_tpa_flags(bp);
10522 bnxt_set_ring_params(bp);
10523 rc = bnxt_set_dflt_rings(bp, true);
10525 netdev_err(bp->dev, "Not enough rings available.\n");
10527 goto init_err_pci_clean;
10530 /* Default RSS hash cfg. */
10531 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10532 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10533 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10534 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10535 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10536 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10537 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10538 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10541 if (bnxt_rfs_supported(bp)) {
10542 dev->hw_features |= NETIF_F_NTUPLE;
10543 if (bnxt_rfs_capable(bp)) {
10544 bp->flags |= BNXT_FLAG_RFS;
10545 dev->features |= NETIF_F_NTUPLE;
10549 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10550 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10552 rc = bnxt_init_int_mode(bp);
10554 goto init_err_pci_clean;
10556 /* No TC has been set yet and rings may have been trimmed due to
10557 * limited MSIX, so we re-initialize the TX rings per TC.
10559 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10561 bnxt_get_wol_settings(bp);
10562 if (bp->flags & BNXT_FLAG_WOL_CAP)
10563 device_set_wakeup_enable(&pdev->dev, bp->wol);
10565 device_set_wakeup_capable(&pdev->dev, false);
10567 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10569 bnxt_hwrm_coal_params_qcaps(bp);
10574 create_singlethread_workqueue("bnxt_pf_wq");
10576 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10577 goto init_err_pci_clean;
10583 rc = register_netdev(dev);
10585 goto init_err_cleanup_tc;
10588 bnxt_dl_register(bp);
10590 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10591 board_info[ent->driver_data].name,
10592 (long)pci_resource_start(pdev, 0), dev->dev_addr);
10593 pcie_print_link_status(pdev);
10597 init_err_cleanup_tc:
10598 bnxt_shutdown_tc(bp);
10599 bnxt_clear_int_mode(bp);
10601 init_err_pci_clean:
10602 bnxt_free_hwrm_resources(bp);
10603 bnxt_free_ctx_mem(bp);
10606 bnxt_cleanup_pci(bp);
10613 static void bnxt_shutdown(struct pci_dev *pdev)
10615 struct net_device *dev = pci_get_drvdata(pdev);
10622 bp = netdev_priv(dev);
10624 goto shutdown_exit;
10626 if (netif_running(dev))
10629 bnxt_ulp_shutdown(bp);
10631 if (system_state == SYSTEM_POWER_OFF) {
10632 bnxt_clear_int_mode(bp);
10633 pci_wake_from_d3(pdev, bp->wol);
10634 pci_set_power_state(pdev, PCI_D3hot);
10641 #ifdef CONFIG_PM_SLEEP
10642 static int bnxt_suspend(struct device *device)
10644 struct pci_dev *pdev = to_pci_dev(device);
10645 struct net_device *dev = pci_get_drvdata(pdev);
10646 struct bnxt *bp = netdev_priv(dev);
10650 if (netif_running(dev)) {
10651 netif_device_detach(dev);
10652 rc = bnxt_close(dev);
10654 bnxt_hwrm_func_drv_unrgtr(bp);
10659 static int bnxt_resume(struct device *device)
10661 struct pci_dev *pdev = to_pci_dev(device);
10662 struct net_device *dev = pci_get_drvdata(pdev);
10663 struct bnxt *bp = netdev_priv(dev);
10667 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10671 rc = bnxt_hwrm_func_reset(bp);
10676 bnxt_get_wol_settings(bp);
10677 if (netif_running(dev)) {
10678 rc = bnxt_open(dev);
10680 netif_device_attach(dev);
10688 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10689 #define BNXT_PM_OPS (&bnxt_pm_ops)
10693 #define BNXT_PM_OPS NULL
10695 #endif /* CONFIG_PM_SLEEP */
10698 * bnxt_io_error_detected - called when PCI error is detected
10699 * @pdev: Pointer to PCI device
10700 * @state: The current pci connection state
10702 * This function is called after a PCI bus error affecting
10703 * this device has been detected.
10705 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10706 pci_channel_state_t state)
10708 struct net_device *netdev = pci_get_drvdata(pdev);
10709 struct bnxt *bp = netdev_priv(netdev);
10711 netdev_info(netdev, "PCI I/O error detected\n");
10714 netif_device_detach(netdev);
10718 if (state == pci_channel_io_perm_failure) {
10720 return PCI_ERS_RESULT_DISCONNECT;
10723 if (netif_running(netdev))
10724 bnxt_close(netdev);
10726 pci_disable_device(pdev);
10729 /* Request a slot slot reset. */
10730 return PCI_ERS_RESULT_NEED_RESET;
10734 * bnxt_io_slot_reset - called after the pci bus has been reset.
10735 * @pdev: Pointer to PCI device
10737 * Restart the card from scratch, as if from a cold-boot.
10738 * At this point, the card has exprienced a hard reset,
10739 * followed by fixups by BIOS, and has its config space
10740 * set up identically to what it was at cold boot.
10742 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10744 struct net_device *netdev = pci_get_drvdata(pdev);
10745 struct bnxt *bp = netdev_priv(netdev);
10747 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10749 netdev_info(bp->dev, "PCI Slot Reset\n");
10753 if (pci_enable_device(pdev)) {
10754 dev_err(&pdev->dev,
10755 "Cannot re-enable PCI device after reset.\n");
10757 pci_set_master(pdev);
10759 err = bnxt_hwrm_func_reset(bp);
10760 if (!err && netif_running(netdev))
10761 err = bnxt_open(netdev);
10764 result = PCI_ERS_RESULT_RECOVERED;
10765 bnxt_ulp_start(bp);
10769 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
10774 return PCI_ERS_RESULT_RECOVERED;
10778 * bnxt_io_resume - called when traffic can start flowing again.
10779 * @pdev: Pointer to PCI device
10781 * This callback is called when the error recovery driver tells
10782 * us that its OK to resume normal operation.
10784 static void bnxt_io_resume(struct pci_dev *pdev)
10786 struct net_device *netdev = pci_get_drvdata(pdev);
10790 netif_device_attach(netdev);
10795 static const struct pci_error_handlers bnxt_err_handler = {
10796 .error_detected = bnxt_io_error_detected,
10797 .slot_reset = bnxt_io_slot_reset,
10798 .resume = bnxt_io_resume
10801 static struct pci_driver bnxt_pci_driver = {
10802 .name = DRV_MODULE_NAME,
10803 .id_table = bnxt_pci_tbl,
10804 .probe = bnxt_init_one,
10805 .remove = bnxt_remove_one,
10806 .shutdown = bnxt_shutdown,
10807 .driver.pm = BNXT_PM_OPS,
10808 .err_handler = &bnxt_err_handler,
10809 #if defined(CONFIG_BNXT_SRIOV)
10810 .sriov_configure = bnxt_sriov_configure,
10814 static int __init bnxt_init(void)
10817 return pci_register_driver(&bnxt_pci_driver);
10820 static void __exit bnxt_exit(void)
10822 pci_unregister_driver(&bnxt_pci_driver);
10824 destroy_workqueue(bnxt_pf_wq);
10828 module_init(bnxt_init);
10829 module_exit(bnxt_exit);