drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62 #include "bnx2x.h"
  63 #include "bnx2x_init.h"
  64 #include "bnx2x_init_ops.h"
  65 #include "bnx2x_cmn.h"
  66 #include "bnx2x_vfpf.h"
  67 #include "bnx2x_dcb.h"
  68 #include "bnx2x_sp.h"
  69 #include <linux/firmware.h>
  70 #include "bnx2x_fw_file_hdr.h"
  71 /* FW files */
  72 #define FW_FILE_VERSION                                 \
  73         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  74         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  75         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  76         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  77 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  78 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  79 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  80
  81 /* Time in jiffies before concluding the transmitter is hung */
  82 #define TX_TIMEOUT              (5*HZ)
  83
  84 static char version[] =
  85         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  86         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  87
  88 MODULE_AUTHOR("Eliezer Tamir");
  89 MODULE_DESCRIPTION("QLogic "
  90                    "BCM57710/57711/57711E/"
  91                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  92                    "57840/57840_MF Driver");
  93 MODULE_LICENSE("GPL");
  94 MODULE_VERSION(DRV_MODULE_VERSION);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  97 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  98
  99 int bnx2x_num_queues;
 100 module_param_named(num_queues, bnx2x_num_queues, int, 0444);
 101 MODULE_PARM_DESC(num_queues,
 102                  " Set number of queues (default is as a number of CPUs)");
 103
 104 static int disable_tpa;
 105 module_param(disable_tpa, int, 0444);
 106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 107
 108 static int int_mode;
 109 module_param(int_mode, int, 0444);
 110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 111                                 "(1 INT#x; 2 MSI)");
 112
 113 static int dropless_fc;
 114 module_param(dropless_fc, int, 0444);
 115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 116
 117 static int mrrs = -1;
 118 module_param(mrrs, int, 0444);
 119 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 120
 121 static int debug;
 122 module_param(debug, int, 0444);
 123 MODULE_PARM_DESC(debug, " Default debug msglevel");
 124
 125 static struct workqueue_struct *bnx2x_wq;
 126 struct workqueue_struct *bnx2x_iov_wq;
 127
 128 struct bnx2x_mac_vals {
 129         u32 xmac_addr;
 130         u32 xmac_val;
 131         u32 emac_addr;
 132         u32 emac_val;
 133         u32 umac_addr[2];
 134         u32 umac_val[2];
 135         u32 bmac_addr;
 136         u32 bmac_val[2];
 137 };
 138
 139 enum bnx2x_board_type {
 140         BCM57710 = 0,
 141         BCM57711,
 142         BCM57711E,
 143         BCM57712,
 144         BCM57712_MF,
 145         BCM57712_VF,
 146         BCM57800,
 147         BCM57800_MF,
 148         BCM57800_VF,
 149         BCM57810,
 150         BCM57810_MF,
 151         BCM57810_VF,
 152         BCM57840_4_10,
 153         BCM57840_2_20,
 154         BCM57840_MF,
 155         BCM57840_VF,
 156         BCM57811,
 157         BCM57811_MF,
 158         BCM57840_O,
 159         BCM57840_MFO,
 160         BCM57811_VF
 161 };
 162
 163 /* indexed by board_type, above */
 164 static struct {
 165         char *name;
 166 } board_info[] = {
 167         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 168         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 169         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 170         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 171         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 172         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 173         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 174         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 175         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 177         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 178         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 179         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 180         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 181         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 182         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 183         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 184         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 185         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 186         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 187         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 188 };
 189
 190 #ifndef PCI_DEVICE_ID_NX2_57710
 191 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 192 #endif
 193 #ifndef PCI_DEVICE_ID_NX2_57711
 194 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57711E
 197 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57712
 200 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 203 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 206 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57800
 209 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 212 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 215 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57810
 218 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 221 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57840_O
 224 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 227 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 230 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 233 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 236 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 239 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 242 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57811
 245 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 248 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 249 #endif
 250 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 251 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 252 #endif
 253
 254 static const struct pci_device_id bnx2x_pci_tbl[] = {
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 268         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 273         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 275         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 277         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 278         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 279         { 0 }
 280 };
 281
 282 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 283
 284 /* Global resources for unloading a previously loaded device */
 285 #define BNX2X_PREV_WAIT_NEEDED 1
 286 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 287 static LIST_HEAD(bnx2x_prev_list);
 288
 289 /* Forward declaration */
 290 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 291 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 292 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 293
 294 /****************************************************************************
 295 * General service functions
 296 ****************************************************************************/
 297
 298 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 299
 300 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 301                                        u32 addr, dma_addr_t mapping)
 302 {
 303         REG_WR(bp,  addr, U64_LO(mapping));
 304         REG_WR(bp,  addr + 4, U64_HI(mapping));
 305 }
 306
 307 static void storm_memset_spq_addr(struct bnx2x *bp,
 308                                   dma_addr_t mapping, u16 abs_fid)
 309 {
 310         u32 addr = XSEM_REG_FAST_MEMORY +
 311                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 312
 313         __storm_memset_dma_mapping(bp, addr, mapping);
 314 }
 315
 316 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 317                                   u16 pf_id)
 318 {
 319         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 324                 pf_id);
 325         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 326                 pf_id);
 327 }
 328
 329 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 330                                  u8 enable)
 331 {
 332         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 337                 enable);
 338         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 339                 enable);
 340 }
 341
 342 static void storm_memset_eq_data(struct bnx2x *bp,
 343                                  struct event_ring_data *eq_data,
 344                                 u16 pfid)
 345 {
 346         size_t size = sizeof(struct event_ring_data);
 347
 348         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 349
 350         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 351 }
 352
 353 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 354                                  u16 pfid)
 355 {
 356         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 357         REG_WR16(bp, addr, eq_prod);
 358 }
 359
 360 /* used only at init
 361  * locking is done by mcp
 362  */
 363 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 364 {
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 366         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 367         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 368                                PCICFG_VENDOR_ID_OFFSET);
 369 }
 370
 371 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 372 {
 373         u32 val;
 374
 375         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 376         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 377         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 378                                PCICFG_VENDOR_ID_OFFSET);
 379
 380         return val;
 381 }
 382
 383 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 384 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 385 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 386 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 387 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 388
 389 static void bnx2x_dp_dmae(struct bnx2x *bp,
 390                           struct dmae_command *dmae, int msglvl)
 391 {
 392         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 393         int i;
 394
 395         switch (dmae->opcode & DMAE_COMMAND_DST) {
 396         case DMAE_CMD_DST_PCI:
 397                 if (src_type == DMAE_CMD_SRC_PCI)
 398                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 399                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 400                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 401                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 402                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 403                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 404                            dmae->comp_val);
 405                 else
 406                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 407                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 408                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 409                            dmae->opcode, dmae->src_addr_lo >> 2,
 410                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 411                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 412                            dmae->comp_val);
 413                 break;
 414         case DMAE_CMD_DST_GRC:
 415                 if (src_type == DMAE_CMD_SRC_PCI)
 416                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 417                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 418                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 419                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 420                            dmae->len, dmae->dst_addr_lo >> 2,
 421                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 422                            dmae->comp_val);
 423                 else
 424                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 425                            "src [%08x], len [%d*4], dst [%08x]\n"
 426                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 427                            dmae->opcode, dmae->src_addr_lo >> 2,
 428                            dmae->len, dmae->dst_addr_lo >> 2,
 429                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 430                            dmae->comp_val);
 431                 break;
 432         default:
 433                 if (src_type == DMAE_CMD_SRC_PCI)
 434                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 435                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 436                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 437                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 438                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 439                            dmae->comp_val);
 440                 else
 441                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 442                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 443                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 444                            dmae->opcode, dmae->src_addr_lo >> 2,
 445                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 446                            dmae->comp_val);
 447                 break;
 448         }
 449
 450         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 451                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 452                    i, *(((u32 *)dmae) + i));
 453 }
 454
 455 /* copy command into DMAE command memory and set DMAE command go */
 456 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 457 {
 458         u32 cmd_offset;
 459         int i;
 460
 461         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 462         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 463                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 464         }
 465         REG_WR(bp, dmae_reg_go_c[idx], 1);
 466 }
 467
 468 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 469 {
 470         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 471                            DMAE_CMD_C_ENABLE);
 472 }
 473
 474 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 475 {
 476         return opcode & ~DMAE_CMD_SRC_RESET;
 477 }
 478
 479 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 480                              bool with_comp, u8 comp_type)
 481 {
 482         u32 opcode = 0;
 483
 484         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 485                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 486
 487         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 488
 489         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 490         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 491                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 492         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 493
 494 #ifdef __BIG_ENDIAN
 495         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 496 #else
 497         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 498 #endif
 499         if (with_comp)
 500                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 501         return opcode;
 502 }
 503
 504 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 505                                       struct dmae_command *dmae,
 506                                       u8 src_type, u8 dst_type)
 507 {
 508         memset(dmae, 0, sizeof(struct dmae_command));
 509
 510         /* set the opcode */
 511         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 512                                          true, DMAE_COMP_PCI);
 513
 514         /* fill in the completion parameters */
 515         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 516         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 517         dmae->comp_val = DMAE_COMP_VAL;
 518 }
 519
 520 /* issue a dmae command over the init-channel and wait for completion */
 521 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 522                                u32 *comp)
 523 {
 524         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 525         int rc = 0;
 526
 527         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 528
 529         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 530          * as long as this code is called both from syscall context and
 531          * from ndo_set_rx_mode() flow that may be called from BH.
 532          */
 533
 534         spin_lock_bh(&bp->dmae_lock);
 535
 536         /* reset completion */
 537         *comp = 0;
 538
 539         /* post the command on the channel used for initializations */
 540         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 541
 542         /* wait for completion */
 543         udelay(5);
 544         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 545
 546                 if (!cnt ||
 547                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 548                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 549                         BNX2X_ERR("DMAE timeout!\n");
 550                         rc = DMAE_TIMEOUT;
 551                         goto unlock;
 552                 }
 553                 cnt--;
 554                 udelay(50);
 555         }
 556         if (*comp & DMAE_PCI_ERR_FLAG) {
 557                 BNX2X_ERR("DMAE PCI error!\n");
 558                 rc = DMAE_PCI_ERROR;
 559         }
 560
 561 unlock:
 562
 563         spin_unlock_bh(&bp->dmae_lock);
 564
 565         return rc;
 566 }
 567
 568 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 569                       u32 len32)
 570 {
 571         int rc;
 572         struct dmae_command dmae;
 573
 574         if (!bp->dmae_ready) {
 575                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 576
 577                 if (CHIP_IS_E1(bp))
 578                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 579                 else
 580                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 581                 return;
 582         }
 583
 584         /* set opcode and fixed command fields */
 585         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 586
 587         /* fill in addresses and len */
 588         dmae.src_addr_lo = U64_LO(dma_addr);
 589         dmae.src_addr_hi = U64_HI(dma_addr);
 590         dmae.dst_addr_lo = dst_addr >> 2;
 591         dmae.dst_addr_hi = 0;
 592         dmae.len = len32;
 593
 594         /* issue the command and wait for completion */
 595         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 596         if (rc) {
 597                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 598 #ifdef BNX2X_STOP_ON_ERROR
 599                 bnx2x_panic();
 600 #endif
 601         }
 602 }
 603
 604 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 605 {
 606         int rc;
 607         struct dmae_command dmae;
 608
 609         if (!bp->dmae_ready) {
 610                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 611                 int i;
 612
 613                 if (CHIP_IS_E1(bp))
 614                         for (i = 0; i < len32; i++)
 615                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 616                 else
 617                         for (i = 0; i < len32; i++)
 618                                 data[i] = REG_RD(bp, src_addr + i*4);
 619
 620                 return;
 621         }
 622
 623         /* set opcode and fixed command fields */
 624         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 625
 626         /* fill in addresses and len */
 627         dmae.src_addr_lo = src_addr >> 2;
 628         dmae.src_addr_hi = 0;
 629         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 630         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 631         dmae.len = len32;
 632
 633         /* issue the command and wait for completion */
 634         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 635         if (rc) {
 636                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 637 #ifdef BNX2X_STOP_ON_ERROR
 638                 bnx2x_panic();
 639 #endif
 640         }
 641 }
 642
 643 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 644                                       u32 addr, u32 len)
 645 {
 646         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 647         int offset = 0;
 648
 649         while (len > dmae_wr_max) {
 650                 bnx2x_write_dmae(bp, phys_addr + offset,
 651                                  addr + offset, dmae_wr_max);
 652                 offset += dmae_wr_max * 4;
 653                 len -= dmae_wr_max;
 654         }
 655
 656         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 657 }
 658
 659 enum storms {
 660            XSTORM,
 661            TSTORM,
 662            CSTORM,
 663            USTORM,
 664            MAX_STORMS
 665 };
 666
 667 #define STORMS_NUM 4
 668 #define REGS_IN_ENTRY 4
 669
 670 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 671                                               enum storms storm,
 672                                               int entry)
 673 {
 674         switch (storm) {
 675         case XSTORM:
 676                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 677         case TSTORM:
 678                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 679         case CSTORM:
 680                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 681         case USTORM:
 682                 return USTORM_ASSERT_LIST_OFFSET(entry);
 683         case MAX_STORMS:
 684         default:
 685                 BNX2X_ERR("unknown storm\n");
 686         }
 687         return -EINVAL;
 688 }
 689
 690 static int bnx2x_mc_assert(struct bnx2x *bp)
 691 {
 692         char last_idx;
 693         int i, j, rc = 0;
 694         enum storms storm;
 695         u32 regs[REGS_IN_ENTRY];
 696         u32 bar_storm_intmem[STORMS_NUM] = {
 697                 BAR_XSTRORM_INTMEM,
 698                 BAR_TSTRORM_INTMEM,
 699                 BAR_CSTRORM_INTMEM,
 700                 BAR_USTRORM_INTMEM
 701         };
 702         u32 storm_assert_list_index[STORMS_NUM] = {
 703                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 704                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 705                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 706                 USTORM_ASSERT_LIST_INDEX_OFFSET
 707         };
 708         char *storms_string[STORMS_NUM] = {
 709                 "XSTORM",
 710                 "TSTORM",
 711                 "CSTORM",
 712                 "USTORM"
 713         };
 714
 715         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 716                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 717                                    storm_assert_list_index[storm]);
 718                 if (last_idx)
 719                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 720                                   storms_string[storm], last_idx);
 721
 722                 /* print the asserts */
 723                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 724                         /* read a single assert entry */
 725                         for (j = 0; j < REGS_IN_ENTRY; j++)
 726                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 727                                           bnx2x_get_assert_list_entry(bp,
 728                                                                       storm,
 729                                                                       i) +
 730                                           sizeof(u32) * j);
 731
 732                         /* log entry if it contains a valid assert */
 733                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 734                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 735                                           storms_string[storm], i, regs[3],
 736                                           regs[2], regs[1], regs[0]);
 737                                 rc++;
 738                         } else {
 739                                 break;
 740                         }
 741                 }
 742         }
 743
 744         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 745                   CHIP_IS_E1(bp) ? "everest1" :
 746                   CHIP_IS_E1H(bp) ? "everest1h" :
 747                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 748                   BCM_5710_FW_MAJOR_VERSION,
 749                   BCM_5710_FW_MINOR_VERSION,
 750                   BCM_5710_FW_REVISION_VERSION);
 751
 752         return rc;
 753 }
 754
 755 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 756 #define SCRATCH_BUFFER_SIZE(bp) \
 757         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 758
 759 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 760 {
 761         u32 addr, val;
 762         u32 mark, offset;
 763         __be32 data[9];
 764         int word;
 765         u32 trace_shmem_base;
 766         if (BP_NOMCP(bp)) {
 767                 BNX2X_ERR("NO MCP - can not dump\n");
 768                 return;
 769         }
 770         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 771                 (bp->common.bc_ver & 0xff0000) >> 16,
 772                 (bp->common.bc_ver & 0xff00) >> 8,
 773                 (bp->common.bc_ver & 0xff));
 774
 775         if (pci_channel_offline(bp->pdev)) {
 776                 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
 777                 return;
 778         }
 779
 780         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 781         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 782                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 783
 784         if (BP_PATH(bp) == 0)
 785                 trace_shmem_base = bp->common.shmem_base;
 786         else
 787                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 788
 789         /* sanity */
 790         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 791             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 792                                 SCRATCH_BUFFER_SIZE(bp)) {
 793                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 794                           trace_shmem_base);
 795                 return;
 796         }
 797
 798         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 799
 800         /* validate TRCB signature */
 801         mark = REG_RD(bp, addr);
 802         if (mark != MFW_TRACE_SIGNATURE) {
 803                 BNX2X_ERR("Trace buffer signature is missing.");
 804                 return ;
 805         }
 806
 807         /* read cyclic buffer pointer */
 808         addr += 4;
 809         mark = REG_RD(bp, addr);
 810         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 811         if (mark >= trace_shmem_base || mark < addr + 4) {
 812                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 813                 return;
 814         }
 815         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 816
 817         printk("%s", lvl);
 818
 819         /* dump buffer after the mark */
 820         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 821                 for (word = 0; word < 8; word++)
 822                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 823                 data[8] = 0x0;
 824                 pr_cont("%s", (char *)data);
 825         }
 826
 827         /* dump buffer before the mark */
 828         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 829                 for (word = 0; word < 8; word++)
 830                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 831                 data[8] = 0x0;
 832                 pr_cont("%s", (char *)data);
 833         }
 834         printk("%s" "end of fw dump\n", lvl);
 835 }
 836
 837 static void bnx2x_fw_dump(struct bnx2x *bp)
 838 {
 839         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 840 }
 841
 842 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 843 {
 844         int port = BP_PORT(bp);
 845         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 846         u32 val = REG_RD(bp, addr);
 847
 848         /* in E1 we must use only PCI configuration space to disable
 849          * MSI/MSIX capability
 850          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 851          */
 852         if (CHIP_IS_E1(bp)) {
 853                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 854                  * Use mask register to prevent from HC sending interrupts
 855                  * after we exit the function
 856                  */
 857                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 858
 859                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 860                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 861                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 862         } else
 863                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 864                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 865                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 866                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 867
 868         DP(NETIF_MSG_IFDOWN,
 869            "write %x to HC %d (addr 0x%x)\n",
 870            val, port, addr);
 871
 872         REG_WR(bp, addr, val);
 873         if (REG_RD(bp, addr) != val)
 874                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 875 }
 876
 877 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 878 {
 879         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 880
 881         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 882                  IGU_PF_CONF_INT_LINE_EN |
 883                  IGU_PF_CONF_ATTN_BIT_EN);
 884
 885         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 886
 887         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 888         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 889                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 890 }
 891
 892 static void bnx2x_int_disable(struct bnx2x *bp)
 893 {
 894         if (bp->common.int_block == INT_BLOCK_HC)
 895                 bnx2x_hc_int_disable(bp);
 896         else
 897                 bnx2x_igu_int_disable(bp);
 898 }
 899
 900 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 901 {
 902         int i;
 903         u16 j;
 904         struct hc_sp_status_block_data sp_sb_data;
 905         int func = BP_FUNC(bp);
 906 #ifdef BNX2X_STOP_ON_ERROR
 907         u16 start = 0, end = 0;
 908         u8 cos;
 909 #endif
 910         if (IS_PF(bp) && disable_int)
 911                 bnx2x_int_disable(bp);
 912
 913         bp->stats_state = STATS_STATE_DISABLED;
 914         bp->eth_stats.unrecoverable_error++;
 915         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 916
 917         BNX2X_ERR("begin crash dump -----------------\n");
 918
 919         /* Indices */
 920         /* Common */
 921         if (IS_PF(bp)) {
 922                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 923                 int data_size, cstorm_offset;
 924
 925                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 926                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 927                           bp->spq_prod_idx, bp->stats_counter);
 928                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 929                           def_sb->atten_status_block.attn_bits,
 930                           def_sb->atten_status_block.attn_bits_ack,
 931                           def_sb->atten_status_block.status_block_id,
 932                           def_sb->atten_status_block.attn_bits_index);
 933                 BNX2X_ERR("     def (");
 934                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 935                         pr_cont("0x%x%s",
 936                                 def_sb->sp_sb.index_values[i],
 937                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 938
 939                 data_size = sizeof(struct hc_sp_status_block_data) /
 940                             sizeof(u32);
 941                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 942                 for (i = 0; i < data_size; i++)
 943                         *((u32 *)&sp_sb_data + i) =
 944                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 945                                            i * sizeof(u32));
 946
 947                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 948                         sp_sb_data.igu_sb_id,
 949                         sp_sb_data.igu_seg_id,
 950                         sp_sb_data.p_func.pf_id,
 951                         sp_sb_data.p_func.vnic_id,
 952                         sp_sb_data.p_func.vf_id,
 953                         sp_sb_data.p_func.vf_valid,
 954                         sp_sb_data.state);
 955         }
 956
 957         for_each_eth_queue(bp, i) {
 958                 struct bnx2x_fastpath *fp = &bp->fp[i];
 959                 int loop;
 960                 struct hc_status_block_data_e2 sb_data_e2;
 961                 struct hc_status_block_data_e1x sb_data_e1x;
 962                 struct hc_status_block_sm  *hc_sm_p =
 963                         CHIP_IS_E1x(bp) ?
 964                         sb_data_e1x.common.state_machine :
 965                         sb_data_e2.common.state_machine;
 966                 struct hc_index_data *hc_index_p =
 967                         CHIP_IS_E1x(bp) ?
 968                         sb_data_e1x.index_data :
 969                         sb_data_e2.index_data;
 970                 u8 data_size, cos;
 971                 u32 *sb_data_p;
 972                 struct bnx2x_fp_txdata txdata;
 973
 974                 if (!bp->fp)
 975                         break;
 976
 977                 if (!fp->rx_cons_sb)
 978                         continue;
 979
 980                 /* Rx */
 981                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 982                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 983                           fp->rx_comp_prod,
 984                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 985                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 986                           fp->rx_sge_prod, fp->last_max_sge,
 987                           le16_to_cpu(fp->fp_hc_idx));
 988
 989                 /* Tx */
 990                 for_each_cos_in_tx_queue(fp, cos)
 991                 {
 992                         if (!fp->txdata_ptr[cos])
 993                                 break;
 994
 995                         txdata = *fp->txdata_ptr[cos];
 996
 997                         if (!txdata.tx_cons_sb)
 998                                 continue;
 999
1000                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1001                                   i, txdata.tx_pkt_prod,
1002                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1003                                   txdata.tx_bd_cons,
1004                                   le16_to_cpu(*txdata.tx_cons_sb));
1005                 }
1006
1007                 loop = CHIP_IS_E1x(bp) ?
1008                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1009
1010                 /* host sb data */
1011
1012                 if (IS_FCOE_FP(fp))
1013                         continue;
1014
1015                 BNX2X_ERR("     run indexes (");
1016                 for (j = 0; j < HC_SB_MAX_SM; j++)
1017                         pr_cont("0x%x%s",
1018                                fp->sb_running_index[j],
1019                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1020
1021                 BNX2X_ERR("     indexes (");
1022                 for (j = 0; j < loop; j++)
1023                         pr_cont("0x%x%s",
1024                                fp->sb_index_values[j],
1025                                (j == loop - 1) ? ")" : " ");
1026
1027                 /* VF cannot access FW refelection for status block */
1028                 if (IS_VF(bp))
1029                         continue;
1030
1031                 /* fw sb data */
1032                 data_size = CHIP_IS_E1x(bp) ?
1033                         sizeof(struct hc_status_block_data_e1x) :
1034                         sizeof(struct hc_status_block_data_e2);
1035                 data_size /= sizeof(u32);
1036                 sb_data_p = CHIP_IS_E1x(bp) ?
1037                         (u32 *)&sb_data_e1x :
1038                         (u32 *)&sb_data_e2;
1039                 /* copy sb data in here */
1040                 for (j = 0; j < data_size; j++)
1041                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1042                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1043                                 j * sizeof(u32));
1044
1045                 if (!CHIP_IS_E1x(bp)) {
1046                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1047                                 sb_data_e2.common.p_func.pf_id,
1048                                 sb_data_e2.common.p_func.vf_id,
1049                                 sb_data_e2.common.p_func.vf_valid,
1050                                 sb_data_e2.common.p_func.vnic_id,
1051                                 sb_data_e2.common.same_igu_sb_1b,
1052                                 sb_data_e2.common.state);
1053                 } else {
1054                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1055                                 sb_data_e1x.common.p_func.pf_id,
1056                                 sb_data_e1x.common.p_func.vf_id,
1057                                 sb_data_e1x.common.p_func.vf_valid,
1058                                 sb_data_e1x.common.p_func.vnic_id,
1059                                 sb_data_e1x.common.same_igu_sb_1b,
1060                                 sb_data_e1x.common.state);
1061                 }
1062
1063                 /* SB_SMs data */
1064                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1065                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1066                                 j, hc_sm_p[j].__flags,
1067                                 hc_sm_p[j].igu_sb_id,
1068                                 hc_sm_p[j].igu_seg_id,
1069                                 hc_sm_p[j].time_to_expire,
1070                                 hc_sm_p[j].timer_value);
1071                 }
1072
1073                 /* Indices data */
1074                 for (j = 0; j < loop; j++) {
1075                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1076                                hc_index_p[j].flags,
1077                                hc_index_p[j].timeout);
1078                 }
1079         }
1080
1081 #ifdef BNX2X_STOP_ON_ERROR
1082         if (IS_PF(bp)) {
1083                 /* event queue */
1084                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1085                 for (i = 0; i < NUM_EQ_DESC; i++) {
1086                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1087
1088                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1089                                   i, bp->eq_ring[i].message.opcode,
1090                                   bp->eq_ring[i].message.error);
1091                         BNX2X_ERR("data: %x %x %x\n",
1092                                   data[0], data[1], data[2]);
1093                 }
1094         }
1095
1096         /* Rings */
1097         /* Rx */
1098         for_each_valid_rx_queue(bp, i) {
1099                 struct bnx2x_fastpath *fp = &bp->fp[i];
1100
1101                 if (!bp->fp)
1102                         break;
1103
1104                 if (!fp->rx_cons_sb)
1105                         continue;
1106
1107                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1108                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1109                 for (j = start; j != end; j = RX_BD(j + 1)) {
1110                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1111                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1112
1113                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1114                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1115                 }
1116
1117                 start = RX_SGE(fp->rx_sge_prod);
1118                 end = RX_SGE(fp->last_max_sge);
1119                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1120                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1121                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1122
1123                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1124                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1125                 }
1126
1127                 start = RCQ_BD(fp->rx_comp_cons - 10);
1128                 end = RCQ_BD(fp->rx_comp_cons + 503);
1129                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1130                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1131
1132                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1133                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1134                 }
1135         }
1136
1137         /* Tx */
1138         for_each_valid_tx_queue(bp, i) {
1139                 struct bnx2x_fastpath *fp = &bp->fp[i];
1140
1141                 if (!bp->fp)
1142                         break;
1143
1144                 for_each_cos_in_tx_queue(fp, cos) {
1145                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1146
1147                         if (!fp->txdata_ptr[cos])
1148                                 break;
1149
1150                         if (!txdata->tx_cons_sb)
1151                                 continue;
1152
1153                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1154                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1155                         for (j = start; j != end; j = TX_BD(j + 1)) {
1156                                 struct sw_tx_bd *sw_bd =
1157                                         &txdata->tx_buf_ring[j];
1158
1159                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1160                                           i, cos, j, sw_bd->skb,
1161                                           sw_bd->first_bd);
1162                         }
1163
1164                         start = TX_BD(txdata->tx_bd_cons - 10);
1165                         end = TX_BD(txdata->tx_bd_cons + 254);
1166                         for (j = start; j != end; j = TX_BD(j + 1)) {
1167                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1168
1169                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1170                                           i, cos, j, tx_bd[0], tx_bd[1],
1171                                           tx_bd[2], tx_bd[3]);
1172                         }
1173                 }
1174         }
1175 #endif
1176         if (IS_PF(bp)) {
1177                 bnx2x_fw_dump(bp);
1178                 bnx2x_mc_assert(bp);
1179         }
1180         BNX2X_ERR("end crash dump -----------------\n");
1181 }
1182
1183 /*
1184  * FLR Support for E2
1185  *
1186  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1187  * initialization.
1188  */
1189 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1190 #define FLR_WAIT_INTERVAL       50      /* usec */
1191 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1192
1193 struct pbf_pN_buf_regs {
1194         int pN;
1195         u32 init_crd;
1196         u32 crd;
1197         u32 crd_freed;
1198 };
1199
1200 struct pbf_pN_cmd_regs {
1201         int pN;
1202         u32 lines_occup;
1203         u32 lines_freed;
1204 };
1205
1206 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1207                                      struct pbf_pN_buf_regs *regs,
1208                                      u32 poll_count)
1209 {
1210         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1211         u32 cur_cnt = poll_count;
1212
1213         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1214         crd = crd_start = REG_RD(bp, regs->crd);
1215         init_crd = REG_RD(bp, regs->init_crd);
1216
1217         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1218         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1219         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1220
1221         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1222                (init_crd - crd_start))) {
1223                 if (cur_cnt--) {
1224                         udelay(FLR_WAIT_INTERVAL);
1225                         crd = REG_RD(bp, regs->crd);
1226                         crd_freed = REG_RD(bp, regs->crd_freed);
1227                 } else {
1228                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1229                            regs->pN);
1230                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1231                            regs->pN, crd);
1232                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1233                            regs->pN, crd_freed);
1234                         break;
1235                 }
1236         }
1237         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1238            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1239 }
1240
1241 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1242                                      struct pbf_pN_cmd_regs *regs,
1243                                      u32 poll_count)
1244 {
1245         u32 occup, to_free, freed, freed_start;
1246         u32 cur_cnt = poll_count;
1247
1248         occup = to_free = REG_RD(bp, regs->lines_occup);
1249         freed = freed_start = REG_RD(bp, regs->lines_freed);
1250
1251         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1252         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1253
1254         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1255                 if (cur_cnt--) {
1256                         udelay(FLR_WAIT_INTERVAL);
1257                         occup = REG_RD(bp, regs->lines_occup);
1258                         freed = REG_RD(bp, regs->lines_freed);
1259                 } else {
1260                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1261                            regs->pN);
1262                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1263                            regs->pN, occup);
1264                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1265                            regs->pN, freed);
1266                         break;
1267                 }
1268         }
1269         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1270            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1271 }
1272
1273 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1274                                     u32 expected, u32 poll_count)
1275 {
1276         u32 cur_cnt = poll_count;
1277         u32 val;
1278
1279         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1280                 udelay(FLR_WAIT_INTERVAL);
1281
1282         return val;
1283 }
1284
1285 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1286                                     char *msg, u32 poll_cnt)
1287 {
1288         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1289         if (val != 0) {
1290                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1291                 return 1;
1292         }
1293         return 0;
1294 }
1295
1296 /* Common routines with VF FLR cleanup */
1297 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1298 {
1299         /* adjust polling timeout */
1300         if (CHIP_REV_IS_EMUL(bp))
1301                 return FLR_POLL_CNT * 2000;
1302
1303         if (CHIP_REV_IS_FPGA(bp))
1304                 return FLR_POLL_CNT * 120;
1305
1306         return FLR_POLL_CNT;
1307 }
1308
1309 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1310 {
1311         struct pbf_pN_cmd_regs cmd_regs[] = {
1312                 {0, (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_OCCUPANCY_Q0 :
1314                         PBF_REG_P0_TQ_OCCUPANCY,
1315                     (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1317                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1318                 {1, (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_OCCUPANCY_Q1 :
1320                         PBF_REG_P1_TQ_OCCUPANCY,
1321                     (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1323                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1324                 {4, (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1326                         PBF_REG_P4_TQ_OCCUPANCY,
1327                     (CHIP_IS_E3B0(bp)) ?
1328                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1329                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1330         };
1331
1332         struct pbf_pN_buf_regs buf_regs[] = {
1333                 {0, (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_INIT_CRD_Q0 :
1335                         PBF_REG_P0_INIT_CRD ,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_CREDIT_Q0 :
1338                         PBF_REG_P0_CREDIT,
1339                     (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1341                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1342                 {1, (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_INIT_CRD_Q1 :
1344                         PBF_REG_P1_INIT_CRD,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_CREDIT_Q1 :
1347                         PBF_REG_P1_CREDIT,
1348                     (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1350                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1351                 {4, (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_INIT_CRD_LB_Q :
1353                         PBF_REG_P4_INIT_CRD,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_CREDIT_LB_Q :
1356                         PBF_REG_P4_CREDIT,
1357                     (CHIP_IS_E3B0(bp)) ?
1358                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1359                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1360         };
1361
1362         int i;
1363
1364         /* Verify the command queues are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1366                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1367
1368         /* Verify the transmission buffers are flushed P0, P1, P4 */
1369         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1370                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1371 }
1372
1373 #define OP_GEN_PARAM(param) \
1374         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1375
1376 #define OP_GEN_TYPE(type) \
1377         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1378
1379 #define OP_GEN_AGG_VECT(index) \
1380         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1381
1382 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1383 {
1384         u32 op_gen_command = 0;
1385         u32 comp_addr = BAR_CSTRORM_INTMEM +
1386                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1387         int ret = 0;
1388
1389         if (REG_RD(bp, comp_addr)) {
1390                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1391                 return 1;
1392         }
1393
1394         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1395         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1396         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1397         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1398
1399         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1400         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1401
1402         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1403                 BNX2X_ERR("FW final cleanup did not succeed\n");
1404                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1405                    (REG_RD(bp, comp_addr)));
1406                 bnx2x_panic();
1407                 return 1;
1408         }
1409         /* Zero completion for next FLR */
1410         REG_WR(bp, comp_addr, 0);
1411
1412         return ret;
1413 }
1414
1415 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1416 {
1417         u16 status;
1418
1419         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1420         return status & PCI_EXP_DEVSTA_TRPND;
1421 }
1422
1423 /* PF FLR specific routines
1424 */
1425 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1426 {
1427         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1428         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1429                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1430                         "CFC PF usage counter timed out",
1431                         poll_cnt))
1432                 return 1;
1433
1434         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1435         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1436                         DORQ_REG_PF_USAGE_CNT,
1437                         "DQ PF usage counter timed out",
1438                         poll_cnt))
1439                 return 1;
1440
1441         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1442         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1443                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1444                         "QM PF usage counter timed out",
1445                         poll_cnt))
1446                 return 1;
1447
1448         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1449         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1450                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1451                         "Timers VNIC usage counter timed out",
1452                         poll_cnt))
1453                 return 1;
1454         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1455                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1456                         "Timers NUM_SCANS usage counter timed out",
1457                         poll_cnt))
1458                 return 1;
1459
1460         /* Wait DMAE PF usage counter to zero */
1461         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1462                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1463                         "DMAE command register timed out",
1464                         poll_cnt))
1465                 return 1;
1466
1467         return 0;
1468 }
1469
1470 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1471 {
1472         u32 val;
1473
1474         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1475         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1476
1477         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1478         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1479
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1482
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1485
1486         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1487         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1488
1489         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1491
1492         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1494
1495         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1496         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1497            val);
1498 }
1499
1500 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1501 {
1502         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1503
1504         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1505
1506         /* Re-enable PF target read access */
1507         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1508
1509         /* Poll HW usage counters */
1510         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1511         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1512                 return -EBUSY;
1513
1514         /* Zero the igu 'trailing edge' and 'leading edge' */
1515
1516         /* Send the FW cleanup command */
1517         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1518                 return -EBUSY;
1519
1520         /* ATC cleanup */
1521
1522         /* Verify TX hw is flushed */
1523         bnx2x_tx_hw_flushed(bp, poll_cnt);
1524
1525         /* Wait 100ms (not adjusted according to platform) */
1526         msleep(100);
1527
1528         /* Verify no pending pci transactions */
1529         if (bnx2x_is_pcie_pending(bp->pdev))
1530                 BNX2X_ERR("PCIE Transactions still pending\n");
1531
1532         /* Debug */
1533         bnx2x_hw_enable_status(bp);
1534
1535         /*
1536          * Master enable - Due to WB DMAE writes performed before this
1537          * register is re-initialized as part of the regular function init
1538          */
1539         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1540
1541         return 0;
1542 }
1543
1544 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1545 {
1546         int port = BP_PORT(bp);
1547         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1548         u32 val = REG_RD(bp, addr);
1549         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1550         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1551         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1552
1553         if (msix) {
1554                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1555                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1556                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1557                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1558                 if (single_msix)
1559                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1560         } else if (msi) {
1561                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1565         } else {
1566                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1567                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1568                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1569                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1570
1571                 if (!CHIP_IS_E1(bp)) {
1572                         DP(NETIF_MSG_IFUP,
1573                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1574
1575                         REG_WR(bp, addr, val);
1576
1577                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1578                 }
1579         }
1580
1581         if (CHIP_IS_E1(bp))
1582                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1583
1584         DP(NETIF_MSG_IFUP,
1585            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1586            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1587
1588         REG_WR(bp, addr, val);
1589         /*
1590          * Ensure that HC_CONFIG is written before leading/trailing edge config
1591          */
1592         barrier();
1593
1594         if (!CHIP_IS_E1(bp)) {
1595                 /* init leading/trailing edge */
1596                 if (IS_MF(bp)) {
1597                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1598                         if (bp->port.pmf)
1599                                 /* enable nig and gpio3 attention */
1600                                 val |= 0x1100;
1601                 } else
1602                         val = 0xffff;
1603
1604                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1605                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1606         }
1607 }
1608
1609 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610 {
1611         u32 val;
1612         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1615
1616         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617
1618         if (msix) {
1619                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620                          IGU_PF_CONF_SINGLE_ISR_EN);
1621                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1622                         IGU_PF_CONF_ATTN_BIT_EN);
1623
1624                 if (single_msix)
1625                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1626         } else if (msi) {
1627                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1628                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1629                         IGU_PF_CONF_ATTN_BIT_EN |
1630                         IGU_PF_CONF_SINGLE_ISR_EN);
1631         } else {
1632                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1633                 val |= (IGU_PF_CONF_INT_LINE_EN |
1634                         IGU_PF_CONF_ATTN_BIT_EN |
1635                         IGU_PF_CONF_SINGLE_ISR_EN);
1636         }
1637
1638         /* Clean previous status - need to configure igu prior to ack*/
1639         if ((!msix) || single_msix) {
1640                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641                 bnx2x_ack_int(bp);
1642         }
1643
1644         val |= IGU_PF_CONF_FUNC_EN;
1645
1646         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1647            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648
1649         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650
1651         if (val & IGU_PF_CONF_INT_LINE_EN)
1652                 pci_intx(bp->pdev, true);
1653
1654         barrier();
1655
1656         /* init leading/trailing edge */
1657         if (IS_MF(bp)) {
1658                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1659                 if (bp->port.pmf)
1660                         /* enable nig and gpio3 attention */
1661                         val |= 0x1100;
1662         } else
1663                 val = 0xffff;
1664
1665         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667 }
1668
1669 void bnx2x_int_enable(struct bnx2x *bp)
1670 {
1671         if (bp->common.int_block == INT_BLOCK_HC)
1672                 bnx2x_hc_int_enable(bp);
1673         else
1674                 bnx2x_igu_int_enable(bp);
1675 }
1676
1677 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1678 {
1679         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1680         int i, offset;
1681
1682         if (disable_hw)
1683                 /* prevent the HW from sending interrupts */
1684                 bnx2x_int_disable(bp);
1685
1686         /* make sure all ISRs are done */
1687         if (msix) {
1688                 synchronize_irq(bp->msix_table[0].vector);
1689                 offset = 1;
1690                 if (CNIC_SUPPORT(bp))
1691                         offset++;
1692                 for_each_eth_queue(bp, i)
1693                         synchronize_irq(bp->msix_table[offset++].vector);
1694         } else
1695                 synchronize_irq(bp->pdev->irq);
1696
1697         /* make sure sp_task is not running */
1698         cancel_delayed_work(&bp->sp_task);
1699         cancel_delayed_work(&bp->period_task);
1700         flush_workqueue(bnx2x_wq);
1701 }
1702
1703 /* fast path */
1704
1705 /*
1706  * General service functions
1707  */
1708
1709 /* Return true if succeeded to acquire the lock */
1710 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1711 {
1712         u32 lock_status;
1713         u32 resource_bit = (1 << resource);
1714         int func = BP_FUNC(bp);
1715         u32 hw_lock_control_reg;
1716
1717         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1718            "Trying to take a lock on resource %d\n", resource);
1719
1720         /* Validating that the resource is within range */
1721         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1722                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1723                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1724                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1725                 return false;
1726         }
1727
1728         if (func <= 5)
1729                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1730         else
1731                 hw_lock_control_reg =
1732                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1733
1734         /* Try to acquire the lock */
1735         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1736         lock_status = REG_RD(bp, hw_lock_control_reg);
1737         if (lock_status & resource_bit)
1738                 return true;
1739
1740         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1741            "Failed to get a lock on resource %d\n", resource);
1742         return false;
1743 }
1744
1745 /**
1746  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1747  *
1748  * @bp: driver handle
1749  *
1750  * Returns the recovery leader resource id according to the engine this function
1751  * belongs to. Currently only only 2 engines is supported.
1752  */
1753 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1754 {
1755         if (BP_PATH(bp))
1756                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1757         else
1758                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1759 }
1760
1761 /**
1762  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1763  *
1764  * @bp: driver handle
1765  *
1766  * Tries to acquire a leader lock for current engine.
1767  */
1768 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1769 {
1770         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1771 }
1772
1773 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1774
1775 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1776 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1777 {
1778         /* Set the interrupt occurred bit for the sp-task to recognize it
1779          * must ack the interrupt and transition according to the IGU
1780          * state machine.
1781          */
1782         atomic_set(&bp->interrupt_occurred, 1);
1783
1784         /* The sp_task must execute only after this bit
1785          * is set, otherwise we will get out of sync and miss all
1786          * further interrupts. Hence, the barrier.
1787          */
1788         smp_wmb();
1789
1790         /* schedule sp_task to workqueue */
1791         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1792 }
1793
1794 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1795 {
1796         struct bnx2x *bp = fp->bp;
1797         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1798         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1799         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1800         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1801
1802         DP(BNX2X_MSG_SP,
1803            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1804            fp->index, cid, command, bp->state,
1805            rr_cqe->ramrod_cqe.ramrod_type);
1806
1807         /* If cid is within VF range, replace the slowpath object with the
1808          * one corresponding to this VF
1809          */
1810         if (cid >= BNX2X_FIRST_VF_CID  &&
1811             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1812                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1813
1814         switch (command) {
1815         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1816                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1817                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1818                 break;
1819
1820         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1821                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1822                 drv_cmd = BNX2X_Q_CMD_SETUP;
1823                 break;
1824
1825         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1826                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1827                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1828                 break;
1829
1830         case (RAMROD_CMD_ID_ETH_HALT):
1831                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1832                 drv_cmd = BNX2X_Q_CMD_HALT;
1833                 break;
1834
1835         case (RAMROD_CMD_ID_ETH_TERMINATE):
1836                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1837                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1838                 break;
1839
1840         case (RAMROD_CMD_ID_ETH_EMPTY):
1841                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1842                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1843                 break;
1844
1845         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1846                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1847                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1848                 break;
1849
1850         default:
1851                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1852                           command, fp->index);
1853                 return;
1854         }
1855
1856         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1857             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1858                 /* q_obj->complete_cmd() failure means that this was
1859                  * an unexpected completion.
1860                  *
1861                  * In this case we don't want to increase the bp->spq_left
1862                  * because apparently we haven't sent this command the first
1863                  * place.
1864                  */
1865 #ifdef BNX2X_STOP_ON_ERROR
1866                 bnx2x_panic();
1867 #else
1868                 return;
1869 #endif
1870
1871         smp_mb__before_atomic();
1872         atomic_inc(&bp->cq_spq_left);
1873         /* push the change in bp->spq_left and towards the memory */
1874         smp_mb__after_atomic();
1875
1876         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1877
1878         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1879             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1880                 /* if Q update ramrod is completed for last Q in AFEX vif set
1881                  * flow, then ACK MCP at the end
1882                  *
1883                  * mark pending ACK to MCP bit.
1884                  * prevent case that both bits are cleared.
1885                  * At the end of load/unload driver checks that
1886                  * sp_state is cleared, and this order prevents
1887                  * races
1888                  */
1889                 smp_mb__before_atomic();
1890                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1891                 wmb();
1892                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1893                 smp_mb__after_atomic();
1894
1895                 /* schedule the sp task as mcp ack is required */
1896                 bnx2x_schedule_sp_task(bp);
1897         }
1898
1899         return;
1900 }
1901
1902 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1903 {
1904         struct bnx2x *bp = netdev_priv(dev_instance);
1905         u16 status = bnx2x_ack_int(bp);
1906         u16 mask;
1907         int i;
1908         u8 cos;
1909
1910         /* Return here if interrupt is shared and it's not for us */
1911         if (unlikely(status == 0)) {
1912                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1913                 return IRQ_NONE;
1914         }
1915         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1916
1917 #ifdef BNX2X_STOP_ON_ERROR
1918         if (unlikely(bp->panic))
1919                 return IRQ_HANDLED;
1920 #endif
1921
1922         for_each_eth_queue(bp, i) {
1923                 struct bnx2x_fastpath *fp = &bp->fp[i];
1924
1925                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1926                 if (status & mask) {
1927                         /* Handle Rx or Tx according to SB id */
1928                         for_each_cos_in_tx_queue(fp, cos)
1929                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1930                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1931                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1932                         status &= ~mask;
1933                 }
1934         }
1935
1936         if (CNIC_SUPPORT(bp)) {
1937                 mask = 0x2;
1938                 if (status & (mask | 0x1)) {
1939                         struct cnic_ops *c_ops = NULL;
1940
1941                         rcu_read_lock();
1942                         c_ops = rcu_dereference(bp->cnic_ops);
1943                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1944                                       CNIC_DRV_STATE_HANDLES_IRQ))
1945                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1946                         rcu_read_unlock();
1947
1948                         status &= ~mask;
1949                 }
1950         }
1951
1952         if (unlikely(status & 0x1)) {
1953
1954                 /* schedule sp task to perform default status block work, ack
1955                  * attentions and enable interrupts.
1956                  */
1957                 bnx2x_schedule_sp_task(bp);
1958
1959                 status &= ~0x1;
1960                 if (!status)
1961                         return IRQ_HANDLED;
1962         }
1963
1964         if (unlikely(status))
1965                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1966                    status);
1967
1968         return IRQ_HANDLED;
1969 }
1970
1971 /* Link */
1972
1973 /*
1974  * General service functions
1975  */
1976
1977 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1978 {
1979         u32 lock_status;
1980         u32 resource_bit = (1 << resource);
1981         int func = BP_FUNC(bp);
1982         u32 hw_lock_control_reg;
1983         int cnt;
1984
1985         /* Validating that the resource is within range */
1986         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1987                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1988                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1989                 return -EINVAL;
1990         }
1991
1992         if (func <= 5) {
1993                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1994         } else {
1995                 hw_lock_control_reg =
1996                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1997         }
1998
1999         /* Validating that the resource is not already taken */
2000         lock_status = REG_RD(bp, hw_lock_control_reg);
2001         if (lock_status & resource_bit) {
2002                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2003                    lock_status, resource_bit);
2004                 return -EEXIST;
2005         }
2006
2007         /* Try for 5 second every 5ms */
2008         for (cnt = 0; cnt < 1000; cnt++) {
2009                 /* Try to acquire the lock */
2010                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2011                 lock_status = REG_RD(bp, hw_lock_control_reg);
2012                 if (lock_status & resource_bit)
2013                         return 0;
2014
2015                 usleep_range(5000, 10000);
2016         }
2017         BNX2X_ERR("Timeout\n");
2018         return -EAGAIN;
2019 }
2020
2021 int bnx2x_release_leader_lock(struct bnx2x *bp)
2022 {
2023         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2024 }
2025
2026 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2027 {
2028         u32 lock_status;
2029         u32 resource_bit = (1 << resource);
2030         int func = BP_FUNC(bp);
2031         u32 hw_lock_control_reg;
2032
2033         /* Validating that the resource is within range */
2034         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2035                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2036                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2037                 return -EINVAL;
2038         }
2039
2040         if (func <= 5) {
2041                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2042         } else {
2043                 hw_lock_control_reg =
2044                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2045         }
2046
2047         /* Validating that the resource is currently taken */
2048         lock_status = REG_RD(bp, hw_lock_control_reg);
2049         if (!(lock_status & resource_bit)) {
2050                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2051                           lock_status, resource_bit);
2052                 return -EFAULT;
2053         }
2054
2055         REG_WR(bp, hw_lock_control_reg, resource_bit);
2056         return 0;
2057 }
2058
2059 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2060 {
2061         /* The GPIO should be swapped if swap register is set and active */
2062         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2063                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2064         int gpio_shift = gpio_num +
2065                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2066         u32 gpio_mask = (1 << gpio_shift);
2067         u32 gpio_reg;
2068         int value;
2069
2070         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2071                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2072                 return -EINVAL;
2073         }
2074
2075         /* read GPIO value */
2076         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2077
2078         /* get the requested pin value */
2079         if ((gpio_reg & gpio_mask) == gpio_mask)
2080                 value = 1;
2081         else
2082                 value = 0;
2083
2084         return value;
2085 }
2086
2087 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2088 {
2089         /* The GPIO should be swapped if swap register is set and active */
2090         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2091                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2092         int gpio_shift = gpio_num +
2093                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2094         u32 gpio_mask = (1 << gpio_shift);
2095         u32 gpio_reg;
2096
2097         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2098                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2099                 return -EINVAL;
2100         }
2101
2102         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2103         /* read GPIO and mask except the float bits */
2104         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2105
2106         switch (mode) {
2107         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2108                 DP(NETIF_MSG_LINK,
2109                    "Set GPIO %d (shift %d) -> output low\n",
2110                    gpio_num, gpio_shift);
2111                 /* clear FLOAT and set CLR */
2112                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2113                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2114                 break;
2115
2116         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2117                 DP(NETIF_MSG_LINK,
2118                    "Set GPIO %d (shift %d) -> output high\n",
2119                    gpio_num, gpio_shift);
2120                 /* clear FLOAT and set SET */
2121                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2122                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2123                 break;
2124
2125         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2126                 DP(NETIF_MSG_LINK,
2127                    "Set GPIO %d (shift %d) -> input\n",
2128                    gpio_num, gpio_shift);
2129                 /* set FLOAT */
2130                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2131                 break;
2132
2133         default:
2134                 break;
2135         }
2136
2137         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2138         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2139
2140         return 0;
2141 }
2142
2143 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2144 {
2145         u32 gpio_reg = 0;
2146         int rc = 0;
2147
2148         /* Any port swapping should be handled by caller. */
2149
2150         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2151         /* read GPIO and mask except the float bits */
2152         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2153         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2154         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2155         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2156
2157         switch (mode) {
2158         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2159                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2160                 /* set CLR */
2161                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2162                 break;
2163
2164         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2165                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2166                 /* set SET */
2167                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2168                 break;
2169
2170         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2171                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2172                 /* set FLOAT */
2173                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2174                 break;
2175
2176         default:
2177                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2178                 rc = -EINVAL;
2179                 break;
2180         }
2181
2182         if (rc == 0)
2183                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2184
2185         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2186
2187         return rc;
2188 }
2189
2190 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2191 {
2192         /* The GPIO should be swapped if swap register is set and active */
2193         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2194                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2195         int gpio_shift = gpio_num +
2196                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2197         u32 gpio_mask = (1 << gpio_shift);
2198         u32 gpio_reg;
2199
2200         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2201                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2202                 return -EINVAL;
2203         }
2204
2205         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2206         /* read GPIO int */
2207         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2208
2209         switch (mode) {
2210         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2211                 DP(NETIF_MSG_LINK,
2212                    "Clear GPIO INT %d (shift %d) -> output low\n",
2213                    gpio_num, gpio_shift);
2214                 /* clear SET and set CLR */
2215                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2216                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2217                 break;
2218
2219         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2220                 DP(NETIF_MSG_LINK,
2221                    "Set GPIO INT %d (shift %d) -> output high\n",
2222                    gpio_num, gpio_shift);
2223                 /* clear CLR and set SET */
2224                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2225                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2226                 break;
2227
2228         default:
2229                 break;
2230         }
2231
2232         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2233         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2234
2235         return 0;
2236 }
2237
2238 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2239 {
2240         u32 spio_reg;
2241
2242         /* Only 2 SPIOs are configurable */
2243         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2244                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2245                 return -EINVAL;
2246         }
2247
2248         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2249         /* read SPIO and mask except the float bits */
2250         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2251
2252         switch (mode) {
2253         case MISC_SPIO_OUTPUT_LOW:
2254                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2255                 /* clear FLOAT and set CLR */
2256                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2257                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2258                 break;
2259
2260         case MISC_SPIO_OUTPUT_HIGH:
2261                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2262                 /* clear FLOAT and set SET */
2263                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2264                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2265                 break;
2266
2267         case MISC_SPIO_INPUT_HI_Z:
2268                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2269                 /* set FLOAT */
2270                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2271                 break;
2272
2273         default:
2274                 break;
2275         }
2276
2277         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2278         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2279
2280         return 0;
2281 }
2282
2283 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2284 {
2285         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2286
2287         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2288                                            ADVERTISED_Pause);
2289         switch (bp->link_vars.ieee_fc &
2290                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2291         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2292                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2293                                                   ADVERTISED_Pause);
2294                 break;
2295
2296         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2297                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2298                 break;
2299
2300         default:
2301                 break;
2302         }
2303 }
2304
2305 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2306 {
2307         /* Initialize link parameters structure variables
2308          * It is recommended to turn off RX FC for jumbo frames
2309          *  for better performance
2310          */
2311         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2312                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2313         else
2314                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2315 }
2316
2317 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2318 {
2319         u32 pause_enabled = 0;
2320
2321         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2322                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2323                         pause_enabled = 1;
2324
2325                 REG_WR(bp, BAR_USTRORM_INTMEM +
2326                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2327                        pause_enabled);
2328         }
2329
2330         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2331            pause_enabled ? "enabled" : "disabled");
2332 }
2333
2334 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2335 {
2336         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2337         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2338
2339         if (!BP_NOMCP(bp)) {
2340                 bnx2x_set_requested_fc(bp);
2341                 bnx2x_acquire_phy_lock(bp);
2342
2343                 if (load_mode == LOAD_DIAG) {
2344                         struct link_params *lp = &bp->link_params;
2345                         lp->loopback_mode = LOOPBACK_XGXS;
2346                         /* Prefer doing PHY loopback at highest speed */
2347                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2348                                 if (lp->speed_cap_mask[cfx_idx] &
2349                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2350                                         lp->req_line_speed[cfx_idx] =
2351                                         SPEED_20000;
2352                                 else if (lp->speed_cap_mask[cfx_idx] &
2353                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2354                                                 lp->req_line_speed[cfx_idx] =
2355                                                 SPEED_10000;
2356                                 else
2357                                         lp->req_line_speed[cfx_idx] =
2358                                         SPEED_1000;
2359                         }
2360                 }
2361
2362                 if (load_mode == LOAD_LOOPBACK_EXT) {
2363                         struct link_params *lp = &bp->link_params;
2364                         lp->loopback_mode = LOOPBACK_EXT;
2365                 }
2366
2367                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2368
2369                 bnx2x_release_phy_lock(bp);
2370
2371                 bnx2x_init_dropless_fc(bp);
2372
2373                 bnx2x_calc_fc_adv(bp);
2374
2375                 if (bp->link_vars.link_up) {
2376                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2377                         bnx2x_link_report(bp);
2378                 }
2379                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2380                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2381                 return rc;
2382         }
2383         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2384         return -EINVAL;
2385 }
2386
2387 void bnx2x_link_set(struct bnx2x *bp)
2388 {
2389         if (!BP_NOMCP(bp)) {
2390                 bnx2x_acquire_phy_lock(bp);
2391                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2392                 bnx2x_release_phy_lock(bp);
2393
2394                 bnx2x_init_dropless_fc(bp);
2395
2396                 bnx2x_calc_fc_adv(bp);
2397         } else
2398                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2399 }
2400
2401 static void bnx2x__link_reset(struct bnx2x *bp)
2402 {
2403         if (!BP_NOMCP(bp)) {
2404                 bnx2x_acquire_phy_lock(bp);
2405                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2406                 bnx2x_release_phy_lock(bp);
2407         } else
2408                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2409 }
2410
2411 void bnx2x_force_link_reset(struct bnx2x *bp)
2412 {
2413         bnx2x_acquire_phy_lock(bp);
2414         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2415         bnx2x_release_phy_lock(bp);
2416 }
2417
2418 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2419 {
2420         u8 rc = 0;
2421
2422         if (!BP_NOMCP(bp)) {
2423                 bnx2x_acquire_phy_lock(bp);
2424                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2425                                      is_serdes);
2426                 bnx2x_release_phy_lock(bp);
2427         } else
2428                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2429
2430         return rc;
2431 }
2432
2433 /* Calculates the sum of vn_min_rates.
2434    It's needed for further normalizing of the min_rates.
2435    Returns:
2436      sum of vn_min_rates.
2437        or
2438      0 - if all the min_rates are 0.
2439      In the later case fairness algorithm should be deactivated.
2440      If not all min_rates are zero then those that are zeroes will be set to 1.
2441  */
2442 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2443                                       struct cmng_init_input *input)
2444 {
2445         int all_zero = 1;
2446         int vn;
2447
2448         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2449                 u32 vn_cfg = bp->mf_config[vn];
2450                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2451                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2452
2453                 /* Skip hidden vns */
2454                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2455                         vn_min_rate = 0;
2456                 /* If min rate is zero - set it to 1 */
2457                 else if (!vn_min_rate)
2458                         vn_min_rate = DEF_MIN_RATE;
2459                 else
2460                         all_zero = 0;
2461
2462                 input->vnic_min_rate[vn] = vn_min_rate;
2463         }
2464
2465         /* if ETS or all min rates are zeros - disable fairness */
2466         if (BNX2X_IS_ETS_ENABLED(bp)) {
2467                 input->flags.cmng_enables &=
2468                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2469                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2470         } else if (all_zero) {
2471                 input->flags.cmng_enables &=
2472                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2473                 DP(NETIF_MSG_IFUP,
2474                    "All MIN values are zeroes fairness will be disabled\n");
2475         } else
2476                 input->flags.cmng_enables |=
2477                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2478 }
2479
2480 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2481                                     struct cmng_init_input *input)
2482 {
2483         u16 vn_max_rate;
2484         u32 vn_cfg = bp->mf_config[vn];
2485
2486         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2487                 vn_max_rate = 0;
2488         else {
2489                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2490
2491                 if (IS_MF_PERCENT_BW(bp)) {
2492                         /* maxCfg in percents of linkspeed */
2493                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2494                 } else /* SD modes */
2495                         /* maxCfg is absolute in 100Mb units */
2496                         vn_max_rate = maxCfg * 100;
2497         }
2498
2499         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2500
2501         input->vnic_max_rate[vn] = vn_max_rate;
2502 }
2503
2504 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2505 {
2506         if (CHIP_REV_IS_SLOW(bp))
2507                 return CMNG_FNS_NONE;
2508         if (IS_MF(bp))
2509                 return CMNG_FNS_MINMAX;
2510
2511         return CMNG_FNS_NONE;
2512 }
2513
2514 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2515 {
2516         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2517
2518         if (BP_NOMCP(bp))
2519                 return; /* what should be the default value in this case */
2520
2521         /* For 2 port configuration the absolute function number formula
2522          * is:
2523          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2524          *
2525          *      and there are 4 functions per port
2526          *
2527          * For 4 port configuration it is
2528          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2529          *
2530          *      and there are 2 functions per port
2531          */
2532         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2533                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2534
2535                 if (func >= E1H_FUNC_MAX)
2536                         break;
2537
2538                 bp->mf_config[vn] =
2539                         MF_CFG_RD(bp, func_mf_config[func].config);
2540         }
2541         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2542                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2543                 bp->flags |= MF_FUNC_DIS;
2544         } else {
2545                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2546                 bp->flags &= ~MF_FUNC_DIS;
2547         }
2548 }
2549
2550 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2551 {
2552         struct cmng_init_input input;
2553         memset(&input, 0, sizeof(struct cmng_init_input));
2554
2555         input.port_rate = bp->link_vars.line_speed;
2556
2557         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2558                 int vn;
2559
2560                 /* read mf conf from shmem */
2561                 if (read_cfg)
2562                         bnx2x_read_mf_cfg(bp);
2563
2564                 /* vn_weight_sum and enable fairness if not 0 */
2565                 bnx2x_calc_vn_min(bp, &input);
2566
2567                 /* calculate and set min-max rate for each vn */
2568                 if (bp->port.pmf)
2569                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2570                                 bnx2x_calc_vn_max(bp, vn, &input);
2571
2572                 /* always enable rate shaping and fairness */
2573                 input.flags.cmng_enables |=
2574                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2575
2576                 bnx2x_init_cmng(&input, &bp->cmng);
2577                 return;
2578         }
2579
2580         /* rate shaping and fairness are disabled */
2581         DP(NETIF_MSG_IFUP,
2582            "rate shaping and fairness are disabled\n");
2583 }
2584
2585 static void storm_memset_cmng(struct bnx2x *bp,
2586                               struct cmng_init *cmng,
2587                               u8 port)
2588 {
2589         int vn;
2590         size_t size = sizeof(struct cmng_struct_per_port);
2591
2592         u32 addr = BAR_XSTRORM_INTMEM +
2593                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2594
2595         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2596
2597         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2598                 int func = func_by_vn(bp, vn);
2599
2600                 addr = BAR_XSTRORM_INTMEM +
2601                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2602                 size = sizeof(struct rate_shaping_vars_per_vn);
2603                 __storm_memset_struct(bp, addr, size,
2604                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2605
2606                 addr = BAR_XSTRORM_INTMEM +
2607                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2608                 size = sizeof(struct fairness_vars_per_vn);
2609                 __storm_memset_struct(bp, addr, size,
2610                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2611         }
2612 }
2613
2614 /* init cmng mode in HW according to local configuration */
2615 void bnx2x_set_local_cmng(struct bnx2x *bp)
2616 {
2617         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2618
2619         if (cmng_fns != CMNG_FNS_NONE) {
2620                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2621                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2622         } else {
2623                 /* rate shaping and fairness are disabled */
2624                 DP(NETIF_MSG_IFUP,
2625                    "single function mode without fairness\n");
2626         }
2627 }
2628
2629 /* This function is called upon link interrupt */
2630 static void bnx2x_link_attn(struct bnx2x *bp)
2631 {
2632         /* Make sure that we are synced with the current statistics */
2633         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2634
2635         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2636
2637         bnx2x_init_dropless_fc(bp);
2638
2639         if (bp->link_vars.link_up) {
2640
2641                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2642                         struct host_port_stats *pstats;
2643
2644                         pstats = bnx2x_sp(bp, port_stats);
2645                         /* reset old mac stats */
2646                         memset(&(pstats->mac_stx[0]), 0,
2647                                sizeof(struct mac_stx));
2648                 }
2649                 if (bp->state == BNX2X_STATE_OPEN)
2650                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2651         }
2652
2653         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2654                 bnx2x_set_local_cmng(bp);
2655
2656         __bnx2x_link_report(bp);
2657
2658         if (IS_MF(bp))
2659                 bnx2x_link_sync_notify(bp);
2660 }
2661
2662 void bnx2x__link_status_update(struct bnx2x *bp)
2663 {
2664         if (bp->state != BNX2X_STATE_OPEN)
2665                 return;
2666
2667         /* read updated dcb configuration */
2668         if (IS_PF(bp)) {
2669                 bnx2x_dcbx_pmf_update(bp);
2670                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2671                 if (bp->link_vars.link_up)
2672                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2673                 else
2674                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2675                         /* indicate link status */
2676                 bnx2x_link_report(bp);
2677
2678         } else { /* VF */
2679                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2680                                           SUPPORTED_10baseT_Full |
2681                                           SUPPORTED_100baseT_Half |
2682                                           SUPPORTED_100baseT_Full |
2683                                           SUPPORTED_1000baseT_Full |
2684                                           SUPPORTED_2500baseX_Full |
2685                                           SUPPORTED_10000baseT_Full |
2686                                           SUPPORTED_TP |
2687                                           SUPPORTED_FIBRE |
2688                                           SUPPORTED_Autoneg |
2689                                           SUPPORTED_Pause |
2690                                           SUPPORTED_Asym_Pause);
2691                 bp->port.advertising[0] = bp->port.supported[0];
2692
2693                 bp->link_params.bp = bp;
2694                 bp->link_params.port = BP_PORT(bp);
2695                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2696                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2697                 bp->link_params.req_line_speed[0] = SPEED_10000;
2698                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2699                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2700                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2701                 bp->link_vars.line_speed = SPEED_10000;
2702                 bp->link_vars.link_status =
2703                         (LINK_STATUS_LINK_UP |
2704                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2705                 bp->link_vars.link_up = 1;
2706                 bp->link_vars.duplex = DUPLEX_FULL;
2707                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2708                 __bnx2x_link_report(bp);
2709
2710                 bnx2x_sample_bulletin(bp);
2711
2712                 /* if bulletin board did not have an update for link status
2713                  * __bnx2x_link_report will report current status
2714                  * but it will NOT duplicate report in case of already reported
2715                  * during sampling bulletin board.
2716                  */
2717                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2718         }
2719 }
2720
2721 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2722                                   u16 vlan_val, u8 allowed_prio)
2723 {
2724         struct bnx2x_func_state_params func_params = {NULL};
2725         struct bnx2x_func_afex_update_params *f_update_params =
2726                 &func_params.params.afex_update;
2727
2728         func_params.f_obj = &bp->func_obj;
2729         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2730
2731         /* no need to wait for RAMROD completion, so don't
2732          * set RAMROD_COMP_WAIT flag
2733          */
2734
2735         f_update_params->vif_id = vifid;
2736         f_update_params->afex_default_vlan = vlan_val;
2737         f_update_params->allowed_priorities = allowed_prio;
2738
2739         /* if ramrod can not be sent, response to MCP immediately */
2740         if (bnx2x_func_state_change(bp, &func_params) < 0)
2741                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2742
2743         return 0;
2744 }
2745
2746 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2747                                           u16 vif_index, u8 func_bit_map)
2748 {
2749         struct bnx2x_func_state_params func_params = {NULL};
2750         struct bnx2x_func_afex_viflists_params *update_params =
2751                 &func_params.params.afex_viflists;
2752         int rc;
2753         u32 drv_msg_code;
2754
2755         /* validate only LIST_SET and LIST_GET are received from switch */
2756         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2757                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2758                           cmd_type);
2759
2760         func_params.f_obj = &bp->func_obj;
2761         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2762
2763         /* set parameters according to cmd_type */
2764         update_params->afex_vif_list_command = cmd_type;
2765         update_params->vif_list_index = vif_index;
2766         update_params->func_bit_map =
2767                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2768         update_params->func_to_clear = 0;
2769         drv_msg_code =
2770                 (cmd_type == VIF_LIST_RULE_GET) ?
2771                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2772                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2773
2774         /* if ramrod can not be sent, respond to MCP immediately for
2775          * SET and GET requests (other are not triggered from MCP)
2776          */
2777         rc = bnx2x_func_state_change(bp, &func_params);
2778         if (rc < 0)
2779                 bnx2x_fw_command(bp, drv_msg_code, 0);
2780
2781         return 0;
2782 }
2783
2784 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2785 {
2786         struct afex_stats afex_stats;
2787         u32 func = BP_ABS_FUNC(bp);
2788         u32 mf_config;
2789         u16 vlan_val;
2790         u32 vlan_prio;
2791         u16 vif_id;
2792         u8 allowed_prio;
2793         u8 vlan_mode;
2794         u32 addr_to_write, vifid, addrs, stats_type, i;
2795
2796         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2797                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2798                 DP(BNX2X_MSG_MCP,
2799                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2800                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2801         }
2802
2803         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2804                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2805                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2806                 DP(BNX2X_MSG_MCP,
2807                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2808                    vifid, addrs);
2809                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2810                                                addrs);
2811         }
2812
2813         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2814                 addr_to_write = SHMEM2_RD(bp,
2815                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2816                 stats_type = SHMEM2_RD(bp,
2817                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2818
2819                 DP(BNX2X_MSG_MCP,
2820                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2821                    addr_to_write);
2822
2823                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2824
2825                 /* write response to scratchpad, for MCP */
2826                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2827                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2828                                *(((u32 *)(&afex_stats))+i));
2829
2830                 /* send ack message to MCP */
2831                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2832         }
2833
2834         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2835                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2836                 bp->mf_config[BP_VN(bp)] = mf_config;
2837                 DP(BNX2X_MSG_MCP,
2838                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2839                    mf_config);
2840
2841                 /* if VIF_SET is "enabled" */
2842                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2843                         /* set rate limit directly to internal RAM */
2844                         struct cmng_init_input cmng_input;
2845                         struct rate_shaping_vars_per_vn m_rs_vn;
2846                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2847                         u32 addr = BAR_XSTRORM_INTMEM +
2848                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2849
2850                         bp->mf_config[BP_VN(bp)] = mf_config;
2851
2852                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2853                         m_rs_vn.vn_counter.rate =
2854                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2855                         m_rs_vn.vn_counter.quota =
2856                                 (m_rs_vn.vn_counter.rate *
2857                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2858
2859                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2860
2861                         /* read relevant values from mf_cfg struct in shmem */
2862                         vif_id =
2863                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2864                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2865                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2866                         vlan_val =
2867                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2868                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2869                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2870                         vlan_prio = (mf_config &
2871                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2872                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2873                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2874                         vlan_mode =
2875                                 (MF_CFG_RD(bp,
2876                                            func_mf_config[func].afex_config) &
2877                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2878                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2879                         allowed_prio =
2880                                 (MF_CFG_RD(bp,
2881                                            func_mf_config[func].afex_config) &
2882                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2883                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2884
2885                         /* send ramrod to FW, return in case of failure */
2886                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2887                                                    allowed_prio))
2888                                 return;
2889
2890                         bp->afex_def_vlan_tag = vlan_val;
2891                         bp->afex_vlan_mode = vlan_mode;
2892                 } else {
2893                         /* notify link down because BP->flags is disabled */
2894                         bnx2x_link_report(bp);
2895
2896                         /* send INVALID VIF ramrod to FW */
2897                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2898
2899                         /* Reset the default afex VLAN */
2900                         bp->afex_def_vlan_tag = -1;
2901                 }
2902         }
2903 }
2904
2905 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2906 {
2907         struct bnx2x_func_switch_update_params *switch_update_params;
2908         struct bnx2x_func_state_params func_params;
2909
2910         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2911         switch_update_params = &func_params.params.switch_update;
2912         func_params.f_obj = &bp->func_obj;
2913         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2914
2915         /* Prepare parameters for function state transitions */
2916         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2917         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
2918
2919         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2920                 int func = BP_ABS_FUNC(bp);
2921                 u32 val;
2922
2923                 /* Re-learn the S-tag from shmem */
2924                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2925                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2926                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2927                         bp->mf_ov = val;
2928                 } else {
2929                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2930                         goto fail;
2931                 }
2932
2933                 /* Configure new S-tag in LLH */
2934                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2935                        bp->mf_ov);
2936
2937                 /* Send Ramrod to update FW of change */
2938                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2939                           &switch_update_params->changes);
2940                 switch_update_params->vlan = bp->mf_ov;
2941
2942                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2943                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2944                                   bp->mf_ov);
2945                         goto fail;
2946                 } else {
2947                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2948                            bp->mf_ov);
2949                 }
2950         } else {
2951                 goto fail;
2952         }
2953
2954         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2955         return;
2956 fail:
2957         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2958 }
2959
2960 static void bnx2x_pmf_update(struct bnx2x *bp)
2961 {
2962         int port = BP_PORT(bp);
2963         u32 val;
2964
2965         bp->port.pmf = 1;
2966         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2967
2968         /*
2969          * We need the mb() to ensure the ordering between the writing to
2970          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2971          */
2972         smp_mb();
2973
2974         /* queue a periodic task */
2975         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2976
2977         bnx2x_dcbx_pmf_update(bp);
2978
2979         /* enable nig attention */
2980         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2981         if (bp->common.int_block == INT_BLOCK_HC) {
2982                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2983                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2984         } else if (!CHIP_IS_E1x(bp)) {
2985                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2986                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2987         }
2988
2989         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2990 }
2991
2992 /* end of Link */
2993
2994 /* slow path */
2995
2996 /*
2997  * General service functions
2998  */
2999
3000 /* send the MCP a request, block until there is a reply */
3001 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3002 {
3003         int mb_idx = BP_FW_MB_IDX(bp);
3004         u32 seq;
3005         u32 rc = 0;
3006         u32 cnt = 1;
3007         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3008
3009         mutex_lock(&bp->fw_mb_mutex);
3010         seq = ++bp->fw_seq;
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3012         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3013
3014         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3015                         (command | seq), param);
3016
3017         do {
3018                 /* let the FW do it's magic ... */
3019                 msleep(delay);
3020
3021                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3022
3023                 /* Give the FW up to 5 second (500*10ms) */
3024         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3025
3026         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3027            cnt*delay, rc, seq);
3028
3029         /* is this a reply to our command? */
3030         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3031                 rc &= FW_MSG_CODE_MASK;
3032         else {
3033                 /* FW BUG! */
3034                 BNX2X_ERR("FW failed to respond!\n");
3035                 bnx2x_fw_dump(bp);
3036                 rc = 0;
3037         }
3038         mutex_unlock(&bp->fw_mb_mutex);
3039
3040         return rc;
3041 }
3042
3043 static void storm_memset_func_cfg(struct bnx2x *bp,
3044                                  struct tstorm_eth_function_common_config *tcfg,
3045                                  u16 abs_fid)
3046 {
3047         size_t size = sizeof(struct tstorm_eth_function_common_config);
3048
3049         u32 addr = BAR_TSTRORM_INTMEM +
3050                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3051
3052         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3053 }
3054
3055 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3056 {
3057         if (CHIP_IS_E1x(bp)) {
3058                 struct tstorm_eth_function_common_config tcfg = {0};
3059
3060                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3061         }
3062
3063         /* Enable the function in the FW */
3064         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3065         storm_memset_func_en(bp, p->func_id, 1);
3066
3067         /* spq */
3068         if (p->spq_active) {
3069                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3070                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3071                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3072         }
3073 }
3074
3075 /**
3076  * bnx2x_get_common_flags - Return common flags
3077  *
3078  * @bp          device handle
3079  * @fp          queue handle
3080  * @zero_stats  TRUE if statistics zeroing is needed
3081  *
3082  * Return the flags that are common for the Tx-only and not normal connections.
3083  */
3084 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3085                                             struct bnx2x_fastpath *fp,
3086                                             bool zero_stats)
3087 {
3088         unsigned long flags = 0;
3089
3090         /* PF driver will always initialize the Queue to an ACTIVE state */
3091         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3092
3093         /* tx only connections collect statistics (on the same index as the
3094          * parent connection). The statistics are zeroed when the parent
3095          * connection is initialized.
3096          */
3097
3098         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3099         if (zero_stats)
3100                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3101
3102         if (bp->flags & TX_SWITCHING)
3103                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3104
3105         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3106         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3107
3108 #ifdef BNX2X_STOP_ON_ERROR
3109         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3110 #endif
3111
3112         return flags;
3113 }
3114
3115 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3116                                        struct bnx2x_fastpath *fp,
3117                                        bool leading)
3118 {
3119         unsigned long flags = 0;
3120
3121         /* calculate other queue flags */
3122         if (IS_MF_SD(bp))
3123                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3124
3125         if (IS_FCOE_FP(fp)) {
3126                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3127                 /* For FCoE - force usage of default priority (for afex) */
3128                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3129         }
3130
3131         if (fp->mode != TPA_MODE_DISABLED) {
3132                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3133                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3134                 if (fp->mode == TPA_MODE_GRO)
3135                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3136         }
3137
3138         if (leading) {
3139                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3140                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3141         }
3142
3143         /* Always set HW VLAN stripping */
3144         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3145
3146         /* configure silent vlan removal */
3147         if (IS_MF_AFEX(bp))
3148                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3149
3150         return flags | bnx2x_get_common_flags(bp, fp, true);
3151 }
3152
3153 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3154         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3155         u8 cos)
3156 {
3157         gen_init->stat_id = bnx2x_stats_id(fp);
3158         gen_init->spcl_id = fp->cl_id;
3159
3160         /* Always use mini-jumbo MTU for FCoE L2 ring */
3161         if (IS_FCOE_FP(fp))
3162                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3163         else
3164                 gen_init->mtu = bp->dev->mtu;
3165
3166         gen_init->cos = cos;
3167
3168         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3169 }
3170
3171 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3172         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3173         struct bnx2x_rxq_setup_params *rxq_init)
3174 {
3175         u8 max_sge = 0;
3176         u16 sge_sz = 0;
3177         u16 tpa_agg_size = 0;
3178
3179         if (fp->mode != TPA_MODE_DISABLED) {
3180                 pause->sge_th_lo = SGE_TH_LO(bp);
3181                 pause->sge_th_hi = SGE_TH_HI(bp);
3182
3183                 /* validate SGE ring has enough to cross high threshold */
3184                 WARN_ON(bp->dropless_fc &&
3185                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3186                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3187
3188                 tpa_agg_size = TPA_AGG_SIZE;
3189                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3190                         SGE_PAGE_SHIFT;
3191                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3192                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3193                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3194         }
3195
3196         /* pause - not for e1 */
3197         if (!CHIP_IS_E1(bp)) {
3198                 pause->bd_th_lo = BD_TH_LO(bp);
3199                 pause->bd_th_hi = BD_TH_HI(bp);
3200
3201                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3202                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3203                 /*
3204                  * validate that rings have enough entries to cross
3205                  * high thresholds
3206                  */
3207                 WARN_ON(bp->dropless_fc &&
3208                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3209                                 bp->rx_ring_size);
3210                 WARN_ON(bp->dropless_fc &&
3211                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3212                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3213
3214                 pause->pri_map = 1;
3215         }
3216
3217         /* rxq setup */
3218         rxq_init->dscr_map = fp->rx_desc_mapping;
3219         rxq_init->sge_map = fp->rx_sge_mapping;
3220         rxq_init->rcq_map = fp->rx_comp_mapping;
3221         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3222
3223         /* This should be a maximum number of data bytes that may be
3224          * placed on the BD (not including paddings).
3225          */
3226         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3227                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3228
3229         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3230         rxq_init->tpa_agg_sz = tpa_agg_size;
3231         rxq_init->sge_buf_sz = sge_sz;
3232         rxq_init->max_sges_pkt = max_sge;
3233         rxq_init->rss_engine_id = BP_FUNC(bp);
3234         rxq_init->mcast_engine_id = BP_FUNC(bp);
3235
3236         /* Maximum number or simultaneous TPA aggregation for this Queue.
3237          *
3238          * For PF Clients it should be the maximum available number.
3239          * VF driver(s) may want to define it to a smaller value.
3240          */
3241         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3242
3243         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3244         rxq_init->fw_sb_id = fp->fw_sb_id;
3245
3246         if (IS_FCOE_FP(fp))
3247                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3248         else
3249                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3250         /* configure silent vlan removal
3251          * if multi function mode is afex, then mask default vlan
3252          */
3253         if (IS_MF_AFEX(bp)) {
3254                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3255                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3256         }
3257 }
3258
3259 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3260         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3261         u8 cos)
3262 {
3263         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3264         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3265         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3266         txq_init->fw_sb_id = fp->fw_sb_id;
3267
3268         /*
3269          * set the tss leading client id for TX classification ==
3270          * leading RSS client id
3271          */
3272         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3273
3274         if (IS_FCOE_FP(fp)) {
3275                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3276                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3277         }
3278 }
3279
3280 static void bnx2x_pf_init(struct bnx2x *bp)
3281 {
3282         struct bnx2x_func_init_params func_init = {0};
3283         struct event_ring_data eq_data = { {0} };
3284
3285         if (!CHIP_IS_E1x(bp)) {
3286                 /* reset IGU PF statistics: MSIX + ATTN */
3287                 /* PF */
3288                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3289                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3290                            (CHIP_MODE_IS_4_PORT(bp) ?
3291                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3292                 /* ATTN */
3293                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3294                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3295                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3296                            (CHIP_MODE_IS_4_PORT(bp) ?
3297                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3298         }
3299
3300         func_init.spq_active = true;
3301         func_init.pf_id = BP_FUNC(bp);
3302         func_init.func_id = BP_FUNC(bp);
3303         func_init.spq_map = bp->spq_mapping;
3304         func_init.spq_prod = bp->spq_prod_idx;
3305
3306         bnx2x_func_init(bp, &func_init);
3307
3308         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3309
3310         /*
3311          * Congestion management values depend on the link rate
3312          * There is no active link so initial link rate is set to 10 Gbps.
3313          * When the link comes up The congestion management values are
3314          * re-calculated according to the actual link rate.
3315          */
3316         bp->link_vars.line_speed = SPEED_10000;
3317         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3318
3319         /* Only the PMF sets the HW */
3320         if (bp->port.pmf)
3321                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3322
3323         /* init Event Queue - PCI bus guarantees correct endianity*/
3324         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3325         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3326         eq_data.producer = bp->eq_prod;
3327         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3328         eq_data.sb_id = DEF_SB_ID;
3329         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3330 }
3331
3332 static void bnx2x_e1h_disable(struct bnx2x *bp)
3333 {
3334         int port = BP_PORT(bp);
3335
3336         bnx2x_tx_disable(bp);
3337
3338         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3339 }
3340
3341 static void bnx2x_e1h_enable(struct bnx2x *bp)
3342 {
3343         int port = BP_PORT(bp);
3344
3345         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3346                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3347
3348         /* Tx queue should be only re-enabled */
3349         netif_tx_wake_all_queues(bp->dev);
3350
3351         /*
3352          * Should not call netif_carrier_on since it will be called if the link
3353          * is up when checking for link state
3354          */
3355 }
3356
3357 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3358
3359 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3360 {
3361         struct eth_stats_info *ether_stat =
3362                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3363         struct bnx2x_vlan_mac_obj *mac_obj =
3364                 &bp->sp_objs->mac_obj;
3365         int i;
3366
3367         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3368                 ETH_STAT_INFO_VERSION_LEN);
3369
3370         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3371          * mac_local field in ether_stat struct. The base address is offset by 2
3372          * bytes to account for the field being 8 bytes but a mac address is
3373          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3374          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3375          * allocated by the ether_stat struct, so the macs will land in their
3376          * proper positions.
3377          */
3378         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3379                 memset(ether_stat->mac_local + i, 0,
3380                        sizeof(ether_stat->mac_local[0]));
3381         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3382                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3383                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3384                                 ETH_ALEN);
3385         ether_stat->mtu_size = bp->dev->mtu;
3386         if (bp->dev->features & NETIF_F_RXCSUM)
3387                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3388         if (bp->dev->features & NETIF_F_TSO)
3389                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3390         ether_stat->feature_flags |= bp->common.boot_mode;
3391
3392         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3393
3394         ether_stat->txq_size = bp->tx_ring_size;
3395         ether_stat->rxq_size = bp->rx_ring_size;
3396
3397 #ifdef CONFIG_BNX2X_SRIOV
3398         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3399 #endif
3400 }
3401
3402 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3403 {
3404         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3405         struct fcoe_stats_info *fcoe_stat =
3406                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3407
3408         if (!CNIC_LOADED(bp))
3409                 return;
3410
3411         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3412
3413         fcoe_stat->qos_priority =
3414                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3415
3416         /* insert FCoE stats from ramrod response */
3417         if (!NO_FCOE(bp)) {
3418                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3419                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3420                         tstorm_queue_statistics;
3421
3422                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3423                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3424                         xstorm_queue_statistics;
3425
3426                 struct fcoe_statistics_params *fw_fcoe_stat =
3427                         &bp->fw_stats_data->fcoe;
3428
3429                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3430                           fcoe_stat->rx_bytes_lo,
3431                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3432
3433                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3434                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3435                           fcoe_stat->rx_bytes_lo,
3436                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3437
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3439                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3440                           fcoe_stat->rx_bytes_lo,
3441                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3442
3443                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3444                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3445                           fcoe_stat->rx_bytes_lo,
3446                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3447
3448                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3449                           fcoe_stat->rx_frames_lo,
3450                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3451
3452                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3453                           fcoe_stat->rx_frames_lo,
3454                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3455
3456                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3457                           fcoe_stat->rx_frames_lo,
3458                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3459
3460                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3461                           fcoe_stat->rx_frames_lo,
3462                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3463
3464                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3465                           fcoe_stat->tx_bytes_lo,
3466                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3467
3468                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3469                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3470                           fcoe_stat->tx_bytes_lo,
3471                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3472
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3474                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3475                           fcoe_stat->tx_bytes_lo,
3476                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3477
3478                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3479                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3480                           fcoe_stat->tx_bytes_lo,
3481                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3482
3483                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3484                           fcoe_stat->tx_frames_lo,
3485                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3486
3487                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3488                           fcoe_stat->tx_frames_lo,
3489                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3490
3491                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3492                           fcoe_stat->tx_frames_lo,
3493                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3494
3495                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3496                           fcoe_stat->tx_frames_lo,
3497                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3498         }
3499
3500         /* ask L5 driver to add data to the struct */
3501         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3502 }
3503
3504 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3505 {
3506         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3507         struct iscsi_stats_info *iscsi_stat =
3508                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3509
3510         if (!CNIC_LOADED(bp))
3511                 return;
3512
3513         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3514                ETH_ALEN);
3515
3516         iscsi_stat->qos_priority =
3517                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3518
3519         /* ask L5 driver to add data to the struct */
3520         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3521 }
3522
3523 /* called due to MCP event (on pmf):
3524  *      reread new bandwidth configuration
3525  *      configure FW
3526  *      notify others function about the change
3527  */
3528 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3529 {
3530         /* Workaround for MFW bug.
3531          * MFW is not supposed to generate BW attention in
3532          * single function mode.
3533          */
3534         if (!IS_MF(bp)) {
3535                 DP(BNX2X_MSG_MCP,
3536                    "Ignoring MF BW config in single function mode\n");
3537                 return;
3538         }
3539
3540         if (bp->link_vars.link_up) {
3541                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3542                 bnx2x_link_sync_notify(bp);
3543         }
3544         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3545 }
3546
3547 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3548 {
3549         bnx2x_config_mf_bw(bp);
3550         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3551 }
3552
3553 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3554 {
3555         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3556         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3557 }
3558
3559 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3560 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3561
3562 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3563 {
3564         enum drv_info_opcode op_code;
3565         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3566         bool release = false;
3567         int wait;
3568
3569         /* if drv_info version supported by MFW doesn't match - send NACK */
3570         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3571                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3572                 return;
3573         }
3574
3575         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3576                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3577
3578         /* Must prevent other flows from accessing drv_info_to_mcp */
3579         mutex_lock(&bp->drv_info_mutex);
3580
3581         memset(&bp->slowpath->drv_info_to_mcp, 0,
3582                sizeof(union drv_info_to_mcp));
3583
3584         switch (op_code) {
3585         case ETH_STATS_OPCODE:
3586                 bnx2x_drv_info_ether_stat(bp);
3587                 break;
3588         case FCOE_STATS_OPCODE:
3589                 bnx2x_drv_info_fcoe_stat(bp);
3590                 break;
3591         case ISCSI_STATS_OPCODE:
3592                 bnx2x_drv_info_iscsi_stat(bp);
3593                 break;
3594         default:
3595                 /* if op code isn't supported - send NACK */
3596                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3597                 goto out;
3598         }
3599
3600         /* if we got drv_info attn from MFW then these fields are defined in
3601          * shmem2 for sure
3602          */
3603         SHMEM2_WR(bp, drv_info_host_addr_lo,
3604                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3605         SHMEM2_WR(bp, drv_info_host_addr_hi,
3606                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3607
3608         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3609
3610         /* Since possible management wants both this and get_driver_version
3611          * need to wait until management notifies us it finished utilizing
3612          * the buffer.
3613          */
3614         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3615                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3616         } else if (!bp->drv_info_mng_owner) {
3617                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3618
3619                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3620                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3621
3622                         /* Management is done; need to clear indication */
3623                         if (indication & bit) {
3624                                 SHMEM2_WR(bp, mfw_drv_indication,
3625                                           indication & ~bit);
3626                                 release = true;
3627                                 break;
3628                         }
3629
3630                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3631                 }
3632         }
3633         if (!release) {
3634                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3635                 bp->drv_info_mng_owner = true;
3636         }
3637
3638 out:
3639         mutex_unlock(&bp->drv_info_mutex);
3640 }
3641
3642 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3643 {
3644         u8 vals[4];
3645         int i = 0;
3646
3647         if (bnx2x_format) {
3648                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3649                            &vals[0], &vals[1], &vals[2], &vals[3]);
3650                 if (i > 0)
3651                         vals[0] -= '0';
3652         } else {
3653                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3654                            &vals[0], &vals[1], &vals[2], &vals[3]);
3655         }
3656
3657         while (i < 4)
3658                 vals[i++] = 0;
3659
3660         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3661 }
3662
3663 void bnx2x_update_mng_version(struct bnx2x *bp)
3664 {
3665         u32 iscsiver = DRV_VER_NOT_LOADED;
3666         u32 fcoever = DRV_VER_NOT_LOADED;
3667         u32 ethver = DRV_VER_NOT_LOADED;
3668         int idx = BP_FW_MB_IDX(bp);
3669         u8 *version;
3670
3671         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3672                 return;
3673
3674         mutex_lock(&bp->drv_info_mutex);
3675         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3676         if (bp->drv_info_mng_owner)
3677                 goto out;
3678
3679         if (bp->state != BNX2X_STATE_OPEN)
3680                 goto out;
3681
3682         /* Parse ethernet driver version */
3683         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3684         if (!CNIC_LOADED(bp))
3685                 goto out;
3686
3687         /* Try getting storage driver version via cnic */
3688         memset(&bp->slowpath->drv_info_to_mcp, 0,
3689                sizeof(union drv_info_to_mcp));
3690         bnx2x_drv_info_iscsi_stat(bp);
3691         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3692         iscsiver = bnx2x_update_mng_version_utility(version, false);
3693
3694         memset(&bp->slowpath->drv_info_to_mcp, 0,
3695                sizeof(union drv_info_to_mcp));
3696         bnx2x_drv_info_fcoe_stat(bp);
3697         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3698         fcoever = bnx2x_update_mng_version_utility(version, false);
3699
3700 out:
3701         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3702         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3703         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3704
3705         mutex_unlock(&bp->drv_info_mutex);
3706
3707         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3708            ethver, iscsiver, fcoever);
3709 }
3710
3711 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3712 {
3713         u32 drv_ver;
3714         u32 valid_dump;
3715
3716         if (!SHMEM2_HAS(bp, drv_info))
3717                 return;
3718
3719         /* Update Driver load time, possibly broken in y2038 */
3720         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3721
3722         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3723         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3724
3725         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3726
3727         /* Check & notify On-Chip dump. */
3728         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3729
3730         if (valid_dump & FIRST_DUMP_VALID)
3731                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3732
3733         if (valid_dump & SECOND_DUMP_VALID)
3734                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3735 }
3736
3737 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3738 {
3739         u32 cmd_ok, cmd_fail;
3740
3741         /* sanity */
3742         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3743             event & DRV_STATUS_OEM_EVENT_MASK) {
3744                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3745                 return;
3746         }
3747
3748         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3749                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3750                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3751         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3752                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3753                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3754         }
3755
3756         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3757
3758         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3759                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3760                 /* This is the only place besides the function initialization
3761                  * where the bp->flags can change so it is done without any
3762                  * locks
3763                  */
3764                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3765                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3766                         bp->flags |= MF_FUNC_DIS;
3767
3768                         bnx2x_e1h_disable(bp);
3769                 } else {
3770                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3771                         bp->flags &= ~MF_FUNC_DIS;
3772
3773                         bnx2x_e1h_enable(bp);
3774                 }
3775                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3776                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3777         }
3778
3779         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3780                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3781                 bnx2x_config_mf_bw(bp);
3782                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3783                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3784         }
3785
3786         /* Report results to MCP */
3787         if (event)
3788                 bnx2x_fw_command(bp, cmd_fail, 0);
3789         else
3790                 bnx2x_fw_command(bp, cmd_ok, 0);
3791 }
3792
3793 /* must be called under the spq lock */
3794 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3795 {
3796         struct eth_spe *next_spe = bp->spq_prod_bd;
3797
3798         if (bp->spq_prod_bd == bp->spq_last_bd) {
3799                 bp->spq_prod_bd = bp->spq;
3800                 bp->spq_prod_idx = 0;
3801                 DP(BNX2X_MSG_SP, "end of spq\n");
3802         } else {
3803                 bp->spq_prod_bd++;
3804                 bp->spq_prod_idx++;
3805         }
3806         return next_spe;
3807 }
3808
3809 /* must be called under the spq lock */
3810 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3811 {
3812         int func = BP_FUNC(bp);
3813
3814         /*
3815          * Make sure that BD data is updated before writing the producer:
3816          * BD data is written to the memory, the producer is read from the
3817          * memory, thus we need a full memory barrier to ensure the ordering.
3818          */
3819         mb();
3820
3821         REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3822                          bp->spq_prod_idx);
3823 }
3824
3825 /**
3826  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3827  *
3828  * @cmd:        command to check
3829  * @cmd_type:   command type
3830  */
3831 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3832 {
3833         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3834             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3835             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3836             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3837             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3838             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3839             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3840                 return true;
3841         else
3842                 return false;
3843 }
3844
3845 /**
3846  * bnx2x_sp_post - place a single command on an SP ring
3847  *
3848  * @bp:         driver handle
3849  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3850  * @cid:        SW CID the command is related to
3851  * @data_hi:    command private data address (high 32 bits)
3852  * @data_lo:    command private data address (low 32 bits)
3853  * @cmd_type:   command type (e.g. NONE, ETH)
3854  *
3855  * SP data is handled as if it's always an address pair, thus data fields are
3856  * not swapped to little endian in upper functions. Instead this function swaps
3857  * data as if it's two u32 fields.
3858  */
3859 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3860                   u32 data_hi, u32 data_lo, int cmd_type)
3861 {
3862         struct eth_spe *spe;
3863         u16 type;
3864         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3865
3866 #ifdef BNX2X_STOP_ON_ERROR
3867         if (unlikely(bp->panic)) {
3868                 BNX2X_ERR("Can't post SP when there is panic\n");
3869                 return -EIO;
3870         }
3871 #endif
3872
3873         spin_lock_bh(&bp->spq_lock);
3874
3875         if (common) {
3876                 if (!atomic_read(&bp->eq_spq_left)) {
3877                         BNX2X_ERR("BUG! EQ ring full!\n");
3878                         spin_unlock_bh(&bp->spq_lock);
3879                         bnx2x_panic();
3880                         return -EBUSY;
3881                 }
3882         } else if (!atomic_read(&bp->cq_spq_left)) {
3883                         BNX2X_ERR("BUG! SPQ ring full!\n");
3884                         spin_unlock_bh(&bp->spq_lock);
3885                         bnx2x_panic();
3886                         return -EBUSY;
3887         }
3888
3889         spe = bnx2x_sp_get_next(bp);
3890
3891         /* CID needs port number to be encoded int it */
3892         spe->hdr.conn_and_cmd_data =
3893                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3894                                     HW_CID(bp, cid));
3895
3896         /* In some cases, type may already contain the func-id
3897          * mainly in SRIOV related use cases, so we add it here only
3898          * if it's not already set.
3899          */
3900         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3901                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3902                         SPE_HDR_CONN_TYPE;
3903                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3904                          SPE_HDR_FUNCTION_ID);
3905         } else {
3906                 type = cmd_type;
3907         }
3908
3909         spe->hdr.type = cpu_to_le16(type);
3910
3911         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3912         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3913
3914         /*
3915          * It's ok if the actual decrement is issued towards the memory
3916          * somewhere between the spin_lock and spin_unlock. Thus no
3917          * more explicit memory barrier is needed.
3918          */
3919         if (common)
3920                 atomic_dec(&bp->eq_spq_left);
3921         else
3922                 atomic_dec(&bp->cq_spq_left);
3923
3924         DP(BNX2X_MSG_SP,
3925            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3926            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3927            (u32)(U64_LO(bp->spq_mapping) +
3928            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3929            HW_CID(bp, cid), data_hi, data_lo, type,
3930            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3931
3932         bnx2x_sp_prod_update(bp);
3933         spin_unlock_bh(&bp->spq_lock);
3934         return 0;
3935 }
3936
3937 /* acquire split MCP access lock register */
3938 static int bnx2x_acquire_alr(struct bnx2x *bp)
3939 {
3940         u32 j, val;
3941         int rc = 0;
3942
3943         might_sleep();
3944         for (j = 0; j < 1000; j++) {
3945                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3946                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3947                 if (val & MCPR_ACCESS_LOCK_LOCK)
3948                         break;
3949
3950                 usleep_range(5000, 10000);
3951         }
3952         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3953                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3954                 rc = -EBUSY;
3955         }
3956
3957         return rc;
3958 }
3959
3960 /* release split MCP access lock register */
3961 static void bnx2x_release_alr(struct bnx2x *bp)
3962 {
3963         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3964 }
3965
3966 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3967 #define BNX2X_DEF_SB_IDX        0x0002
3968
3969 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3970 {
3971         struct host_sp_status_block *def_sb = bp->def_status_blk;
3972         u16 rc = 0;
3973
3974         barrier(); /* status block is written to by the chip */
3975         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3976                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3977                 rc |= BNX2X_DEF_SB_ATT_IDX;
3978         }
3979
3980         if (bp->def_idx != def_sb->sp_sb.running_index) {
3981                 bp->def_idx = def_sb->sp_sb.running_index;
3982                 rc |= BNX2X_DEF_SB_IDX;
3983         }
3984
3985         /* Do not reorder: indices reading should complete before handling */
3986         barrier();
3987         return rc;
3988 }
3989
3990 /*
3991  * slow path service functions
3992  */
3993
3994 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3995 {
3996         int port = BP_PORT(bp);
3997         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3998                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3999         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4000                                        NIG_REG_MASK_INTERRUPT_PORT0;
4001         u32 aeu_mask;
4002         u32 nig_mask = 0;
4003         u32 reg_addr;
4004
4005         if (bp->attn_state & asserted)
4006                 BNX2X_ERR("IGU ERROR\n");
4007
4008         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4009         aeu_mask = REG_RD(bp, aeu_addr);
4010
4011         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4012            aeu_mask, asserted);
4013         aeu_mask &= ~(asserted & 0x3ff);
4014         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4015
4016         REG_WR(bp, aeu_addr, aeu_mask);
4017         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4018
4019         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4020         bp->attn_state |= asserted;
4021         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4022
4023         if (asserted & ATTN_HARD_WIRED_MASK) {
4024                 if (asserted & ATTN_NIG_FOR_FUNC) {
4025
4026                         bnx2x_acquire_phy_lock(bp);
4027
4028                         /* save nig interrupt mask */
4029                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4030
4031                         /* If nig_mask is not set, no need to call the update
4032                          * function.
4033                          */
4034                         if (nig_mask) {
4035                                 REG_WR(bp, nig_int_mask_addr, 0);
4036
4037                                 bnx2x_link_attn(bp);
4038                         }
4039
4040                         /* handle unicore attn? */
4041                 }
4042                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4043                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4044
4045                 if (asserted & GPIO_2_FUNC)
4046                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4047
4048                 if (asserted & GPIO_3_FUNC)
4049                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4050
4051                 if (asserted & GPIO_4_FUNC)
4052                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4053
4054                 if (port == 0) {
4055                         if (asserted & ATTN_GENERAL_ATTN_1) {
4056                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4057                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4058                         }
4059                         if (asserted & ATTN_GENERAL_ATTN_2) {
4060                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4061                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4062                         }
4063                         if (asserted & ATTN_GENERAL_ATTN_3) {
4064                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4065                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4066                         }
4067                 } else {
4068                         if (asserted & ATTN_GENERAL_ATTN_4) {
4069                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4070                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4071                         }
4072                         if (asserted & ATTN_GENERAL_ATTN_5) {
4073                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4074                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4075                         }
4076                         if (asserted & ATTN_GENERAL_ATTN_6) {
4077                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4078                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4079                         }
4080                 }
4081
4082         } /* if hardwired */
4083
4084         if (bp->common.int_block == INT_BLOCK_HC)
4085                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4086                             COMMAND_REG_ATTN_BITS_SET);
4087         else
4088                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4089
4090         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4091            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4092         REG_WR(bp, reg_addr, asserted);
4093
4094         /* now set back the mask */
4095         if (asserted & ATTN_NIG_FOR_FUNC) {
4096                 /* Verify that IGU ack through BAR was written before restoring
4097                  * NIG mask. This loop should exit after 2-3 iterations max.
4098                  */
4099                 if (bp->common.int_block != INT_BLOCK_HC) {
4100                         u32 cnt = 0, igu_acked;
4101                         do {
4102                                 igu_acked = REG_RD(bp,
4103                                                    IGU_REG_ATTENTION_ACK_BITS);
4104                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4105                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4106                         if (!igu_acked)
4107                                 DP(NETIF_MSG_HW,
4108                                    "Failed to verify IGU ack on time\n");
4109                         barrier();
4110                 }
4111                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4112                 bnx2x_release_phy_lock(bp);
4113         }
4114 }
4115
4116 static void bnx2x_fan_failure(struct bnx2x *bp)
4117 {
4118         int port = BP_PORT(bp);
4119         u32 ext_phy_config;
4120         /* mark the failure */
4121         ext_phy_config =
4122                 SHMEM_RD(bp,
4123                          dev_info.port_hw_config[port].external_phy_config);
4124
4125         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4126         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4127         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4128                  ext_phy_config);
4129
4130         /* log the failure */
4131         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4132                             "Please contact OEM Support for assistance\n");
4133
4134         /* Schedule device reset (unload)
4135          * This is due to some boards consuming sufficient power when driver is
4136          * up to overheat if fan fails.
4137          */
4138         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4139 }
4140
4141 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4142 {
4143         int port = BP_PORT(bp);
4144         int reg_offset;
4145         u32 val;
4146
4147         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4148                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4149
4150         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4151
4152                 val = REG_RD(bp, reg_offset);
4153                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4154                 REG_WR(bp, reg_offset, val);
4155
4156                 BNX2X_ERR("SPIO5 hw attention\n");
4157
4158                 /* Fan failure attention */
4159                 bnx2x_hw_reset_phy(&bp->link_params);
4160                 bnx2x_fan_failure(bp);
4161         }
4162
4163         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4164                 bnx2x_acquire_phy_lock(bp);
4165                 bnx2x_handle_module_detect_int(&bp->link_params);
4166                 bnx2x_release_phy_lock(bp);
4167         }
4168
4169         if (attn & HW_INTERRUPT_ASSERT_SET_0) {
4170
4171                 val = REG_RD(bp, reg_offset);
4172                 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0);
4173                 REG_WR(bp, reg_offset, val);
4174
4175                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4176                           (u32)(attn & HW_INTERRUPT_ASSERT_SET_0));
4177                 bnx2x_panic();
4178         }
4179 }
4180
4181 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4182 {
4183         u32 val;
4184
4185         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4186
4187                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4188                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4189                 /* DORQ discard attention */
4190                 if (val & 0x2)
4191                         BNX2X_ERR("FATAL error from DORQ\n");
4192         }
4193
4194         if (attn & HW_INTERRUPT_ASSERT_SET_1) {
4195
4196                 int port = BP_PORT(bp);
4197                 int reg_offset;
4198
4199                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4200                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4201
4202                 val = REG_RD(bp, reg_offset);
4203                 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1);
4204                 REG_WR(bp, reg_offset, val);
4205
4206                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4207                           (u32)(attn & HW_INTERRUPT_ASSERT_SET_1));
4208                 bnx2x_panic();
4209         }
4210 }
4211
4212 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4213 {
4214         u32 val;
4215
4216         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4217
4218                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4219                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4220                 /* CFC error attention */
4221                 if (val & 0x2)
4222                         BNX2X_ERR("FATAL error from CFC\n");
4223         }
4224
4225         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4226                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4227                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4228                 /* RQ_USDMDP_FIFO_OVERFLOW */
4229                 if (val & 0x18000)
4230                         BNX2X_ERR("FATAL error from PXP\n");
4231
4232                 if (!CHIP_IS_E1x(bp)) {
4233                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4234                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4235                 }
4236         }
4237
4238         if (attn & HW_INTERRUPT_ASSERT_SET_2) {
4239
4240                 int port = BP_PORT(bp);
4241                 int reg_offset;
4242
4243                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4244                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4245
4246                 val = REG_RD(bp, reg_offset);
4247                 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2);
4248                 REG_WR(bp, reg_offset, val);
4249
4250                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4251                           (u32)(attn & HW_INTERRUPT_ASSERT_SET_2));
4252                 bnx2x_panic();
4253         }
4254 }
4255
4256 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4257 {
4258         u32 val;
4259
4260         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4261
4262                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4263                         int func = BP_FUNC(bp);
4264
4265                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4266                         bnx2x_read_mf_cfg(bp);
4267                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4268                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4269                         val = SHMEM_RD(bp,
4270                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4271
4272                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4273                                    DRV_STATUS_OEM_EVENT_MASK))
4274                                 bnx2x_oem_event(bp,
4275                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4276                                                 DRV_STATUS_OEM_EVENT_MASK)));
4277
4278                         if (val & DRV_STATUS_SET_MF_BW)
4279                                 bnx2x_set_mf_bw(bp);
4280
4281                         if (val & DRV_STATUS_DRV_INFO_REQ)
4282                                 bnx2x_handle_drv_info_req(bp);
4283
4284                         if (val & DRV_STATUS_VF_DISABLED)
4285                                 bnx2x_schedule_iov_task(bp,
4286                                                         BNX2X_IOV_HANDLE_FLR);
4287
4288                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4289                                 bnx2x_pmf_update(bp);
4290
4291                         if (bp->port.pmf &&
4292                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4293                                 bp->dcbx_enabled > 0)
4294                                 /* start dcbx state machine */
4295                                 bnx2x_dcbx_set_params(bp,
4296                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4297                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4298                                 bnx2x_handle_afex_cmd(bp,
4299                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4300                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4301                                 bnx2x_handle_eee_event(bp);
4302
4303                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4304                                 bnx2x_schedule_sp_rtnl(bp,
4305                                         BNX2X_SP_RTNL_UPDATE_SVID, 0);
4306
4307                         if (bp->link_vars.periodic_flags &
4308                             PERIODIC_FLAGS_LINK_EVENT) {
4309                                 /*  sync with link */
4310                                 bnx2x_acquire_phy_lock(bp);
4311                                 bp->link_vars.periodic_flags &=
4312                                         ~PERIODIC_FLAGS_LINK_EVENT;
4313                                 bnx2x_release_phy_lock(bp);
4314                                 if (IS_MF(bp))
4315                                         bnx2x_link_sync_notify(bp);
4316                                 bnx2x_link_report(bp);
4317                         }
4318                         /* Always call it here: bnx2x_link_report() will
4319                          * prevent the link indication duplication.
4320                          */
4321                         bnx2x__link_status_update(bp);
4322                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4323
4324                         BNX2X_ERR("MC assert!\n");
4325                         bnx2x_mc_assert(bp);
4326                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4327                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4328                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4329                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4330                         bnx2x_panic();
4331
4332                 } else if (attn & BNX2X_MCP_ASSERT) {
4333
4334                         BNX2X_ERR("MCP assert!\n");
4335                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4336                         bnx2x_fw_dump(bp);
4337
4338                 } else
4339                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4340         }
4341
4342         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4343                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4344                 if (attn & BNX2X_GRC_TIMEOUT) {
4345                         val = CHIP_IS_E1(bp) ? 0 :
4346                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4347                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4348                 }
4349                 if (attn & BNX2X_GRC_RSV) {
4350                         val = CHIP_IS_E1(bp) ? 0 :
4351                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4352                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4353                 }
4354                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4355         }
4356 }
4357
4358 /*
4359  * Bits map:
4360  * 0-7   - Engine0 load counter.
4361  * 8-15  - Engine1 load counter.
4362  * 16    - Engine0 RESET_IN_PROGRESS bit.
4363  * 17    - Engine1 RESET_IN_PROGRESS bit.
4364  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4365  *         on the engine
4366  * 19    - Engine1 ONE_IS_LOADED.
4367  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4368  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4369  *         just the one belonging to its engine).
4370  *
4371  */
4372 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4373
4374 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4375 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4376 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4377 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4378 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4379 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4380 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4381
4382 /*
4383  * Set the GLOBAL_RESET bit.
4384  *
4385  * Should be run under rtnl lock
4386  */
4387 void bnx2x_set_reset_global(struct bnx2x *bp)
4388 {
4389         u32 val;
4390         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4391         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4392         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4393         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4394 }
4395
4396 /*
4397  * Clear the GLOBAL_RESET bit.
4398  *
4399  * Should be run under rtnl lock
4400  */
4401 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4402 {
4403         u32 val;
4404         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4405         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4406         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4407         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4408 }
4409
4410 /*
4411  * Checks the GLOBAL_RESET bit.
4412  *
4413  * should be run under rtnl lock
4414  */
4415 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4416 {
4417         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4418
4419         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4420         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4421 }
4422
4423 /*
4424  * Clear RESET_IN_PROGRESS bit for the current engine.
4425  *
4426  * Should be run under rtnl lock
4427  */
4428 static void bnx2x_set_reset_done(struct bnx2x *bp)
4429 {
4430         u32 val;
4431         u32 bit = BP_PATH(bp) ?
4432                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4433         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4434         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4435
4436         /* Clear the bit */
4437         val &= ~bit;
4438         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4439
4440         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4441 }
4442
4443 /*
4444  * Set RESET_IN_PROGRESS for the current engine.
4445  *
4446  * should be run under rtnl lock
4447  */
4448 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4449 {
4450         u32 val;
4451         u32 bit = BP_PATH(bp) ?
4452                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4453         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4454         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4455
4456         /* Set the bit */
4457         val |= bit;
4458         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4459         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4460 }
4461
4462 /*
4463  * Checks the RESET_IN_PROGRESS bit for the given engine.
4464  * should be run under rtnl lock
4465  */
4466 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4467 {
4468         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4469         u32 bit = engine ?
4470                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4471
4472         /* return false if bit is set */
4473         return (val & bit) ? false : true;
4474 }
4475
4476 /*
4477  * set pf load for the current pf.
4478  *
4479  * should be run under rtnl lock
4480  */
4481 void bnx2x_set_pf_load(struct bnx2x *bp)
4482 {
4483         u32 val1, val;
4484         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4485                              BNX2X_PATH0_LOAD_CNT_MASK;
4486         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4487                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4488
4489         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4490         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4491
4492         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4493
4494         /* get the current counter value */
4495         val1 = (val & mask) >> shift;
4496
4497         /* set bit of that PF */
4498         val1 |= (1 << bp->pf_num);
4499
4500         /* clear the old value */
4501         val &= ~mask;
4502
4503         /* set the new one */
4504         val |= ((val1 << shift) & mask);
4505
4506         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4507         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4508 }
4509
4510 /**
4511  * bnx2x_clear_pf_load - clear pf load mark
4512  *
4513  * @bp:         driver handle
4514  *
4515  * Should be run under rtnl lock.
4516  * Decrements the load counter for the current engine. Returns
4517  * whether other functions are still loaded
4518  */
4519 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4520 {
4521         u32 val1, val;
4522         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4523                              BNX2X_PATH0_LOAD_CNT_MASK;
4524         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4525                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4526
4527         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4528         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4529         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4530
4531         /* get the current counter value */
4532         val1 = (val & mask) >> shift;
4533
4534         /* clear bit of that PF */
4535         val1 &= ~(1 << bp->pf_num);
4536
4537         /* clear the old value */
4538         val &= ~mask;
4539
4540         /* set the new one */
4541         val |= ((val1 << shift) & mask);
4542
4543         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4544         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4545         return val1 != 0;
4546 }
4547
4548 /*
4549  * Read the load status for the current engine.
4550  *
4551  * should be run under rtnl lock
4552  */
4553 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4554 {
4555         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4556                              BNX2X_PATH0_LOAD_CNT_MASK);
4557         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4558                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4559         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4560
4561         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4562
4563         val = (val & mask) >> shift;
4564
4565         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4566            engine, val);
4567
4568         return val != 0;
4569 }
4570
4571 static void _print_parity(struct bnx2x *bp, u32 reg)
4572 {
4573         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4574 }
4575
4576 static void _print_next_block(int idx, const char *blk)
4577 {
4578         pr_cont("%s%s", idx ? ", " : "", blk);
4579 }
4580
4581 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4582                                             int *par_num, bool print)
4583 {
4584         u32 cur_bit;
4585         bool res;
4586         int i;
4587
4588         res = false;
4589
4590         for (i = 0; sig; i++) {
4591                 cur_bit = (0x1UL << i);
4592                 if (sig & cur_bit) {
4593                         res |= true; /* Each bit is real error! */
4594
4595                         if (print) {
4596                                 switch (cur_bit) {
4597                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4598                                         _print_next_block((*par_num)++, "BRB");
4599                                         _print_parity(bp,
4600                                                       BRB1_REG_BRB1_PRTY_STS);
4601                                         break;
4602                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4603                                         _print_next_block((*par_num)++,
4604                                                           "PARSER");
4605                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4606                                         break;
4607                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4608                                         _print_next_block((*par_num)++, "TSDM");
4609                                         _print_parity(bp,
4610                                                       TSDM_REG_TSDM_PRTY_STS);
4611                                         break;
4612                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4613                                         _print_next_block((*par_num)++,
4614                                                           "SEARCHER");
4615                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4616                                         break;
4617                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4618                                         _print_next_block((*par_num)++, "TCM");
4619                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4620                                         break;
4621                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4622                                         _print_next_block((*par_num)++,
4623                                                           "TSEMI");
4624                                         _print_parity(bp,
4625                                                       TSEM_REG_TSEM_PRTY_STS_0);
4626                                         _print_parity(bp,
4627                                                       TSEM_REG_TSEM_PRTY_STS_1);
4628                                         break;
4629                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4630                                         _print_next_block((*par_num)++, "XPB");
4631                                         _print_parity(bp, GRCBASE_XPB +
4632                                                           PB_REG_PB_PRTY_STS);
4633                                         break;
4634                                 }
4635                         }
4636
4637                         /* Clear the bit */
4638                         sig &= ~cur_bit;
4639                 }
4640         }
4641
4642         return res;
4643 }
4644
4645 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4646                                             int *par_num, bool *global,
4647                                             bool print)
4648 {
4649         u32 cur_bit;
4650         bool res;
4651         int i;
4652
4653         res = false;
4654
4655         for (i = 0; sig; i++) {
4656                 cur_bit = (0x1UL << i);
4657                 if (sig & cur_bit) {
4658                         res |= true; /* Each bit is real error! */
4659                         switch (cur_bit) {
4660                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4661                                 if (print) {
4662                                         _print_next_block((*par_num)++, "PBF");
4663                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4664                                 }
4665                                 break;
4666                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4667                                 if (print) {
4668                                         _print_next_block((*par_num)++, "QM");
4669                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4670                                 }
4671                                 break;
4672                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4673                                 if (print) {
4674                                         _print_next_block((*par_num)++, "TM");
4675                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4676                                 }
4677                                 break;
4678                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4679                                 if (print) {
4680                                         _print_next_block((*par_num)++, "XSDM");
4681                                         _print_parity(bp,
4682                                                       XSDM_REG_XSDM_PRTY_STS);
4683                                 }
4684                                 break;
4685                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4686                                 if (print) {
4687                                         _print_next_block((*par_num)++, "XCM");
4688                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4689                                 }
4690                                 break;
4691                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4692                                 if (print) {
4693                                         _print_next_block((*par_num)++,
4694                                                           "XSEMI");
4695                                         _print_parity(bp,
4696                                                       XSEM_REG_XSEM_PRTY_STS_0);
4697                                         _print_parity(bp,
4698                                                       XSEM_REG_XSEM_PRTY_STS_1);
4699                                 }
4700                                 break;
4701                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4702                                 if (print) {
4703                                         _print_next_block((*par_num)++,
4704                                                           "DOORBELLQ");
4705                                         _print_parity(bp,
4706                                                       DORQ_REG_DORQ_PRTY_STS);
4707                                 }
4708                                 break;
4709                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4710                                 if (print) {
4711                                         _print_next_block((*par_num)++, "NIG");
4712                                         if (CHIP_IS_E1x(bp)) {
4713                                                 _print_parity(bp,
4714                                                         NIG_REG_NIG_PRTY_STS);
4715                                         } else {
4716                                                 _print_parity(bp,
4717                                                         NIG_REG_NIG_PRTY_STS_0);
4718                                                 _print_parity(bp,
4719                                                         NIG_REG_NIG_PRTY_STS_1);
4720                                         }
4721                                 }
4722                                 break;
4723                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4724                                 if (print)
4725                                         _print_next_block((*par_num)++,
4726                                                           "VAUX PCI CORE");
4727                                 *global = true;
4728                                 break;
4729                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4730                                 if (print) {
4731                                         _print_next_block((*par_num)++,
4732                                                           "DEBUG");
4733                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4734                                 }
4735                                 break;
4736                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4737                                 if (print) {
4738                                         _print_next_block((*par_num)++, "USDM");
4739                                         _print_parity(bp,
4740                                                       USDM_REG_USDM_PRTY_STS);
4741                                 }
4742                                 break;
4743                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4744                                 if (print) {
4745                                         _print_next_block((*par_num)++, "UCM");
4746                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4747                                 }
4748                                 break;
4749                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4750                                 if (print) {
4751                                         _print_next_block((*par_num)++,
4752                                                           "USEMI");
4753                                         _print_parity(bp,
4754                                                       USEM_REG_USEM_PRTY_STS_0);
4755                                         _print_parity(bp,
4756                                                       USEM_REG_USEM_PRTY_STS_1);
4757                                 }
4758                                 break;
4759                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4760                                 if (print) {
4761                                         _print_next_block((*par_num)++, "UPB");
4762                                         _print_parity(bp, GRCBASE_UPB +
4763                                                           PB_REG_PB_PRTY_STS);
4764                                 }
4765                                 break;
4766                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4767                                 if (print) {
4768                                         _print_next_block((*par_num)++, "CSDM");
4769                                         _print_parity(bp,
4770                                                       CSDM_REG_CSDM_PRTY_STS);
4771                                 }
4772                                 break;
4773                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4774                                 if (print) {
4775                                         _print_next_block((*par_num)++, "CCM");
4776                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4777                                 }
4778                                 break;
4779                         }
4780
4781                         /* Clear the bit */
4782                         sig &= ~cur_bit;
4783                 }
4784         }
4785
4786         return res;
4787 }
4788
4789 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4790                                             int *par_num, bool print)
4791 {
4792         u32 cur_bit;
4793         bool res;
4794         int i;
4795
4796         res = false;
4797
4798         for (i = 0; sig; i++) {
4799                 cur_bit = (0x1UL << i);
4800                 if (sig & cur_bit) {
4801                         res = true; /* Each bit is real error! */
4802                         if (print) {
4803                                 switch (cur_bit) {
4804                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4805                                         _print_next_block((*par_num)++,
4806                                                           "CSEMI");
4807                                         _print_parity(bp,
4808                                                       CSEM_REG_CSEM_PRTY_STS_0);
4809                                         _print_parity(bp,
4810                                                       CSEM_REG_CSEM_PRTY_STS_1);
4811                                         break;
4812                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4813                                         _print_next_block((*par_num)++, "PXP");
4814                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4815                                         _print_parity(bp,
4816                                                       PXP2_REG_PXP2_PRTY_STS_0);
4817                                         _print_parity(bp,
4818                                                       PXP2_REG_PXP2_PRTY_STS_1);
4819                                         break;
4820                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4821                                         _print_next_block((*par_num)++,
4822                                                           "PXPPCICLOCKCLIENT");
4823                                         break;
4824                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4825                                         _print_next_block((*par_num)++, "CFC");
4826                                         _print_parity(bp,
4827                                                       CFC_REG_CFC_PRTY_STS);
4828                                         break;
4829                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4830                                         _print_next_block((*par_num)++, "CDU");
4831                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4832                                         break;
4833                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4834                                         _print_next_block((*par_num)++, "DMAE");
4835                                         _print_parity(bp,
4836                                                       DMAE_REG_DMAE_PRTY_STS);
4837                                         break;
4838                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4839                                         _print_next_block((*par_num)++, "IGU");
4840                                         if (CHIP_IS_E1x(bp))
4841                                                 _print_parity(bp,
4842                                                         HC_REG_HC_PRTY_STS);
4843                                         else
4844                                                 _print_parity(bp,
4845                                                         IGU_REG_IGU_PRTY_STS);
4846                                         break;
4847                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4848                                         _print_next_block((*par_num)++, "MISC");
4849                                         _print_parity(bp,
4850                                                       MISC_REG_MISC_PRTY_STS);
4851                                         break;
4852                                 }
4853                         }
4854
4855                         /* Clear the bit */
4856                         sig &= ~cur_bit;
4857                 }
4858         }
4859
4860         return res;
4861 }
4862
4863 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4864                                             int *par_num, bool *global,
4865                                             bool print)
4866 {
4867         bool res = false;
4868         u32 cur_bit;
4869         int i;
4870
4871         for (i = 0; sig; i++) {
4872                 cur_bit = (0x1UL << i);
4873                 if (sig & cur_bit) {
4874                         switch (cur_bit) {
4875                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4876                                 if (print)
4877                                         _print_next_block((*par_num)++,
4878                                                           "MCP ROM");
4879                                 *global = true;
4880                                 res = true;
4881                                 break;
4882                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4883                                 if (print)
4884                                         _print_next_block((*par_num)++,
4885                                                           "MCP UMP RX");
4886                                 *global = true;
4887                                 res = true;
4888                                 break;
4889                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4890                                 if (print)
4891                                         _print_next_block((*par_num)++,
4892                                                           "MCP UMP TX");
4893                                 *global = true;
4894                                 res = true;
4895                                 break;
4896                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4897                                 (*par_num)++;
4898                                 /* clear latched SCPAD PATIRY from MCP */
4899                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4900                                        1UL << 10);
4901                                 break;
4902                         }
4903
4904                         /* Clear the bit */
4905                         sig &= ~cur_bit;
4906                 }
4907         }
4908
4909         return res;
4910 }
4911
4912 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4913                                             int *par_num, bool print)
4914 {
4915         u32 cur_bit;
4916         bool res;
4917         int i;
4918
4919         res = false;
4920
4921         for (i = 0; sig; i++) {
4922                 cur_bit = (0x1UL << i);
4923                 if (sig & cur_bit) {
4924                         res = true; /* Each bit is real error! */
4925                         if (print) {
4926                                 switch (cur_bit) {
4927                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4928                                         _print_next_block((*par_num)++,
4929                                                           "PGLUE_B");
4930                                         _print_parity(bp,
4931                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4932                                         break;
4933                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4934                                         _print_next_block((*par_num)++, "ATC");
4935                                         _print_parity(bp,
4936                                                       ATC_REG_ATC_PRTY_STS);
4937                                         break;
4938                                 }
4939                         }
4940                         /* Clear the bit */
4941                         sig &= ~cur_bit;
4942                 }
4943         }
4944
4945         return res;
4946 }
4947
4948 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4949                               u32 *sig)
4950 {
4951         bool res = false;
4952
4953         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4954             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4955             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4956             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4957             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4958                 int par_num = 0;
4959
4960                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4961                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4962                           sig[0] & HW_PRTY_ASSERT_SET_0,
4963                           sig[1] & HW_PRTY_ASSERT_SET_1,
4964                           sig[2] & HW_PRTY_ASSERT_SET_2,
4965                           sig[3] & HW_PRTY_ASSERT_SET_3,
4966                           sig[4] & HW_PRTY_ASSERT_SET_4);
4967                 if (print) {
4968                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4969                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4970                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4971                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4972                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4973                                 netdev_err(bp->dev,
4974                                            "Parity errors detected in blocks: ");
4975                         } else {
4976                                 print = false;
4977                         }
4978                 }
4979                 res |= bnx2x_check_blocks_with_parity0(bp,
4980                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4981                 res |= bnx2x_check_blocks_with_parity1(bp,
4982                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4983                 res |= bnx2x_check_blocks_with_parity2(bp,
4984                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4985                 res |= bnx2x_check_blocks_with_parity3(bp,
4986                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4987                 res |= bnx2x_check_blocks_with_parity4(bp,
4988                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4989
4990                 if (print)
4991                         pr_cont("\n");
4992         }
4993
4994         return res;
4995 }
4996
4997 /**
4998  * bnx2x_chk_parity_attn - checks for parity attentions.
4999  *
5000  * @bp:         driver handle
5001  * @global:     true if there was a global attention
5002  * @print:      show parity attention in syslog
5003  */
5004 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5005 {
5006         struct attn_route attn = { {0} };
5007         int port = BP_PORT(bp);
5008
5009         attn.sig[0] = REG_RD(bp,
5010                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5011                              port*4);
5012         attn.sig[1] = REG_RD(bp,
5013                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5014                              port*4);
5015         attn.sig[2] = REG_RD(bp,
5016                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5017                              port*4);
5018         attn.sig[3] = REG_RD(bp,
5019                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5020                              port*4);
5021         /* Since MCP attentions can't be disabled inside the block, we need to
5022          * read AEU registers to see whether they're currently disabled
5023          */
5024         attn.sig[3] &= ((REG_RD(bp,
5025                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5026                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5027                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5028                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5029
5030         if (!CHIP_IS_E1x(bp))
5031                 attn.sig[4] = REG_RD(bp,
5032                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5033                                      port*4);
5034
5035         return bnx2x_parity_attn(bp, global, print, attn.sig);
5036 }
5037
5038 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5039 {
5040         u32 val;
5041         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5042
5043                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5044                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5045                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5046                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5047                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5048                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5049                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5050                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5051                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5052                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5053                 if (val &
5054                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5055                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5056                 if (val &
5057                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5058                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5059                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5060                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5061                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5062                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5063                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5064                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5065         }
5066         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5067                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5068                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5069                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5070                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5071                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5072                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5073                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5074                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5075                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5076                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5077                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5078                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5079                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5080                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5081         }
5082
5083         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5084                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5085                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5086                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5087                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5088         }
5089 }
5090
5091 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5092 {
5093         struct attn_route attn, *group_mask;
5094         int port = BP_PORT(bp);
5095         int index;
5096         u32 reg_addr;
5097         u32 val;
5098         u32 aeu_mask;
5099         bool global = false;
5100
5101         /* need to take HW lock because MCP or other port might also
5102            try to handle this event */
5103         bnx2x_acquire_alr(bp);
5104
5105         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5106 #ifndef BNX2X_STOP_ON_ERROR
5107                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5108                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5109                 /* Disable HW interrupts */
5110                 bnx2x_int_disable(bp);
5111                 /* In case of parity errors don't handle attentions so that
5112                  * other function would "see" parity errors.
5113                  */
5114 #else
5115                 bnx2x_panic();
5116 #endif
5117                 bnx2x_release_alr(bp);
5118                 return;
5119         }
5120
5121         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5122         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5123         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5124         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5125         if (!CHIP_IS_E1x(bp))
5126                 attn.sig[4] =
5127                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5128         else
5129                 attn.sig[4] = 0;
5130
5131         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5132            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5133
5134         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5135                 if (deasserted & (1 << index)) {
5136                         group_mask = &bp->attn_group[index];
5137
5138                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5139                            index,
5140                            group_mask->sig[0], group_mask->sig[1],
5141                            group_mask->sig[2], group_mask->sig[3],
5142                            group_mask->sig[4]);
5143
5144                         bnx2x_attn_int_deasserted4(bp,
5145                                         attn.sig[4] & group_mask->sig[4]);
5146                         bnx2x_attn_int_deasserted3(bp,
5147                                         attn.sig[3] & group_mask->sig[3]);
5148                         bnx2x_attn_int_deasserted1(bp,
5149                                         attn.sig[1] & group_mask->sig[1]);
5150                         bnx2x_attn_int_deasserted2(bp,
5151                                         attn.sig[2] & group_mask->sig[2]);
5152                         bnx2x_attn_int_deasserted0(bp,
5153                                         attn.sig[0] & group_mask->sig[0]);
5154                 }
5155         }
5156
5157         bnx2x_release_alr(bp);
5158
5159         if (bp->common.int_block == INT_BLOCK_HC)
5160                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5161                             COMMAND_REG_ATTN_BITS_CLR);
5162         else
5163                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5164
5165         val = ~deasserted;
5166         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5167            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5168         REG_WR(bp, reg_addr, val);
5169
5170         if (~bp->attn_state & deasserted)
5171                 BNX2X_ERR("IGU ERROR\n");
5172
5173         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5174                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5175
5176         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5177         aeu_mask = REG_RD(bp, reg_addr);
5178
5179         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5180            aeu_mask, deasserted);
5181         aeu_mask |= (deasserted & 0x3ff);
5182         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5183
5184         REG_WR(bp, reg_addr, aeu_mask);
5185         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5186
5187         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5188         bp->attn_state &= ~deasserted;
5189         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5190 }
5191
5192 static void bnx2x_attn_int(struct bnx2x *bp)
5193 {
5194         /* read local copy of bits */
5195         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5196                                                                 attn_bits);
5197         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5198                                                                 attn_bits_ack);
5199         u32 attn_state = bp->attn_state;
5200
5201         /* look for changed bits */
5202         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5203         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5204
5205         DP(NETIF_MSG_HW,
5206            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5207            attn_bits, attn_ack, asserted, deasserted);
5208
5209         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5210                 BNX2X_ERR("BAD attention state\n");
5211
5212         /* handle bits that were raised */
5213         if (asserted)
5214                 bnx2x_attn_int_asserted(bp, asserted);
5215
5216         if (deasserted)
5217                 bnx2x_attn_int_deasserted(bp, deasserted);
5218 }
5219
5220 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5221                       u16 index, u8 op, u8 update)
5222 {
5223         u32 igu_addr = bp->igu_base_addr;
5224         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5225         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5226                              igu_addr);
5227 }
5228
5229 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5230 {
5231         /* No memory barriers */
5232         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5233 }
5234
5235 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5236                                       union event_ring_elem *elem)
5237 {
5238         u8 err = elem->message.error;
5239
5240         if (!bp->cnic_eth_dev.starting_cid  ||
5241             (cid < bp->cnic_eth_dev.starting_cid &&
5242             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5243                 return 1;
5244
5245         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5246
5247         if (unlikely(err)) {
5248
5249                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5250                           cid);
5251                 bnx2x_panic_dump(bp, false);
5252         }
5253         bnx2x_cnic_cfc_comp(bp, cid, err);
5254         return 0;
5255 }
5256
5257 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5258 {
5259         struct bnx2x_mcast_ramrod_params rparam;
5260         int rc;
5261
5262         memset(&rparam, 0, sizeof(rparam));
5263
5264         rparam.mcast_obj = &bp->mcast_obj;
5265
5266         netif_addr_lock_bh(bp->dev);
5267
5268         /* Clear pending state for the last command */
5269         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5270
5271         /* If there are pending mcast commands - send them */
5272         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5273                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5274                 if (rc < 0)
5275                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5276                                   rc);
5277         }
5278
5279         netif_addr_unlock_bh(bp->dev);
5280 }
5281
5282 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5283                                             union event_ring_elem *elem)
5284 {
5285         unsigned long ramrod_flags = 0;
5286         int rc = 0;
5287         u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5288         u32 cid = echo & BNX2X_SWCID_MASK;
5289         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5290
5291         /* Always push next commands out, don't wait here */
5292         __set_bit(RAMROD_CONT, &ramrod_flags);
5293
5294         switch (echo >> BNX2X_SWCID_SHIFT) {
5295         case BNX2X_FILTER_MAC_PENDING:
5296                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5297                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5298                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5299                 else
5300                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5301
5302                 break;
5303         case BNX2X_FILTER_VLAN_PENDING:
5304                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5305                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5306                 break;
5307         case BNX2X_FILTER_MCAST_PENDING:
5308                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5309                 /* This is only relevant for 57710 where multicast MACs are
5310                  * configured as unicast MACs using the same ramrod.
5311                  */
5312                 bnx2x_handle_mcast_eqe(bp);
5313                 return;
5314         default:
5315                 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
5316                 return;
5317         }
5318
5319         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5320
5321         if (rc < 0)
5322                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5323         else if (rc > 0)
5324                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5325 }
5326
5327 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5328
5329 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5330 {
5331         netif_addr_lock_bh(bp->dev);
5332
5333         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5334
5335         /* Send rx_mode command again if was requested */
5336         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5337                 bnx2x_set_storm_rx_mode(bp);
5338         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5339                                     &bp->sp_state))
5340                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5341         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5342                                     &bp->sp_state))
5343                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5344
5345         netif_addr_unlock_bh(bp->dev);
5346 }
5347
5348 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5349                                               union event_ring_elem *elem)
5350 {
5351         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5352                 DP(BNX2X_MSG_SP,
5353                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5354                    elem->message.data.vif_list_event.func_bit_map);
5355                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5356                         elem->message.data.vif_list_event.func_bit_map);
5357         } else if (elem->message.data.vif_list_event.echo ==
5358                    VIF_LIST_RULE_SET) {
5359                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5360                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5361         }
5362 }
5363
5364 /* called with rtnl_lock */
5365 static void bnx2x_after_function_update(struct bnx2x *bp)
5366 {
5367         int q, rc;
5368         struct bnx2x_fastpath *fp;
5369         struct bnx2x_queue_state_params queue_params = {NULL};
5370         struct bnx2x_queue_update_params *q_update_params =
5371                 &queue_params.params.update;
5372
5373         /* Send Q update command with afex vlan removal values for all Qs */
5374         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5375
5376         /* set silent vlan removal values according to vlan mode */
5377         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5378                   &q_update_params->update_flags);
5379         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5380                   &q_update_params->update_flags);
5381         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5382
5383         /* in access mode mark mask and value are 0 to strip all vlans */
5384         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5385                 q_update_params->silent_removal_value = 0;
5386                 q_update_params->silent_removal_mask = 0;
5387         } else {
5388                 q_update_params->silent_removal_value =
5389                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5390                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5391         }
5392
5393         for_each_eth_queue(bp, q) {
5394                 /* Set the appropriate Queue object */
5395                 fp = &bp->fp[q];
5396                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5397
5398                 /* send the ramrod */
5399                 rc = bnx2x_queue_state_change(bp, &queue_params);
5400                 if (rc < 0)
5401                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5402                                   q);
5403         }
5404
5405         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5406                 fp = &bp->fp[FCOE_IDX(bp)];
5407                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5408
5409                 /* clear pending completion bit */
5410                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5411
5412                 /* mark latest Q bit */
5413                 smp_mb__before_atomic();
5414                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5415                 smp_mb__after_atomic();
5416
5417                 /* send Q update ramrod for FCoE Q */
5418                 rc = bnx2x_queue_state_change(bp, &queue_params);
5419                 if (rc < 0)
5420                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5421                                   q);
5422         } else {
5423                 /* If no FCoE ring - ACK MCP now */
5424                 bnx2x_link_report(bp);
5425                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5426         }
5427 }
5428
5429 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5430         struct bnx2x *bp, u32 cid)
5431 {
5432         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5433
5434         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5435                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5436         else
5437                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5438 }
5439
5440 static void bnx2x_eq_int(struct bnx2x *bp)
5441 {
5442         u16 hw_cons, sw_cons, sw_prod;
5443         union event_ring_elem *elem;
5444         u8 echo;
5445         u32 cid;
5446         u8 opcode;
5447         int rc, spqe_cnt = 0;
5448         struct bnx2x_queue_sp_obj *q_obj;
5449         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5450         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5451
5452         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5453
5454         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5455          * when we get the next-page we need to adjust so the loop
5456          * condition below will be met. The next element is the size of a
5457          * regular element and hence incrementing by 1
5458          */
5459         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5460                 hw_cons++;
5461
5462         /* This function may never run in parallel with itself for a
5463          * specific bp, thus there is no need in "paired" read memory
5464          * barrier here.
5465          */
5466         sw_cons = bp->eq_cons;
5467         sw_prod = bp->eq_prod;
5468
5469         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5470                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5471
5472         for (; sw_cons != hw_cons;
5473               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5474
5475                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5476
5477                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5478                 if (!rc) {
5479                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5480                            rc);
5481                         goto next_spqe;
5482                 }
5483
5484                 opcode = elem->message.opcode;
5485
5486                 /* handle eq element */
5487                 switch (opcode) {
5488                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5489                         bnx2x_vf_mbx_schedule(bp,
5490                                               &elem->message.data.vf_pf_event);
5491                         continue;
5492
5493                 case EVENT_RING_OPCODE_STAT_QUERY:
5494                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5495                                "got statistics comp event %d\n",
5496                                bp->stats_comp++);
5497                         /* nothing to do with stats comp */
5498                         goto next_spqe;
5499
5500                 case EVENT_RING_OPCODE_CFC_DEL:
5501                         /* handle according to cid range */
5502                         /*
5503                          * we may want to verify here that the bp state is
5504                          * HALTING
5505                          */
5506
5507                         /* elem CID originates from FW; actually LE */
5508                         cid = SW_CID(elem->message.data.cfc_del_event.cid);
5509
5510                         DP(BNX2X_MSG_SP,
5511                            "got delete ramrod for MULTI[%d]\n", cid);
5512
5513                         if (CNIC_LOADED(bp) &&
5514                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5515                                 goto next_spqe;
5516
5517                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5518
5519                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5520                                 break;
5521
5522                         goto next_spqe;
5523
5524                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5525                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5526                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5527                         if (f_obj->complete_cmd(bp, f_obj,
5528                                                 BNX2X_F_CMD_TX_STOP))
5529                                 break;
5530                         goto next_spqe;
5531
5532                 case EVENT_RING_OPCODE_START_TRAFFIC:
5533                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5534                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5535                         if (f_obj->complete_cmd(bp, f_obj,
5536                                                 BNX2X_F_CMD_TX_START))
5537                                 break;
5538                         goto next_spqe;
5539
5540                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5541                         echo = elem->message.data.function_update_event.echo;
5542                         if (echo == SWITCH_UPDATE) {
5543                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5544                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5545                                 if (f_obj->complete_cmd(
5546                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5547                                         break;
5548
5549                         } else {
5550                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5551
5552                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5553                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5554                                 f_obj->complete_cmd(bp, f_obj,
5555                                                     BNX2X_F_CMD_AFEX_UPDATE);
5556
5557                                 /* We will perform the Queues update from
5558                                  * sp_rtnl task as all Queue SP operations
5559                                  * should run under rtnl_lock.
5560                                  */
5561                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5562                         }
5563
5564                         goto next_spqe;
5565
5566                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5567                         f_obj->complete_cmd(bp, f_obj,
5568                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5569                         bnx2x_after_afex_vif_lists(bp, elem);
5570                         goto next_spqe;
5571                 case EVENT_RING_OPCODE_FUNCTION_START:
5572                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5573                            "got FUNC_START ramrod\n");
5574                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5575                                 break;
5576
5577                         goto next_spqe;
5578
5579                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5580                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5581                            "got FUNC_STOP ramrod\n");
5582                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5583                                 break;
5584
5585                         goto next_spqe;
5586
5587                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5588                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5589                            "got set_timesync ramrod completion\n");
5590                         if (f_obj->complete_cmd(bp, f_obj,
5591                                                 BNX2X_F_CMD_SET_TIMESYNC))
5592                                 break;
5593                         goto next_spqe;
5594                 }
5595
5596                 switch (opcode | bp->state) {
5597                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598                       BNX2X_STATE_OPEN):
5599                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5600                       BNX2X_STATE_OPENING_WAIT4_PORT):
5601                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5602                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5603                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5604                            SW_CID(elem->message.data.eth_event.echo));
5605                         rss_raw->clear_pending(rss_raw);
5606                         break;
5607
5608                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5609                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5610                 case (EVENT_RING_OPCODE_SET_MAC |
5611                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5612                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5613                       BNX2X_STATE_OPEN):
5614                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615                       BNX2X_STATE_DIAG):
5616                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5617                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5618                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5619                         bnx2x_handle_classification_eqe(bp, elem);
5620                         break;
5621
5622                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5623                       BNX2X_STATE_OPEN):
5624                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625                       BNX2X_STATE_DIAG):
5626                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5627                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5628                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5629                         bnx2x_handle_mcast_eqe(bp);
5630                         break;
5631
5632                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5633                       BNX2X_STATE_OPEN):
5634                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5635                       BNX2X_STATE_DIAG):
5636                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5637                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5638                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5639                         bnx2x_handle_rx_mode_eqe(bp);
5640                         break;
5641                 default:
5642                         /* unknown event log error and continue */
5643                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5644                                   elem->message.opcode, bp->state);
5645                 }
5646 next_spqe:
5647                 spqe_cnt++;
5648         } /* for */
5649
5650         smp_mb__before_atomic();
5651         atomic_add(spqe_cnt, &bp->eq_spq_left);
5652
5653         bp->eq_cons = sw_cons;
5654         bp->eq_prod = sw_prod;
5655         /* Make sure that above mem writes were issued towards the memory */
5656         smp_wmb();
5657
5658         /* update producer */
5659         bnx2x_update_eq_prod(bp, bp->eq_prod);
5660 }
5661
5662 static void bnx2x_sp_task(struct work_struct *work)
5663 {
5664         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5665
5666         DP(BNX2X_MSG_SP, "sp task invoked\n");
5667
5668         /* make sure the atomic interrupt_occurred has been written */
5669         smp_rmb();
5670         if (atomic_read(&bp->interrupt_occurred)) {
5671
5672                 /* what work needs to be performed? */
5673                 u16 status = bnx2x_update_dsb_idx(bp);
5674
5675                 DP(BNX2X_MSG_SP, "status %x\n", status);
5676                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5677                 atomic_set(&bp->interrupt_occurred, 0);
5678
5679                 /* HW attentions */
5680                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5681                         bnx2x_attn_int(bp);
5682                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5683                 }
5684
5685                 /* SP events: STAT_QUERY and others */
5686                 if (status & BNX2X_DEF_SB_IDX) {
5687                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5688
5689                         if (FCOE_INIT(bp) &&
5690                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5691                                 /* Prevent local bottom-halves from running as
5692                                  * we are going to change the local NAPI list.
5693                                  */
5694                                 local_bh_disable();
5695                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5696                                 local_bh_enable();
5697                         }
5698
5699                         /* Handle EQ completions */
5700                         bnx2x_eq_int(bp);
5701                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5702                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5703
5704                         status &= ~BNX2X_DEF_SB_IDX;
5705                 }
5706
5707                 /* if status is non zero then perhaps something went wrong */
5708                 if (unlikely(status))
5709                         DP(BNX2X_MSG_SP,
5710                            "got an unknown interrupt! (status 0x%x)\n", status);
5711
5712                 /* ack status block only if something was actually handled */
5713                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5714                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5715         }
5716
5717         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5718         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5719                                &bp->sp_state)) {
5720                 bnx2x_link_report(bp);
5721                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5722         }
5723 }
5724
5725 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5726 {
5727         struct net_device *dev = dev_instance;
5728         struct bnx2x *bp = netdev_priv(dev);
5729
5730         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5731                      IGU_INT_DISABLE, 0);
5732
5733 #ifdef BNX2X_STOP_ON_ERROR
5734         if (unlikely(bp->panic))
5735                 return IRQ_HANDLED;
5736 #endif
5737
5738         if (CNIC_LOADED(bp)) {
5739                 struct cnic_ops *c_ops;
5740
5741                 rcu_read_lock();
5742                 c_ops = rcu_dereference(bp->cnic_ops);
5743                 if (c_ops)
5744                         c_ops->cnic_handler(bp->cnic_data, NULL);
5745                 rcu_read_unlock();
5746         }
5747
5748         /* schedule sp task to perform default status block work, ack
5749          * attentions and enable interrupts.
5750          */
5751         bnx2x_schedule_sp_task(bp);
5752
5753         return IRQ_HANDLED;
5754 }
5755
5756 /* end of slow path */
5757
5758 void bnx2x_drv_pulse(struct bnx2x *bp)
5759 {
5760         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5761                  bp->fw_drv_pulse_wr_seq);
5762 }
5763
5764 static void bnx2x_timer(struct timer_list *t)
5765 {
5766         struct bnx2x *bp = from_timer(bp, t, timer);
5767
5768         if (!netif_running(bp->dev))
5769                 return;
5770
5771         if (IS_PF(bp) &&
5772             !BP_NOMCP(bp)) {
5773                 int mb_idx = BP_FW_MB_IDX(bp);
5774                 u16 drv_pulse;
5775                 u16 mcp_pulse;
5776
5777                 ++bp->fw_drv_pulse_wr_seq;
5778                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5779                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5780                 bnx2x_drv_pulse(bp);
5781
5782                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5783                              MCP_PULSE_SEQ_MASK);
5784                 /* The delta between driver pulse and mcp response
5785                  * should not get too big. If the MFW is more than 5 pulses
5786                  * behind, we should worry about it enough to generate an error
5787                  * log.
5788                  */
5789                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5790                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5791                                   drv_pulse, mcp_pulse);
5792         }
5793
5794         if (bp->state == BNX2X_STATE_OPEN)
5795                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5796
5797         /* sample pf vf bulletin board for new posts from pf */
5798         if (IS_VF(bp))
5799                 bnx2x_timer_sriov(bp);
5800
5801         mod_timer(&bp->timer, jiffies + bp->current_interval);
5802 }
5803
5804 /* end of Statistics */
5805
5806 /* nic init */
5807
5808 /*
5809  * nic init service functions
5810  */
5811
5812 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5813 {
5814         u32 i;
5815         if (!(len%4) && !(addr%4))
5816                 for (i = 0; i < len; i += 4)
5817                         REG_WR(bp, addr + i, fill);
5818         else
5819                 for (i = 0; i < len; i++)
5820                         REG_WR8(bp, addr + i, fill);
5821 }
5822
5823 /* helper: writes FP SP data to FW - data_size in dwords */
5824 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5825                                 int fw_sb_id,
5826                                 u32 *sb_data_p,
5827                                 u32 data_size)
5828 {
5829         int index;
5830         for (index = 0; index < data_size; index++)
5831                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5832                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5833                         sizeof(u32)*index,
5834                         *(sb_data_p + index));
5835 }
5836
5837 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5838 {
5839         u32 *sb_data_p;
5840         u32 data_size = 0;
5841         struct hc_status_block_data_e2 sb_data_e2;
5842         struct hc_status_block_data_e1x sb_data_e1x;
5843
5844         /* disable the function first */
5845         if (!CHIP_IS_E1x(bp)) {
5846                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5847                 sb_data_e2.common.state = SB_DISABLED;
5848                 sb_data_e2.common.p_func.vf_valid = false;
5849                 sb_data_p = (u32 *)&sb_data_e2;
5850                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5851         } else {
5852                 memset(&sb_data_e1x, 0,
5853                        sizeof(struct hc_status_block_data_e1x));
5854                 sb_data_e1x.common.state = SB_DISABLED;
5855                 sb_data_e1x.common.p_func.vf_valid = false;
5856                 sb_data_p = (u32 *)&sb_data_e1x;
5857                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5858         }
5859         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5860
5861         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5862                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5863                         CSTORM_STATUS_BLOCK_SIZE);
5864         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5865                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5866                         CSTORM_SYNC_BLOCK_SIZE);
5867 }
5868
5869 /* helper:  writes SP SB data to FW */
5870 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5871                 struct hc_sp_status_block_data *sp_sb_data)
5872 {
5873         int func = BP_FUNC(bp);
5874         int i;
5875         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5876                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5877                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5878                         i*sizeof(u32),
5879                         *((u32 *)sp_sb_data + i));
5880 }
5881
5882 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5883 {
5884         int func = BP_FUNC(bp);
5885         struct hc_sp_status_block_data sp_sb_data;
5886         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5887
5888         sp_sb_data.state = SB_DISABLED;
5889         sp_sb_data.p_func.vf_valid = false;
5890
5891         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5892
5893         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5894                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5895                         CSTORM_SP_STATUS_BLOCK_SIZE);
5896         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5897                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5898                         CSTORM_SP_SYNC_BLOCK_SIZE);
5899 }
5900
5901 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5902                                            int igu_sb_id, int igu_seg_id)
5903 {
5904         hc_sm->igu_sb_id = igu_sb_id;
5905         hc_sm->igu_seg_id = igu_seg_id;
5906         hc_sm->timer_value = 0xFF;
5907         hc_sm->time_to_expire = 0xFFFFFFFF;
5908 }
5909
5910 /* allocates state machine ids. */
5911 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5912 {
5913         /* zero out state machine indices */
5914         /* rx indices */
5915         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5916
5917         /* tx indices */
5918         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5919         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5920         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5921         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5922
5923         /* map indices */
5924         /* rx indices */
5925         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5926                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5927
5928         /* tx indices */
5929         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5930                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5932                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5934                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5936                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5937 }
5938
5939 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5940                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5941 {
5942         int igu_seg_id;
5943
5944         struct hc_status_block_data_e2 sb_data_e2;
5945         struct hc_status_block_data_e1x sb_data_e1x;
5946         struct hc_status_block_sm  *hc_sm_p;
5947         int data_size;
5948         u32 *sb_data_p;
5949
5950         if (CHIP_INT_MODE_IS_BC(bp))
5951                 igu_seg_id = HC_SEG_ACCESS_NORM;
5952         else
5953                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5954
5955         bnx2x_zero_fp_sb(bp, fw_sb_id);
5956
5957         if (!CHIP_IS_E1x(bp)) {
5958                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5959                 sb_data_e2.common.state = SB_ENABLED;
5960                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5961                 sb_data_e2.common.p_func.vf_id = vfid;
5962                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5963                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5964                 sb_data_e2.common.same_igu_sb_1b = true;
5965                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5966                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5967                 hc_sm_p = sb_data_e2.common.state_machine;
5968                 sb_data_p = (u32 *)&sb_data_e2;
5969                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5970                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5971         } else {
5972                 memset(&sb_data_e1x, 0,
5973                        sizeof(struct hc_status_block_data_e1x));
5974                 sb_data_e1x.common.state = SB_ENABLED;
5975                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5976                 sb_data_e1x.common.p_func.vf_id = 0xff;
5977                 sb_data_e1x.common.p_func.vf_valid = false;
5978                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5979                 sb_data_e1x.common.same_igu_sb_1b = true;
5980                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5981                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5982                 hc_sm_p = sb_data_e1x.common.state_machine;
5983                 sb_data_p = (u32 *)&sb_data_e1x;
5984                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5985                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5986         }
5987
5988         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5989                                        igu_sb_id, igu_seg_id);
5990         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5991                                        igu_sb_id, igu_seg_id);
5992
5993         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5994
5995         /* write indices to HW - PCI guarantees endianity of regpairs */
5996         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5997 }
5998
5999 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6000                                      u16 tx_usec, u16 rx_usec)
6001 {
6002         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6003                                     false, rx_usec);
6004         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6005                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6006                                        tx_usec);
6007         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6008                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6009                                        tx_usec);
6010         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6011                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6012                                        tx_usec);
6013 }
6014
6015 static void bnx2x_init_def_sb(struct bnx2x *bp)
6016 {
6017         struct host_sp_status_block *def_sb = bp->def_status_blk;
6018         dma_addr_t mapping = bp->def_status_blk_mapping;
6019         int igu_sp_sb_index;
6020         int igu_seg_id;
6021         int port = BP_PORT(bp);
6022         int func = BP_FUNC(bp);
6023         int reg_offset, reg_offset_en5;
6024         u64 section;
6025         int index;
6026         struct hc_sp_status_block_data sp_sb_data;
6027         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6028
6029         if (CHIP_INT_MODE_IS_BC(bp)) {
6030                 igu_sp_sb_index = DEF_SB_IGU_ID;
6031                 igu_seg_id = HC_SEG_ACCESS_DEF;
6032         } else {
6033                 igu_sp_sb_index = bp->igu_dsb_id;
6034                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6035         }
6036
6037         /* ATTN */
6038         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6039                                             atten_status_block);
6040         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6041
6042         bp->attn_state = 0;
6043
6044         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6045                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6046         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6047                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6048         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6049                 int sindex;
6050                 /* take care of sig[0]..sig[4] */
6051                 for (sindex = 0; sindex < 4; sindex++)
6052                         bp->attn_group[index].sig[sindex] =
6053                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6054
6055                 if (!CHIP_IS_E1x(bp))
6056                         /*
6057                          * enable5 is separate from the rest of the registers,
6058                          * and therefore the address skip is 4
6059                          * and not 16 between the different groups
6060                          */
6061                         bp->attn_group[index].sig[4] = REG_RD(bp,
6062                                         reg_offset_en5 + 0x4*index);
6063                 else
6064                         bp->attn_group[index].sig[4] = 0;
6065         }
6066
6067         if (bp->common.int_block == INT_BLOCK_HC) {
6068                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6069                                      HC_REG_ATTN_MSG0_ADDR_L);
6070
6071                 REG_WR(bp, reg_offset, U64_LO(section));
6072                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6073         } else if (!CHIP_IS_E1x(bp)) {
6074                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6075                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6076         }
6077
6078         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6079                                             sp_sb);
6080
6081         bnx2x_zero_sp_sb(bp);
6082
6083         /* PCI guarantees endianity of regpairs */
6084         sp_sb_data.state                = SB_ENABLED;
6085         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6086         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6087         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6088         sp_sb_data.igu_seg_id           = igu_seg_id;
6089         sp_sb_data.p_func.pf_id         = func;
6090         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6091         sp_sb_data.p_func.vf_id         = 0xff;
6092
6093         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6094
6095         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6096 }
6097
6098 void bnx2x_update_coalesce(struct bnx2x *bp)
6099 {
6100         int i;
6101
6102         for_each_eth_queue(bp, i)
6103                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6104                                          bp->tx_ticks, bp->rx_ticks);
6105 }
6106
6107 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6108 {
6109         spin_lock_init(&bp->spq_lock);
6110         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6111
6112         bp->spq_prod_idx = 0;
6113         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6114         bp->spq_prod_bd = bp->spq;
6115         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6116 }
6117
6118 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6119 {
6120         int i;
6121         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6122                 union event_ring_elem *elem =
6123                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6124
6125                 elem->next_page.addr.hi =
6126                         cpu_to_le32(U64_HI(bp->eq_mapping +
6127                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6128                 elem->next_page.addr.lo =
6129                         cpu_to_le32(U64_LO(bp->eq_mapping +
6130                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6131         }
6132         bp->eq_cons = 0;
6133         bp->eq_prod = NUM_EQ_DESC;
6134         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6135         /* we want a warning message before it gets wrought... */
6136         atomic_set(&bp->eq_spq_left,
6137                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6138 }
6139
6140 /* called with netif_addr_lock_bh() */
6141 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6142                                unsigned long rx_mode_flags,
6143                                unsigned long rx_accept_flags,
6144                                unsigned long tx_accept_flags,
6145                                unsigned long ramrod_flags)
6146 {
6147         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6148         int rc;
6149
6150         memset(&ramrod_param, 0, sizeof(ramrod_param));
6151
6152         /* Prepare ramrod parameters */
6153         ramrod_param.cid = 0;
6154         ramrod_param.cl_id = cl_id;
6155         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6156         ramrod_param.func_id = BP_FUNC(bp);
6157
6158         ramrod_param.pstate = &bp->sp_state;
6159         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6160
6161         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6162         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6163
6164         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6165
6166         ramrod_param.ramrod_flags = ramrod_flags;
6167         ramrod_param.rx_mode_flags = rx_mode_flags;
6168
6169         ramrod_param.rx_accept_flags = rx_accept_flags;
6170         ramrod_param.tx_accept_flags = tx_accept_flags;
6171
6172         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6173         if (rc < 0) {
6174                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6175                 return rc;
6176         }
6177
6178         return 0;
6179 }
6180
6181 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6182                                    unsigned long *rx_accept_flags,
6183                                    unsigned long *tx_accept_flags)
6184 {
6185         /* Clear the flags first */
6186         *rx_accept_flags = 0;
6187         *tx_accept_flags = 0;
6188
6189         switch (rx_mode) {
6190         case BNX2X_RX_MODE_NONE:
6191                 /*
6192                  * 'drop all' supersedes any accept flags that may have been
6193                  * passed to the function.
6194                  */
6195                 break;
6196         case BNX2X_RX_MODE_NORMAL:
6197                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6198                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6199                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6200
6201                 /* internal switching mode */
6202                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6203                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6204                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6205
6206                 if (bp->accept_any_vlan) {
6207                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6208                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6209                 }
6210
6211                 break;
6212         case BNX2X_RX_MODE_ALLMULTI:
6213                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6214                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6215                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6216
6217                 /* internal switching mode */
6218                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6219                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6220                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6221
6222                 if (bp->accept_any_vlan) {
6223                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6224                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6225                 }
6226
6227                 break;
6228         case BNX2X_RX_MODE_PROMISC:
6229                 /* According to definition of SI mode, iface in promisc mode
6230                  * should receive matched and unmatched (in resolution of port)
6231                  * unicast packets.
6232                  */
6233                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6234                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6235                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6236                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6237
6238                 /* internal switching mode */
6239                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6240                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6241
6242                 if (IS_MF_SI(bp))
6243                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6244                 else
6245                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6246
6247                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6248                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6249
6250                 break;
6251         default:
6252                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6253                 return -EINVAL;
6254         }
6255
6256         return 0;
6257 }
6258
6259 /* called with netif_addr_lock_bh() */
6260 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6261 {
6262         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6263         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6264         int rc;
6265
6266         if (!NO_FCOE(bp))
6267                 /* Configure rx_mode of FCoE Queue */
6268                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6269
6270         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6271                                      &tx_accept_flags);
6272         if (rc)
6273                 return rc;
6274
6275         __set_bit(RAMROD_RX, &ramrod_flags);
6276         __set_bit(RAMROD_TX, &ramrod_flags);
6277
6278         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6279                                    rx_accept_flags, tx_accept_flags,
6280                                    ramrod_flags);
6281 }
6282
6283 static void bnx2x_init_internal_common(struct bnx2x *bp)
6284 {
6285         int i;
6286
6287         /* Zero this manually as its initialization is
6288            currently missing in the initTool */
6289         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6290                 REG_WR(bp, BAR_USTRORM_INTMEM +
6291                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6292         if (!CHIP_IS_E1x(bp)) {
6293                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6294                         CHIP_INT_MODE_IS_BC(bp) ?
6295                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6296         }
6297 }
6298
6299 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6300 {
6301         switch (load_code) {
6302         case FW_MSG_CODE_DRV_LOAD_COMMON:
6303         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6304                 bnx2x_init_internal_common(bp);
6305                 /* no break */
6306
6307         case FW_MSG_CODE_DRV_LOAD_PORT:
6308                 /* nothing to do */
6309                 /* no break */
6310
6311         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6312                 /* internal memory per function is
6313                    initialized inside bnx2x_pf_init */
6314                 break;
6315
6316         default:
6317                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6318                 break;
6319         }
6320 }
6321
6322 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6323 {
6324         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6325 }
6326
6327 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6328 {
6329         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6330 }
6331
6332 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6333 {
6334         if (CHIP_IS_E1x(fp->bp))
6335                 return BP_L_ID(fp->bp) + fp->index;
6336         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6337                 return bnx2x_fp_igu_sb_id(fp);
6338 }
6339
6340 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6341 {
6342         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6343         u8 cos;
6344         unsigned long q_type = 0;
6345         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6346         fp->rx_queue = fp_idx;
6347         fp->cid = fp_idx;
6348         fp->cl_id = bnx2x_fp_cl_id(fp);
6349         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6350         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6351         /* qZone id equals to FW (per path) client id */
6352         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6353
6354         /* init shortcut */
6355         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6356
6357         /* Setup SB indices */
6358         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6359
6360         /* Configure Queue State object */
6361         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6362         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6363
6364         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6365
6366         /* init tx data */
6367         for_each_cos_in_tx_queue(fp, cos) {
6368                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6369                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6370                                   FP_COS_TO_TXQ(fp, cos, bp),
6371                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6372                 cids[cos] = fp->txdata_ptr[cos]->cid;
6373         }
6374
6375         /* nothing more for vf to do here */
6376         if (IS_VF(bp))
6377                 return;
6378
6379         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6380                       fp->fw_sb_id, fp->igu_sb_id);
6381         bnx2x_update_fpsb_idx(fp);
6382         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6383                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6384                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6385
6386         /**
6387          * Configure classification DBs: Always enable Tx switching
6388          */
6389         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6390
6391         DP(NETIF_MSG_IFUP,
6392            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6393            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6394            fp->igu_sb_id);
6395 }
6396
6397 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6398 {
6399         int i;
6400
6401         for (i = 1; i <= NUM_TX_RINGS; i++) {
6402                 struct eth_tx_next_bd *tx_next_bd =
6403                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6404
6405                 tx_next_bd->addr_hi =
6406                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6407                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6408                 tx_next_bd->addr_lo =
6409                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6410                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6411         }
6412
6413         *txdata->tx_cons_sb = cpu_to_le16(0);
6414
6415         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6416         txdata->tx_db.data.zero_fill1 = 0;
6417         txdata->tx_db.data.prod = 0;
6418
6419         txdata->tx_pkt_prod = 0;
6420         txdata->tx_pkt_cons = 0;
6421         txdata->tx_bd_prod = 0;
6422         txdata->tx_bd_cons = 0;
6423         txdata->tx_pkt = 0;
6424 }
6425
6426 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6427 {
6428         int i;
6429
6430         for_each_tx_queue_cnic(bp, i)
6431                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6432 }
6433
6434 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6435 {
6436         int i;
6437         u8 cos;
6438
6439         for_each_eth_queue(bp, i)
6440                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6441                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6442 }
6443
6444 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6445 {
6446         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6447         unsigned long q_type = 0;
6448
6449         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6450         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6451                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6452         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6453         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6454         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6455         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6456         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6457                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6458                           fp);
6459
6460         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6461
6462         /* qZone id equals to FW (per path) client id */
6463         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6464         /* init shortcut */
6465         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6466                 bnx2x_rx_ustorm_prods_offset(fp);
6467
6468         /* Configure Queue State object */
6469         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6470         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6471
6472         /* No multi-CoS for FCoE L2 client */
6473         BUG_ON(fp->max_cos != 1);
6474
6475         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6476                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6477                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6478
6479         DP(NETIF_MSG_IFUP,
6480            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6481            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6482            fp->igu_sb_id);
6483 }
6484
6485 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6486 {
6487         if (!NO_FCOE(bp))
6488                 bnx2x_init_fcoe_fp(bp);
6489
6490         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6491                       BNX2X_VF_ID_INVALID, false,
6492                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6493
6494         /* ensure status block indices were read */
6495         rmb();
6496         bnx2x_init_rx_rings_cnic(bp);
6497         bnx2x_init_tx_rings_cnic(bp);
6498
6499         /* flush all */
6500         mb();
6501 }
6502
6503 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6504 {
6505         int i;
6506
6507         /* Setup NIC internals and enable interrupts */
6508         for_each_eth_queue(bp, i)
6509                 bnx2x_init_eth_fp(bp, i);
6510
6511         /* ensure status block indices were read */
6512         rmb();
6513         bnx2x_init_rx_rings(bp);
6514         bnx2x_init_tx_rings(bp);
6515
6516         if (IS_PF(bp)) {
6517                 /* Initialize MOD_ABS interrupts */
6518                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6519                                        bp->common.shmem_base,
6520                                        bp->common.shmem2_base, BP_PORT(bp));
6521
6522                 /* initialize the default status block and sp ring */
6523                 bnx2x_init_def_sb(bp);
6524                 bnx2x_update_dsb_idx(bp);
6525                 bnx2x_init_sp_ring(bp);
6526         } else {
6527                 bnx2x_memset_stats(bp);
6528         }
6529 }
6530
6531 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6532 {
6533         bnx2x_init_eq_ring(bp);
6534         bnx2x_init_internal(bp, load_code);
6535         bnx2x_pf_init(bp);
6536         bnx2x_stats_init(bp);
6537
6538         /* flush all before enabling interrupts */
6539         mb();
6540
6541         bnx2x_int_enable(bp);
6542
6543         /* Check for SPIO5 */
6544         bnx2x_attn_int_deasserted0(bp,
6545                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6546                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6547 }
6548
6549 /* gzip service functions */
6550 static int bnx2x_gunzip_init(struct bnx2x *bp)
6551 {
6552         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6553                                             &bp->gunzip_mapping, GFP_KERNEL);
6554         if (bp->gunzip_buf  == NULL)
6555                 goto gunzip_nomem1;
6556
6557         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6558         if (bp->strm  == NULL)
6559                 goto gunzip_nomem2;
6560
6561         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6562         if (bp->strm->workspace == NULL)
6563                 goto gunzip_nomem3;
6564
6565         return 0;
6566
6567 gunzip_nomem3:
6568         kfree(bp->strm);
6569         bp->strm = NULL;
6570
6571 gunzip_nomem2:
6572         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6573                           bp->gunzip_mapping);
6574         bp->gunzip_buf = NULL;
6575
6576 gunzip_nomem1:
6577         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6578         return -ENOMEM;
6579 }
6580
6581 static void bnx2x_gunzip_end(struct bnx2x *bp)
6582 {
6583         if (bp->strm) {
6584                 vfree(bp->strm->workspace);
6585                 kfree(bp->strm);
6586                 bp->strm = NULL;
6587         }
6588
6589         if (bp->gunzip_buf) {
6590                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6591                                   bp->gunzip_mapping);
6592                 bp->gunzip_buf = NULL;
6593         }
6594 }
6595
6596 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6597 {
6598         int n, rc;
6599
6600         /* check gzip header */
6601         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6602                 BNX2X_ERR("Bad gzip header\n");
6603                 return -EINVAL;
6604         }
6605
6606         n = 10;
6607
6608 #define FNAME                           0x8
6609
6610         if (zbuf[3] & FNAME)
6611                 while ((zbuf[n++] != 0) && (n < len));
6612
6613         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6614         bp->strm->avail_in = len - n;
6615         bp->strm->next_out = bp->gunzip_buf;
6616         bp->strm->avail_out = FW_BUF_SIZE;
6617
6618         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6619         if (rc != Z_OK)
6620                 return rc;
6621
6622         rc = zlib_inflate(bp->strm, Z_FINISH);
6623         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6624                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6625                            bp->strm->msg);
6626
6627         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6628         if (bp->gunzip_outlen & 0x3)
6629                 netdev_err(bp->dev,
6630                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6631                                 bp->gunzip_outlen);
6632         bp->gunzip_outlen >>= 2;
6633
6634         zlib_inflateEnd(bp->strm);
6635
6636         if (rc == Z_STREAM_END)
6637                 return 0;
6638
6639         return rc;
6640 }
6641
6642 /* nic load/unload */
6643
6644 /*
6645  * General service functions
6646  */
6647
6648 /* send a NIG loopback debug packet */
6649 static void bnx2x_lb_pckt(struct bnx2x *bp)
6650 {
6651         u32 wb_write[3];
6652
6653         /* Ethernet source and destination addresses */
6654         wb_write[0] = 0x55555555;
6655         wb_write[1] = 0x55555555;
6656         wb_write[2] = 0x20;             /* SOP */
6657         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6658
6659         /* NON-IP protocol */
6660         wb_write[0] = 0x09000000;
6661         wb_write[1] = 0x55555555;
6662         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6663         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6664 }
6665
6666 /* some of the internal memories
6667  * are not directly readable from the driver
6668  * to test them we send debug packets
6669  */
6670 static int bnx2x_int_mem_test(struct bnx2x *bp)
6671 {
6672         int factor;
6673         int count, i;
6674         u32 val = 0;
6675
6676         if (CHIP_REV_IS_FPGA(bp))
6677                 factor = 120;
6678         else if (CHIP_REV_IS_EMUL(bp))
6679                 factor = 200;
6680         else
6681                 factor = 1;
6682
6683         /* Disable inputs of parser neighbor blocks */
6684         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6685         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6686         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6687         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6688
6689         /*  Write 0 to parser credits for CFC search request */
6690         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6691
6692         /* send Ethernet packet */
6693         bnx2x_lb_pckt(bp);
6694
6695         /* TODO do i reset NIG statistic? */
6696         /* Wait until NIG register shows 1 packet of size 0x10 */
6697         count = 1000 * factor;
6698         while (count) {
6699
6700                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6701                 val = *bnx2x_sp(bp, wb_data[0]);
6702                 if (val == 0x10)
6703                         break;
6704
6705                 usleep_range(10000, 20000);
6706                 count--;
6707         }
6708         if (val != 0x10) {
6709                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6710                 return -1;
6711         }
6712
6713         /* Wait until PRS register shows 1 packet */
6714         count = 1000 * factor;
6715         while (count) {
6716                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6717                 if (val == 1)
6718                         break;
6719
6720                 usleep_range(10000, 20000);
6721                 count--;
6722         }
6723         if (val != 0x1) {
6724                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6725                 return -2;
6726         }
6727
6728         /* Reset and init BRB, PRS */
6729         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6730         msleep(50);
6731         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6732         msleep(50);
6733         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6734         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6735
6736         DP(NETIF_MSG_HW, "part2\n");
6737
6738         /* Disable inputs of parser neighbor blocks */
6739         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6740         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6741         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6742         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6743
6744         /* Write 0 to parser credits for CFC search request */
6745         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6746
6747         /* send 10 Ethernet packets */
6748         for (i = 0; i < 10; i++)
6749                 bnx2x_lb_pckt(bp);
6750
6751         /* Wait until NIG register shows 10 + 1
6752            packets of size 11*0x10 = 0xb0 */
6753         count = 1000 * factor;
6754         while (count) {
6755
6756                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6757                 val = *bnx2x_sp(bp, wb_data[0]);
6758                 if (val == 0xb0)
6759                         break;
6760
6761                 usleep_range(10000, 20000);
6762                 count--;
6763         }
6764         if (val != 0xb0) {
6765                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6766                 return -3;
6767         }
6768
6769         /* Wait until PRS register shows 2 packets */
6770         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6771         if (val != 2)
6772                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6773
6774         /* Write 1 to parser credits for CFC search request */
6775         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6776
6777         /* Wait until PRS register shows 3 packets */
6778         msleep(10 * factor);
6779         /* Wait until NIG register shows 1 packet of size 0x10 */
6780         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6781         if (val != 3)
6782                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6783
6784         /* clear NIG EOP FIFO */
6785         for (i = 0; i < 11; i++)
6786                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6787         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6788         if (val != 1) {
6789                 BNX2X_ERR("clear of NIG failed\n");
6790                 return -4;
6791         }
6792
6793         /* Reset and init BRB, PRS, NIG */
6794         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6795         msleep(50);
6796         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6797         msleep(50);
6798         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6799         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6800         if (!CNIC_SUPPORT(bp))
6801                 /* set NIC mode */
6802                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6803
6804         /* Enable inputs of parser neighbor blocks */
6805         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6806         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6807         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6808         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6809
6810         DP(NETIF_MSG_HW, "done\n");
6811
6812         return 0; /* OK */
6813 }
6814
6815 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6816 {
6817         u32 val;
6818
6819         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6820         if (!CHIP_IS_E1x(bp))
6821                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6822         else
6823                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6824         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6825         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6826         /*
6827          * mask read length error interrupts in brb for parser
6828          * (parsing unit and 'checksum and crc' unit)
6829          * these errors are legal (PU reads fixed length and CAC can cause
6830          * read length error on truncated packets)
6831          */
6832         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6833         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6834         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6835         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6836         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6837         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6838 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6839 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6840         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6841         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6842         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6843 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6844 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6845         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6846         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6847         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6848         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6849 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6850 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6851
6852         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6853                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6854                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6855         if (!CHIP_IS_E1x(bp))
6856                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6857                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6858         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6859
6860         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6861         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6862         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6863 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6864
6865         if (!CHIP_IS_E1x(bp))
6866                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6867                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6868
6869         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6870         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6871 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6872         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6873 }
6874
6875 static void bnx2x_reset_common(struct bnx2x *bp)
6876 {
6877         u32 val = 0x1400;
6878
6879         /* reset_common */
6880         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6881                0xd3ffff7f);
6882
6883         if (CHIP_IS_E3(bp)) {
6884                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6885                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6886         }
6887
6888         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6889 }
6890
6891 static void bnx2x_setup_dmae(struct bnx2x *bp)
6892 {
6893         bp->dmae_ready = 0;
6894         spin_lock_init(&bp->dmae_lock);
6895 }
6896
6897 static void bnx2x_init_pxp(struct bnx2x *bp)
6898 {
6899         u16 devctl;
6900         int r_order, w_order;
6901
6902         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6903         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6904         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6905         if (bp->mrrs == -1)
6906                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6907         else {
6908                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6909                 r_order = bp->mrrs;
6910         }
6911
6912         bnx2x_init_pxp_arb(bp, r_order, w_order);
6913 }
6914
6915 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6916 {
6917         int is_required;
6918         u32 val;
6919         int port;
6920
6921         if (BP_NOMCP(bp))
6922                 return;
6923
6924         is_required = 0;
6925         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6926               SHARED_HW_CFG_FAN_FAILURE_MASK;
6927
6928         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6929                 is_required = 1;
6930
6931         /*
6932          * The fan failure mechanism is usually related to the PHY type since
6933          * the power consumption of the board is affected by the PHY. Currently,
6934          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6935          */
6936         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6937                 for (port = PORT_0; port < PORT_MAX; port++) {
6938                         is_required |=
6939                                 bnx2x_fan_failure_det_req(
6940                                         bp,
6941                                         bp->common.shmem_base,
6942                                         bp->common.shmem2_base,
6943                                         port);
6944                 }
6945
6946         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6947
6948         if (is_required == 0)
6949                 return;
6950
6951         /* Fan failure is indicated by SPIO 5 */
6952         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6953
6954         /* set to active low mode */
6955         val = REG_RD(bp, MISC_REG_SPIO_INT);
6956         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6957         REG_WR(bp, MISC_REG_SPIO_INT, val);
6958
6959         /* enable interrupt to signal the IGU */
6960         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6961         val |= MISC_SPIO_SPIO5;
6962         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6963 }
6964
6965 void bnx2x_pf_disable(struct bnx2x *bp)
6966 {
6967         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6968         val &= ~IGU_PF_CONF_FUNC_EN;
6969
6970         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6971         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6972         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6973 }
6974
6975 static void bnx2x__common_init_phy(struct bnx2x *bp)
6976 {
6977         u32 shmem_base[2], shmem2_base[2];
6978         /* Avoid common init in case MFW supports LFA */
6979         if (SHMEM2_RD(bp, size) >
6980             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6981                 return;
6982         shmem_base[0] =  bp->common.shmem_base;
6983         shmem2_base[0] = bp->common.shmem2_base;
6984         if (!CHIP_IS_E1x(bp)) {
6985                 shmem_base[1] =
6986                         SHMEM2_RD(bp, other_shmem_base_addr);
6987                 shmem2_base[1] =
6988                         SHMEM2_RD(bp, other_shmem2_base_addr);
6989         }
6990         bnx2x_acquire_phy_lock(bp);
6991         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6992                               bp->common.chip_id);
6993         bnx2x_release_phy_lock(bp);
6994 }
6995
6996 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6997 {
6998         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6999         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7000         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7001         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7002         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7003
7004         /* make sure this value is 0 */
7005         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7006
7007         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7008         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7009         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7010         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7011 }
7012
7013 static void bnx2x_set_endianity(struct bnx2x *bp)
7014 {
7015 #ifdef __BIG_ENDIAN
7016         bnx2x_config_endianity(bp, 1);
7017 #else
7018         bnx2x_config_endianity(bp, 0);
7019 #endif
7020 }
7021
7022 static void bnx2x_reset_endianity(struct bnx2x *bp)
7023 {
7024         bnx2x_config_endianity(bp, 0);
7025 }
7026
7027 /**
7028  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7029  *
7030  * @bp:         driver handle
7031  */
7032 static int bnx2x_init_hw_common(struct bnx2x *bp)
7033 {
7034         u32 val;
7035
7036         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7037
7038         /*
7039          * take the RESET lock to protect undi_unload flow from accessing
7040          * registers while we're resetting the chip
7041          */
7042         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7043
7044         bnx2x_reset_common(bp);
7045         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7046
7047         val = 0xfffc;
7048         if (CHIP_IS_E3(bp)) {
7049                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7050                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7051         }
7052         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7053
7054         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7055
7056         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7057
7058         if (!CHIP_IS_E1x(bp)) {
7059                 u8 abs_func_id;
7060
7061                 /**
7062                  * 4-port mode or 2-port mode we need to turn of master-enable
7063                  * for everyone, after that, turn it back on for self.
7064                  * so, we disregard multi-function or not, and always disable
7065                  * for all functions on the given path, this means 0,2,4,6 for
7066                  * path 0 and 1,3,5,7 for path 1
7067                  */
7068                 for (abs_func_id = BP_PATH(bp);
7069                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7070                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7071                                 REG_WR(bp,
7072                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7073                                     1);
7074                                 continue;
7075                         }
7076
7077                         bnx2x_pretend_func(bp, abs_func_id);
7078                         /* clear pf enable */
7079                         bnx2x_pf_disable(bp);
7080                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7081                 }
7082         }
7083
7084         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7085         if (CHIP_IS_E1(bp)) {
7086                 /* enable HW interrupt from PXP on USDM overflow
7087                    bit 16 on INT_MASK_0 */
7088                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7089         }
7090
7091         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7092         bnx2x_init_pxp(bp);
7093         bnx2x_set_endianity(bp);
7094         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7095
7096         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7097                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7098
7099         /* let the HW do it's magic ... */
7100         msleep(100);
7101         /* finish PXP init */
7102         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7103         if (val != 1) {
7104                 BNX2X_ERR("PXP2 CFG failed\n");
7105                 return -EBUSY;
7106         }
7107         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7108         if (val != 1) {
7109                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7110                 return -EBUSY;
7111         }
7112
7113         /* Timers bug workaround E2 only. We need to set the entire ILT to
7114          * have entries with value "0" and valid bit on.
7115          * This needs to be done by the first PF that is loaded in a path
7116          * (i.e. common phase)
7117          */
7118         if (!CHIP_IS_E1x(bp)) {
7119 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7120  * (i.e. vnic3) to start even if it is marked as "scan-off".
7121  * This occurs when a different function (func2,3) is being marked
7122  * as "scan-off". Real-life scenario for example: if a driver is being
7123  * load-unloaded while func6,7 are down. This will cause the timer to access
7124  * the ilt, translate to a logical address and send a request to read/write.
7125  * Since the ilt for the function that is down is not valid, this will cause
7126  * a translation error which is unrecoverable.
7127  * The Workaround is intended to make sure that when this happens nothing fatal
7128  * will occur. The workaround:
7129  *      1.  First PF driver which loads on a path will:
7130  *              a.  After taking the chip out of reset, by using pretend,
7131  *                  it will write "0" to the following registers of
7132  *                  the other vnics.
7133  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7134  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7135  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7136  *                  And for itself it will write '1' to
7137  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7138  *                  dmae-operations (writing to pram for example.)
7139  *                  note: can be done for only function 6,7 but cleaner this
7140  *                        way.
7141  *              b.  Write zero+valid to the entire ILT.
7142  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7143  *                  VNIC3 (of that port). The range allocated will be the
7144  *                  entire ILT. This is needed to prevent  ILT range error.
7145  *      2.  Any PF driver load flow:
7146  *              a.  ILT update with the physical addresses of the allocated
7147  *                  logical pages.
7148  *              b.  Wait 20msec. - note that this timeout is needed to make
7149  *                  sure there are no requests in one of the PXP internal
7150  *                  queues with "old" ILT addresses.
7151  *              c.  PF enable in the PGLC.
7152  *              d.  Clear the was_error of the PF in the PGLC. (could have
7153  *                  occurred while driver was down)
7154  *              e.  PF enable in the CFC (WEAK + STRONG)
7155  *              f.  Timers scan enable
7156  *      3.  PF driver unload flow:
7157  *              a.  Clear the Timers scan_en.
7158  *              b.  Polling for scan_on=0 for that PF.
7159  *              c.  Clear the PF enable bit in the PXP.
7160  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7161  *              e.  Write zero+valid to all ILT entries (The valid bit must
7162  *                  stay set)
7163  *              f.  If this is VNIC 3 of a port then also init
7164  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7165  *                  to the last entry in the ILT.
7166  *
7167  *      Notes:
7168  *      Currently the PF error in the PGLC is non recoverable.
7169  *      In the future the there will be a recovery routine for this error.
7170  *      Currently attention is masked.
7171  *      Having an MCP lock on the load/unload process does not guarantee that
7172  *      there is no Timer disable during Func6/7 enable. This is because the
7173  *      Timers scan is currently being cleared by the MCP on FLR.
7174  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7175  *      there is error before clearing it. But the flow above is simpler and
7176  *      more general.
7177  *      All ILT entries are written by zero+valid and not just PF6/7
7178  *      ILT entries since in the future the ILT entries allocation for
7179  *      PF-s might be dynamic.
7180  */
7181                 struct ilt_client_info ilt_cli;
7182                 struct bnx2x_ilt ilt;
7183                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7184                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7185
7186                 /* initialize dummy TM client */
7187                 ilt_cli.start = 0;
7188                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7189                 ilt_cli.client_num = ILT_CLIENT_TM;
7190
7191                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7192                  * Step 2: set the timers first/last ilt entry to point
7193                  * to the entire range to prevent ILT range error for 3rd/4th
7194                  * vnic (this code assumes existence of the vnic)
7195                  *
7196                  * both steps performed by call to bnx2x_ilt_client_init_op()
7197                  * with dummy TM client
7198                  *
7199                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7200                  * and his brother are split registers
7201                  */
7202                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7203                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7204                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7205
7206                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7207                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7208                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7209         }
7210
7211         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7212         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7213
7214         if (!CHIP_IS_E1x(bp)) {
7215                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7216                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7217                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7218
7219                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7220
7221                 /* let the HW do it's magic ... */
7222                 do {
7223                         msleep(200);
7224                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7225                 } while (factor-- && (val != 1));
7226
7227                 if (val != 1) {
7228                         BNX2X_ERR("ATC_INIT failed\n");
7229                         return -EBUSY;
7230                 }
7231         }
7232
7233         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7234
7235         bnx2x_iov_init_dmae(bp);
7236
7237         /* clean the DMAE memory */
7238         bp->dmae_ready = 1;
7239         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7240
7241         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7242
7243         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7244
7245         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7246
7247         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7248
7249         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7250         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7251         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7252         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7253
7254         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7255
7256         /* QM queues pointers table */
7257         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7258
7259         /* soft reset pulse */
7260         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7261         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7262
7263         if (CNIC_SUPPORT(bp))
7264                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7265
7266         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7267
7268         if (!CHIP_REV_IS_SLOW(bp))
7269                 /* enable hw interrupt from doorbell Q */
7270                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7271
7272         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7273
7274         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7275         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7276
7277         if (!CHIP_IS_E1(bp))
7278                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7279
7280         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7281                 if (IS_MF_AFEX(bp)) {
7282                         /* configure that VNTag and VLAN headers must be
7283                          * received in afex mode
7284                          */
7285                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7286                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7287                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7288                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7289                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7290                 } else {
7291                         /* Bit-map indicating which L2 hdrs may appear
7292                          * after the basic Ethernet header
7293                          */
7294                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7295                                bp->path_has_ovlan ? 7 : 6);
7296                 }
7297         }
7298
7299         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7300         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7301         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7302         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7303
7304         if (!CHIP_IS_E1x(bp)) {
7305                 /* reset VFC memories */
7306                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7307                            VFC_MEMORIES_RST_REG_CAM_RST |
7308                            VFC_MEMORIES_RST_REG_RAM_RST);
7309                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7310                            VFC_MEMORIES_RST_REG_CAM_RST |
7311                            VFC_MEMORIES_RST_REG_RAM_RST);
7312
7313                 msleep(20);
7314         }
7315
7316         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7317         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7318         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7319         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7320
7321         /* sync semi rtc */
7322         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7323                0x80000000);
7324         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7325                0x80000000);
7326
7327         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7328         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7329         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7330
7331         if (!CHIP_IS_E1x(bp)) {
7332                 if (IS_MF_AFEX(bp)) {
7333                         /* configure that VNTag and VLAN headers must be
7334                          * sent in afex mode
7335                          */
7336                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7337                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7338                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7339                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7340                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7341                 } else {
7342                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7343                                bp->path_has_ovlan ? 7 : 6);
7344                 }
7345         }
7346
7347         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7348
7349         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7350
7351         if (CNIC_SUPPORT(bp)) {
7352                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7353                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7354                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7355                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7356                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7357                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7358                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7359                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7360                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7361                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7362         }
7363         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7364
7365         if (sizeof(union cdu_context) != 1024)
7366                 /* we currently assume that a context is 1024 bytes */
7367                 dev_alert(&bp->pdev->dev,
7368                           "please adjust the size of cdu_context(%ld)\n",
7369                           (long)sizeof(union cdu_context));
7370
7371         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7372         val = (4 << 24) + (0 << 12) + 1024;
7373         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7374
7375         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7376         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7377         /* enable context validation interrupt from CFC */
7378         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7379
7380         /* set the thresholds to prevent CFC/CDU race */
7381         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7382
7383         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7384
7385         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7386                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7387
7388         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7389         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7390
7391         /* Reset PCIE errors for debug */
7392         REG_WR(bp, 0x2814, 0xffffffff);
7393         REG_WR(bp, 0x3820, 0xffffffff);
7394
7395         if (!CHIP_IS_E1x(bp)) {
7396                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7397                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7398                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7399                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7400                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7401                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7402                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7403                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7404                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7405                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7406                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7407         }
7408
7409         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7410         if (!CHIP_IS_E1(bp)) {
7411                 /* in E3 this done in per-port section */
7412                 if (!CHIP_IS_E3(bp))
7413                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7414         }
7415         if (CHIP_IS_E1H(bp))
7416                 /* not applicable for E2 (and above ...) */
7417                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7418
7419         if (CHIP_REV_IS_SLOW(bp))
7420                 msleep(200);
7421
7422         /* finish CFC init */
7423         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7424         if (val != 1) {
7425                 BNX2X_ERR("CFC LL_INIT failed\n");
7426                 return -EBUSY;
7427         }
7428         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7429         if (val != 1) {
7430                 BNX2X_ERR("CFC AC_INIT failed\n");
7431                 return -EBUSY;
7432         }
7433         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7434         if (val != 1) {
7435                 BNX2X_ERR("CFC CAM_INIT failed\n");
7436                 return -EBUSY;
7437         }
7438         REG_WR(bp, CFC_REG_DEBUG0, 0);
7439
7440         if (CHIP_IS_E1(bp)) {
7441                 /* read NIG statistic
7442                    to see if this is our first up since powerup */
7443                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7444                 val = *bnx2x_sp(bp, wb_data[0]);
7445
7446                 /* do internal memory self test */
7447                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7448                         BNX2X_ERR("internal mem self test failed\n");
7449                         return -EBUSY;
7450                 }
7451         }
7452
7453         bnx2x_setup_fan_failure_detection(bp);
7454
7455         /* clear PXP2 attentions */
7456         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7457
7458         bnx2x_enable_blocks_attention(bp);
7459         bnx2x_enable_blocks_parity(bp);
7460
7461         if (!BP_NOMCP(bp)) {
7462                 if (CHIP_IS_E1x(bp))
7463                         bnx2x__common_init_phy(bp);
7464         } else
7465                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7466
7467         if (SHMEM2_HAS(bp, netproc_fw_ver))
7468                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7469
7470         return 0;
7471 }
7472
7473 /**
7474  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7475  *
7476  * @bp:         driver handle
7477  */
7478 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7479 {
7480         int rc = bnx2x_init_hw_common(bp);
7481
7482         if (rc)
7483                 return rc;
7484
7485         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7486         if (!BP_NOMCP(bp))
7487                 bnx2x__common_init_phy(bp);
7488
7489         return 0;
7490 }
7491
7492 static int bnx2x_init_hw_port(struct bnx2x *bp)
7493 {
7494         int port = BP_PORT(bp);
7495         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7496         u32 low, high;
7497         u32 val, reg;
7498
7499         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7500
7501         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7502
7503         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7504         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7505         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7506
7507         /* Timers bug workaround: disables the pf_master bit in pglue at
7508          * common phase, we need to enable it here before any dmae access are
7509          * attempted. Therefore we manually added the enable-master to the
7510          * port phase (it also happens in the function phase)
7511          */
7512         if (!CHIP_IS_E1x(bp))
7513                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7514
7515         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7516         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7517         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7518         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7519
7520         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7521         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7522         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7523         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7524
7525         /* QM cid (connection) count */
7526         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7527
7528         if (CNIC_SUPPORT(bp)) {
7529                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7530                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7531                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7532         }
7533
7534         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7535
7536         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7537
7538         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7539
7540                 if (IS_MF(bp))
7541                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7542                 else if (bp->dev->mtu > 4096) {
7543                         if (bp->flags & ONE_PORT_FLAG)
7544                                 low = 160;
7545                         else {
7546                                 val = bp->dev->mtu;
7547                                 /* (24*1024 + val*4)/256 */
7548                                 low = 96 + (val/64) +
7549                                                 ((val % 64) ? 1 : 0);
7550                         }
7551                 } else
7552                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7553                 high = low + 56;        /* 14*1024/256 */
7554                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7555                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7556         }
7557
7558         if (CHIP_MODE_IS_4_PORT(bp))
7559                 REG_WR(bp, (BP_PORT(bp) ?
7560                             BRB1_REG_MAC_GUARANTIED_1 :
7561                             BRB1_REG_MAC_GUARANTIED_0), 40);
7562
7563         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7564         if (CHIP_IS_E3B0(bp)) {
7565                 if (IS_MF_AFEX(bp)) {
7566                         /* configure headers for AFEX mode */
7567                         REG_WR(bp, BP_PORT(bp) ?
7568                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7569                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7570                         REG_WR(bp, BP_PORT(bp) ?
7571                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7572                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7573                         REG_WR(bp, BP_PORT(bp) ?
7574                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7575                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7576                 } else {
7577                         /* Ovlan exists only if we are in multi-function +
7578                          * switch-dependent mode, in switch-independent there
7579                          * is no ovlan headers
7580                          */
7581                         REG_WR(bp, BP_PORT(bp) ?
7582                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7583                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7584                                (bp->path_has_ovlan ? 7 : 6));
7585                 }
7586         }
7587
7588         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7589         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7590         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7591         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7592
7593         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7594         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7595         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7596         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7597
7598         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7599         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7600
7601         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7602
7603         if (CHIP_IS_E1x(bp)) {
7604                 /* configure PBF to work without PAUSE mtu 9000 */
7605                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7606
7607                 /* update threshold */
7608                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7609                 /* update init credit */
7610                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7611
7612                 /* probe changes */
7613                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7614                 udelay(50);
7615                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7616         }
7617
7618         if (CNIC_SUPPORT(bp))
7619                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7620
7621         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7622         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7623
7624         if (CHIP_IS_E1(bp)) {
7625                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7626                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7627         }
7628         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7629
7630         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7631
7632         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7633         /* init aeu_mask_attn_func_0/1:
7634          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7635          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7636          *             bits 4-7 are used for "per vn group attention" */
7637         val = IS_MF(bp) ? 0xF7 : 0x7;
7638         /* Enable DCBX attention for all but E1 */
7639         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7640         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7641
7642         /* SCPAD_PARITY should NOT trigger close the gates */
7643         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7644         REG_WR(bp, reg,
7645                REG_RD(bp, reg) &
7646                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7647
7648         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7649         REG_WR(bp, reg,
7650                REG_RD(bp, reg) &
7651                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7652
7653         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7654
7655         if (!CHIP_IS_E1x(bp)) {
7656                 /* Bit-map indicating which L2 hdrs may appear after the
7657                  * basic Ethernet header
7658                  */
7659                 if (IS_MF_AFEX(bp))
7660                         REG_WR(bp, BP_PORT(bp) ?
7661                                NIG_REG_P1_HDRS_AFTER_BASIC :
7662                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7663                 else
7664                         REG_WR(bp, BP_PORT(bp) ?
7665                                NIG_REG_P1_HDRS_AFTER_BASIC :
7666                                NIG_REG_P0_HDRS_AFTER_BASIC,
7667                                IS_MF_SD(bp) ? 7 : 6);
7668
7669                 if (CHIP_IS_E3(bp))
7670                         REG_WR(bp, BP_PORT(bp) ?
7671                                    NIG_REG_LLH1_MF_MODE :
7672                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7673         }
7674         if (!CHIP_IS_E3(bp))
7675                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7676
7677         if (!CHIP_IS_E1(bp)) {
7678                 /* 0x2 disable mf_ov, 0x1 enable */
7679                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7680                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7681
7682                 if (!CHIP_IS_E1x(bp)) {
7683                         val = 0;
7684                         switch (bp->mf_mode) {
7685                         case MULTI_FUNCTION_SD:
7686                                 val = 1;
7687                                 break;
7688                         case MULTI_FUNCTION_SI:
7689                         case MULTI_FUNCTION_AFEX:
7690                                 val = 2;
7691                                 break;
7692                         }
7693
7694                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7695                                                   NIG_REG_LLH0_CLS_TYPE), val);
7696                 }
7697                 {
7698                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7699                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7700                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7701                 }
7702         }
7703
7704         /* If SPIO5 is set to generate interrupts, enable it for this port */
7705         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7706         if (val & MISC_SPIO_SPIO5) {
7707                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7708                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7709                 val = REG_RD(bp, reg_addr);
7710                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7711                 REG_WR(bp, reg_addr, val);
7712         }
7713
7714         if (CHIP_IS_E3B0(bp))
7715                 bp->flags |= PTP_SUPPORTED;
7716
7717         return 0;
7718 }
7719
7720 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7721 {
7722         int reg;
7723         u32 wb_write[2];
7724
7725         if (CHIP_IS_E1(bp))
7726                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7727         else
7728                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7729
7730         wb_write[0] = ONCHIP_ADDR1(addr);
7731         wb_write[1] = ONCHIP_ADDR2(addr);
7732         REG_WR_DMAE(bp, reg, wb_write, 2);
7733 }
7734
7735 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7736 {
7737         u32 data, ctl, cnt = 100;
7738         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7739         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7740         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7741         u32 sb_bit =  1 << (idu_sb_id%32);
7742         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7743         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7744
7745         /* Not supported in BC mode */
7746         if (CHIP_INT_MODE_IS_BC(bp))
7747                 return;
7748
7749         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7750                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7751                 IGU_REGULAR_CLEANUP_SET                         |
7752                 IGU_REGULAR_BCLEANUP;
7753
7754         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7755               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7756               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7757
7758         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7759                          data, igu_addr_data);
7760         REG_WR(bp, igu_addr_data, data);
7761         barrier();
7762         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7763                           ctl, igu_addr_ctl);
7764         REG_WR(bp, igu_addr_ctl, ctl);
7765         barrier();
7766
7767         /* wait for clean up to finish */
7768         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7769                 msleep(20);
7770
7771         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7772                 DP(NETIF_MSG_HW,
7773                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7774                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7775         }
7776 }
7777
7778 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7779 {
7780         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7781 }
7782
7783 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7784 {
7785         u32 i, base = FUNC_ILT_BASE(func);
7786         for (i = base; i < base + ILT_PER_FUNC; i++)
7787                 bnx2x_ilt_wr(bp, i, 0);
7788 }
7789
7790 static void bnx2x_init_searcher(struct bnx2x *bp)
7791 {
7792         int port = BP_PORT(bp);
7793         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7794         /* T1 hash bits value determines the T1 number of entries */
7795         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7796 }
7797
7798 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7799 {
7800         int rc;
7801         struct bnx2x_func_state_params func_params = {NULL};
7802         struct bnx2x_func_switch_update_params *switch_update_params =
7803                 &func_params.params.switch_update;
7804
7805         /* Prepare parameters for function state transitions */
7806         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7807         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7808
7809         func_params.f_obj = &bp->func_obj;
7810         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7811
7812         /* Function parameters */
7813         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7814                   &switch_update_params->changes);
7815         if (suspend)
7816                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7817                           &switch_update_params->changes);
7818
7819         rc = bnx2x_func_state_change(bp, &func_params);
7820
7821         return rc;
7822 }
7823
7824 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7825 {
7826         int rc, i, port = BP_PORT(bp);
7827         int vlan_en = 0, mac_en[NUM_MACS];
7828
7829         /* Close input from network */
7830         if (bp->mf_mode == SINGLE_FUNCTION) {
7831                 bnx2x_set_rx_filter(&bp->link_params, 0);
7832         } else {
7833                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7834                                    NIG_REG_LLH0_FUNC_EN);
7835                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7836                           NIG_REG_LLH0_FUNC_EN, 0);
7837                 for (i = 0; i < NUM_MACS; i++) {
7838                         mac_en[i] = REG_RD(bp, port ?
7839                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7840                                               4 * i) :
7841                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7842                                               4 * i));
7843                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7844                                               4 * i) :
7845                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7846                 }
7847         }
7848
7849         /* Close BMC to host */
7850         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7851                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7852
7853         /* Suspend Tx switching to the PF. Completion of this ramrod
7854          * further guarantees that all the packets of that PF / child
7855          * VFs in BRB were processed by the Parser, so it is safe to
7856          * change the NIC_MODE register.
7857          */
7858         rc = bnx2x_func_switch_update(bp, 1);
7859         if (rc) {
7860                 BNX2X_ERR("Can't suspend tx-switching!\n");
7861                 return rc;
7862         }
7863
7864         /* Change NIC_MODE register */
7865         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7866
7867         /* Open input from network */
7868         if (bp->mf_mode == SINGLE_FUNCTION) {
7869                 bnx2x_set_rx_filter(&bp->link_params, 1);
7870         } else {
7871                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7872                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7873                 for (i = 0; i < NUM_MACS; i++) {
7874                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7875                                               4 * i) :
7876                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7877                                   mac_en[i]);
7878                 }
7879         }
7880
7881         /* Enable BMC to host */
7882         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7883                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7884
7885         /* Resume Tx switching to the PF */
7886         rc = bnx2x_func_switch_update(bp, 0);
7887         if (rc) {
7888                 BNX2X_ERR("Can't resume tx-switching!\n");
7889                 return rc;
7890         }
7891
7892         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7893         return 0;
7894 }
7895
7896 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7897 {
7898         int rc;
7899
7900         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7901
7902         if (CONFIGURE_NIC_MODE(bp)) {
7903                 /* Configure searcher as part of function hw init */
7904                 bnx2x_init_searcher(bp);
7905
7906                 /* Reset NIC mode */
7907                 rc = bnx2x_reset_nic_mode(bp);
7908                 if (rc)
7909                         BNX2X_ERR("Can't change NIC mode!\n");
7910                 return rc;
7911         }
7912
7913         return 0;
7914 }
7915
7916 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7917  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7918  * the addresses of the transaction, resulting in was-error bit set in the pci
7919  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7920  * to clear the interrupt which detected this from the pglueb and the was done
7921  * bit
7922  */
7923 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7924 {
7925         if (!CHIP_IS_E1x(bp))
7926                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7927                        1 << BP_ABS_FUNC(bp));
7928 }
7929
7930 static int bnx2x_init_hw_func(struct bnx2x *bp)
7931 {
7932         int port = BP_PORT(bp);
7933         int func = BP_FUNC(bp);
7934         int init_phase = PHASE_PF0 + func;
7935         struct bnx2x_ilt *ilt = BP_ILT(bp);
7936         u16 cdu_ilt_start;
7937         u32 addr, val;
7938         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7939         int i, main_mem_width, rc;
7940
7941         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7942
7943         /* FLR cleanup - hmmm */
7944         if (!CHIP_IS_E1x(bp)) {
7945                 rc = bnx2x_pf_flr_clnup(bp);
7946                 if (rc) {
7947                         bnx2x_fw_dump(bp);
7948                         return rc;
7949                 }
7950         }
7951
7952         /* set MSI reconfigure capability */
7953         if (bp->common.int_block == INT_BLOCK_HC) {
7954                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7955                 val = REG_RD(bp, addr);
7956                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7957                 REG_WR(bp, addr, val);
7958         }
7959
7960         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7961         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7962
7963         ilt = BP_ILT(bp);
7964         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7965
7966         if (IS_SRIOV(bp))
7967                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7968         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7969
7970         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7971          * those of the VFs, so start line should be reset
7972          */
7973         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7974         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7975                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7976                 ilt->lines[cdu_ilt_start + i].page_mapping =
7977                         bp->context[i].cxt_mapping;
7978                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7979         }
7980
7981         bnx2x_ilt_init_op(bp, INITOP_SET);
7982
7983         if (!CONFIGURE_NIC_MODE(bp)) {
7984                 bnx2x_init_searcher(bp);
7985                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7986                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7987         } else {
7988                 /* Set NIC mode */
7989                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7990                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7991         }
7992
7993         if (!CHIP_IS_E1x(bp)) {
7994                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7995
7996                 /* Turn on a single ISR mode in IGU if driver is going to use
7997                  * INT#x or MSI
7998                  */
7999                 if (!(bp->flags & USING_MSIX_FLAG))
8000                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8001                 /*
8002                  * Timers workaround bug: function init part.
8003                  * Need to wait 20msec after initializing ILT,
8004                  * needed to make sure there are no requests in
8005                  * one of the PXP internal queues with "old" ILT addresses
8006                  */
8007                 msleep(20);
8008                 /*
8009                  * Master enable - Due to WB DMAE writes performed before this
8010                  * register is re-initialized as part of the regular function
8011                  * init
8012                  */
8013                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8014                 /* Enable the function in IGU */
8015                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8016         }
8017
8018         bp->dmae_ready = 1;
8019
8020         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8021
8022         bnx2x_clean_pglue_errors(bp);
8023
8024         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8025         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8026         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8027         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8028         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8029         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8030         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8031         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8032         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8033         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8034         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8035         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8036         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8037
8038         if (!CHIP_IS_E1x(bp))
8039                 REG_WR(bp, QM_REG_PF_EN, 1);
8040
8041         if (!CHIP_IS_E1x(bp)) {
8042                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8043                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8044                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8045                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8046         }
8047         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8048
8049         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8050         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8051         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8052
8053         bnx2x_iov_init_dq(bp);
8054
8055         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8056         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8057         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8058         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8059         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8060         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8061         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8062         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8063         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8064         if (!CHIP_IS_E1x(bp))
8065                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8066
8067         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8068
8069         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8070
8071         if (!CHIP_IS_E1x(bp))
8072                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8073
8074         if (IS_MF(bp)) {
8075                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8076                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8077                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8078                                bp->mf_ov);
8079                 }
8080         }
8081
8082         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8083
8084         /* HC init per function */
8085         if (bp->common.int_block == INT_BLOCK_HC) {
8086                 if (CHIP_IS_E1H(bp)) {
8087                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8088
8089                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8090                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8091                 }
8092                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8093
8094         } else {
8095                 int num_segs, sb_idx, prod_offset;
8096
8097                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8098
8099                 if (!CHIP_IS_E1x(bp)) {
8100                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8101                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8102                 }
8103
8104                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8105
8106                 if (!CHIP_IS_E1x(bp)) {
8107                         int dsb_idx = 0;
8108                         /**
8109                          * Producer memory:
8110                          * E2 mode: address 0-135 match to the mapping memory;
8111                          * 136 - PF0 default prod; 137 - PF1 default prod;
8112                          * 138 - PF2 default prod; 139 - PF3 default prod;
8113                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8114                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8115                          * 144-147 reserved.
8116                          *
8117                          * E1.5 mode - In backward compatible mode;
8118                          * for non default SB; each even line in the memory
8119                          * holds the U producer and each odd line hold
8120                          * the C producer. The first 128 producers are for
8121                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8122                          * producers are for the DSB for each PF.
8123                          * Each PF has five segments: (the order inside each
8124                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8125                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8126                          * 144-147 attn prods;
8127                          */
8128                         /* non-default-status-blocks */
8129                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8130                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8131                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8132                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8133                                         num_segs;
8134
8135                                 for (i = 0; i < num_segs; i++) {
8136                                         addr = IGU_REG_PROD_CONS_MEMORY +
8137                                                         (prod_offset + i) * 4;
8138                                         REG_WR(bp, addr, 0);
8139                                 }
8140                                 /* send consumer update with value 0 */
8141                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8142                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8143                                 bnx2x_igu_clear_sb(bp,
8144                                                    bp->igu_base_sb + sb_idx);
8145                         }
8146
8147                         /* default-status-blocks */
8148                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8149                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8150
8151                         if (CHIP_MODE_IS_4_PORT(bp))
8152                                 dsb_idx = BP_FUNC(bp);
8153                         else
8154                                 dsb_idx = BP_VN(bp);
8155
8156                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8157                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8158                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8159
8160                         /*
8161                          * igu prods come in chunks of E1HVN_MAX (4) -
8162                          * does not matters what is the current chip mode
8163                          */
8164                         for (i = 0; i < (num_segs * E1HVN_MAX);
8165                              i += E1HVN_MAX) {
8166                                 addr = IGU_REG_PROD_CONS_MEMORY +
8167                                                         (prod_offset + i)*4;
8168                                 REG_WR(bp, addr, 0);
8169                         }
8170                         /* send consumer update with 0 */
8171                         if (CHIP_INT_MODE_IS_BC(bp)) {
8172                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8173                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8174                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8175                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8176                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8177                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8178                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8179                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8180                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8181                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8182                         } else {
8183                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8184                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8185                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8186                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8187                         }
8188                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8189
8190                         /* !!! These should become driver const once
8191                            rf-tool supports split-68 const */
8192                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8193                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8194                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8195                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8196                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8197                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8198                 }
8199         }
8200
8201         /* Reset PCIE errors for debug */
8202         REG_WR(bp, 0x2114, 0xffffffff);
8203         REG_WR(bp, 0x2120, 0xffffffff);
8204
8205         if (CHIP_IS_E1x(bp)) {
8206                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8207                 main_mem_base = HC_REG_MAIN_MEMORY +
8208                                 BP_PORT(bp) * (main_mem_size * 4);
8209                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8210                 main_mem_width = 8;
8211
8212                 val = REG_RD(bp, main_mem_prty_clr);
8213                 if (val)
8214                         DP(NETIF_MSG_HW,
8215                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8216                            val);
8217
8218                 /* Clear "false" parity errors in MSI-X table */
8219                 for (i = main_mem_base;
8220                      i < main_mem_base + main_mem_size * 4;
8221                      i += main_mem_width) {
8222                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8223                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8224                                          i, main_mem_width / 4);
8225                 }
8226                 /* Clear HC parity attention */
8227                 REG_RD(bp, main_mem_prty_clr);
8228         }
8229
8230 #ifdef BNX2X_STOP_ON_ERROR
8231         /* Enable STORMs SP logging */
8232         REG_WR8(bp, BAR_USTRORM_INTMEM +
8233                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8234         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8235                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8236         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8237                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8238         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8239                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8240 #endif
8241
8242         bnx2x_phy_probe(&bp->link_params);
8243
8244         return 0;
8245 }
8246
8247 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8248 {
8249         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8250
8251         if (!CHIP_IS_E1x(bp))
8252                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8253                                sizeof(struct host_hc_status_block_e2));
8254         else
8255                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8256                                sizeof(struct host_hc_status_block_e1x));
8257
8258         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8259 }
8260
8261 void bnx2x_free_mem(struct bnx2x *bp)
8262 {
8263         int i;
8264
8265         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8266                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8267
8268         if (IS_VF(bp))
8269                 return;
8270
8271         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8272                        sizeof(struct host_sp_status_block));
8273
8274         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8275                        sizeof(struct bnx2x_slowpath));
8276
8277         for (i = 0; i < L2_ILT_LINES(bp); i++)
8278                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8279                                bp->context[i].size);
8280         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8281
8282         BNX2X_FREE(bp->ilt->lines);
8283
8284         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8285
8286         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8287                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8288
8289         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8290
8291         bnx2x_iov_free_mem(bp);
8292 }
8293
8294 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8295 {
8296         if (!CHIP_IS_E1x(bp)) {
8297                 /* size = the status block + ramrod buffers */
8298                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8299                                                     sizeof(struct host_hc_status_block_e2));
8300                 if (!bp->cnic_sb.e2_sb)
8301                         goto alloc_mem_err;
8302         } else {
8303                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8304                                                      sizeof(struct host_hc_status_block_e1x));
8305                 if (!bp->cnic_sb.e1x_sb)
8306                         goto alloc_mem_err;
8307         }
8308
8309         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8310                 /* allocate searcher T2 table, as it wasn't allocated before */
8311                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8312                 if (!bp->t2)
8313                         goto alloc_mem_err;
8314         }
8315
8316         /* write address to which L5 should insert its values */
8317         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8318                 &bp->slowpath->drv_info_to_mcp;
8319
8320         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8321                 goto alloc_mem_err;
8322
8323         return 0;
8324
8325 alloc_mem_err:
8326         bnx2x_free_mem_cnic(bp);
8327         BNX2X_ERR("Can't allocate memory\n");
8328         return -ENOMEM;
8329 }
8330
8331 int bnx2x_alloc_mem(struct bnx2x *bp)
8332 {
8333         int i, allocated, context_size;
8334
8335         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8336                 /* allocate searcher T2 table */
8337                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8338                 if (!bp->t2)
8339                         goto alloc_mem_err;
8340         }
8341
8342         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8343                                              sizeof(struct host_sp_status_block));
8344         if (!bp->def_status_blk)
8345                 goto alloc_mem_err;
8346
8347         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8348                                        sizeof(struct bnx2x_slowpath));
8349         if (!bp->slowpath)
8350                 goto alloc_mem_err;
8351
8352         /* Allocate memory for CDU context:
8353          * This memory is allocated separately and not in the generic ILT
8354          * functions because CDU differs in few aspects:
8355          * 1. There are multiple entities allocating memory for context -
8356          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8357          * its own ILT lines.
8358          * 2. Since CDU page-size is not a single 4KB page (which is the case
8359          * for the other ILT clients), to be efficient we want to support
8360          * allocation of sub-page-size in the last entry.
8361          * 3. Context pointers are used by the driver to pass to FW / update
8362          * the context (for the other ILT clients the pointers are used just to
8363          * free the memory during unload).
8364          */
8365         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8366
8367         for (i = 0, allocated = 0; allocated < context_size; i++) {
8368                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8369                                           (context_size - allocated));
8370                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8371                                                       bp->context[i].size);
8372                 if (!bp->context[i].vcxt)
8373                         goto alloc_mem_err;
8374                 allocated += bp->context[i].size;
8375         }
8376         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8377                                  GFP_KERNEL);
8378         if (!bp->ilt->lines)
8379                 goto alloc_mem_err;
8380
8381         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8382                 goto alloc_mem_err;
8383
8384         if (bnx2x_iov_alloc_mem(bp))
8385                 goto alloc_mem_err;
8386
8387         /* Slow path ring */
8388         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8389         if (!bp->spq)
8390                 goto alloc_mem_err;
8391
8392         /* EQ */
8393         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8394                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8395         if (!bp->eq_ring)
8396                 goto alloc_mem_err;
8397
8398         return 0;
8399
8400 alloc_mem_err:
8401         bnx2x_free_mem(bp);
8402         BNX2X_ERR("Can't allocate memory\n");
8403         return -ENOMEM;
8404 }
8405
8406 /*
8407  * Init service functions
8408  */
8409
8410 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8411                       struct bnx2x_vlan_mac_obj *obj, bool set,
8412                       int mac_type, unsigned long *ramrod_flags)
8413 {
8414         int rc;
8415         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8416
8417         memset(&ramrod_param, 0, sizeof(ramrod_param));
8418
8419         /* Fill general parameters */
8420         ramrod_param.vlan_mac_obj = obj;
8421         ramrod_param.ramrod_flags = *ramrod_flags;
8422
8423         /* Fill a user request section if needed */
8424         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8425                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8426
8427                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8428
8429                 /* Set the command: ADD or DEL */
8430                 if (set)
8431                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8432                 else
8433                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8434         }
8435
8436         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8437
8438         if (rc == -EEXIST) {
8439                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8440                 /* do not treat adding same MAC as error */
8441                 rc = 0;
8442         } else if (rc < 0)
8443                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8444
8445         return rc;
8446 }
8447
8448 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8449                        struct bnx2x_vlan_mac_obj *obj, bool set,
8450                        unsigned long *ramrod_flags)
8451 {
8452         int rc;
8453         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8454
8455         memset(&ramrod_param, 0, sizeof(ramrod_param));
8456
8457         /* Fill general parameters */
8458         ramrod_param.vlan_mac_obj = obj;
8459         ramrod_param.ramrod_flags = *ramrod_flags;
8460
8461         /* Fill a user request section if needed */
8462         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8463                 ramrod_param.user_req.u.vlan.vlan = vlan;
8464                 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags);
8465                 /* Set the command: ADD or DEL */
8466                 if (set)
8467                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8468                 else
8469                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8470         }
8471
8472         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8473
8474         if (rc == -EEXIST) {
8475                 /* Do not treat adding same vlan as error. */
8476                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8477                 rc = 0;
8478         } else if (rc < 0) {
8479                 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8480         }
8481
8482         return rc;
8483 }
8484
8485 static int bnx2x_del_all_vlans(struct bnx2x *bp)
8486 {
8487         struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj;
8488         unsigned long ramrod_flags = 0, vlan_flags = 0;
8489         struct bnx2x_vlan_entry *vlan;
8490         int rc;
8491
8492         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8493         __set_bit(BNX2X_VLAN, &vlan_flags);
8494         rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags);
8495         if (rc)
8496                 return rc;
8497
8498         /* Mark that hw forgot all entries */
8499         list_for_each_entry(vlan, &bp->vlan_reg, link)
8500                 vlan->hw = false;
8501         bp->vlan_cnt = 0;
8502
8503         return 0;
8504 }
8505
8506 int bnx2x_del_all_macs(struct bnx2x *bp,
8507                        struct bnx2x_vlan_mac_obj *mac_obj,
8508                        int mac_type, bool wait_for_comp)
8509 {
8510         int rc;
8511         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8512
8513         /* Wait for completion of requested */
8514         if (wait_for_comp)
8515                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8516
8517         /* Set the mac type of addresses we want to clear */
8518         __set_bit(mac_type, &vlan_mac_flags);
8519
8520         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8521         if (rc < 0)
8522                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8523
8524         return rc;
8525 }
8526
8527 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8528 {
8529         if (IS_PF(bp)) {
8530                 unsigned long ramrod_flags = 0;
8531
8532                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8533                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8534                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8535                                          &bp->sp_objs->mac_obj, set,
8536                                          BNX2X_ETH_MAC, &ramrod_flags);
8537         } else { /* vf */
8538                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8539                                              bp->fp->index, set);
8540         }
8541 }
8542
8543 int bnx2x_setup_leading(struct bnx2x *bp)
8544 {
8545         if (IS_PF(bp))
8546                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8547         else /* VF */
8548                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8549 }
8550
8551 /**
8552  * bnx2x_set_int_mode - configure interrupt mode
8553  *
8554  * @bp:         driver handle
8555  *
8556  * In case of MSI-X it will also try to enable MSI-X.
8557  */
8558 int bnx2x_set_int_mode(struct bnx2x *bp)
8559 {
8560         int rc = 0;
8561
8562         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8563                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8564                 return -EINVAL;
8565         }
8566
8567         switch (int_mode) {
8568         case BNX2X_INT_MODE_MSIX:
8569                 /* attempt to enable msix */
8570                 rc = bnx2x_enable_msix(bp);
8571
8572                 /* msix attained */
8573                 if (!rc)
8574                         return 0;
8575
8576                 /* vfs use only msix */
8577                 if (rc && IS_VF(bp))
8578                         return rc;
8579
8580                 /* failed to enable multiple MSI-X */
8581                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8582                                bp->num_queues,
8583                                1 + bp->num_cnic_queues);
8584
8585                 /* fall through */
8586         case BNX2X_INT_MODE_MSI:
8587                 bnx2x_enable_msi(bp);
8588
8589                 /* fall through */
8590         case BNX2X_INT_MODE_INTX:
8591                 bp->num_ethernet_queues = 1;
8592                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8593                 BNX2X_DEV_INFO("set number of queues to 1\n");
8594                 break;
8595         default:
8596                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8597                 return -EINVAL;
8598         }
8599         return 0;
8600 }
8601
8602 /* must be called prior to any HW initializations */
8603 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8604 {
8605         if (IS_SRIOV(bp))
8606                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8607         return L2_ILT_LINES(bp);
8608 }
8609
8610 void bnx2x_ilt_set_info(struct bnx2x *bp)
8611 {
8612         struct ilt_client_info *ilt_client;
8613         struct bnx2x_ilt *ilt = BP_ILT(bp);
8614         u16 line = 0;
8615
8616         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8617         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8618
8619         /* CDU */
8620         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8621         ilt_client->client_num = ILT_CLIENT_CDU;
8622         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8623         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8624         ilt_client->start = line;
8625         line += bnx2x_cid_ilt_lines(bp);
8626
8627         if (CNIC_SUPPORT(bp))
8628                 line += CNIC_ILT_LINES;
8629         ilt_client->end = line - 1;
8630
8631         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8632            ilt_client->start,
8633            ilt_client->end,
8634            ilt_client->page_size,
8635            ilt_client->flags,
8636            ilog2(ilt_client->page_size >> 12));
8637
8638         /* QM */
8639         if (QM_INIT(bp->qm_cid_count)) {
8640                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8641                 ilt_client->client_num = ILT_CLIENT_QM;
8642                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8643                 ilt_client->flags = 0;
8644                 ilt_client->start = line;
8645
8646                 /* 4 bytes for each cid */
8647                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8648                                                          QM_ILT_PAGE_SZ);
8649
8650                 ilt_client->end = line - 1;
8651
8652                 DP(NETIF_MSG_IFUP,
8653                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8654                    ilt_client->start,
8655                    ilt_client->end,
8656                    ilt_client->page_size,
8657                    ilt_client->flags,
8658                    ilog2(ilt_client->page_size >> 12));
8659         }
8660
8661         if (CNIC_SUPPORT(bp)) {
8662                 /* SRC */
8663                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8664                 ilt_client->client_num = ILT_CLIENT_SRC;
8665                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8666                 ilt_client->flags = 0;
8667                 ilt_client->start = line;
8668                 line += SRC_ILT_LINES;
8669                 ilt_client->end = line - 1;
8670
8671                 DP(NETIF_MSG_IFUP,
8672                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8673                    ilt_client->start,
8674                    ilt_client->end,
8675                    ilt_client->page_size,
8676                    ilt_client->flags,
8677                    ilog2(ilt_client->page_size >> 12));
8678
8679                 /* TM */
8680                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8681                 ilt_client->client_num = ILT_CLIENT_TM;
8682                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8683                 ilt_client->flags = 0;
8684                 ilt_client->start = line;
8685                 line += TM_ILT_LINES;
8686                 ilt_client->end = line - 1;
8687
8688                 DP(NETIF_MSG_IFUP,
8689                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8690                    ilt_client->start,
8691                    ilt_client->end,
8692                    ilt_client->page_size,
8693                    ilt_client->flags,
8694                    ilog2(ilt_client->page_size >> 12));
8695         }
8696
8697         BUG_ON(line > ILT_MAX_LINES);
8698 }
8699
8700 /**
8701  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8702  *
8703  * @bp:                 driver handle
8704  * @fp:                 pointer to fastpath
8705  * @init_params:        pointer to parameters structure
8706  *
8707  * parameters configured:
8708  *      - HC configuration
8709  *      - Queue's CDU context
8710  */
8711 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8712         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8713 {
8714         u8 cos;
8715         int cxt_index, cxt_offset;
8716
8717         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8718         if (!IS_FCOE_FP(fp)) {
8719                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8720                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8721
8722                 /* If HC is supported, enable host coalescing in the transition
8723                  * to INIT state.
8724                  */
8725                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8726                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8727
8728                 /* HC rate */
8729                 init_params->rx.hc_rate = bp->rx_ticks ?
8730                         (1000000 / bp->rx_ticks) : 0;
8731                 init_params->tx.hc_rate = bp->tx_ticks ?
8732                         (1000000 / bp->tx_ticks) : 0;
8733
8734                 /* FW SB ID */
8735                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8736                         fp->fw_sb_id;
8737
8738                 /*
8739                  * CQ index among the SB indices: FCoE clients uses the default
8740                  * SB, therefore it's different.
8741                  */
8742                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8743                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8744         }
8745
8746         /* set maximum number of COSs supported by this queue */
8747         init_params->max_cos = fp->max_cos;
8748
8749         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8750             fp->index, init_params->max_cos);
8751
8752         /* set the context pointers queue object */
8753         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8754                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8755                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8756                                 ILT_PAGE_CIDS);
8757                 init_params->cxts[cos] =
8758                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8759         }
8760 }
8761
8762 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8763                         struct bnx2x_queue_state_params *q_params,
8764                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8765                         int tx_index, bool leading)
8766 {
8767         memset(tx_only_params, 0, sizeof(*tx_only_params));
8768
8769         /* Set the command */
8770         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8771
8772         /* Set tx-only QUEUE flags: don't zero statistics */
8773         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8774
8775         /* choose the index of the cid to send the slow path on */
8776         tx_only_params->cid_index = tx_index;
8777
8778         /* Set general TX_ONLY_SETUP parameters */
8779         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8780
8781         /* Set Tx TX_ONLY_SETUP parameters */
8782         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8783
8784         DP(NETIF_MSG_IFUP,
8785            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8786            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8787            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8788            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8789
8790         /* send the ramrod */
8791         return bnx2x_queue_state_change(bp, q_params);
8792 }
8793
8794 /**
8795  * bnx2x_setup_queue - setup queue
8796  *
8797  * @bp:         driver handle
8798  * @fp:         pointer to fastpath
8799  * @leading:    is leading
8800  *
8801  * This function performs 2 steps in a Queue state machine
8802  *      actually: 1) RESET->INIT 2) INIT->SETUP
8803  */
8804
8805 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8806                        bool leading)
8807 {
8808         struct bnx2x_queue_state_params q_params = {NULL};
8809         struct bnx2x_queue_setup_params *setup_params =
8810                                                 &q_params.params.setup;
8811         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8812                                                 &q_params.params.tx_only;
8813         int rc;
8814         u8 tx_index;
8815
8816         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8817
8818         /* reset IGU state skip FCoE L2 queue */
8819         if (!IS_FCOE_FP(fp))
8820                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8821                              IGU_INT_ENABLE, 0);
8822
8823         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8824         /* We want to wait for completion in this context */
8825         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8826
8827         /* Prepare the INIT parameters */
8828         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8829
8830         /* Set the command */
8831         q_params.cmd = BNX2X_Q_CMD_INIT;
8832
8833         /* Change the state to INIT */
8834         rc = bnx2x_queue_state_change(bp, &q_params);
8835         if (rc) {
8836                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8837                 return rc;
8838         }
8839
8840         DP(NETIF_MSG_IFUP, "init complete\n");
8841
8842         /* Now move the Queue to the SETUP state... */
8843         memset(setup_params, 0, sizeof(*setup_params));
8844
8845         /* Set QUEUE flags */
8846         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8847
8848         /* Set general SETUP parameters */
8849         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8850                                 FIRST_TX_COS_INDEX);
8851
8852         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8853                             &setup_params->rxq_params);
8854
8855         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8856                            FIRST_TX_COS_INDEX);
8857
8858         /* Set the command */
8859         q_params.cmd = BNX2X_Q_CMD_SETUP;
8860
8861         if (IS_FCOE_FP(fp))
8862                 bp->fcoe_init = true;
8863
8864         /* Change the state to SETUP */
8865         rc = bnx2x_queue_state_change(bp, &q_params);
8866         if (rc) {
8867                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8868                 return rc;
8869         }
8870
8871         /* loop through the relevant tx-only indices */
8872         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8873               tx_index < fp->max_cos;
8874               tx_index++) {
8875
8876                 /* prepare and send tx-only ramrod*/
8877                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8878                                           tx_only_params, tx_index, leading);
8879                 if (rc) {
8880                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8881                                   fp->index, tx_index);
8882                         return rc;
8883                 }
8884         }
8885
8886         return rc;
8887 }
8888
8889 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8890 {
8891         struct bnx2x_fastpath *fp = &bp->fp[index];
8892         struct bnx2x_fp_txdata *txdata;
8893         struct bnx2x_queue_state_params q_params = {NULL};
8894         int rc, tx_index;
8895
8896         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8897
8898         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8899         /* We want to wait for completion in this context */
8900         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8901
8902         /* close tx-only connections */
8903         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8904              tx_index < fp->max_cos;
8905              tx_index++){
8906
8907                 /* ascertain this is a normal queue*/
8908                 txdata = fp->txdata_ptr[tx_index];
8909
8910                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8911                                                         txdata->txq_index);
8912
8913                 /* send halt terminate on tx-only connection */
8914                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8915                 memset(&q_params.params.terminate, 0,
8916                        sizeof(q_params.params.terminate));
8917                 q_params.params.terminate.cid_index = tx_index;
8918
8919                 rc = bnx2x_queue_state_change(bp, &q_params);
8920                 if (rc)
8921                         return rc;
8922
8923                 /* send halt terminate on tx-only connection */
8924                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8925                 memset(&q_params.params.cfc_del, 0,
8926                        sizeof(q_params.params.cfc_del));
8927                 q_params.params.cfc_del.cid_index = tx_index;
8928                 rc = bnx2x_queue_state_change(bp, &q_params);
8929                 if (rc)
8930                         return rc;
8931         }
8932         /* Stop the primary connection: */
8933         /* ...halt the connection */
8934         q_params.cmd = BNX2X_Q_CMD_HALT;
8935         rc = bnx2x_queue_state_change(bp, &q_params);
8936         if (rc)
8937                 return rc;
8938
8939         /* ...terminate the connection */
8940         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8941         memset(&q_params.params.terminate, 0,
8942                sizeof(q_params.params.terminate));
8943         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8944         rc = bnx2x_queue_state_change(bp, &q_params);
8945         if (rc)
8946                 return rc;
8947         /* ...delete cfc entry */
8948         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8949         memset(&q_params.params.cfc_del, 0,
8950                sizeof(q_params.params.cfc_del));
8951         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8952         return bnx2x_queue_state_change(bp, &q_params);
8953 }
8954
8955 static void bnx2x_reset_func(struct bnx2x *bp)
8956 {
8957         int port = BP_PORT(bp);
8958         int func = BP_FUNC(bp);
8959         int i;
8960
8961         /* Disable the function in the FW */
8962         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8963         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8964         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8965         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8966
8967         /* FP SBs */
8968         for_each_eth_queue(bp, i) {
8969                 struct bnx2x_fastpath *fp = &bp->fp[i];
8970                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8971                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8972                            SB_DISABLED);
8973         }
8974
8975         if (CNIC_LOADED(bp))
8976                 /* CNIC SB */
8977                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8978                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8979                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8980
8981         /* SP SB */
8982         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8983                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8984                 SB_DISABLED);
8985
8986         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8987                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8988                        0);
8989
8990         /* Configure IGU */
8991         if (bp->common.int_block == INT_BLOCK_HC) {
8992                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8993                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8994         } else {
8995                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8996                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8997         }
8998
8999         if (CNIC_LOADED(bp)) {
9000                 /* Disable Timer scan */
9001                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
9002                 /*
9003                  * Wait for at least 10ms and up to 2 second for the timers
9004                  * scan to complete
9005                  */
9006                 for (i = 0; i < 200; i++) {
9007                         usleep_range(10000, 20000);
9008                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
9009                                 break;
9010                 }
9011         }
9012         /* Clear ILT */
9013         bnx2x_clear_func_ilt(bp, func);
9014
9015         /* Timers workaround bug for E2: if this is vnic-3,
9016          * we need to set the entire ilt range for this timers.
9017          */
9018         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
9019                 struct ilt_client_info ilt_cli;
9020                 /* use dummy TM client */
9021                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9022                 ilt_cli.start = 0;
9023                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9024                 ilt_cli.client_num = ILT_CLIENT_TM;
9025
9026                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9027         }
9028
9029         /* this assumes that reset_port() called before reset_func()*/
9030         if (!CHIP_IS_E1x(bp))
9031                 bnx2x_pf_disable(bp);
9032
9033         bp->dmae_ready = 0;
9034 }
9035
9036 static void bnx2x_reset_port(struct bnx2x *bp)
9037 {
9038         int port = BP_PORT(bp);
9039         u32 val;
9040
9041         /* Reset physical Link */
9042         bnx2x__link_reset(bp);
9043
9044         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9045
9046         /* Do not rcv packets to BRB */
9047         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9048         /* Do not direct rcv packets that are not for MCP to the BRB */
9049         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9050                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9051
9052         /* Configure AEU */
9053         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9054
9055         msleep(100);
9056         /* Check for BRB port occupancy */
9057         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9058         if (val)
9059                 DP(NETIF_MSG_IFDOWN,
9060                    "BRB1 is not empty  %d blocks are occupied\n", val);
9061
9062         /* TODO: Close Doorbell port? */
9063 }
9064
9065 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9066 {
9067         struct bnx2x_func_state_params func_params = {NULL};
9068
9069         /* Prepare parameters for function state transitions */
9070         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9071
9072         func_params.f_obj = &bp->func_obj;
9073         func_params.cmd = BNX2X_F_CMD_HW_RESET;
9074
9075         func_params.params.hw_init.load_phase = load_code;
9076
9077         return bnx2x_func_state_change(bp, &func_params);
9078 }
9079
9080 static int bnx2x_func_stop(struct bnx2x *bp)
9081 {
9082         struct bnx2x_func_state_params func_params = {NULL};
9083         int rc;
9084
9085         /* Prepare parameters for function state transitions */
9086         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9087         func_params.f_obj = &bp->func_obj;
9088         func_params.cmd = BNX2X_F_CMD_STOP;
9089
9090         /*
9091          * Try to stop the function the 'good way'. If fails (in case
9092          * of a parity error during bnx2x_chip_cleanup()) and we are
9093          * not in a debug mode, perform a state transaction in order to
9094          * enable further HW_RESET transaction.
9095          */
9096         rc = bnx2x_func_state_change(bp, &func_params);
9097         if (rc) {
9098 #ifdef BNX2X_STOP_ON_ERROR
9099                 return rc;
9100 #else
9101                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9102                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9103                 return bnx2x_func_state_change(bp, &func_params);
9104 #endif
9105         }
9106
9107         return 0;
9108 }
9109
9110 /**
9111  * bnx2x_send_unload_req - request unload mode from the MCP.
9112  *
9113  * @bp:                 driver handle
9114  * @unload_mode:        requested function's unload mode
9115  *
9116  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9117  */
9118 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9119 {
9120         u32 reset_code = 0;
9121         int port = BP_PORT(bp);
9122
9123         /* Select the UNLOAD request mode */
9124         if (unload_mode == UNLOAD_NORMAL)
9125                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9126
9127         else if (bp->flags & NO_WOL_FLAG)
9128                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9129
9130         else if (bp->wol) {
9131                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9132                 u8 *mac_addr = bp->dev->dev_addr;
9133                 struct pci_dev *pdev = bp->pdev;
9134                 u32 val;
9135                 u16 pmc;
9136
9137                 /* The mac address is written to entries 1-4 to
9138                  * preserve entry 0 which is used by the PMF
9139                  */
9140                 u8 entry = (BP_VN(bp) + 1)*8;
9141
9142                 val = (mac_addr[0] << 8) | mac_addr[1];
9143                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9144
9145                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9146                       (mac_addr[4] << 8) | mac_addr[5];
9147                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9148
9149                 /* Enable the PME and clear the status */
9150                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9151                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9152                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9153
9154                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9155
9156         } else
9157                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9158
9159         /* Send the request to the MCP */
9160         if (!BP_NOMCP(bp))
9161                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9162         else {
9163                 int path = BP_PATH(bp);
9164
9165                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9166                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9167                    bnx2x_load_count[path][2]);
9168                 bnx2x_load_count[path][0]--;
9169                 bnx2x_load_count[path][1 + port]--;
9170                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9171                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9172                    bnx2x_load_count[path][2]);
9173                 if (bnx2x_load_count[path][0] == 0)
9174                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9175                 else if (bnx2x_load_count[path][1 + port] == 0)
9176                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9177                 else
9178                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9179         }
9180
9181         return reset_code;
9182 }
9183
9184 /**
9185  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9186  *
9187  * @bp:         driver handle
9188  * @keep_link:          true iff link should be kept up
9189  */
9190 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9191 {
9192         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9193
9194         /* Report UNLOAD_DONE to MCP */
9195         if (!BP_NOMCP(bp))
9196                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9197 }
9198
9199 static int bnx2x_func_wait_started(struct bnx2x *bp)
9200 {
9201         int tout = 50;
9202         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9203
9204         if (!bp->port.pmf)
9205                 return 0;
9206
9207         /*
9208          * (assumption: No Attention from MCP at this stage)
9209          * PMF probably in the middle of TX disable/enable transaction
9210          * 1. Sync IRS for default SB
9211          * 2. Sync SP queue - this guarantees us that attention handling started
9212          * 3. Wait, that TX disable/enable transaction completes
9213          *
9214          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9215          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9216          * received completion for the transaction the state is TX_STOPPED.
9217          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9218          * transaction.
9219          */
9220
9221         /* make sure default SB ISR is done */
9222         if (msix)
9223                 synchronize_irq(bp->msix_table[0].vector);
9224         else
9225                 synchronize_irq(bp->pdev->irq);
9226
9227         flush_workqueue(bnx2x_wq);
9228         flush_workqueue(bnx2x_iov_wq);
9229
9230         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9231                                 BNX2X_F_STATE_STARTED && tout--)
9232                 msleep(20);
9233
9234         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9235                                                 BNX2X_F_STATE_STARTED) {
9236 #ifdef BNX2X_STOP_ON_ERROR
9237                 BNX2X_ERR("Wrong function state\n");
9238                 return -EBUSY;
9239 #else
9240                 /*
9241                  * Failed to complete the transaction in a "good way"
9242                  * Force both transactions with CLR bit
9243                  */
9244                 struct bnx2x_func_state_params func_params = {NULL};
9245
9246                 DP(NETIF_MSG_IFDOWN,
9247                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9248
9249                 func_params.f_obj = &bp->func_obj;
9250                 __set_bit(RAMROD_DRV_CLR_ONLY,
9251                                         &func_params.ramrod_flags);
9252
9253                 /* STARTED-->TX_ST0PPED */
9254                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9255                 bnx2x_func_state_change(bp, &func_params);
9256
9257                 /* TX_ST0PPED-->STARTED */
9258                 func_params.cmd = BNX2X_F_CMD_TX_START;
9259                 return bnx2x_func_state_change(bp, &func_params);
9260 #endif
9261         }
9262
9263         return 0;
9264 }
9265
9266 static void bnx2x_disable_ptp(struct bnx2x *bp)
9267 {
9268         int port = BP_PORT(bp);
9269
9270         /* Disable sending PTP packets to host */
9271         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9272                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9273
9274         /* Reset PTP event detection rules */
9275         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9276                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9277         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9278                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9279         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9280                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9281         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9282                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9283
9284         /* Disable the PTP feature */
9285         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9286                NIG_REG_P0_PTP_EN, 0x0);
9287 }
9288
9289 /* Called during unload, to stop PTP-related stuff */
9290 static void bnx2x_stop_ptp(struct bnx2x *bp)
9291 {
9292         /* Cancel PTP work queue. Should be done after the Tx queues are
9293          * drained to prevent additional scheduling.
9294          */
9295         cancel_work_sync(&bp->ptp_task);
9296
9297         if (bp->ptp_tx_skb) {
9298                 dev_kfree_skb_any(bp->ptp_tx_skb);
9299                 bp->ptp_tx_skb = NULL;
9300         }
9301
9302         /* Disable PTP in HW */
9303         bnx2x_disable_ptp(bp);
9304
9305         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9306 }
9307
9308 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9309 {
9310         int port = BP_PORT(bp);
9311         int i, rc = 0;
9312         u8 cos;
9313         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9314         u32 reset_code;
9315
9316         /* Wait until tx fastpath tasks complete */
9317         for_each_tx_queue(bp, i) {
9318                 struct bnx2x_fastpath *fp = &bp->fp[i];
9319
9320                 for_each_cos_in_tx_queue(fp, cos)
9321                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9322 #ifdef BNX2X_STOP_ON_ERROR
9323                 if (rc)
9324                         return;
9325 #endif
9326         }
9327
9328         /* Give HW time to discard old tx messages */
9329         usleep_range(1000, 2000);
9330
9331         /* Clean all ETH MACs */
9332         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9333                                 false);
9334         if (rc < 0)
9335                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9336
9337         /* Clean up UC list  */
9338         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9339                                 true);
9340         if (rc < 0)
9341                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9342                           rc);
9343
9344         /* The whole *vlan_obj structure may be not initialized if VLAN
9345          * filtering offload is not supported by hardware. Currently this is
9346          * true for all hardware covered by CHIP_IS_E1x().
9347          */
9348         if (!CHIP_IS_E1x(bp)) {
9349                 /* Remove all currently configured VLANs */
9350                 rc = bnx2x_del_all_vlans(bp);
9351                 if (rc < 0)
9352                         BNX2X_ERR("Failed to delete all VLANs\n");
9353         }
9354
9355         /* Disable LLH */
9356         if (!CHIP_IS_E1(bp))
9357                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9358
9359         /* Set "drop all" (stop Rx).
9360          * We need to take a netif_addr_lock() here in order to prevent
9361          * a race between the completion code and this code.
9362          */
9363         netif_addr_lock_bh(bp->dev);
9364         /* Schedule the rx_mode command */
9365         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9366                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9367         else if (bp->slowpath)
9368                 bnx2x_set_storm_rx_mode(bp);
9369
9370         /* Cleanup multicast configuration */
9371         rparam.mcast_obj = &bp->mcast_obj;
9372         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9373         if (rc < 0)
9374                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9375
9376         netif_addr_unlock_bh(bp->dev);
9377
9378         bnx2x_iov_chip_cleanup(bp);
9379
9380         /*
9381          * Send the UNLOAD_REQUEST to the MCP. This will return if
9382          * this function should perform FUNC, PORT or COMMON HW
9383          * reset.
9384          */
9385         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9386
9387         /*
9388          * (assumption: No Attention from MCP at this stage)
9389          * PMF probably in the middle of TX disable/enable transaction
9390          */
9391         rc = bnx2x_func_wait_started(bp);
9392         if (rc) {
9393                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9394 #ifdef BNX2X_STOP_ON_ERROR
9395                 return;
9396 #endif
9397         }
9398
9399         /* Close multi and leading connections
9400          * Completions for ramrods are collected in a synchronous way
9401          */
9402         for_each_eth_queue(bp, i)
9403                 if (bnx2x_stop_queue(bp, i))
9404 #ifdef BNX2X_STOP_ON_ERROR
9405                         return;
9406 #else
9407                         goto unload_error;
9408 #endif
9409
9410         if (CNIC_LOADED(bp)) {
9411                 for_each_cnic_queue(bp, i)
9412                         if (bnx2x_stop_queue(bp, i))
9413 #ifdef BNX2X_STOP_ON_ERROR
9414                                 return;
9415 #else
9416                                 goto unload_error;
9417 #endif
9418         }
9419
9420         /* If SP settings didn't get completed so far - something
9421          * very wrong has happen.
9422          */
9423         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9424                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9425
9426 #ifndef BNX2X_STOP_ON_ERROR
9427 unload_error:
9428 #endif
9429         rc = bnx2x_func_stop(bp);
9430         if (rc) {
9431                 BNX2X_ERR("Function stop failed!\n");
9432 #ifdef BNX2X_STOP_ON_ERROR
9433                 return;
9434 #endif
9435         }
9436
9437         /* stop_ptp should be after the Tx queues are drained to prevent
9438          * scheduling to the cancelled PTP work queue. It should also be after
9439          * function stop ramrod is sent, since as part of this ramrod FW access
9440          * PTP registers.
9441          */
9442         if (bp->flags & PTP_SUPPORTED) {
9443                 bnx2x_stop_ptp(bp);
9444                 if (bp->ptp_clock) {
9445                         ptp_clock_unregister(bp->ptp_clock);
9446                         bp->ptp_clock = NULL;
9447                 }
9448         }
9449
9450         /* Disable HW interrupts, NAPI */
9451         bnx2x_netif_stop(bp, 1);
9452         /* Delete all NAPI objects */
9453         bnx2x_del_all_napi(bp);
9454         if (CNIC_LOADED(bp))
9455                 bnx2x_del_all_napi_cnic(bp);
9456
9457         /* Release IRQs */
9458         bnx2x_free_irq(bp);
9459
9460         /* Reset the chip, unless PCI function is offline. If we reach this
9461          * point following a PCI error handling, it means device is really
9462          * in a bad state and we're about to remove it, so reset the chip
9463          * is not a good idea.
9464          */
9465         if (!pci_channel_offline(bp->pdev)) {
9466                 rc = bnx2x_reset_hw(bp, reset_code);
9467                 if (rc)
9468                         BNX2X_ERR("HW_RESET failed\n");
9469         }
9470
9471         /* Report UNLOAD_DONE to MCP */
9472         bnx2x_send_unload_done(bp, keep_link);
9473 }
9474
9475 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9476 {
9477         u32 val;
9478
9479         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9480
9481         if (CHIP_IS_E1(bp)) {
9482                 int port = BP_PORT(bp);
9483                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9484                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9485
9486                 val = REG_RD(bp, addr);
9487                 val &= ~(0x300);
9488                 REG_WR(bp, addr, val);
9489         } else {
9490                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9491                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9492                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9493                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9494         }
9495 }
9496
9497 /* Close gates #2, #3 and #4: */
9498 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9499 {
9500         u32 val;
9501
9502         /* Gates #2 and #4a are closed/opened for "not E1" only */
9503         if (!CHIP_IS_E1(bp)) {
9504                 /* #4 */
9505                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9506                 /* #2 */
9507                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9508         }
9509
9510         /* #3 */
9511         if (CHIP_IS_E1x(bp)) {
9512                 /* Prevent interrupts from HC on both ports */
9513                 val = REG_RD(bp, HC_REG_CONFIG_1);
9514                 REG_WR(bp, HC_REG_CONFIG_1,
9515                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9516                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9517
9518                 val = REG_RD(bp, HC_REG_CONFIG_0);
9519                 REG_WR(bp, HC_REG_CONFIG_0,
9520                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9521                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9522         } else {
9523                 /* Prevent incoming interrupts in IGU */
9524                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9525
9526                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9527                        (!close) ?
9528                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9529                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9530         }
9531
9532         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9533                 close ? "closing" : "opening");
9534 }
9535
9536 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9537
9538 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9539 {
9540         /* Do some magic... */
9541         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9542         *magic_val = val & SHARED_MF_CLP_MAGIC;
9543         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9544 }
9545
9546 /**
9547  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9548  *
9549  * @bp:         driver handle
9550  * @magic_val:  old value of the `magic' bit.
9551  */
9552 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9553 {
9554         /* Restore the `magic' bit value... */
9555         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9556         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9557                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9558 }
9559
9560 /**
9561  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9562  *
9563  * @bp:         driver handle
9564  * @magic_val:  old value of 'magic' bit.
9565  *
9566  * Takes care of CLP configurations.
9567  */
9568 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9569 {
9570         u32 shmem;
9571         u32 validity_offset;
9572
9573         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9574
9575         /* Set `magic' bit in order to save MF config */
9576         if (!CHIP_IS_E1(bp))
9577                 bnx2x_clp_reset_prep(bp, magic_val);
9578
9579         /* Get shmem offset */
9580         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9581         validity_offset =
9582                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9583
9584         /* Clear validity map flags */
9585         if (shmem > 0)
9586                 REG_WR(bp, shmem + validity_offset, 0);
9587 }
9588
9589 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9590 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9591
9592 /**
9593  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9594  *
9595  * @bp: driver handle
9596  */
9597 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9598 {
9599         /* special handling for emulation and FPGA,
9600            wait 10 times longer */
9601         if (CHIP_REV_IS_SLOW(bp))
9602                 msleep(MCP_ONE_TIMEOUT*10);
9603         else
9604                 msleep(MCP_ONE_TIMEOUT);
9605 }
9606
9607 /*
9608  * initializes bp->common.shmem_base and waits for validity signature to appear
9609  */
9610 static int bnx2x_init_shmem(struct bnx2x *bp)
9611 {
9612         int cnt = 0;
9613         u32 val = 0;
9614
9615         do {
9616                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9617
9618                 /* If we read all 0xFFs, means we are in PCI error state and
9619                  * should bail out to avoid crashes on adapter's FW reads.
9620                  */
9621                 if (bp->common.shmem_base == 0xFFFFFFFF) {
9622                         bp->flags |= NO_MCP_FLAG;
9623                         return -ENODEV;
9624                 }
9625
9626                 if (bp->common.shmem_base) {
9627                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9628                         if (val & SHR_MEM_VALIDITY_MB)
9629                                 return 0;
9630                 }
9631
9632                 bnx2x_mcp_wait_one(bp);
9633
9634         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9635
9636         BNX2X_ERR("BAD MCP validity signature\n");
9637
9638         return -ENODEV;
9639 }
9640
9641 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9642 {
9643         int rc = bnx2x_init_shmem(bp);
9644
9645         /* Restore the `magic' bit value */
9646         if (!CHIP_IS_E1(bp))
9647                 bnx2x_clp_reset_done(bp, magic_val);
9648
9649         return rc;
9650 }
9651
9652 static void bnx2x_pxp_prep(struct bnx2x *bp)
9653 {
9654         if (!CHIP_IS_E1(bp)) {
9655                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9656                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9657         }
9658 }
9659
9660 /*
9661  * Reset the whole chip except for:
9662  *      - PCIE core
9663  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9664  *              one reset bit)
9665  *      - IGU
9666  *      - MISC (including AEU)
9667  *      - GRC
9668  *      - RBCN, RBCP
9669  */
9670 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9671 {
9672         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9673         u32 global_bits2, stay_reset2;
9674
9675         /*
9676          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9677          * (per chip) blocks.
9678          */
9679         global_bits2 =
9680                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9681                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9682
9683         /* Don't reset the following blocks.
9684          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9685          *            reset, as in 4 port device they might still be owned
9686          *            by the MCP (there is only one leader per path).
9687          */
9688         not_reset_mask1 =
9689                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9690                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9691                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9692
9693         not_reset_mask2 =
9694                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9695                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9696                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9697                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9698                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9699                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9700                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9701                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9702                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9703                 MISC_REGISTERS_RESET_REG_2_PGLC |
9704                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9705                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9706                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9707                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9708                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9709                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9710
9711         /*
9712          * Keep the following blocks in reset:
9713          *  - all xxMACs are handled by the bnx2x_link code.
9714          */
9715         stay_reset2 =
9716                 MISC_REGISTERS_RESET_REG_2_XMAC |
9717                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9718
9719         /* Full reset masks according to the chip */
9720         reset_mask1 = 0xffffffff;
9721
9722         if (CHIP_IS_E1(bp))
9723                 reset_mask2 = 0xffff;
9724         else if (CHIP_IS_E1H(bp))
9725                 reset_mask2 = 0x1ffff;
9726         else if (CHIP_IS_E2(bp))
9727                 reset_mask2 = 0xfffff;
9728         else /* CHIP_IS_E3 */
9729                 reset_mask2 = 0x3ffffff;
9730
9731         /* Don't reset global blocks unless we need to */
9732         if (!global)
9733                 reset_mask2 &= ~global_bits2;
9734
9735         /*
9736          * In case of attention in the QM, we need to reset PXP
9737          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9738          * because otherwise QM reset would release 'close the gates' shortly
9739          * before resetting the PXP, then the PSWRQ would send a write
9740          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9741          * read the payload data from PSWWR, but PSWWR would not
9742          * respond. The write queue in PGLUE would stuck, dmae commands
9743          * would not return. Therefore it's important to reset the second
9744          * reset register (containing the
9745          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9746          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9747          * bit).
9748          */
9749         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9750                reset_mask2 & (~not_reset_mask2));
9751
9752         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9753                reset_mask1 & (~not_reset_mask1));
9754
9755         barrier();
9756
9757         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9758                reset_mask2 & (~stay_reset2));
9759
9760         barrier();
9761
9762         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9763 }
9764
9765 /**
9766  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9767  * It should get cleared in no more than 1s.
9768  *
9769  * @bp: driver handle
9770  *
9771  * It should get cleared in no more than 1s. Returns 0 if
9772  * pending writes bit gets cleared.
9773  */
9774 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9775 {
9776         u32 cnt = 1000;
9777         u32 pend_bits = 0;
9778
9779         do {
9780                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9781
9782                 if (pend_bits == 0)
9783                         break;
9784
9785                 usleep_range(1000, 2000);
9786         } while (cnt-- > 0);
9787
9788         if (cnt <= 0) {
9789                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9790                           pend_bits);
9791                 return -EBUSY;
9792         }
9793
9794         return 0;
9795 }
9796
9797 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9798 {
9799         int cnt = 1000;
9800         u32 val = 0;
9801         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9802         u32 tags_63_32 = 0;
9803
9804         /* Empty the Tetris buffer, wait for 1s */
9805         do {
9806                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9807                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9808                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9809                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9810                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9811                 if (CHIP_IS_E3(bp))
9812                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9813
9814                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9815                     ((port_is_idle_0 & 0x1) == 0x1) &&
9816                     ((port_is_idle_1 & 0x1) == 0x1) &&
9817                     (pgl_exp_rom2 == 0xffffffff) &&
9818                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9819                         break;
9820                 usleep_range(1000, 2000);
9821         } while (cnt-- > 0);
9822
9823         if (cnt <= 0) {
9824                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9825                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9826                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9827                           pgl_exp_rom2);
9828                 return -EAGAIN;
9829         }
9830
9831         barrier();
9832
9833         /* Close gates #2, #3 and #4 */
9834         bnx2x_set_234_gates(bp, true);
9835
9836         /* Poll for IGU VQs for 57712 and newer chips */
9837         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9838                 return -EAGAIN;
9839
9840         /* TBD: Indicate that "process kill" is in progress to MCP */
9841
9842         /* Clear "unprepared" bit */
9843         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9844         barrier();
9845
9846         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9847          * PSWHST, GRC and PSWRD Tetris buffer.
9848          */
9849         usleep_range(1000, 2000);
9850
9851         /* Prepare to chip reset: */
9852         /* MCP */
9853         if (global)
9854                 bnx2x_reset_mcp_prep(bp, &val);
9855
9856         /* PXP */
9857         bnx2x_pxp_prep(bp);
9858         barrier();
9859
9860         /* reset the chip */
9861         bnx2x_process_kill_chip_reset(bp, global);
9862         barrier();
9863
9864         /* clear errors in PGB */
9865         if (!CHIP_IS_E1x(bp))
9866                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9867
9868         /* Recover after reset: */
9869         /* MCP */
9870         if (global && bnx2x_reset_mcp_comp(bp, val))
9871                 return -EAGAIN;
9872
9873         /* TBD: Add resetting the NO_MCP mode DB here */
9874
9875         /* Open the gates #2, #3 and #4 */
9876         bnx2x_set_234_gates(bp, false);
9877
9878         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9879          * reset state, re-enable attentions. */
9880
9881         return 0;
9882 }
9883
9884 static int bnx2x_leader_reset(struct bnx2x *bp)
9885 {
9886         int rc = 0;
9887         bool global = bnx2x_reset_is_global(bp);
9888         u32 load_code;
9889
9890         /* if not going to reset MCP - load "fake" driver to reset HW while
9891          * driver is owner of the HW
9892          */
9893         if (!global && !BP_NOMCP(bp)) {
9894                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9895                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9896                 if (!load_code) {
9897                         BNX2X_ERR("MCP response failure, aborting\n");
9898                         rc = -EAGAIN;
9899                         goto exit_leader_reset;
9900                 }
9901                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9902                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9903                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9904                         rc = -EAGAIN;
9905                         goto exit_leader_reset2;
9906                 }
9907                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9908                 if (!load_code) {
9909                         BNX2X_ERR("MCP response failure, aborting\n");
9910                         rc = -EAGAIN;
9911                         goto exit_leader_reset2;
9912                 }
9913         }
9914
9915         /* Try to recover after the failure */
9916         if (bnx2x_process_kill(bp, global)) {
9917                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9918                           BP_PATH(bp));
9919                 rc = -EAGAIN;
9920                 goto exit_leader_reset2;
9921         }
9922
9923         /*
9924          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9925          * state.
9926          */
9927         bnx2x_set_reset_done(bp);
9928         if (global)
9929                 bnx2x_clear_reset_global(bp);
9930
9931 exit_leader_reset2:
9932         /* unload "fake driver" if it was loaded */
9933         if (!global && !BP_NOMCP(bp)) {
9934                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9935                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9936         }
9937 exit_leader_reset:
9938         bp->is_leader = 0;
9939         bnx2x_release_leader_lock(bp);
9940         smp_mb();
9941         return rc;
9942 }
9943
9944 static void bnx2x_recovery_failed(struct bnx2x *bp)
9945 {
9946         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9947
9948         /* Disconnect this device */
9949         netif_device_detach(bp->dev);
9950
9951         /*
9952          * Block ifup for all function on this engine until "process kill"
9953          * or power cycle.
9954          */
9955         bnx2x_set_reset_in_progress(bp);
9956
9957         /* Shut down the power */
9958         bnx2x_set_power_state(bp, PCI_D3hot);
9959
9960         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9961
9962         smp_mb();
9963 }
9964
9965 /*
9966  * Assumption: runs under rtnl lock. This together with the fact
9967  * that it's called only from bnx2x_sp_rtnl() ensure that it
9968  * will never be called when netif_running(bp->dev) is false.
9969  */
9970 static void bnx2x_parity_recover(struct bnx2x *bp)
9971 {
9972         bool global = false;
9973         u32 error_recovered, error_unrecovered;
9974         bool is_parity;
9975
9976         DP(NETIF_MSG_HW, "Handling parity\n");
9977         while (1) {
9978                 switch (bp->recovery_state) {
9979                 case BNX2X_RECOVERY_INIT:
9980                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9981                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9982                         WARN_ON(!is_parity);
9983
9984                         /* Try to get a LEADER_LOCK HW lock */
9985                         if (bnx2x_trylock_leader_lock(bp)) {
9986                                 bnx2x_set_reset_in_progress(bp);
9987                                 /*
9988                                  * Check if there is a global attention and if
9989                                  * there was a global attention, set the global
9990                                  * reset bit.
9991                                  */
9992
9993                                 if (global)
9994                                         bnx2x_set_reset_global(bp);
9995
9996                                 bp->is_leader = 1;
9997                         }
9998
9999                         /* Stop the driver */
10000                         /* If interface has been removed - break */
10001                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
10002                                 return;
10003
10004                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
10005
10006                         /* Ensure "is_leader", MCP command sequence and
10007                          * "recovery_state" update values are seen on other
10008                          * CPUs.
10009                          */
10010                         smp_mb();
10011                         break;
10012
10013                 case BNX2X_RECOVERY_WAIT:
10014                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
10015                         if (bp->is_leader) {
10016                                 int other_engine = BP_PATH(bp) ? 0 : 1;
10017                                 bool other_load_status =
10018                                         bnx2x_get_load_status(bp, other_engine);
10019                                 bool load_status =
10020                                         bnx2x_get_load_status(bp, BP_PATH(bp));
10021                                 global = bnx2x_reset_is_global(bp);
10022
10023                                 /*
10024                                  * In case of a parity in a global block, let
10025                                  * the first leader that performs a
10026                                  * leader_reset() reset the global blocks in
10027                                  * order to clear global attentions. Otherwise
10028                                  * the gates will remain closed for that
10029                                  * engine.
10030                                  */
10031                                 if (load_status ||
10032                                     (global && other_load_status)) {
10033                                         /* Wait until all other functions get
10034                                          * down.
10035                                          */
10036                                         schedule_delayed_work(&bp->sp_rtnl_task,
10037                                                                 HZ/10);
10038                                         return;
10039                                 } else {
10040                                         /* If all other functions got down -
10041                                          * try to bring the chip back to
10042                                          * normal. In any case it's an exit
10043                                          * point for a leader.
10044                                          */
10045                                         if (bnx2x_leader_reset(bp)) {
10046                                                 bnx2x_recovery_failed(bp);
10047                                                 return;
10048                                         }
10049
10050                                         /* If we are here, means that the
10051                                          * leader has succeeded and doesn't
10052                                          * want to be a leader any more. Try
10053                                          * to continue as a none-leader.
10054                                          */
10055                                         break;
10056                                 }
10057                         } else { /* non-leader */
10058                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10059                                         /* Try to get a LEADER_LOCK HW lock as
10060                                          * long as a former leader may have
10061                                          * been unloaded by the user or
10062                                          * released a leadership by another
10063                                          * reason.
10064                                          */
10065                                         if (bnx2x_trylock_leader_lock(bp)) {
10066                                                 /* I'm a leader now! Restart a
10067                                                  * switch case.
10068                                                  */
10069                                                 bp->is_leader = 1;
10070                                                 break;
10071                                         }
10072
10073                                         schedule_delayed_work(&bp->sp_rtnl_task,
10074                                                                 HZ/10);
10075                                         return;
10076
10077                                 } else {
10078                                         /*
10079                                          * If there was a global attention, wait
10080                                          * for it to be cleared.
10081                                          */
10082                                         if (bnx2x_reset_is_global(bp)) {
10083                                                 schedule_delayed_work(
10084                                                         &bp->sp_rtnl_task,
10085                                                         HZ/10);
10086                                                 return;
10087                                         }
10088
10089                                         error_recovered =
10090                                           bp->eth_stats.recoverable_error;
10091                                         error_unrecovered =
10092                                           bp->eth_stats.unrecoverable_error;
10093                                         bp->recovery_state =
10094                                                 BNX2X_RECOVERY_NIC_LOADING;
10095                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10096                                                 error_unrecovered++;
10097                                                 netdev_err(bp->dev,
10098                                                            "Recovery failed. Power cycle needed\n");
10099                                                 /* Disconnect this device */
10100                                                 netif_device_detach(bp->dev);
10101                                                 /* Shut down the power */
10102                                                 bnx2x_set_power_state(
10103                                                         bp, PCI_D3hot);
10104                                                 smp_mb();
10105                                         } else {
10106                                                 bp->recovery_state =
10107                                                         BNX2X_RECOVERY_DONE;
10108                                                 error_recovered++;
10109                                                 smp_mb();
10110                                         }
10111                                         bp->eth_stats.recoverable_error =
10112                                                 error_recovered;
10113                                         bp->eth_stats.unrecoverable_error =
10114                                                 error_unrecovered;
10115
10116                                         return;
10117                                 }
10118                         }
10119                 default:
10120                         return;
10121                 }
10122         }
10123 }
10124
10125 static int bnx2x_udp_port_update(struct bnx2x *bp)
10126 {
10127         struct bnx2x_func_switch_update_params *switch_update_params;
10128         struct bnx2x_func_state_params func_params = {NULL};
10129         struct bnx2x_udp_tunnel *udp_tunnel;
10130         u16 vxlan_port = 0, geneve_port = 0;
10131         int rc;
10132
10133         switch_update_params = &func_params.params.switch_update;
10134
10135         /* Prepare parameters for function state transitions */
10136         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10137         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10138
10139         func_params.f_obj = &bp->func_obj;
10140         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10141
10142         /* Function parameters */
10143         __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10144                   &switch_update_params->changes);
10145
10146         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10147                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10148                 geneve_port = udp_tunnel->dst_port;
10149                 switch_update_params->geneve_dst_port = geneve_port;
10150         }
10151
10152         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10153                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10154                 vxlan_port = udp_tunnel->dst_port;
10155                 switch_update_params->vxlan_dst_port = vxlan_port;
10156         }
10157
10158         /* Re-enable inner-rss for the offloaded UDP tunnels */
10159         __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10160                   &switch_update_params->changes);
10161
10162         rc = bnx2x_func_state_change(bp, &func_params);
10163         if (rc)
10164                 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10165                           vxlan_port, geneve_port, rc);
10166         else
10167                 DP(BNX2X_MSG_SP,
10168                    "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10169                    vxlan_port, geneve_port);
10170
10171         return rc;
10172 }
10173
10174 static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10175                                  enum bnx2x_udp_port_type type)
10176 {
10177         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10178
10179         if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp))
10180                 return;
10181
10182         if (udp_port->count && udp_port->dst_port == port) {
10183                 udp_port->count++;
10184                 return;
10185         }
10186
10187         if (udp_port->count) {
10188                 DP(BNX2X_MSG_SP,
10189                    "UDP tunnel [%d] -  destination port limit reached\n",
10190                    type);
10191                 return;
10192         }
10193
10194         udp_port->dst_port = port;
10195         udp_port->count = 1;
10196         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10197 }
10198
10199 static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10200                                  enum bnx2x_udp_port_type type)
10201 {
10202         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10203
10204         if (!IS_PF(bp) || CHIP_IS_E1x(bp))
10205                 return;
10206
10207         if (!udp_port->count || udp_port->dst_port != port) {
10208                 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10209                    type);
10210                 return;
10211         }
10212
10213         /* Remove reference, and make certain it's no longer in use */
10214         udp_port->count--;
10215         if (udp_port->count)
10216                 return;
10217         udp_port->dst_port = 0;
10218
10219         if (netif_running(bp->dev))
10220                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10221         else
10222                 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10223                    type, port);
10224 }
10225
10226 static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10227                                  struct udp_tunnel_info *ti)
10228 {
10229         struct bnx2x *bp = netdev_priv(netdev);
10230         u16 t_port = ntohs(ti->port);
10231
10232         switch (ti->type) {
10233         case UDP_TUNNEL_TYPE_VXLAN:
10234                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10235                 break;
10236         case UDP_TUNNEL_TYPE_GENEVE:
10237                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10238                 break;
10239         default:
10240                 break;
10241         }
10242 }
10243
10244 static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10245                                  struct udp_tunnel_info *ti)
10246 {
10247         struct bnx2x *bp = netdev_priv(netdev);
10248         u16 t_port = ntohs(ti->port);
10249
10250         switch (ti->type) {
10251         case UDP_TUNNEL_TYPE_VXLAN:
10252                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10253                 break;
10254         case UDP_TUNNEL_TYPE_GENEVE:
10255                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10256                 break;
10257         default:
10258                 break;
10259         }
10260 }
10261
10262 static int bnx2x_close(struct net_device *dev);
10263
10264 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10265  * scheduled on a general queue in order to prevent a dead lock.
10266  */
10267 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10268 {
10269         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10270
10271         rtnl_lock();
10272
10273         if (!netif_running(bp->dev)) {
10274                 rtnl_unlock();
10275                 return;
10276         }
10277
10278         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10279 #ifdef BNX2X_STOP_ON_ERROR
10280                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10281                           "you will need to reboot when done\n");
10282                 goto sp_rtnl_not_reset;
10283 #endif
10284                 /*
10285                  * Clear all pending SP commands as we are going to reset the
10286                  * function anyway.
10287                  */
10288                 bp->sp_rtnl_state = 0;
10289                 smp_mb();
10290
10291                 bnx2x_parity_recover(bp);
10292
10293                 rtnl_unlock();
10294                 return;
10295         }
10296
10297         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10298 #ifdef BNX2X_STOP_ON_ERROR
10299                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10300                           "you will need to reboot when done\n");
10301                 goto sp_rtnl_not_reset;
10302 #endif
10303
10304                 /*
10305                  * Clear all pending SP commands as we are going to reset the
10306                  * function anyway.
10307                  */
10308                 bp->sp_rtnl_state = 0;
10309                 smp_mb();
10310
10311                 /* Immediately indicate link as down */
10312                 bp->link_vars.link_up = 0;
10313                 bp->force_link_down = true;
10314                 netif_carrier_off(bp->dev);
10315                 BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
10316
10317                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10318                 /* When ret value shows failure of allocation failure,
10319                  * the nic is rebooted again. If open still fails, a error
10320                  * message to notify the user.
10321                  */
10322                 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) {
10323                         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10324                         if (bnx2x_nic_load(bp, LOAD_NORMAL))
10325                                 BNX2X_ERR("Open the NIC fails again!\n");
10326                 }
10327                 rtnl_unlock();
10328                 return;
10329         }
10330 #ifdef BNX2X_STOP_ON_ERROR
10331 sp_rtnl_not_reset:
10332 #endif
10333         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10334                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10335         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10336                 bnx2x_after_function_update(bp);
10337         /*
10338          * in case of fan failure we need to reset id if the "stop on error"
10339          * debug flag is set, since we trying to prevent permanent overheating
10340          * damage
10341          */
10342         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10343                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10344                 netif_device_detach(bp->dev);
10345                 bnx2x_close(bp->dev);
10346                 rtnl_unlock();
10347                 return;
10348         }
10349
10350         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10351                 DP(BNX2X_MSG_SP,
10352                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10353                 bnx2x_vfpf_set_mcast(bp->dev);
10354         }
10355         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10356                                &bp->sp_rtnl_state)){
10357                 if (netif_carrier_ok(bp->dev)) {
10358                         bnx2x_tx_disable(bp);
10359                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10360                 }
10361         }
10362
10363         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10364                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10365                 bnx2x_set_rx_mode_inner(bp);
10366         }
10367
10368         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10369                                &bp->sp_rtnl_state))
10370                 bnx2x_pf_set_vfs_vlan(bp);
10371
10372         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10373                 bnx2x_dcbx_stop_hw_tx(bp);
10374                 bnx2x_dcbx_resume_hw_tx(bp);
10375         }
10376
10377         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10378                                &bp->sp_rtnl_state))
10379                 bnx2x_update_mng_version(bp);
10380
10381         if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state))
10382                 bnx2x_handle_update_svid_cmd(bp);
10383
10384         if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
10385                                &bp->sp_rtnl_state)) {
10386                 if (bnx2x_udp_port_update(bp)) {
10387                         /* On error, forget configuration */
10388                         memset(bp->udp_tunnel_ports, 0,
10389                                sizeof(struct bnx2x_udp_tunnel) *
10390                                BNX2X_UDP_PORT_MAX);
10391                 } else {
10392                         /* Since we don't store additional port information,
10393                          * if no ports are configured for any feature ask for
10394                          * information about currently configured ports.
10395                          */
10396                         if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10397                             !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10398                                 udp_tunnel_get_rx_info(bp->dev);
10399                 }
10400         }
10401
10402         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10403          * can be called from other contexts as well)
10404          */
10405         rtnl_unlock();
10406
10407         /* enable SR-IOV if applicable */
10408         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10409                                                &bp->sp_rtnl_state)) {
10410                 bnx2x_disable_sriov(bp);
10411                 bnx2x_enable_sriov(bp);
10412         }
10413 }
10414
10415 static void bnx2x_period_task(struct work_struct *work)
10416 {
10417         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10418
10419         if (!netif_running(bp->dev))
10420                 goto period_task_exit;
10421
10422         if (CHIP_REV_IS_SLOW(bp)) {
10423                 BNX2X_ERR("period task called on emulation, ignoring\n");
10424                 goto period_task_exit;
10425         }
10426
10427         bnx2x_acquire_phy_lock(bp);
10428         /*
10429          * The barrier is needed to ensure the ordering between the writing to
10430          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10431          * the reading here.
10432          */
10433         smp_mb();
10434         if (bp->port.pmf) {
10435                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10436
10437                 /* Re-queue task in 1 sec */
10438                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10439         }
10440
10441         bnx2x_release_phy_lock(bp);
10442 period_task_exit:
10443         return;
10444 }
10445
10446 /*
10447  * Init service functions
10448  */
10449
10450 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10451 {
10452         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10453         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10454         return base + (BP_ABS_FUNC(bp)) * stride;
10455 }
10456
10457 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10458                                          u8 port, u32 reset_reg,
10459                                          struct bnx2x_mac_vals *vals)
10460 {
10461         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10462         u32 base_addr;
10463
10464         if (!(mask & reset_reg))
10465                 return false;
10466
10467         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10468         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10469         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10470         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10471         REG_WR(bp, vals->umac_addr[port], 0);
10472
10473         return true;
10474 }
10475
10476 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10477                                         struct bnx2x_mac_vals *vals)
10478 {
10479         u32 val, base_addr, offset, mask, reset_reg;
10480         bool mac_stopped = false;
10481         u8 port = BP_PORT(bp);
10482
10483         /* reset addresses as they also mark which values were changed */
10484         memset(vals, 0, sizeof(*vals));
10485
10486         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10487
10488         if (!CHIP_IS_E3(bp)) {
10489                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10490                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10491                 if ((mask & reset_reg) && val) {
10492                         u32 wb_data[2];
10493                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10494                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10495                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10496                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10497                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10498
10499                         /*
10500                          * use rd/wr since we cannot use dmae. This is safe
10501                          * since MCP won't access the bus due to the request
10502                          * to unload, and no function on the path can be
10503                          * loaded at this time.
10504                          */
10505                         wb_data[0] = REG_RD(bp, base_addr + offset);
10506                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10507                         vals->bmac_addr = base_addr + offset;
10508                         vals->bmac_val[0] = wb_data[0];
10509                         vals->bmac_val[1] = wb_data[1];
10510                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10511                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10512                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10513                 }
10514                 BNX2X_DEV_INFO("Disable emac Rx\n");
10515                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10516                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10517                 REG_WR(bp, vals->emac_addr, 0);
10518                 mac_stopped = true;
10519         } else {
10520                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10521                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10522                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10523                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10524                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10525                                val & ~(1 << 1));
10526                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10527                                val | (1 << 1));
10528                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10529                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10530                         REG_WR(bp, vals->xmac_addr, 0);
10531                         mac_stopped = true;
10532                 }
10533
10534                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10535                                                             reset_reg, vals);
10536                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10537                                                             reset_reg, vals);
10538         }
10539
10540         if (mac_stopped)
10541                 msleep(20);
10542 }
10543
10544 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10545 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10546                                         0x1848 + ((f) << 4))
10547 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10548 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10549 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10550
10551 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10552 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10553 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10554
10555 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10556 {
10557         /* UNDI marks its presence in DORQ -
10558          * it initializes CID offset for normal bell to 0x7
10559          */
10560         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10561             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10562                 return false;
10563
10564         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10565                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10566                 return true;
10567         }
10568
10569         return false;
10570 }
10571
10572 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10573 {
10574         u16 rcq, bd;
10575         u32 addr, tmp_reg;
10576
10577         if (BP_FUNC(bp) < 2)
10578                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10579         else
10580                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10581
10582         tmp_reg = REG_RD(bp, addr);
10583         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10584         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10585
10586         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10587         REG_WR(bp, addr, tmp_reg);
10588
10589         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10590                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10591 }
10592
10593 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10594 {
10595         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10596                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10597         if (!rc) {
10598                 BNX2X_ERR("MCP response failure, aborting\n");
10599                 return -EBUSY;
10600         }
10601
10602         return 0;
10603 }
10604
10605 static struct bnx2x_prev_path_list *
10606                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10607 {
10608         struct bnx2x_prev_path_list *tmp_list;
10609
10610         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10611                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10612                     bp->pdev->bus->number == tmp_list->bus &&
10613                     BP_PATH(bp) == tmp_list->path)
10614                         return tmp_list;
10615
10616         return NULL;
10617 }
10618
10619 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10620 {
10621         struct bnx2x_prev_path_list *tmp_list;
10622         int rc;
10623
10624         rc = down_interruptible(&bnx2x_prev_sem);
10625         if (rc) {
10626                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10627                 return rc;
10628         }
10629
10630         tmp_list = bnx2x_prev_path_get_entry(bp);
10631         if (tmp_list) {
10632                 tmp_list->aer = 1;
10633                 rc = 0;
10634         } else {
10635                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10636                           BP_PATH(bp));
10637         }
10638
10639         up(&bnx2x_prev_sem);
10640
10641         return rc;
10642 }
10643
10644 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10645 {
10646         struct bnx2x_prev_path_list *tmp_list;
10647         bool rc = false;
10648
10649         if (down_trylock(&bnx2x_prev_sem))
10650                 return false;
10651
10652         tmp_list = bnx2x_prev_path_get_entry(bp);
10653         if (tmp_list) {
10654                 if (tmp_list->aer) {
10655                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10656                            BP_PATH(bp));
10657                 } else {
10658                         rc = true;
10659                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10660                                        BP_PATH(bp));
10661                 }
10662         }
10663
10664         up(&bnx2x_prev_sem);
10665
10666         return rc;
10667 }
10668
10669 bool bnx2x_port_after_undi(struct bnx2x *bp)
10670 {
10671         struct bnx2x_prev_path_list *entry;
10672         bool val;
10673
10674         down(&bnx2x_prev_sem);
10675
10676         entry = bnx2x_prev_path_get_entry(bp);
10677         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10678
10679         up(&bnx2x_prev_sem);
10680
10681         return val;
10682 }
10683
10684 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10685 {
10686         struct bnx2x_prev_path_list *tmp_list;
10687         int rc;
10688
10689         rc = down_interruptible(&bnx2x_prev_sem);
10690         if (rc) {
10691                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10692                 return rc;
10693         }
10694
10695         /* Check whether the entry for this path already exists */
10696         tmp_list = bnx2x_prev_path_get_entry(bp);
10697         if (tmp_list) {
10698                 if (!tmp_list->aer) {
10699                         BNX2X_ERR("Re-Marking the path.\n");
10700                 } else {
10701                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10702                            BP_PATH(bp));
10703                         tmp_list->aer = 0;
10704                 }
10705                 up(&bnx2x_prev_sem);
10706                 return 0;
10707         }
10708         up(&bnx2x_prev_sem);
10709
10710         /* Create an entry for this path and add it */
10711         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10712         if (!tmp_list) {
10713                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10714                 return -ENOMEM;
10715         }
10716
10717         tmp_list->bus = bp->pdev->bus->number;
10718         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10719         tmp_list->path = BP_PATH(bp);
10720         tmp_list->aer = 0;
10721         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10722
10723         rc = down_interruptible(&bnx2x_prev_sem);
10724         if (rc) {
10725                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10726                 kfree(tmp_list);
10727         } else {
10728                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10729                    BP_PATH(bp));
10730                 list_add(&tmp_list->list, &bnx2x_prev_list);
10731                 up(&bnx2x_prev_sem);
10732         }
10733
10734         return rc;
10735 }
10736
10737 static int bnx2x_do_flr(struct bnx2x *bp)
10738 {
10739         struct pci_dev *dev = bp->pdev;
10740
10741         if (CHIP_IS_E1x(bp)) {
10742                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10743                 return -EINVAL;
10744         }
10745
10746         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10747         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10748                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10749                           bp->common.bc_ver);
10750                 return -EINVAL;
10751         }
10752
10753         if (!pci_wait_for_pending_transaction(dev))
10754                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10755
10756         BNX2X_DEV_INFO("Initiating FLR\n");
10757         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10758
10759         return 0;
10760 }
10761
10762 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10763 {
10764         int rc;
10765
10766         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10767
10768         /* Test if previous unload process was already finished for this path */
10769         if (bnx2x_prev_is_path_marked(bp))
10770                 return bnx2x_prev_mcp_done(bp);
10771
10772         BNX2X_DEV_INFO("Path is unmarked\n");
10773
10774         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10775         if (bnx2x_prev_is_after_undi(bp))
10776                 goto out;
10777
10778         /* If function has FLR capabilities, and existing FW version matches
10779          * the one required, then FLR will be sufficient to clean any residue
10780          * left by previous driver
10781          */
10782         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10783
10784         if (!rc) {
10785                 /* fw version is good */
10786                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10787                 rc = bnx2x_do_flr(bp);
10788         }
10789
10790         if (!rc) {
10791                 /* FLR was performed */
10792                 BNX2X_DEV_INFO("FLR successful\n");
10793                 return 0;
10794         }
10795
10796         BNX2X_DEV_INFO("Could not FLR\n");
10797
10798 out:
10799         /* Close the MCP request, return failure*/
10800         rc = bnx2x_prev_mcp_done(bp);
10801         if (!rc)
10802                 rc = BNX2X_PREV_WAIT_NEEDED;
10803
10804         return rc;
10805 }
10806
10807 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10808 {
10809         u32 reset_reg, tmp_reg = 0, rc;
10810         bool prev_undi = false;
10811         struct bnx2x_mac_vals mac_vals;
10812
10813         /* It is possible a previous function received 'common' answer,
10814          * but hasn't loaded yet, therefore creating a scenario of
10815          * multiple functions receiving 'common' on the same path.
10816          */
10817         BNX2X_DEV_INFO("Common unload Flow\n");
10818
10819         memset(&mac_vals, 0, sizeof(mac_vals));
10820
10821         if (bnx2x_prev_is_path_marked(bp))
10822                 return bnx2x_prev_mcp_done(bp);
10823
10824         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10825
10826         /* Reset should be performed after BRB is emptied */
10827         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10828                 u32 timer_count = 1000;
10829
10830                 /* Close the MAC Rx to prevent BRB from filling up */
10831                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10832
10833                 /* close LLH filters for both ports towards the BRB */
10834                 bnx2x_set_rx_filter(&bp->link_params, 0);
10835                 bp->link_params.port ^= 1;
10836                 bnx2x_set_rx_filter(&bp->link_params, 0);
10837                 bp->link_params.port ^= 1;
10838
10839                 /* Check if the UNDI driver was previously loaded */
10840                 if (bnx2x_prev_is_after_undi(bp)) {
10841                         prev_undi = true;
10842                         /* clear the UNDI indication */
10843                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10844                         /* clear possible idle check errors */
10845                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10846                 }
10847                 if (!CHIP_IS_E1x(bp))
10848                         /* block FW from writing to host */
10849                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10850
10851                 /* wait until BRB is empty */
10852                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10853                 while (timer_count) {
10854                         u32 prev_brb = tmp_reg;
10855
10856                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10857                         if (!tmp_reg)
10858                                 break;
10859
10860                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10861
10862                         /* reset timer as long as BRB actually gets emptied */
10863                         if (prev_brb > tmp_reg)
10864                                 timer_count = 1000;
10865                         else
10866                                 timer_count--;
10867
10868                         /* If UNDI resides in memory, manually increment it */
10869                         if (prev_undi)
10870                                 bnx2x_prev_unload_undi_inc(bp, 1);
10871
10872                         udelay(10);
10873                 }
10874
10875                 if (!timer_count)
10876                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10877         }
10878
10879         /* No packets are in the pipeline, path is ready for reset */
10880         bnx2x_reset_common(bp);
10881
10882         if (mac_vals.xmac_addr)
10883                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10884         if (mac_vals.umac_addr[0])
10885                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10886         if (mac_vals.umac_addr[1])
10887                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10888         if (mac_vals.emac_addr)
10889                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10890         if (mac_vals.bmac_addr) {
10891                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10892                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10893         }
10894
10895         rc = bnx2x_prev_mark_path(bp, prev_undi);
10896         if (rc) {
10897                 bnx2x_prev_mcp_done(bp);
10898                 return rc;
10899         }
10900
10901         return bnx2x_prev_mcp_done(bp);
10902 }
10903
10904 static int bnx2x_prev_unload(struct bnx2x *bp)
10905 {
10906         int time_counter = 10;
10907         u32 rc, fw, hw_lock_reg, hw_lock_val;
10908         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10909
10910         /* clear hw from errors which may have resulted from an interrupted
10911          * dmae transaction.
10912          */
10913         bnx2x_clean_pglue_errors(bp);
10914
10915         /* Release previously held locks */
10916         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10917                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10918                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10919
10920         hw_lock_val = REG_RD(bp, hw_lock_reg);
10921         if (hw_lock_val) {
10922                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10923                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10924                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10925                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10926                 }
10927
10928                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10929                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10930         } else
10931                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10932
10933         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10934                 BNX2X_DEV_INFO("Release previously held alr\n");
10935                 bnx2x_release_alr(bp);
10936         }
10937
10938         do {
10939                 int aer = 0;
10940                 /* Lock MCP using an unload request */
10941                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10942                 if (!fw) {
10943                         BNX2X_ERR("MCP response failure, aborting\n");
10944                         rc = -EBUSY;
10945                         break;
10946                 }
10947
10948                 rc = down_interruptible(&bnx2x_prev_sem);
10949                 if (rc) {
10950                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10951                                   rc);
10952                 } else {
10953                         /* If Path is marked by EEH, ignore unload status */
10954                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10955                                  bnx2x_prev_path_get_entry(bp)->aer);
10956                         up(&bnx2x_prev_sem);
10957                 }
10958
10959                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10960                         rc = bnx2x_prev_unload_common(bp);
10961                         break;
10962                 }
10963
10964                 /* non-common reply from MCP might require looping */
10965                 rc = bnx2x_prev_unload_uncommon(bp);
10966                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10967                         break;
10968
10969                 msleep(20);
10970         } while (--time_counter);
10971
10972         if (!time_counter || rc) {
10973                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10974                 rc = -EPROBE_DEFER;
10975         }
10976
10977         /* Mark function if its port was used to boot from SAN */
10978         if (bnx2x_port_after_undi(bp))
10979                 bp->link_params.feature_config_flags |=
10980                         FEATURE_CONFIG_BOOT_FROM_SAN;
10981
10982         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10983
10984         return rc;
10985 }
10986
10987 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10988 {
10989         u32 val, val2, val3, val4, id, boot_mode;
10990         u16 pmc;
10991
10992         /* Get the chip revision id and number. */
10993         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10994         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10995         id = ((val & 0xffff) << 16);
10996         val = REG_RD(bp, MISC_REG_CHIP_REV);
10997         id |= ((val & 0xf) << 12);
10998
10999         /* Metal is read from PCI regs, but we can't access >=0x400 from
11000          * the configuration space (so we need to reg_rd)
11001          */
11002         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
11003         id |= (((val >> 24) & 0xf) << 4);
11004         val = REG_RD(bp, MISC_REG_BOND_ID);
11005         id |= (val & 0xf);
11006         bp->common.chip_id = id;
11007
11008         /* force 57811 according to MISC register */
11009         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
11010                 if (CHIP_IS_57810(bp))
11011                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
11012                                 (bp->common.chip_id & 0x0000FFFF);
11013                 else if (CHIP_IS_57810_MF(bp))
11014                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
11015                                 (bp->common.chip_id & 0x0000FFFF);
11016                 bp->common.chip_id |= 0x1;
11017         }
11018
11019         /* Set doorbell size */
11020         bp->db_size = (1 << BNX2X_DB_SHIFT);
11021
11022         if (!CHIP_IS_E1x(bp)) {
11023                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
11024                 if ((val & 1) == 0)
11025                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
11026                 else
11027                         val = (val >> 1) & 1;
11028                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
11029                                                        "2_PORT_MODE");
11030                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
11031                                                  CHIP_2_PORT_MODE;
11032
11033                 if (CHIP_MODE_IS_4_PORT(bp))
11034                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
11035                 else
11036                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
11037         } else {
11038                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
11039                 bp->pfid = bp->pf_num;                  /* 0..7 */
11040         }
11041
11042         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
11043
11044         bp->link_params.chip_id = bp->common.chip_id;
11045         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
11046
11047         val = (REG_RD(bp, 0x2874) & 0x55);
11048         if ((bp->common.chip_id & 0x1) ||
11049             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
11050                 bp->flags |= ONE_PORT_FLAG;
11051                 BNX2X_DEV_INFO("single port device\n");
11052         }
11053
11054         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
11055         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
11056                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
11057         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11058                        bp->common.flash_size, bp->common.flash_size);
11059
11060         bnx2x_init_shmem(bp);
11061
11062         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11063                                         MISC_REG_GENERIC_CR_1 :
11064                                         MISC_REG_GENERIC_CR_0));
11065
11066         bp->link_params.shmem_base = bp->common.shmem_base;
11067         bp->link_params.shmem2_base = bp->common.shmem2_base;
11068         if (SHMEM2_RD(bp, size) >
11069             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11070                 bp->link_params.lfa_base =
11071                 REG_RD(bp, bp->common.shmem2_base +
11072                        (u32)offsetof(struct shmem2_region,
11073                                      lfa_host_addr[BP_PORT(bp)]));
11074         else
11075                 bp->link_params.lfa_base = 0;
11076         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
11077                        bp->common.shmem_base, bp->common.shmem2_base);
11078
11079         if (!bp->common.shmem_base) {
11080                 BNX2X_DEV_INFO("MCP not active\n");
11081                 bp->flags |= NO_MCP_FLAG;
11082                 return;
11083         }
11084
11085         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
11086         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
11087
11088         bp->link_params.hw_led_mode = ((bp->common.hw_config &
11089                                         SHARED_HW_CFG_LED_MODE_MASK) >>
11090                                        SHARED_HW_CFG_LED_MODE_SHIFT);
11091
11092         bp->link_params.feature_config_flags = 0;
11093         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11094         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11095                 bp->link_params.feature_config_flags |=
11096                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11097         else
11098                 bp->link_params.feature_config_flags &=
11099                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11100
11101         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11102         bp->common.bc_ver = val;
11103         BNX2X_DEV_INFO("bc_ver %X\n", val);
11104         if (val < BNX2X_BC_VER) {
11105                 /* for now only warn
11106                  * later we might need to enforce this */
11107                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11108                           BNX2X_BC_VER, val);
11109         }
11110         bp->link_params.feature_config_flags |=
11111                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11112                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11113
11114         bp->link_params.feature_config_flags |=
11115                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11116                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11117         bp->link_params.feature_config_flags |=
11118                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11119                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11120         bp->link_params.feature_config_flags |=
11121                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11122                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11123
11124         bp->link_params.feature_config_flags |=
11125                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11126                 FEATURE_CONFIG_MT_SUPPORT : 0;
11127
11128         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11129                         BC_SUPPORTS_PFC_STATS : 0;
11130
11131         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11132                         BC_SUPPORTS_FCOE_FEATURES : 0;
11133
11134         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11135                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11136
11137         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11138                         BC_SUPPORTS_RMMOD_CMD : 0;
11139
11140         boot_mode = SHMEM_RD(bp,
11141                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11142                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11143         switch (boot_mode) {
11144         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11145                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11146                 break;
11147         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11148                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11149                 break;
11150         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11151                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11152                 break;
11153         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11154                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11155                 break;
11156         }
11157
11158         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11159         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11160
11161         BNX2X_DEV_INFO("%sWoL capable\n",
11162                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
11163
11164         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11165         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11166         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11167         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11168
11169         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11170                  val, val2, val3, val4);
11171 }
11172
11173 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11174 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11175
11176 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11177 {
11178         int pfid = BP_FUNC(bp);
11179         int igu_sb_id;
11180         u32 val;
11181         u8 fid, igu_sb_cnt = 0;
11182
11183         bp->igu_base_sb = 0xff;
11184         if (CHIP_INT_MODE_IS_BC(bp)) {
11185                 int vn = BP_VN(bp);
11186                 igu_sb_cnt = bp->igu_sb_cnt;
11187                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11188                         FP_SB_MAX_E1x;
11189
11190                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
11191                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11192
11193                 return 0;
11194         }
11195
11196         /* IGU in normal mode - read CAM */
11197         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11198              igu_sb_id++) {
11199                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11200                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11201                         continue;
11202                 fid = IGU_FID(val);
11203                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11204                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11205                                 continue;
11206                         if (IGU_VEC(val) == 0)
11207                                 /* default status block */
11208                                 bp->igu_dsb_id = igu_sb_id;
11209                         else {
11210                                 if (bp->igu_base_sb == 0xff)
11211                                         bp->igu_base_sb = igu_sb_id;
11212                                 igu_sb_cnt++;
11213                         }
11214                 }
11215         }
11216
11217 #ifdef CONFIG_PCI_MSI
11218         /* Due to new PF resource allocation by MFW T7.4 and above, it's
11219          * optional that number of CAM entries will not be equal to the value
11220          * advertised in PCI.
11221          * Driver should use the minimal value of both as the actual status
11222          * block count
11223          */
11224         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11225 #endif
11226
11227         if (igu_sb_cnt == 0) {
11228                 BNX2X_ERR("CAM configuration error\n");
11229                 return -EINVAL;
11230         }
11231
11232         return 0;
11233 }
11234
11235 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11236 {
11237         int cfg_size = 0, idx, port = BP_PORT(bp);
11238
11239         /* Aggregation of supported attributes of all external phys */
11240         bp->port.supported[0] = 0;
11241         bp->port.supported[1] = 0;
11242         switch (bp->link_params.num_phys) {
11243         case 1:
11244                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11245                 cfg_size = 1;
11246                 break;
11247         case 2:
11248                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11249                 cfg_size = 1;
11250                 break;
11251         case 3:
11252                 if (bp->link_params.multi_phy_config &
11253                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11254                         bp->port.supported[1] =
11255                                 bp->link_params.phy[EXT_PHY1].supported;
11256                         bp->port.supported[0] =
11257                                 bp->link_params.phy[EXT_PHY2].supported;
11258                 } else {
11259                         bp->port.supported[0] =
11260                                 bp->link_params.phy[EXT_PHY1].supported;
11261                         bp->port.supported[1] =
11262                                 bp->link_params.phy[EXT_PHY2].supported;
11263                 }
11264                 cfg_size = 2;
11265                 break;
11266         }
11267
11268         if (!(bp->port.supported[0] || bp->port.supported[1])) {
11269                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11270                            SHMEM_RD(bp,
11271                            dev_info.port_hw_config[port].external_phy_config),
11272                            SHMEM_RD(bp,
11273                            dev_info.port_hw_config[port].external_phy_config2));
11274                 return;
11275         }
11276
11277         if (CHIP_IS_E3(bp))
11278                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11279         else {
11280                 switch (switch_cfg) {
11281                 case SWITCH_CFG_1G:
11282                         bp->port.phy_addr = REG_RD(
11283                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11284                         break;
11285                 case SWITCH_CFG_10G:
11286                         bp->port.phy_addr = REG_RD(
11287                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11288                         break;
11289                 default:
11290                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11291                                   bp->port.link_config[0]);
11292                         return;
11293                 }
11294         }
11295         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11296         /* mask what we support according to speed_cap_mask per configuration */
11297         for (idx = 0; idx < cfg_size; idx++) {
11298                 if (!(bp->link_params.speed_cap_mask[idx] &
11299                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11300                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11301
11302                 if (!(bp->link_params.speed_cap_mask[idx] &
11303                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11304                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11305
11306                 if (!(bp->link_params.speed_cap_mask[idx] &
11307                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11308                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11309
11310                 if (!(bp->link_params.speed_cap_mask[idx] &
11311                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11312                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11313
11314                 if (!(bp->link_params.speed_cap_mask[idx] &
11315                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11316                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11317                                                      SUPPORTED_1000baseT_Full);
11318
11319                 if (!(bp->link_params.speed_cap_mask[idx] &
11320                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11321                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11322
11323                 if (!(bp->link_params.speed_cap_mask[idx] &
11324                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11325                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11326
11327                 if (!(bp->link_params.speed_cap_mask[idx] &
11328                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11329                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11330         }
11331
11332         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11333                        bp->port.supported[1]);
11334 }
11335
11336 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11337 {
11338         u32 link_config, idx, cfg_size = 0;
11339         bp->port.advertising[0] = 0;
11340         bp->port.advertising[1] = 0;
11341         switch (bp->link_params.num_phys) {
11342         case 1:
11343         case 2:
11344                 cfg_size = 1;
11345                 break;
11346         case 3:
11347                 cfg_size = 2;
11348                 break;
11349         }
11350         for (idx = 0; idx < cfg_size; idx++) {
11351                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11352                 link_config = bp->port.link_config[idx];
11353                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11354                 case PORT_FEATURE_LINK_SPEED_AUTO:
11355                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11356                                 bp->link_params.req_line_speed[idx] =
11357                                         SPEED_AUTO_NEG;
11358                                 bp->port.advertising[idx] |=
11359                                         bp->port.supported[idx];
11360                                 if (bp->link_params.phy[EXT_PHY1].type ==
11361                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11362                                         bp->port.advertising[idx] |=
11363                                         (SUPPORTED_100baseT_Half |
11364                                          SUPPORTED_100baseT_Full);
11365                         } else {
11366                                 /* force 10G, no AN */
11367                                 bp->link_params.req_line_speed[idx] =
11368                                         SPEED_10000;
11369                                 bp->port.advertising[idx] |=
11370                                         (ADVERTISED_10000baseT_Full |
11371                                          ADVERTISED_FIBRE);
11372                                 continue;
11373                         }
11374                         break;
11375
11376                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11377                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11378                                 bp->link_params.req_line_speed[idx] =
11379                                         SPEED_10;
11380                                 bp->port.advertising[idx] |=
11381                                         (ADVERTISED_10baseT_Full |
11382                                          ADVERTISED_TP);
11383                         } else {
11384                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11385                                             link_config,
11386                                     bp->link_params.speed_cap_mask[idx]);
11387                                 return;
11388                         }
11389                         break;
11390
11391                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11392                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11393                                 bp->link_params.req_line_speed[idx] =
11394                                         SPEED_10;
11395                                 bp->link_params.req_duplex[idx] =
11396                                         DUPLEX_HALF;
11397                                 bp->port.advertising[idx] |=
11398                                         (ADVERTISED_10baseT_Half |
11399                                          ADVERTISED_TP);
11400                         } else {
11401                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11402                                             link_config,
11403                                           bp->link_params.speed_cap_mask[idx]);
11404                                 return;
11405                         }
11406                         break;
11407
11408                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11409                         if (bp->port.supported[idx] &
11410                             SUPPORTED_100baseT_Full) {
11411                                 bp->link_params.req_line_speed[idx] =
11412                                         SPEED_100;
11413                                 bp->port.advertising[idx] |=
11414                                         (ADVERTISED_100baseT_Full |
11415                                          ADVERTISED_TP);
11416                         } else {
11417                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11418                                             link_config,
11419                                           bp->link_params.speed_cap_mask[idx]);
11420                                 return;
11421                         }
11422                         break;
11423
11424                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11425                         if (bp->port.supported[idx] &
11426                             SUPPORTED_100baseT_Half) {
11427                                 bp->link_params.req_line_speed[idx] =
11428                                                                 SPEED_100;
11429                                 bp->link_params.req_duplex[idx] =
11430                                                                 DUPLEX_HALF;
11431                                 bp->port.advertising[idx] |=
11432                                         (ADVERTISED_100baseT_Half |
11433                                          ADVERTISED_TP);
11434                         } else {
11435                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11436                                     link_config,
11437                                     bp->link_params.speed_cap_mask[idx]);
11438                                 return;
11439                         }
11440                         break;
11441
11442                 case PORT_FEATURE_LINK_SPEED_1G:
11443                         if (bp->port.supported[idx] &
11444                             SUPPORTED_1000baseT_Full) {
11445                                 bp->link_params.req_line_speed[idx] =
11446                                         SPEED_1000;
11447                                 bp->port.advertising[idx] |=
11448                                         (ADVERTISED_1000baseT_Full |
11449                                          ADVERTISED_TP);
11450                         } else if (bp->port.supported[idx] &
11451                                    SUPPORTED_1000baseKX_Full) {
11452                                 bp->link_params.req_line_speed[idx] =
11453                                         SPEED_1000;
11454                                 bp->port.advertising[idx] |=
11455                                         ADVERTISED_1000baseKX_Full;
11456                         } else {
11457                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11458                                     link_config,
11459                                     bp->link_params.speed_cap_mask[idx]);
11460                                 return;
11461                         }
11462                         break;
11463
11464                 case PORT_FEATURE_LINK_SPEED_2_5G:
11465                         if (bp->port.supported[idx] &
11466                             SUPPORTED_2500baseX_Full) {
11467                                 bp->link_params.req_line_speed[idx] =
11468                                         SPEED_2500;
11469                                 bp->port.advertising[idx] |=
11470                                         (ADVERTISED_2500baseX_Full |
11471                                                 ADVERTISED_TP);
11472                         } else {
11473                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11474                                     link_config,
11475                                     bp->link_params.speed_cap_mask[idx]);
11476                                 return;
11477                         }
11478                         break;
11479
11480                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11481                         if (bp->port.supported[idx] &
11482                             SUPPORTED_10000baseT_Full) {
11483                                 bp->link_params.req_line_speed[idx] =
11484                                         SPEED_10000;
11485                                 bp->port.advertising[idx] |=
11486                                         (ADVERTISED_10000baseT_Full |
11487                                                 ADVERTISED_FIBRE);
11488                         } else if (bp->port.supported[idx] &
11489                                    SUPPORTED_10000baseKR_Full) {
11490                                 bp->link_params.req_line_speed[idx] =
11491                                         SPEED_10000;
11492                                 bp->port.advertising[idx] |=
11493                                         (ADVERTISED_10000baseKR_Full |
11494                                                 ADVERTISED_FIBRE);
11495                         } else {
11496                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11497                                     link_config,
11498                                     bp->link_params.speed_cap_mask[idx]);
11499                                 return;
11500                         }
11501                         break;
11502                 case PORT_FEATURE_LINK_SPEED_20G:
11503                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11504
11505                         break;
11506                 default:
11507                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11508                                   link_config);
11509                                 bp->link_params.req_line_speed[idx] =
11510                                                         SPEED_AUTO_NEG;
11511                                 bp->port.advertising[idx] =
11512                                                 bp->port.supported[idx];
11513                         break;
11514                 }
11515
11516                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11517                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11518                 if (bp->link_params.req_flow_ctrl[idx] ==
11519                     BNX2X_FLOW_CTRL_AUTO) {
11520                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11521                                 bp->link_params.req_flow_ctrl[idx] =
11522                                                         BNX2X_FLOW_CTRL_NONE;
11523                         else
11524                                 bnx2x_set_requested_fc(bp);
11525                 }
11526
11527                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11528                                bp->link_params.req_line_speed[idx],
11529                                bp->link_params.req_duplex[idx],
11530                                bp->link_params.req_flow_ctrl[idx],
11531                                bp->port.advertising[idx]);
11532         }
11533 }
11534
11535 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11536 {
11537         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11538         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11539         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11540         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11541 }
11542
11543 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11544 {
11545         int port = BP_PORT(bp);
11546         u32 config;
11547         u32 ext_phy_type, ext_phy_config, eee_mode;
11548
11549         bp->link_params.bp = bp;
11550         bp->link_params.port = port;
11551
11552         bp->link_params.lane_config =
11553                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11554
11555         bp->link_params.speed_cap_mask[0] =
11556                 SHMEM_RD(bp,
11557                          dev_info.port_hw_config[port].speed_capability_mask) &
11558                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11559         bp->link_params.speed_cap_mask[1] =
11560                 SHMEM_RD(bp,
11561                          dev_info.port_hw_config[port].speed_capability_mask2) &
11562                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11563         bp->port.link_config[0] =
11564                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11565
11566         bp->port.link_config[1] =
11567                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11568
11569         bp->link_params.multi_phy_config =
11570                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11571         /* If the device is capable of WoL, set the default state according
11572          * to the HW
11573          */
11574         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11575         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11576                    (config & PORT_FEATURE_WOL_ENABLED));
11577
11578         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11579             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11580                 bp->flags |= NO_ISCSI_FLAG;
11581         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11582             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11583                 bp->flags |= NO_FCOE_FLAG;
11584
11585         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11586                        bp->link_params.lane_config,
11587                        bp->link_params.speed_cap_mask[0],
11588                        bp->port.link_config[0]);
11589
11590         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11591                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11592         bnx2x_phy_probe(&bp->link_params);
11593         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11594
11595         bnx2x_link_settings_requested(bp);
11596
11597         /*
11598          * If connected directly, work with the internal PHY, otherwise, work
11599          * with the external PHY
11600          */
11601         ext_phy_config =
11602                 SHMEM_RD(bp,
11603                          dev_info.port_hw_config[port].external_phy_config);
11604         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11605         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11606                 bp->mdio.prtad = bp->port.phy_addr;
11607
11608         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11609                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11610                 bp->mdio.prtad =
11611                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11612
11613         /* Configure link feature according to nvram value */
11614         eee_mode = (((SHMEM_RD(bp, dev_info.
11615                       port_feature_config[port].eee_power_mode)) &
11616                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11617                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11618         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11619                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11620                                            EEE_MODE_ENABLE_LPI |
11621                                            EEE_MODE_OUTPUT_TIME;
11622         } else {
11623                 bp->link_params.eee_mode = 0;
11624         }
11625 }
11626
11627 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11628 {
11629         u32 no_flags = NO_ISCSI_FLAG;
11630         int port = BP_PORT(bp);
11631         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11632                                 drv_lic_key[port].max_iscsi_conn);
11633
11634         if (!CNIC_SUPPORT(bp)) {
11635                 bp->flags |= no_flags;
11636                 return;
11637         }
11638
11639         /* Get the number of maximum allowed iSCSI connections */
11640         bp->cnic_eth_dev.max_iscsi_conn =
11641                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11642                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11643
11644         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11645                        bp->cnic_eth_dev.max_iscsi_conn);
11646
11647         /*
11648          * If maximum allowed number of connections is zero -
11649          * disable the feature.
11650          */
11651         if (!bp->cnic_eth_dev.max_iscsi_conn)
11652                 bp->flags |= no_flags;
11653 }
11654
11655 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11656 {
11657         /* Port info */
11658         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11659                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11660         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11661                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11662
11663         /* Node info */
11664         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11665                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11666         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11667                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11668 }
11669
11670 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11671 {
11672         u8 count = 0;
11673
11674         if (IS_MF(bp)) {
11675                 u8 fid;
11676
11677                 /* iterate over absolute function ids for this path: */
11678                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11679                         if (IS_MF_SD(bp)) {
11680                                 u32 cfg = MF_CFG_RD(bp,
11681                                                     func_mf_config[fid].config);
11682
11683                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11684                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11685                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11686                                         count++;
11687                         } else {
11688                                 u32 cfg = MF_CFG_RD(bp,
11689                                                     func_ext_config[fid].
11690                                                                       func_cfg);
11691
11692                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11693                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11694                                         count++;
11695                         }
11696                 }
11697         } else { /* SF */
11698                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11699
11700                 for (port = 0; port < port_cnt; port++) {
11701                         u32 lic = SHMEM_RD(bp,
11702                                            drv_lic_key[port].max_fcoe_conn) ^
11703                                   FW_ENCODE_32BIT_PATTERN;
11704                         if (lic)
11705                                 count++;
11706                 }
11707         }
11708
11709         return count;
11710 }
11711
11712 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11713 {
11714         int port = BP_PORT(bp);
11715         int func = BP_ABS_FUNC(bp);
11716         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11717                                 drv_lic_key[port].max_fcoe_conn);
11718         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11719
11720         if (!CNIC_SUPPORT(bp)) {
11721                 bp->flags |= NO_FCOE_FLAG;
11722                 return;
11723         }
11724
11725         /* Get the number of maximum allowed FCoE connections */
11726         bp->cnic_eth_dev.max_fcoe_conn =
11727                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11728                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11729
11730         /* Calculate the number of maximum allowed FCoE tasks */
11731         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11732
11733         /* check if FCoE resources must be shared between different functions */
11734         if (num_fcoe_func)
11735                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11736
11737         /* Read the WWN: */
11738         if (!IS_MF(bp)) {
11739                 /* Port info */
11740                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11741                         SHMEM_RD(bp,
11742                                  dev_info.port_hw_config[port].
11743                                  fcoe_wwn_port_name_upper);
11744                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11745                         SHMEM_RD(bp,
11746                                  dev_info.port_hw_config[port].
11747                                  fcoe_wwn_port_name_lower);
11748
11749                 /* Node info */
11750                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11751                         SHMEM_RD(bp,
11752                                  dev_info.port_hw_config[port].
11753                                  fcoe_wwn_node_name_upper);
11754                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11755                         SHMEM_RD(bp,
11756                                  dev_info.port_hw_config[port].
11757                                  fcoe_wwn_node_name_lower);
11758         } else if (!IS_MF_SD(bp)) {
11759                 /* Read the WWN info only if the FCoE feature is enabled for
11760                  * this function.
11761                  */
11762                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11763                         bnx2x_get_ext_wwn_info(bp, func);
11764         } else {
11765                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11766                         bnx2x_get_ext_wwn_info(bp, func);
11767         }
11768
11769         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11770
11771         /*
11772          * If maximum allowed number of connections is zero -
11773          * disable the feature.
11774          */
11775         if (!bp->cnic_eth_dev.max_fcoe_conn) {
11776                 bp->flags |= NO_FCOE_FLAG;
11777                 eth_zero_addr(bp->fip_mac);
11778         }
11779 }
11780
11781 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11782 {
11783         /*
11784          * iSCSI may be dynamically disabled but reading
11785          * info here we will decrease memory usage by driver
11786          * if the feature is disabled for good
11787          */
11788         bnx2x_get_iscsi_info(bp);
11789         bnx2x_get_fcoe_info(bp);
11790 }
11791
11792 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11793 {
11794         u32 val, val2;
11795         int func = BP_ABS_FUNC(bp);
11796         int port = BP_PORT(bp);
11797         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11798         u8 *fip_mac = bp->fip_mac;
11799
11800         if (IS_MF(bp)) {
11801                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11802                  * FCoE MAC then the appropriate feature should be disabled.
11803                  * In non SD mode features configuration comes from struct
11804                  * func_ext_config.
11805                  */
11806                 if (!IS_MF_SD(bp)) {
11807                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11808                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11809                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11810                                                  iscsi_mac_addr_upper);
11811                                 val = MF_CFG_RD(bp, func_ext_config[func].
11812                                                 iscsi_mac_addr_lower);
11813                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11814                                 BNX2X_DEV_INFO
11815                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11816                         } else {
11817                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11818                         }
11819
11820                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11821                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11822                                                  fcoe_mac_addr_upper);
11823                                 val = MF_CFG_RD(bp, func_ext_config[func].
11824                                                 fcoe_mac_addr_lower);
11825                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11826                                 BNX2X_DEV_INFO
11827                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11828                         } else {
11829                                 bp->flags |= NO_FCOE_FLAG;
11830                         }
11831
11832                         bp->mf_ext_config = cfg;
11833
11834                 } else { /* SD MODE */
11835                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11836                                 /* use primary mac as iscsi mac */
11837                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11838
11839                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11840                                 BNX2X_DEV_INFO
11841                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11842                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11843                                 /* use primary mac as fip mac */
11844                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11845                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11846                                 BNX2X_DEV_INFO
11847                                         ("Read FIP MAC: %pM\n", fip_mac);
11848                         }
11849                 }
11850
11851                 /* If this is a storage-only interface, use SAN mac as
11852                  * primary MAC. Notice that for SD this is already the case,
11853                  * as the SAN mac was copied from the primary MAC.
11854                  */
11855                 if (IS_MF_FCOE_AFEX(bp))
11856                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11857         } else {
11858                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11859                                 iscsi_mac_upper);
11860                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11861                                iscsi_mac_lower);
11862                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11863
11864                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11865                                 fcoe_fip_mac_upper);
11866                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11867                                fcoe_fip_mac_lower);
11868                 bnx2x_set_mac_buf(fip_mac, val, val2);
11869         }
11870
11871         /* Disable iSCSI OOO if MAC configuration is invalid. */
11872         if (!is_valid_ether_addr(iscsi_mac)) {
11873                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11874                 eth_zero_addr(iscsi_mac);
11875         }
11876
11877         /* Disable FCoE if MAC configuration is invalid. */
11878         if (!is_valid_ether_addr(fip_mac)) {
11879                 bp->flags |= NO_FCOE_FLAG;
11880                 eth_zero_addr(bp->fip_mac);
11881         }
11882 }
11883
11884 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11885 {
11886         u32 val, val2;
11887         int func = BP_ABS_FUNC(bp);
11888         int port = BP_PORT(bp);
11889
11890         /* Zero primary MAC configuration */
11891         eth_zero_addr(bp->dev->dev_addr);
11892
11893         if (BP_NOMCP(bp)) {
11894                 BNX2X_ERROR("warning: random MAC workaround active\n");
11895                 eth_hw_addr_random(bp->dev);
11896         } else if (IS_MF(bp)) {
11897                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11898                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11899                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11900                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11901                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11902
11903                 if (CNIC_SUPPORT(bp))
11904                         bnx2x_get_cnic_mac_hwinfo(bp);
11905         } else {
11906                 /* in SF read MACs from port configuration */
11907                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11908                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11909                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11910
11911                 if (CNIC_SUPPORT(bp))
11912                         bnx2x_get_cnic_mac_hwinfo(bp);
11913         }
11914
11915         if (!BP_NOMCP(bp)) {
11916                 /* Read physical port identifier from shmem */
11917                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11918                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11919                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11920                 bp->flags |= HAS_PHYS_PORT_ID;
11921         }
11922
11923         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11924
11925         if (!is_valid_ether_addr(bp->dev->dev_addr))
11926                 dev_err(&bp->pdev->dev,
11927                         "bad Ethernet MAC address configuration: %pM\n"
11928                         "change it manually before bringing up the appropriate network interface\n",
11929                         bp->dev->dev_addr);
11930 }
11931
11932 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11933 {
11934         int tmp;
11935         u32 cfg;
11936
11937         if (IS_VF(bp))
11938                 return false;
11939
11940         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11941                 /* Take function: tmp = func */
11942                 tmp = BP_ABS_FUNC(bp);
11943                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11944                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11945         } else {
11946                 /* Take port: tmp = port */
11947                 tmp = BP_PORT(bp);
11948                 cfg = SHMEM_RD(bp,
11949                                dev_info.port_hw_config[tmp].generic_features);
11950                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11951         }
11952         return cfg;
11953 }
11954
11955 static void validate_set_si_mode(struct bnx2x *bp)
11956 {
11957         u8 func = BP_ABS_FUNC(bp);
11958         u32 val;
11959
11960         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11961
11962         /* check for legal mac (upper bytes) */
11963         if (val != 0xffff) {
11964                 bp->mf_mode = MULTI_FUNCTION_SI;
11965                 bp->mf_config[BP_VN(bp)] =
11966                         MF_CFG_RD(bp, func_mf_config[func].config);
11967         } else
11968                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11969 }
11970
11971 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11972 {
11973         int /*abs*/func = BP_ABS_FUNC(bp);
11974         int vn;
11975         u32 val = 0, val2 = 0;
11976         int rc = 0;
11977
11978         /* Validate that chip access is feasible */
11979         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11980                 dev_err(&bp->pdev->dev,
11981                         "Chip read returns all Fs. Preventing probe from continuing\n");
11982                 return -EINVAL;
11983         }
11984
11985         bnx2x_get_common_hwinfo(bp);
11986
11987         /*
11988          * initialize IGU parameters
11989          */
11990         if (CHIP_IS_E1x(bp)) {
11991                 bp->common.int_block = INT_BLOCK_HC;
11992
11993                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11994                 bp->igu_base_sb = 0;
11995         } else {
11996                 bp->common.int_block = INT_BLOCK_IGU;
11997
11998                 /* do not allow device reset during IGU info processing */
11999                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12000
12001                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
12002
12003                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12004                         int tout = 5000;
12005
12006                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
12007
12008                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
12009                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
12010                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
12011
12012                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12013                                 tout--;
12014                                 usleep_range(1000, 2000);
12015                         }
12016
12017                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12018                                 dev_err(&bp->pdev->dev,
12019                                         "FORCING Normal Mode failed!!!\n");
12020                                 bnx2x_release_hw_lock(bp,
12021                                                       HW_LOCK_RESOURCE_RESET);
12022                                 return -EPERM;
12023                         }
12024                 }
12025
12026                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12027                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
12028                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
12029                 } else
12030                         BNX2X_DEV_INFO("IGU Normal Mode\n");
12031
12032                 rc = bnx2x_get_igu_cam_info(bp);
12033                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12034                 if (rc)
12035                         return rc;
12036         }
12037
12038         /*
12039          * set base FW non-default (fast path) status block id, this value is
12040          * used to initialize the fw_sb_id saved on the fp/queue structure to
12041          * determine the id used by the FW.
12042          */
12043         if (CHIP_IS_E1x(bp))
12044                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
12045         else /*
12046               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
12047               * the same queue are indicated on the same IGU SB). So we prefer
12048               * FW and IGU SBs to be the same value.
12049               */
12050                 bp->base_fw_ndsb = bp->igu_base_sb;
12051
12052         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
12053                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
12054                        bp->igu_sb_cnt, bp->base_fw_ndsb);
12055
12056         /*
12057          * Initialize MF configuration
12058          */
12059         bp->mf_ov = 0;
12060         bp->mf_mode = 0;
12061         bp->mf_sub_mode = 0;
12062         vn = BP_VN(bp);
12063
12064         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
12065                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12066                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
12067                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12068
12069                 if (SHMEM2_HAS(bp, mf_cfg_addr))
12070                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12071                 else
12072                         bp->common.mf_cfg_base = bp->common.shmem_base +
12073                                 offsetof(struct shmem_region, func_mb) +
12074                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
12075                 /*
12076                  * get mf configuration:
12077                  * 1. Existence of MF configuration
12078                  * 2. MAC address must be legal (check only upper bytes)
12079                  *    for  Switch-Independent mode;
12080                  *    OVLAN must be legal for Switch-Dependent mode
12081                  * 3. SF_MODE configures specific MF mode
12082                  */
12083                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12084                         /* get mf configuration */
12085                         val = SHMEM_RD(bp,
12086                                        dev_info.shared_feature_config.config);
12087                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12088
12089                         switch (val) {
12090                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
12091                                 validate_set_si_mode(bp);
12092                                 break;
12093                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12094                                 if ((!CHIP_IS_E1x(bp)) &&
12095                                     (MF_CFG_RD(bp, func_mf_config[func].
12096                                                mac_upper) != 0xffff) &&
12097                                     (SHMEM2_HAS(bp,
12098                                                 afex_driver_support))) {
12099                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
12100                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12101                                                 func_mf_config[func].config);
12102                                 } else {
12103                                         BNX2X_DEV_INFO("can not configure afex mode\n");
12104                                 }
12105                                 break;
12106                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12107                                 /* get OV configuration */
12108                                 val = MF_CFG_RD(bp,
12109                                         func_mf_config[FUNC_0].e1hov_tag);
12110                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12111
12112                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12113                                         bp->mf_mode = MULTI_FUNCTION_SD;
12114                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12115                                                 func_mf_config[func].config);
12116                                 } else
12117                                         BNX2X_DEV_INFO("illegal OV for SD\n");
12118                                 break;
12119                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12120                                 bp->mf_mode = MULTI_FUNCTION_SD;
12121                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
12122                                 bp->mf_config[vn] =
12123                                         MF_CFG_RD(bp,
12124                                                   func_mf_config[func].config);
12125
12126                                 if (SHMEM2_HAS(bp, mtu_size)) {
12127                                         int mtu_idx = BP_FW_MB_IDX(bp);
12128                                         u16 mtu_size;
12129                                         u32 mtu;
12130
12131                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12132                                         mtu_size = (u16)mtu;
12133                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12134                                            mtu_size, mtu);
12135
12136                                         /* if valid: update device mtu */
12137                                         if ((mtu_size >= ETH_MIN_PACKET_SIZE) &&
12138                                             (mtu_size <=
12139                                              ETH_MAX_JUMBO_PACKET_SIZE))
12140                                                 bp->dev->mtu = mtu_size;
12141                                 }
12142                                 break;
12143                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12144                                 bp->mf_mode = MULTI_FUNCTION_SD;
12145                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12146                                 bp->mf_config[vn] =
12147                                         MF_CFG_RD(bp,
12148                                                   func_mf_config[func].config);
12149                                 break;
12150                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12151                                 bp->mf_config[vn] = 0;
12152                                 break;
12153                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12154                                 val2 = SHMEM_RD(bp,
12155                                         dev_info.shared_hw_config.config_3);
12156                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12157                                 switch (val2) {
12158                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12159                                         validate_set_si_mode(bp);
12160                                         bp->mf_sub_mode =
12161                                                         SUB_MF_MODE_NPAR1_DOT_5;
12162                                         break;
12163                                 default:
12164                                         /* Unknown configuration */
12165                                         bp->mf_config[vn] = 0;
12166                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12167                                                        val);
12168                                 }
12169                                 break;
12170                         default:
12171                                 /* Unknown configuration: reset mf_config */
12172                                 bp->mf_config[vn] = 0;
12173                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12174                         }
12175                 }
12176
12177                 BNX2X_DEV_INFO("%s function mode\n",
12178                                IS_MF(bp) ? "multi" : "single");
12179
12180                 switch (bp->mf_mode) {
12181                 case MULTI_FUNCTION_SD:
12182                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12183                               FUNC_MF_CFG_E1HOV_TAG_MASK;
12184                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12185                                 bp->mf_ov = val;
12186                                 bp->path_has_ovlan = true;
12187
12188                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12189                                                func, bp->mf_ov, bp->mf_ov);
12190                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12191                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12192                                 dev_err(&bp->pdev->dev,
12193                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12194                                         func);
12195                                 bp->path_has_ovlan = true;
12196                         } else {
12197                                 dev_err(&bp->pdev->dev,
12198                                         "No valid MF OV for func %d, aborting\n",
12199                                         func);
12200                                 return -EPERM;
12201                         }
12202                         break;
12203                 case MULTI_FUNCTION_AFEX:
12204                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12205                         break;
12206                 case MULTI_FUNCTION_SI:
12207                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12208                                        func);
12209                         break;
12210                 default:
12211                         if (vn) {
12212                                 dev_err(&bp->pdev->dev,
12213                                         "VN %d is in a single function mode, aborting\n",
12214                                         vn);
12215                                 return -EPERM;
12216                         }
12217                         break;
12218                 }
12219
12220                 /* check if other port on the path needs ovlan:
12221                  * Since MF configuration is shared between ports
12222                  * Possible mixed modes are only
12223                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12224                  */
12225                 if (CHIP_MODE_IS_4_PORT(bp) &&
12226                     !bp->path_has_ovlan &&
12227                     !IS_MF(bp) &&
12228                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12229                         u8 other_port = !BP_PORT(bp);
12230                         u8 other_func = BP_PATH(bp) + 2*other_port;
12231                         val = MF_CFG_RD(bp,
12232                                         func_mf_config[other_func].e1hov_tag);
12233                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12234                                 bp->path_has_ovlan = true;
12235                 }
12236         }
12237
12238         /* adjust igu_sb_cnt to MF for E1H */
12239         if (CHIP_IS_E1H(bp) && IS_MF(bp))
12240                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12241
12242         /* port info */
12243         bnx2x_get_port_hwinfo(bp);
12244
12245         /* Get MAC addresses */
12246         bnx2x_get_mac_hwinfo(bp);
12247
12248         bnx2x_get_cnic_info(bp);
12249
12250         return rc;
12251 }
12252
12253 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12254 {
12255         int cnt, i, block_end, rodi;
12256         char vpd_start[BNX2X_VPD_LEN+1];
12257         char str_id_reg[VENDOR_ID_LEN+1];
12258         char str_id_cap[VENDOR_ID_LEN+1];
12259         char *vpd_data;
12260         char *vpd_extended_data = NULL;
12261         u8 len;
12262
12263         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12264         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12265
12266         if (cnt < BNX2X_VPD_LEN)
12267                 goto out_not_found;
12268
12269         /* VPD RO tag should be first tag after identifier string, hence
12270          * we should be able to find it in first BNX2X_VPD_LEN chars
12271          */
12272         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12273                              PCI_VPD_LRDT_RO_DATA);
12274         if (i < 0)
12275                 goto out_not_found;
12276
12277         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12278                     pci_vpd_lrdt_size(&vpd_start[i]);
12279
12280         i += PCI_VPD_LRDT_TAG_SIZE;
12281
12282         if (block_end > BNX2X_VPD_LEN) {
12283                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12284                 if (vpd_extended_data  == NULL)
12285                         goto out_not_found;
12286
12287                 /* read rest of vpd image into vpd_extended_data */
12288                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12289                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12290                                    block_end - BNX2X_VPD_LEN,
12291                                    vpd_extended_data + BNX2X_VPD_LEN);
12292                 if (cnt < (block_end - BNX2X_VPD_LEN))
12293                         goto out_not_found;
12294                 vpd_data = vpd_extended_data;
12295         } else
12296                 vpd_data = vpd_start;
12297
12298         /* now vpd_data holds full vpd content in both cases */
12299
12300         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12301                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12302         if (rodi < 0)
12303                 goto out_not_found;
12304
12305         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12306
12307         if (len != VENDOR_ID_LEN)
12308                 goto out_not_found;
12309
12310         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12311
12312         /* vendor specific info */
12313         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12314         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12315         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12316             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12317
12318                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12319                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12320                 if (rodi >= 0) {
12321                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12322
12323                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12324
12325                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12326                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12327                                 bp->fw_ver[len] = ' ';
12328                         }
12329                 }
12330                 kfree(vpd_extended_data);
12331                 return;
12332         }
12333 out_not_found:
12334         kfree(vpd_extended_data);
12335         return;
12336 }
12337
12338 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12339 {
12340         u32 flags = 0;
12341
12342         if (CHIP_REV_IS_FPGA(bp))
12343                 SET_FLAGS(flags, MODE_FPGA);
12344         else if (CHIP_REV_IS_EMUL(bp))
12345                 SET_FLAGS(flags, MODE_EMUL);
12346         else
12347                 SET_FLAGS(flags, MODE_ASIC);
12348
12349         if (CHIP_MODE_IS_4_PORT(bp))
12350                 SET_FLAGS(flags, MODE_PORT4);
12351         else
12352                 SET_FLAGS(flags, MODE_PORT2);
12353
12354         if (CHIP_IS_E2(bp))
12355                 SET_FLAGS(flags, MODE_E2);
12356         else if (CHIP_IS_E3(bp)) {
12357                 SET_FLAGS(flags, MODE_E3);
12358                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12359                         SET_FLAGS(flags, MODE_E3_A0);
12360                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12361                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12362         }
12363
12364         if (IS_MF(bp)) {
12365                 SET_FLAGS(flags, MODE_MF);
12366                 switch (bp->mf_mode) {
12367                 case MULTI_FUNCTION_SD:
12368                         SET_FLAGS(flags, MODE_MF_SD);
12369                         break;
12370                 case MULTI_FUNCTION_SI:
12371                         SET_FLAGS(flags, MODE_MF_SI);
12372                         break;
12373                 case MULTI_FUNCTION_AFEX:
12374                         SET_FLAGS(flags, MODE_MF_AFEX);
12375                         break;
12376                 }
12377         } else
12378                 SET_FLAGS(flags, MODE_SF);
12379
12380 #if defined(__LITTLE_ENDIAN)
12381         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12382 #else /*(__BIG_ENDIAN)*/
12383         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12384 #endif
12385         INIT_MODE_FLAGS(bp) = flags;
12386 }
12387
12388 static int bnx2x_init_bp(struct bnx2x *bp)
12389 {
12390         int func;
12391         int rc;
12392
12393         mutex_init(&bp->port.phy_mutex);
12394         mutex_init(&bp->fw_mb_mutex);
12395         mutex_init(&bp->drv_info_mutex);
12396         sema_init(&bp->stats_lock, 1);
12397         bp->drv_info_mng_owner = false;
12398         INIT_LIST_HEAD(&bp->vlan_reg);
12399
12400         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12401         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12402         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12403         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12404         if (IS_PF(bp)) {
12405                 rc = bnx2x_get_hwinfo(bp);
12406                 if (rc)
12407                         return rc;
12408         } else {
12409                 eth_zero_addr(bp->dev->dev_addr);
12410         }
12411
12412         bnx2x_set_modes_bitmap(bp);
12413
12414         rc = bnx2x_alloc_mem_bp(bp);
12415         if (rc)
12416                 return rc;
12417
12418         bnx2x_read_fwinfo(bp);
12419
12420         func = BP_FUNC(bp);
12421
12422         /* need to reset chip if undi was active */
12423         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12424                 /* init fw_seq */
12425                 bp->fw_seq =
12426                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12427                                                         DRV_MSG_SEQ_NUMBER_MASK;
12428                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12429
12430                 rc = bnx2x_prev_unload(bp);
12431                 if (rc) {
12432                         bnx2x_free_mem_bp(bp);
12433                         return rc;
12434                 }
12435         }
12436
12437         if (CHIP_REV_IS_FPGA(bp))
12438                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12439
12440         if (BP_NOMCP(bp) && (func == 0))
12441                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12442
12443         bp->disable_tpa = disable_tpa;
12444         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12445         /* Reduce memory usage in kdump environment by disabling TPA */
12446         bp->disable_tpa |= is_kdump_kernel();
12447
12448         /* Set TPA flags */
12449         if (bp->disable_tpa) {
12450                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12451                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12452         }
12453
12454         if (CHIP_IS_E1(bp))
12455                 bp->dropless_fc = 0;
12456         else
12457                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12458
12459         bp->mrrs = mrrs;
12460
12461         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12462         if (IS_VF(bp))
12463                 bp->rx_ring_size = MAX_RX_AVAIL;
12464
12465         /* make sure that the numbers are in the right granularity */
12466         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12467         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12468
12469         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12470
12471         timer_setup(&bp->timer, bnx2x_timer, 0);
12472         bp->timer.expires = jiffies + bp->current_interval;
12473
12474         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12475             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12476             SHMEM2_HAS(bp, dcbx_en) &&
12477             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12478             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12479             SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
12480                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12481                 bnx2x_dcbx_init_params(bp);
12482         } else {
12483                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12484         }
12485
12486         if (CHIP_IS_E1x(bp))
12487                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12488         else
12489                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12490
12491         /* multiple tx priority */
12492         if (IS_VF(bp))
12493                 bp->max_cos = 1;
12494         else if (CHIP_IS_E1x(bp))
12495                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12496         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12497                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12498         else if (CHIP_IS_E3B0(bp))
12499                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12500         else
12501                 BNX2X_ERR("unknown chip %x revision %x\n",
12502                           CHIP_NUM(bp), CHIP_REV(bp));
12503         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12504
12505         /* We need at least one default status block for slow-path events,
12506          * second status block for the L2 queue, and a third status block for
12507          * CNIC if supported.
12508          */
12509         if (IS_VF(bp))
12510                 bp->min_msix_vec_cnt = 1;
12511         else if (CNIC_SUPPORT(bp))
12512                 bp->min_msix_vec_cnt = 3;
12513         else /* PF w/o cnic */
12514                 bp->min_msix_vec_cnt = 2;
12515         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12516
12517         bp->dump_preset_idx = 1;
12518
12519         return rc;
12520 }
12521
12522 /****************************************************************************
12523 * General service functions
12524 ****************************************************************************/
12525
12526 /*
12527  * net_device service functions
12528  */
12529
12530 /* called with rtnl_lock */
12531 static int bnx2x_open(struct net_device *dev)
12532 {
12533         struct bnx2x *bp = netdev_priv(dev);
12534         int rc;
12535
12536         bp->stats_init = true;
12537
12538         netif_carrier_off(dev);
12539
12540         bnx2x_set_power_state(bp, PCI_D0);
12541
12542         /* If parity had happen during the unload, then attentions
12543          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12544          * want the first function loaded on the current engine to
12545          * complete the recovery.
12546          * Parity recovery is only relevant for PF driver.
12547          */
12548         if (IS_PF(bp)) {
12549                 int other_engine = BP_PATH(bp) ? 0 : 1;
12550                 bool other_load_status, load_status;
12551                 bool global = false;
12552
12553                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12554                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12555                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12556                     bnx2x_chk_parity_attn(bp, &global, true)) {
12557                         do {
12558                                 /* If there are attentions and they are in a
12559                                  * global blocks, set the GLOBAL_RESET bit
12560                                  * regardless whether it will be this function
12561                                  * that will complete the recovery or not.
12562                                  */
12563                                 if (global)
12564                                         bnx2x_set_reset_global(bp);
12565
12566                                 /* Only the first function on the current
12567                                  * engine should try to recover in open. In case
12568                                  * of attentions in global blocks only the first
12569                                  * in the chip should try to recover.
12570                                  */
12571                                 if ((!load_status &&
12572                                      (!global || !other_load_status)) &&
12573                                       bnx2x_trylock_leader_lock(bp) &&
12574                                       !bnx2x_leader_reset(bp)) {
12575                                         netdev_info(bp->dev,
12576                                                     "Recovered in open\n");
12577                                         break;
12578                                 }
12579
12580                                 /* recovery has failed... */
12581                                 bnx2x_set_power_state(bp, PCI_D3hot);
12582                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12583
12584                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12585                                           "If you still see this message after a few retries then power cycle is required.\n");
12586
12587                                 return -EAGAIN;
12588                         } while (0);
12589                 }
12590         }
12591
12592         bp->recovery_state = BNX2X_RECOVERY_DONE;
12593         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12594         if (rc)
12595                 return rc;
12596
12597         if (IS_PF(bp))
12598                 udp_tunnel_get_rx_info(dev);
12599
12600         return 0;
12601 }
12602
12603 /* called with rtnl_lock */
12604 static int bnx2x_close(struct net_device *dev)
12605 {
12606         struct bnx2x *bp = netdev_priv(dev);
12607
12608         /* Unload the driver, release IRQs */
12609         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12610
12611         return 0;
12612 }
12613
12614 struct bnx2x_mcast_list_elem_group
12615 {
12616         struct list_head mcast_group_link;
12617         struct bnx2x_mcast_list_elem mcast_elems[];
12618 };
12619
12620 #define MCAST_ELEMS_PER_PG \
12621         ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12622         sizeof(struct bnx2x_mcast_list_elem))
12623
12624 static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list)
12625 {
12626         struct bnx2x_mcast_list_elem_group *current_mcast_group;
12627
12628         while (!list_empty(mcast_group_list)) {
12629                 current_mcast_group = list_first_entry(mcast_group_list,
12630                                       struct bnx2x_mcast_list_elem_group,
12631                                       mcast_group_link);
12632                 list_del(&current_mcast_group->mcast_group_link);
12633                 free_page((unsigned long)current_mcast_group);
12634         }
12635 }
12636
12637 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12638                                       struct bnx2x_mcast_ramrod_params *p,
12639                                       struct list_head *mcast_group_list)
12640 {
12641         struct bnx2x_mcast_list_elem *mc_mac;
12642         struct netdev_hw_addr *ha;
12643         struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL;
12644         int mc_count = netdev_mc_count(bp->dev);
12645         int offset = 0;
12646
12647         INIT_LIST_HEAD(&p->mcast_list);
12648         netdev_for_each_mc_addr(ha, bp->dev) {
12649                 if (!offset) {
12650                         current_mcast_group =
12651                                 (struct bnx2x_mcast_list_elem_group *)
12652                                 __get_free_page(GFP_ATOMIC);
12653                         if (!current_mcast_group) {
12654                                 bnx2x_free_mcast_macs_list(mcast_group_list);
12655                                 BNX2X_ERR("Failed to allocate mc MAC list\n");
12656                                 return -ENOMEM;
12657                         }
12658                         list_add(&current_mcast_group->mcast_group_link,
12659                                  mcast_group_list);
12660                 }
12661                 mc_mac = &current_mcast_group->mcast_elems[offset];
12662                 mc_mac->mac = bnx2x_mc_addr(ha);
12663                 list_add_tail(&mc_mac->link, &p->mcast_list);
12664                 offset++;
12665                 if (offset == MCAST_ELEMS_PER_PG)
12666                         offset = 0;
12667         }
12668         p->mcast_list_len = mc_count;
12669         return 0;
12670 }
12671
12672 /**
12673  * bnx2x_set_uc_list - configure a new unicast MACs list.
12674  *
12675  * @bp: driver handle
12676  *
12677  * We will use zero (0) as a MAC type for these MACs.
12678  */
12679 static int bnx2x_set_uc_list(struct bnx2x *bp)
12680 {
12681         int rc;
12682         struct net_device *dev = bp->dev;
12683         struct netdev_hw_addr *ha;
12684         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12685         unsigned long ramrod_flags = 0;
12686
12687         /* First schedule a cleanup up of old configuration */
12688         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12689         if (rc < 0) {
12690                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12691                 return rc;
12692         }
12693
12694         netdev_for_each_uc_addr(ha, dev) {
12695                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12696                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12697                 if (rc == -EEXIST) {
12698                         DP(BNX2X_MSG_SP,
12699                            "Failed to schedule ADD operations: %d\n", rc);
12700                         /* do not treat adding same MAC as error */
12701                         rc = 0;
12702
12703                 } else if (rc < 0) {
12704
12705                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12706                                   rc);
12707                         return rc;
12708                 }
12709         }
12710
12711         /* Execute the pending commands */
12712         __set_bit(RAMROD_CONT, &ramrod_flags);
12713         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12714                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12715 }
12716
12717 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
12718 {
12719         LIST_HEAD(mcast_group_list);
12720         struct net_device *dev = bp->dev;
12721         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12722         int rc = 0;
12723
12724         rparam.mcast_obj = &bp->mcast_obj;
12725
12726         /* first, clear all configured multicast MACs */
12727         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12728         if (rc < 0) {
12729                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12730                 return rc;
12731         }
12732
12733         /* then, configure a new MACs list */
12734         if (netdev_mc_count(dev)) {
12735                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12736                 if (rc)
12737                         return rc;
12738
12739                 /* Now add the new MACs */
12740                 rc = bnx2x_config_mcast(bp, &rparam,
12741                                         BNX2X_MCAST_CMD_ADD);
12742                 if (rc < 0)
12743                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12744                                   rc);
12745
12746                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12747         }
12748
12749         return rc;
12750 }
12751
12752 static int bnx2x_set_mc_list(struct bnx2x *bp)
12753 {
12754         LIST_HEAD(mcast_group_list);
12755         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12756         struct net_device *dev = bp->dev;
12757         int rc = 0;
12758
12759         /* On older adapters, we need to flush and re-add filters */
12760         if (CHIP_IS_E1x(bp))
12761                 return bnx2x_set_mc_list_e1x(bp);
12762
12763         rparam.mcast_obj = &bp->mcast_obj;
12764
12765         if (netdev_mc_count(dev)) {
12766                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12767                 if (rc)
12768                         return rc;
12769
12770                 /* Override the curently configured set of mc filters */
12771                 rc = bnx2x_config_mcast(bp, &rparam,
12772                                         BNX2X_MCAST_CMD_SET);
12773                 if (rc < 0)
12774                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12775                                   rc);
12776
12777                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12778         } else {
12779                 /* If no mc addresses are required, flush the configuration */
12780                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12781                 if (rc < 0)
12782                         BNX2X_ERR("Failed to clear multicast configuration %d\n",
12783                                   rc);
12784         }
12785
12786         return rc;
12787 }
12788
12789 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12790 static void bnx2x_set_rx_mode(struct net_device *dev)
12791 {
12792         struct bnx2x *bp = netdev_priv(dev);
12793
12794         if (bp->state != BNX2X_STATE_OPEN) {
12795                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12796                 return;
12797         } else {
12798                 /* Schedule an SP task to handle rest of change */
12799                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12800                                        NETIF_MSG_IFUP);
12801         }
12802 }
12803
12804 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12805 {
12806         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12807
12808         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12809
12810         netif_addr_lock_bh(bp->dev);
12811
12812         if (bp->dev->flags & IFF_PROMISC) {
12813                 rx_mode = BNX2X_RX_MODE_PROMISC;
12814         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12815                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12816                     CHIP_IS_E1(bp))) {
12817                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12818         } else {
12819                 if (IS_PF(bp)) {
12820                         /* some multicasts */
12821                         if (bnx2x_set_mc_list(bp) < 0)
12822                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12823
12824                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12825                         netif_addr_unlock_bh(bp->dev);
12826                         if (bnx2x_set_uc_list(bp) < 0)
12827                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12828                         netif_addr_lock_bh(bp->dev);
12829                 } else {
12830                         /* configuring mcast to a vf involves sleeping (when we
12831                          * wait for the pf's response).
12832                          */
12833                         bnx2x_schedule_sp_rtnl(bp,
12834                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12835                 }
12836         }
12837
12838         bp->rx_mode = rx_mode;
12839         /* handle ISCSI SD mode */
12840         if (IS_MF_ISCSI_ONLY(bp))
12841                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12842
12843         /* Schedule the rx_mode command */
12844         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12845                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12846                 netif_addr_unlock_bh(bp->dev);
12847                 return;
12848         }
12849
12850         if (IS_PF(bp)) {
12851                 bnx2x_set_storm_rx_mode(bp);
12852                 netif_addr_unlock_bh(bp->dev);
12853         } else {
12854                 /* VF will need to request the PF to make this change, and so
12855                  * the VF needs to release the bottom-half lock prior to the
12856                  * request (as it will likely require sleep on the VF side)
12857                  */
12858                 netif_addr_unlock_bh(bp->dev);
12859                 bnx2x_vfpf_storm_rx_mode(bp);
12860         }
12861 }
12862
12863 /* called with rtnl_lock */
12864 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12865                            int devad, u16 addr)
12866 {
12867         struct bnx2x *bp = netdev_priv(netdev);
12868         u16 value;
12869         int rc;
12870
12871         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12872            prtad, devad, addr);
12873
12874         /* The HW expects different devad if CL22 is used */
12875         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12876
12877         bnx2x_acquire_phy_lock(bp);
12878         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12879         bnx2x_release_phy_lock(bp);
12880         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12881
12882         if (!rc)
12883                 rc = value;
12884         return rc;
12885 }
12886
12887 /* called with rtnl_lock */
12888 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12889                             u16 addr, u16 value)
12890 {
12891         struct bnx2x *bp = netdev_priv(netdev);
12892         int rc;
12893
12894         DP(NETIF_MSG_LINK,
12895            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12896            prtad, devad, addr, value);
12897
12898         /* The HW expects different devad if CL22 is used */
12899         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12900
12901         bnx2x_acquire_phy_lock(bp);
12902         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12903         bnx2x_release_phy_lock(bp);
12904         return rc;
12905 }
12906
12907 /* called with rtnl_lock */
12908 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12909 {
12910         struct bnx2x *bp = netdev_priv(dev);
12911         struct mii_ioctl_data *mdio = if_mii(ifr);
12912
12913         if (!netif_running(dev))
12914                 return -EAGAIN;
12915
12916         switch (cmd) {
12917         case SIOCSHWTSTAMP:
12918                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12919         default:
12920                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12921                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12922                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12923         }
12924 }
12925
12926 static int bnx2x_validate_addr(struct net_device *dev)
12927 {
12928         struct bnx2x *bp = netdev_priv(dev);
12929
12930         /* query the bulletin board for mac address configured by the PF */
12931         if (IS_VF(bp))
12932                 bnx2x_sample_bulletin(bp);
12933
12934         if (!is_valid_ether_addr(dev->dev_addr)) {
12935                 BNX2X_ERR("Non-valid Ethernet address\n");
12936                 return -EADDRNOTAVAIL;
12937         }
12938         return 0;
12939 }
12940
12941 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12942                                   struct netdev_phys_item_id *ppid)
12943 {
12944         struct bnx2x *bp = netdev_priv(netdev);
12945
12946         if (!(bp->flags & HAS_PHYS_PORT_ID))
12947                 return -EOPNOTSUPP;
12948
12949         ppid->id_len = sizeof(bp->phys_port_id);
12950         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12951
12952         return 0;
12953 }
12954
12955 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12956                                               struct net_device *dev,
12957                                               netdev_features_t features)
12958 {
12959         /*
12960          * A skb with gso_size + header length > 9700 will cause a
12961          * firmware panic. Drop GSO support.
12962          *
12963          * Eventually the upper layer should not pass these packets down.
12964          *
12965          * For speed, if the gso_size is <= 9000, assume there will
12966          * not be 700 bytes of headers and pass it through. Only do a
12967          * full (slow) validation if the gso_size is > 9000.
12968          *
12969          * (Due to the way SKB_BY_FRAGS works this will also do a full
12970          * validation in that case.)
12971          */
12972         if (unlikely(skb_is_gso(skb) &&
12973                      (skb_shinfo(skb)->gso_size > 9000) &&
12974                      !skb_gso_validate_mac_len(skb, 9700)))
12975                 features &= ~NETIF_F_GSO_MASK;
12976
12977         features = vlan_features_check(skb, features);
12978         return vxlan_features_check(skb, features);
12979 }
12980
12981 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12982 {
12983         int rc;
12984
12985         if (IS_PF(bp)) {
12986                 unsigned long ramrod_flags = 0;
12987
12988                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12989                 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12990                                         add, &ramrod_flags);
12991         } else {
12992                 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12993         }
12994
12995         return rc;
12996 }
12997
12998 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
12999 {
13000         struct bnx2x_vlan_entry *vlan;
13001         int rc = 0;
13002
13003         /* Configure all non-configured entries */
13004         list_for_each_entry(vlan, &bp->vlan_reg, link) {
13005                 if (vlan->hw)
13006                         continue;
13007
13008                 if (bp->vlan_cnt >= bp->vlan_credit)
13009                         return -ENOBUFS;
13010
13011                 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
13012                 if (rc) {
13013                         BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
13014                         return rc;
13015                 }
13016
13017                 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
13018                 vlan->hw = true;
13019                 bp->vlan_cnt++;
13020         }
13021
13022         return 0;
13023 }
13024
13025 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
13026 {
13027         bool need_accept_any_vlan;
13028
13029         need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
13030
13031         if (bp->accept_any_vlan != need_accept_any_vlan) {
13032                 bp->accept_any_vlan = need_accept_any_vlan;
13033                 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
13034                    bp->accept_any_vlan ? "raised" : "cleared");
13035                 if (set_rx_mode) {
13036                         if (IS_PF(bp))
13037                                 bnx2x_set_rx_mode_inner(bp);
13038                         else
13039                                 bnx2x_vfpf_storm_rx_mode(bp);
13040                 }
13041         }
13042 }
13043
13044 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
13045 {
13046         /* Don't set rx mode here. Our caller will do it. */
13047         bnx2x_vlan_configure(bp, false);
13048
13049         return 0;
13050 }
13051
13052 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
13053 {
13054         struct bnx2x *bp = netdev_priv(dev);
13055         struct bnx2x_vlan_entry *vlan;
13056
13057         DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
13058
13059         vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
13060         if (!vlan)
13061                 return -ENOMEM;
13062
13063         vlan->vid = vid;
13064         vlan->hw = false;
13065         list_add_tail(&vlan->link, &bp->vlan_reg);
13066
13067         if (netif_running(dev))
13068                 bnx2x_vlan_configure(bp, true);
13069
13070         return 0;
13071 }
13072
13073 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
13074 {
13075         struct bnx2x *bp = netdev_priv(dev);
13076         struct bnx2x_vlan_entry *vlan;
13077         bool found = false;
13078         int rc = 0;
13079
13080         DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
13081
13082         list_for_each_entry(vlan, &bp->vlan_reg, link)
13083                 if (vlan->vid == vid) {
13084                         found = true;
13085                         break;
13086                 }
13087
13088         if (!found) {
13089                 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13090                 return -EINVAL;
13091         }
13092
13093         if (netif_running(dev) && vlan->hw) {
13094                 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
13095                 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13096                 bp->vlan_cnt--;
13097         }
13098
13099         list_del(&vlan->link);
13100         kfree(vlan);
13101
13102         if (netif_running(dev))
13103                 bnx2x_vlan_configure(bp, true);
13104
13105         DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13106
13107         return rc;
13108 }
13109
13110 static const struct net_device_ops bnx2x_netdev_ops = {
13111         .ndo_open               = bnx2x_open,
13112         .ndo_stop               = bnx2x_close,
13113         .ndo_start_xmit         = bnx2x_start_xmit,
13114         .ndo_select_queue       = bnx2x_select_queue,
13115         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
13116         .ndo_set_mac_address    = bnx2x_change_mac_addr,
13117         .ndo_validate_addr      = bnx2x_validate_addr,
13118         .ndo_do_ioctl           = bnx2x_ioctl,
13119         .ndo_change_mtu         = bnx2x_change_mtu,
13120         .ndo_fix_features       = bnx2x_fix_features,
13121         .ndo_set_features       = bnx2x_set_features,
13122         .ndo_tx_timeout         = bnx2x_tx_timeout,
13123         .ndo_vlan_rx_add_vid    = bnx2x_vlan_rx_add_vid,
13124         .ndo_vlan_rx_kill_vid   = bnx2x_vlan_rx_kill_vid,
13125         .ndo_setup_tc           = __bnx2x_setup_tc,
13126 #ifdef CONFIG_BNX2X_SRIOV
13127         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
13128         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
13129         .ndo_get_vf_config      = bnx2x_get_vf_config,
13130         .ndo_set_vf_spoofchk    = bnx2x_set_vf_spoofchk,
13131 #endif
13132 #ifdef NETDEV_FCOE_WWNN
13133         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
13134 #endif
13135
13136         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
13137         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
13138         .ndo_features_check     = bnx2x_features_check,
13139         .ndo_udp_tunnel_add     = bnx2x_udp_tunnel_add,
13140         .ndo_udp_tunnel_del     = bnx2x_udp_tunnel_del,
13141 };
13142
13143 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13144 {
13145         struct device *dev = &bp->pdev->dev;
13146
13147         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13148             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13149                 dev_err(dev, "System does not support DMA, aborting\n");
13150                 return -EIO;
13151         }
13152
13153         return 0;
13154 }
13155
13156 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13157 {
13158         if (bp->flags & AER_ENABLED) {
13159                 pci_disable_pcie_error_reporting(bp->pdev);
13160                 bp->flags &= ~AER_ENABLED;
13161         }
13162 }
13163
13164 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13165                           struct net_device *dev, unsigned long board_type)
13166 {
13167         int rc;
13168         u32 pci_cfg_dword;
13169         bool chip_is_e1x = (board_type == BCM57710 ||
13170                             board_type == BCM57711 ||
13171                             board_type == BCM57711E);
13172
13173         SET_NETDEV_DEV(dev, &pdev->dev);
13174
13175         bp->dev = dev;
13176         bp->pdev = pdev;
13177
13178         rc = pci_enable_device(pdev);
13179         if (rc) {
13180                 dev_err(&bp->pdev->dev,
13181                         "Cannot enable PCI device, aborting\n");
13182                 goto err_out;
13183         }
13184
13185         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13186                 dev_err(&bp->pdev->dev,
13187                         "Cannot find PCI device base address, aborting\n");
13188                 rc = -ENODEV;
13189                 goto err_out_disable;
13190         }
13191
13192         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13193                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13194                 rc = -ENODEV;
13195                 goto err_out_disable;
13196         }
13197
13198         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13199         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13200             PCICFG_REVESION_ID_ERROR_VAL) {
13201                 pr_err("PCI device error, probably due to fan failure, aborting\n");
13202                 rc = -ENODEV;
13203                 goto err_out_disable;
13204         }
13205
13206         if (atomic_read(&pdev->enable_cnt) == 1) {
13207                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13208                 if (rc) {
13209                         dev_err(&bp->pdev->dev,
13210                                 "Cannot obtain PCI resources, aborting\n");
13211                         goto err_out_disable;
13212                 }
13213
13214                 pci_set_master(pdev);
13215                 pci_save_state(pdev);
13216         }
13217
13218         if (IS_PF(bp)) {
13219                 if (!pdev->pm_cap) {
13220                         dev_err(&bp->pdev->dev,
13221                                 "Cannot find power management capability, aborting\n");
13222                         rc = -EIO;
13223                         goto err_out_release;
13224                 }
13225         }
13226
13227         if (!pci_is_pcie(pdev)) {
13228                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13229                 rc = -EIO;
13230                 goto err_out_release;
13231         }
13232
13233         rc = bnx2x_set_coherency_mask(bp);
13234         if (rc)
13235                 goto err_out_release;
13236
13237         dev->mem_start = pci_resource_start(pdev, 0);
13238         dev->base_addr = dev->mem_start;
13239         dev->mem_end = pci_resource_end(pdev, 0);
13240
13241         dev->irq = pdev->irq;
13242
13243         bp->regview = pci_ioremap_bar(pdev, 0);
13244         if (!bp->regview) {
13245                 dev_err(&bp->pdev->dev,
13246                         "Cannot map register space, aborting\n");
13247                 rc = -ENOMEM;
13248                 goto err_out_release;
13249         }
13250
13251         /* In E1/E1H use pci device function given by kernel.
13252          * In E2/E3 read physical function from ME register since these chips
13253          * support Physical Device Assignment where kernel BDF maybe arbitrary
13254          * (depending on hypervisor).
13255          */
13256         if (chip_is_e1x) {
13257                 bp->pf_num = PCI_FUNC(pdev->devfn);
13258         } else {
13259                 /* chip is E2/3*/
13260                 pci_read_config_dword(bp->pdev,
13261                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
13262                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13263                                   ME_REG_ABS_PF_NUM_SHIFT);
13264         }
13265         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13266
13267         /* clean indirect addresses */
13268         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13269                                PCICFG_VENDOR_ID_OFFSET);
13270
13271         /* Set PCIe reset type to fundamental for EEH recovery */
13272         pdev->needs_freset = 1;
13273
13274         /* AER (Advanced Error reporting) configuration */
13275         rc = pci_enable_pcie_error_reporting(pdev);
13276         if (!rc)
13277                 bp->flags |= AER_ENABLED;
13278         else
13279                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13280
13281         /*
13282          * Clean the following indirect addresses for all functions since it
13283          * is not used by the driver.
13284          */
13285         if (IS_PF(bp)) {
13286                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13287                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13288                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13289                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13290
13291                 if (chip_is_e1x) {
13292                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13293                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13294                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13295                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13296                 }
13297
13298                 /* Enable internal target-read (in case we are probed after PF
13299                  * FLR). Must be done prior to any BAR read access. Only for
13300                  * 57712 and up
13301                  */
13302                 if (!chip_is_e1x)
13303                         REG_WR(bp,
13304                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13305         }
13306
13307         dev->watchdog_timeo = TX_TIMEOUT;
13308
13309         dev->netdev_ops = &bnx2x_netdev_ops;
13310         bnx2x_set_ethtool_ops(bp, dev);
13311
13312         dev->priv_flags |= IFF_UNICAST_FLT;
13313
13314         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13315                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13316                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW |
13317                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13318         if (!chip_is_e1x) {
13319                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13320                                     NETIF_F_GSO_IPXIP4 |
13321                                     NETIF_F_GSO_UDP_TUNNEL |
13322                                     NETIF_F_GSO_UDP_TUNNEL_CSUM |
13323                                     NETIF_F_GSO_PARTIAL;
13324
13325                 dev->hw_enc_features =
13326                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13327                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13328                         NETIF_F_GSO_IPXIP4 |
13329                         NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13330                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13331                         NETIF_F_GSO_PARTIAL;
13332
13333                 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13334                                             NETIF_F_GSO_UDP_TUNNEL_CSUM;
13335         }
13336
13337         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13338                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13339
13340         if (IS_PF(bp)) {
13341                 if (chip_is_e1x)
13342                         bp->accept_any_vlan = true;
13343                 else
13344                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13345         }
13346         /* For VF we'll know whether to enable VLAN filtering after
13347          * getting a response to CHANNEL_TLV_ACQUIRE from PF.
13348          */
13349
13350         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13351         dev->features |= NETIF_F_HIGHDMA;
13352         if (dev->features & NETIF_F_LRO)
13353                 dev->features &= ~NETIF_F_GRO_HW;
13354
13355         /* Add Loopback capability to the device */
13356         dev->hw_features |= NETIF_F_LOOPBACK;
13357
13358 #ifdef BCM_DCBNL
13359         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13360 #endif
13361
13362         /* MTU range, 46 - 9600 */
13363         dev->min_mtu = ETH_MIN_PACKET_SIZE;
13364         dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE;
13365
13366         /* get_port_hwinfo() will set prtad and mmds properly */
13367         bp->mdio.prtad = MDIO_PRTAD_NONE;
13368         bp->mdio.mmds = 0;
13369         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13370         bp->mdio.dev = dev;
13371         bp->mdio.mdio_read = bnx2x_mdio_read;
13372         bp->mdio.mdio_write = bnx2x_mdio_write;
13373
13374         return 0;
13375
13376 err_out_release:
13377         if (atomic_read(&pdev->enable_cnt) == 1)
13378                 pci_release_regions(pdev);
13379
13380 err_out_disable:
13381         pci_disable_device(pdev);
13382
13383 err_out:
13384         return rc;
13385 }
13386
13387 static int bnx2x_check_firmware(struct bnx2x *bp)
13388 {
13389         const struct firmware *firmware = bp->firmware;
13390         struct bnx2x_fw_file_hdr *fw_hdr;
13391         struct bnx2x_fw_file_section *sections;
13392         u32 offset, len, num_ops;
13393         __be16 *ops_offsets;
13394         int i;
13395         const u8 *fw_ver;
13396
13397         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13398                 BNX2X_ERR("Wrong FW size\n");
13399                 return -EINVAL;
13400         }
13401
13402         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13403         sections = (struct bnx2x_fw_file_section *)fw_hdr;
13404
13405         /* Make sure none of the offsets and sizes make us read beyond
13406          * the end of the firmware data */
13407         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13408                 offset = be32_to_cpu(sections[i].offset);
13409                 len = be32_to_cpu(sections[i].len);
13410                 if (offset + len > firmware->size) {
13411                         BNX2X_ERR("Section %d length is out of bounds\n", i);
13412                         return -EINVAL;
13413                 }
13414         }
13415
13416         /* Likewise for the init_ops offsets */
13417         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
13418         ops_offsets = (__force __be16 *)(firmware->data + offset);
13419         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13420
13421         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13422                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
13423                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
13424                         return -EINVAL;
13425                 }
13426         }
13427
13428         /* Check FW version */
13429         offset = be32_to_cpu(fw_hdr->fw_version.offset);
13430         fw_ver = firmware->data + offset;
13431         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13432             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13433             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13434             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
13435                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13436                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13437                        BCM_5710_FW_MAJOR_VERSION,
13438                        BCM_5710_FW_MINOR_VERSION,
13439                        BCM_5710_FW_REVISION_VERSION,
13440                        BCM_5710_FW_ENGINEERING_VERSION);
13441                 return -EINVAL;
13442         }
13443
13444         return 0;
13445 }
13446
13447 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13448 {
13449         const __be32 *source = (const __be32 *)_source;
13450         u32 *target = (u32 *)_target;
13451         u32 i;
13452
13453         for (i = 0; i < n/4; i++)
13454                 target[i] = be32_to_cpu(source[i]);
13455 }
13456
13457 /*
13458    Ops array is stored in the following format:
13459    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13460  */
13461 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13462 {
13463         const __be32 *source = (const __be32 *)_source;
13464         struct raw_op *target = (struct raw_op *)_target;
13465         u32 i, j, tmp;
13466
13467         for (i = 0, j = 0; i < n/8; i++, j += 2) {
13468                 tmp = be32_to_cpu(source[j]);
13469                 target[i].op = (tmp >> 24) & 0xff;
13470                 target[i].offset = tmp & 0xffffff;
13471                 target[i].raw_data = be32_to_cpu(source[j + 1]);
13472         }
13473 }
13474
13475 /* IRO array is stored in the following format:
13476  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13477  */
13478 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13479 {
13480         const __be32 *source = (const __be32 *)_source;
13481         struct iro *target = (struct iro *)_target;
13482         u32 i, j, tmp;
13483
13484         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13485                 target[i].base = be32_to_cpu(source[j]);
13486                 j++;
13487                 tmp = be32_to_cpu(source[j]);
13488                 target[i].m1 = (tmp >> 16) & 0xffff;
13489                 target[i].m2 = tmp & 0xffff;
13490                 j++;
13491                 tmp = be32_to_cpu(source[j]);
13492                 target[i].m3 = (tmp >> 16) & 0xffff;
13493                 target[i].size = tmp & 0xffff;
13494                 j++;
13495         }
13496 }
13497
13498 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13499 {
13500         const __be16 *source = (const __be16 *)_source;
13501         u16 *target = (u16 *)_target;
13502         u32 i;
13503
13504         for (i = 0; i < n/2; i++)
13505                 target[i] = be16_to_cpu(source[i]);
13506 }
13507
13508 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13509 do {                                                                    \
13510         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13511         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13512         if (!bp->arr)                                                   \
13513                 goto lbl;                                               \
13514         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13515              (u8 *)bp->arr, len);                                       \
13516 } while (0)
13517
13518 static int bnx2x_init_firmware(struct bnx2x *bp)
13519 {
13520         const char *fw_file_name;
13521         struct bnx2x_fw_file_hdr *fw_hdr;
13522         int rc;
13523
13524         if (bp->firmware)
13525                 return 0;
13526
13527         if (CHIP_IS_E1(bp))
13528                 fw_file_name = FW_FILE_NAME_E1;
13529         else if (CHIP_IS_E1H(bp))
13530                 fw_file_name = FW_FILE_NAME_E1H;
13531         else if (!CHIP_IS_E1x(bp))
13532                 fw_file_name = FW_FILE_NAME_E2;
13533         else {
13534                 BNX2X_ERR("Unsupported chip revision\n");
13535                 return -EINVAL;
13536         }
13537         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13538
13539         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13540         if (rc) {
13541                 BNX2X_ERR("Can't load firmware file %s\n",
13542                           fw_file_name);
13543                 goto request_firmware_exit;
13544         }
13545
13546         rc = bnx2x_check_firmware(bp);
13547         if (rc) {
13548                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13549                 goto request_firmware_exit;
13550         }
13551
13552         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13553
13554         /* Initialize the pointers to the init arrays */
13555         /* Blob */
13556         rc = -ENOMEM;
13557         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13558
13559         /* Opcodes */
13560         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13561
13562         /* Offsets */
13563         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13564                             be16_to_cpu_n);
13565
13566         /* STORMs firmware */
13567         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13568                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13569         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13570                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13571         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13572                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13573         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13574                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13575         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13576                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13577         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13578                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13579         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13580                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13581         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13582                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13583         /* IRO */
13584         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13585
13586         return 0;
13587
13588 iro_alloc_err:
13589         kfree(bp->init_ops_offsets);
13590 init_offsets_alloc_err:
13591         kfree(bp->init_ops);
13592 init_ops_alloc_err:
13593         kfree(bp->init_data);
13594 request_firmware_exit:
13595         release_firmware(bp->firmware);
13596         bp->firmware = NULL;
13597
13598         return rc;
13599 }
13600
13601 static void bnx2x_release_firmware(struct bnx2x *bp)
13602 {
13603         kfree(bp->init_ops_offsets);
13604         kfree(bp->init_ops);
13605         kfree(bp->init_data);
13606         release_firmware(bp->firmware);
13607         bp->firmware = NULL;
13608 }
13609
13610 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13611         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13612         .init_hw_cmn      = bnx2x_init_hw_common,
13613         .init_hw_port     = bnx2x_init_hw_port,
13614         .init_hw_func     = bnx2x_init_hw_func,
13615
13616         .reset_hw_cmn     = bnx2x_reset_common,
13617         .reset_hw_port    = bnx2x_reset_port,
13618         .reset_hw_func    = bnx2x_reset_func,
13619
13620         .gunzip_init      = bnx2x_gunzip_init,
13621         .gunzip_end       = bnx2x_gunzip_end,
13622
13623         .init_fw          = bnx2x_init_firmware,
13624         .release_fw       = bnx2x_release_firmware,
13625 };
13626
13627 void bnx2x__init_func_obj(struct bnx2x *bp)
13628 {
13629         /* Prepare DMAE related driver resources */
13630         bnx2x_setup_dmae(bp);
13631
13632         bnx2x_init_func_obj(bp, &bp->func_obj,
13633                             bnx2x_sp(bp, func_rdata),
13634                             bnx2x_sp_mapping(bp, func_rdata),
13635                             bnx2x_sp(bp, func_afex_rdata),
13636                             bnx2x_sp_mapping(bp, func_afex_rdata),
13637                             &bnx2x_func_sp_drv);
13638 }
13639
13640 /* must be called after sriov-enable */
13641 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13642 {
13643         int cid_count = BNX2X_L2_MAX_CID(bp);
13644
13645         if (IS_SRIOV(bp))
13646                 cid_count += BNX2X_VF_CIDS;
13647
13648         if (CNIC_SUPPORT(bp))
13649                 cid_count += CNIC_CID_MAX;
13650
13651         return roundup(cid_count, QM_CID_ROUND);
13652 }
13653
13654 /**
13655  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13656  *
13657  * @dev:        pci device
13658  *
13659  */
13660 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13661 {
13662         int index;
13663         u16 control = 0;
13664
13665         /*
13666          * If MSI-X is not supported - return number of SBs needed to support
13667          * one fast path queue: one FP queue + SB for CNIC
13668          */
13669         if (!pdev->msix_cap) {
13670                 dev_info(&pdev->dev, "no msix capability found\n");
13671                 return 1 + cnic_cnt;
13672         }
13673         dev_info(&pdev->dev, "msix capability found\n");
13674
13675         /*
13676          * The value in the PCI configuration space is the index of the last
13677          * entry, namely one less than the actual size of the table, which is
13678          * exactly what we want to return from this function: number of all SBs
13679          * without the default SB.
13680          * For VFs there is no default SB, then we return (index+1).
13681          */
13682         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13683
13684         index = control & PCI_MSIX_FLAGS_QSIZE;
13685
13686         return index;
13687 }
13688
13689 static int set_max_cos_est(int chip_id)
13690 {
13691         switch (chip_id) {
13692         case BCM57710:
13693         case BCM57711:
13694         case BCM57711E:
13695                 return BNX2X_MULTI_TX_COS_E1X;
13696         case BCM57712:
13697         case BCM57712_MF:
13698                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13699         case BCM57800:
13700         case BCM57800_MF:
13701         case BCM57810:
13702         case BCM57810_MF:
13703         case BCM57840_4_10:
13704         case BCM57840_2_20:
13705         case BCM57840_O:
13706         case BCM57840_MFO:
13707         case BCM57840_MF:
13708         case BCM57811:
13709         case BCM57811_MF:
13710                 return BNX2X_MULTI_TX_COS_E3B0;
13711         case BCM57712_VF:
13712         case BCM57800_VF:
13713         case BCM57810_VF:
13714         case BCM57840_VF:
13715         case BCM57811_VF:
13716                 return 1;
13717         default:
13718                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13719                 return -ENODEV;
13720         }
13721 }
13722
13723 static int set_is_vf(int chip_id)
13724 {
13725         switch (chip_id) {
13726         case BCM57712_VF:
13727         case BCM57800_VF:
13728         case BCM57810_VF:
13729         case BCM57840_VF:
13730         case BCM57811_VF:
13731                 return true;
13732         default:
13733                 return false;
13734         }
13735 }
13736
13737 /* nig_tsgen registers relative address */
13738 #define tsgen_ctrl 0x0
13739 #define tsgen_freecount 0x10
13740 #define tsgen_synctime_t0 0x20
13741 #define tsgen_offset_t0 0x28
13742 #define tsgen_drift_t0 0x30
13743 #define tsgen_synctime_t1 0x58
13744 #define tsgen_offset_t1 0x60
13745 #define tsgen_drift_t1 0x68
13746
13747 /* FW workaround for setting drift */
13748 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13749                                           int best_val, int best_period)
13750 {
13751         struct bnx2x_func_state_params func_params = {NULL};
13752         struct bnx2x_func_set_timesync_params *set_timesync_params =
13753                 &func_params.params.set_timesync;
13754
13755         /* Prepare parameters for function state transitions */
13756         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13757         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13758
13759         func_params.f_obj = &bp->func_obj;
13760         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13761
13762         /* Function parameters */
13763         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13764         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13765         set_timesync_params->add_sub_drift_adjust_value =
13766                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13767         set_timesync_params->drift_adjust_value = best_val;
13768         set_timesync_params->drift_adjust_period = best_period;
13769
13770         return bnx2x_func_state_change(bp, &func_params);
13771 }
13772
13773 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13774 {
13775         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13776         int rc;
13777         int drift_dir = 1;
13778         int val, period, period1, period2, dif, dif1, dif2;
13779         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13780
13781         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13782
13783         if (!netif_running(bp->dev)) {
13784                 DP(BNX2X_MSG_PTP,
13785                    "PTP adjfreq called while the interface is down\n");
13786                 return -ENETDOWN;
13787         }
13788
13789         if (ppb < 0) {
13790                 ppb = -ppb;
13791                 drift_dir = 0;
13792         }
13793
13794         if (ppb == 0) {
13795                 best_val = 1;
13796                 best_period = 0x1FFFFFF;
13797         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13798                 best_val = 31;
13799                 best_period = 1;
13800         } else {
13801                 /* Changed not to allow val = 8, 16, 24 as these values
13802                  * are not supported in workaround.
13803                  */
13804                 for (val = 0; val <= 31; val++) {
13805                         if ((val & 0x7) == 0)
13806                                 continue;
13807                         period1 = val * 1000000 / ppb;
13808                         period2 = period1 + 1;
13809                         if (period1 != 0)
13810                                 dif1 = ppb - (val * 1000000 / period1);
13811                         else
13812                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13813                         if (dif1 < 0)
13814                                 dif1 = -dif1;
13815                         dif2 = ppb - (val * 1000000 / period2);
13816                         if (dif2 < 0)
13817                                 dif2 = -dif2;
13818                         dif = (dif1 < dif2) ? dif1 : dif2;
13819                         period = (dif1 < dif2) ? period1 : period2;
13820                         if (dif < best_dif) {
13821                                 best_dif = dif;
13822                                 best_val = val;
13823                                 best_period = period;
13824                         }
13825                 }
13826         }
13827
13828         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13829                                             best_period);
13830         if (rc) {
13831                 BNX2X_ERR("Failed to set drift\n");
13832                 return -EFAULT;
13833         }
13834
13835         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13836            best_period);
13837
13838         return 0;
13839 }
13840
13841 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13842 {
13843         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13844
13845         if (!netif_running(bp->dev)) {
13846                 DP(BNX2X_MSG_PTP,
13847                    "PTP adjtime called while the interface is down\n");
13848                 return -ENETDOWN;
13849         }
13850
13851         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13852
13853         timecounter_adjtime(&bp->timecounter, delta);
13854
13855         return 0;
13856 }
13857
13858 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13859 {
13860         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13861         u64 ns;
13862
13863         if (!netif_running(bp->dev)) {
13864                 DP(BNX2X_MSG_PTP,
13865                    "PTP gettime called while the interface is down\n");
13866                 return -ENETDOWN;
13867         }
13868
13869         ns = timecounter_read(&bp->timecounter);
13870
13871         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13872
13873         *ts = ns_to_timespec64(ns);
13874
13875         return 0;
13876 }
13877
13878 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13879                              const struct timespec64 *ts)
13880 {
13881         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13882         u64 ns;
13883
13884         if (!netif_running(bp->dev)) {
13885                 DP(BNX2X_MSG_PTP,
13886                    "PTP settime called while the interface is down\n");
13887                 return -ENETDOWN;
13888         }
13889
13890         ns = timespec64_to_ns(ts);
13891
13892         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13893
13894         /* Re-init the timecounter */
13895         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13896
13897         return 0;
13898 }
13899
13900 /* Enable (or disable) ancillary features of the phc subsystem */
13901 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13902                             struct ptp_clock_request *rq, int on)
13903 {
13904         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13905
13906         BNX2X_ERR("PHC ancillary features are not supported\n");
13907         return -ENOTSUPP;
13908 }
13909
13910 void bnx2x_register_phc(struct bnx2x *bp)
13911 {
13912         /* Fill the ptp_clock_info struct and register PTP clock*/
13913         bp->ptp_clock_info.owner = THIS_MODULE;
13914         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13915         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13916         bp->ptp_clock_info.n_alarm = 0;
13917         bp->ptp_clock_info.n_ext_ts = 0;
13918         bp->ptp_clock_info.n_per_out = 0;
13919         bp->ptp_clock_info.pps = 0;
13920         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13921         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13922         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13923         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13924         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13925
13926         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13927         if (IS_ERR(bp->ptp_clock)) {
13928                 bp->ptp_clock = NULL;
13929                 BNX2X_ERR("PTP clock registration failed\n");
13930         }
13931 }
13932
13933 static int bnx2x_init_one(struct pci_dev *pdev,
13934                                     const struct pci_device_id *ent)
13935 {
13936         struct net_device *dev = NULL;
13937         struct bnx2x *bp;
13938         int rc, max_non_def_sbs;
13939         int rx_count, tx_count, rss_count, doorbell_size;
13940         int max_cos_est;
13941         bool is_vf;
13942         int cnic_cnt;
13943
13944         /* Management FW 'remembers' living interfaces. Allow it some time
13945          * to forget previously living interfaces, allowing a proper re-load.
13946          */
13947         if (is_kdump_kernel()) {
13948                 ktime_t now = ktime_get_boottime();
13949                 ktime_t fw_ready_time = ktime_set(5, 0);
13950
13951                 if (ktime_before(now, fw_ready_time))
13952                         msleep(ktime_ms_delta(fw_ready_time, now));
13953         }
13954
13955         /* An estimated maximum supported CoS number according to the chip
13956          * version.
13957          * We will try to roughly estimate the maximum number of CoSes this chip
13958          * may support in order to minimize the memory allocated for Tx
13959          * netdev_queue's. This number will be accurately calculated during the
13960          * initialization of bp->max_cos based on the chip versions AND chip
13961          * revision in the bnx2x_init_bp().
13962          */
13963         max_cos_est = set_max_cos_est(ent->driver_data);
13964         if (max_cos_est < 0)
13965                 return max_cos_est;
13966         is_vf = set_is_vf(ent->driver_data);
13967         cnic_cnt = is_vf ? 0 : 1;
13968
13969         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13970
13971         /* add another SB for VF as it has no default SB */
13972         max_non_def_sbs += is_vf ? 1 : 0;
13973
13974         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13975         rss_count = max_non_def_sbs - cnic_cnt;
13976
13977         if (rss_count < 1)
13978                 return -EINVAL;
13979
13980         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13981         rx_count = rss_count + cnic_cnt;
13982
13983         /* Maximum number of netdev Tx queues:
13984          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13985          */
13986         tx_count = rss_count * max_cos_est + cnic_cnt;
13987
13988         /* dev zeroed in init_etherdev */
13989         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13990         if (!dev)
13991                 return -ENOMEM;
13992
13993         bp = netdev_priv(dev);
13994
13995         bp->flags = 0;
13996         if (is_vf)
13997                 bp->flags |= IS_VF_FLAG;
13998
13999         bp->igu_sb_cnt = max_non_def_sbs;
14000         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
14001         bp->msg_enable = debug;
14002         bp->cnic_support = cnic_cnt;
14003         bp->cnic_probe = bnx2x_cnic_probe;
14004
14005         pci_set_drvdata(pdev, dev);
14006
14007         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
14008         if (rc < 0) {
14009                 free_netdev(dev);
14010                 return rc;
14011         }
14012
14013         BNX2X_DEV_INFO("This is a %s function\n",
14014                        IS_PF(bp) ? "physical" : "virtual");
14015         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
14016         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
14017         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
14018                        tx_count, rx_count);
14019
14020         rc = bnx2x_init_bp(bp);
14021         if (rc)
14022                 goto init_one_exit;
14023
14024         /* Map doorbells here as we need the real value of bp->max_cos which
14025          * is initialized in bnx2x_init_bp() to determine the number of
14026          * l2 connections.
14027          */
14028         if (IS_VF(bp)) {
14029                 bp->doorbells = bnx2x_vf_doorbells(bp);
14030                 rc = bnx2x_vf_pci_alloc(bp);
14031                 if (rc)
14032                         goto init_one_freemem;
14033         } else {
14034                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
14035                 if (doorbell_size > pci_resource_len(pdev, 2)) {
14036                         dev_err(&bp->pdev->dev,
14037                                 "Cannot map doorbells, bar size too small, aborting\n");
14038                         rc = -ENOMEM;
14039                         goto init_one_freemem;
14040                 }
14041                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
14042                                                 doorbell_size);
14043         }
14044         if (!bp->doorbells) {
14045                 dev_err(&bp->pdev->dev,
14046                         "Cannot map doorbell space, aborting\n");
14047                 rc = -ENOMEM;
14048                 goto init_one_freemem;
14049         }
14050
14051         if (IS_VF(bp)) {
14052                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
14053                 if (rc)
14054                         goto init_one_freemem;
14055
14056 #ifdef CONFIG_BNX2X_SRIOV
14057                 /* VF with OLD Hypervisor or old PF do not support filtering */
14058                 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
14059                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14060                         dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14061                 }
14062 #endif
14063         }
14064
14065         /* Enable SRIOV if capability found in configuration space */
14066         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
14067         if (rc)
14068                 goto init_one_freemem;
14069
14070         /* calc qm_cid_count */
14071         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
14072         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
14073
14074         /* disable FCOE L2 queue for E1x*/
14075         if (CHIP_IS_E1x(bp))
14076                 bp->flags |= NO_FCOE_FLAG;
14077
14078         /* Set bp->num_queues for MSI-X mode*/
14079         bnx2x_set_num_queues(bp);
14080
14081         /* Configure interrupt mode: try to enable MSI-X/MSI if
14082          * needed.
14083          */
14084         rc = bnx2x_set_int_mode(bp);
14085         if (rc) {
14086                 dev_err(&pdev->dev, "Cannot set interrupts\n");
14087                 goto init_one_freemem;
14088         }
14089         BNX2X_DEV_INFO("set interrupts successfully\n");
14090
14091         /* register the net device */
14092         rc = register_netdev(dev);
14093         if (rc) {
14094                 dev_err(&pdev->dev, "Cannot register net device\n");
14095                 goto init_one_freemem;
14096         }
14097         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
14098
14099         if (!NO_FCOE(bp)) {
14100                 /* Add storage MAC address */
14101                 rtnl_lock();
14102                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14103                 rtnl_unlock();
14104         }
14105         BNX2X_DEV_INFO(
14106                "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n",
14107                board_info[ent->driver_data].name,
14108                (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14109                dev->base_addr, bp->pdev->irq, dev->dev_addr);
14110         pcie_print_link_status(bp->pdev);
14111
14112         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14113                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14114
14115         return 0;
14116
14117 init_one_freemem:
14118         bnx2x_free_mem_bp(bp);
14119
14120 init_one_exit:
14121         bnx2x_disable_pcie_error_reporting(bp);
14122
14123         if (bp->regview)
14124                 iounmap(bp->regview);
14125
14126         if (IS_PF(bp) && bp->doorbells)
14127                 iounmap(bp->doorbells);
14128
14129         free_netdev(dev);
14130
14131         if (atomic_read(&pdev->enable_cnt) == 1)
14132                 pci_release_regions(pdev);
14133
14134         pci_disable_device(pdev);
14135
14136         return rc;
14137 }
14138
14139 static void __bnx2x_remove(struct pci_dev *pdev,
14140                            struct net_device *dev,
14141                            struct bnx2x *bp,
14142                            bool remove_netdev)
14143 {
14144         /* Delete storage MAC address */
14145         if (!NO_FCOE(bp)) {
14146                 rtnl_lock();
14147                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14148                 rtnl_unlock();
14149         }
14150
14151 #ifdef BCM_DCBNL
14152         /* Delete app tlvs from dcbnl */
14153         bnx2x_dcbnl_update_applist(bp, true);
14154 #endif
14155
14156         if (IS_PF(bp) &&
14157             !BP_NOMCP(bp) &&
14158             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14159                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14160
14161         /* Close the interface - either directly or implicitly */
14162         if (remove_netdev) {
14163                 unregister_netdev(dev);
14164         } else {
14165                 rtnl_lock();
14166                 dev_close(dev);
14167                 rtnl_unlock();
14168         }
14169
14170         bnx2x_iov_remove_one(bp);
14171
14172         /* Power on: we can't let PCI layer write to us while we are in D3 */
14173         if (IS_PF(bp)) {
14174                 bnx2x_set_power_state(bp, PCI_D0);
14175                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14176
14177                 /* Set endianity registers to reset values in case next driver
14178                  * boots in different endianty environment.
14179                  */
14180                 bnx2x_reset_endianity(bp);
14181         }
14182
14183         /* Disable MSI/MSI-X */
14184         bnx2x_disable_msi(bp);
14185
14186         /* Power off */
14187         if (IS_PF(bp))
14188                 bnx2x_set_power_state(bp, PCI_D3hot);
14189
14190         /* Make sure RESET task is not scheduled before continuing */
14191         cancel_delayed_work_sync(&bp->sp_rtnl_task);
14192
14193         /* send message via vfpf channel to release the resources of this vf */
14194         if (IS_VF(bp))
14195                 bnx2x_vfpf_release(bp);
14196
14197         /* Assumes no further PCIe PM changes will occur */
14198         if (system_state == SYSTEM_POWER_OFF) {
14199                 pci_wake_from_d3(pdev, bp->wol);
14200                 pci_set_power_state(pdev, PCI_D3hot);
14201         }
14202
14203         bnx2x_disable_pcie_error_reporting(bp);
14204         if (remove_netdev) {
14205                 if (bp->regview)
14206                         iounmap(bp->regview);
14207
14208                 /* For vfs, doorbells are part of the regview and were unmapped
14209                  * along with it. FW is only loaded by PF.
14210                  */
14211                 if (IS_PF(bp)) {
14212                         if (bp->doorbells)
14213                                 iounmap(bp->doorbells);
14214
14215                         bnx2x_release_firmware(bp);
14216                 } else {
14217                         bnx2x_vf_pci_dealloc(bp);
14218                 }
14219                 bnx2x_free_mem_bp(bp);
14220
14221                 free_netdev(dev);
14222
14223                 if (atomic_read(&pdev->enable_cnt) == 1)
14224                         pci_release_regions(pdev);
14225
14226                 pci_disable_device(pdev);
14227         }
14228 }
14229
14230 static void bnx2x_remove_one(struct pci_dev *pdev)
14231 {
14232         struct net_device *dev = pci_get_drvdata(pdev);
14233         struct bnx2x *bp;
14234
14235         if (!dev) {
14236                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14237                 return;
14238         }
14239         bp = netdev_priv(dev);
14240
14241         __bnx2x_remove(pdev, dev, bp, true);
14242 }
14243
14244 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14245 {
14246         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14247
14248         bp->rx_mode = BNX2X_RX_MODE_NONE;
14249
14250         if (CNIC_LOADED(bp))
14251                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14252
14253         /* Stop Tx */
14254         bnx2x_tx_disable(bp);
14255         /* Delete all NAPI objects */
14256         bnx2x_del_all_napi(bp);
14257         if (CNIC_LOADED(bp))
14258                 bnx2x_del_all_napi_cnic(bp);
14259         netdev_reset_tc(bp->dev);
14260
14261         del_timer_sync(&bp->timer);
14262         cancel_delayed_work_sync(&bp->sp_task);
14263         cancel_delayed_work_sync(&bp->period_task);
14264
14265         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14266                 bp->stats_state = STATS_STATE_DISABLED;
14267                 up(&bp->stats_lock);
14268         }
14269
14270         bnx2x_save_statistics(bp);
14271
14272         netif_carrier_off(bp->dev);
14273
14274         return 0;
14275 }
14276
14277 /**
14278  * bnx2x_io_error_detected - called when PCI error is detected
14279  * @pdev: Pointer to PCI device
14280  * @state: The current pci connection state
14281  *
14282  * This function is called after a PCI bus error affecting
14283  * this device has been detected.
14284  */
14285 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14286                                                 pci_channel_state_t state)
14287 {
14288         struct net_device *dev = pci_get_drvdata(pdev);
14289         struct bnx2x *bp = netdev_priv(dev);
14290
14291         rtnl_lock();
14292
14293         BNX2X_ERR("IO error detected\n");
14294
14295         netif_device_detach(dev);
14296
14297         if (state == pci_channel_io_perm_failure) {
14298                 rtnl_unlock();
14299                 return PCI_ERS_RESULT_DISCONNECT;
14300         }
14301
14302         if (netif_running(dev))
14303                 bnx2x_eeh_nic_unload(bp);
14304
14305         bnx2x_prev_path_mark_eeh(bp);
14306
14307         pci_disable_device(pdev);
14308
14309         rtnl_unlock();
14310
14311         /* Request a slot reset */
14312         return PCI_ERS_RESULT_NEED_RESET;
14313 }
14314
14315 /**
14316  * bnx2x_io_slot_reset - called after the PCI bus has been reset
14317  * @pdev: Pointer to PCI device
14318  *
14319  * Restart the card from scratch, as if from a cold-boot.
14320  */
14321 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14322 {
14323         struct net_device *dev = pci_get_drvdata(pdev);
14324         struct bnx2x *bp = netdev_priv(dev);
14325         int i;
14326
14327         rtnl_lock();
14328         BNX2X_ERR("IO slot reset initializing...\n");
14329         if (pci_enable_device(pdev)) {
14330                 dev_err(&pdev->dev,
14331                         "Cannot re-enable PCI device after reset\n");
14332                 rtnl_unlock();
14333                 return PCI_ERS_RESULT_DISCONNECT;
14334         }
14335
14336         pci_set_master(pdev);
14337         pci_restore_state(pdev);
14338         pci_save_state(pdev);
14339
14340         if (netif_running(dev))
14341                 bnx2x_set_power_state(bp, PCI_D0);
14342
14343         if (netif_running(dev)) {
14344                 BNX2X_ERR("IO slot reset --> driver unload\n");
14345
14346                 /* MCP should have been reset; Need to wait for validity */
14347                 if (bnx2x_init_shmem(bp)) {
14348                         rtnl_unlock();
14349                         return PCI_ERS_RESULT_DISCONNECT;
14350                 }
14351
14352                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14353                         u32 v;
14354
14355                         v = SHMEM2_RD(bp,
14356                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14357                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14358                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14359                 }
14360                 bnx2x_drain_tx_queues(bp);
14361                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14362                 bnx2x_netif_stop(bp, 1);
14363                 bnx2x_free_irq(bp);
14364
14365                 /* Report UNLOAD_DONE to MCP */
14366                 bnx2x_send_unload_done(bp, true);
14367
14368                 bp->sp_state = 0;
14369                 bp->port.pmf = 0;
14370
14371                 bnx2x_prev_unload(bp);
14372
14373                 /* We should have reseted the engine, so It's fair to
14374                  * assume the FW will no longer write to the bnx2x driver.
14375                  */
14376                 bnx2x_squeeze_objects(bp);
14377                 bnx2x_free_skbs(bp);
14378                 for_each_rx_queue(bp, i)
14379                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14380                 bnx2x_free_fp_mem(bp);
14381                 bnx2x_free_mem(bp);
14382
14383                 bp->state = BNX2X_STATE_CLOSED;
14384         }
14385
14386         rtnl_unlock();
14387
14388         return PCI_ERS_RESULT_RECOVERED;
14389 }
14390
14391 /**
14392  * bnx2x_io_resume - called when traffic can start flowing again
14393  * @pdev: Pointer to PCI device
14394  *
14395  * This callback is called when the error recovery driver tells us that
14396  * its OK to resume normal operation.
14397  */
14398 static void bnx2x_io_resume(struct pci_dev *pdev)
14399 {
14400         struct net_device *dev = pci_get_drvdata(pdev);
14401         struct bnx2x *bp = netdev_priv(dev);
14402
14403         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14404                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14405                 return;
14406         }
14407
14408         rtnl_lock();
14409
14410         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14411                                                         DRV_MSG_SEQ_NUMBER_MASK;
14412
14413         if (netif_running(dev))
14414                 bnx2x_nic_load(bp, LOAD_NORMAL);
14415
14416         netif_device_attach(dev);
14417
14418         rtnl_unlock();
14419 }
14420
14421 static const struct pci_error_handlers bnx2x_err_handler = {
14422         .error_detected = bnx2x_io_error_detected,
14423         .slot_reset     = bnx2x_io_slot_reset,
14424         .resume         = bnx2x_io_resume,
14425 };
14426
14427 static void bnx2x_shutdown(struct pci_dev *pdev)
14428 {
14429         struct net_device *dev = pci_get_drvdata(pdev);
14430         struct bnx2x *bp;
14431
14432         if (!dev)
14433                 return;
14434
14435         bp = netdev_priv(dev);
14436         if (!bp)
14437                 return;
14438
14439         rtnl_lock();
14440         netif_device_detach(dev);
14441         rtnl_unlock();
14442
14443         /* Don't remove the netdevice, as there are scenarios which will cause
14444          * the kernel to hang, e.g., when trying to remove bnx2i while the
14445          * rootfs is mounted from SAN.
14446          */
14447         __bnx2x_remove(pdev, dev, bp, false);
14448 }
14449
14450 static struct pci_driver bnx2x_pci_driver = {
14451         .name        = DRV_MODULE_NAME,
14452         .id_table    = bnx2x_pci_tbl,
14453         .probe       = bnx2x_init_one,
14454         .remove      = bnx2x_remove_one,
14455         .suspend     = bnx2x_suspend,
14456         .resume      = bnx2x_resume,
14457         .err_handler = &bnx2x_err_handler,
14458 #ifdef CONFIG_BNX2X_SRIOV
14459         .sriov_configure = bnx2x_sriov_configure,
14460 #endif
14461         .shutdown    = bnx2x_shutdown,
14462 };
14463
14464 static int __init bnx2x_init(void)
14465 {
14466         int ret;
14467
14468         pr_info("%s", version);
14469
14470         bnx2x_wq = create_singlethread_workqueue("bnx2x");
14471         if (bnx2x_wq == NULL) {
14472                 pr_err("Cannot create workqueue\n");
14473                 return -ENOMEM;
14474         }
14475         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14476         if (!bnx2x_iov_wq) {
14477                 pr_err("Cannot create iov workqueue\n");
14478                 destroy_workqueue(bnx2x_wq);
14479                 return -ENOMEM;
14480         }
14481
14482         ret = pci_register_driver(&bnx2x_pci_driver);
14483         if (ret) {
14484                 pr_err("Cannot register driver\n");
14485                 destroy_workqueue(bnx2x_wq);
14486                 destroy_workqueue(bnx2x_iov_wq);
14487         }
14488         return ret;
14489 }
14490
14491 static void __exit bnx2x_cleanup(void)
14492 {
14493         struct list_head *pos, *q;
14494
14495         pci_unregister_driver(&bnx2x_pci_driver);
14496
14497         destroy_workqueue(bnx2x_wq);
14498         destroy_workqueue(bnx2x_iov_wq);
14499
14500         /* Free globally allocated resources */
14501         list_for_each_safe(pos, q, &bnx2x_prev_list) {
14502                 struct bnx2x_prev_path_list *tmp =
14503                         list_entry(pos, struct bnx2x_prev_path_list, list);
14504                 list_del(pos);
14505                 kfree(tmp);
14506         }
14507 }
14508
14509 void bnx2x_notify_link_changed(struct bnx2x *bp)
14510 {
14511         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14512 }
14513
14514 module_init(bnx2x_init);
14515 module_exit(bnx2x_cleanup);
14516
14517 /**
14518  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14519  *
14520  * @bp:         driver handle
14521  * @set:        set or clear the CAM entry
14522  *
14523  * This function will wait until the ramrod completion returns.
14524  * Return 0 if success, -ENODEV if ramrod doesn't return.
14525  */
14526 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14527 {
14528         unsigned long ramrod_flags = 0;
14529
14530         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14531         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14532                                  &bp->iscsi_l2_mac_obj, true,
14533                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14534 }
14535
14536 /* count denotes the number of new completions we have seen */
14537 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14538 {
14539         struct eth_spe *spe;
14540         int cxt_index, cxt_offset;
14541
14542 #ifdef BNX2X_STOP_ON_ERROR
14543         if (unlikely(bp->panic))
14544                 return;
14545 #endif
14546
14547         spin_lock_bh(&bp->spq_lock);
14548         BUG_ON(bp->cnic_spq_pending < count);
14549         bp->cnic_spq_pending -= count;
14550
14551         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14552                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14553                                 & SPE_HDR_CONN_TYPE) >>
14554                                 SPE_HDR_CONN_TYPE_SHIFT;
14555                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14556                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14557
14558                 /* Set validation for iSCSI L2 client before sending SETUP
14559                  *  ramrod
14560                  */
14561                 if (type == ETH_CONNECTION_TYPE) {
14562                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14563                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14564                                         ILT_PAGE_CIDS;
14565                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14566                                         (cxt_index * ILT_PAGE_CIDS);
14567                                 bnx2x_set_ctx_validation(bp,
14568                                         &bp->context[cxt_index].
14569                                                          vcxt[cxt_offset].eth,
14570                                         BNX2X_ISCSI_ETH_CID(bp));
14571                         }
14572                 }
14573
14574                 /*
14575                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14576                  * and in the air. We also check that number of outstanding
14577                  * COMMON ramrods is not more than the EQ and SPQ can
14578                  * accommodate.
14579                  */
14580                 if (type == ETH_CONNECTION_TYPE) {
14581                         if (!atomic_read(&bp->cq_spq_left))
14582                                 break;
14583                         else
14584                                 atomic_dec(&bp->cq_spq_left);
14585                 } else if (type == NONE_CONNECTION_TYPE) {
14586                         if (!atomic_read(&bp->eq_spq_left))
14587                                 break;
14588                         else
14589                                 atomic_dec(&bp->eq_spq_left);
14590                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14591                            (type == FCOE_CONNECTION_TYPE)) {
14592                         if (bp->cnic_spq_pending >=
14593                             bp->cnic_eth_dev.max_kwqe_pending)
14594                                 break;
14595                         else
14596                                 bp->cnic_spq_pending++;
14597                 } else {
14598                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14599                         bnx2x_panic();
14600                         break;
14601                 }
14602
14603                 spe = bnx2x_sp_get_next(bp);
14604                 *spe = *bp->cnic_kwq_cons;
14605
14606                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14607                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14608
14609                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14610                         bp->cnic_kwq_cons = bp->cnic_kwq;
14611                 else
14612                         bp->cnic_kwq_cons++;
14613         }
14614         bnx2x_sp_prod_update(bp);
14615         spin_unlock_bh(&bp->spq_lock);
14616 }
14617
14618 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14619                                struct kwqe_16 *kwqes[], u32 count)
14620 {
14621         struct bnx2x *bp = netdev_priv(dev);
14622         int i;
14623
14624 #ifdef BNX2X_STOP_ON_ERROR
14625         if (unlikely(bp->panic)) {
14626                 BNX2X_ERR("Can't post to SP queue while panic\n");
14627                 return -EIO;
14628         }
14629 #endif
14630
14631         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14632             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14633                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14634                 return -EAGAIN;
14635         }
14636
14637         spin_lock_bh(&bp->spq_lock);
14638
14639         for (i = 0; i < count; i++) {
14640                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14641
14642                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14643                         break;
14644
14645                 *bp->cnic_kwq_prod = *spe;
14646
14647                 bp->cnic_kwq_pending++;
14648
14649                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14650                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14651                    spe->data.update_data_addr.hi,
14652                    spe->data.update_data_addr.lo,
14653                    bp->cnic_kwq_pending);
14654
14655                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14656                         bp->cnic_kwq_prod = bp->cnic_kwq;
14657                 else
14658                         bp->cnic_kwq_prod++;
14659         }
14660
14661         spin_unlock_bh(&bp->spq_lock);
14662
14663         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14664                 bnx2x_cnic_sp_post(bp, 0);
14665
14666         return i;
14667 }
14668
14669 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14670 {
14671         struct cnic_ops *c_ops;
14672         int rc = 0;
14673
14674         mutex_lock(&bp->cnic_mutex);
14675         c_ops = rcu_dereference_protected(bp->cnic_ops,
14676                                           lockdep_is_held(&bp->cnic_mutex));
14677         if (c_ops)
14678                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14679         mutex_unlock(&bp->cnic_mutex);
14680
14681         return rc;
14682 }
14683
14684 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14685 {
14686         struct cnic_ops *c_ops;
14687         int rc = 0;
14688
14689         rcu_read_lock();
14690         c_ops = rcu_dereference(bp->cnic_ops);
14691         if (c_ops)
14692                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14693         rcu_read_unlock();
14694
14695         return rc;
14696 }
14697
14698 /*
14699  * for commands that have no data
14700  */
14701 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14702 {
14703         struct cnic_ctl_info ctl = {0};
14704
14705         ctl.cmd = cmd;
14706
14707         return bnx2x_cnic_ctl_send(bp, &ctl);
14708 }
14709
14710 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14711 {
14712         struct cnic_ctl_info ctl = {0};
14713
14714         /* first we tell CNIC and only then we count this as a completion */
14715         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14716         ctl.data.comp.cid = cid;
14717         ctl.data.comp.error = err;
14718
14719         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14720         bnx2x_cnic_sp_post(bp, 0);
14721 }
14722
14723 /* Called with netif_addr_lock_bh() taken.
14724  * Sets an rx_mode config for an iSCSI ETH client.
14725  * Doesn't block.
14726  * Completion should be checked outside.
14727  */
14728 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14729 {
14730         unsigned long accept_flags = 0, ramrod_flags = 0;
14731         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14732         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14733
14734         if (start) {
14735                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14736                  * because it's the only way for UIO Queue to accept
14737                  * multicasts (in non-promiscuous mode only one Queue per
14738                  * function will receive multicast packets (leading in our
14739                  * case).
14740                  */
14741                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14742                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14743                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14744                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14745
14746                 /* Clear STOP_PENDING bit if START is requested */
14747                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14748
14749                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14750         } else
14751                 /* Clear START_PENDING bit if STOP is requested */
14752                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14753
14754         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14755                 set_bit(sched_state, &bp->sp_state);
14756         else {
14757                 __set_bit(RAMROD_RX, &ramrod_flags);
14758                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14759                                     ramrod_flags);
14760         }
14761 }
14762
14763 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14764 {
14765         struct bnx2x *bp = netdev_priv(dev);
14766         int rc = 0;
14767
14768         switch (ctl->cmd) {
14769         case DRV_CTL_CTXTBL_WR_CMD: {
14770                 u32 index = ctl->data.io.offset;
14771                 dma_addr_t addr = ctl->data.io.dma_addr;
14772
14773                 bnx2x_ilt_wr(bp, index, addr);
14774                 break;
14775         }
14776
14777         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14778                 int count = ctl->data.credit.credit_count;
14779
14780                 bnx2x_cnic_sp_post(bp, count);
14781                 break;
14782         }
14783
14784         /* rtnl_lock is held.  */
14785         case DRV_CTL_START_L2_CMD: {
14786                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14787                 unsigned long sp_bits = 0;
14788
14789                 /* Configure the iSCSI classification object */
14790                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14791                                    cp->iscsi_l2_client_id,
14792                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14793                                    bnx2x_sp(bp, mac_rdata),
14794                                    bnx2x_sp_mapping(bp, mac_rdata),
14795                                    BNX2X_FILTER_MAC_PENDING,
14796                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14797                                    &bp->macs_pool);
14798
14799                 /* Set iSCSI MAC address */
14800                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14801                 if (rc)
14802                         break;
14803
14804                 barrier();
14805
14806                 /* Start accepting on iSCSI L2 ring */
14807
14808                 netif_addr_lock_bh(dev);
14809                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14810                 netif_addr_unlock_bh(dev);
14811
14812                 /* bits to wait on */
14813                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14814                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14815
14816                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14817                         BNX2X_ERR("rx_mode completion timed out!\n");
14818
14819                 break;
14820         }
14821
14822         /* rtnl_lock is held.  */
14823         case DRV_CTL_STOP_L2_CMD: {
14824                 unsigned long sp_bits = 0;
14825
14826                 /* Stop accepting on iSCSI L2 ring */
14827                 netif_addr_lock_bh(dev);
14828                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14829                 netif_addr_unlock_bh(dev);
14830
14831                 /* bits to wait on */
14832                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14833                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14834
14835                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14836                         BNX2X_ERR("rx_mode completion timed out!\n");
14837
14838                 barrier();
14839
14840                 /* Unset iSCSI L2 MAC */
14841                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14842                                         BNX2X_ISCSI_ETH_MAC, true);
14843                 break;
14844         }
14845         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14846                 int count = ctl->data.credit.credit_count;
14847
14848                 smp_mb__before_atomic();
14849                 atomic_add(count, &bp->cq_spq_left);
14850                 smp_mb__after_atomic();
14851                 break;
14852         }
14853         case DRV_CTL_ULP_REGISTER_CMD: {
14854                 int ulp_type = ctl->data.register_data.ulp_type;
14855
14856                 if (CHIP_IS_E3(bp)) {
14857                         int idx = BP_FW_MB_IDX(bp);
14858                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14859                         int path = BP_PATH(bp);
14860                         int port = BP_PORT(bp);
14861                         int i;
14862                         u32 scratch_offset;
14863                         u32 *host_addr;
14864
14865                         /* first write capability to shmem2 */
14866                         if (ulp_type == CNIC_ULP_ISCSI)
14867                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14868                         else if (ulp_type == CNIC_ULP_FCOE)
14869                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14870                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14871
14872                         if ((ulp_type != CNIC_ULP_FCOE) ||
14873                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14874                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14875                                 break;
14876
14877                         /* if reached here - should write fcoe capabilities */
14878                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14879                         if (!scratch_offset)
14880                                 break;
14881                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14882                                                    fcoe_features[path][port]);
14883                         host_addr = (u32 *) &(ctl->data.register_data.
14884                                               fcoe_features);
14885                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14886                              i += 4)
14887                                 REG_WR(bp, scratch_offset + i,
14888                                        *(host_addr + i/4));
14889                 }
14890                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14891                 break;
14892         }
14893
14894         case DRV_CTL_ULP_UNREGISTER_CMD: {
14895                 int ulp_type = ctl->data.ulp_type;
14896
14897                 if (CHIP_IS_E3(bp)) {
14898                         int idx = BP_FW_MB_IDX(bp);
14899                         u32 cap;
14900
14901                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14902                         if (ulp_type == CNIC_ULP_ISCSI)
14903                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14904                         else if (ulp_type == CNIC_ULP_FCOE)
14905                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14906                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14907                 }
14908                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14909                 break;
14910         }
14911
14912         default:
14913                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14914                 rc = -EINVAL;
14915         }
14916
14917         /* For storage-only interfaces, change driver state */
14918         if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14919                 switch (ctl->drv_state) {
14920                 case DRV_NOP:
14921                         break;
14922                 case DRV_ACTIVE:
14923                         bnx2x_set_os_driver_state(bp,
14924                                                   OS_DRIVER_STATE_ACTIVE);
14925                         break;
14926                 case DRV_INACTIVE:
14927                         bnx2x_set_os_driver_state(bp,
14928                                                   OS_DRIVER_STATE_DISABLED);
14929                         break;
14930                 case DRV_UNLOADED:
14931                         bnx2x_set_os_driver_state(bp,
14932                                                   OS_DRIVER_STATE_NOT_LOADED);
14933                         break;
14934                 default:
14935                 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14936                 }
14937         }
14938
14939         return rc;
14940 }
14941
14942 static int bnx2x_get_fc_npiv(struct net_device *dev,
14943                              struct cnic_fc_npiv_tbl *cnic_tbl)
14944 {
14945         struct bnx2x *bp = netdev_priv(dev);
14946         struct bdn_fc_npiv_tbl *tbl = NULL;
14947         u32 offset, entries;
14948         int rc = -EINVAL;
14949         int i;
14950
14951         if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14952                 goto out;
14953
14954         DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14955
14956         tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14957         if (!tbl) {
14958                 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14959                 goto out;
14960         }
14961
14962         offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14963         if (!offset) {
14964                 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14965                 goto out;
14966         }
14967         DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14968
14969         /* Read the table contents from nvram */
14970         if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14971                 BNX2X_ERR("Failed to read FC-NPIV table\n");
14972                 goto out;
14973         }
14974
14975         /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14976          * the number of entries back to cpu endianness.
14977          */
14978         entries = tbl->fc_npiv_cfg.num_of_npiv;
14979         entries = (__force u32)be32_to_cpu((__force __be32)entries);
14980         tbl->fc_npiv_cfg.num_of_npiv = entries;
14981
14982         if (!tbl->fc_npiv_cfg.num_of_npiv) {
14983                 DP(BNX2X_MSG_MCP,
14984                    "No FC-NPIV table [valid, simply not present]\n");
14985                 goto out;
14986         } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14987                 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14988                           tbl->fc_npiv_cfg.num_of_npiv);
14989                 goto out;
14990         } else {
14991                 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14992                    tbl->fc_npiv_cfg.num_of_npiv);
14993         }
14994
14995         /* Copy the data into cnic-provided struct */
14996         cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14997         for (i = 0; i < cnic_tbl->count; i++) {
14998                 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14999                 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
15000         }
15001
15002         rc = 0;
15003 out:
15004         kfree(tbl);
15005         return rc;
15006 }
15007
15008 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
15009 {
15010         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15011
15012         if (bp->flags & USING_MSIX_FLAG) {
15013                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
15014                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
15015                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
15016         } else {
15017                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
15018                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
15019         }
15020         if (!CHIP_IS_E1x(bp))
15021                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
15022         else
15023                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
15024
15025         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
15026         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
15027         cp->irq_arr[1].status_blk = bp->def_status_blk;
15028         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
15029         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
15030
15031         cp->num_irq = 2;
15032 }
15033
15034 void bnx2x_setup_cnic_info(struct bnx2x *bp)
15035 {
15036         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15037
15038         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15039                              bnx2x_cid_ilt_lines(bp);
15040         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15041         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15042         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15043
15044         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
15045            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
15046            cp->iscsi_l2_cid);
15047
15048         if (NO_ISCSI_OOO(bp))
15049                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15050 }
15051
15052 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
15053                                void *data)
15054 {
15055         struct bnx2x *bp = netdev_priv(dev);
15056         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15057         int rc;
15058
15059         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
15060
15061         if (ops == NULL) {
15062                 BNX2X_ERR("NULL ops received\n");
15063                 return -EINVAL;
15064         }
15065
15066         if (!CNIC_SUPPORT(bp)) {
15067                 BNX2X_ERR("Can't register CNIC when not supported\n");
15068                 return -EOPNOTSUPP;
15069         }
15070
15071         if (!CNIC_LOADED(bp)) {
15072                 rc = bnx2x_load_cnic(bp);
15073                 if (rc) {
15074                         BNX2X_ERR("CNIC-related load failed\n");
15075                         return rc;
15076                 }
15077         }
15078
15079         bp->cnic_enabled = true;
15080
15081         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
15082         if (!bp->cnic_kwq)
15083                 return -ENOMEM;
15084
15085         bp->cnic_kwq_cons = bp->cnic_kwq;
15086         bp->cnic_kwq_prod = bp->cnic_kwq;
15087         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
15088
15089         bp->cnic_spq_pending = 0;
15090         bp->cnic_kwq_pending = 0;
15091
15092         bp->cnic_data = data;
15093
15094         cp->num_irq = 0;
15095         cp->drv_state |= CNIC_DRV_STATE_REGD;
15096         cp->iro_arr = bp->iro_arr;
15097
15098         bnx2x_setup_cnic_irq_info(bp);
15099
15100         rcu_assign_pointer(bp->cnic_ops, ops);
15101
15102         /* Schedule driver to read CNIC driver versions */
15103         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15104
15105         return 0;
15106 }
15107
15108 static int bnx2x_unregister_cnic(struct net_device *dev)
15109 {
15110         struct bnx2x *bp = netdev_priv(dev);
15111         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15112
15113         mutex_lock(&bp->cnic_mutex);
15114         cp->drv_state = 0;
15115         RCU_INIT_POINTER(bp->cnic_ops, NULL);
15116         mutex_unlock(&bp->cnic_mutex);
15117         synchronize_rcu();
15118         bp->cnic_enabled = false;
15119         kfree(bp->cnic_kwq);
15120         bp->cnic_kwq = NULL;
15121
15122         return 0;
15123 }
15124
15125 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
15126 {
15127         struct bnx2x *bp = netdev_priv(dev);
15128         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15129
15130         /* If both iSCSI and FCoE are disabled - return NULL in
15131          * order to indicate CNIC that it should not try to work
15132          * with this device.
15133          */
15134         if (NO_ISCSI(bp) && NO_FCOE(bp))
15135                 return NULL;
15136
15137         cp->drv_owner = THIS_MODULE;
15138         cp->chip_id = CHIP_ID(bp);
15139         cp->pdev = bp->pdev;
15140         cp->io_base = bp->regview;
15141         cp->io_base2 = bp->doorbells;
15142         cp->max_kwqe_pending = 8;
15143         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
15144         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15145                              bnx2x_cid_ilt_lines(bp);
15146         cp->ctx_tbl_len = CNIC_ILT_LINES;
15147         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15148         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15149         cp->drv_ctl = bnx2x_drv_ctl;
15150         cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15151         cp->drv_register_cnic = bnx2x_register_cnic;
15152         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15153         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15154         cp->iscsi_l2_client_id =
15155                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15156         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15157
15158         if (NO_ISCSI_OOO(bp))
15159                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15160
15161         if (NO_ISCSI(bp))
15162                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15163
15164         if (NO_FCOE(bp))
15165                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15166
15167         BNX2X_DEV_INFO(
15168                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15169            cp->ctx_blk_size,
15170            cp->ctx_tbl_offset,
15171            cp->ctx_tbl_len,
15172            cp->starting_cid);
15173         return cp;
15174 }
15175
15176 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15177 {
15178         struct bnx2x *bp = fp->bp;
15179         u32 offset = BAR_USTRORM_INTMEM;
15180
15181         if (IS_VF(bp))
15182                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15183         else if (!CHIP_IS_E1x(bp))
15184                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15185         else
15186                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15187
15188         return offset;
15189 }
15190
15191 /* called only on E1H or E2.
15192  * When pretending to be PF, the pretend value is the function number 0...7
15193  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15194  * combination
15195  */
15196 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15197 {
15198         u32 pretend_reg;
15199
15200         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15201                 return -1;
15202
15203         /* get my own pretend register */
15204         pretend_reg = bnx2x_get_pretend_reg(bp);
15205         REG_WR(bp, pretend_reg, pretend_func_val);
15206         REG_RD(bp, pretend_reg);
15207         return 0;
15208 }
15209
15210 static void bnx2x_ptp_task(struct work_struct *work)
15211 {
15212         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15213         int port = BP_PORT(bp);
15214         u32 val_seq;
15215         u64 timestamp, ns;
15216         struct skb_shared_hwtstamps shhwtstamps;
15217         bool bail = true;
15218         int i;
15219
15220         /* FW may take a while to complete timestamping; try a bit and if it's
15221          * still not complete, may indicate an error state - bail out then.
15222          */
15223         for (i = 0; i < 10; i++) {
15224                 /* Read Tx timestamp registers */
15225                 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15226                                  NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15227                 if (val_seq & 0x10000) {
15228                         bail = false;
15229                         break;
15230                 }
15231                 msleep(1 << i);
15232         }
15233
15234         if (!bail) {
15235                 /* There is a valid timestamp value */
15236                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15237                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15238                 timestamp <<= 32;
15239                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15240                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15241                 /* Reset timestamp register to allow new timestamp */
15242                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15243                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15244                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15245
15246                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15247                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15248                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15249
15250                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15251                    timestamp, ns);
15252         } else {
15253                 DP(BNX2X_MSG_PTP,
15254                    "Tx timestamp is not recorded (register read=%u)\n",
15255                    val_seq);
15256                 bp->eth_stats.ptp_skip_tx_ts++;
15257         }
15258
15259         dev_kfree_skb_any(bp->ptp_tx_skb);
15260         bp->ptp_tx_skb = NULL;
15261 }
15262
15263 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15264 {
15265         int port = BP_PORT(bp);
15266         u64 timestamp, ns;
15267
15268         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15269                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15270         timestamp <<= 32;
15271         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15272                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15273
15274         /* Reset timestamp register to allow new timestamp */
15275         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15276                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15277
15278         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15279
15280         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15281
15282         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15283            timestamp, ns);
15284 }
15285
15286 /* Read the PHC */
15287 static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15288 {
15289         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15290         int port = BP_PORT(bp);
15291         u32 wb_data[2];
15292         u64 phc_cycles;
15293
15294         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15295                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15296         phc_cycles = wb_data[1];
15297         phc_cycles = (phc_cycles << 32) + wb_data[0];
15298
15299         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15300
15301         return phc_cycles;
15302 }
15303
15304 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15305 {
15306         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15307         bp->cyclecounter.read = bnx2x_cyclecounter_read;
15308         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15309         bp->cyclecounter.shift = 0;
15310         bp->cyclecounter.mult = 1;
15311 }
15312
15313 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15314 {
15315         struct bnx2x_func_state_params func_params = {NULL};
15316         struct bnx2x_func_set_timesync_params *set_timesync_params =
15317                 &func_params.params.set_timesync;
15318
15319         /* Prepare parameters for function state transitions */
15320         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15321         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15322
15323         func_params.f_obj = &bp->func_obj;
15324         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15325
15326         /* Function parameters */
15327         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15328         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15329
15330         return bnx2x_func_state_change(bp, &func_params);
15331 }
15332
15333 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15334 {
15335         struct bnx2x_queue_state_params q_params;
15336         int rc, i;
15337
15338         /* send queue update ramrod to enable PTP packets */
15339         memset(&q_params, 0, sizeof(q_params));
15340         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15341         q_params.cmd = BNX2X_Q_CMD_UPDATE;
15342         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15343                   &q_params.params.update.update_flags);
15344         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15345                   &q_params.params.update.update_flags);
15346
15347         /* send the ramrod on all the queues of the PF */
15348         for_each_eth_queue(bp, i) {
15349                 struct bnx2x_fastpath *fp = &bp->fp[i];
15350
15351                 /* Set the appropriate Queue object */
15352                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15353
15354                 /* Update the Queue state */
15355                 rc = bnx2x_queue_state_change(bp, &q_params);
15356                 if (rc) {
15357                         BNX2X_ERR("Failed to enable PTP packets\n");
15358                         return rc;
15359                 }
15360         }
15361
15362         return 0;
15363 }
15364
15365 #define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5
15366 #define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB
15367 #define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15368 #define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15369 #define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE)
15370 #define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE)
15371 #define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA)
15372 #define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE)
15373 #define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF)
15374 #define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF)
15375 #define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15376 #define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15377
15378 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15379 {
15380         int port = BP_PORT(bp);
15381         u32 param, rule;
15382         int rc;
15383
15384         if (!bp->hwtstamp_ioctl_called)
15385                 return 0;
15386
15387         param = port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15388                 NIG_REG_P0_TLLH_PTP_PARAM_MASK;
15389         rule = port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15390                 NIG_REG_P0_TLLH_PTP_RULE_MASK;
15391         switch (bp->tx_type) {
15392         case HWTSTAMP_TX_ON:
15393                 bp->flags |= TX_TIMESTAMPING_EN;
15394                 REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK);
15395                 REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK);
15396                 break;
15397         case HWTSTAMP_TX_ONESTEP_SYNC:
15398                 BNX2X_ERR("One-step timestamping is not supported\n");
15399                 return -ERANGE;
15400         }
15401
15402         param = port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15403                 NIG_REG_P0_LLH_PTP_PARAM_MASK;
15404         rule = port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15405                 NIG_REG_P0_LLH_PTP_RULE_MASK;
15406         switch (bp->rx_filter) {
15407         case HWTSTAMP_FILTER_NONE:
15408                 break;
15409         case HWTSTAMP_FILTER_ALL:
15410         case HWTSTAMP_FILTER_SOME:
15411         case HWTSTAMP_FILTER_NTP_ALL:
15412                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15413                 break;
15414         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15415         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15416         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15417                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15418                 /* Initialize PTP detection for UDP/IPv4 events */
15419                 REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK);
15420                 REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK);
15421                 break;
15422         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15423         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15424         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15425                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15426                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15427                 REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK);
15428                 REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK);
15429                 break;
15430         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15431         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15432         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15433                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15434                 /* Initialize PTP detection L2 events */
15435                 REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK);
15436                 REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK);
15437
15438                 break;
15439         case HWTSTAMP_FILTER_PTP_V2_EVENT:
15440         case HWTSTAMP_FILTER_PTP_V2_SYNC:
15441         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15442                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15443                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15444                 REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK);
15445                 REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK);
15446                 break;
15447         }
15448
15449         /* Indicate to FW that this PF expects recorded PTP packets */
15450         rc = bnx2x_enable_ptp_packets(bp);
15451         if (rc)
15452                 return rc;
15453
15454         /* Enable sending PTP packets to host */
15455         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15456                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15457
15458         return 0;
15459 }
15460
15461 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15462 {
15463         struct hwtstamp_config config;
15464         int rc;
15465
15466         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15467
15468         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15469                 return -EFAULT;
15470
15471         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15472            config.tx_type, config.rx_filter);
15473
15474         if (config.flags) {
15475                 BNX2X_ERR("config.flags is reserved for future use\n");
15476                 return -EINVAL;
15477         }
15478
15479         bp->hwtstamp_ioctl_called = 1;
15480         bp->tx_type = config.tx_type;
15481         bp->rx_filter = config.rx_filter;
15482
15483         rc = bnx2x_configure_ptp_filters(bp);
15484         if (rc)
15485                 return rc;
15486
15487         config.rx_filter = bp->rx_filter;
15488
15489         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15490                 -EFAULT : 0;
15491 }
15492
15493 /* Configures HW for PTP */
15494 static int bnx2x_configure_ptp(struct bnx2x *bp)
15495 {
15496         int rc, port = BP_PORT(bp);
15497         u32 wb_data[2];
15498
15499         /* Reset PTP event detection rules - will be configured in the IOCTL */
15500         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15501                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15502         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15503                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15504         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15505                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15506         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15507                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15508
15509         /* Disable PTP packets to host - will be configured in the IOCTL*/
15510         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15511                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15512
15513         /* Enable the PTP feature */
15514         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15515                NIG_REG_P0_PTP_EN, 0x3F);
15516
15517         /* Enable the free-running counter */
15518         wb_data[0] = 0;
15519         wb_data[1] = 0;
15520         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15521
15522         /* Reset drift register (offset register is not reset) */
15523         rc = bnx2x_send_reset_timesync_ramrod(bp);
15524         if (rc) {
15525                 BNX2X_ERR("Failed to reset PHC drift register\n");
15526                 return -EFAULT;
15527         }
15528
15529         /* Reset possibly old timestamps */
15530         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15531                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15532         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15533                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15534
15535         return 0;
15536 }
15537
15538 /* Called during load, to initialize PTP-related stuff */
15539 void bnx2x_init_ptp(struct bnx2x *bp)
15540 {
15541         int rc;
15542
15543         /* Configure PTP in HW */
15544         rc = bnx2x_configure_ptp(bp);
15545         if (rc) {
15546                 BNX2X_ERR("Stopping PTP initialization\n");
15547                 return;
15548         }
15549
15550         /* Init work queue for Tx timestamping */
15551         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15552
15553         /* Init cyclecounter and timecounter. This is done only in the first
15554          * load. If done in every load, PTP application will fail when doing
15555          * unload / load (e.g. MTU change) while it is running.
15556          */
15557         if (!bp->timecounter_init_done) {
15558                 bnx2x_init_cyclecounter(bp);
15559                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15560                                  ktime_to_ns(ktime_get_real()));
15561                 bp->timecounter_init_done = 1;
15562         }
15563
15564         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15565 }