drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
  11
  12 #include "../aq_hw.h"
  13 #include "../aq_hw_utils.h"
  14 #include "../aq_ring.h"
  15 #include "../aq_nic.h"
  16 #include "hw_atl_b0.h"
  17 #include "hw_atl_utils.h"
  18 #include "hw_atl_llh.h"
  19 #include "hw_atl_b0_internal.h"
  20 #include "hw_atl_llh_internal.h"
  21
  22 #define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
  23         .is_64_dma = true,                \
  24         .msix_irqs = 4U,                  \
  25         .irq_mask = ~0U,                  \
  26         .vecs = HW_ATL_B0_RSS_MAX,        \
  27         .tcs = HW_ATL_B0_TC_MAX,          \
  28         .rxd_alignment = 1U,              \
  29         .rxd_size = HW_ATL_B0_RXD_SIZE,   \
  30         .rxds_max = HW_ATL_B0_MAX_RXD,    \
  31         .rxds_min = HW_ATL_B0_MIN_RXD,    \
  32         .txd_alignment = 1U,              \
  33         .txd_size = HW_ATL_B0_TXD_SIZE,   \
  34         .txds_max = HW_ATL_B0_MAX_TXD,    \
  35         .txds_min = HW_ATL_B0_MIN_TXD,    \
  36         .txhwb_alignment = 4096U,         \
  37         .tx_rings = HW_ATL_B0_TX_RINGS,   \
  38         .rx_rings = HW_ATL_B0_RX_RINGS,   \
  39         .hw_features = NETIF_F_HW_CSUM |  \
  40                         NETIF_F_RXCSUM |  \
  41                         NETIF_F_RXHASH |  \
  42                         NETIF_F_SG |      \
  43                         NETIF_F_TSO |     \
  44                         NETIF_F_LRO,      \
  45         .hw_priv_flags = IFF_UNICAST_FLT, \
  46         .flow_control = true,             \
  47         .mtu = HW_ATL_B0_MTU_JUMBO,       \
  48         .mac_regs_count = 88,             \
  49         .hw_alive_check_addr = 0x10U
  50
  51 const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
  52         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  53         .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
  54         .link_speed_msk = AQ_NIC_RATE_10G |
  55                           AQ_NIC_RATE_5G |
  56                           AQ_NIC_RATE_2GS |
  57                           AQ_NIC_RATE_1G |
  58                           AQ_NIC_RATE_100M,
  59 };
  60
  61 const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
  62         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  63         .media_type = AQ_HW_MEDIA_TYPE_TP,
  64         .link_speed_msk = AQ_NIC_RATE_10G |
  65                           AQ_NIC_RATE_5G |
  66                           AQ_NIC_RATE_2GS |
  67                           AQ_NIC_RATE_1G |
  68                           AQ_NIC_RATE_100M,
  69 };
  70
  71 const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
  72         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  73         .media_type = AQ_HW_MEDIA_TYPE_TP,
  74         .link_speed_msk = AQ_NIC_RATE_5G |
  75                           AQ_NIC_RATE_2GS |
  76                           AQ_NIC_RATE_1G |
  77                           AQ_NIC_RATE_100M,
  78 };
  79
  80 const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
  81         DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
  82         .media_type = AQ_HW_MEDIA_TYPE_TP,
  83         .link_speed_msk = AQ_NIC_RATE_2GS |
  84                           AQ_NIC_RATE_1G |
  85                           AQ_NIC_RATE_100M,
  86 };
  87
  88 static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
  89 {
  90         int err = 0;
  91
  92         err = hw_atl_utils_soft_reset(self);
  93         if (err)
  94                 return err;
  95
  96         self->aq_fw_ops->set_state(self, MPI_RESET);
  97
  98         err = aq_hw_err_from_flags(self);
  99
 100         return err;
 101 }
 102
 103 static int hw_atl_b0_set_fc(struct aq_hw_s *self, u32 fc, u32 tc)
 104 {
 105         hw_atl_rpb_rx_xoff_en_per_tc_set(self, !!(fc & AQ_NIC_FC_RX), tc);
 106         return 0;
 107 }
 108
 109 static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
 110 {
 111         u32 tc = 0U;
 112         u32 buff_size = 0U;
 113         unsigned int i_priority = 0U;
 114
 115         /* TPS Descriptor rate init */
 116         hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
 117         hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
 118
 119         /* TPS VM init */
 120         hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
 121
 122         /* TPS TC credits init */
 123         hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
 124         hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
 125
 126         hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
 127         hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
 128         hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
 129         hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
 130
 131         /* Tx buf size */
 132         buff_size = HW_ATL_B0_TXBUF_MAX;
 133
 134         hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 135         hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
 136                                                    (buff_size *
 137                                                    (1024 / 32U) * 66U) /
 138                                                    100U, tc);
 139         hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
 140                                                    (buff_size *
 141                                                    (1024 / 32U) * 50U) /
 142                                                    100U, tc);
 143
 144         /* QoS Rx buf size per TC */
 145         tc = 0;
 146         buff_size = HW_ATL_B0_RXBUF_MAX;
 147
 148         hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 149         hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
 150                                                    (buff_size *
 151                                                    (1024U / 32U) * 66U) /
 152                                                    100U, tc);
 153         hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
 154                                                    (buff_size *
 155                                                    (1024U / 32U) * 50U) /
 156                                                    100U, tc);
 157
 158         hw_atl_b0_set_fc(self, self->aq_nic_cfg->flow_control, tc);
 159
 160         /* QoS 802.1p priority -> TC mapping */
 161         for (i_priority = 8U; i_priority--;)
 162                 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
 163
 164         return aq_hw_err_from_flags(self);
 165 }
 166
 167 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
 168                                      struct aq_rss_parameters *rss_params)
 169 {
 170         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 171         int err = 0;
 172         unsigned int i = 0U;
 173         unsigned int addr = 0U;
 174
 175         for (i = 10, addr = 0U; i--; ++addr) {
 176                 u32 key_data = cfg->is_rss ?
 177                         __swab32(rss_params->hash_secret_key[i]) : 0U;
 178                 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
 179                 hw_atl_rpf_rss_key_addr_set(self, addr);
 180                 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
 181                 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
 182                                1000U, 10U);
 183                 if (err < 0)
 184                         goto err_exit;
 185         }
 186
 187         err = aq_hw_err_from_flags(self);
 188
 189 err_exit:
 190         return err;
 191 }
 192
 193 static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
 194                                 struct aq_rss_parameters *rss_params)
 195 {
 196         u8 *indirection_table = rss_params->indirection_table;
 197         u32 i = 0U;
 198         u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
 199         int err = 0;
 200         u16 bitary[(HW_ATL_B0_RSS_REDIRECTION_MAX *
 201                                         HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
 202
 203         memset(bitary, 0, sizeof(bitary));
 204
 205         for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
 206                 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
 207                         ((indirection_table[i] % num_rss_queues) <<
 208                         ((i * 3U) & 0xFU));
 209         }
 210
 211         for (i = ARRAY_SIZE(bitary); i--;) {
 212                 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
 213                 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
 214                 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
 215                 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
 216                                1000U, 10U);
 217                 if (err < 0)
 218                         goto err_exit;
 219         }
 220
 221         err = aq_hw_err_from_flags(self);
 222
 223 err_exit:
 224         return err;
 225 }
 226
 227 static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
 228                                     struct aq_nic_cfg_s *aq_nic_cfg)
 229 {
 230         unsigned int i;
 231
 232         /* TX checksums offloads*/
 233         hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
 234         hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
 235
 236         /* RX checksums offloads*/
 237         hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
 238         hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
 239
 240         /* LSO offloads*/
 241         hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
 242
 243 /* LRO offloads */
 244         {
 245                 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
 246                         ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
 247                         ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
 248
 249                 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
 250                         hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);
 251
 252                 hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
 253                 hw_atl_rpo_lro_inactive_interval_set(self, 0);
 254                 hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
 255
 256                 hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
 257
 258                 hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
 259
 260                 hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
 261
 262                 hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
 263
 264                 hw_atl_rpo_lro_pkt_lim_set(self, 1U);
 265
 266                 hw_atl_rpo_lro_en_set(self,
 267                                       aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
 268         }
 269         return aq_hw_err_from_flags(self);
 270 }
 271
 272 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
 273 {
 274         hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
 275         hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
 276         hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
 277
 278         /* Tx interrupts */
 279         hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 280
 281         /* misc */
 282         aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
 283                         0x00010000U : 0x00000000U);
 284         hw_atl_tdm_tx_dca_en_set(self, 0U);
 285         hw_atl_tdm_tx_dca_mode_set(self, 0U);
 286
 287         hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
 288
 289         return aq_hw_err_from_flags(self);
 290 }
 291
 292 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
 293 {
 294         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 295         int i;
 296
 297         /* Rx TC/RSS number config */
 298         hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
 299
 300         /* Rx flow control */
 301         hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
 302
 303         /* RSS Ring selection */
 304         hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
 305                                         0xB3333333U : 0x00000000U);
 306
 307         /* Multicast filters */
 308         for (i = HW_ATL_B0_MAC_MAX; i--;) {
 309                 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
 310                 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
 311         }
 312
 313         hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
 314         hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
 315
 316         /* Vlan filters */
 317         hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
 318         hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
 319
 320         if (cfg->vlan_id) {
 321                 hw_atl_rpf_vlan_flr_act_set(self, 1U, 0U);
 322                 hw_atl_rpf_vlan_id_flr_set(self, 0U, 0U);
 323                 hw_atl_rpf_vlan_flr_en_set(self, 0U, 0U);
 324
 325                 hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
 326                 hw_atl_rpf_vlan_untagged_act_set(self, 1U);
 327
 328                 hw_atl_rpf_vlan_flr_act_set(self, 1U, 1U);
 329                 hw_atl_rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
 330                 hw_atl_rpf_vlan_flr_en_set(self, 1U, 1U);
 331         } else {
 332                 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
 333         }
 334
 335         /* Rx Interrupts */
 336         hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 337
 338         /* misc */
 339         aq_hw_write_reg(self, 0x00005040U,
 340                         IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
 341
 342         hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
 343         hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
 344
 345         hw_atl_rdm_rx_dca_en_set(self, 0U);
 346         hw_atl_rdm_rx_dca_mode_set(self, 0U);
 347
 348         return aq_hw_err_from_flags(self);
 349 }
 350
 351 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
 352 {
 353         int err = 0;
 354         unsigned int h = 0U;
 355         unsigned int l = 0U;
 356
 357         if (!mac_addr) {
 358                 err = -EINVAL;
 359                 goto err_exit;
 360         }
 361         h = (mac_addr[0] << 8) | (mac_addr[1]);
 362         l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
 363                 (mac_addr[4] << 8) | mac_addr[5];
 364
 365         hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
 366         hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
 367         hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
 368         hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
 369
 370         err = aq_hw_err_from_flags(self);
 371
 372 err_exit:
 373         return err;
 374 }
 375
 376 static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
 377 {
 378         static u32 aq_hw_atl_igcr_table_[4][2] = {
 379                 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
 380                 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
 381                 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
 382                 { 0x20000022U, 0x20000026U }  /* AQ_IRQ_MSIX */
 383         };
 384
 385         int err = 0;
 386         u32 val;
 387
 388         struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
 389
 390         hw_atl_b0_hw_init_tx_path(self);
 391         hw_atl_b0_hw_init_rx_path(self);
 392
 393         hw_atl_b0_hw_mac_addr_set(self, mac_addr);
 394
 395         self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
 396         self->aq_fw_ops->set_state(self, MPI_INIT);
 397
 398         hw_atl_b0_hw_qos_set(self);
 399         hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
 400         hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
 401
 402         /* Force limit MRRS on RDM/TDM to 2K */
 403         val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
 404         aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,
 405                         (val & ~0x707) | 0x404);
 406
 407         /* TX DMA total request limit. B0 hardware is not capable to
 408          * handle more than (8K-MRRS) incoming DMA data.
 409          * Value 24 in 256byte units
 410          */
 411         aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);
 412
 413         /* Reset link status and read out initial hardware counters */
 414         self->aq_link_status.mbps = 0;
 415         self->aq_fw_ops->update_stats(self);
 416
 417         err = aq_hw_err_from_flags(self);
 418         if (err < 0)
 419                 goto err_exit;
 420
 421         /* Interrupts */
 422         hw_atl_reg_irq_glb_ctl_set(self,
 423                                    aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
 424                                                  [(aq_nic_cfg->vecs > 1U) ?
 425                                                  1 : 0]);
 426
 427         hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
 428
 429         /* Interrupts */
 430         hw_atl_reg_gen_irq_map_set(self,
 431                                    ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
 432                             ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
 433
 434         hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
 435
 436 err_exit:
 437         return err;
 438 }
 439
 440 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
 441                                       struct aq_ring_s *ring)
 442 {
 443         hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
 444         return aq_hw_err_from_flags(self);
 445 }
 446
 447 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
 448                                       struct aq_ring_s *ring)
 449 {
 450         hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
 451         return aq_hw_err_from_flags(self);
 452 }
 453
 454 static int hw_atl_b0_hw_start(struct aq_hw_s *self)
 455 {
 456         hw_atl_tpb_tx_buff_en_set(self, 1);
 457         hw_atl_rpb_rx_buff_en_set(self, 1);
 458         return aq_hw_err_from_flags(self);
 459 }
 460
 461 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
 462                                             struct aq_ring_s *ring)
 463 {
 464         hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
 465         return 0;
 466 }
 467
 468 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
 469                                      struct aq_ring_s *ring,
 470                                      unsigned int frags)
 471 {
 472         struct aq_ring_buff_s *buff = NULL;
 473         struct hw_atl_txd_s *txd = NULL;
 474         unsigned int buff_pa_len = 0U;
 475         unsigned int pkt_len = 0U;
 476         unsigned int frag_count = 0U;
 477         bool is_gso = false;
 478
 479         buff = &ring->buff_ring[ring->sw_tail];
 480         pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
 481
 482         for (frag_count = 0; frag_count < frags; frag_count++) {
 483                 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
 484                                                 HW_ATL_B0_TXD_SIZE];
 485                 txd->ctl = 0;
 486                 txd->ctl2 = 0;
 487                 txd->buf_addr = 0;
 488
 489                 buff = &ring->buff_ring[ring->sw_tail];
 490
 491                 if (buff->is_txc) {
 492                         txd->ctl |= (buff->len_l3 << 31) |
 493                                 (buff->len_l2 << 24) |
 494                                 HW_ATL_B0_TXD_CTL_CMD_TCP |
 495                                 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
 496                         txd->ctl2 |= (buff->mss << 16) |
 497                                 (buff->len_l4 << 8) |
 498                                 (buff->len_l3 >> 1);
 499
 500                         pkt_len -= (buff->len_l4 +
 501                                     buff->len_l3 +
 502                                     buff->len_l2);
 503                         is_gso = true;
 504
 505                         if (buff->is_ipv6)
 506                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6;
 507                 } else {
 508                         buff_pa_len = buff->len;
 509
 510                         txd->buf_addr = buff->pa;
 511                         txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
 512                                                 ((u32)buff_pa_len << 4));
 513                         txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
 514                         /* PAY_LEN */
 515                         txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
 516
 517                         if (is_gso) {
 518                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
 519                                 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
 520                         }
 521
 522                         /* Tx checksum offloads */
 523                         if (buff->is_ip_cso)
 524                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
 525
 526                         if (buff->is_udp_cso || buff->is_tcp_cso)
 527                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
 528
 529                         if (unlikely(buff->is_eop)) {
 530                                 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
 531                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
 532                                 is_gso = false;
 533                         }
 534                 }
 535
 536                 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
 537         }
 538
 539         hw_atl_b0_hw_tx_ring_tail_update(self, ring);
 540         return aq_hw_err_from_flags(self);
 541 }
 542
 543 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
 544                                      struct aq_ring_s *aq_ring,
 545                                      struct aq_ring_param_s *aq_ring_param)
 546 {
 547         u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
 548         u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 549
 550         hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
 551
 552         hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 553
 554         hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
 555                                                   aq_ring->idx);
 556
 557         hw_atl_reg_rx_dma_desc_base_addressmswset(self,
 558                                                   dma_desc_addr_msw, aq_ring->idx);
 559
 560         hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 561
 562         hw_atl_rdm_rx_desc_data_buff_size_set(self,
 563                                               AQ_CFG_RX_FRAME_MAX / 1024U,
 564                                        aq_ring->idx);
 565
 566         hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
 567         hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 568         hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
 569
 570         /* Rx ring set mode */
 571
 572         /* Mapping interrupt vector */
 573         hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 574         hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
 575
 576         hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 577         hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
 578         hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
 579         hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
 580
 581         return aq_hw_err_from_flags(self);
 582 }
 583
 584 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
 585                                      struct aq_ring_s *aq_ring,
 586                                      struct aq_ring_param_s *aq_ring_param)
 587 {
 588         u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
 589         u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 590
 591         hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
 592                                                   aq_ring->idx);
 593
 594         hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
 595                                                   aq_ring->idx);
 596
 597         hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 598
 599         hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
 600
 601         /* Set Tx threshold */
 602         hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
 603
 604         /* Mapping interrupt vector */
 605         hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 606         hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
 607
 608         hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 609         hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
 610
 611         return aq_hw_err_from_flags(self);
 612 }
 613
 614 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
 615                                      struct aq_ring_s *ring,
 616                                      unsigned int sw_tail_old)
 617 {
 618         for (; sw_tail_old != ring->sw_tail;
 619                 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
 620                 struct hw_atl_rxd_s *rxd =
 621                         (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
 622                                                         HW_ATL_B0_RXD_SIZE];
 623
 624                 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
 625
 626                 rxd->buf_addr = buff->pa;
 627                 rxd->hdr_addr = 0U;
 628         }
 629
 630         hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
 631
 632         return aq_hw_err_from_flags(self);
 633 }
 634
 635 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
 636                                             struct aq_ring_s *ring)
 637 {
 638         int err = 0;
 639         unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
 640
 641         if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
 642                 err = -ENXIO;
 643                 goto err_exit;
 644         }
 645         ring->hw_head = hw_head_;
 646         err = aq_hw_err_from_flags(self);
 647
 648 err_exit:
 649         return err;
 650 }
 651
 652 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
 653                                         struct aq_ring_s *ring)
 654 {
 655         struct device *ndev = aq_nic_get_dev(ring->aq_nic);
 656
 657         for (; ring->hw_head != ring->sw_tail;
 658                 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
 659                 struct aq_ring_buff_s *buff = NULL;
 660                 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
 661                         &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
 662
 663                 unsigned int is_rx_check_sum_enabled = 0U;
 664                 unsigned int pkt_type = 0U;
 665                 u8 rx_stat = 0U;
 666
 667                 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
 668                         break;
 669                 }
 670
 671                 buff = &ring->buff_ring[ring->hw_head];
 672
 673                 rx_stat = (0x0000003CU & rxd_wb->status) >> 2;
 674
 675                 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
 676
 677                 pkt_type = 0xFFU & (rxd_wb->type >> 4);
 678
 679                 if (is_rx_check_sum_enabled & BIT(0) &&
 680                     (0x0U == (pkt_type & 0x3U)))
 681                         buff->is_ip_cso = (rx_stat & BIT(1)) ? 0U : 1U;
 682
 683                 if (is_rx_check_sum_enabled & BIT(1)) {
 684                         if (0x4U == (pkt_type & 0x1CU))
 685                                 buff->is_udp_cso = (rx_stat & BIT(2)) ? 0U :
 686                                                    !!(rx_stat & BIT(3));
 687                         else if (0x0U == (pkt_type & 0x1CU))
 688                                 buff->is_tcp_cso = (rx_stat & BIT(2)) ? 0U :
 689                                                    !!(rx_stat & BIT(3));
 690                 }
 691                 buff->is_cso_err = !!(rx_stat & 0x6);
 692                 /* Checksum offload workaround for small packets */
 693                 if (unlikely(rxd_wb->pkt_len <= 60)) {
 694                         buff->is_ip_cso = 0U;
 695                         buff->is_cso_err = 0U;
 696                 }
 697
 698                 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
 699
 700                 if ((rx_stat & BIT(0)) || rxd_wb->type & 0x1000U) {
 701                         /* MAC error or DMA error */
 702                         buff->is_error = 1U;
 703                 } else {
 704                         if (self->aq_nic_cfg->is_rss) {
 705                                 /* last 4 byte */
 706                                 u16 rss_type = rxd_wb->type & 0xFU;
 707
 708                                 if (rss_type && rss_type < 0x8U) {
 709                                         buff->is_hash_l4 = (rss_type == 0x4 ||
 710                                         rss_type == 0x5);
 711                                         buff->rss_hash = rxd_wb->rss_hash;
 712                                 }
 713                         }
 714
 715                         if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
 716                                 buff->len = rxd_wb->pkt_len %
 717                                         AQ_CFG_RX_FRAME_MAX;
 718                                 buff->len = buff->len ?
 719                                         buff->len : AQ_CFG_RX_FRAME_MAX;
 720                                 buff->next = 0U;
 721                                 buff->is_eop = 1U;
 722                         } else {
 723                                 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
 724                                         rxd_wb->status) {
 725                                         /* LRO */
 726                                         buff->next = rxd_wb->next_desc_ptr;
 727                                         ++ring->stats.rx.lro_packets;
 728                                 } else {
 729                                         /* jumbo */
 730                                         buff->next =
 731                                                 aq_ring_next_dx(ring,
 732                                                                 ring->hw_head);
 733                                         ++ring->stats.rx.jumbo_packets;
 734                                 }
 735                         }
 736                 }
 737         }
 738
 739         return aq_hw_err_from_flags(self);
 740 }
 741
 742 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
 743 {
 744         hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
 745         return aq_hw_err_from_flags(self);
 746 }
 747
 748 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 749 {
 750         hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
 751         hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
 752
 753         atomic_inc(&self->dpc);
 754         return aq_hw_err_from_flags(self);
 755 }
 756
 757 static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
 758 {
 759         *mask = hw_atl_itr_irq_statuslsw_get(self);
 760         return aq_hw_err_from_flags(self);
 761 }
 762
 763 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
 764
 765 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
 766                                           unsigned int packet_filter)
 767 {
 768         unsigned int i = 0U;
 769
 770         hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
 771         hw_atl_rpfl2multicast_flr_en_set(self,
 772                                          IS_FILTER_ENABLED(IFF_ALLMULTI), 0);
 773
 774         hw_atl_rpfl2_accept_all_mc_packets_set(self,
 775                                                IS_FILTER_ENABLED(IFF_ALLMULTI));
 776
 777         hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
 778
 779         self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
 780
 781         for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
 782                 hw_atl_rpfl2_uc_flr_en_set(self,
 783                                            (self->aq_nic_cfg->is_mc_list_enabled &&
 784                                     (i <= self->aq_nic_cfg->mc_list_count)) ?
 785                                     1U : 0U, i);
 786
 787         return aq_hw_err_from_flags(self);
 788 }
 789
 790 #undef IS_FILTER_ENABLED
 791
 792 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
 793                                            u8 ar_mac
 794                                            [AQ_HW_MULTICAST_ADDRESS_MAX]
 795                                            [ETH_ALEN],
 796                                            u32 count)
 797 {
 798         int err = 0;
 799
 800         if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
 801                 err = -EBADRQC;
 802                 goto err_exit;
 803         }
 804         for (self->aq_nic_cfg->mc_list_count = 0U;
 805                         self->aq_nic_cfg->mc_list_count < count;
 806                         ++self->aq_nic_cfg->mc_list_count) {
 807                 u32 i = self->aq_nic_cfg->mc_list_count;
 808                 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
 809                 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
 810                                         (ar_mac[i][4] << 8) | ar_mac[i][5];
 811
 812                 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
 813
 814                 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
 815                                                         l, HW_ATL_B0_MAC_MIN + i);
 816
 817                 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
 818                                                         h, HW_ATL_B0_MAC_MIN + i);
 819
 820                 hw_atl_rpfl2_uc_flr_en_set(self,
 821                                            (self->aq_nic_cfg->is_mc_list_enabled),
 822                                            HW_ATL_B0_MAC_MIN + i);
 823         }
 824
 825         err = aq_hw_err_from_flags(self);
 826
 827 err_exit:
 828         return err;
 829 }
 830
 831 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
 832 {
 833         unsigned int i = 0U;
 834         u32 itr_tx = 2U;
 835         u32 itr_rx = 2U;
 836
 837         switch (self->aq_nic_cfg->itr) {
 838         case  AQ_CFG_INTERRUPT_MODERATION_ON:
 839         case  AQ_CFG_INTERRUPT_MODERATION_AUTO:
 840                 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
 841                 hw_atl_tdm_tdm_intr_moder_en_set(self, 1U);
 842                 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
 843                 hw_atl_rdm_rdm_intr_moder_en_set(self, 1U);
 844
 845                 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
 846                         /* HW timers are in 2us units */
 847                         int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
 848                         int tx_min_timer = tx_max_timer / 2;
 849
 850                         int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
 851                         int rx_min_timer = rx_max_timer / 2;
 852
 853                         tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
 854                         tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
 855                         rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
 856                         rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
 857
 858                         itr_tx |= tx_min_timer << 0x8U;
 859                         itr_tx |= tx_max_timer << 0x10U;
 860                         itr_rx |= rx_min_timer << 0x8U;
 861                         itr_rx |= rx_max_timer << 0x10U;
 862                 } else {
 863                         static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
 864                                 {0xfU, 0xffU}, /* 10Gbit */
 865                                 {0xfU, 0x1ffU}, /* 5Gbit */
 866                                 {0xfU, 0x1ffU}, /* 5Gbit 5GS */
 867                                 {0xfU, 0x1ffU}, /* 2.5Gbit */
 868                                 {0xfU, 0x1ffU}, /* 1Gbit */
 869                                 {0xfU, 0x1ffU}, /* 100Mbit */
 870                         };
 871
 872                         static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
 873                                 {0x6U, 0x38U},/* 10Gbit */
 874                                 {0xCU, 0x70U},/* 5Gbit */
 875                                 {0xCU, 0x70U},/* 5Gbit 5GS */
 876                                 {0x18U, 0xE0U},/* 2.5Gbit */
 877                                 {0x30U, 0x80U},/* 1Gbit */
 878                                 {0x4U, 0x50U},/* 100Mbit */
 879                         };
 880
 881                         unsigned int speed_index =
 882                                         hw_atl_utils_mbps_2_speed_index(
 883                                                 self->aq_link_status.mbps);
 884
 885                         /* Update user visible ITR settings */
 886                         self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
 887                                                         [speed_index][1] * 2;
 888                         self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
 889                                                         [speed_index][1] * 2;
 890
 891                         itr_tx |= hw_atl_b0_timers_table_tx_
 892                                                 [speed_index][0] << 0x8U;
 893                         itr_tx |= hw_atl_b0_timers_table_tx_
 894                                                 [speed_index][1] << 0x10U;
 895
 896                         itr_rx |= hw_atl_b0_timers_table_rx_
 897                                                 [speed_index][0] << 0x8U;
 898                         itr_rx |= hw_atl_b0_timers_table_rx_
 899                                                 [speed_index][1] << 0x10U;
 900                 }
 901                 break;
 902         case AQ_CFG_INTERRUPT_MODERATION_OFF:
 903                 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 904                 hw_atl_tdm_tdm_intr_moder_en_set(self, 0U);
 905                 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 906                 hw_atl_rdm_rdm_intr_moder_en_set(self, 0U);
 907                 itr_tx = 0U;
 908                 itr_rx = 0U;
 909                 break;
 910         }
 911
 912         for (i = HW_ATL_B0_RINGS_MAX; i--;) {
 913                 hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
 914                 hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
 915         }
 916
 917         return aq_hw_err_from_flags(self);
 918 }
 919
 920 static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
 921 {
 922         hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
 923
 924         /* Invalidate Descriptor Cache to prevent writing to the cached
 925          * descriptors and to the data pointer of those descriptors
 926          */
 927         hw_atl_rdm_rx_dma_desc_cache_init_set(self, 1);
 928
 929         return aq_hw_err_from_flags(self);
 930 }
 931
 932 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
 933                                      struct aq_ring_s *ring)
 934 {
 935         hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
 936         return aq_hw_err_from_flags(self);
 937 }
 938
 939 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
 940                                      struct aq_ring_s *ring)
 941 {
 942         hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
 943         return aq_hw_err_from_flags(self);
 944 }
 945
 946 const struct aq_hw_ops hw_atl_ops_b0 = {
 947         .hw_set_mac_address   = hw_atl_b0_hw_mac_addr_set,
 948         .hw_init              = hw_atl_b0_hw_init,
 949         .hw_reset             = hw_atl_b0_hw_reset,
 950         .hw_start             = hw_atl_b0_hw_start,
 951         .hw_ring_tx_start     = hw_atl_b0_hw_ring_tx_start,
 952         .hw_ring_tx_stop      = hw_atl_b0_hw_ring_tx_stop,
 953         .hw_ring_rx_start     = hw_atl_b0_hw_ring_rx_start,
 954         .hw_ring_rx_stop      = hw_atl_b0_hw_ring_rx_stop,
 955         .hw_stop              = hw_atl_b0_hw_stop,
 956
 957         .hw_ring_tx_xmit         = hw_atl_b0_hw_ring_tx_xmit,
 958         .hw_ring_tx_head_update  = hw_atl_b0_hw_ring_tx_head_update,
 959
 960         .hw_ring_rx_receive      = hw_atl_b0_hw_ring_rx_receive,
 961         .hw_ring_rx_fill         = hw_atl_b0_hw_ring_rx_fill,
 962
 963         .hw_irq_enable           = hw_atl_b0_hw_irq_enable,
 964         .hw_irq_disable          = hw_atl_b0_hw_irq_disable,
 965         .hw_irq_read             = hw_atl_b0_hw_irq_read,
 966
 967         .hw_ring_rx_init             = hw_atl_b0_hw_ring_rx_init,
 968         .hw_ring_tx_init             = hw_atl_b0_hw_ring_tx_init,
 969         .hw_packet_filter_set        = hw_atl_b0_hw_packet_filter_set,
 970         .hw_multicast_list_set       = hw_atl_b0_hw_multicast_list_set,
 971         .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
 972         .hw_rss_set                  = hw_atl_b0_hw_rss_set,
 973         .hw_rss_hash_set             = hw_atl_b0_hw_rss_hash_set,
 974         .hw_get_regs                 = hw_atl_utils_hw_get_regs,
 975         .hw_get_hw_stats             = hw_atl_utils_get_hw_stats,
 976         .hw_get_fw_version           = hw_atl_utils_get_fw_version,
 977         .hw_set_fc                   = hw_atl_b0_set_fc,
 978 };