drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File aq_pci_func.c: Definition of PCI functions. */
  11
  12 #include <linux/interrupt.h>
  13 #include <linux/module.h>
  14
  15 #include "aq_main.h"
  16 #include "aq_nic.h"
  17 #include "aq_vec.h"
  18 #include "aq_hw.h"
  19 #include "aq_pci_func.h"
  20 #include "hw_atl/hw_atl_a0.h"
  21 #include "hw_atl/hw_atl_b0.h"
  22 #include "aq_filters.h"
  23
  24 static const struct pci_device_id aq_pci_tbl[] = {
  25         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_0001), },
  26         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D100), },
  27         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D107), },
  28         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D108), },
  29         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D109), },
  30
  31         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100), },
  32         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107), },
  33         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108), },
  34         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109), },
  35         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111), },
  36         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112), },
  37
  38         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100S), },
  39         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107S), },
  40         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108S), },
  41         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109S), },
  42         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111S), },
  43         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112S), },
  44
  45         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111E), },
  46         { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112E), },
  47
  48         {}
  49 };
  50
  51 static const struct aq_board_revision_s hw_atl_boards[] = {
  52         { AQ_DEVICE_ID_0001,    AQ_HWREV_1,     &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
  53         { AQ_DEVICE_ID_D100,    AQ_HWREV_1,     &hw_atl_ops_a0, &hw_atl_a0_caps_aqc100, },
  54         { AQ_DEVICE_ID_D107,    AQ_HWREV_1,     &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
  55         { AQ_DEVICE_ID_D108,    AQ_HWREV_1,     &hw_atl_ops_a0, &hw_atl_a0_caps_aqc108, },
  56         { AQ_DEVICE_ID_D109,    AQ_HWREV_1,     &hw_atl_ops_a0, &hw_atl_a0_caps_aqc109, },
  57
  58         { AQ_DEVICE_ID_0001,    AQ_HWREV_2,     &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
  59         { AQ_DEVICE_ID_D100,    AQ_HWREV_2,     &hw_atl_ops_b0, &hw_atl_b0_caps_aqc100, },
  60         { AQ_DEVICE_ID_D107,    AQ_HWREV_2,     &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
  61         { AQ_DEVICE_ID_D108,    AQ_HWREV_2,     &hw_atl_ops_b0, &hw_atl_b0_caps_aqc108, },
  62         { AQ_DEVICE_ID_D109,    AQ_HWREV_2,     &hw_atl_ops_b0, &hw_atl_b0_caps_aqc109, },
  63
  64         { AQ_DEVICE_ID_AQC100,  AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
  65         { AQ_DEVICE_ID_AQC107,  AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
  66         { AQ_DEVICE_ID_AQC108,  AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108, },
  67         { AQ_DEVICE_ID_AQC109,  AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109, },
  68         { AQ_DEVICE_ID_AQC111,  AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111, },
  69         { AQ_DEVICE_ID_AQC112,  AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112, },
  70
  71         { AQ_DEVICE_ID_AQC100S, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc100s, },
  72         { AQ_DEVICE_ID_AQC107S, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107s, },
  73         { AQ_DEVICE_ID_AQC108S, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108s, },
  74         { AQ_DEVICE_ID_AQC109S, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, },
  75         { AQ_DEVICE_ID_AQC111S, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, },
  76         { AQ_DEVICE_ID_AQC112S, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, },
  77
  78         { AQ_DEVICE_ID_AQC111E, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111e, },
  79         { AQ_DEVICE_ID_AQC112E, AQ_HWREV_ANY,   &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112e, },
  80 };
  81
  82 MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
  83
  84 static int aq_pci_probe_get_hw_by_id(struct pci_dev *pdev,
  85                                      const struct aq_hw_ops **ops,
  86                                      const struct aq_hw_caps_s **caps)
  87 {
  88         int i;
  89
  90         if (pdev->vendor != PCI_VENDOR_ID_AQUANTIA)
  91                 return -EINVAL;
  92
  93         for (i = 0; i < ARRAY_SIZE(hw_atl_boards); i++) {
  94                 if (hw_atl_boards[i].devid == pdev->device &&
  95                     (hw_atl_boards[i].revision == AQ_HWREV_ANY ||
  96                      hw_atl_boards[i].revision == pdev->revision)) {
  97                         *ops = hw_atl_boards[i].ops;
  98                         *caps = hw_atl_boards[i].caps;
  99                         break;
 100                 }
 101         }
 102
 103         if (i == ARRAY_SIZE(hw_atl_boards))
 104                 return -EINVAL;
 105
 106         return 0;
 107 }
 108
 109 int aq_pci_func_init(struct pci_dev *pdev)
 110 {
 111         int err;
 112
 113         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
 114         if (!err) {
 115                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 116
 117         }
 118         if (err) {
 119                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 120                 if (!err)
 121                         err = pci_set_consistent_dma_mask(pdev,
 122                                                           DMA_BIT_MASK(32));
 123         }
 124         if (err != 0) {
 125                 err = -ENOSR;
 126                 goto err_exit;
 127         }
 128
 129         err = pci_request_regions(pdev, AQ_CFG_DRV_NAME "_mmio");
 130         if (err < 0)
 131                 goto err_exit;
 132
 133         pci_set_master(pdev);
 134
 135         return 0;
 136
 137 err_exit:
 138         return err;
 139 }
 140
 141 int aq_pci_func_alloc_irq(struct aq_nic_s *self, unsigned int i,
 142                           char *name, void *aq_vec, cpumask_t *affinity_mask)
 143 {
 144         struct pci_dev *pdev = self->pdev;
 145         int err;
 146
 147         if (pdev->msix_enabled || pdev->msi_enabled)
 148                 err = request_irq(pci_irq_vector(pdev, i), aq_vec_isr, 0,
 149                                   name, aq_vec);
 150         else
 151                 err = request_irq(pci_irq_vector(pdev, i), aq_vec_isr_legacy,
 152                                   IRQF_SHARED, name, aq_vec);
 153
 154         if (err >= 0) {
 155                 self->msix_entry_mask |= (1 << i);
 156                 self->aq_vec[i] = aq_vec;
 157
 158                 if (pdev->msix_enabled)
 159                         irq_set_affinity_hint(pci_irq_vector(pdev, i),
 160                                               affinity_mask);
 161         }
 162         return err;
 163 }
 164
 165 void aq_pci_func_free_irqs(struct aq_nic_s *self)
 166 {
 167         struct pci_dev *pdev = self->pdev;
 168         unsigned int i;
 169
 170         for (i = 32U; i--;) {
 171                 if (!((1U << i) & self->msix_entry_mask))
 172                         continue;
 173                 if (i >= AQ_CFG_VECS_MAX)
 174                         continue;
 175
 176                 if (pdev->msix_enabled)
 177                         irq_set_affinity_hint(pci_irq_vector(pdev, i), NULL);
 178                 free_irq(pci_irq_vector(pdev, i), self->aq_vec[i]);
 179                 self->msix_entry_mask &= ~(1U << i);
 180         }
 181 }
 182
 183 unsigned int aq_pci_func_get_irq_type(struct aq_nic_s *self)
 184 {
 185         if (self->pdev->msix_enabled)
 186                 return AQ_HW_IRQ_MSIX;
 187         if (self->pdev->msi_enabled)
 188                 return AQ_HW_IRQ_MSIX;
 189         return AQ_HW_IRQ_LEGACY;
 190 }
 191
 192 static void aq_pci_free_irq_vectors(struct aq_nic_s *self)
 193 {
 194         pci_free_irq_vectors(self->pdev);
 195 }
 196
 197 static int aq_pci_probe(struct pci_dev *pdev,
 198                         const struct pci_device_id *pci_id)
 199 {
 200         struct aq_nic_s *self;
 201         int err;
 202         struct net_device *ndev;
 203         resource_size_t mmio_pa;
 204         u32 bar;
 205         u32 numvecs;
 206
 207         err = pci_enable_device(pdev);
 208         if (err)
 209                 return err;
 210
 211         err = aq_pci_func_init(pdev);
 212         if (err)
 213                 goto err_pci_func;
 214
 215         ndev = aq_ndev_alloc();
 216         if (!ndev) {
 217                 err = -ENOMEM;
 218                 goto err_ndev;
 219         }
 220
 221         self = netdev_priv(ndev);
 222         self->pdev = pdev;
 223         SET_NETDEV_DEV(ndev, &pdev->dev);
 224         pci_set_drvdata(pdev, self);
 225
 226         err = aq_pci_probe_get_hw_by_id(pdev, &self->aq_hw_ops,
 227                                         &aq_nic_get_cfg(self)->aq_hw_caps);
 228         if (err)
 229                 goto err_ioremap;
 230
 231         self->aq_hw = kzalloc(sizeof(*self->aq_hw), GFP_KERNEL);
 232         if (!self->aq_hw) {
 233                 err = -ENOMEM;
 234                 goto err_ioremap;
 235         }
 236         self->aq_hw->aq_nic_cfg = aq_nic_get_cfg(self);
 237
 238         for (bar = 0; bar < 4; ++bar) {
 239                 if (IORESOURCE_MEM & pci_resource_flags(pdev, bar)) {
 240                         resource_size_t reg_sz;
 241
 242                         mmio_pa = pci_resource_start(pdev, bar);
 243                         if (mmio_pa == 0U) {
 244                                 err = -EIO;
 245                                 goto err_free_aq_hw;
 246                         }
 247
 248                         reg_sz = pci_resource_len(pdev, bar);
 249                         if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
 250                                 err = -EIO;
 251                                 goto err_free_aq_hw;
 252                         }
 253
 254                         self->aq_hw->mmio = ioremap_nocache(mmio_pa, reg_sz);
 255                         if (!self->aq_hw->mmio) {
 256                                 err = -EIO;
 257                                 goto err_free_aq_hw;
 258                         }
 259                         break;
 260                 }
 261         }
 262
 263         if (bar == 4) {
 264                 err = -EIO;
 265                 goto err_free_aq_hw;
 266         }
 267
 268         numvecs = min((u8)AQ_CFG_VECS_DEF,
 269                       aq_nic_get_cfg(self)->aq_hw_caps->msix_irqs);
 270         numvecs = min(numvecs, num_online_cpus());
 271         /*enable interrupts */
 272 #if !AQ_CFG_FORCE_LEGACY_INT
 273         err = pci_alloc_irq_vectors(self->pdev, 1, numvecs,
 274                                     PCI_IRQ_MSIX | PCI_IRQ_MSI |
 275                                     PCI_IRQ_LEGACY);
 276
 277         if (err < 0)
 278                 goto err_hwinit;
 279         numvecs = err;
 280 #endif
 281         self->irqvecs = numvecs;
 282
 283         /* net device init */
 284         aq_nic_cfg_start(self);
 285
 286         aq_nic_ndev_init(self);
 287
 288         err = aq_nic_ndev_register(self);
 289         if (err < 0)
 290                 goto err_register;
 291
 292         return 0;
 293
 294 err_register:
 295         aq_nic_free_vectors(self);
 296         aq_pci_free_irq_vectors(self);
 297 err_hwinit:
 298         iounmap(self->aq_hw->mmio);
 299 err_free_aq_hw:
 300         kfree(self->aq_hw);
 301 err_ioremap:
 302         free_netdev(ndev);
 303 err_ndev:
 304         pci_release_regions(pdev);
 305 err_pci_func:
 306         pci_disable_device(pdev);
 307         return err;
 308 }
 309
 310 static void aq_pci_remove(struct pci_dev *pdev)
 311 {
 312         struct aq_nic_s *self = pci_get_drvdata(pdev);
 313
 314         if (self->ndev) {
 315                 aq_clear_rxnfc_all_rules(self);
 316                 if (self->ndev->reg_state == NETREG_REGISTERED)
 317                         unregister_netdev(self->ndev);
 318                 aq_nic_free_vectors(self);
 319                 aq_pci_free_irq_vectors(self);
 320                 iounmap(self->aq_hw->mmio);
 321                 kfree(self->aq_hw);
 322                 pci_release_regions(pdev);
 323                 free_netdev(self->ndev);
 324         }
 325
 326         pci_disable_device(pdev);
 327 }
 328
 329 static void aq_pci_shutdown(struct pci_dev *pdev)
 330 {
 331         struct aq_nic_s *self = pci_get_drvdata(pdev);
 332
 333         aq_nic_shutdown(self);
 334
 335         pci_disable_device(pdev);
 336
 337         if (system_state == SYSTEM_POWER_OFF) {
 338                 pci_wake_from_d3(pdev, false);
 339                 pci_set_power_state(pdev, PCI_D3hot);
 340         }
 341 }
 342
 343 static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
 344 {
 345         struct aq_nic_s *self = pci_get_drvdata(pdev);
 346
 347         return aq_nic_change_pm_state(self, &pm_msg);
 348 }
 349
 350 static int aq_pci_resume(struct pci_dev *pdev)
 351 {
 352         struct aq_nic_s *self = pci_get_drvdata(pdev);
 353         pm_message_t pm_msg = PMSG_RESTORE;
 354
 355         return aq_nic_change_pm_state(self, &pm_msg);
 356 }
 357
 358 static struct pci_driver aq_pci_ops = {
 359         .name = AQ_CFG_DRV_NAME,
 360         .id_table = aq_pci_tbl,
 361         .probe = aq_pci_probe,
 362         .remove = aq_pci_remove,
 363         .suspend = aq_pci_suspend,
 364         .resume = aq_pci_resume,
 365         .shutdown = aq_pci_shutdown,
 366 };
 367
 368 module_pci_driver(aq_pci_ops);