drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include <linux/netdevice.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/delay.h>
  60 #include <linux/pci.h>
  61
  62 #include "e1000.h"
  63
  64 #define ICH_FLASH_GFPREG                0x0000
  65 #define ICH_FLASH_HSFSTS                0x0004
  66 #define ICH_FLASH_HSFCTL                0x0006
  67 #define ICH_FLASH_FADDR                 0x0008
  68 #define ICH_FLASH_FDATA0                0x0010
  69 #define ICH_FLASH_PR0                   0x0074
  70
  71 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  74 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  75 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  76
  77 #define ICH_CYCLE_READ                  0
  78 #define ICH_CYCLE_WRITE                 2
  79 #define ICH_CYCLE_ERASE                 3
  80
  81 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  82 #define FLASH_SECTOR_ADDR_SHIFT         12
  83
  84 #define ICH_FLASH_SEG_SIZE_256          256
  85 #define ICH_FLASH_SEG_SIZE_4K           4096
  86 #define ICH_FLASH_SEG_SIZE_8K           8192
  87 #define ICH_FLASH_SEG_SIZE_64K          65536
  88
  89
  90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  91
  92 #define E1000_ICH_MNG_IAMT_MODE         0x2
  93
  94 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  95                                  (ID_LED_DEF1_OFF2 <<  8) | \
  96                                  (ID_LED_DEF1_ON2  <<  4) | \
  97                                  (ID_LED_DEF1_DEF2))
  98
  99 #define E1000_ICH_NVM_SIG_WORD          0x13
 100 #define E1000_ICH_NVM_SIG_MASK          0xC000
 101 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 102 #define E1000_ICH_NVM_SIG_VALUE         0x80
 103
 104 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 105
 106 #define E1000_FEXTNVM_SW_CONFIG         1
 107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 108
 109 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 110
 111 #define E1000_ICH_RAR_ENTRIES           7
 112
 113 #define PHY_PAGE_SHIFT 5
 114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 115                            ((reg) & MAX_PHY_REG_ADDRESS))
 116 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 117 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 118
 119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 121 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 122
 123 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 124
 125 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 126
 127 /* SMBus Address Phy Register */
 128 #define HV_SMB_ADDR            PHY_REG(768, 26)
 129 #define HV_SMB_ADDR_PEC_EN     0x0200
 130 #define HV_SMB_ADDR_VALID      0x0080
 131
 132 /* Strapping Option Register - RO */
 133 #define E1000_STRAP                     0x0000C
 134 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 135 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 136
 137 /* OEM Bits Phy Register */
 138 #define HV_OEM_BITS            PHY_REG(768, 25)
 139 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 140 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 141 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 142
 143 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 144 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 145
 146 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 147 /* Offset 04h HSFSTS */
 148 union ich8_hws_flash_status {
 149         struct ich8_hsfsts {
 150                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 151                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 152                 u16 dael       :1; /* bit 2 Direct Access error Log */
 153                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 154                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 155                 u16 reserved1  :2; /* bit 13:6 Reserved */
 156                 u16 reserved2  :6; /* bit 13:6 Reserved */
 157                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 158                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 159         } hsf_status;
 160         u16 regval;
 161 };
 162
 163 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 164 /* Offset 06h FLCTL */
 165 union ich8_hws_flash_ctrl {
 166         struct ich8_hsflctl {
 167                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 168                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 169                 u16 reserved   :5;   /* 7:3 Reserved  */
 170                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 171                 u16 flockdn    :6;   /* 15:10 Reserved */
 172         } hsf_ctrl;
 173         u16 regval;
 174 };
 175
 176 /* ICH Flash Region Access Permissions */
 177 union ich8_hws_flash_regacc {
 178         struct ich8_flracc {
 179                 u32 grra      :8; /* 0:7 GbE region Read Access */
 180                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 181                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 182                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 183         } hsf_flregacc;
 184         u16 regval;
 185 };
 186
 187 /* ICH Flash Protected Region */
 188 union ich8_flash_protected_range {
 189         struct ich8_pr {
 190                 u32 base:13;     /* 0:12 Protected Range Base */
 191                 u32 reserved1:2; /* 13:14 Reserved */
 192                 u32 rpe:1;       /* 15 Read Protection Enable */
 193                 u32 limit:13;    /* 16:28 Protected Range Limit */
 194                 u32 reserved2:2; /* 29:30 Reserved */
 195                 u32 wpe:1;       /* 31 Write Protection Enable */
 196         } range;
 197         u32 regval;
 198 };
 199
 200 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 201 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 202 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 203 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 204 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 205 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 206                                                 u32 offset, u8 byte);
 207 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 208                                          u8 *data);
 209 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 210                                          u16 *data);
 211 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 212                                          u8 size, u16 *data);
 213 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 214 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 215 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 216 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 217 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 218 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 219 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 220 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 221 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 222 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 223 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 224 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 225 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 226 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 227 static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
 228
 229 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 230 {
 231         return readw(hw->flash_address + reg);
 232 }
 233
 234 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 235 {
 236         return readl(hw->flash_address + reg);
 237 }
 238
 239 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 240 {
 241         writew(val, hw->flash_address + reg);
 242 }
 243
 244 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 245 {
 246         writel(val, hw->flash_address + reg);
 247 }
 248
 249 #define er16flash(reg)          __er16flash(hw, (reg))
 250 #define er32flash(reg)          __er32flash(hw, (reg))
 251 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 252 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 253
 254 /**
 255  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 256  *  @hw: pointer to the HW structure
 257  *
 258  *  Initialize family-specific PHY parameters and function pointers.
 259  **/
 260 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 261 {
 262         struct e1000_phy_info *phy = &hw->phy;
 263         s32 ret_val = 0;
 264
 265         phy->addr                     = 1;
 266         phy->reset_delay_us           = 100;
 267
 268         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 269         phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;
 270         phy->ops.read_phy_reg_locked  = e1000_read_phy_reg_hv_locked;
 271         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 272         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 273         phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;
 274         phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
 275         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 276
 277         phy->id = e1000_phy_unknown;
 278         e1000e_get_phy_id(hw);
 279         phy->type = e1000e_get_phy_type_from_id(phy->id);
 280
 281         if (phy->type == e1000_phy_82577) {
 282                 phy->ops.check_polarity = e1000_check_polarity_82577;
 283                 phy->ops.force_speed_duplex =
 284                         e1000_phy_force_speed_duplex_82577;
 285                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 286                 phy->ops.get_phy_info = e1000_get_phy_info_82577;
 287                 phy->ops.commit_phy = e1000e_phy_sw_reset;
 288         }
 289
 290         return ret_val;
 291 }
 292
 293 /**
 294  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 295  *  @hw: pointer to the HW structure
 296  *
 297  *  Initialize family-specific PHY parameters and function pointers.
 298  **/
 299 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 300 {
 301         struct e1000_phy_info *phy = &hw->phy;
 302         s32 ret_val;
 303         u16 i = 0;
 304
 305         phy->addr                       = 1;
 306         phy->reset_delay_us             = 100;
 307
 308         /*
 309          * We may need to do this twice - once for IGP and if that fails,
 310          * we'll set BM func pointers and try again
 311          */
 312         ret_val = e1000e_determine_phy_address(hw);
 313         if (ret_val) {
 314                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 315                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 316                 ret_val = e1000e_determine_phy_address(hw);
 317                 if (ret_val)
 318                         return ret_val;
 319         }
 320
 321         phy->id = 0;
 322         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 323                (i++ < 100)) {
 324                 msleep(1);
 325                 ret_val = e1000e_get_phy_id(hw);
 326                 if (ret_val)
 327                         return ret_val;
 328         }
 329
 330         /* Verify phy id */
 331         switch (phy->id) {
 332         case IGP03E1000_E_PHY_ID:
 333                 phy->type = e1000_phy_igp_3;
 334                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 335                 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
 336                 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
 337                 break;
 338         case IFE_E_PHY_ID:
 339         case IFE_PLUS_E_PHY_ID:
 340         case IFE_C_E_PHY_ID:
 341                 phy->type = e1000_phy_ife;
 342                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 343                 break;
 344         case BME1000_E_PHY_ID:
 345                 phy->type = e1000_phy_bm;
 346                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 347                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 348                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 349                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 350                 break;
 351         default:
 352                 return -E1000_ERR_PHY;
 353                 break;
 354         }
 355
 356         phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
 357
 358         return 0;
 359 }
 360
 361 /**
 362  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 363  *  @hw: pointer to the HW structure
 364  *
 365  *  Initialize family-specific NVM parameters and function
 366  *  pointers.
 367  **/
 368 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 369 {
 370         struct e1000_nvm_info *nvm = &hw->nvm;
 371         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 372         u32 gfpreg, sector_base_addr, sector_end_addr;
 373         u16 i;
 374
 375         /* Can't read flash registers if the register set isn't mapped. */
 376         if (!hw->flash_address) {
 377                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 378                 return -E1000_ERR_CONFIG;
 379         }
 380
 381         nvm->type = e1000_nvm_flash_sw;
 382
 383         gfpreg = er32flash(ICH_FLASH_GFPREG);
 384
 385         /*
 386          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 387          * Add 1 to sector_end_addr since this sector is included in
 388          * the overall size.
 389          */
 390         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 391         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 392
 393         /* flash_base_addr is byte-aligned */
 394         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 395
 396         /*
 397          * find total size of the NVM, then cut in half since the total
 398          * size represents two separate NVM banks.
 399          */
 400         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 401                                 << FLASH_SECTOR_ADDR_SHIFT;
 402         nvm->flash_bank_size /= 2;
 403         /* Adjust to word count */
 404         nvm->flash_bank_size /= sizeof(u16);
 405
 406         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 407
 408         /* Clear shadow ram */
 409         for (i = 0; i < nvm->word_size; i++) {
 410                 dev_spec->shadow_ram[i].modified = 0;
 411                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 412         }
 413
 414         return 0;
 415 }
 416
 417 /**
 418  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 419  *  @hw: pointer to the HW structure
 420  *
 421  *  Initialize family-specific MAC parameters and function
 422  *  pointers.
 423  **/
 424 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 425 {
 426         struct e1000_hw *hw = &adapter->hw;
 427         struct e1000_mac_info *mac = &hw->mac;
 428
 429         /* Set media type function pointer */
 430         hw->phy.media_type = e1000_media_type_copper;
 431
 432         /* Set mta register count */
 433         mac->mta_reg_count = 32;
 434         /* Set rar entry count */
 435         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 436         if (mac->type == e1000_ich8lan)
 437                 mac->rar_entry_count--;
 438         /* Set if manageability features are enabled. */
 439         mac->arc_subsystem_valid = 1;
 440
 441         /* LED operations */
 442         switch (mac->type) {
 443         case e1000_ich8lan:
 444         case e1000_ich9lan:
 445         case e1000_ich10lan:
 446                 /* ID LED init */
 447                 mac->ops.id_led_init = e1000e_id_led_init;
 448                 /* setup LED */
 449                 mac->ops.setup_led = e1000e_setup_led_generic;
 450                 /* cleanup LED */
 451                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 452                 /* turn on/off LED */
 453                 mac->ops.led_on = e1000_led_on_ich8lan;
 454                 mac->ops.led_off = e1000_led_off_ich8lan;
 455                 break;
 456         case e1000_pchlan:
 457                 /* ID LED init */
 458                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 459                 /* setup LED */
 460                 mac->ops.setup_led = e1000_setup_led_pchlan;
 461                 /* cleanup LED */
 462                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 463                 /* turn on/off LED */
 464                 mac->ops.led_on = e1000_led_on_pchlan;
 465                 mac->ops.led_off = e1000_led_off_pchlan;
 466                 break;
 467         default:
 468                 break;
 469         }
 470
 471         /* Enable PCS Lock-loss workaround for ICH8 */
 472         if (mac->type == e1000_ich8lan)
 473                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 474
 475         return 0;
 476 }
 477
 478 /**
 479  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 480  *  @hw: pointer to the HW structure
 481  *
 482  *  Checks to see of the link status of the hardware has changed.  If a
 483  *  change in link status has been detected, then we read the PHY registers
 484  *  to get the current speed/duplex if link exists.
 485  **/
 486 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 487 {
 488         struct e1000_mac_info *mac = &hw->mac;
 489         s32 ret_val;
 490         bool link;
 491
 492         /*
 493          * We only want to go out to the PHY registers to see if Auto-Neg
 494          * has completed and/or if our link status has changed.  The
 495          * get_link_status flag is set upon receiving a Link Status
 496          * Change or Rx Sequence Error interrupt.
 497          */
 498         if (!mac->get_link_status) {
 499                 ret_val = 0;
 500                 goto out;
 501         }
 502
 503         /*
 504          * First we want to see if the MII Status Register reports
 505          * link.  If so, then we want to get the current speed/duplex
 506          * of the PHY.
 507          */
 508         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 509         if (ret_val)
 510                 goto out;
 511
 512         if (hw->mac.type == e1000_pchlan) {
 513                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 514                 if (ret_val)
 515                         goto out;
 516         }
 517
 518         if (!link)
 519                 goto out; /* No link detected */
 520
 521         mac->get_link_status = false;
 522
 523         if (hw->phy.type == e1000_phy_82578) {
 524                 ret_val = e1000_link_stall_workaround_hv(hw);
 525                 if (ret_val)
 526                         goto out;
 527         }
 528
 529         /*
 530          * Check if there was DownShift, must be checked
 531          * immediately after link-up
 532          */
 533         e1000e_check_downshift(hw);
 534
 535         /*
 536          * If we are forcing speed/duplex, then we simply return since
 537          * we have already determined whether we have link or not.
 538          */
 539         if (!mac->autoneg) {
 540                 ret_val = -E1000_ERR_CONFIG;
 541                 goto out;
 542         }
 543
 544         /*
 545          * Auto-Neg is enabled.  Auto Speed Detection takes care
 546          * of MAC speed/duplex configuration.  So we only need to
 547          * configure Collision Distance in the MAC.
 548          */
 549         e1000e_config_collision_dist(hw);
 550
 551         /*
 552          * Configure Flow Control now that Auto-Neg has completed.
 553          * First, we need to restore the desired flow control
 554          * settings because we may have had to re-autoneg with a
 555          * different link partner.
 556          */
 557         ret_val = e1000e_config_fc_after_link_up(hw);
 558         if (ret_val)
 559                 hw_dbg(hw, "Error configuring flow control\n");
 560
 561 out:
 562         return ret_val;
 563 }
 564
 565 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 566 {
 567         struct e1000_hw *hw = &adapter->hw;
 568         s32 rc;
 569
 570         rc = e1000_init_mac_params_ich8lan(adapter);
 571         if (rc)
 572                 return rc;
 573
 574         rc = e1000_init_nvm_params_ich8lan(hw);
 575         if (rc)
 576                 return rc;
 577
 578         if (hw->mac.type == e1000_pchlan)
 579                 rc = e1000_init_phy_params_pchlan(hw);
 580         else
 581                 rc = e1000_init_phy_params_ich8lan(hw);
 582         if (rc)
 583                 return rc;
 584
 585         if (adapter->hw.phy.type == e1000_phy_ife) {
 586                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 587                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 588         }
 589
 590         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 591             (adapter->hw.phy.type == e1000_phy_igp_3))
 592                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 593
 594         return 0;
 595 }
 596
 597 static DEFINE_MUTEX(nvm_mutex);
 598
 599 /**
 600  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 601  *  @hw: pointer to the HW structure
 602  *
 603  *  Acquires the mutex for performing NVM operations.
 604  **/
 605 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 606 {
 607         mutex_lock(&nvm_mutex);
 608
 609         return 0;
 610 }
 611
 612 /**
 613  *  e1000_release_nvm_ich8lan - Release NVM mutex
 614  *  @hw: pointer to the HW structure
 615  *
 616  *  Releases the mutex used while performing NVM operations.
 617  **/
 618 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 619 {
 620         mutex_unlock(&nvm_mutex);
 621
 622         return;
 623 }
 624
 625 static DEFINE_MUTEX(swflag_mutex);
 626
 627 /**
 628  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 629  *  @hw: pointer to the HW structure
 630  *
 631  *  Acquires the software control flag for performing PHY and select
 632  *  MAC CSR accesses.
 633  **/
 634 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 635 {
 636         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 637         s32 ret_val = 0;
 638
 639         might_sleep();
 640
 641         mutex_lock(&swflag_mutex);
 642
 643         while (timeout) {
 644                 extcnf_ctrl = er32(EXTCNF_CTRL);
 645                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 646                         break;
 647
 648                 mdelay(1);
 649                 timeout--;
 650         }
 651
 652         if (!timeout) {
 653                 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
 654                 ret_val = -E1000_ERR_CONFIG;
 655                 goto out;
 656         }
 657
 658         timeout = SW_FLAG_TIMEOUT;
 659
 660         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 661         ew32(EXTCNF_CTRL, extcnf_ctrl);
 662
 663         while (timeout) {
 664                 extcnf_ctrl = er32(EXTCNF_CTRL);
 665                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 666                         break;
 667
 668                 mdelay(1);
 669                 timeout--;
 670         }
 671
 672         if (!timeout) {
 673                 hw_dbg(hw, "Failed to acquire the semaphore.\n");
 674                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 675                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 676                 ret_val = -E1000_ERR_CONFIG;
 677                 goto out;
 678         }
 679
 680 out:
 681         if (ret_val)
 682                 mutex_unlock(&swflag_mutex);
 683
 684         return ret_val;
 685 }
 686
 687 /**
 688  *  e1000_release_swflag_ich8lan - Release software control flag
 689  *  @hw: pointer to the HW structure
 690  *
 691  *  Releases the software control flag for performing PHY and select
 692  *  MAC CSR accesses.
 693  **/
 694 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 695 {
 696         u32 extcnf_ctrl;
 697
 698         extcnf_ctrl = er32(EXTCNF_CTRL);
 699         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 700         ew32(EXTCNF_CTRL, extcnf_ctrl);
 701
 702         mutex_unlock(&swflag_mutex);
 703
 704         return;
 705 }
 706
 707 /**
 708  *  e1000_check_mng_mode_ich8lan - Checks management mode
 709  *  @hw: pointer to the HW structure
 710  *
 711  *  This checks if the adapter has manageability enabled.
 712  *  This is a function pointer entry point only called by read/write
 713  *  routines for the PHY and NVM parts.
 714  **/
 715 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 716 {
 717         u32 fwsm = er32(FWSM);
 718
 719         return (fwsm & E1000_FWSM_MODE_MASK) ==
 720                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 721 }
 722
 723 /**
 724  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 725  *  @hw: pointer to the HW structure
 726  *
 727  *  Checks if firmware is blocking the reset of the PHY.
 728  *  This is a function pointer entry point only called by
 729  *  reset routines.
 730  **/
 731 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 732 {
 733         u32 fwsm;
 734
 735         fwsm = er32(FWSM);
 736
 737         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 738 }
 739
 740 /**
 741  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 742  *  @hw: pointer to the HW structure
 743  *
 744  *  Forces the speed and duplex settings of the PHY.
 745  *  This is a function pointer entry point only called by
 746  *  PHY setup routines.
 747  **/
 748 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 749 {
 750         struct e1000_phy_info *phy = &hw->phy;
 751         s32 ret_val;
 752         u16 data;
 753         bool link;
 754
 755         if (phy->type != e1000_phy_ife) {
 756                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 757                 return ret_val;
 758         }
 759
 760         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 761         if (ret_val)
 762                 return ret_val;
 763
 764         e1000e_phy_force_speed_duplex_setup(hw, &data);
 765
 766         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 767         if (ret_val)
 768                 return ret_val;
 769
 770         /* Disable MDI-X support for 10/100 */
 771         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 772         if (ret_val)
 773                 return ret_val;
 774
 775         data &= ~IFE_PMC_AUTO_MDIX;
 776         data &= ~IFE_PMC_FORCE_MDIX;
 777
 778         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 779         if (ret_val)
 780                 return ret_val;
 781
 782         hw_dbg(hw, "IFE PMC: %X\n", data);
 783
 784         udelay(1);
 785
 786         if (phy->autoneg_wait_to_complete) {
 787                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 788
 789                 ret_val = e1000e_phy_has_link_generic(hw,
 790                                                      PHY_FORCE_LIMIT,
 791                                                      100000,
 792                                                      &link);
 793                 if (ret_val)
 794                         return ret_val;
 795
 796                 if (!link)
 797                         hw_dbg(hw, "Link taking longer than expected.\n");
 798
 799                 /* Try once more */
 800                 ret_val = e1000e_phy_has_link_generic(hw,
 801                                                      PHY_FORCE_LIMIT,
 802                                                      100000,
 803                                                      &link);
 804                 if (ret_val)
 805                         return ret_val;
 806         }
 807
 808         return 0;
 809 }
 810
 811 /**
 812  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 813  *  @hw:   pointer to the HW structure
 814  *
 815  *  SW should configure the LCD from the NVM extended configuration region
 816  *  as a workaround for certain parts.
 817  **/
 818 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 819 {
 820         struct e1000_phy_info *phy = &hw->phy;
 821         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 822         s32 ret_val;
 823         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 824
 825         ret_val = hw->phy.ops.acquire_phy(hw);
 826         if (ret_val)
 827                 return ret_val;
 828
 829         /*
 830          * Initialize the PHY from the NVM on ICH platforms.  This
 831          * is needed due to an issue where the NVM configuration is
 832          * not properly autoloaded after power transitions.
 833          * Therefore, after each PHY reset, we will load the
 834          * configuration data out of the NVM manually.
 835          */
 836         if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
 837                 (hw->mac.type == e1000_pchlan)) {
 838                 struct e1000_adapter *adapter = hw->adapter;
 839
 840                 /* Check if SW needs to configure the PHY */
 841                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 842                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
 843                     (hw->mac.type == e1000_pchlan))
 844                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 845                 else
 846                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 847
 848                 data = er32(FEXTNVM);
 849                 if (!(data & sw_cfg_mask))
 850                         goto out;
 851
 852                 /* Wait for basic configuration completes before proceeding */
 853                 e1000_lan_init_done_ich8lan(hw);
 854
 855                 /*
 856                  * Make sure HW does not configure LCD from PHY
 857                  * extended configuration before SW configuration
 858                  */
 859                 data = er32(EXTCNF_CTRL);
 860                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 861                         goto out;
 862
 863                 cnf_size = er32(EXTCNF_SIZE);
 864                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 865                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 866                 if (!cnf_size)
 867                         goto out;
 868
 869                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 870                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 871
 872                 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
 873                     (hw->mac.type == e1000_pchlan)) {
 874                         /*
 875                          * HW configures the SMBus address and LEDs when the
 876                          * OEM and LCD Write Enable bits are set in the NVM.
 877                          * When both NVM bits are cleared, SW will configure
 878                          * them instead.
 879                          */
 880                         data = er32(STRAP);
 881                         data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 882                         reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
 883                         reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 884                         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
 885                                                                 reg_data);
 886                         if (ret_val)
 887                                 goto out;
 888
 889                         data = er32(LEDCTL);
 890                         ret_val = e1000_write_phy_reg_hv_locked(hw,
 891                                                                 HV_LED_CONFIG,
 892                                                                 (u16)data);
 893                         if (ret_val)
 894                                 goto out;
 895                 }
 896                 /* Configure LCD from extended configuration region. */
 897
 898                 /* cnf_base_addr is in DWORD */
 899                 word_addr = (u16)(cnf_base_addr << 1);
 900
 901                 for (i = 0; i < cnf_size; i++) {
 902                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
 903                                                    &reg_data);
 904                         if (ret_val)
 905                                 goto out;
 906
 907                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
 908                                                    1, &reg_addr);
 909                         if (ret_val)
 910                                 goto out;
 911
 912                         /* Save off the PHY page for future writes. */
 913                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 914                                 phy_page = reg_data;
 915                                 continue;
 916                         }
 917
 918                         reg_addr &= PHY_REG_MASK;
 919                         reg_addr |= phy_page;
 920
 921                         ret_val = phy->ops.write_phy_reg_locked(hw,
 922                                                             (u32)reg_addr,
 923                                                             reg_data);
 924                         if (ret_val)
 925                                 goto out;
 926                 }
 927         }
 928
 929 out:
 930         hw->phy.ops.release_phy(hw);
 931         return ret_val;
 932 }
 933
 934 /**
 935  *  e1000_k1_gig_workaround_hv - K1 Si workaround
 936  *  @hw:   pointer to the HW structure
 937  *  @link: link up bool flag
 938  *
 939  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
 940  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
 941  *  If link is down, the function will restore the default K1 setting located
 942  *  in the NVM.
 943  **/
 944 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
 945 {
 946         s32 ret_val = 0;
 947         u16 status_reg = 0;
 948         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
 949
 950         if (hw->mac.type != e1000_pchlan)
 951                 goto out;
 952
 953         /* Wrap the whole flow with the sw flag */
 954         ret_val = hw->phy.ops.acquire_phy(hw);
 955         if (ret_val)
 956                 goto out;
 957
 958         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
 959         if (link) {
 960                 if (hw->phy.type == e1000_phy_82578) {
 961                         ret_val = hw->phy.ops.read_phy_reg_locked(hw,
 962                                                                   BM_CS_STATUS,
 963                                                                   &status_reg);
 964                         if (ret_val)
 965                                 goto release;
 966
 967                         status_reg &= BM_CS_STATUS_LINK_UP |
 968                                       BM_CS_STATUS_RESOLVED |
 969                                       BM_CS_STATUS_SPEED_MASK;
 970
 971                         if (status_reg == (BM_CS_STATUS_LINK_UP |
 972                                            BM_CS_STATUS_RESOLVED |
 973                                            BM_CS_STATUS_SPEED_1000))
 974                                 k1_enable = false;
 975                 }
 976
 977                 if (hw->phy.type == e1000_phy_82577) {
 978                         ret_val = hw->phy.ops.read_phy_reg_locked(hw,
 979                                                                   HV_M_STATUS,
 980                                                                   &status_reg);
 981                         if (ret_val)
 982                                 goto release;
 983
 984                         status_reg &= HV_M_STATUS_LINK_UP |
 985                                       HV_M_STATUS_AUTONEG_COMPLETE |
 986                                       HV_M_STATUS_SPEED_MASK;
 987
 988                         if (status_reg == (HV_M_STATUS_LINK_UP |
 989                                            HV_M_STATUS_AUTONEG_COMPLETE |
 990                                            HV_M_STATUS_SPEED_1000))
 991                                 k1_enable = false;
 992                 }
 993
 994                 /* Link stall fix for link up */
 995                 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
 996                                                            0x0100);
 997                 if (ret_val)
 998                         goto release;
 999
1000         } else {
1001                 /* Link stall fix for link down */
1002                 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
1003                                                            0x4100);
1004                 if (ret_val)
1005                         goto release;
1006         }
1007
1008         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1009
1010 release:
1011         hw->phy.ops.release_phy(hw);
1012 out:
1013         return ret_val;
1014 }
1015
1016 /**
1017  *  e1000_configure_k1_ich8lan - Configure K1 power state
1018  *  @hw: pointer to the HW structure
1019  *  @enable: K1 state to configure
1020  *
1021  *  Configure the K1 power state based on the provided parameter.
1022  *  Assumes semaphore already acquired.
1023  *
1024  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1025  **/
1026 static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1027 {
1028         s32 ret_val = 0;
1029         u32 ctrl_reg = 0;
1030         u32 ctrl_ext = 0;
1031         u32 reg = 0;
1032         u16 kmrn_reg = 0;
1033
1034         ret_val = e1000e_read_kmrn_reg_locked(hw,
1035                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1036                                              &kmrn_reg);
1037         if (ret_val)
1038                 goto out;
1039
1040         if (k1_enable)
1041                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1042         else
1043                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1044
1045         ret_val = e1000e_write_kmrn_reg_locked(hw,
1046                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1047                                               kmrn_reg);
1048         if (ret_val)
1049                 goto out;
1050
1051         udelay(20);
1052         ctrl_ext = er32(CTRL_EXT);
1053         ctrl_reg = er32(CTRL);
1054
1055         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1056         reg |= E1000_CTRL_FRCSPD;
1057         ew32(CTRL, reg);
1058
1059         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1060         udelay(20);
1061         ew32(CTRL, ctrl_reg);
1062         ew32(CTRL_EXT, ctrl_ext);
1063         udelay(20);
1064
1065 out:
1066         return ret_val;
1067 }
1068
1069 /**
1070  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1071  *  @hw:       pointer to the HW structure
1072  *  @d0_state: boolean if entering d0 or d3 device state
1073  *
1074  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1075  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1076  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1077  **/
1078 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1079 {
1080         s32 ret_val = 0;
1081         u32 mac_reg;
1082         u16 oem_reg;
1083
1084         if (hw->mac.type != e1000_pchlan)
1085                 return ret_val;
1086
1087         ret_val = hw->phy.ops.acquire_phy(hw);
1088         if (ret_val)
1089                 return ret_val;
1090
1091         mac_reg = er32(EXTCNF_CTRL);
1092         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1093                 goto out;
1094
1095         mac_reg = er32(FEXTNVM);
1096         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1097                 goto out;
1098
1099         mac_reg = er32(PHY_CTRL);
1100
1101         ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1102         if (ret_val)
1103                 goto out;
1104
1105         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1106
1107         if (d0_state) {
1108                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1109                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1110
1111                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1112                         oem_reg |= HV_OEM_BITS_LPLU;
1113         } else {
1114                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1115                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1116
1117                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1118                         oem_reg |= HV_OEM_BITS_LPLU;
1119         }
1120         /* Restart auto-neg to activate the bits */
1121         oem_reg |= HV_OEM_BITS_RESTART_AN;
1122         ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
1123
1124 out:
1125         hw->phy.ops.release_phy(hw);
1126
1127         return ret_val;
1128 }
1129
1130
1131 /**
1132  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1133  *  done after every PHY reset.
1134  **/
1135 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1136 {
1137         s32 ret_val = 0;
1138
1139         if (hw->mac.type != e1000_pchlan)
1140                 return ret_val;
1141
1142         if (((hw->phy.type == e1000_phy_82577) &&
1143              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1144             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1145                 /* Disable generation of early preamble */
1146                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1147                 if (ret_val)
1148                         return ret_val;
1149
1150                 /* Preamble tuning for SSC */
1151                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1152                 if (ret_val)
1153                         return ret_val;
1154         }
1155
1156         if (hw->phy.type == e1000_phy_82578) {
1157                 /*
1158                  * Return registers to default by doing a soft reset then
1159                  * writing 0x3140 to the control register.
1160                  */
1161                 if (hw->phy.revision < 2) {
1162                         e1000e_phy_sw_reset(hw);
1163                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1164                 }
1165         }
1166
1167         /* Select page 0 */
1168         ret_val = hw->phy.ops.acquire_phy(hw);
1169         if (ret_val)
1170                 return ret_val;
1171
1172         hw->phy.addr = 1;
1173         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1174         if (ret_val)
1175                 goto out;
1176         hw->phy.ops.release_phy(hw);
1177
1178         /*
1179          * Configure the K1 Si workaround during phy reset assuming there is
1180          * link so that it disables K1 if link is in 1Gbps.
1181          */
1182         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1183
1184 out:
1185         return ret_val;
1186 }
1187
1188 /**
1189  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1190  *  @hw: pointer to the HW structure
1191  *
1192  *  Check the appropriate indication the MAC has finished configuring the
1193  *  PHY after a software reset.
1194  **/
1195 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1196 {
1197         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1198
1199         /* Wait for basic configuration completes before proceeding */
1200         do {
1201                 data = er32(STATUS);
1202                 data &= E1000_STATUS_LAN_INIT_DONE;
1203                 udelay(100);
1204         } while ((!data) && --loop);
1205
1206         /*
1207          * If basic configuration is incomplete before the above loop
1208          * count reaches 0, loading the configuration from NVM will
1209          * leave the PHY in a bad state possibly resulting in no link.
1210          */
1211         if (loop == 0)
1212                 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
1213
1214         /* Clear the Init Done bit for the next init event */
1215         data = er32(STATUS);
1216         data &= ~E1000_STATUS_LAN_INIT_DONE;
1217         ew32(STATUS, data);
1218 }
1219
1220 /**
1221  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1222  *  @hw: pointer to the HW structure
1223  *
1224  *  Resets the PHY
1225  *  This is a function pointer entry point called by drivers
1226  *  or other shared routines.
1227  **/
1228 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1229 {
1230         s32 ret_val = 0;
1231         u16 reg;
1232
1233         ret_val = e1000e_phy_hw_reset_generic(hw);
1234         if (ret_val)
1235                 return ret_val;
1236
1237         /* Allow time for h/w to get to a quiescent state after reset */
1238         mdelay(10);
1239
1240         if (hw->mac.type == e1000_pchlan) {
1241                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1242                 if (ret_val)
1243                         return ret_val;
1244         }
1245
1246         /* Dummy read to clear the phy wakeup bit after lcd reset */
1247         if (hw->mac.type == e1000_pchlan)
1248                 e1e_rphy(hw, BM_WUC, &reg);
1249
1250         /* Configure the LCD with the extended configuration region in NVM */
1251         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1252         if (ret_val)
1253                 goto out;
1254
1255         /* Configure the LCD with the OEM bits in NVM */
1256         if (hw->mac.type == e1000_pchlan)
1257                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1258
1259 out:
1260         return 0;
1261 }
1262
1263 /**
1264  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1265  *  @hw: pointer to the HW structure
1266  *
1267  *  Populates "phy" structure with various feature states.
1268  *  This function is only called by other family-specific
1269  *  routines.
1270  **/
1271 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1272 {
1273         struct e1000_phy_info *phy = &hw->phy;
1274         s32 ret_val;
1275         u16 data;
1276         bool link;
1277
1278         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1279         if (ret_val)
1280                 return ret_val;
1281
1282         if (!link) {
1283                 hw_dbg(hw, "Phy info is only valid if link is up\n");
1284                 return -E1000_ERR_CONFIG;
1285         }
1286
1287         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1288         if (ret_val)
1289                 return ret_val;
1290         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1291
1292         if (phy->polarity_correction) {
1293                 ret_val = phy->ops.check_polarity(hw);
1294                 if (ret_val)
1295                         return ret_val;
1296         } else {
1297                 /* Polarity is forced */
1298                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1299                                       ? e1000_rev_polarity_reversed
1300                                       : e1000_rev_polarity_normal;
1301         }
1302
1303         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1304         if (ret_val)
1305                 return ret_val;
1306
1307         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1308
1309         /* The following parameters are undefined for 10/100 operation. */
1310         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1311         phy->local_rx = e1000_1000t_rx_status_undefined;
1312         phy->remote_rx = e1000_1000t_rx_status_undefined;
1313
1314         return 0;
1315 }
1316
1317 /**
1318  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1319  *  @hw: pointer to the HW structure
1320  *
1321  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
1322  *  This is a function pointer entry point called by drivers
1323  *  or other shared routines.
1324  **/
1325 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1326 {
1327         switch (hw->phy.type) {
1328         case e1000_phy_ife:
1329                 return e1000_get_phy_info_ife_ich8lan(hw);
1330                 break;
1331         case e1000_phy_igp_3:
1332         case e1000_phy_bm:
1333         case e1000_phy_82578:
1334         case e1000_phy_82577:
1335                 return e1000e_get_phy_info_igp(hw);
1336                 break;
1337         default:
1338                 break;
1339         }
1340
1341         return -E1000_ERR_PHY_TYPE;
1342 }
1343
1344 /**
1345  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1346  *  @hw: pointer to the HW structure
1347  *
1348  *  Polarity is determined on the polarity reversal feature being enabled.
1349  *  This function is only called by other family-specific
1350  *  routines.
1351  **/
1352 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1353 {
1354         struct e1000_phy_info *phy = &hw->phy;
1355         s32 ret_val;
1356         u16 phy_data, offset, mask;
1357
1358         /*
1359          * Polarity is determined based on the reversal feature being enabled.
1360          */
1361         if (phy->polarity_correction) {
1362                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
1363                 mask    = IFE_PESC_POLARITY_REVERSED;
1364         } else {
1365                 offset  = IFE_PHY_SPECIAL_CONTROL;
1366                 mask    = IFE_PSC_FORCE_POLARITY;
1367         }
1368
1369         ret_val = e1e_rphy(hw, offset, &phy_data);
1370
1371         if (!ret_val)
1372                 phy->cable_polarity = (phy_data & mask)
1373                                       ? e1000_rev_polarity_reversed
1374                                       : e1000_rev_polarity_normal;
1375
1376         return ret_val;
1377 }
1378
1379 /**
1380  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1381  *  @hw: pointer to the HW structure
1382  *  @active: true to enable LPLU, false to disable
1383  *
1384  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1385  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1386  *  the phy speed. This function will manually set the LPLU bit and restart
1387  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1388  *  since it configures the same bit.
1389  **/
1390 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1391 {
1392         s32 ret_val = 0;
1393         u16 oem_reg;
1394
1395         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1396         if (ret_val)
1397                 goto out;
1398
1399         if (active)
1400                 oem_reg |= HV_OEM_BITS_LPLU;
1401         else
1402                 oem_reg &= ~HV_OEM_BITS_LPLU;
1403
1404         oem_reg |= HV_OEM_BITS_RESTART_AN;
1405         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1406
1407 out:
1408         return ret_val;
1409 }
1410
1411 /**
1412  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1413  *  @hw: pointer to the HW structure
1414  *  @active: TRUE to enable LPLU, FALSE to disable
1415  *
1416  *  Sets the LPLU D0 state according to the active flag.  When
1417  *  activating LPLU this function also disables smart speed
1418  *  and vice versa.  LPLU will not be activated unless the
1419  *  device autonegotiation advertisement meets standards of
1420  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1421  *  This is a function pointer entry point only called by
1422  *  PHY setup routines.
1423  **/
1424 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1425 {
1426         struct e1000_phy_info *phy = &hw->phy;
1427         u32 phy_ctrl;
1428         s32 ret_val = 0;
1429         u16 data;
1430
1431         if (phy->type == e1000_phy_ife)
1432                 return ret_val;
1433
1434         phy_ctrl = er32(PHY_CTRL);
1435
1436         if (active) {
1437                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1438                 ew32(PHY_CTRL, phy_ctrl);
1439
1440                 if (phy->type != e1000_phy_igp_3)
1441                         return 0;
1442
1443                 /*
1444                  * Call gig speed drop workaround on LPLU before accessing
1445                  * any PHY registers
1446                  */
1447                 if (hw->mac.type == e1000_ich8lan)
1448                         e1000e_gig_downshift_workaround_ich8lan(hw);
1449
1450                 /* When LPLU is enabled, we should disable SmartSpeed */
1451                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1452                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1453                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1454                 if (ret_val)
1455                         return ret_val;
1456         } else {
1457                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1458                 ew32(PHY_CTRL, phy_ctrl);
1459
1460                 if (phy->type != e1000_phy_igp_3)
1461                         return 0;
1462
1463                 /*
1464                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1465                  * during Dx states where the power conservation is most
1466                  * important.  During driver activity we should enable
1467                  * SmartSpeed, so performance is maintained.
1468                  */
1469                 if (phy->smart_speed == e1000_smart_speed_on) {
1470                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1471                                            &data);
1472                         if (ret_val)
1473                                 return ret_val;
1474
1475                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1476                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1477                                            data);
1478                         if (ret_val)
1479                                 return ret_val;
1480                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1481                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1482                                            &data);
1483                         if (ret_val)
1484                                 return ret_val;
1485
1486                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1487                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1488                                            data);
1489                         if (ret_val)
1490                                 return ret_val;
1491                 }
1492         }
1493
1494         return 0;
1495 }
1496
1497 /**
1498  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1499  *  @hw: pointer to the HW structure
1500  *  @active: TRUE to enable LPLU, FALSE to disable
1501  *
1502  *  Sets the LPLU D3 state according to the active flag.  When
1503  *  activating LPLU this function also disables smart speed
1504  *  and vice versa.  LPLU will not be activated unless the
1505  *  device autonegotiation advertisement meets standards of
1506  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1507  *  This is a function pointer entry point only called by
1508  *  PHY setup routines.
1509  **/
1510 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1511 {
1512         struct e1000_phy_info *phy = &hw->phy;
1513         u32 phy_ctrl;
1514         s32 ret_val;
1515         u16 data;
1516
1517         phy_ctrl = er32(PHY_CTRL);
1518
1519         if (!active) {
1520                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1521                 ew32(PHY_CTRL, phy_ctrl);
1522
1523                 if (phy->type != e1000_phy_igp_3)
1524                         return 0;
1525
1526                 /*
1527                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1528                  * during Dx states where the power conservation is most
1529                  * important.  During driver activity we should enable
1530                  * SmartSpeed, so performance is maintained.
1531                  */
1532                 if (phy->smart_speed == e1000_smart_speed_on) {
1533                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1534                                            &data);
1535                         if (ret_val)
1536                                 return ret_val;
1537
1538                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1539                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1540                                            data);
1541                         if (ret_val)
1542                                 return ret_val;
1543                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1544                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1545                                            &data);
1546                         if (ret_val)
1547                                 return ret_val;
1548
1549                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1550                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1551                                            data);
1552                         if (ret_val)
1553                                 return ret_val;
1554                 }
1555         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1556                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1557                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1558                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1559                 ew32(PHY_CTRL, phy_ctrl);
1560
1561                 if (phy->type != e1000_phy_igp_3)
1562                         return 0;
1563
1564                 /*
1565                  * Call gig speed drop workaround on LPLU before accessing
1566                  * any PHY registers
1567                  */
1568                 if (hw->mac.type == e1000_ich8lan)
1569                         e1000e_gig_downshift_workaround_ich8lan(hw);
1570
1571                 /* When LPLU is enabled, we should disable SmartSpeed */
1572                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1573                 if (ret_val)
1574                         return ret_val;
1575
1576                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1577                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1578         }
1579
1580         return 0;
1581 }
1582
1583 /**
1584  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1585  *  @hw: pointer to the HW structure
1586  *  @bank:  pointer to the variable that returns the active bank
1587  *
1588  *  Reads signature byte from the NVM using the flash access registers.
1589  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1590  **/
1591 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1592 {
1593         u32 eecd;
1594         struct e1000_nvm_info *nvm = &hw->nvm;
1595         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1596         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1597         u8 sig_byte = 0;
1598         s32 ret_val = 0;
1599
1600         switch (hw->mac.type) {
1601         case e1000_ich8lan:
1602         case e1000_ich9lan:
1603                 eecd = er32(EECD);
1604                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1605                     E1000_EECD_SEC1VAL_VALID_MASK) {
1606                         if (eecd & E1000_EECD_SEC1VAL)
1607                                 *bank = 1;
1608                         else
1609                                 *bank = 0;
1610
1611                         return 0;
1612                 }
1613                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1614                        "reading flash signature\n");
1615                 /* fall-thru */
1616         default:
1617                 /* set bank to 0 in case flash read fails */
1618                 *bank = 0;
1619
1620                 /* Check bank 0 */
1621                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1622                                                         &sig_byte);
1623                 if (ret_val)
1624                         return ret_val;
1625                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1626                     E1000_ICH_NVM_SIG_VALUE) {
1627                         *bank = 0;
1628                         return 0;
1629                 }
1630
1631                 /* Check bank 1 */
1632                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1633                                                         bank1_offset,
1634                                                         &sig_byte);
1635                 if (ret_val)
1636                         return ret_val;
1637                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1638                     E1000_ICH_NVM_SIG_VALUE) {
1639                         *bank = 1;
1640                         return 0;
1641                 }
1642
1643                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1644                 return -E1000_ERR_NVM;
1645         }
1646
1647         return 0;
1648 }
1649
1650 /**
1651  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1652  *  @hw: pointer to the HW structure
1653  *  @offset: The offset (in bytes) of the word(s) to read.
1654  *  @words: Size of data to read in words
1655  *  @data: Pointer to the word(s) to read at offset.
1656  *
1657  *  Reads a word(s) from the NVM using the flash access registers.
1658  **/
1659 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1660                                   u16 *data)
1661 {
1662         struct e1000_nvm_info *nvm = &hw->nvm;
1663         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1664         u32 act_offset;
1665         s32 ret_val = 0;
1666         u32 bank = 0;
1667         u16 i, word;
1668
1669         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1670             (words == 0)) {
1671                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1672                 ret_val = -E1000_ERR_NVM;
1673                 goto out;
1674         }
1675
1676         nvm->ops.acquire_nvm(hw);
1677
1678         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1679         if (ret_val) {
1680                 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1681                 bank = 0;
1682         }
1683
1684         act_offset = (bank) ? nvm->flash_bank_size : 0;
1685         act_offset += offset;
1686
1687         ret_val = 0;
1688         for (i = 0; i < words; i++) {
1689                 if ((dev_spec->shadow_ram) &&
1690                     (dev_spec->shadow_ram[offset+i].modified)) {
1691                         data[i] = dev_spec->shadow_ram[offset+i].value;
1692                 } else {
1693                         ret_val = e1000_read_flash_word_ich8lan(hw,
1694                                                                 act_offset + i,
1695                                                                 &word);
1696                         if (ret_val)
1697                                 break;
1698                         data[i] = word;
1699                 }
1700         }
1701
1702         nvm->ops.release_nvm(hw);
1703
1704 out:
1705         if (ret_val)
1706                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1707
1708         return ret_val;
1709 }
1710
1711 /**
1712  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1713  *  @hw: pointer to the HW structure
1714  *
1715  *  This function does initial flash setup so that a new read/write/erase cycle
1716  *  can be started.
1717  **/
1718 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1719 {
1720         union ich8_hws_flash_status hsfsts;
1721         s32 ret_val = -E1000_ERR_NVM;
1722         s32 i = 0;
1723
1724         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1725
1726         /* Check if the flash descriptor is valid */
1727         if (hsfsts.hsf_status.fldesvalid == 0) {
1728                 hw_dbg(hw, "Flash descriptor invalid.  "
1729                          "SW Sequencing must be used.");
1730                 return -E1000_ERR_NVM;
1731         }
1732
1733         /* Clear FCERR and DAEL in hw status by writing 1 */
1734         hsfsts.hsf_status.flcerr = 1;
1735         hsfsts.hsf_status.dael = 1;
1736
1737         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1738
1739         /*
1740          * Either we should have a hardware SPI cycle in progress
1741          * bit to check against, in order to start a new cycle or
1742          * FDONE bit should be changed in the hardware so that it
1743          * is 1 after hardware reset, which can then be used as an
1744          * indication whether a cycle is in progress or has been
1745          * completed.
1746          */
1747
1748         if (hsfsts.hsf_status.flcinprog == 0) {
1749                 /*
1750                  * There is no cycle running at present,
1751                  * so we can start a cycle
1752                  * Begin by setting Flash Cycle Done.
1753                  */
1754                 hsfsts.hsf_status.flcdone = 1;
1755                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1756                 ret_val = 0;
1757         } else {
1758                 /*
1759                  * otherwise poll for sometime so the current
1760                  * cycle has a chance to end before giving up.
1761                  */
1762                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1763                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1764                         if (hsfsts.hsf_status.flcinprog == 0) {
1765                                 ret_val = 0;
1766                                 break;
1767                         }
1768                         udelay(1);
1769                 }
1770                 if (ret_val == 0) {
1771                         /*
1772                          * Successful in waiting for previous cycle to timeout,
1773                          * now set the Flash Cycle Done.
1774                          */
1775                         hsfsts.hsf_status.flcdone = 1;
1776                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1777                 } else {
1778                         hw_dbg(hw, "Flash controller busy, cannot get access");
1779                 }
1780         }
1781
1782         return ret_val;
1783 }
1784
1785 /**
1786  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1787  *  @hw: pointer to the HW structure
1788  *  @timeout: maximum time to wait for completion
1789  *
1790  *  This function starts a flash cycle and waits for its completion.
1791  **/
1792 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1793 {
1794         union ich8_hws_flash_ctrl hsflctl;
1795         union ich8_hws_flash_status hsfsts;
1796         s32 ret_val = -E1000_ERR_NVM;
1797         u32 i = 0;
1798
1799         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1800         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1801         hsflctl.hsf_ctrl.flcgo = 1;
1802         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1803
1804         /* wait till FDONE bit is set to 1 */
1805         do {
1806                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1807                 if (hsfsts.hsf_status.flcdone == 1)
1808                         break;
1809                 udelay(1);
1810         } while (i++ < timeout);
1811
1812         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1813                 return 0;
1814
1815         return ret_val;
1816 }
1817
1818 /**
1819  *  e1000_read_flash_word_ich8lan - Read word from flash
1820  *  @hw: pointer to the HW structure
1821  *  @offset: offset to data location
1822  *  @data: pointer to the location for storing the data
1823  *
1824  *  Reads the flash word at offset into data.  Offset is converted
1825  *  to bytes before read.
1826  **/
1827 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1828                                          u16 *data)
1829 {
1830         /* Must convert offset into bytes. */
1831         offset <<= 1;
1832
1833         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1834 }
1835
1836 /**
1837  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1838  *  @hw: pointer to the HW structure
1839  *  @offset: The offset of the byte to read.
1840  *  @data: Pointer to a byte to store the value read.
1841  *
1842  *  Reads a single byte from the NVM using the flash access registers.
1843  **/
1844 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1845                                          u8 *data)
1846 {
1847         s32 ret_val;
1848         u16 word = 0;
1849
1850         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1851         if (ret_val)
1852                 return ret_val;
1853
1854         *data = (u8)word;
1855
1856         return 0;
1857 }
1858
1859 /**
1860  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1861  *  @hw: pointer to the HW structure
1862  *  @offset: The offset (in bytes) of the byte or word to read.
1863  *  @size: Size of data to read, 1=byte 2=word
1864  *  @data: Pointer to the word to store the value read.
1865  *
1866  *  Reads a byte or word from the NVM using the flash access registers.
1867  **/
1868 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1869                                          u8 size, u16 *data)
1870 {
1871         union ich8_hws_flash_status hsfsts;
1872         union ich8_hws_flash_ctrl hsflctl;
1873         u32 flash_linear_addr;
1874         u32 flash_data = 0;
1875         s32 ret_val = -E1000_ERR_NVM;
1876         u8 count = 0;
1877
1878         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1879                 return -E1000_ERR_NVM;
1880
1881         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1882                             hw->nvm.flash_base_addr;
1883
1884         do {
1885                 udelay(1);
1886                 /* Steps */
1887                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1888                 if (ret_val != 0)
1889                         break;
1890
1891                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1892                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1893                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1894                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1895                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1896
1897                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1898
1899                 ret_val = e1000_flash_cycle_ich8lan(hw,
1900                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1901
1902                 /*
1903                  * Check if FCERR is set to 1, if set to 1, clear it
1904                  * and try the whole sequence a few more times, else
1905                  * read in (shift in) the Flash Data0, the order is
1906                  * least significant byte first msb to lsb
1907                  */
1908                 if (ret_val == 0) {
1909                         flash_data = er32flash(ICH_FLASH_FDATA0);
1910                         if (size == 1) {
1911                                 *data = (u8)(flash_data & 0x000000FF);
1912                         } else if (size == 2) {
1913                                 *data = (u16)(flash_data & 0x0000FFFF);
1914                         }
1915                         break;
1916                 } else {
1917                         /*
1918                          * If we've gotten here, then things are probably
1919                          * completely hosed, but if the error condition is
1920                          * detected, it won't hurt to give it another try...
1921                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1922                          */
1923                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1924                         if (hsfsts.hsf_status.flcerr == 1) {
1925                                 /* Repeat for some time before giving up. */
1926                                 continue;
1927                         } else if (hsfsts.hsf_status.flcdone == 0) {
1928                                 hw_dbg(hw, "Timeout error - flash cycle "
1929                                          "did not complete.");
1930                                 break;
1931                         }
1932                 }
1933         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1934
1935         return ret_val;
1936 }
1937
1938 /**
1939  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1940  *  @hw: pointer to the HW structure
1941  *  @offset: The offset (in bytes) of the word(s) to write.
1942  *  @words: Size of data to write in words
1943  *  @data: Pointer to the word(s) to write at offset.
1944  *
1945  *  Writes a byte or word to the NVM using the flash access registers.
1946  **/
1947 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1948                                    u16 *data)
1949 {
1950         struct e1000_nvm_info *nvm = &hw->nvm;
1951         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1952         u16 i;
1953
1954         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1955             (words == 0)) {
1956                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1957                 return -E1000_ERR_NVM;
1958         }
1959
1960         nvm->ops.acquire_nvm(hw);
1961
1962         for (i = 0; i < words; i++) {
1963                 dev_spec->shadow_ram[offset+i].modified = 1;
1964                 dev_spec->shadow_ram[offset+i].value = data[i];
1965         }
1966
1967         nvm->ops.release_nvm(hw);
1968
1969         return 0;
1970 }
1971
1972 /**
1973  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1974  *  @hw: pointer to the HW structure
1975  *
1976  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1977  *  which writes the checksum to the shadow ram.  The changes in the shadow
1978  *  ram are then committed to the EEPROM by processing each bank at a time
1979  *  checking for the modified bit and writing only the pending changes.
1980  *  After a successful commit, the shadow ram is cleared and is ready for
1981  *  future writes.
1982  **/
1983 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1984 {
1985         struct e1000_nvm_info *nvm = &hw->nvm;
1986         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1987         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1988         s32 ret_val;
1989         u16 data;
1990
1991         ret_val = e1000e_update_nvm_checksum_generic(hw);
1992         if (ret_val)
1993                 goto out;
1994
1995         if (nvm->type != e1000_nvm_flash_sw)
1996                 goto out;
1997
1998         nvm->ops.acquire_nvm(hw);
1999
2000         /*
2001          * We're writing to the opposite bank so if we're on bank 1,
2002          * write to bank 0 etc.  We also need to erase the segment that
2003          * is going to be written
2004          */
2005         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2006         if (ret_val) {
2007                 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
2008                 bank = 0;
2009         }
2010
2011         if (bank == 0) {
2012                 new_bank_offset = nvm->flash_bank_size;
2013                 old_bank_offset = 0;
2014                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2015                 if (ret_val) {
2016                         nvm->ops.release_nvm(hw);
2017                         goto out;
2018                 }
2019         } else {
2020                 old_bank_offset = nvm->flash_bank_size;
2021                 new_bank_offset = 0;
2022                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2023                 if (ret_val) {
2024                         nvm->ops.release_nvm(hw);
2025                         goto out;
2026                 }
2027         }
2028
2029         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2030                 /*
2031                  * Determine whether to write the value stored
2032                  * in the other NVM bank or a modified value stored
2033                  * in the shadow RAM
2034                  */
2035                 if (dev_spec->shadow_ram[i].modified) {
2036                         data = dev_spec->shadow_ram[i].value;
2037                 } else {
2038                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2039                                                                 old_bank_offset,
2040                                                                 &data);
2041                         if (ret_val)
2042                                 break;
2043                 }
2044
2045                 /*
2046                  * If the word is 0x13, then make sure the signature bits
2047                  * (15:14) are 11b until the commit has completed.
2048                  * This will allow us to write 10b which indicates the
2049                  * signature is valid.  We want to do this after the write
2050                  * has completed so that we don't mark the segment valid
2051                  * while the write is still in progress
2052                  */
2053                 if (i == E1000_ICH_NVM_SIG_WORD)
2054                         data |= E1000_ICH_NVM_SIG_MASK;
2055
2056                 /* Convert offset to bytes. */
2057                 act_offset = (i + new_bank_offset) << 1;
2058
2059                 udelay(100);
2060                 /* Write the bytes to the new bank. */
2061                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2062                                                                act_offset,
2063                                                                (u8)data);
2064                 if (ret_val)
2065                         break;
2066
2067                 udelay(100);
2068                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2069                                                           act_offset + 1,
2070                                                           (u8)(data >> 8));
2071                 if (ret_val)
2072                         break;
2073         }
2074
2075         /*
2076          * Don't bother writing the segment valid bits if sector
2077          * programming failed.
2078          */
2079         if (ret_val) {
2080                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2081                 hw_dbg(hw, "Flash commit failed.\n");
2082                 nvm->ops.release_nvm(hw);
2083                 goto out;
2084         }
2085
2086         /*
2087          * Finally validate the new segment by setting bit 15:14
2088          * to 10b in word 0x13 , this can be done without an
2089          * erase as well since these bits are 11 to start with
2090          * and we need to change bit 14 to 0b
2091          */
2092         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2093         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2094         if (ret_val) {
2095                 nvm->ops.release_nvm(hw);
2096                 goto out;
2097         }
2098         data &= 0xBFFF;
2099         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2100                                                        act_offset * 2 + 1,
2101                                                        (u8)(data >> 8));
2102         if (ret_val) {
2103                 nvm->ops.release_nvm(hw);
2104                 goto out;
2105         }
2106
2107         /*
2108          * And invalidate the previously valid segment by setting
2109          * its signature word (0x13) high_byte to 0b. This can be
2110          * done without an erase because flash erase sets all bits
2111          * to 1's. We can write 1's to 0's without an erase
2112          */
2113         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2114         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2115         if (ret_val) {
2116                 nvm->ops.release_nvm(hw);
2117                 goto out;
2118         }
2119
2120         /* Great!  Everything worked, we can now clear the cached entries. */
2121         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2122                 dev_spec->shadow_ram[i].modified = 0;
2123                 dev_spec->shadow_ram[i].value = 0xFFFF;
2124         }
2125
2126         nvm->ops.release_nvm(hw);
2127
2128         /*
2129          * Reload the EEPROM, or else modifications will not appear
2130          * until after the next adapter reset.
2131          */
2132         e1000e_reload_nvm(hw);
2133         msleep(10);
2134
2135 out:
2136         if (ret_val)
2137                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
2138
2139         return ret_val;
2140 }
2141
2142 /**
2143  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2144  *  @hw: pointer to the HW structure
2145  *
2146  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2147  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2148  *  calculated, in which case we need to calculate the checksum and set bit 6.
2149  **/
2150 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2151 {
2152         s32 ret_val;
2153         u16 data;
2154
2155         /*
2156          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2157          * needs to be fixed.  This bit is an indication that the NVM
2158          * was prepared by OEM software and did not calculate the
2159          * checksum...a likely scenario.
2160          */
2161         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2162         if (ret_val)
2163                 return ret_val;
2164
2165         if ((data & 0x40) == 0) {
2166                 data |= 0x40;
2167                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2168                 if (ret_val)
2169                         return ret_val;
2170                 ret_val = e1000e_update_nvm_checksum(hw);
2171                 if (ret_val)
2172                         return ret_val;
2173         }
2174
2175         return e1000e_validate_nvm_checksum_generic(hw);
2176 }
2177
2178 /**
2179  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2180  *  @hw: pointer to the HW structure
2181  *
2182  *  To prevent malicious write/erase of the NVM, set it to be read-only
2183  *  so that the hardware ignores all write/erase cycles of the NVM via
2184  *  the flash control registers.  The shadow-ram copy of the NVM will
2185  *  still be updated, however any updates to this copy will not stick
2186  *  across driver reloads.
2187  **/
2188 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2189 {
2190         struct e1000_nvm_info *nvm = &hw->nvm;
2191         union ich8_flash_protected_range pr0;
2192         union ich8_hws_flash_status hsfsts;
2193         u32 gfpreg;
2194
2195         nvm->ops.acquire_nvm(hw);
2196
2197         gfpreg = er32flash(ICH_FLASH_GFPREG);
2198
2199         /* Write-protect GbE Sector of NVM */
2200         pr0.regval = er32flash(ICH_FLASH_PR0);
2201         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2202         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2203         pr0.range.wpe = true;
2204         ew32flash(ICH_FLASH_PR0, pr0.regval);
2205
2206         /*
2207          * Lock down a subset of GbE Flash Control Registers, e.g.
2208          * PR0 to prevent the write-protection from being lifted.
2209          * Once FLOCKDN is set, the registers protected by it cannot
2210          * be written until FLOCKDN is cleared by a hardware reset.
2211          */
2212         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2213         hsfsts.hsf_status.flockdn = true;
2214         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2215
2216         nvm->ops.release_nvm(hw);
2217 }
2218
2219 /**
2220  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2221  *  @hw: pointer to the HW structure
2222  *  @offset: The offset (in bytes) of the byte/word to read.
2223  *  @size: Size of data to read, 1=byte 2=word
2224  *  @data: The byte(s) to write to the NVM.
2225  *
2226  *  Writes one/two bytes to the NVM using the flash access registers.
2227  **/
2228 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2229                                           u8 size, u16 data)
2230 {
2231         union ich8_hws_flash_status hsfsts;
2232         union ich8_hws_flash_ctrl hsflctl;
2233         u32 flash_linear_addr;
2234         u32 flash_data = 0;
2235         s32 ret_val;
2236         u8 count = 0;
2237
2238         if (size < 1 || size > 2 || data > size * 0xff ||
2239             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2240                 return -E1000_ERR_NVM;
2241
2242         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2243                             hw->nvm.flash_base_addr;
2244
2245         do {
2246                 udelay(1);
2247                 /* Steps */
2248                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2249                 if (ret_val)
2250                         break;
2251
2252                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2253                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2254                 hsflctl.hsf_ctrl.fldbcount = size -1;
2255                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2256                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2257
2258                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2259
2260                 if (size == 1)
2261                         flash_data = (u32)data & 0x00FF;
2262                 else
2263                         flash_data = (u32)data;
2264
2265                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2266
2267                 /*
2268                  * check if FCERR is set to 1 , if set to 1, clear it
2269                  * and try the whole sequence a few more times else done
2270                  */
2271                 ret_val = e1000_flash_cycle_ich8lan(hw,
2272                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2273                 if (!ret_val)
2274                         break;
2275
2276                 /*
2277                  * If we're here, then things are most likely
2278                  * completely hosed, but if the error condition
2279                  * is detected, it won't hurt to give it another
2280                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2281                  */
2282                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2283                 if (hsfsts.hsf_status.flcerr == 1)
2284                         /* Repeat for some time before giving up. */
2285                         continue;
2286                 if (hsfsts.hsf_status.flcdone == 0) {
2287                         hw_dbg(hw, "Timeout error - flash cycle "
2288                                  "did not complete.");
2289                         break;
2290                 }
2291         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2292
2293         return ret_val;
2294 }
2295
2296 /**
2297  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2298  *  @hw: pointer to the HW structure
2299  *  @offset: The index of the byte to read.
2300  *  @data: The byte to write to the NVM.
2301  *
2302  *  Writes a single byte to the NVM using the flash access registers.
2303  **/
2304 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2305                                           u8 data)
2306 {
2307         u16 word = (u16)data;
2308
2309         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2310 }
2311
2312 /**
2313  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2314  *  @hw: pointer to the HW structure
2315  *  @offset: The offset of the byte to write.
2316  *  @byte: The byte to write to the NVM.
2317  *
2318  *  Writes a single byte to the NVM using the flash access registers.
2319  *  Goes through a retry algorithm before giving up.
2320  **/
2321 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2322                                                 u32 offset, u8 byte)
2323 {
2324         s32 ret_val;
2325         u16 program_retries;
2326
2327         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2328         if (!ret_val)
2329                 return ret_val;
2330
2331         for (program_retries = 0; program_retries < 100; program_retries++) {
2332                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
2333                 udelay(100);
2334                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2335                 if (!ret_val)
2336                         break;
2337         }
2338         if (program_retries == 100)
2339                 return -E1000_ERR_NVM;
2340
2341         return 0;
2342 }
2343
2344 /**
2345  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2346  *  @hw: pointer to the HW structure
2347  *  @bank: 0 for first bank, 1 for second bank, etc.
2348  *
2349  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2350  *  bank N is 4096 * N + flash_reg_addr.
2351  **/
2352 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2353 {
2354         struct e1000_nvm_info *nvm = &hw->nvm;
2355         union ich8_hws_flash_status hsfsts;
2356         union ich8_hws_flash_ctrl hsflctl;
2357         u32 flash_linear_addr;
2358         /* bank size is in 16bit words - adjust to bytes */
2359         u32 flash_bank_size = nvm->flash_bank_size * 2;
2360         s32 ret_val;
2361         s32 count = 0;
2362         s32 iteration;
2363         s32 sector_size;
2364         s32 j;
2365
2366         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2367
2368         /*
2369          * Determine HW Sector size: Read BERASE bits of hw flash status
2370          * register
2371          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2372          *     consecutive sectors.  The start index for the nth Hw sector
2373          *     can be calculated as = bank * 4096 + n * 256
2374          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2375          *     The start index for the nth Hw sector can be calculated
2376          *     as = bank * 4096
2377          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2378          *     (ich9 only, otherwise error condition)
2379          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2380          */
2381         switch (hsfsts.hsf_status.berasesz) {
2382         case 0:
2383                 /* Hw sector size 256 */
2384                 sector_size = ICH_FLASH_SEG_SIZE_256;
2385                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2386                 break;
2387         case 1:
2388                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2389                 iteration = 1;
2390                 break;
2391         case 2:
2392                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2393                 iteration = 1;
2394                 break;
2395         case 3:
2396                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2397                 iteration = 1;
2398                 break;
2399         default:
2400                 return -E1000_ERR_NVM;
2401         }
2402
2403         /* Start with the base address, then add the sector offset. */
2404         flash_linear_addr = hw->nvm.flash_base_addr;
2405         flash_linear_addr += (bank) ? flash_bank_size : 0;
2406
2407         for (j = 0; j < iteration ; j++) {
2408                 do {
2409                         /* Steps */
2410                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2411                         if (ret_val)
2412                                 return ret_val;
2413
2414                         /*
2415                          * Write a value 11 (block Erase) in Flash
2416                          * Cycle field in hw flash control
2417                          */
2418                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2419                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2420                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2421
2422                         /*
2423                          * Write the last 24 bits of an index within the
2424                          * block into Flash Linear address field in Flash
2425                          * Address.
2426                          */
2427                         flash_linear_addr += (j * sector_size);
2428                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2429
2430                         ret_val = e1000_flash_cycle_ich8lan(hw,
2431                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2432                         if (ret_val == 0)
2433                                 break;
2434
2435                         /*
2436                          * Check if FCERR is set to 1.  If 1,
2437                          * clear it and try the whole sequence
2438                          * a few more times else Done
2439                          */
2440                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2441                         if (hsfsts.hsf_status.flcerr == 1)
2442                                 /* repeat for some time before giving up */
2443                                 continue;
2444                         else if (hsfsts.hsf_status.flcdone == 0)
2445                                 return ret_val;
2446                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2447         }
2448
2449         return 0;
2450 }
2451
2452 /**
2453  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2454  *  @hw: pointer to the HW structure
2455  *  @data: Pointer to the LED settings
2456  *
2457  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2458  *  settings is all 0's or F's, set the LED default to a valid LED default
2459  *  setting.
2460  **/
2461 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2462 {
2463         s32 ret_val;
2464
2465         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2466         if (ret_val) {
2467                 hw_dbg(hw, "NVM Read Error\n");
2468                 return ret_val;
2469         }
2470
2471         if (*data == ID_LED_RESERVED_0000 ||
2472             *data == ID_LED_RESERVED_FFFF)
2473                 *data = ID_LED_DEFAULT_ICH8LAN;
2474
2475         return 0;
2476 }
2477
2478 /**
2479  *  e1000_id_led_init_pchlan - store LED configurations
2480  *  @hw: pointer to the HW structure
2481  *
2482  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2483  *  the PHY LED configuration register.
2484  *
2485  *  PCH also does not have an "always on" or "always off" mode which
2486  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2487  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2488  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2489  *  link based on logic in e1000_led_[on|off]_pchlan().
2490  **/
2491 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2492 {
2493         struct e1000_mac_info *mac = &hw->mac;
2494         s32 ret_val;
2495         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2496         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2497         u16 data, i, temp, shift;
2498
2499         /* Get default ID LED modes */
2500         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2501         if (ret_val)
2502                 goto out;
2503
2504         mac->ledctl_default = er32(LEDCTL);
2505         mac->ledctl_mode1 = mac->ledctl_default;
2506         mac->ledctl_mode2 = mac->ledctl_default;
2507
2508         for (i = 0; i < 4; i++) {
2509                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2510                 shift = (i * 5);
2511                 switch (temp) {
2512                 case ID_LED_ON1_DEF2:
2513                 case ID_LED_ON1_ON2:
2514                 case ID_LED_ON1_OFF2:
2515                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2516                         mac->ledctl_mode1 |= (ledctl_on << shift);
2517                         break;
2518                 case ID_LED_OFF1_DEF2:
2519                 case ID_LED_OFF1_ON2:
2520                 case ID_LED_OFF1_OFF2:
2521                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2522                         mac->ledctl_mode1 |= (ledctl_off << shift);
2523                         break;
2524                 default:
2525                         /* Do nothing */
2526                         break;
2527                 }
2528                 switch (temp) {
2529                 case ID_LED_DEF1_ON2:
2530                 case ID_LED_ON1_ON2:
2531                 case ID_LED_OFF1_ON2:
2532                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2533                         mac->ledctl_mode2 |= (ledctl_on << shift);
2534                         break;
2535                 case ID_LED_DEF1_OFF2:
2536                 case ID_LED_ON1_OFF2:
2537                 case ID_LED_OFF1_OFF2:
2538                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2539                         mac->ledctl_mode2 |= (ledctl_off << shift);
2540                         break;
2541                 default:
2542                         /* Do nothing */
2543                         break;
2544                 }
2545         }
2546
2547 out:
2548         return ret_val;
2549 }
2550
2551 /**
2552  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2553  *  @hw: pointer to the HW structure
2554  *
2555  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2556  *  register, so the the bus width is hard coded.
2557  **/
2558 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2559 {
2560         struct e1000_bus_info *bus = &hw->bus;
2561         s32 ret_val;
2562
2563         ret_val = e1000e_get_bus_info_pcie(hw);
2564
2565         /*
2566          * ICH devices are "PCI Express"-ish.  They have
2567          * a configuration space, but do not contain
2568          * PCI Express Capability registers, so bus width
2569          * must be hardcoded.
2570          */
2571         if (bus->width == e1000_bus_width_unknown)
2572                 bus->width = e1000_bus_width_pcie_x1;
2573
2574         return ret_val;
2575 }
2576
2577 /**
2578  *  e1000_reset_hw_ich8lan - Reset the hardware
2579  *  @hw: pointer to the HW structure
2580  *
2581  *  Does a full reset of the hardware which includes a reset of the PHY and
2582  *  MAC.
2583  **/
2584 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2585 {
2586         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2587         u16 reg;
2588         u32 ctrl, icr, kab;
2589         s32 ret_val;
2590
2591         /*
2592          * Prevent the PCI-E bus from sticking if there is no TLP connection
2593          * on the last TLP read/write transaction when MAC is reset.
2594          */
2595         ret_val = e1000e_disable_pcie_master(hw);
2596         if (ret_val) {
2597                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2598         }
2599
2600         hw_dbg(hw, "Masking off all interrupts\n");
2601         ew32(IMC, 0xffffffff);
2602
2603         /*
2604          * Disable the Transmit and Receive units.  Then delay to allow
2605          * any pending transactions to complete before we hit the MAC
2606          * with the global reset.
2607          */
2608         ew32(RCTL, 0);
2609         ew32(TCTL, E1000_TCTL_PSP);
2610         e1e_flush();
2611
2612         msleep(10);
2613
2614         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2615         if (hw->mac.type == e1000_ich8lan) {
2616                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2617                 ew32(PBA, E1000_PBA_8K);
2618                 /* Set Packet Buffer Size to 16k. */
2619                 ew32(PBS, E1000_PBS_16K);
2620         }
2621
2622         if (hw->mac.type == e1000_pchlan) {
2623                 /* Save the NVM K1 bit setting*/
2624                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2625                 if (ret_val)
2626                         return ret_val;
2627
2628                 if (reg & E1000_NVM_K1_ENABLE)
2629                         dev_spec->nvm_k1_enabled = true;
2630                 else
2631                         dev_spec->nvm_k1_enabled = false;
2632         }
2633
2634         ctrl = er32(CTRL);
2635
2636         if (!e1000_check_reset_block(hw)) {
2637                 /* Clear PHY Reset Asserted bit */
2638                 if (hw->mac.type >= e1000_pchlan) {
2639                         u32 status = er32(STATUS);
2640                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2641                 }
2642
2643                 /*
2644                  * PHY HW reset requires MAC CORE reset at the same
2645                  * time to make sure the interface between MAC and the
2646                  * external PHY is reset.
2647                  */
2648                 ctrl |= E1000_CTRL_PHY_RST;
2649         }
2650         ret_val = e1000_acquire_swflag_ich8lan(hw);
2651         /* Whether or not the swflag was acquired, we need to reset the part */
2652         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2653         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2654         msleep(20);
2655
2656         if (!ret_val)
2657                 e1000_release_swflag_ich8lan(hw);
2658
2659         if (ctrl & E1000_CTRL_PHY_RST)
2660                 ret_val = hw->phy.ops.get_cfg_done(hw);
2661
2662         if (hw->mac.type >= e1000_ich10lan) {
2663                 e1000_lan_init_done_ich8lan(hw);
2664         } else {
2665                 ret_val = e1000e_get_auto_rd_done(hw);
2666                 if (ret_val) {
2667                         /*
2668                          * When auto config read does not complete, do not
2669                          * return with an error. This can happen in situations
2670                          * where there is no eeprom and prevents getting link.
2671                          */
2672                         hw_dbg(hw, "Auto Read Done did not complete\n");
2673                 }
2674         }
2675         /* Dummy read to clear the phy wakeup bit after lcd reset */
2676         if (hw->mac.type == e1000_pchlan)
2677                 e1e_rphy(hw, BM_WUC, &reg);
2678
2679         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2680         if (ret_val)
2681                 goto out;
2682
2683         if (hw->mac.type == e1000_pchlan) {
2684                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2685                 if (ret_val)
2686                         goto out;
2687         }
2688         /*
2689          * For PCH, this write will make sure that any noise
2690          * will be detected as a CRC error and be dropped rather than show up
2691          * as a bad packet to the DMA engine.
2692          */
2693         if (hw->mac.type == e1000_pchlan)
2694                 ew32(CRC_OFFSET, 0x65656565);
2695
2696         ew32(IMC, 0xffffffff);
2697         icr = er32(ICR);
2698
2699         kab = er32(KABGTXD);
2700         kab |= E1000_KABGTXD_BGSQLBIAS;
2701         ew32(KABGTXD, kab);
2702
2703         if (hw->mac.type == e1000_pchlan)
2704                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2705
2706 out:
2707         return ret_val;
2708 }
2709
2710 /**
2711  *  e1000_init_hw_ich8lan - Initialize the hardware
2712  *  @hw: pointer to the HW structure
2713  *
2714  *  Prepares the hardware for transmit and receive by doing the following:
2715  *   - initialize hardware bits
2716  *   - initialize LED identification
2717  *   - setup receive address registers
2718  *   - setup flow control
2719  *   - setup transmit descriptors
2720  *   - clear statistics
2721  **/
2722 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2723 {
2724         struct e1000_mac_info *mac = &hw->mac;
2725         u32 ctrl_ext, txdctl, snoop;
2726         s32 ret_val;
2727         u16 i;
2728
2729         e1000_initialize_hw_bits_ich8lan(hw);
2730
2731         /* Initialize identification LED */
2732         ret_val = mac->ops.id_led_init(hw);
2733         if (ret_val) {
2734                 hw_dbg(hw, "Error initializing identification LED\n");
2735                 return ret_val;
2736         }
2737
2738         /* Setup the receive address. */
2739         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2740
2741         /* Zero out the Multicast HASH table */
2742         hw_dbg(hw, "Zeroing the MTA\n");
2743         for (i = 0; i < mac->mta_reg_count; i++)
2744                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2745
2746         /*
2747          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2748          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2749          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2750          */
2751         if (hw->phy.type == e1000_phy_82578) {
2752                 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2753                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2754                 if (ret_val)
2755                         return ret_val;
2756         }
2757
2758         /* Setup link and flow control */
2759         ret_val = e1000_setup_link_ich8lan(hw);
2760
2761         /* Set the transmit descriptor write-back policy for both queues */
2762         txdctl = er32(TXDCTL(0));
2763         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2764                  E1000_TXDCTL_FULL_TX_DESC_WB;
2765         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2766                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2767         ew32(TXDCTL(0), txdctl);
2768         txdctl = er32(TXDCTL(1));
2769         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2770                  E1000_TXDCTL_FULL_TX_DESC_WB;
2771         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2772                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2773         ew32(TXDCTL(1), txdctl);
2774
2775         /*
2776          * ICH8 has opposite polarity of no_snoop bits.
2777          * By default, we should use snoop behavior.
2778          */
2779         if (mac->type == e1000_ich8lan)
2780                 snoop = PCIE_ICH8_SNOOP_ALL;
2781         else
2782                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2783         e1000e_set_pcie_no_snoop(hw, snoop);
2784
2785         ctrl_ext = er32(CTRL_EXT);
2786         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2787         ew32(CTRL_EXT, ctrl_ext);
2788
2789         /*
2790          * Clear all of the statistics registers (clear on read).  It is
2791          * important that we do this after we have tried to establish link
2792          * because the symbol error count will increment wildly if there
2793          * is no link.
2794          */
2795         e1000_clear_hw_cntrs_ich8lan(hw);
2796
2797         return 0;
2798 }
2799 /**
2800  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2801  *  @hw: pointer to the HW structure
2802  *
2803  *  Sets/Clears required hardware bits necessary for correctly setting up the
2804  *  hardware for transmit and receive.
2805  **/
2806 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2807 {
2808         u32 reg;
2809
2810         /* Extended Device Control */
2811         reg = er32(CTRL_EXT);
2812         reg |= (1 << 22);
2813         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2814         if (hw->mac.type >= e1000_pchlan)
2815                 reg |= E1000_CTRL_EXT_PHYPDEN;
2816         ew32(CTRL_EXT, reg);
2817
2818         /* Transmit Descriptor Control 0 */
2819         reg = er32(TXDCTL(0));
2820         reg |= (1 << 22);
2821         ew32(TXDCTL(0), reg);
2822
2823         /* Transmit Descriptor Control 1 */
2824         reg = er32(TXDCTL(1));
2825         reg |= (1 << 22);
2826         ew32(TXDCTL(1), reg);
2827
2828         /* Transmit Arbitration Control 0 */
2829         reg = er32(TARC(0));
2830         if (hw->mac.type == e1000_ich8lan)
2831                 reg |= (1 << 28) | (1 << 29);
2832         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2833         ew32(TARC(0), reg);
2834
2835         /* Transmit Arbitration Control 1 */
2836         reg = er32(TARC(1));
2837         if (er32(TCTL) & E1000_TCTL_MULR)
2838                 reg &= ~(1 << 28);
2839         else
2840                 reg |= (1 << 28);
2841         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2842         ew32(TARC(1), reg);
2843
2844         /* Device Status */
2845         if (hw->mac.type == e1000_ich8lan) {
2846                 reg = er32(STATUS);
2847                 reg &= ~(1 << 31);
2848                 ew32(STATUS, reg);
2849         }
2850 }
2851
2852 /**
2853  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2854  *  @hw: pointer to the HW structure
2855  *
2856  *  Determines which flow control settings to use, then configures flow
2857  *  control.  Calls the appropriate media-specific link configuration
2858  *  function.  Assuming the adapter has a valid link partner, a valid link
2859  *  should be established.  Assumes the hardware has previously been reset
2860  *  and the transmitter and receiver are not enabled.
2861  **/
2862 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2863 {
2864         s32 ret_val;
2865
2866         if (e1000_check_reset_block(hw))
2867                 return 0;
2868
2869         /*
2870          * ICH parts do not have a word in the NVM to determine
2871          * the default flow control setting, so we explicitly
2872          * set it to full.
2873          */
2874         if (hw->fc.requested_mode == e1000_fc_default) {
2875                 /* Workaround h/w hang when Tx flow control enabled */
2876                 if (hw->mac.type == e1000_pchlan)
2877                         hw->fc.requested_mode = e1000_fc_rx_pause;
2878                 else
2879                         hw->fc.requested_mode = e1000_fc_full;
2880         }
2881
2882         /*
2883          * Save off the requested flow control mode for use later.  Depending
2884          * on the link partner's capabilities, we may or may not use this mode.
2885          */
2886         hw->fc.current_mode = hw->fc.requested_mode;
2887
2888         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2889                 hw->fc.current_mode);
2890
2891         /* Continue to configure the copper link. */
2892         ret_val = e1000_setup_copper_link_ich8lan(hw);
2893         if (ret_val)
2894                 return ret_val;
2895
2896         ew32(FCTTV, hw->fc.pause_time);
2897         if ((hw->phy.type == e1000_phy_82578) ||
2898             (hw->phy.type == e1000_phy_82577)) {
2899                 ret_val = hw->phy.ops.write_phy_reg(hw,
2900                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2901                                              hw->fc.pause_time);
2902                 if (ret_val)
2903                         return ret_val;
2904         }
2905
2906         return e1000e_set_fc_watermarks(hw);
2907 }
2908
2909 /**
2910  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2911  *  @hw: pointer to the HW structure
2912  *
2913  *  Configures the kumeran interface to the PHY to wait the appropriate time
2914  *  when polling the PHY, then call the generic setup_copper_link to finish
2915  *  configuring the copper link.
2916  **/
2917 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2918 {
2919         u32 ctrl;
2920         s32 ret_val;
2921         u16 reg_data;
2922
2923         ctrl = er32(CTRL);
2924         ctrl |= E1000_CTRL_SLU;
2925         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2926         ew32(CTRL, ctrl);
2927
2928         /*
2929          * Set the mac to wait the maximum time between each iteration
2930          * and increase the max iterations when polling the phy;
2931          * this fixes erroneous timeouts at 10Mbps.
2932          */
2933         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2934         if (ret_val)
2935                 return ret_val;
2936         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2937         if (ret_val)
2938                 return ret_val;
2939         reg_data |= 0x3F;
2940         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2941         if (ret_val)
2942                 return ret_val;
2943
2944         switch (hw->phy.type) {
2945         case e1000_phy_igp_3:
2946                 ret_val = e1000e_copper_link_setup_igp(hw);
2947                 if (ret_val)
2948                         return ret_val;
2949                 break;
2950         case e1000_phy_bm:
2951         case e1000_phy_82578:
2952                 ret_val = e1000e_copper_link_setup_m88(hw);
2953                 if (ret_val)
2954                         return ret_val;
2955                 break;
2956         case e1000_phy_82577:
2957                 ret_val = e1000_copper_link_setup_82577(hw);
2958                 if (ret_val)
2959                         return ret_val;
2960                 break;
2961         case e1000_phy_ife:
2962                 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2963                                                &reg_data);
2964                 if (ret_val)
2965                         return ret_val;
2966
2967                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2968
2969                 switch (hw->phy.mdix) {
2970                 case 1:
2971                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2972                         break;
2973                 case 2:
2974                         reg_data |= IFE_PMC_FORCE_MDIX;
2975                         break;
2976                 case 0:
2977                 default:
2978                         reg_data |= IFE_PMC_AUTO_MDIX;
2979                         break;
2980                 }
2981                 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2982                                                 reg_data);
2983                 if (ret_val)
2984                         return ret_val;
2985                 break;
2986         default:
2987                 break;
2988         }
2989         return e1000e_setup_copper_link(hw);
2990 }
2991
2992 /**
2993  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2994  *  @hw: pointer to the HW structure
2995  *  @speed: pointer to store current link speed
2996  *  @duplex: pointer to store the current link duplex
2997  *
2998  *  Calls the generic get_speed_and_duplex to retrieve the current link
2999  *  information and then calls the Kumeran lock loss workaround for links at
3000  *  gigabit speeds.
3001  **/
3002 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3003                                           u16 *duplex)
3004 {
3005         s32 ret_val;
3006
3007         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3008         if (ret_val)
3009                 return ret_val;
3010
3011         if ((hw->mac.type == e1000_ich8lan) &&
3012             (hw->phy.type == e1000_phy_igp_3) &&
3013             (*speed == SPEED_1000)) {
3014                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3015         }
3016
3017         return ret_val;
3018 }
3019
3020 /**
3021  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3022  *  @hw: pointer to the HW structure
3023  *
3024  *  Work-around for 82566 Kumeran PCS lock loss:
3025  *  On link status change (i.e. PCI reset, speed change) and link is up and
3026  *  speed is gigabit-
3027  *    0) if workaround is optionally disabled do nothing
3028  *    1) wait 1ms for Kumeran link to come up
3029  *    2) check Kumeran Diagnostic register PCS lock loss bit
3030  *    3) if not set the link is locked (all is good), otherwise...
3031  *    4) reset the PHY
3032  *    5) repeat up to 10 times
3033  *  Note: this is only called for IGP3 copper when speed is 1gb.
3034  **/
3035 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3036 {
3037         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3038         u32 phy_ctrl;
3039         s32 ret_val;
3040         u16 i, data;
3041         bool link;
3042
3043         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3044                 return 0;
3045
3046         /*
3047          * Make sure link is up before proceeding.  If not just return.
3048          * Attempting this while link is negotiating fouled up link
3049          * stability
3050          */
3051         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3052         if (!link)
3053                 return 0;
3054
3055         for (i = 0; i < 10; i++) {
3056                 /* read once to clear */
3057                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3058                 if (ret_val)
3059                         return ret_val;
3060                 /* and again to get new status */
3061                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3062                 if (ret_val)
3063                         return ret_val;
3064
3065                 /* check for PCS lock */
3066                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3067                         return 0;
3068
3069                 /* Issue PHY reset */
3070                 e1000_phy_hw_reset(hw);
3071                 mdelay(5);
3072         }
3073         /* Disable GigE link negotiation */
3074         phy_ctrl = er32(PHY_CTRL);
3075         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3076                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3077         ew32(PHY_CTRL, phy_ctrl);
3078
3079         /*
3080          * Call gig speed drop workaround on Gig disable before accessing
3081          * any PHY registers
3082          */
3083         e1000e_gig_downshift_workaround_ich8lan(hw);
3084
3085         /* unable to acquire PCS lock */
3086         return -E1000_ERR_PHY;
3087 }
3088
3089 /**
3090  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3091  *  @hw: pointer to the HW structure
3092  *  @state: boolean value used to set the current Kumeran workaround state
3093  *
3094  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
3095  *  /disabled - FALSE).
3096  **/
3097 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3098                                                  bool state)
3099 {
3100         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3101
3102         if (hw->mac.type != e1000_ich8lan) {
3103                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
3104                 return;
3105         }
3106
3107         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3108 }
3109
3110 /**
3111  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3112  *  @hw: pointer to the HW structure
3113  *
3114  *  Workaround for 82566 power-down on D3 entry:
3115  *    1) disable gigabit link
3116  *    2) write VR power-down enable
3117  *    3) read it back
3118  *  Continue if successful, else issue LCD reset and repeat
3119  **/
3120 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3121 {
3122         u32 reg;
3123         u16 data;
3124         u8  retry = 0;
3125
3126         if (hw->phy.type != e1000_phy_igp_3)
3127                 return;
3128
3129         /* Try the workaround twice (if needed) */
3130         do {
3131                 /* Disable link */
3132                 reg = er32(PHY_CTRL);
3133                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3134                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3135                 ew32(PHY_CTRL, reg);
3136
3137                 /*
3138                  * Call gig speed drop workaround on Gig disable before
3139                  * accessing any PHY registers
3140                  */
3141                 if (hw->mac.type == e1000_ich8lan)
3142                         e1000e_gig_downshift_workaround_ich8lan(hw);
3143
3144                 /* Write VR power-down enable */
3145                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3146                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3147                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3148
3149                 /* Read it back and test */
3150                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3151                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3152                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3153                         break;
3154
3155                 /* Issue PHY reset and repeat at most one more time */
3156                 reg = er32(CTRL);
3157                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3158                 retry++;
3159         } while (retry);
3160 }
3161
3162 /**
3163  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3164  *  @hw: pointer to the HW structure
3165  *
3166  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3167  *  LPLU, Gig disable, MDIC PHY reset):
3168  *    1) Set Kumeran Near-end loopback
3169  *    2) Clear Kumeran Near-end loopback
3170  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3171  **/
3172 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3173 {
3174         s32 ret_val;
3175         u16 reg_data;
3176
3177         if ((hw->mac.type != e1000_ich8lan) ||
3178             (hw->phy.type != e1000_phy_igp_3))
3179                 return;
3180
3181         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3182                                       &reg_data);
3183         if (ret_val)
3184                 return;
3185         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3186         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3187                                        reg_data);
3188         if (ret_val)
3189                 return;
3190         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3191         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3192                                        reg_data);
3193 }
3194
3195 /**
3196  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3197  *  @hw: pointer to the HW structure
3198  *
3199  *  During S0 to Sx transition, it is possible the link remains at gig
3200  *  instead of negotiating to a lower speed.  Before going to Sx, set
3201  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3202  *  to a lower speed.
3203  *
3204  *  Should only be called for applicable parts.
3205  **/
3206 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3207 {
3208         u32 phy_ctrl;
3209
3210         switch (hw->mac.type) {
3211         case e1000_ich9lan:
3212         case e1000_ich10lan:
3213         case e1000_pchlan:
3214                 phy_ctrl = er32(PHY_CTRL);
3215                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3216                             E1000_PHY_CTRL_GBE_DISABLE;
3217                 ew32(PHY_CTRL, phy_ctrl);
3218
3219                 if (hw->mac.type == e1000_pchlan)
3220                         e1000_phy_hw_reset_ich8lan(hw);
3221         default:
3222                 break;
3223         }
3224
3225         return;
3226 }
3227
3228 /**
3229  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3230  *  @hw: pointer to the HW structure
3231  *
3232  *  Return the LED back to the default configuration.
3233  **/
3234 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3235 {
3236         if (hw->phy.type == e1000_phy_ife)
3237                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3238
3239         ew32(LEDCTL, hw->mac.ledctl_default);
3240         return 0;
3241 }
3242
3243 /**
3244  *  e1000_led_on_ich8lan - Turn LEDs on
3245  *  @hw: pointer to the HW structure
3246  *
3247  *  Turn on the LEDs.
3248  **/
3249 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3250 {
3251         if (hw->phy.type == e1000_phy_ife)
3252                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3253                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3254
3255         ew32(LEDCTL, hw->mac.ledctl_mode2);
3256         return 0;
3257 }
3258
3259 /**
3260  *  e1000_led_off_ich8lan - Turn LEDs off
3261  *  @hw: pointer to the HW structure
3262  *
3263  *  Turn off the LEDs.
3264  **/
3265 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3266 {
3267         if (hw->phy.type == e1000_phy_ife)
3268                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3269                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3270
3271         ew32(LEDCTL, hw->mac.ledctl_mode1);
3272         return 0;
3273 }
3274
3275 /**
3276  *  e1000_setup_led_pchlan - Configures SW controllable LED
3277  *  @hw: pointer to the HW structure
3278  *
3279  *  This prepares the SW controllable LED for use.
3280  **/
3281 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3282 {
3283         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3284                                         (u16)hw->mac.ledctl_mode1);
3285 }
3286
3287 /**
3288  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3289  *  @hw: pointer to the HW structure
3290  *
3291  *  Return the LED back to the default configuration.
3292  **/
3293 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3294 {
3295         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3296                                         (u16)hw->mac.ledctl_default);
3297 }
3298
3299 /**
3300  *  e1000_led_on_pchlan - Turn LEDs on
3301  *  @hw: pointer to the HW structure
3302  *
3303  *  Turn on the LEDs.
3304  **/
3305 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3306 {
3307         u16 data = (u16)hw->mac.ledctl_mode2;
3308         u32 i, led;
3309
3310         /*
3311          * If no link, then turn LED on by setting the invert bit
3312          * for each LED that's mode is "link_up" in ledctl_mode2.
3313          */
3314         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3315                 for (i = 0; i < 3; i++) {
3316                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3317                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3318                             E1000_LEDCTL_MODE_LINK_UP)
3319                                 continue;
3320                         if (led & E1000_PHY_LED0_IVRT)
3321                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3322                         else
3323                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3324                 }
3325         }
3326
3327         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3328 }
3329
3330 /**
3331  *  e1000_led_off_pchlan - Turn LEDs off
3332  *  @hw: pointer to the HW structure
3333  *
3334  *  Turn off the LEDs.
3335  **/
3336 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3337 {
3338         u16 data = (u16)hw->mac.ledctl_mode1;
3339         u32 i, led;
3340
3341         /*
3342          * If no link, then turn LED off by clearing the invert bit
3343          * for each LED that's mode is "link_up" in ledctl_mode1.
3344          */
3345         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3346                 for (i = 0; i < 3; i++) {
3347                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3348                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3349                             E1000_LEDCTL_MODE_LINK_UP)
3350                                 continue;
3351                         if (led & E1000_PHY_LED0_IVRT)
3352                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3353                         else
3354                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3355                 }
3356         }
3357
3358         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3359 }
3360
3361 /**
3362  *  e1000_get_cfg_done_ich8lan - Read config done bit
3363  *  @hw: pointer to the HW structure
3364  *
3365  *  Read the management control register for the config done bit for
3366  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3367  *  to read the config done bit, so an error is *ONLY* logged and returns
3368  *  0.  If we were to return with error, EEPROM-less silicon
3369  *  would not be able to be reset or change link.
3370  **/
3371 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3372 {
3373         u32 bank = 0;
3374
3375         if (hw->mac.type >= e1000_pchlan) {
3376                 u32 status = er32(STATUS);
3377
3378                 if (status & E1000_STATUS_PHYRA)
3379                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3380                 else
3381                         hw_dbg(hw,
3382                                "PHY Reset Asserted not set - needs delay\n");
3383         }
3384
3385         e1000e_get_cfg_done(hw);
3386
3387         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3388         if ((hw->mac.type != e1000_ich10lan) &&
3389             (hw->mac.type != e1000_pchlan)) {
3390                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3391                     (hw->phy.type == e1000_phy_igp_3)) {
3392                         e1000e_phy_init_script_igp3(hw);
3393                 }
3394         } else {
3395                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3396                         /* Maybe we should do a basic PHY config */
3397                         hw_dbg(hw, "EEPROM not present\n");
3398                         return -E1000_ERR_CONFIG;
3399                 }
3400         }
3401
3402         return 0;
3403 }
3404
3405 /**
3406  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3407  *  @hw: pointer to the HW structure
3408  *
3409  *  Clears hardware counters specific to the silicon family and calls
3410  *  clear_hw_cntrs_generic to clear all general purpose counters.
3411  **/
3412 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3413 {
3414         u32 temp;
3415         u16 phy_data;
3416
3417         e1000e_clear_hw_cntrs_base(hw);
3418
3419         temp = er32(ALGNERRC);
3420         temp = er32(RXERRC);
3421         temp = er32(TNCRS);
3422         temp = er32(CEXTERR);
3423         temp = er32(TSCTC);
3424         temp = er32(TSCTFC);
3425
3426         temp = er32(MGTPRC);
3427         temp = er32(MGTPDC);
3428         temp = er32(MGTPTC);
3429
3430         temp = er32(IAC);
3431         temp = er32(ICRXOC);
3432
3433         /* Clear PHY statistics registers */
3434         if ((hw->phy.type == e1000_phy_82578) ||
3435             (hw->phy.type == e1000_phy_82577)) {
3436                 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3437                 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3438                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3439                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3440                 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3441                 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3442                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3443                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3444                 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3445                 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3446                 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3447                 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3448                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3449                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3450         }
3451 }
3452
3453 static struct e1000_mac_operations ich8_mac_ops = {
3454         .id_led_init            = e1000e_id_led_init,
3455         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3456         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3457         /* cleanup_led dependent on mac type */
3458         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3459         .get_bus_info           = e1000_get_bus_info_ich8lan,
3460         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3461         /* led_on dependent on mac type */
3462         /* led_off dependent on mac type */
3463         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3464         .reset_hw               = e1000_reset_hw_ich8lan,
3465         .init_hw                = e1000_init_hw_ich8lan,
3466         .setup_link             = e1000_setup_link_ich8lan,
3467         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3468         /* id_led_init dependent on mac type */
3469 };
3470
3471 static struct e1000_phy_operations ich8_phy_ops = {
3472         .acquire_phy            = e1000_acquire_swflag_ich8lan,
3473         .check_reset_block      = e1000_check_reset_block_ich8lan,
3474         .commit_phy             = NULL,
3475         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
3476         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3477         .get_cable_length       = e1000e_get_cable_length_igp_2,
3478         .get_phy_info           = e1000_get_phy_info_ich8lan,
3479         .read_phy_reg           = e1000e_read_phy_reg_igp,
3480         .release_phy            = e1000_release_swflag_ich8lan,
3481         .reset_phy              = e1000_phy_hw_reset_ich8lan,
3482         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3483         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3484         .write_phy_reg          = e1000e_write_phy_reg_igp,
3485 };
3486
3487 static struct e1000_nvm_operations ich8_nvm_ops = {
3488         .acquire_nvm            = e1000_acquire_nvm_ich8lan,
3489         .read_nvm               = e1000_read_nvm_ich8lan,
3490         .release_nvm            = e1000_release_nvm_ich8lan,
3491         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
3492         .valid_led_default      = e1000_valid_led_default_ich8lan,
3493         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
3494         .write_nvm              = e1000_write_nvm_ich8lan,
3495 };
3496
3497 struct e1000_info e1000_ich8_info = {
3498         .mac                    = e1000_ich8lan,
3499         .flags                  = FLAG_HAS_WOL
3500                                   | FLAG_IS_ICH
3501                                   | FLAG_RX_CSUM_ENABLED
3502                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3503                                   | FLAG_HAS_AMT
3504                                   | FLAG_HAS_FLASH
3505                                   | FLAG_APME_IN_WUC,
3506         .pba                    = 8,
3507         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3508         .get_variants           = e1000_get_variants_ich8lan,
3509         .mac_ops                = &ich8_mac_ops,
3510         .phy_ops                = &ich8_phy_ops,
3511         .nvm_ops                = &ich8_nvm_ops,
3512 };
3513
3514 struct e1000_info e1000_ich9_info = {
3515         .mac                    = e1000_ich9lan,
3516         .flags                  = FLAG_HAS_JUMBO_FRAMES
3517                                   | FLAG_IS_ICH
3518                                   | FLAG_HAS_WOL
3519                                   | FLAG_RX_CSUM_ENABLED
3520                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3521                                   | FLAG_HAS_AMT
3522                                   | FLAG_HAS_ERT
3523                                   | FLAG_HAS_FLASH
3524                                   | FLAG_APME_IN_WUC,
3525         .pba                    = 10,
3526         .max_hw_frame_size      = DEFAULT_JUMBO,
3527         .get_variants           = e1000_get_variants_ich8lan,
3528         .mac_ops                = &ich8_mac_ops,
3529         .phy_ops                = &ich8_phy_ops,
3530         .nvm_ops                = &ich8_nvm_ops,
3531 };
3532
3533 struct e1000_info e1000_ich10_info = {
3534         .mac                    = e1000_ich10lan,
3535         .flags                  = FLAG_HAS_JUMBO_FRAMES
3536                                   | FLAG_IS_ICH
3537                                   | FLAG_HAS_WOL
3538                                   | FLAG_RX_CSUM_ENABLED
3539                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3540                                   | FLAG_HAS_AMT
3541                                   | FLAG_HAS_ERT
3542                                   | FLAG_HAS_FLASH
3543                                   | FLAG_APME_IN_WUC,
3544         .pba                    = 10,
3545         .max_hw_frame_size      = DEFAULT_JUMBO,
3546         .get_variants           = e1000_get_variants_ich8lan,
3547         .mac_ops                = &ich8_mac_ops,
3548         .phy_ops                = &ich8_phy_ops,
3549         .nvm_ops                = &ich8_nvm_ops,
3550 };
3551
3552 struct e1000_info e1000_pch_info = {
3553         .mac                    = e1000_pchlan,
3554         .flags                  = FLAG_IS_ICH
3555                                   | FLAG_HAS_WOL
3556                                   | FLAG_RX_CSUM_ENABLED
3557                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3558                                   | FLAG_HAS_AMT
3559                                   | FLAG_HAS_FLASH
3560                                   | FLAG_HAS_JUMBO_FRAMES
3561                                   | FLAG_APME_IN_WUC,
3562         .pba                    = 26,
3563         .max_hw_frame_size      = 4096,
3564         .get_variants           = e1000_get_variants_ich8lan,
3565         .mac_ops                = &ich8_mac_ops,
3566         .phy_ops                = &ich8_phy_ops,
3567         .nvm_ops                = &ich8_nvm_ops,
3568 };