drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include <linux/netdevice.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/delay.h>
  60 #include <linux/pci.h>
  61
  62 #include "e1000.h"
  63
  64 #define ICH_FLASH_GFPREG                0x0000
  65 #define ICH_FLASH_HSFSTS                0x0004
  66 #define ICH_FLASH_HSFCTL                0x0006
  67 #define ICH_FLASH_FADDR                 0x0008
  68 #define ICH_FLASH_FDATA0                0x0010
  69 #define ICH_FLASH_PR0                   0x0074
  70
  71 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  74 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  75 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  76
  77 #define ICH_CYCLE_READ                  0
  78 #define ICH_CYCLE_WRITE                 2
  79 #define ICH_CYCLE_ERASE                 3
  80
  81 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  82 #define FLASH_SECTOR_ADDR_SHIFT         12
  83
  84 #define ICH_FLASH_SEG_SIZE_256          256
  85 #define ICH_FLASH_SEG_SIZE_4K           4096
  86 #define ICH_FLASH_SEG_SIZE_8K           8192
  87 #define ICH_FLASH_SEG_SIZE_64K          65536
  88
  89
  90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  91
  92 #define E1000_ICH_MNG_IAMT_MODE         0x2
  93
  94 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  95                                  (ID_LED_DEF1_OFF2 <<  8) | \
  96                                  (ID_LED_DEF1_ON2  <<  4) | \
  97                                  (ID_LED_DEF1_DEF2))
  98
  99 #define E1000_ICH_NVM_SIG_WORD          0x13
 100 #define E1000_ICH_NVM_SIG_MASK          0xC000
 101 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 102 #define E1000_ICH_NVM_SIG_VALUE         0x80
 103
 104 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 105
 106 #define E1000_FEXTNVM_SW_CONFIG         1
 107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 108
 109 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 110
 111 #define E1000_ICH_RAR_ENTRIES           7
 112
 113 #define PHY_PAGE_SHIFT 5
 114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 115                            ((reg) & MAX_PHY_REG_ADDRESS))
 116 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 117 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 118
 119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 121 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 122
 123 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 124
 125 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 126
 127 /* OEM Bits Phy Register */
 128 #define HV_OEM_BITS            PHY_REG(768, 25)
 129 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 130 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 131
 132 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 133 /* Offset 04h HSFSTS */
 134 union ich8_hws_flash_status {
 135         struct ich8_hsfsts {
 136                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 137                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 138                 u16 dael       :1; /* bit 2 Direct Access error Log */
 139                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 140                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 141                 u16 reserved1  :2; /* bit 13:6 Reserved */
 142                 u16 reserved2  :6; /* bit 13:6 Reserved */
 143                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 144                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 145         } hsf_status;
 146         u16 regval;
 147 };
 148
 149 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 150 /* Offset 06h FLCTL */
 151 union ich8_hws_flash_ctrl {
 152         struct ich8_hsflctl {
 153                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 154                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 155                 u16 reserved   :5;   /* 7:3 Reserved  */
 156                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 157                 u16 flockdn    :6;   /* 15:10 Reserved */
 158         } hsf_ctrl;
 159         u16 regval;
 160 };
 161
 162 /* ICH Flash Region Access Permissions */
 163 union ich8_hws_flash_regacc {
 164         struct ich8_flracc {
 165                 u32 grra      :8; /* 0:7 GbE region Read Access */
 166                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 167                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 168                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 169         } hsf_flregacc;
 170         u16 regval;
 171 };
 172
 173 /* ICH Flash Protected Region */
 174 union ich8_flash_protected_range {
 175         struct ich8_pr {
 176                 u32 base:13;     /* 0:12 Protected Range Base */
 177                 u32 reserved1:2; /* 13:14 Reserved */
 178                 u32 rpe:1;       /* 15 Read Protection Enable */
 179                 u32 limit:13;    /* 16:28 Protected Range Limit */
 180                 u32 reserved2:2; /* 29:30 Reserved */
 181                 u32 wpe:1;       /* 31 Write Protection Enable */
 182         } range;
 183         u32 regval;
 184 };
 185
 186 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 187 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 188 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 189 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 190 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 191 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 192                                                 u32 offset, u8 byte);
 193 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 194                                          u8 *data);
 195 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 196                                          u16 *data);
 197 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 198                                          u8 size, u16 *data);
 199 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 200 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 201 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 202 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 203 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 204 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 205 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 206 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 207 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 208 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 209 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 210 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 211
 212 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 213 {
 214         return readw(hw->flash_address + reg);
 215 }
 216
 217 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 218 {
 219         return readl(hw->flash_address + reg);
 220 }
 221
 222 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 223 {
 224         writew(val, hw->flash_address + reg);
 225 }
 226
 227 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 228 {
 229         writel(val, hw->flash_address + reg);
 230 }
 231
 232 #define er16flash(reg)          __er16flash(hw, (reg))
 233 #define er32flash(reg)          __er32flash(hw, (reg))
 234 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 235 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 236
 237 /**
 238  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 239  *  @hw: pointer to the HW structure
 240  *
 241  *  Initialize family-specific PHY parameters and function pointers.
 242  **/
 243 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 244 {
 245         struct e1000_phy_info *phy = &hw->phy;
 246         s32 ret_val = 0;
 247
 248         phy->addr                     = 1;
 249         phy->reset_delay_us           = 100;
 250
 251         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 252         phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;
 253         phy->ops.read_phy_reg_locked  = e1000_read_phy_reg_hv_locked;
 254         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 255         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 256         phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;
 257         phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
 258         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 259
 260         phy->id = e1000_phy_unknown;
 261         e1000e_get_phy_id(hw);
 262         phy->type = e1000e_get_phy_type_from_id(phy->id);
 263
 264         if (phy->type == e1000_phy_82577) {
 265                 phy->ops.check_polarity = e1000_check_polarity_82577;
 266                 phy->ops.force_speed_duplex =
 267                         e1000_phy_force_speed_duplex_82577;
 268                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 269                 phy->ops.get_phy_info = e1000_get_phy_info_82577;
 270                 phy->ops.commit_phy = e1000e_phy_sw_reset;
 271         }
 272
 273         return ret_val;
 274 }
 275
 276 /**
 277  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 278  *  @hw: pointer to the HW structure
 279  *
 280  *  Initialize family-specific PHY parameters and function pointers.
 281  **/
 282 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 283 {
 284         struct e1000_phy_info *phy = &hw->phy;
 285         s32 ret_val;
 286         u16 i = 0;
 287
 288         phy->addr                       = 1;
 289         phy->reset_delay_us             = 100;
 290
 291         /*
 292          * We may need to do this twice - once for IGP and if that fails,
 293          * we'll set BM func pointers and try again
 294          */
 295         ret_val = e1000e_determine_phy_address(hw);
 296         if (ret_val) {
 297                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 298                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 299                 ret_val = e1000e_determine_phy_address(hw);
 300                 if (ret_val)
 301                         return ret_val;
 302         }
 303
 304         phy->id = 0;
 305         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 306                (i++ < 100)) {
 307                 msleep(1);
 308                 ret_val = e1000e_get_phy_id(hw);
 309                 if (ret_val)
 310                         return ret_val;
 311         }
 312
 313         /* Verify phy id */
 314         switch (phy->id) {
 315         case IGP03E1000_E_PHY_ID:
 316                 phy->type = e1000_phy_igp_3;
 317                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 318                 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
 319                 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
 320                 break;
 321         case IFE_E_PHY_ID:
 322         case IFE_PLUS_E_PHY_ID:
 323         case IFE_C_E_PHY_ID:
 324                 phy->type = e1000_phy_ife;
 325                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 326                 break;
 327         case BME1000_E_PHY_ID:
 328                 phy->type = e1000_phy_bm;
 329                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 330                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 331                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 332                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 333                 break;
 334         default:
 335                 return -E1000_ERR_PHY;
 336                 break;
 337         }
 338
 339         phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
 340
 341         return 0;
 342 }
 343
 344 /**
 345  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 346  *  @hw: pointer to the HW structure
 347  *
 348  *  Initialize family-specific NVM parameters and function
 349  *  pointers.
 350  **/
 351 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 352 {
 353         struct e1000_nvm_info *nvm = &hw->nvm;
 354         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 355         u32 gfpreg, sector_base_addr, sector_end_addr;
 356         u16 i;
 357
 358         /* Can't read flash registers if the register set isn't mapped. */
 359         if (!hw->flash_address) {
 360                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 361                 return -E1000_ERR_CONFIG;
 362         }
 363
 364         nvm->type = e1000_nvm_flash_sw;
 365
 366         gfpreg = er32flash(ICH_FLASH_GFPREG);
 367
 368         /*
 369          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 370          * Add 1 to sector_end_addr since this sector is included in
 371          * the overall size.
 372          */
 373         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 374         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 375
 376         /* flash_base_addr is byte-aligned */
 377         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 378
 379         /*
 380          * find total size of the NVM, then cut in half since the total
 381          * size represents two separate NVM banks.
 382          */
 383         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 384                                 << FLASH_SECTOR_ADDR_SHIFT;
 385         nvm->flash_bank_size /= 2;
 386         /* Adjust to word count */
 387         nvm->flash_bank_size /= sizeof(u16);
 388
 389         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 390
 391         /* Clear shadow ram */
 392         for (i = 0; i < nvm->word_size; i++) {
 393                 dev_spec->shadow_ram[i].modified = 0;
 394                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 395         }
 396
 397         return 0;
 398 }
 399
 400 /**
 401  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 402  *  @hw: pointer to the HW structure
 403  *
 404  *  Initialize family-specific MAC parameters and function
 405  *  pointers.
 406  **/
 407 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 408 {
 409         struct e1000_hw *hw = &adapter->hw;
 410         struct e1000_mac_info *mac = &hw->mac;
 411
 412         /* Set media type function pointer */
 413         hw->phy.media_type = e1000_media_type_copper;
 414
 415         /* Set mta register count */
 416         mac->mta_reg_count = 32;
 417         /* Set rar entry count */
 418         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 419         if (mac->type == e1000_ich8lan)
 420                 mac->rar_entry_count--;
 421         /* Set if manageability features are enabled. */
 422         mac->arc_subsystem_valid = 1;
 423
 424         /* LED operations */
 425         switch (mac->type) {
 426         case e1000_ich8lan:
 427         case e1000_ich9lan:
 428         case e1000_ich10lan:
 429                 /* ID LED init */
 430                 mac->ops.id_led_init = e1000e_id_led_init;
 431                 /* setup LED */
 432                 mac->ops.setup_led = e1000e_setup_led_generic;
 433                 /* cleanup LED */
 434                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 435                 /* turn on/off LED */
 436                 mac->ops.led_on = e1000_led_on_ich8lan;
 437                 mac->ops.led_off = e1000_led_off_ich8lan;
 438                 break;
 439         case e1000_pchlan:
 440                 /* ID LED init */
 441                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 442                 /* setup LED */
 443                 mac->ops.setup_led = e1000_setup_led_pchlan;
 444                 /* cleanup LED */
 445                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 446                 /* turn on/off LED */
 447                 mac->ops.led_on = e1000_led_on_pchlan;
 448                 mac->ops.led_off = e1000_led_off_pchlan;
 449                 break;
 450         default:
 451                 break;
 452         }
 453
 454         /* Enable PCS Lock-loss workaround for ICH8 */
 455         if (mac->type == e1000_ich8lan)
 456                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 457
 458         return 0;
 459 }
 460
 461 /**
 462  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 463  *  @hw: pointer to the HW structure
 464  *
 465  *  Checks to see of the link status of the hardware has changed.  If a
 466  *  change in link status has been detected, then we read the PHY registers
 467  *  to get the current speed/duplex if link exists.
 468  **/
 469 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 470 {
 471         struct e1000_mac_info *mac = &hw->mac;
 472         s32 ret_val;
 473         bool link;
 474
 475         /*
 476          * We only want to go out to the PHY registers to see if Auto-Neg
 477          * has completed and/or if our link status has changed.  The
 478          * get_link_status flag is set upon receiving a Link Status
 479          * Change or Rx Sequence Error interrupt.
 480          */
 481         if (!mac->get_link_status) {
 482                 ret_val = 0;
 483                 goto out;
 484         }
 485
 486         if (hw->mac.type == e1000_pchlan) {
 487                 ret_val = e1000e_write_kmrn_reg(hw,
 488                                                    E1000_KMRNCTRLSTA_K1_CONFIG,
 489                                                    E1000_KMRNCTRLSTA_K1_ENABLE);
 490                 if (ret_val)
 491                         goto out;
 492         }
 493
 494         /*
 495          * First we want to see if the MII Status Register reports
 496          * link.  If so, then we want to get the current speed/duplex
 497          * of the PHY.
 498          */
 499         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 500         if (ret_val)
 501                 goto out;
 502
 503         if (!link)
 504                 goto out; /* No link detected */
 505
 506         mac->get_link_status = false;
 507
 508         if (hw->phy.type == e1000_phy_82578) {
 509                 ret_val = e1000_link_stall_workaround_hv(hw);
 510                 if (ret_val)
 511                         goto out;
 512         }
 513
 514         /*
 515          * Check if there was DownShift, must be checked
 516          * immediately after link-up
 517          */
 518         e1000e_check_downshift(hw);
 519
 520         /*
 521          * If we are forcing speed/duplex, then we simply return since
 522          * we have already determined whether we have link or not.
 523          */
 524         if (!mac->autoneg) {
 525                 ret_val = -E1000_ERR_CONFIG;
 526                 goto out;
 527         }
 528
 529         /*
 530          * Auto-Neg is enabled.  Auto Speed Detection takes care
 531          * of MAC speed/duplex configuration.  So we only need to
 532          * configure Collision Distance in the MAC.
 533          */
 534         e1000e_config_collision_dist(hw);
 535
 536         /*
 537          * Configure Flow Control now that Auto-Neg has completed.
 538          * First, we need to restore the desired flow control
 539          * settings because we may have had to re-autoneg with a
 540          * different link partner.
 541          */
 542         ret_val = e1000e_config_fc_after_link_up(hw);
 543         if (ret_val)
 544                 hw_dbg(hw, "Error configuring flow control\n");
 545
 546 out:
 547         return ret_val;
 548 }
 549
 550 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 551 {
 552         struct e1000_hw *hw = &adapter->hw;
 553         s32 rc;
 554
 555         rc = e1000_init_mac_params_ich8lan(adapter);
 556         if (rc)
 557                 return rc;
 558
 559         rc = e1000_init_nvm_params_ich8lan(hw);
 560         if (rc)
 561                 return rc;
 562
 563         if (hw->mac.type == e1000_pchlan)
 564                 rc = e1000_init_phy_params_pchlan(hw);
 565         else
 566                 rc = e1000_init_phy_params_ich8lan(hw);
 567         if (rc)
 568                 return rc;
 569
 570         if (adapter->hw.phy.type == e1000_phy_ife) {
 571                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 572                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 573         }
 574
 575         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 576             (adapter->hw.phy.type == e1000_phy_igp_3))
 577                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 578
 579         return 0;
 580 }
 581
 582 static DEFINE_MUTEX(nvm_mutex);
 583
 584 /**
 585  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 586  *  @hw: pointer to the HW structure
 587  *
 588  *  Acquires the mutex for performing NVM operations.
 589  **/
 590 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 591 {
 592         mutex_lock(&nvm_mutex);
 593
 594         return 0;
 595 }
 596
 597 /**
 598  *  e1000_release_nvm_ich8lan - Release NVM mutex
 599  *  @hw: pointer to the HW structure
 600  *
 601  *  Releases the mutex used while performing NVM operations.
 602  **/
 603 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 604 {
 605         mutex_unlock(&nvm_mutex);
 606
 607         return;
 608 }
 609
 610 static DEFINE_MUTEX(swflag_mutex);
 611
 612 /**
 613  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 614  *  @hw: pointer to the HW structure
 615  *
 616  *  Acquires the software control flag for performing PHY and select
 617  *  MAC CSR accesses.
 618  **/
 619 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 620 {
 621         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 622         s32 ret_val = 0;
 623
 624         might_sleep();
 625
 626         mutex_lock(&swflag_mutex);
 627
 628         while (timeout) {
 629                 extcnf_ctrl = er32(EXTCNF_CTRL);
 630                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 631                         break;
 632
 633                 mdelay(1);
 634                 timeout--;
 635         }
 636
 637         if (!timeout) {
 638                 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
 639                 ret_val = -E1000_ERR_CONFIG;
 640                 goto out;
 641         }
 642
 643         timeout = SW_FLAG_TIMEOUT;
 644
 645         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 646         ew32(EXTCNF_CTRL, extcnf_ctrl);
 647
 648         while (timeout) {
 649                 extcnf_ctrl = er32(EXTCNF_CTRL);
 650                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 651                         break;
 652
 653                 mdelay(1);
 654                 timeout--;
 655         }
 656
 657         if (!timeout) {
 658                 hw_dbg(hw, "Failed to acquire the semaphore.\n");
 659                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 660                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 661                 ret_val = -E1000_ERR_CONFIG;
 662                 goto out;
 663         }
 664
 665 out:
 666         if (ret_val)
 667                 mutex_unlock(&swflag_mutex);
 668
 669         return ret_val;
 670 }
 671
 672 /**
 673  *  e1000_release_swflag_ich8lan - Release software control flag
 674  *  @hw: pointer to the HW structure
 675  *
 676  *  Releases the software control flag for performing PHY and select
 677  *  MAC CSR accesses.
 678  **/
 679 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 680 {
 681         u32 extcnf_ctrl;
 682
 683         extcnf_ctrl = er32(EXTCNF_CTRL);
 684         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 685         ew32(EXTCNF_CTRL, extcnf_ctrl);
 686
 687         mutex_unlock(&swflag_mutex);
 688
 689         return;
 690 }
 691
 692 /**
 693  *  e1000_check_mng_mode_ich8lan - Checks management mode
 694  *  @hw: pointer to the HW structure
 695  *
 696  *  This checks if the adapter has manageability enabled.
 697  *  This is a function pointer entry point only called by read/write
 698  *  routines for the PHY and NVM parts.
 699  **/
 700 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 701 {
 702         u32 fwsm = er32(FWSM);
 703
 704         return (fwsm & E1000_FWSM_MODE_MASK) ==
 705                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 706 }
 707
 708 /**
 709  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 710  *  @hw: pointer to the HW structure
 711  *
 712  *  Checks if firmware is blocking the reset of the PHY.
 713  *  This is a function pointer entry point only called by
 714  *  reset routines.
 715  **/
 716 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 717 {
 718         u32 fwsm;
 719
 720         fwsm = er32(FWSM);
 721
 722         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 723 }
 724
 725 /**
 726  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 727  *  @hw: pointer to the HW structure
 728  *
 729  *  Forces the speed and duplex settings of the PHY.
 730  *  This is a function pointer entry point only called by
 731  *  PHY setup routines.
 732  **/
 733 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 734 {
 735         struct e1000_phy_info *phy = &hw->phy;
 736         s32 ret_val;
 737         u16 data;
 738         bool link;
 739
 740         if (phy->type != e1000_phy_ife) {
 741                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 742                 return ret_val;
 743         }
 744
 745         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 746         if (ret_val)
 747                 return ret_val;
 748
 749         e1000e_phy_force_speed_duplex_setup(hw, &data);
 750
 751         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 752         if (ret_val)
 753                 return ret_val;
 754
 755         /* Disable MDI-X support for 10/100 */
 756         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 757         if (ret_val)
 758                 return ret_val;
 759
 760         data &= ~IFE_PMC_AUTO_MDIX;
 761         data &= ~IFE_PMC_FORCE_MDIX;
 762
 763         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 764         if (ret_val)
 765                 return ret_val;
 766
 767         hw_dbg(hw, "IFE PMC: %X\n", data);
 768
 769         udelay(1);
 770
 771         if (phy->autoneg_wait_to_complete) {
 772                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 773
 774                 ret_val = e1000e_phy_has_link_generic(hw,
 775                                                      PHY_FORCE_LIMIT,
 776                                                      100000,
 777                                                      &link);
 778                 if (ret_val)
 779                         return ret_val;
 780
 781                 if (!link)
 782                         hw_dbg(hw, "Link taking longer than expected.\n");
 783
 784                 /* Try once more */
 785                 ret_val = e1000e_phy_has_link_generic(hw,
 786                                                      PHY_FORCE_LIMIT,
 787                                                      100000,
 788                                                      &link);
 789                 if (ret_val)
 790                         return ret_val;
 791         }
 792
 793         return 0;
 794 }
 795
 796 /**
 797  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
 798  *  done after every PHY reset.
 799  **/
 800 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 801 {
 802         s32 ret_val = 0;
 803
 804         if (hw->mac.type != e1000_pchlan)
 805                 return ret_val;
 806
 807         if (((hw->phy.type == e1000_phy_82577) &&
 808              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
 809             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
 810                 /* Disable generation of early preamble */
 811                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
 812                 if (ret_val)
 813                         return ret_val;
 814
 815                 /* Preamble tuning for SSC */
 816                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
 817                 if (ret_val)
 818                         return ret_val;
 819         }
 820
 821         if (hw->phy.type == e1000_phy_82578) {
 822                 /*
 823                  * Return registers to default by doing a soft reset then
 824                  * writing 0x3140 to the control register.
 825                  */
 826                 if (hw->phy.revision < 2) {
 827                         e1000e_phy_sw_reset(hw);
 828                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
 829                 }
 830         }
 831
 832         /* Select page 0 */
 833         ret_val = hw->phy.ops.acquire_phy(hw);
 834         if (ret_val)
 835                 return ret_val;
 836         hw->phy.addr = 1;
 837         e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
 838         hw->phy.ops.release_phy(hw);
 839
 840         return ret_val;
 841 }
 842
 843 /**
 844  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
 845  *  @hw: pointer to the HW structure
 846  *
 847  *  Check the appropriate indication the MAC has finished configuring the
 848  *  PHY after a software reset.
 849  **/
 850 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
 851 {
 852         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 853
 854         /* Wait for basic configuration completes before proceeding */
 855         do {
 856                 data = er32(STATUS);
 857                 data &= E1000_STATUS_LAN_INIT_DONE;
 858                 udelay(100);
 859         } while ((!data) && --loop);
 860
 861         /*
 862          * If basic configuration is incomplete before the above loop
 863          * count reaches 0, loading the configuration from NVM will
 864          * leave the PHY in a bad state possibly resulting in no link.
 865          */
 866         if (loop == 0)
 867                 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 868
 869         /* Clear the Init Done bit for the next init event */
 870         data = er32(STATUS);
 871         data &= ~E1000_STATUS_LAN_INIT_DONE;
 872         ew32(STATUS, data);
 873 }
 874
 875 /**
 876  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 877  *  @hw: pointer to the HW structure
 878  *
 879  *  Resets the PHY
 880  *  This is a function pointer entry point called by drivers
 881  *  or other shared routines.
 882  **/
 883 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 884 {
 885         struct e1000_phy_info *phy = &hw->phy;
 886         u32 i;
 887         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 888         s32 ret_val;
 889         u16 reg, word_addr, reg_data, reg_addr, phy_page = 0;
 890
 891         ret_val = e1000e_phy_hw_reset_generic(hw);
 892         if (ret_val)
 893                 return ret_val;
 894
 895         /* Allow time for h/w to get to a quiescent state after reset */
 896         mdelay(10);
 897
 898         if (hw->mac.type == e1000_pchlan) {
 899                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
 900                 if (ret_val)
 901                         return ret_val;
 902         }
 903
 904         /* Dummy read to clear the phy wakeup bit after lcd reset */
 905         if (hw->mac.type == e1000_pchlan)
 906                 e1e_rphy(hw, BM_WUC, &reg);
 907
 908         /*
 909          * Initialize the PHY from the NVM on ICH platforms.  This
 910          * is needed due to an issue where the NVM configuration is
 911          * not properly autoloaded after power transitions.
 912          * Therefore, after each PHY reset, we will load the
 913          * configuration data out of the NVM manually.
 914          */
 915         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 916                 struct e1000_adapter *adapter = hw->adapter;
 917
 918                 /* Check if SW needs configure the PHY */
 919                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 920                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 921                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 922                 else
 923                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 924
 925                 data = er32(FEXTNVM);
 926                 if (!(data & sw_cfg_mask))
 927                         return 0;
 928
 929                 /* Wait for basic configuration completes before proceeding */
 930                 e1000_lan_init_done_ich8lan(hw);
 931
 932                 /*
 933                  * Make sure HW does not configure LCD from PHY
 934                  * extended configuration before SW configuration
 935                  */
 936                 data = er32(EXTCNF_CTRL);
 937                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 938                         return 0;
 939
 940                 cnf_size = er32(EXTCNF_SIZE);
 941                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 942                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 943                 if (!cnf_size)
 944                         return 0;
 945
 946                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 947                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 948
 949                 /* Configure LCD from extended configuration region. */
 950
 951                 /* cnf_base_addr is in DWORD */
 952                 word_addr = (u16)(cnf_base_addr << 1);
 953
 954                 for (i = 0; i < cnf_size; i++) {
 955                         ret_val = e1000_read_nvm(hw,
 956                                                 (word_addr + i * 2),
 957                                                 1,
 958                                                 &reg_data);
 959                         if (ret_val)
 960                                 return ret_val;
 961
 962                         ret_val = e1000_read_nvm(hw,
 963                                                 (word_addr + i * 2 + 1),
 964                                                 1,
 965                                                 &reg_addr);
 966                         if (ret_val)
 967                                 return ret_val;
 968
 969                         /* Save off the PHY page for future writes. */
 970                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 971                                 phy_page = reg_data;
 972                                 continue;
 973                         }
 974
 975                         reg_addr |= phy_page;
 976
 977                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 978                         if (ret_val)
 979                                 return ret_val;
 980                 }
 981         }
 982
 983         return 0;
 984 }
 985
 986 /**
 987  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 988  *  @hw: pointer to the HW structure
 989  *
 990  *  Populates "phy" structure with various feature states.
 991  *  This function is only called by other family-specific
 992  *  routines.
 993  **/
 994 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 995 {
 996         struct e1000_phy_info *phy = &hw->phy;
 997         s32 ret_val;
 998         u16 data;
 999         bool link;
1000
1001         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1002         if (ret_val)
1003                 return ret_val;
1004
1005         if (!link) {
1006                 hw_dbg(hw, "Phy info is only valid if link is up\n");
1007                 return -E1000_ERR_CONFIG;
1008         }
1009
1010         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1011         if (ret_val)
1012                 return ret_val;
1013         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1014
1015         if (phy->polarity_correction) {
1016                 ret_val = phy->ops.check_polarity(hw);
1017                 if (ret_val)
1018                         return ret_val;
1019         } else {
1020                 /* Polarity is forced */
1021                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1022                                       ? e1000_rev_polarity_reversed
1023                                       : e1000_rev_polarity_normal;
1024         }
1025
1026         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1027         if (ret_val)
1028                 return ret_val;
1029
1030         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1031
1032         /* The following parameters are undefined for 10/100 operation. */
1033         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1034         phy->local_rx = e1000_1000t_rx_status_undefined;
1035         phy->remote_rx = e1000_1000t_rx_status_undefined;
1036
1037         return 0;
1038 }
1039
1040 /**
1041  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1042  *  @hw: pointer to the HW structure
1043  *
1044  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
1045  *  This is a function pointer entry point called by drivers
1046  *  or other shared routines.
1047  **/
1048 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1049 {
1050         switch (hw->phy.type) {
1051         case e1000_phy_ife:
1052                 return e1000_get_phy_info_ife_ich8lan(hw);
1053                 break;
1054         case e1000_phy_igp_3:
1055         case e1000_phy_bm:
1056         case e1000_phy_82578:
1057         case e1000_phy_82577:
1058                 return e1000e_get_phy_info_igp(hw);
1059                 break;
1060         default:
1061                 break;
1062         }
1063
1064         return -E1000_ERR_PHY_TYPE;
1065 }
1066
1067 /**
1068  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1069  *  @hw: pointer to the HW structure
1070  *
1071  *  Polarity is determined on the polarity reversal feature being enabled.
1072  *  This function is only called by other family-specific
1073  *  routines.
1074  **/
1075 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1076 {
1077         struct e1000_phy_info *phy = &hw->phy;
1078         s32 ret_val;
1079         u16 phy_data, offset, mask;
1080
1081         /*
1082          * Polarity is determined based on the reversal feature being enabled.
1083          */
1084         if (phy->polarity_correction) {
1085                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
1086                 mask    = IFE_PESC_POLARITY_REVERSED;
1087         } else {
1088                 offset  = IFE_PHY_SPECIAL_CONTROL;
1089                 mask    = IFE_PSC_FORCE_POLARITY;
1090         }
1091
1092         ret_val = e1e_rphy(hw, offset, &phy_data);
1093
1094         if (!ret_val)
1095                 phy->cable_polarity = (phy_data & mask)
1096                                       ? e1000_rev_polarity_reversed
1097                                       : e1000_rev_polarity_normal;
1098
1099         return ret_val;
1100 }
1101
1102 /**
1103  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1104  *  @hw: pointer to the HW structure
1105  *  @active: true to enable LPLU, false to disable
1106  *
1107  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1108  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1109  *  the phy speed. This function will manually set the LPLU bit and restart
1110  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1111  *  since it configures the same bit.
1112  **/
1113 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1114 {
1115         s32 ret_val = 0;
1116         u16 oem_reg;
1117
1118         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1119         if (ret_val)
1120                 goto out;
1121
1122         if (active)
1123                 oem_reg |= HV_OEM_BITS_LPLU;
1124         else
1125                 oem_reg &= ~HV_OEM_BITS_LPLU;
1126
1127         oem_reg |= HV_OEM_BITS_RESTART_AN;
1128         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1129
1130 out:
1131         return ret_val;
1132 }
1133
1134 /**
1135  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1136  *  @hw: pointer to the HW structure
1137  *  @active: TRUE to enable LPLU, FALSE to disable
1138  *
1139  *  Sets the LPLU D0 state according to the active flag.  When
1140  *  activating LPLU this function also disables smart speed
1141  *  and vice versa.  LPLU will not be activated unless the
1142  *  device autonegotiation advertisement meets standards of
1143  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1144  *  This is a function pointer entry point only called by
1145  *  PHY setup routines.
1146  **/
1147 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1148 {
1149         struct e1000_phy_info *phy = &hw->phy;
1150         u32 phy_ctrl;
1151         s32 ret_val = 0;
1152         u16 data;
1153
1154         if (phy->type == e1000_phy_ife)
1155                 return ret_val;
1156
1157         phy_ctrl = er32(PHY_CTRL);
1158
1159         if (active) {
1160                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1161                 ew32(PHY_CTRL, phy_ctrl);
1162
1163                 if (phy->type != e1000_phy_igp_3)
1164                         return 0;
1165
1166                 /*
1167                  * Call gig speed drop workaround on LPLU before accessing
1168                  * any PHY registers
1169                  */
1170                 if (hw->mac.type == e1000_ich8lan)
1171                         e1000e_gig_downshift_workaround_ich8lan(hw);
1172
1173                 /* When LPLU is enabled, we should disable SmartSpeed */
1174                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1175                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1176                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1177                 if (ret_val)
1178                         return ret_val;
1179         } else {
1180                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1181                 ew32(PHY_CTRL, phy_ctrl);
1182
1183                 if (phy->type != e1000_phy_igp_3)
1184                         return 0;
1185
1186                 /*
1187                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1188                  * during Dx states where the power conservation is most
1189                  * important.  During driver activity we should enable
1190                  * SmartSpeed, so performance is maintained.
1191                  */
1192                 if (phy->smart_speed == e1000_smart_speed_on) {
1193                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1194                                            &data);
1195                         if (ret_val)
1196                                 return ret_val;
1197
1198                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1199                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1200                                            data);
1201                         if (ret_val)
1202                                 return ret_val;
1203                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1204                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1205                                            &data);
1206                         if (ret_val)
1207                                 return ret_val;
1208
1209                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1210                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1211                                            data);
1212                         if (ret_val)
1213                                 return ret_val;
1214                 }
1215         }
1216
1217         return 0;
1218 }
1219
1220 /**
1221  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1222  *  @hw: pointer to the HW structure
1223  *  @active: TRUE to enable LPLU, FALSE to disable
1224  *
1225  *  Sets the LPLU D3 state according to the active flag.  When
1226  *  activating LPLU this function also disables smart speed
1227  *  and vice versa.  LPLU will not be activated unless the
1228  *  device autonegotiation advertisement meets standards of
1229  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1230  *  This is a function pointer entry point only called by
1231  *  PHY setup routines.
1232  **/
1233 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1234 {
1235         struct e1000_phy_info *phy = &hw->phy;
1236         u32 phy_ctrl;
1237         s32 ret_val;
1238         u16 data;
1239
1240         phy_ctrl = er32(PHY_CTRL);
1241
1242         if (!active) {
1243                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1244                 ew32(PHY_CTRL, phy_ctrl);
1245
1246                 if (phy->type != e1000_phy_igp_3)
1247                         return 0;
1248
1249                 /*
1250                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1251                  * during Dx states where the power conservation is most
1252                  * important.  During driver activity we should enable
1253                  * SmartSpeed, so performance is maintained.
1254                  */
1255                 if (phy->smart_speed == e1000_smart_speed_on) {
1256                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1257                                            &data);
1258                         if (ret_val)
1259                                 return ret_val;
1260
1261                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1262                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1263                                            data);
1264                         if (ret_val)
1265                                 return ret_val;
1266                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1267                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1268                                            &data);
1269                         if (ret_val)
1270                                 return ret_val;
1271
1272                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1273                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1274                                            data);
1275                         if (ret_val)
1276                                 return ret_val;
1277                 }
1278         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1279                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1280                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1281                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1282                 ew32(PHY_CTRL, phy_ctrl);
1283
1284                 if (phy->type != e1000_phy_igp_3)
1285                         return 0;
1286
1287                 /*
1288                  * Call gig speed drop workaround on LPLU before accessing
1289                  * any PHY registers
1290                  */
1291                 if (hw->mac.type == e1000_ich8lan)
1292                         e1000e_gig_downshift_workaround_ich8lan(hw);
1293
1294                 /* When LPLU is enabled, we should disable SmartSpeed */
1295                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1296                 if (ret_val)
1297                         return ret_val;
1298
1299                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1300                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1301         }
1302
1303         return 0;
1304 }
1305
1306 /**
1307  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1308  *  @hw: pointer to the HW structure
1309  *  @bank:  pointer to the variable that returns the active bank
1310  *
1311  *  Reads signature byte from the NVM using the flash access registers.
1312  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1313  **/
1314 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1315 {
1316         u32 eecd;
1317         struct e1000_nvm_info *nvm = &hw->nvm;
1318         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1319         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1320         u8 sig_byte = 0;
1321         s32 ret_val = 0;
1322
1323         switch (hw->mac.type) {
1324         case e1000_ich8lan:
1325         case e1000_ich9lan:
1326                 eecd = er32(EECD);
1327                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1328                     E1000_EECD_SEC1VAL_VALID_MASK) {
1329                         if (eecd & E1000_EECD_SEC1VAL)
1330                                 *bank = 1;
1331                         else
1332                                 *bank = 0;
1333
1334                         return 0;
1335                 }
1336                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1337                        "reading flash signature\n");
1338                 /* fall-thru */
1339         default:
1340                 /* set bank to 0 in case flash read fails */
1341                 *bank = 0;
1342
1343                 /* Check bank 0 */
1344                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1345                                                         &sig_byte);
1346                 if (ret_val)
1347                         return ret_val;
1348                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1349                     E1000_ICH_NVM_SIG_VALUE) {
1350                         *bank = 0;
1351                         return 0;
1352                 }
1353
1354                 /* Check bank 1 */
1355                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1356                                                         bank1_offset,
1357                                                         &sig_byte);
1358                 if (ret_val)
1359                         return ret_val;
1360                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1361                     E1000_ICH_NVM_SIG_VALUE) {
1362                         *bank = 1;
1363                         return 0;
1364                 }
1365
1366                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1367                 return -E1000_ERR_NVM;
1368         }
1369
1370         return 0;
1371 }
1372
1373 /**
1374  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1375  *  @hw: pointer to the HW structure
1376  *  @offset: The offset (in bytes) of the word(s) to read.
1377  *  @words: Size of data to read in words
1378  *  @data: Pointer to the word(s) to read at offset.
1379  *
1380  *  Reads a word(s) from the NVM using the flash access registers.
1381  **/
1382 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1383                                   u16 *data)
1384 {
1385         struct e1000_nvm_info *nvm = &hw->nvm;
1386         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1387         u32 act_offset;
1388         s32 ret_val = 0;
1389         u32 bank = 0;
1390         u16 i, word;
1391
1392         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1393             (words == 0)) {
1394                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1395                 ret_val = -E1000_ERR_NVM;
1396                 goto out;
1397         }
1398
1399         nvm->ops.acquire_nvm(hw);
1400
1401         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1402         if (ret_val) {
1403                 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1404                 bank = 0;
1405         }
1406
1407         act_offset = (bank) ? nvm->flash_bank_size : 0;
1408         act_offset += offset;
1409
1410         ret_val = 0;
1411         for (i = 0; i < words; i++) {
1412                 if ((dev_spec->shadow_ram) &&
1413                     (dev_spec->shadow_ram[offset+i].modified)) {
1414                         data[i] = dev_spec->shadow_ram[offset+i].value;
1415                 } else {
1416                         ret_val = e1000_read_flash_word_ich8lan(hw,
1417                                                                 act_offset + i,
1418                                                                 &word);
1419                         if (ret_val)
1420                                 break;
1421                         data[i] = word;
1422                 }
1423         }
1424
1425         nvm->ops.release_nvm(hw);
1426
1427 out:
1428         if (ret_val)
1429                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1430
1431         return ret_val;
1432 }
1433
1434 /**
1435  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1436  *  @hw: pointer to the HW structure
1437  *
1438  *  This function does initial flash setup so that a new read/write/erase cycle
1439  *  can be started.
1440  **/
1441 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1442 {
1443         union ich8_hws_flash_status hsfsts;
1444         s32 ret_val = -E1000_ERR_NVM;
1445         s32 i = 0;
1446
1447         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1448
1449         /* Check if the flash descriptor is valid */
1450         if (hsfsts.hsf_status.fldesvalid == 0) {
1451                 hw_dbg(hw, "Flash descriptor invalid.  "
1452                          "SW Sequencing must be used.");
1453                 return -E1000_ERR_NVM;
1454         }
1455
1456         /* Clear FCERR and DAEL in hw status by writing 1 */
1457         hsfsts.hsf_status.flcerr = 1;
1458         hsfsts.hsf_status.dael = 1;
1459
1460         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1461
1462         /*
1463          * Either we should have a hardware SPI cycle in progress
1464          * bit to check against, in order to start a new cycle or
1465          * FDONE bit should be changed in the hardware so that it
1466          * is 1 after hardware reset, which can then be used as an
1467          * indication whether a cycle is in progress or has been
1468          * completed.
1469          */
1470
1471         if (hsfsts.hsf_status.flcinprog == 0) {
1472                 /*
1473                  * There is no cycle running at present,
1474                  * so we can start a cycle
1475                  * Begin by setting Flash Cycle Done.
1476                  */
1477                 hsfsts.hsf_status.flcdone = 1;
1478                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1479                 ret_val = 0;
1480         } else {
1481                 /*
1482                  * otherwise poll for sometime so the current
1483                  * cycle has a chance to end before giving up.
1484                  */
1485                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1486                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1487                         if (hsfsts.hsf_status.flcinprog == 0) {
1488                                 ret_val = 0;
1489                                 break;
1490                         }
1491                         udelay(1);
1492                 }
1493                 if (ret_val == 0) {
1494                         /*
1495                          * Successful in waiting for previous cycle to timeout,
1496                          * now set the Flash Cycle Done.
1497                          */
1498                         hsfsts.hsf_status.flcdone = 1;
1499                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1500                 } else {
1501                         hw_dbg(hw, "Flash controller busy, cannot get access");
1502                 }
1503         }
1504
1505         return ret_val;
1506 }
1507
1508 /**
1509  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1510  *  @hw: pointer to the HW structure
1511  *  @timeout: maximum time to wait for completion
1512  *
1513  *  This function starts a flash cycle and waits for its completion.
1514  **/
1515 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1516 {
1517         union ich8_hws_flash_ctrl hsflctl;
1518         union ich8_hws_flash_status hsfsts;
1519         s32 ret_val = -E1000_ERR_NVM;
1520         u32 i = 0;
1521
1522         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1523         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1524         hsflctl.hsf_ctrl.flcgo = 1;
1525         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1526
1527         /* wait till FDONE bit is set to 1 */
1528         do {
1529                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1530                 if (hsfsts.hsf_status.flcdone == 1)
1531                         break;
1532                 udelay(1);
1533         } while (i++ < timeout);
1534
1535         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1536                 return 0;
1537
1538         return ret_val;
1539 }
1540
1541 /**
1542  *  e1000_read_flash_word_ich8lan - Read word from flash
1543  *  @hw: pointer to the HW structure
1544  *  @offset: offset to data location
1545  *  @data: pointer to the location for storing the data
1546  *
1547  *  Reads the flash word at offset into data.  Offset is converted
1548  *  to bytes before read.
1549  **/
1550 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1551                                          u16 *data)
1552 {
1553         /* Must convert offset into bytes. */
1554         offset <<= 1;
1555
1556         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1557 }
1558
1559 /**
1560  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1561  *  @hw: pointer to the HW structure
1562  *  @offset: The offset of the byte to read.
1563  *  @data: Pointer to a byte to store the value read.
1564  *
1565  *  Reads a single byte from the NVM using the flash access registers.
1566  **/
1567 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1568                                          u8 *data)
1569 {
1570         s32 ret_val;
1571         u16 word = 0;
1572
1573         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1574         if (ret_val)
1575                 return ret_val;
1576
1577         *data = (u8)word;
1578
1579         return 0;
1580 }
1581
1582 /**
1583  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1584  *  @hw: pointer to the HW structure
1585  *  @offset: The offset (in bytes) of the byte or word to read.
1586  *  @size: Size of data to read, 1=byte 2=word
1587  *  @data: Pointer to the word to store the value read.
1588  *
1589  *  Reads a byte or word from the NVM using the flash access registers.
1590  **/
1591 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1592                                          u8 size, u16 *data)
1593 {
1594         union ich8_hws_flash_status hsfsts;
1595         union ich8_hws_flash_ctrl hsflctl;
1596         u32 flash_linear_addr;
1597         u32 flash_data = 0;
1598         s32 ret_val = -E1000_ERR_NVM;
1599         u8 count = 0;
1600
1601         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1602                 return -E1000_ERR_NVM;
1603
1604         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1605                             hw->nvm.flash_base_addr;
1606
1607         do {
1608                 udelay(1);
1609                 /* Steps */
1610                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1611                 if (ret_val != 0)
1612                         break;
1613
1614                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1615                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1616                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1617                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1618                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1619
1620                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1621
1622                 ret_val = e1000_flash_cycle_ich8lan(hw,
1623                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1624
1625                 /*
1626                  * Check if FCERR is set to 1, if set to 1, clear it
1627                  * and try the whole sequence a few more times, else
1628                  * read in (shift in) the Flash Data0, the order is
1629                  * least significant byte first msb to lsb
1630                  */
1631                 if (ret_val == 0) {
1632                         flash_data = er32flash(ICH_FLASH_FDATA0);
1633                         if (size == 1) {
1634                                 *data = (u8)(flash_data & 0x000000FF);
1635                         } else if (size == 2) {
1636                                 *data = (u16)(flash_data & 0x0000FFFF);
1637                         }
1638                         break;
1639                 } else {
1640                         /*
1641                          * If we've gotten here, then things are probably
1642                          * completely hosed, but if the error condition is
1643                          * detected, it won't hurt to give it another try...
1644                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1645                          */
1646                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1647                         if (hsfsts.hsf_status.flcerr == 1) {
1648                                 /* Repeat for some time before giving up. */
1649                                 continue;
1650                         } else if (hsfsts.hsf_status.flcdone == 0) {
1651                                 hw_dbg(hw, "Timeout error - flash cycle "
1652                                          "did not complete.");
1653                                 break;
1654                         }
1655                 }
1656         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1657
1658         return ret_val;
1659 }
1660
1661 /**
1662  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1663  *  @hw: pointer to the HW structure
1664  *  @offset: The offset (in bytes) of the word(s) to write.
1665  *  @words: Size of data to write in words
1666  *  @data: Pointer to the word(s) to write at offset.
1667  *
1668  *  Writes a byte or word to the NVM using the flash access registers.
1669  **/
1670 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1671                                    u16 *data)
1672 {
1673         struct e1000_nvm_info *nvm = &hw->nvm;
1674         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1675         u16 i;
1676
1677         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1678             (words == 0)) {
1679                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1680                 return -E1000_ERR_NVM;
1681         }
1682
1683         nvm->ops.acquire_nvm(hw);
1684
1685         for (i = 0; i < words; i++) {
1686                 dev_spec->shadow_ram[offset+i].modified = 1;
1687                 dev_spec->shadow_ram[offset+i].value = data[i];
1688         }
1689
1690         nvm->ops.release_nvm(hw);
1691
1692         return 0;
1693 }
1694
1695 /**
1696  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1697  *  @hw: pointer to the HW structure
1698  *
1699  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1700  *  which writes the checksum to the shadow ram.  The changes in the shadow
1701  *  ram are then committed to the EEPROM by processing each bank at a time
1702  *  checking for the modified bit and writing only the pending changes.
1703  *  After a successful commit, the shadow ram is cleared and is ready for
1704  *  future writes.
1705  **/
1706 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1707 {
1708         struct e1000_nvm_info *nvm = &hw->nvm;
1709         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1710         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1711         s32 ret_val;
1712         u16 data;
1713
1714         ret_val = e1000e_update_nvm_checksum_generic(hw);
1715         if (ret_val)
1716                 goto out;
1717
1718         if (nvm->type != e1000_nvm_flash_sw)
1719                 goto out;
1720
1721         nvm->ops.acquire_nvm(hw);
1722
1723         /*
1724          * We're writing to the opposite bank so if we're on bank 1,
1725          * write to bank 0 etc.  We also need to erase the segment that
1726          * is going to be written
1727          */
1728         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1729         if (ret_val) {
1730                 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1731                 bank = 0;
1732         }
1733
1734         if (bank == 0) {
1735                 new_bank_offset = nvm->flash_bank_size;
1736                 old_bank_offset = 0;
1737                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1738                 if (ret_val) {
1739                         nvm->ops.release_nvm(hw);
1740                         goto out;
1741                 }
1742         } else {
1743                 old_bank_offset = nvm->flash_bank_size;
1744                 new_bank_offset = 0;
1745                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1746                 if (ret_val) {
1747                         nvm->ops.release_nvm(hw);
1748                         goto out;
1749                 }
1750         }
1751
1752         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1753                 /*
1754                  * Determine whether to write the value stored
1755                  * in the other NVM bank or a modified value stored
1756                  * in the shadow RAM
1757                  */
1758                 if (dev_spec->shadow_ram[i].modified) {
1759                         data = dev_spec->shadow_ram[i].value;
1760                 } else {
1761                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1762                                                                 old_bank_offset,
1763                                                                 &data);
1764                         if (ret_val)
1765                                 break;
1766                 }
1767
1768                 /*
1769                  * If the word is 0x13, then make sure the signature bits
1770                  * (15:14) are 11b until the commit has completed.
1771                  * This will allow us to write 10b which indicates the
1772                  * signature is valid.  We want to do this after the write
1773                  * has completed so that we don't mark the segment valid
1774                  * while the write is still in progress
1775                  */
1776                 if (i == E1000_ICH_NVM_SIG_WORD)
1777                         data |= E1000_ICH_NVM_SIG_MASK;
1778
1779                 /* Convert offset to bytes. */
1780                 act_offset = (i + new_bank_offset) << 1;
1781
1782                 udelay(100);
1783                 /* Write the bytes to the new bank. */
1784                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1785                                                                act_offset,
1786                                                                (u8)data);
1787                 if (ret_val)
1788                         break;
1789
1790                 udelay(100);
1791                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1792                                                           act_offset + 1,
1793                                                           (u8)(data >> 8));
1794                 if (ret_val)
1795                         break;
1796         }
1797
1798         /*
1799          * Don't bother writing the segment valid bits if sector
1800          * programming failed.
1801          */
1802         if (ret_val) {
1803                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1804                 hw_dbg(hw, "Flash commit failed.\n");
1805                 nvm->ops.release_nvm(hw);
1806                 goto out;
1807         }
1808
1809         /*
1810          * Finally validate the new segment by setting bit 15:14
1811          * to 10b in word 0x13 , this can be done without an
1812          * erase as well since these bits are 11 to start with
1813          * and we need to change bit 14 to 0b
1814          */
1815         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1816         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1817         if (ret_val) {
1818                 nvm->ops.release_nvm(hw);
1819                 goto out;
1820         }
1821         data &= 0xBFFF;
1822         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1823                                                        act_offset * 2 + 1,
1824                                                        (u8)(data >> 8));
1825         if (ret_val) {
1826                 nvm->ops.release_nvm(hw);
1827                 goto out;
1828         }
1829
1830         /*
1831          * And invalidate the previously valid segment by setting
1832          * its signature word (0x13) high_byte to 0b. This can be
1833          * done without an erase because flash erase sets all bits
1834          * to 1's. We can write 1's to 0's without an erase
1835          */
1836         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1837         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1838         if (ret_val) {
1839                 nvm->ops.release_nvm(hw);
1840                 goto out;
1841         }
1842
1843         /* Great!  Everything worked, we can now clear the cached entries. */
1844         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1845                 dev_spec->shadow_ram[i].modified = 0;
1846                 dev_spec->shadow_ram[i].value = 0xFFFF;
1847         }
1848
1849         nvm->ops.release_nvm(hw);
1850
1851         /*
1852          * Reload the EEPROM, or else modifications will not appear
1853          * until after the next adapter reset.
1854          */
1855         e1000e_reload_nvm(hw);
1856         msleep(10);
1857
1858 out:
1859         if (ret_val)
1860                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1861
1862         return ret_val;
1863 }
1864
1865 /**
1866  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1867  *  @hw: pointer to the HW structure
1868  *
1869  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1870  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1871  *  calculated, in which case we need to calculate the checksum and set bit 6.
1872  **/
1873 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1874 {
1875         s32 ret_val;
1876         u16 data;
1877
1878         /*
1879          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1880          * needs to be fixed.  This bit is an indication that the NVM
1881          * was prepared by OEM software and did not calculate the
1882          * checksum...a likely scenario.
1883          */
1884         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1885         if (ret_val)
1886                 return ret_val;
1887
1888         if ((data & 0x40) == 0) {
1889                 data |= 0x40;
1890                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1891                 if (ret_val)
1892                         return ret_val;
1893                 ret_val = e1000e_update_nvm_checksum(hw);
1894                 if (ret_val)
1895                         return ret_val;
1896         }
1897
1898         return e1000e_validate_nvm_checksum_generic(hw);
1899 }
1900
1901 /**
1902  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1903  *  @hw: pointer to the HW structure
1904  *
1905  *  To prevent malicious write/erase of the NVM, set it to be read-only
1906  *  so that the hardware ignores all write/erase cycles of the NVM via
1907  *  the flash control registers.  The shadow-ram copy of the NVM will
1908  *  still be updated, however any updates to this copy will not stick
1909  *  across driver reloads.
1910  **/
1911 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1912 {
1913         struct e1000_nvm_info *nvm = &hw->nvm;
1914         union ich8_flash_protected_range pr0;
1915         union ich8_hws_flash_status hsfsts;
1916         u32 gfpreg;
1917
1918         nvm->ops.acquire_nvm(hw);
1919
1920         gfpreg = er32flash(ICH_FLASH_GFPREG);
1921
1922         /* Write-protect GbE Sector of NVM */
1923         pr0.regval = er32flash(ICH_FLASH_PR0);
1924         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1925         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1926         pr0.range.wpe = true;
1927         ew32flash(ICH_FLASH_PR0, pr0.regval);
1928
1929         /*
1930          * Lock down a subset of GbE Flash Control Registers, e.g.
1931          * PR0 to prevent the write-protection from being lifted.
1932          * Once FLOCKDN is set, the registers protected by it cannot
1933          * be written until FLOCKDN is cleared by a hardware reset.
1934          */
1935         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1936         hsfsts.hsf_status.flockdn = true;
1937         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1938
1939         nvm->ops.release_nvm(hw);
1940 }
1941
1942 /**
1943  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1944  *  @hw: pointer to the HW structure
1945  *  @offset: The offset (in bytes) of the byte/word to read.
1946  *  @size: Size of data to read, 1=byte 2=word
1947  *  @data: The byte(s) to write to the NVM.
1948  *
1949  *  Writes one/two bytes to the NVM using the flash access registers.
1950  **/
1951 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1952                                           u8 size, u16 data)
1953 {
1954         union ich8_hws_flash_status hsfsts;
1955         union ich8_hws_flash_ctrl hsflctl;
1956         u32 flash_linear_addr;
1957         u32 flash_data = 0;
1958         s32 ret_val;
1959         u8 count = 0;
1960
1961         if (size < 1 || size > 2 || data > size * 0xff ||
1962             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1963                 return -E1000_ERR_NVM;
1964
1965         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1966                             hw->nvm.flash_base_addr;
1967
1968         do {
1969                 udelay(1);
1970                 /* Steps */
1971                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1972                 if (ret_val)
1973                         break;
1974
1975                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1976                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1977                 hsflctl.hsf_ctrl.fldbcount = size -1;
1978                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1979                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1980
1981                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1982
1983                 if (size == 1)
1984                         flash_data = (u32)data & 0x00FF;
1985                 else
1986                         flash_data = (u32)data;
1987
1988                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1989
1990                 /*
1991                  * check if FCERR is set to 1 , if set to 1, clear it
1992                  * and try the whole sequence a few more times else done
1993                  */
1994                 ret_val = e1000_flash_cycle_ich8lan(hw,
1995                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1996                 if (!ret_val)
1997                         break;
1998
1999                 /*
2000                  * If we're here, then things are most likely
2001                  * completely hosed, but if the error condition
2002                  * is detected, it won't hurt to give it another
2003                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2004                  */
2005                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2006                 if (hsfsts.hsf_status.flcerr == 1)
2007                         /* Repeat for some time before giving up. */
2008                         continue;
2009                 if (hsfsts.hsf_status.flcdone == 0) {
2010                         hw_dbg(hw, "Timeout error - flash cycle "
2011                                  "did not complete.");
2012                         break;
2013                 }
2014         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2015
2016         return ret_val;
2017 }
2018
2019 /**
2020  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2021  *  @hw: pointer to the HW structure
2022  *  @offset: The index of the byte to read.
2023  *  @data: The byte to write to the NVM.
2024  *
2025  *  Writes a single byte to the NVM using the flash access registers.
2026  **/
2027 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2028                                           u8 data)
2029 {
2030         u16 word = (u16)data;
2031
2032         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2033 }
2034
2035 /**
2036  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2037  *  @hw: pointer to the HW structure
2038  *  @offset: The offset of the byte to write.
2039  *  @byte: The byte to write to the NVM.
2040  *
2041  *  Writes a single byte to the NVM using the flash access registers.
2042  *  Goes through a retry algorithm before giving up.
2043  **/
2044 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2045                                                 u32 offset, u8 byte)
2046 {
2047         s32 ret_val;
2048         u16 program_retries;
2049
2050         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2051         if (!ret_val)
2052                 return ret_val;
2053
2054         for (program_retries = 0; program_retries < 100; program_retries++) {
2055                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
2056                 udelay(100);
2057                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2058                 if (!ret_val)
2059                         break;
2060         }
2061         if (program_retries == 100)
2062                 return -E1000_ERR_NVM;
2063
2064         return 0;
2065 }
2066
2067 /**
2068  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2069  *  @hw: pointer to the HW structure
2070  *  @bank: 0 for first bank, 1 for second bank, etc.
2071  *
2072  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2073  *  bank N is 4096 * N + flash_reg_addr.
2074  **/
2075 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2076 {
2077         struct e1000_nvm_info *nvm = &hw->nvm;
2078         union ich8_hws_flash_status hsfsts;
2079         union ich8_hws_flash_ctrl hsflctl;
2080         u32 flash_linear_addr;
2081         /* bank size is in 16bit words - adjust to bytes */
2082         u32 flash_bank_size = nvm->flash_bank_size * 2;
2083         s32 ret_val;
2084         s32 count = 0;
2085         s32 iteration;
2086         s32 sector_size;
2087         s32 j;
2088
2089         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2090
2091         /*
2092          * Determine HW Sector size: Read BERASE bits of hw flash status
2093          * register
2094          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2095          *     consecutive sectors.  The start index for the nth Hw sector
2096          *     can be calculated as = bank * 4096 + n * 256
2097          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2098          *     The start index for the nth Hw sector can be calculated
2099          *     as = bank * 4096
2100          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2101          *     (ich9 only, otherwise error condition)
2102          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2103          */
2104         switch (hsfsts.hsf_status.berasesz) {
2105         case 0:
2106                 /* Hw sector size 256 */
2107                 sector_size = ICH_FLASH_SEG_SIZE_256;
2108                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2109                 break;
2110         case 1:
2111                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2112                 iteration = 1;
2113                 break;
2114         case 2:
2115                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2116                 iteration = 1;
2117                 break;
2118         case 3:
2119                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2120                 iteration = 1;
2121                 break;
2122         default:
2123                 return -E1000_ERR_NVM;
2124         }
2125
2126         /* Start with the base address, then add the sector offset. */
2127         flash_linear_addr = hw->nvm.flash_base_addr;
2128         flash_linear_addr += (bank) ? flash_bank_size : 0;
2129
2130         for (j = 0; j < iteration ; j++) {
2131                 do {
2132                         /* Steps */
2133                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2134                         if (ret_val)
2135                                 return ret_val;
2136
2137                         /*
2138                          * Write a value 11 (block Erase) in Flash
2139                          * Cycle field in hw flash control
2140                          */
2141                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2142                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2143                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2144
2145                         /*
2146                          * Write the last 24 bits of an index within the
2147                          * block into Flash Linear address field in Flash
2148                          * Address.
2149                          */
2150                         flash_linear_addr += (j * sector_size);
2151                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2152
2153                         ret_val = e1000_flash_cycle_ich8lan(hw,
2154                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2155                         if (ret_val == 0)
2156                                 break;
2157
2158                         /*
2159                          * Check if FCERR is set to 1.  If 1,
2160                          * clear it and try the whole sequence
2161                          * a few more times else Done
2162                          */
2163                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2164                         if (hsfsts.hsf_status.flcerr == 1)
2165                                 /* repeat for some time before giving up */
2166                                 continue;
2167                         else if (hsfsts.hsf_status.flcdone == 0)
2168                                 return ret_val;
2169                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2170         }
2171
2172         return 0;
2173 }
2174
2175 /**
2176  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2177  *  @hw: pointer to the HW structure
2178  *  @data: Pointer to the LED settings
2179  *
2180  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2181  *  settings is all 0's or F's, set the LED default to a valid LED default
2182  *  setting.
2183  **/
2184 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2185 {
2186         s32 ret_val;
2187
2188         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2189         if (ret_val) {
2190                 hw_dbg(hw, "NVM Read Error\n");
2191                 return ret_val;
2192         }
2193
2194         if (*data == ID_LED_RESERVED_0000 ||
2195             *data == ID_LED_RESERVED_FFFF)
2196                 *data = ID_LED_DEFAULT_ICH8LAN;
2197
2198         return 0;
2199 }
2200
2201 /**
2202  *  e1000_id_led_init_pchlan - store LED configurations
2203  *  @hw: pointer to the HW structure
2204  *
2205  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2206  *  the PHY LED configuration register.
2207  *
2208  *  PCH also does not have an "always on" or "always off" mode which
2209  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2210  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2211  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2212  *  link based on logic in e1000_led_[on|off]_pchlan().
2213  **/
2214 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2215 {
2216         struct e1000_mac_info *mac = &hw->mac;
2217         s32 ret_val;
2218         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2219         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2220         u16 data, i, temp, shift;
2221
2222         /* Get default ID LED modes */
2223         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2224         if (ret_val)
2225                 goto out;
2226
2227         mac->ledctl_default = er32(LEDCTL);
2228         mac->ledctl_mode1 = mac->ledctl_default;
2229         mac->ledctl_mode2 = mac->ledctl_default;
2230
2231         for (i = 0; i < 4; i++) {
2232                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2233                 shift = (i * 5);
2234                 switch (temp) {
2235                 case ID_LED_ON1_DEF2:
2236                 case ID_LED_ON1_ON2:
2237                 case ID_LED_ON1_OFF2:
2238                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2239                         mac->ledctl_mode1 |= (ledctl_on << shift);
2240                         break;
2241                 case ID_LED_OFF1_DEF2:
2242                 case ID_LED_OFF1_ON2:
2243                 case ID_LED_OFF1_OFF2:
2244                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2245                         mac->ledctl_mode1 |= (ledctl_off << shift);
2246                         break;
2247                 default:
2248                         /* Do nothing */
2249                         break;
2250                 }
2251                 switch (temp) {
2252                 case ID_LED_DEF1_ON2:
2253                 case ID_LED_ON1_ON2:
2254                 case ID_LED_OFF1_ON2:
2255                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2256                         mac->ledctl_mode2 |= (ledctl_on << shift);
2257                         break;
2258                 case ID_LED_DEF1_OFF2:
2259                 case ID_LED_ON1_OFF2:
2260                 case ID_LED_OFF1_OFF2:
2261                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2262                         mac->ledctl_mode2 |= (ledctl_off << shift);
2263                         break;
2264                 default:
2265                         /* Do nothing */
2266                         break;
2267                 }
2268         }
2269
2270 out:
2271         return ret_val;
2272 }
2273
2274 /**
2275  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2276  *  @hw: pointer to the HW structure
2277  *
2278  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2279  *  register, so the the bus width is hard coded.
2280  **/
2281 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2282 {
2283         struct e1000_bus_info *bus = &hw->bus;
2284         s32 ret_val;
2285
2286         ret_val = e1000e_get_bus_info_pcie(hw);
2287
2288         /*
2289          * ICH devices are "PCI Express"-ish.  They have
2290          * a configuration space, but do not contain
2291          * PCI Express Capability registers, so bus width
2292          * must be hardcoded.
2293          */
2294         if (bus->width == e1000_bus_width_unknown)
2295                 bus->width = e1000_bus_width_pcie_x1;
2296
2297         return ret_val;
2298 }
2299
2300 /**
2301  *  e1000_reset_hw_ich8lan - Reset the hardware
2302  *  @hw: pointer to the HW structure
2303  *
2304  *  Does a full reset of the hardware which includes a reset of the PHY and
2305  *  MAC.
2306  **/
2307 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2308 {
2309         u16 reg;
2310         u32 ctrl, icr, kab;
2311         s32 ret_val;
2312
2313         /*
2314          * Prevent the PCI-E bus from sticking if there is no TLP connection
2315          * on the last TLP read/write transaction when MAC is reset.
2316          */
2317         ret_val = e1000e_disable_pcie_master(hw);
2318         if (ret_val) {
2319                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2320         }
2321
2322         hw_dbg(hw, "Masking off all interrupts\n");
2323         ew32(IMC, 0xffffffff);
2324
2325         /*
2326          * Disable the Transmit and Receive units.  Then delay to allow
2327          * any pending transactions to complete before we hit the MAC
2328          * with the global reset.
2329          */
2330         ew32(RCTL, 0);
2331         ew32(TCTL, E1000_TCTL_PSP);
2332         e1e_flush();
2333
2334         msleep(10);
2335
2336         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2337         if (hw->mac.type == e1000_ich8lan) {
2338                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2339                 ew32(PBA, E1000_PBA_8K);
2340                 /* Set Packet Buffer Size to 16k. */
2341                 ew32(PBS, E1000_PBS_16K);
2342         }
2343
2344         ctrl = er32(CTRL);
2345
2346         if (!e1000_check_reset_block(hw)) {
2347                 /* Clear PHY Reset Asserted bit */
2348                 if (hw->mac.type >= e1000_pchlan) {
2349                         u32 status = er32(STATUS);
2350                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2351                 }
2352
2353                 /*
2354                  * PHY HW reset requires MAC CORE reset at the same
2355                  * time to make sure the interface between MAC and the
2356                  * external PHY is reset.
2357                  */
2358                 ctrl |= E1000_CTRL_PHY_RST;
2359         }
2360         ret_val = e1000_acquire_swflag_ich8lan(hw);
2361         /* Whether or not the swflag was acquired, we need to reset the part */
2362         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2363         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2364         msleep(20);
2365
2366         if (!ret_val)
2367                 e1000_release_swflag_ich8lan(hw);
2368
2369         if (ctrl & E1000_CTRL_PHY_RST)
2370                 ret_val = hw->phy.ops.get_cfg_done(hw);
2371
2372         if (hw->mac.type >= e1000_ich10lan) {
2373                 e1000_lan_init_done_ich8lan(hw);
2374         } else {
2375                 ret_val = e1000e_get_auto_rd_done(hw);
2376                 if (ret_val) {
2377                         /*
2378                          * When auto config read does not complete, do not
2379                          * return with an error. This can happen in situations
2380                          * where there is no eeprom and prevents getting link.
2381                          */
2382                         hw_dbg(hw, "Auto Read Done did not complete\n");
2383                 }
2384         }
2385         /* Dummy read to clear the phy wakeup bit after lcd reset */
2386         if (hw->mac.type == e1000_pchlan)
2387                 e1e_rphy(hw, BM_WUC, &reg);
2388
2389         /*
2390          * For PCH, this write will make sure that any noise
2391          * will be detected as a CRC error and be dropped rather than show up
2392          * as a bad packet to the DMA engine.
2393          */
2394         if (hw->mac.type == e1000_pchlan)
2395                 ew32(CRC_OFFSET, 0x65656565);
2396
2397         ew32(IMC, 0xffffffff);
2398         icr = er32(ICR);
2399
2400         kab = er32(KABGTXD);
2401         kab |= E1000_KABGTXD_BGSQLBIAS;
2402         ew32(KABGTXD, kab);
2403
2404         if (hw->mac.type == e1000_pchlan)
2405                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2406
2407         return ret_val;
2408 }
2409
2410 /**
2411  *  e1000_init_hw_ich8lan - Initialize the hardware
2412  *  @hw: pointer to the HW structure
2413  *
2414  *  Prepares the hardware for transmit and receive by doing the following:
2415  *   - initialize hardware bits
2416  *   - initialize LED identification
2417  *   - setup receive address registers
2418  *   - setup flow control
2419  *   - setup transmit descriptors
2420  *   - clear statistics
2421  **/
2422 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2423 {
2424         struct e1000_mac_info *mac = &hw->mac;
2425         u32 ctrl_ext, txdctl, snoop;
2426         s32 ret_val;
2427         u16 i;
2428
2429         e1000_initialize_hw_bits_ich8lan(hw);
2430
2431         /* Initialize identification LED */
2432         ret_val = mac->ops.id_led_init(hw);
2433         if (ret_val) {
2434                 hw_dbg(hw, "Error initializing identification LED\n");
2435                 return ret_val;
2436         }
2437
2438         /* Setup the receive address. */
2439         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2440
2441         /* Zero out the Multicast HASH table */
2442         hw_dbg(hw, "Zeroing the MTA\n");
2443         for (i = 0; i < mac->mta_reg_count; i++)
2444                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2445
2446         /*
2447          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2448          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2449          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2450          */
2451         if (hw->phy.type == e1000_phy_82578) {
2452                 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2453                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2454                 if (ret_val)
2455                         return ret_val;
2456         }
2457
2458         /* Setup link and flow control */
2459         ret_val = e1000_setup_link_ich8lan(hw);
2460
2461         /* Set the transmit descriptor write-back policy for both queues */
2462         txdctl = er32(TXDCTL(0));
2463         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2464                  E1000_TXDCTL_FULL_TX_DESC_WB;
2465         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2466                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2467         ew32(TXDCTL(0), txdctl);
2468         txdctl = er32(TXDCTL(1));
2469         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2470                  E1000_TXDCTL_FULL_TX_DESC_WB;
2471         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2472                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2473         ew32(TXDCTL(1), txdctl);
2474
2475         /*
2476          * ICH8 has opposite polarity of no_snoop bits.
2477          * By default, we should use snoop behavior.
2478          */
2479         if (mac->type == e1000_ich8lan)
2480                 snoop = PCIE_ICH8_SNOOP_ALL;
2481         else
2482                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2483         e1000e_set_pcie_no_snoop(hw, snoop);
2484
2485         ctrl_ext = er32(CTRL_EXT);
2486         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2487         ew32(CTRL_EXT, ctrl_ext);
2488
2489         /*
2490          * Clear all of the statistics registers (clear on read).  It is
2491          * important that we do this after we have tried to establish link
2492          * because the symbol error count will increment wildly if there
2493          * is no link.
2494          */
2495         e1000_clear_hw_cntrs_ich8lan(hw);
2496
2497         return 0;
2498 }
2499 /**
2500  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2501  *  @hw: pointer to the HW structure
2502  *
2503  *  Sets/Clears required hardware bits necessary for correctly setting up the
2504  *  hardware for transmit and receive.
2505  **/
2506 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2507 {
2508         u32 reg;
2509
2510         /* Extended Device Control */
2511         reg = er32(CTRL_EXT);
2512         reg |= (1 << 22);
2513         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2514         if (hw->mac.type >= e1000_pchlan)
2515                 reg |= E1000_CTRL_EXT_PHYPDEN;
2516         ew32(CTRL_EXT, reg);
2517
2518         /* Transmit Descriptor Control 0 */
2519         reg = er32(TXDCTL(0));
2520         reg |= (1 << 22);
2521         ew32(TXDCTL(0), reg);
2522
2523         /* Transmit Descriptor Control 1 */
2524         reg = er32(TXDCTL(1));
2525         reg |= (1 << 22);
2526         ew32(TXDCTL(1), reg);
2527
2528         /* Transmit Arbitration Control 0 */
2529         reg = er32(TARC(0));
2530         if (hw->mac.type == e1000_ich8lan)
2531                 reg |= (1 << 28) | (1 << 29);
2532         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2533         ew32(TARC(0), reg);
2534
2535         /* Transmit Arbitration Control 1 */
2536         reg = er32(TARC(1));
2537         if (er32(TCTL) & E1000_TCTL_MULR)
2538                 reg &= ~(1 << 28);
2539         else
2540                 reg |= (1 << 28);
2541         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2542         ew32(TARC(1), reg);
2543
2544         /* Device Status */
2545         if (hw->mac.type == e1000_ich8lan) {
2546                 reg = er32(STATUS);
2547                 reg &= ~(1 << 31);
2548                 ew32(STATUS, reg);
2549         }
2550 }
2551
2552 /**
2553  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2554  *  @hw: pointer to the HW structure
2555  *
2556  *  Determines which flow control settings to use, then configures flow
2557  *  control.  Calls the appropriate media-specific link configuration
2558  *  function.  Assuming the adapter has a valid link partner, a valid link
2559  *  should be established.  Assumes the hardware has previously been reset
2560  *  and the transmitter and receiver are not enabled.
2561  **/
2562 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2563 {
2564         s32 ret_val;
2565
2566         if (e1000_check_reset_block(hw))
2567                 return 0;
2568
2569         /*
2570          * ICH parts do not have a word in the NVM to determine
2571          * the default flow control setting, so we explicitly
2572          * set it to full.
2573          */
2574         if (hw->fc.requested_mode == e1000_fc_default) {
2575                 /* Workaround h/w hang when Tx flow control enabled */
2576                 if (hw->mac.type == e1000_pchlan)
2577                         hw->fc.requested_mode = e1000_fc_rx_pause;
2578                 else
2579                         hw->fc.requested_mode = e1000_fc_full;
2580         }
2581
2582         /*
2583          * Save off the requested flow control mode for use later.  Depending
2584          * on the link partner's capabilities, we may or may not use this mode.
2585          */
2586         hw->fc.current_mode = hw->fc.requested_mode;
2587
2588         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2589                 hw->fc.current_mode);
2590
2591         /* Continue to configure the copper link. */
2592         ret_val = e1000_setup_copper_link_ich8lan(hw);
2593         if (ret_val)
2594                 return ret_val;
2595
2596         ew32(FCTTV, hw->fc.pause_time);
2597         if ((hw->phy.type == e1000_phy_82578) ||
2598             (hw->phy.type == e1000_phy_82577)) {
2599                 ret_val = hw->phy.ops.write_phy_reg(hw,
2600                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2601                                              hw->fc.pause_time);
2602                 if (ret_val)
2603                         return ret_val;
2604         }
2605
2606         return e1000e_set_fc_watermarks(hw);
2607 }
2608
2609 /**
2610  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2611  *  @hw: pointer to the HW structure
2612  *
2613  *  Configures the kumeran interface to the PHY to wait the appropriate time
2614  *  when polling the PHY, then call the generic setup_copper_link to finish
2615  *  configuring the copper link.
2616  **/
2617 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2618 {
2619         u32 ctrl;
2620         s32 ret_val;
2621         u16 reg_data;
2622
2623         ctrl = er32(CTRL);
2624         ctrl |= E1000_CTRL_SLU;
2625         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2626         ew32(CTRL, ctrl);
2627
2628         /*
2629          * Set the mac to wait the maximum time between each iteration
2630          * and increase the max iterations when polling the phy;
2631          * this fixes erroneous timeouts at 10Mbps.
2632          */
2633         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2634         if (ret_val)
2635                 return ret_val;
2636         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2637         if (ret_val)
2638                 return ret_val;
2639         reg_data |= 0x3F;
2640         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2641         if (ret_val)
2642                 return ret_val;
2643
2644         switch (hw->phy.type) {
2645         case e1000_phy_igp_3:
2646                 ret_val = e1000e_copper_link_setup_igp(hw);
2647                 if (ret_val)
2648                         return ret_val;
2649                 break;
2650         case e1000_phy_bm:
2651         case e1000_phy_82578:
2652                 ret_val = e1000e_copper_link_setup_m88(hw);
2653                 if (ret_val)
2654                         return ret_val;
2655                 break;
2656         case e1000_phy_82577:
2657                 ret_val = e1000_copper_link_setup_82577(hw);
2658                 if (ret_val)
2659                         return ret_val;
2660                 break;
2661         case e1000_phy_ife:
2662                 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2663                                                &reg_data);
2664                 if (ret_val)
2665                         return ret_val;
2666
2667                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2668
2669                 switch (hw->phy.mdix) {
2670                 case 1:
2671                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2672                         break;
2673                 case 2:
2674                         reg_data |= IFE_PMC_FORCE_MDIX;
2675                         break;
2676                 case 0:
2677                 default:
2678                         reg_data |= IFE_PMC_AUTO_MDIX;
2679                         break;
2680                 }
2681                 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2682                                                 reg_data);
2683                 if (ret_val)
2684                         return ret_val;
2685                 break;
2686         default:
2687                 break;
2688         }
2689         return e1000e_setup_copper_link(hw);
2690 }
2691
2692 /**
2693  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2694  *  @hw: pointer to the HW structure
2695  *  @speed: pointer to store current link speed
2696  *  @duplex: pointer to store the current link duplex
2697  *
2698  *  Calls the generic get_speed_and_duplex to retrieve the current link
2699  *  information and then calls the Kumeran lock loss workaround for links at
2700  *  gigabit speeds.
2701  **/
2702 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2703                                           u16 *duplex)
2704 {
2705         s32 ret_val;
2706
2707         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2708         if (ret_val)
2709                 return ret_val;
2710
2711         if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
2712                 ret_val = e1000e_write_kmrn_reg(hw,
2713                                                   E1000_KMRNCTRLSTA_K1_CONFIG,
2714                                                   E1000_KMRNCTRLSTA_K1_DISABLE);
2715                 if (ret_val)
2716                         return ret_val;
2717         }
2718
2719         if ((hw->mac.type == e1000_ich8lan) &&
2720             (hw->phy.type == e1000_phy_igp_3) &&
2721             (*speed == SPEED_1000)) {
2722                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2723         }
2724
2725         return ret_val;
2726 }
2727
2728 /**
2729  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2730  *  @hw: pointer to the HW structure
2731  *
2732  *  Work-around for 82566 Kumeran PCS lock loss:
2733  *  On link status change (i.e. PCI reset, speed change) and link is up and
2734  *  speed is gigabit-
2735  *    0) if workaround is optionally disabled do nothing
2736  *    1) wait 1ms for Kumeran link to come up
2737  *    2) check Kumeran Diagnostic register PCS lock loss bit
2738  *    3) if not set the link is locked (all is good), otherwise...
2739  *    4) reset the PHY
2740  *    5) repeat up to 10 times
2741  *  Note: this is only called for IGP3 copper when speed is 1gb.
2742  **/
2743 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2744 {
2745         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2746         u32 phy_ctrl;
2747         s32 ret_val;
2748         u16 i, data;
2749         bool link;
2750
2751         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2752                 return 0;
2753
2754         /*
2755          * Make sure link is up before proceeding.  If not just return.
2756          * Attempting this while link is negotiating fouled up link
2757          * stability
2758          */
2759         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2760         if (!link)
2761                 return 0;
2762
2763         for (i = 0; i < 10; i++) {
2764                 /* read once to clear */
2765                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2766                 if (ret_val)
2767                         return ret_val;
2768                 /* and again to get new status */
2769                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2770                 if (ret_val)
2771                         return ret_val;
2772
2773                 /* check for PCS lock */
2774                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2775                         return 0;
2776
2777                 /* Issue PHY reset */
2778                 e1000_phy_hw_reset(hw);
2779                 mdelay(5);
2780         }
2781         /* Disable GigE link negotiation */
2782         phy_ctrl = er32(PHY_CTRL);
2783         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2784                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2785         ew32(PHY_CTRL, phy_ctrl);
2786
2787         /*
2788          * Call gig speed drop workaround on Gig disable before accessing
2789          * any PHY registers
2790          */
2791         e1000e_gig_downshift_workaround_ich8lan(hw);
2792
2793         /* unable to acquire PCS lock */
2794         return -E1000_ERR_PHY;
2795 }
2796
2797 /**
2798  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2799  *  @hw: pointer to the HW structure
2800  *  @state: boolean value used to set the current Kumeran workaround state
2801  *
2802  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2803  *  /disabled - FALSE).
2804  **/
2805 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2806                                                  bool state)
2807 {
2808         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2809
2810         if (hw->mac.type != e1000_ich8lan) {
2811                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2812                 return;
2813         }
2814
2815         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2816 }
2817
2818 /**
2819  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2820  *  @hw: pointer to the HW structure
2821  *
2822  *  Workaround for 82566 power-down on D3 entry:
2823  *    1) disable gigabit link
2824  *    2) write VR power-down enable
2825  *    3) read it back
2826  *  Continue if successful, else issue LCD reset and repeat
2827  **/
2828 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2829 {
2830         u32 reg;
2831         u16 data;
2832         u8  retry = 0;
2833
2834         if (hw->phy.type != e1000_phy_igp_3)
2835                 return;
2836
2837         /* Try the workaround twice (if needed) */
2838         do {
2839                 /* Disable link */
2840                 reg = er32(PHY_CTRL);
2841                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2842                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2843                 ew32(PHY_CTRL, reg);
2844
2845                 /*
2846                  * Call gig speed drop workaround on Gig disable before
2847                  * accessing any PHY registers
2848                  */
2849                 if (hw->mac.type == e1000_ich8lan)
2850                         e1000e_gig_downshift_workaround_ich8lan(hw);
2851
2852                 /* Write VR power-down enable */
2853                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2854                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2855                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2856
2857                 /* Read it back and test */
2858                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2859                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2860                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2861                         break;
2862
2863                 /* Issue PHY reset and repeat at most one more time */
2864                 reg = er32(CTRL);
2865                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2866                 retry++;
2867         } while (retry);
2868 }
2869
2870 /**
2871  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2872  *  @hw: pointer to the HW structure
2873  *
2874  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2875  *  LPLU, Gig disable, MDIC PHY reset):
2876  *    1) Set Kumeran Near-end loopback
2877  *    2) Clear Kumeran Near-end loopback
2878  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2879  **/
2880 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2881 {
2882         s32 ret_val;
2883         u16 reg_data;
2884
2885         if ((hw->mac.type != e1000_ich8lan) ||
2886             (hw->phy.type != e1000_phy_igp_3))
2887                 return;
2888
2889         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2890                                       &reg_data);
2891         if (ret_val)
2892                 return;
2893         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2894         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2895                                        reg_data);
2896         if (ret_val)
2897                 return;
2898         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2899         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2900                                        reg_data);
2901 }
2902
2903 /**
2904  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2905  *  @hw: pointer to the HW structure
2906  *
2907  *  During S0 to Sx transition, it is possible the link remains at gig
2908  *  instead of negotiating to a lower speed.  Before going to Sx, set
2909  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2910  *  to a lower speed.
2911  *
2912  *  Should only be called for applicable parts.
2913  **/
2914 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2915 {
2916         u32 phy_ctrl;
2917
2918         switch (hw->mac.type) {
2919         case e1000_ich9lan:
2920         case e1000_ich10lan:
2921         case e1000_pchlan:
2922                 phy_ctrl = er32(PHY_CTRL);
2923                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2924                             E1000_PHY_CTRL_GBE_DISABLE;
2925                 ew32(PHY_CTRL, phy_ctrl);
2926
2927                 if (hw->mac.type == e1000_pchlan)
2928                         e1000_phy_hw_reset_ich8lan(hw);
2929         default:
2930                 break;
2931         }
2932
2933         return;
2934 }
2935
2936 /**
2937  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2938  *  @hw: pointer to the HW structure
2939  *
2940  *  Return the LED back to the default configuration.
2941  **/
2942 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2943 {
2944         if (hw->phy.type == e1000_phy_ife)
2945                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2946
2947         ew32(LEDCTL, hw->mac.ledctl_default);
2948         return 0;
2949 }
2950
2951 /**
2952  *  e1000_led_on_ich8lan - Turn LEDs on
2953  *  @hw: pointer to the HW structure
2954  *
2955  *  Turn on the LEDs.
2956  **/
2957 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2958 {
2959         if (hw->phy.type == e1000_phy_ife)
2960                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2961                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2962
2963         ew32(LEDCTL, hw->mac.ledctl_mode2);
2964         return 0;
2965 }
2966
2967 /**
2968  *  e1000_led_off_ich8lan - Turn LEDs off
2969  *  @hw: pointer to the HW structure
2970  *
2971  *  Turn off the LEDs.
2972  **/
2973 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2974 {
2975         if (hw->phy.type == e1000_phy_ife)
2976                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2977                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2978
2979         ew32(LEDCTL, hw->mac.ledctl_mode1);
2980         return 0;
2981 }
2982
2983 /**
2984  *  e1000_setup_led_pchlan - Configures SW controllable LED
2985  *  @hw: pointer to the HW structure
2986  *
2987  *  This prepares the SW controllable LED for use.
2988  **/
2989 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2990 {
2991         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2992                                         (u16)hw->mac.ledctl_mode1);
2993 }
2994
2995 /**
2996  *  e1000_cleanup_led_pchlan - Restore the default LED operation
2997  *  @hw: pointer to the HW structure
2998  *
2999  *  Return the LED back to the default configuration.
3000  **/
3001 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3002 {
3003         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3004                                         (u16)hw->mac.ledctl_default);
3005 }
3006
3007 /**
3008  *  e1000_led_on_pchlan - Turn LEDs on
3009  *  @hw: pointer to the HW structure
3010  *
3011  *  Turn on the LEDs.
3012  **/
3013 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3014 {
3015         u16 data = (u16)hw->mac.ledctl_mode2;
3016         u32 i, led;
3017
3018         /*
3019          * If no link, then turn LED on by setting the invert bit
3020          * for each LED that's mode is "link_up" in ledctl_mode2.
3021          */
3022         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3023                 for (i = 0; i < 3; i++) {
3024                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3025                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3026                             E1000_LEDCTL_MODE_LINK_UP)
3027                                 continue;
3028                         if (led & E1000_PHY_LED0_IVRT)
3029                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3030                         else
3031                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3032                 }
3033         }
3034
3035         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3036 }
3037
3038 /**
3039  *  e1000_led_off_pchlan - Turn LEDs off
3040  *  @hw: pointer to the HW structure
3041  *
3042  *  Turn off the LEDs.
3043  **/
3044 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3045 {
3046         u16 data = (u16)hw->mac.ledctl_mode1;
3047         u32 i, led;
3048
3049         /*
3050          * If no link, then turn LED off by clearing the invert bit
3051          * for each LED that's mode is "link_up" in ledctl_mode1.
3052          */
3053         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3054                 for (i = 0; i < 3; i++) {
3055                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3056                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3057                             E1000_LEDCTL_MODE_LINK_UP)
3058                                 continue;
3059                         if (led & E1000_PHY_LED0_IVRT)
3060                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3061                         else
3062                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3063                 }
3064         }
3065
3066         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3067 }
3068
3069 /**
3070  *  e1000_get_cfg_done_ich8lan - Read config done bit
3071  *  @hw: pointer to the HW structure
3072  *
3073  *  Read the management control register for the config done bit for
3074  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3075  *  to read the config done bit, so an error is *ONLY* logged and returns
3076  *  0.  If we were to return with error, EEPROM-less silicon
3077  *  would not be able to be reset or change link.
3078  **/
3079 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3080 {
3081         u32 bank = 0;
3082
3083         if (hw->mac.type >= e1000_pchlan) {
3084                 u32 status = er32(STATUS);
3085
3086                 if (status & E1000_STATUS_PHYRA)
3087                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3088                 else
3089                         hw_dbg(hw,
3090                                "PHY Reset Asserted not set - needs delay\n");
3091         }
3092
3093         e1000e_get_cfg_done(hw);
3094
3095         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3096         if ((hw->mac.type != e1000_ich10lan) &&
3097             (hw->mac.type != e1000_pchlan)) {
3098                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3099                     (hw->phy.type == e1000_phy_igp_3)) {
3100                         e1000e_phy_init_script_igp3(hw);
3101                 }
3102         } else {
3103                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3104                         /* Maybe we should do a basic PHY config */
3105                         hw_dbg(hw, "EEPROM not present\n");
3106                         return -E1000_ERR_CONFIG;
3107                 }
3108         }
3109
3110         return 0;
3111 }
3112
3113 /**
3114  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3115  *  @hw: pointer to the HW structure
3116  *
3117  *  Clears hardware counters specific to the silicon family and calls
3118  *  clear_hw_cntrs_generic to clear all general purpose counters.
3119  **/
3120 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3121 {
3122         u32 temp;
3123         u16 phy_data;
3124
3125         e1000e_clear_hw_cntrs_base(hw);
3126
3127         temp = er32(ALGNERRC);
3128         temp = er32(RXERRC);
3129         temp = er32(TNCRS);
3130         temp = er32(CEXTERR);
3131         temp = er32(TSCTC);
3132         temp = er32(TSCTFC);
3133
3134         temp = er32(MGTPRC);
3135         temp = er32(MGTPDC);
3136         temp = er32(MGTPTC);
3137
3138         temp = er32(IAC);
3139         temp = er32(ICRXOC);
3140
3141         /* Clear PHY statistics registers */
3142         if ((hw->phy.type == e1000_phy_82578) ||
3143             (hw->phy.type == e1000_phy_82577)) {
3144                 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3145                 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3146                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3147                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3148                 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3149                 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3150                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3151                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3152                 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3153                 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3154                 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3155                 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3156                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3157                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3158         }
3159 }
3160
3161 static struct e1000_mac_operations ich8_mac_ops = {
3162         .id_led_init            = e1000e_id_led_init,
3163         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3164         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3165         /* cleanup_led dependent on mac type */
3166         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3167         .get_bus_info           = e1000_get_bus_info_ich8lan,
3168         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3169         /* led_on dependent on mac type */
3170         /* led_off dependent on mac type */
3171         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3172         .reset_hw               = e1000_reset_hw_ich8lan,
3173         .init_hw                = e1000_init_hw_ich8lan,
3174         .setup_link             = e1000_setup_link_ich8lan,
3175         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3176         /* id_led_init dependent on mac type */
3177 };
3178
3179 static struct e1000_phy_operations ich8_phy_ops = {
3180         .acquire_phy            = e1000_acquire_swflag_ich8lan,
3181         .check_reset_block      = e1000_check_reset_block_ich8lan,
3182         .commit_phy             = NULL,
3183         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
3184         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3185         .get_cable_length       = e1000e_get_cable_length_igp_2,
3186         .get_phy_info           = e1000_get_phy_info_ich8lan,
3187         .read_phy_reg           = e1000e_read_phy_reg_igp,
3188         .release_phy            = e1000_release_swflag_ich8lan,
3189         .reset_phy              = e1000_phy_hw_reset_ich8lan,
3190         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3191         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3192         .write_phy_reg          = e1000e_write_phy_reg_igp,
3193 };
3194
3195 static struct e1000_nvm_operations ich8_nvm_ops = {
3196         .acquire_nvm            = e1000_acquire_nvm_ich8lan,
3197         .read_nvm               = e1000_read_nvm_ich8lan,
3198         .release_nvm            = e1000_release_nvm_ich8lan,
3199         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
3200         .valid_led_default      = e1000_valid_led_default_ich8lan,
3201         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
3202         .write_nvm              = e1000_write_nvm_ich8lan,
3203 };
3204
3205 struct e1000_info e1000_ich8_info = {
3206         .mac                    = e1000_ich8lan,
3207         .flags                  = FLAG_HAS_WOL
3208                                   | FLAG_IS_ICH
3209                                   | FLAG_RX_CSUM_ENABLED
3210                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3211                                   | FLAG_HAS_AMT
3212                                   | FLAG_HAS_FLASH
3213                                   | FLAG_APME_IN_WUC,
3214         .pba                    = 8,
3215         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3216         .get_variants           = e1000_get_variants_ich8lan,
3217         .mac_ops                = &ich8_mac_ops,
3218         .phy_ops                = &ich8_phy_ops,
3219         .nvm_ops                = &ich8_nvm_ops,
3220 };
3221
3222 struct e1000_info e1000_ich9_info = {
3223         .mac                    = e1000_ich9lan,
3224         .flags                  = FLAG_HAS_JUMBO_FRAMES
3225                                   | FLAG_IS_ICH
3226                                   | FLAG_HAS_WOL
3227                                   | FLAG_RX_CSUM_ENABLED
3228                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3229                                   | FLAG_HAS_AMT
3230                                   | FLAG_HAS_ERT
3231                                   | FLAG_HAS_FLASH
3232                                   | FLAG_APME_IN_WUC,
3233         .pba                    = 10,
3234         .max_hw_frame_size      = DEFAULT_JUMBO,
3235         .get_variants           = e1000_get_variants_ich8lan,
3236         .mac_ops                = &ich8_mac_ops,
3237         .phy_ops                = &ich8_phy_ops,
3238         .nvm_ops                = &ich8_nvm_ops,
3239 };
3240
3241 struct e1000_info e1000_ich10_info = {
3242         .mac                    = e1000_ich10lan,
3243         .flags                  = FLAG_HAS_JUMBO_FRAMES
3244                                   | FLAG_IS_ICH
3245                                   | FLAG_HAS_WOL
3246                                   | FLAG_RX_CSUM_ENABLED
3247                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3248                                   | FLAG_HAS_AMT
3249                                   | FLAG_HAS_ERT
3250                                   | FLAG_HAS_FLASH
3251                                   | FLAG_APME_IN_WUC,
3252         .pba                    = 10,
3253         .max_hw_frame_size      = DEFAULT_JUMBO,
3254         .get_variants           = e1000_get_variants_ich8lan,
3255         .mac_ops                = &ich8_mac_ops,
3256         .phy_ops                = &ich8_phy_ops,
3257         .nvm_ops                = &ich8_nvm_ops,
3258 };
3259
3260 struct e1000_info e1000_pch_info = {
3261         .mac                    = e1000_pchlan,
3262         .flags                  = FLAG_IS_ICH
3263                                   | FLAG_HAS_WOL
3264                                   | FLAG_RX_CSUM_ENABLED
3265                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3266                                   | FLAG_HAS_AMT
3267                                   | FLAG_HAS_FLASH
3268                                   | FLAG_HAS_JUMBO_FRAMES
3269                                   | FLAG_APME_IN_WUC,
3270         .pba                    = 26,
3271         .max_hw_frame_size      = 4096,
3272         .get_variants           = e1000_get_variants_ich8lan,
3273         .mac_ops                = &ich8_mac_ops,
3274         .phy_ops                = &ich8_phy_ops,
3275         .nvm_ops                = &ich8_nvm_ops,
3276 };