drivers/net/dsa/mv88e6xxx/global2.h

   1 /*
   2  * Marvell 88E6xxx Switch Global 2 Registers support (device address 0x1C)
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   7  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #ifndef _MV88E6XXX_GLOBAL2_H
  16 #define _MV88E6XXX_GLOBAL2_H
  17
  18 #include "chip.h"
  19
  20 #define ADDR_GLOBAL2    0x1c
  21
  22 #define GLOBAL2_INT_SOURCE      0x00
  23 #define GLOBAL2_INT_SOURCE_WATCHDOG     15
  24 #define GLOBAL2_INT_MASK        0x01
  25 #define GLOBAL2_MGMT_EN_2X      0x02
  26 #define GLOBAL2_MGMT_EN_0X      0x03
  27 #define GLOBAL2_FLOW_CONTROL    0x04
  28 #define GLOBAL2_SWITCH_MGMT     0x05
  29 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
  30 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS       BIT(14)
  31 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG    BIT(13)
  32 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
  33 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU            BIT(3)
  34 #define GLOBAL2_DEVICE_MAPPING  0x06
  35 #define GLOBAL2_DEVICE_MAPPING_UPDATE           BIT(15)
  36 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT     8
  37 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK        0x0f
  38 #define GLOBAL2_TRUNK_MASK      0x07
  39 #define GLOBAL2_TRUNK_MASK_UPDATE               BIT(15)
  40 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT            12
  41 #define GLOBAL2_TRUNK_MASK_HASK                 BIT(11)
  42 #define GLOBAL2_TRUNK_MAPPING   0x08
  43 #define GLOBAL2_TRUNK_MAPPING_UPDATE            BIT(15)
  44 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT          11
  45 #define GLOBAL2_IRL_CMD         0x09
  46 #define GLOBAL2_IRL_CMD_BUSY    BIT(15)
  47 #define GLOBAL2_IRL_CMD_OP_INIT_ALL     ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)
  48 #define GLOBAL2_IRL_CMD_OP_INIT_SEL     ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)
  49 #define GLOBAL2_IRL_CMD_OP_WRITE_SEL    ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)
  50 #define GLOBAL2_IRL_CMD_OP_READ_SEL     ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)
  51 #define GLOBAL2_IRL_DATA        0x0a
  52 #define GLOBAL2_PVT_ADDR        0x0b
  53 #define GLOBAL2_PVT_ADDR_BUSY   BIT(15)
  54 #define GLOBAL2_PVT_ADDR_OP_INIT_ONES   ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)
  55 #define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY)
  56 #define GLOBAL2_PVT_ADDR_OP_READ        ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY)
  57 #define GLOBAL2_PVT_DATA        0x0c
  58 #define GLOBAL2_SWITCH_MAC      0x0d
  59 #define GLOBAL2_ATU_STATS       0x0e
  60 #define GLOBAL2_PRIO_OVERRIDE   0x0f
  61 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP       BIT(7)
  62 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT       4
  63 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP         BIT(3)
  64 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT         0
  65 #define GLOBAL2_EEPROM_CMD              0x14
  66 #define GLOBAL2_EEPROM_CMD_BUSY         BIT(15)
  67 #define GLOBAL2_EEPROM_CMD_OP_WRITE     ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
  68 #define GLOBAL2_EEPROM_CMD_OP_READ      ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
  69 #define GLOBAL2_EEPROM_CMD_OP_LOAD      ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
  70 #define GLOBAL2_EEPROM_CMD_RUNNING      BIT(11)
  71 #define GLOBAL2_EEPROM_CMD_WRITE_EN     BIT(10)
  72 #define GLOBAL2_EEPROM_CMD_ADDR_MASK    0xff
  73 #define GLOBAL2_EEPROM_DATA     0x15
  74 #define GLOBAL2_EEPROM_ADDR     0x15 /* 6390, 6341 */
  75 #define GLOBAL2_PTP_AVB_OP      0x16
  76 #define GLOBAL2_PTP_AVB_DATA    0x17
  77 #define GLOBAL2_SMI_PHY_CMD                     0x18
  78 #define GLOBAL2_SMI_PHY_CMD_BUSY                BIT(15)
  79 #define GLOBAL2_SMI_PHY_CMD_EXTERNAL            BIT(13)
  80 #define GLOBAL2_SMI_PHY_CMD_MODE_22             BIT(12)
  81 #define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA    ((0x1 << 10) | \
  82                                                  GLOBAL2_SMI_PHY_CMD_MODE_22 | \
  83                                                  GLOBAL2_SMI_PHY_CMD_BUSY)
  84 #define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA     ((0x2 << 10) | \
  85                                                  GLOBAL2_SMI_PHY_CMD_MODE_22 | \
  86                                                  GLOBAL2_SMI_PHY_CMD_BUSY)
  87 #define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_ADDR    ((0x0 << 10) | \
  88                                                  GLOBAL2_SMI_PHY_CMD_BUSY)
  89 #define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA    ((0x1 << 10) | \
  90                                                  GLOBAL2_SMI_PHY_CMD_BUSY)
  91 #define GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA     ((0x3 << 10) | \
  92                                                  GLOBAL2_SMI_PHY_CMD_BUSY)
  93
  94 #define GLOBAL2_SMI_PHY_DATA                    0x19
  95 #define GLOBAL2_SCRATCH_MISC    0x1a
  96 #define GLOBAL2_SCRATCH_BUSY            BIT(15)
  97 #define GLOBAL2_SCRATCH_REGISTER_SHIFT  8
  98 #define GLOBAL2_SCRATCH_VALUE_MASK      0xff
  99 #define GLOBAL2_WDOG_CONTROL    0x1b
 100 #define GLOBAL2_WDOG_CONTROL_EGRESS_EVENT       BIT(7)
 101 #define GLOBAL2_WDOG_CONTROL_RMU_TIMEOUT        BIT(6)
 102 #define GLOBAL2_WDOG_CONTROL_QC_ENABLE          BIT(5)
 103 #define GLOBAL2_WDOG_CONTROL_EGRESS_HISTORY     BIT(4)
 104 #define GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE      BIT(3)
 105 #define GLOBAL2_WDOG_CONTROL_FORCE_IRQ          BIT(2)
 106 #define GLOBAL2_WDOG_CONTROL_HISTORY            BIT(1)
 107 #define GLOBAL2_WDOG_CONTROL_SWRESET            BIT(0)
 108 #define GLOBAL2_WDOG_UPDATE                     BIT(15)
 109 #define GLOBAL2_WDOG_INT_SOURCE                 (0x00 << 8)
 110 #define GLOBAL2_WDOG_INT_STATUS                 (0x10 << 8)
 111 #define GLOBAL2_WDOG_INT_ENABLE                 (0x11 << 8)
 112 #define GLOBAL2_WDOG_EVENT                      (0x12 << 8)
 113 #define GLOBAL2_WDOG_HISTORY                    (0x13 << 8)
 114 #define GLOBAL2_WDOG_DATA_MASK                  0xff
 115 #define GLOBAL2_WDOG_CUT_THROUGH                BIT(3)
 116 #define GLOBAL2_WDOG_QUEUE_CONTROLLER           BIT(2)
 117 #define GLOBAL2_WDOG_EGRESS                     BIT(1)
 118 #define GLOBAL2_WDOG_FORCE_IRQ                  BIT(0)
 119 #define GLOBAL2_QOS_WEIGHT      0x1c
 120 #define GLOBAL2_MISC            0x1d
 121 #define GLOBAL2_MISC_5_BIT_PORT BIT(14)
 122
 123 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
 124
 125 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
 126 {
 127         return 0;
 128 }
 129
 130 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
 131                               struct mii_bus *bus,
 132                               int addr, int reg, u16 *val);
 133 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
 134                                struct mii_bus *bus,
 135                                int addr, int reg, u16 val);
 136 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
 137
 138 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
 139                              struct ethtool_eeprom *eeprom, u8 *data);
 140 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
 141                              struct ethtool_eeprom *eeprom, u8 *data);
 142
 143 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
 144                               struct ethtool_eeprom *eeprom, u8 *data);
 145 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
 146                               struct ethtool_eeprom *eeprom, u8 *data);
 147
 148 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
 149                            int src_port, u16 data);
 150 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
 151
 152 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip);
 153 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
 154 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
 155 int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
 156
 157 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
 158 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
 159
 160 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
 161
 162 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
 163 {
 164         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
 165                 dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
 166                 return -EOPNOTSUPP;
 167         }
 168
 169         return 0;
 170 }
 171
 172 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
 173                                             struct mii_bus *bus,
 174                                             int addr, int reg, u16 *val)
 175 {
 176         return -EOPNOTSUPP;
 177 }
 178
 179 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
 180                                              struct mii_bus *bus,
 181                                              int addr, int reg, u16 val)
 182 {
 183         return -EOPNOTSUPP;
 184 }
 185
 186 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip,
 187                                               u8 *addr)
 188 {
 189         return -EOPNOTSUPP;
 190 }
 191
 192 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
 193                                            struct ethtool_eeprom *eeprom,
 194                                            u8 *data)
 195 {
 196         return -EOPNOTSUPP;
 197 }
 198
 199 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
 200                                            struct ethtool_eeprom *eeprom,
 201                                            u8 *data)
 202 {
 203         return -EOPNOTSUPP;
 204 }
 205
 206 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
 207                                             struct ethtool_eeprom *eeprom,
 208                                             u8 *data)
 209 {
 210         return -EOPNOTSUPP;
 211 }
 212
 213 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
 214                                             struct ethtool_eeprom *eeprom,
 215                                             u8 *data)
 216 {
 217         return -EOPNOTSUPP;
 218 }
 219
 220 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
 221                                          int src_dev, int src_port, u16 data)
 222 {
 223         return -EOPNOTSUPP;
 224 }
 225
 226 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
 227 {
 228         return -EOPNOTSUPP;
 229 }
 230
 231 static inline int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
 232 {
 233         return -EOPNOTSUPP;
 234 }
 235
 236 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
 237 {
 238         return -EOPNOTSUPP;
 239 }
 240
 241 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
 242 {
 243 }
 244
 245 static inline int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
 246 {
 247         return -EOPNOTSUPP;
 248 }
 249
 250 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
 251 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
 252
 253 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
 254
 255 #endif /* _MV88E6XXX_GLOBAL2_H */