2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/platform_data/mv88e6xxx.h>
32 #include <linux/netdevice.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/phy.h>
35 #include <linux/phylink.h>
47 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 dev_err(chip->dev, "Switch registers lock not held!\n");
55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
59 * is the only device connected to the SMI master. In this mode it responds to
60 * all 32 possible SMI addresses, and thus maps directly the internal devices.
62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
63 * multiple devices to share the SMI interface. In this mode it responds to only
64 * 2 registers, used to indirectly access the internal SMI devices.
67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
68 int addr, int reg, u16 *val)
73 return chip->smi_ops->read(chip, addr, reg, val);
76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
77 int addr, int reg, u16 val)
82 return chip->smi_ops->write(chip, addr, reg, val);
85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
86 int addr, int reg, u16 *val)
90 ret = mdiobus_read_nested(chip->bus, addr, reg);
99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
100 int addr, int reg, u16 val)
104 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
112 .read = mv88e6xxx_smi_single_chip_read,
113 .write = mv88e6xxx_smi_single_chip_write,
116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
121 for (i = 0; i < 16; i++) {
122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
126 if ((ret & SMI_CMD_BUSY) == 0)
133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
134 int addr, int reg, u16 *val)
138 /* Wait for the bus to become free. */
139 ret = mv88e6xxx_smi_multi_chip_wait(chip);
143 /* Transmit the read command. */
144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
145 SMI_CMD_OP_22_READ | (addr << 5) | reg);
149 /* Wait for the read command to complete. */
150 ret = mv88e6xxx_smi_multi_chip_wait(chip);
155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
165 int addr, int reg, u16 val)
169 /* Wait for the bus to become free. */
170 ret = mv88e6xxx_smi_multi_chip_wait(chip);
174 /* Transmit the data to write. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
179 /* Transmit the write command. */
180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
185 /* Wait for the write command to complete. */
186 ret = mv88e6xxx_smi_multi_chip_wait(chip);
193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
194 .read = mv88e6xxx_smi_multi_chip_read,
195 .write = mv88e6xxx_smi_multi_chip_write,
198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
202 assert_reg_lock(chip);
204 err = mv88e6xxx_smi_read(chip, addr, reg, val);
208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
218 assert_reg_lock(chip);
220 err = mv88e6xxx_smi_write(chip, addr, reg, val);
224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
232 struct mv88e6xxx_mdio_bus *mdio_bus;
234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
239 return mdio_bus->bus;
242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
245 unsigned int n = d->hwirq;
247 chip->g1_irq.masked |= (1 << n);
250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
253 unsigned int n = d->hwirq;
255 chip->g1_irq.masked &= ~(1 << n);
258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
260 unsigned int nhandled = 0;
261 unsigned int sub_irq;
266 mutex_lock(&chip->reg_lock);
267 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
268 mutex_unlock(&chip->reg_lock);
273 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
274 if (reg & (1 << n)) {
275 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
276 handle_nested_irq(sub_irq);
281 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
284 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
286 struct mv88e6xxx_chip *chip = dev_id;
288 return mv88e6xxx_g1_irq_thread_work(chip);
291 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
293 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
295 mutex_lock(&chip->reg_lock);
298 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
300 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
301 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
305 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
310 reg |= (~chip->g1_irq.masked & mask);
312 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
317 mutex_unlock(&chip->reg_lock);
320 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
321 .name = "mv88e6xxx-g1",
322 .irq_mask = mv88e6xxx_g1_irq_mask,
323 .irq_unmask = mv88e6xxx_g1_irq_unmask,
324 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
325 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
328 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
330 irq_hw_number_t hwirq)
332 struct mv88e6xxx_chip *chip = d->host_data;
334 irq_set_chip_data(irq, d->host_data);
335 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
336 irq_set_noprobe(irq);
341 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
342 .map = mv88e6xxx_g1_irq_domain_map,
343 .xlate = irq_domain_xlate_twocell,
346 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
351 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
352 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
353 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
355 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
356 virq = irq_find_mapping(chip->g1_irq.domain, irq);
357 irq_dispose_mapping(virq);
360 irq_domain_remove(chip->g1_irq.domain);
363 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
365 mv88e6xxx_g1_irq_free_common(chip);
367 free_irq(chip->irq, chip);
370 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
375 chip->g1_irq.nirqs = chip->info->g1_irqs;
376 chip->g1_irq.domain = irq_domain_add_simple(
377 NULL, chip->g1_irq.nirqs, 0,
378 &mv88e6xxx_g1_irq_domain_ops, chip);
379 if (!chip->g1_irq.domain)
382 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
383 irq_create_mapping(chip->g1_irq.domain, irq);
385 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
386 chip->g1_irq.masked = ~0;
388 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
392 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
394 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
398 /* Reading the interrupt status clears (most of) them */
399 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
406 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
407 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
410 for (irq = 0; irq < 16; irq++) {
411 virq = irq_find_mapping(chip->g1_irq.domain, irq);
412 irq_dispose_mapping(virq);
415 irq_domain_remove(chip->g1_irq.domain);
420 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
424 err = mv88e6xxx_g1_irq_setup_common(chip);
428 err = request_threaded_irq(chip->irq, NULL,
429 mv88e6xxx_g1_irq_thread_fn,
431 dev_name(chip->dev), chip);
433 mv88e6xxx_g1_irq_free_common(chip);
438 static void mv88e6xxx_irq_poll(struct kthread_work *work)
440 struct mv88e6xxx_chip *chip = container_of(work,
441 struct mv88e6xxx_chip,
443 mv88e6xxx_g1_irq_thread_work(chip);
445 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
446 msecs_to_jiffies(100));
449 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
453 err = mv88e6xxx_g1_irq_setup_common(chip);
457 kthread_init_delayed_work(&chip->irq_poll_work,
460 chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
461 if (IS_ERR(chip->kworker))
462 return PTR_ERR(chip->kworker);
464 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
465 msecs_to_jiffies(100));
470 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
472 mv88e6xxx_g1_irq_free_common(chip);
474 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
475 kthread_destroy_worker(chip->kworker);
478 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
482 for (i = 0; i < 16; i++) {
486 err = mv88e6xxx_read(chip, addr, reg, &val);
493 usleep_range(1000, 2000);
496 dev_err(chip->dev, "Timeout while waiting for switch\n");
500 /* Indirect write to single pointer-data register with an Update bit */
501 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
506 /* Wait until the previous operation is completed */
507 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
511 /* Set the Update bit to trigger a write operation */
512 val = BIT(15) | update;
514 return mv88e6xxx_write(chip, addr, reg, val);
517 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
518 int link, int speed, int duplex,
519 phy_interface_t mode)
523 if (!chip->info->ops->port_set_link)
526 /* Port's MAC control must not be changed unless the link is down */
527 err = chip->info->ops->port_set_link(chip, port, 0);
531 if (chip->info->ops->port_set_speed) {
532 err = chip->info->ops->port_set_speed(chip, port, speed);
533 if (err && err != -EOPNOTSUPP)
537 if (chip->info->ops->port_set_duplex) {
538 err = chip->info->ops->port_set_duplex(chip, port, duplex);
539 if (err && err != -EOPNOTSUPP)
543 if (chip->info->ops->port_set_rgmii_delay) {
544 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
545 if (err && err != -EOPNOTSUPP)
549 if (chip->info->ops->port_set_cmode) {
550 err = chip->info->ops->port_set_cmode(chip, port, mode);
551 if (err && err != -EOPNOTSUPP)
557 if (chip->info->ops->port_set_link(chip, port, link))
558 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
563 /* We expect the switch to perform auto negotiation if there is a real
564 * phy. However, in the case of a fixed link phy, we force the port
565 * settings from the fixed link settings.
567 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
568 struct phy_device *phydev)
570 struct mv88e6xxx_chip *chip = ds->priv;
573 if (!phy_is_pseudo_fixed_link(phydev))
576 mutex_lock(&chip->reg_lock);
577 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
578 phydev->duplex, phydev->interface);
579 mutex_unlock(&chip->reg_lock);
581 if (err && err != -EOPNOTSUPP)
582 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
585 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
586 unsigned long *supported,
587 struct phylink_link_state *state)
591 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
592 struct phylink_link_state *state)
594 struct mv88e6xxx_chip *chip = ds->priv;
597 mutex_lock(&chip->reg_lock);
598 err = mv88e6xxx_port_link_state(chip, port, state);
599 mutex_unlock(&chip->reg_lock);
604 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
606 const struct phylink_link_state *state)
608 struct mv88e6xxx_chip *chip = ds->priv;
609 int speed, duplex, link, err;
611 if (mode == MLO_AN_PHY)
614 if (mode == MLO_AN_FIXED) {
615 link = LINK_FORCED_UP;
616 speed = state->speed;
617 duplex = state->duplex;
619 speed = SPEED_UNFORCED;
620 duplex = DUPLEX_UNFORCED;
621 link = LINK_UNFORCED;
624 mutex_lock(&chip->reg_lock);
625 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex,
627 mutex_unlock(&chip->reg_lock);
629 if (err && err != -EOPNOTSUPP)
630 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
633 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
635 struct mv88e6xxx_chip *chip = ds->priv;
638 mutex_lock(&chip->reg_lock);
639 err = chip->info->ops->port_set_link(chip, port, link);
640 mutex_unlock(&chip->reg_lock);
643 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
646 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
648 phy_interface_t interface)
650 if (mode == MLO_AN_FIXED)
651 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
654 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
655 unsigned int mode, phy_interface_t interface,
656 struct phy_device *phydev)
658 if (mode == MLO_AN_FIXED)
659 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
662 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
664 if (!chip->info->ops->stats_snapshot)
667 return chip->info->ops->stats_snapshot(chip, port);
670 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
671 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
672 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
673 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
674 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
675 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
676 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
677 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
678 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
679 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
680 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
681 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
682 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
683 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
684 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
685 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
686 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
687 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
688 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
689 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
690 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
691 { "single", 4, 0x14, STATS_TYPE_BANK0, },
692 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
693 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
694 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
695 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
696 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
697 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
698 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
699 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
700 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
701 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
702 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
703 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
704 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
705 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
706 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
707 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
708 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
709 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
710 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
711 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
712 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
713 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
714 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
715 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
716 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
717 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
718 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
719 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
720 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
721 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
722 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
723 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
724 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
725 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
726 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
727 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
728 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
729 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
732 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
733 struct mv88e6xxx_hw_stat *s,
734 int port, u16 bank1_select,
744 case STATS_TYPE_PORT:
745 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
751 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
757 case STATS_TYPE_BANK1:
760 case STATS_TYPE_BANK0:
761 reg |= s->reg | histogram;
762 mv88e6xxx_g1_stats_read(chip, reg, &low);
764 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
769 value = (((u64)high) << 16) | low;
773 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
774 uint8_t *data, int types)
776 struct mv88e6xxx_hw_stat *stat;
779 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
780 stat = &mv88e6xxx_hw_stats[i];
781 if (stat->type & types) {
782 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
791 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
794 return mv88e6xxx_stats_get_strings(chip, data,
795 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
798 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
801 return mv88e6xxx_stats_get_strings(chip, data,
802 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
805 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
806 "atu_member_violation",
807 "atu_miss_violation",
808 "atu_full_violation",
809 "vtu_member_violation",
810 "vtu_miss_violation",
813 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
817 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
818 strlcpy(data + i * ETH_GSTRING_LEN,
819 mv88e6xxx_atu_vtu_stats_strings[i],
823 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
824 u32 stringset, uint8_t *data)
826 struct mv88e6xxx_chip *chip = ds->priv;
829 if (stringset != ETH_SS_STATS)
832 mutex_lock(&chip->reg_lock);
834 if (chip->info->ops->stats_get_strings)
835 count = chip->info->ops->stats_get_strings(chip, data);
837 if (chip->info->ops->serdes_get_strings) {
838 data += count * ETH_GSTRING_LEN;
839 count = chip->info->ops->serdes_get_strings(chip, port, data);
842 data += count * ETH_GSTRING_LEN;
843 mv88e6xxx_atu_vtu_get_strings(data);
845 mutex_unlock(&chip->reg_lock);
848 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
851 struct mv88e6xxx_hw_stat *stat;
854 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
855 stat = &mv88e6xxx_hw_stats[i];
856 if (stat->type & types)
862 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
864 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
868 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
870 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
874 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
876 struct mv88e6xxx_chip *chip = ds->priv;
877 int serdes_count = 0;
880 if (sset != ETH_SS_STATS)
883 mutex_lock(&chip->reg_lock);
884 if (chip->info->ops->stats_get_sset_count)
885 count = chip->info->ops->stats_get_sset_count(chip);
889 if (chip->info->ops->serdes_get_sset_count)
890 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
892 if (serdes_count < 0) {
893 count = serdes_count;
896 count += serdes_count;
897 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
900 mutex_unlock(&chip->reg_lock);
905 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
906 uint64_t *data, int types,
907 u16 bank1_select, u16 histogram)
909 struct mv88e6xxx_hw_stat *stat;
912 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
913 stat = &mv88e6xxx_hw_stats[i];
914 if (stat->type & types) {
915 mutex_lock(&chip->reg_lock);
916 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
919 mutex_unlock(&chip->reg_lock);
927 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
930 return mv88e6xxx_stats_get_stats(chip, port, data,
931 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
932 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
935 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
938 return mv88e6xxx_stats_get_stats(chip, port, data,
939 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
940 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
941 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
944 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
947 return mv88e6xxx_stats_get_stats(chip, port, data,
948 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
949 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
953 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
956 *data++ = chip->ports[port].atu_member_violation;
957 *data++ = chip->ports[port].atu_miss_violation;
958 *data++ = chip->ports[port].atu_full_violation;
959 *data++ = chip->ports[port].vtu_member_violation;
960 *data++ = chip->ports[port].vtu_miss_violation;
963 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
968 if (chip->info->ops->stats_get_stats)
969 count = chip->info->ops->stats_get_stats(chip, port, data);
971 mutex_lock(&chip->reg_lock);
972 if (chip->info->ops->serdes_get_stats) {
974 count = chip->info->ops->serdes_get_stats(chip, port, data);
977 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
978 mutex_unlock(&chip->reg_lock);
981 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
984 struct mv88e6xxx_chip *chip = ds->priv;
987 mutex_lock(&chip->reg_lock);
989 ret = mv88e6xxx_stats_snapshot(chip, port);
990 mutex_unlock(&chip->reg_lock);
995 mv88e6xxx_get_stats(chip, port, data);
999 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1001 return 32 * sizeof(u16);
1004 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1005 struct ethtool_regs *regs, void *_p)
1007 struct mv88e6xxx_chip *chip = ds->priv;
1015 memset(p, 0xff, 32 * sizeof(u16));
1017 mutex_lock(&chip->reg_lock);
1019 for (i = 0; i < 32; i++) {
1021 err = mv88e6xxx_port_read(chip, port, i, ®);
1026 mutex_unlock(&chip->reg_lock);
1029 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1030 struct ethtool_eee *e)
1032 /* Nothing to do on the port's MAC */
1036 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1037 struct ethtool_eee *e)
1039 /* Nothing to do on the port's MAC */
1043 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1045 struct dsa_switch *ds = NULL;
1046 struct net_device *br;
1050 if (dev < DSA_MAX_SWITCHES)
1051 ds = chip->ds->dst->ds[dev];
1053 /* Prevent frames from unknown switch or port */
1054 if (!ds || port >= ds->num_ports)
1057 /* Frames from DSA links and CPU ports can egress any local port */
1058 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1059 return mv88e6xxx_port_mask(chip);
1061 br = ds->ports[port].bridge_dev;
1064 /* Frames from user ports can egress any local DSA links and CPU ports,
1065 * as well as any local member of their bridge group.
1067 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1068 if (dsa_is_cpu_port(chip->ds, i) ||
1069 dsa_is_dsa_port(chip->ds, i) ||
1070 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1076 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1078 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1080 /* prevent frames from going back out of the port they came in on */
1081 output_ports &= ~BIT(port);
1083 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1086 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1089 struct mv88e6xxx_chip *chip = ds->priv;
1092 mutex_lock(&chip->reg_lock);
1093 err = mv88e6xxx_port_set_state(chip, port, state);
1094 mutex_unlock(&chip->reg_lock);
1097 dev_err(ds->dev, "p%d: failed to update state\n", port);
1100 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1104 if (chip->info->ops->ieee_pri_map) {
1105 err = chip->info->ops->ieee_pri_map(chip);
1110 if (chip->info->ops->ip_pri_map) {
1111 err = chip->info->ops->ip_pri_map(chip);
1119 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1124 if (!chip->info->global2_addr)
1127 /* Initialize the routing port to the 32 possible target devices */
1128 for (target = 0; target < 32; target++) {
1130 if (target < DSA_MAX_SWITCHES)
1131 if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1132 port = chip->ds->rtable[target];
1134 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1139 if (chip->info->ops->set_cascade_port) {
1140 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1141 err = chip->info->ops->set_cascade_port(chip, port);
1146 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1153 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1155 /* Clear all trunk masks and mapping */
1156 if (chip->info->global2_addr)
1157 return mv88e6xxx_g2_trunk_clear(chip);
1162 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1164 if (chip->info->ops->rmu_disable)
1165 return chip->info->ops->rmu_disable(chip);
1170 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1172 if (chip->info->ops->pot_clear)
1173 return chip->info->ops->pot_clear(chip);
1178 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1180 if (chip->info->ops->mgmt_rsvd2cpu)
1181 return chip->info->ops->mgmt_rsvd2cpu(chip);
1186 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1190 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1194 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1198 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1201 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1206 if (!chip->info->ops->irl_init_all)
1209 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1210 /* Disable ingress rate limiting by resetting all per port
1211 * ingress rate limit resources to their initial state.
1213 err = chip->info->ops->irl_init_all(chip, port);
1221 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1223 if (chip->info->ops->set_switch_mac) {
1226 eth_random_addr(addr);
1228 return chip->info->ops->set_switch_mac(chip, addr);
1234 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1238 if (!mv88e6xxx_has_pvt(chip))
1241 /* Skip the local source device, which uses in-chip port VLAN */
1242 if (dev != chip->ds->index)
1243 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1245 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1248 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1253 if (!mv88e6xxx_has_pvt(chip))
1256 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1257 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1259 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1263 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1264 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1265 err = mv88e6xxx_pvt_map(chip, dev, port);
1274 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1276 struct mv88e6xxx_chip *chip = ds->priv;
1279 mutex_lock(&chip->reg_lock);
1280 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1281 mutex_unlock(&chip->reg_lock);
1284 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1287 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1289 if (!chip->info->max_vid)
1292 return mv88e6xxx_g1_vtu_flush(chip);
1295 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1296 struct mv88e6xxx_vtu_entry *entry)
1298 if (!chip->info->ops->vtu_getnext)
1301 return chip->info->ops->vtu_getnext(chip, entry);
1304 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1305 struct mv88e6xxx_vtu_entry *entry)
1307 if (!chip->info->ops->vtu_loadpurge)
1310 return chip->info->ops->vtu_loadpurge(chip, entry);
1313 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1315 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1316 struct mv88e6xxx_vtu_entry vlan = {
1317 .vid = chip->info->max_vid,
1321 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1323 /* Set every FID bit used by the (un)bridged ports */
1324 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1325 err = mv88e6xxx_port_get_fid(chip, i, fid);
1329 set_bit(*fid, fid_bitmap);
1332 /* Set every FID bit used by the VLAN entries */
1334 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1341 set_bit(vlan.fid, fid_bitmap);
1342 } while (vlan.vid < chip->info->max_vid);
1344 /* The reset value 0x000 is used to indicate that multiple address
1345 * databases are not needed. Return the next positive available.
1347 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1348 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1351 /* Clear the database */
1352 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1355 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1356 struct mv88e6xxx_vtu_entry *entry, bool new)
1363 entry->vid = vid - 1;
1364 entry->valid = false;
1366 err = mv88e6xxx_vtu_getnext(chip, entry);
1370 if (entry->vid == vid && entry->valid)
1376 /* Initialize a fresh VLAN entry */
1377 memset(entry, 0, sizeof(*entry));
1378 entry->valid = true;
1381 /* Exclude all ports */
1382 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1384 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1386 return mv88e6xxx_atu_new(chip, &entry->fid);
1389 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1393 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1394 u16 vid_begin, u16 vid_end)
1396 struct mv88e6xxx_chip *chip = ds->priv;
1397 struct mv88e6xxx_vtu_entry vlan = {
1398 .vid = vid_begin - 1,
1402 /* DSA and CPU ports have to be members of multiple vlans */
1403 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1409 mutex_lock(&chip->reg_lock);
1412 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1419 if (vlan.vid > vid_end)
1422 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1423 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1426 if (!ds->ports[i].slave)
1429 if (vlan.member[i] ==
1430 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1433 if (dsa_to_port(ds, i)->bridge_dev ==
1434 ds->ports[port].bridge_dev)
1435 break; /* same bridge, check next VLAN */
1437 if (!dsa_to_port(ds, i)->bridge_dev)
1440 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1442 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1446 } while (vlan.vid < vid_end);
1449 mutex_unlock(&chip->reg_lock);
1454 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1455 bool vlan_filtering)
1457 struct mv88e6xxx_chip *chip = ds->priv;
1458 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1459 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1462 if (!chip->info->max_vid)
1465 mutex_lock(&chip->reg_lock);
1466 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1467 mutex_unlock(&chip->reg_lock);
1473 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1474 const struct switchdev_obj_port_vlan *vlan)
1476 struct mv88e6xxx_chip *chip = ds->priv;
1479 if (!chip->info->max_vid)
1482 /* If the requested port doesn't belong to the same bridge as the VLAN
1483 * members, do not support it (yet) and fallback to software VLAN.
1485 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1490 /* We don't need any dynamic resource from the kernel (yet),
1491 * so skip the prepare phase.
1496 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1497 const unsigned char *addr, u16 vid,
1500 struct mv88e6xxx_vtu_entry vlan;
1501 struct mv88e6xxx_atu_entry entry;
1504 /* Null VLAN ID corresponds to the port private database */
1506 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1508 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1512 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1513 ether_addr_copy(entry.mac, addr);
1514 eth_addr_dec(entry.mac);
1516 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1520 /* Initialize a fresh ATU entry if it isn't found */
1521 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1522 !ether_addr_equal(entry.mac, addr)) {
1523 memset(&entry, 0, sizeof(entry));
1524 ether_addr_copy(entry.mac, addr);
1527 /* Purge the ATU entry only if no port is using it anymore */
1528 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1529 entry.portvec &= ~BIT(port);
1531 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1533 entry.portvec |= BIT(port);
1534 entry.state = state;
1537 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1540 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1543 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1544 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1546 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1549 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1554 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1555 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1563 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1566 struct mv88e6xxx_vtu_entry vlan;
1569 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1573 vlan.member[port] = member;
1575 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1579 return mv88e6xxx_broadcast_setup(chip, vid);
1582 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1583 const struct switchdev_obj_port_vlan *vlan)
1585 struct mv88e6xxx_chip *chip = ds->priv;
1586 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1587 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1591 if (!chip->info->max_vid)
1594 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1595 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1597 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1599 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1601 mutex_lock(&chip->reg_lock);
1603 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1604 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1605 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1606 vid, untagged ? 'u' : 't');
1608 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1609 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1612 mutex_unlock(&chip->reg_lock);
1615 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1618 struct mv88e6xxx_vtu_entry vlan;
1621 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1625 /* Tell switchdev if this VLAN is handled in software */
1626 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1629 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1631 /* keep the VLAN unless all ports are excluded */
1633 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1634 if (vlan.member[i] !=
1635 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1641 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1645 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1648 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1649 const struct switchdev_obj_port_vlan *vlan)
1651 struct mv88e6xxx_chip *chip = ds->priv;
1655 if (!chip->info->max_vid)
1658 mutex_lock(&chip->reg_lock);
1660 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1664 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1665 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1670 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1677 mutex_unlock(&chip->reg_lock);
1682 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1683 const unsigned char *addr, u16 vid)
1685 struct mv88e6xxx_chip *chip = ds->priv;
1688 mutex_lock(&chip->reg_lock);
1689 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1690 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1691 mutex_unlock(&chip->reg_lock);
1696 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1697 const unsigned char *addr, u16 vid)
1699 struct mv88e6xxx_chip *chip = ds->priv;
1702 mutex_lock(&chip->reg_lock);
1703 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1704 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1705 mutex_unlock(&chip->reg_lock);
1710 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1711 u16 fid, u16 vid, int port,
1712 dsa_fdb_dump_cb_t *cb, void *data)
1714 struct mv88e6xxx_atu_entry addr;
1718 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1719 eth_broadcast_addr(addr.mac);
1722 mutex_lock(&chip->reg_lock);
1723 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1724 mutex_unlock(&chip->reg_lock);
1728 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1731 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1734 if (!is_unicast_ether_addr(addr.mac))
1737 is_static = (addr.state ==
1738 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1739 err = cb(addr.mac, vid, is_static, data);
1742 } while (!is_broadcast_ether_addr(addr.mac));
1747 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1748 dsa_fdb_dump_cb_t *cb, void *data)
1750 struct mv88e6xxx_vtu_entry vlan = {
1751 .vid = chip->info->max_vid,
1756 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1757 mutex_lock(&chip->reg_lock);
1758 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1759 mutex_unlock(&chip->reg_lock);
1764 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1768 /* Dump VLANs' Filtering Information Databases */
1770 mutex_lock(&chip->reg_lock);
1771 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1772 mutex_unlock(&chip->reg_lock);
1779 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1783 } while (vlan.vid < chip->info->max_vid);
1788 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1789 dsa_fdb_dump_cb_t *cb, void *data)
1791 struct mv88e6xxx_chip *chip = ds->priv;
1793 return mv88e6xxx_port_db_dump(chip, port, cb, data);
1796 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1797 struct net_device *br)
1799 struct dsa_switch *ds;
1804 /* Remap the Port VLAN of each local bridge group member */
1805 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1806 if (chip->ds->ports[port].bridge_dev == br) {
1807 err = mv88e6xxx_port_vlan_map(chip, port);
1813 if (!mv88e6xxx_has_pvt(chip))
1816 /* Remap the Port VLAN of each cross-chip bridge group member */
1817 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1818 ds = chip->ds->dst->ds[dev];
1822 for (port = 0; port < ds->num_ports; ++port) {
1823 if (ds->ports[port].bridge_dev == br) {
1824 err = mv88e6xxx_pvt_map(chip, dev, port);
1834 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1835 struct net_device *br)
1837 struct mv88e6xxx_chip *chip = ds->priv;
1840 mutex_lock(&chip->reg_lock);
1841 err = mv88e6xxx_bridge_map(chip, br);
1842 mutex_unlock(&chip->reg_lock);
1847 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1848 struct net_device *br)
1850 struct mv88e6xxx_chip *chip = ds->priv;
1852 mutex_lock(&chip->reg_lock);
1853 if (mv88e6xxx_bridge_map(chip, br) ||
1854 mv88e6xxx_port_vlan_map(chip, port))
1855 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1856 mutex_unlock(&chip->reg_lock);
1859 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1860 int port, struct net_device *br)
1862 struct mv88e6xxx_chip *chip = ds->priv;
1865 if (!mv88e6xxx_has_pvt(chip))
1868 mutex_lock(&chip->reg_lock);
1869 err = mv88e6xxx_pvt_map(chip, dev, port);
1870 mutex_unlock(&chip->reg_lock);
1875 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1876 int port, struct net_device *br)
1878 struct mv88e6xxx_chip *chip = ds->priv;
1880 if (!mv88e6xxx_has_pvt(chip))
1883 mutex_lock(&chip->reg_lock);
1884 if (mv88e6xxx_pvt_map(chip, dev, port))
1885 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1886 mutex_unlock(&chip->reg_lock);
1889 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1891 if (chip->info->ops->reset)
1892 return chip->info->ops->reset(chip);
1897 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1899 struct gpio_desc *gpiod = chip->reset;
1901 /* If there is a GPIO connected to the reset pin, toggle it */
1903 gpiod_set_value_cansleep(gpiod, 1);
1904 usleep_range(10000, 20000);
1905 gpiod_set_value_cansleep(gpiod, 0);
1906 usleep_range(10000, 20000);
1910 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1914 /* Set all ports to the Disabled state */
1915 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1916 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1921 /* Wait for transmit queues to drain,
1922 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1924 usleep_range(2000, 4000);
1929 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1933 err = mv88e6xxx_disable_ports(chip);
1937 mv88e6xxx_hardware_reset(chip);
1939 return mv88e6xxx_software_reset(chip);
1942 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1943 enum mv88e6xxx_frame_mode frame,
1944 enum mv88e6xxx_egress_mode egress, u16 etype)
1948 if (!chip->info->ops->port_set_frame_mode)
1951 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1955 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1959 if (chip->info->ops->port_set_ether_type)
1960 return chip->info->ops->port_set_ether_type(chip, port, etype);
1965 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1967 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1968 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1969 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1972 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1974 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1975 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1976 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1979 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1981 return mv88e6xxx_set_port_mode(chip, port,
1982 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1983 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1987 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1989 if (dsa_is_dsa_port(chip->ds, port))
1990 return mv88e6xxx_set_port_mode_dsa(chip, port);
1992 if (dsa_is_user_port(chip->ds, port))
1993 return mv88e6xxx_set_port_mode_normal(chip, port);
1995 /* Setup CPU port mode depending on its supported tag format */
1996 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1997 return mv88e6xxx_set_port_mode_dsa(chip, port);
1999 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2000 return mv88e6xxx_set_port_mode_edsa(chip, port);
2005 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2007 bool message = dsa_is_dsa_port(chip->ds, port);
2009 return mv88e6xxx_port_set_message_port(chip, port, message);
2012 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2014 struct dsa_switch *ds = chip->ds;
2017 /* Upstream ports flood frames with unknown unicast or multicast DA */
2018 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2019 if (chip->info->ops->port_set_egress_floods)
2020 return chip->info->ops->port_set_egress_floods(chip, port,
2026 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2029 if (chip->info->ops->serdes_power)
2030 return chip->info->ops->serdes_power(chip, port, on);
2035 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2037 struct dsa_switch *ds = chip->ds;
2041 upstream_port = dsa_upstream_port(ds, port);
2042 if (chip->info->ops->port_set_upstream_port) {
2043 err = chip->info->ops->port_set_upstream_port(chip, port,
2049 if (port == upstream_port) {
2050 if (chip->info->ops->set_cpu_port) {
2051 err = chip->info->ops->set_cpu_port(chip,
2057 if (chip->info->ops->set_egress_port) {
2058 err = chip->info->ops->set_egress_port(chip,
2068 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2070 struct dsa_switch *ds = chip->ds;
2074 /* MAC Forcing register: don't force link, speed, duplex or flow control
2075 * state to any particular values on physical ports, but force the CPU
2076 * port and all DSA ports to their maximum bandwidth and full duplex.
2078 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2079 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2080 SPEED_MAX, DUPLEX_FULL,
2081 PHY_INTERFACE_MODE_NA);
2083 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2084 SPEED_UNFORCED, DUPLEX_UNFORCED,
2085 PHY_INTERFACE_MODE_NA);
2089 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2090 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2091 * tunneling, determine priority by looking at 802.1p and IP
2092 * priority fields (IP prio has precedence), and set STP state
2095 * If this is the CPU link, use DSA or EDSA tagging depending
2096 * on which tagging mode was configured.
2098 * If this is a link to another switch, use DSA tagging mode.
2100 * If this is the upstream port for this switch, enable
2101 * forwarding of unknown unicasts and multicasts.
2103 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2104 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2105 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2106 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2110 err = mv88e6xxx_setup_port_mode(chip, port);
2114 err = mv88e6xxx_setup_egress_floods(chip, port);
2118 /* Enable the SERDES interface for DSA and CPU ports. Normal
2119 * ports SERDES are enabled when the port is enabled, thus
2120 * saving a bit of power.
2122 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
2123 err = mv88e6xxx_serdes_power(chip, port, true);
2128 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2129 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2130 * untagged frames on this port, do a destination address lookup on all
2131 * received packets as usual, disable ARP mirroring and don't send a
2132 * copy of all transmitted/received frames on this port to the CPU.
2134 err = mv88e6xxx_port_set_map_da(chip, port);
2138 err = mv88e6xxx_setup_upstream_port(chip, port);
2142 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2143 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2147 if (chip->info->ops->port_set_jumbo_size) {
2148 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2153 /* Port Association Vector: when learning source addresses
2154 * of packets, add the address to the address database using
2155 * a port bitmap that has only the bit for this port set and
2156 * the other bits clear.
2159 /* Disable learning for CPU port */
2160 if (dsa_is_cpu_port(ds, port))
2163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2168 /* Egress rate control 2: disable egress rate control. */
2169 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2174 if (chip->info->ops->port_pause_limit) {
2175 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2180 if (chip->info->ops->port_disable_learn_limit) {
2181 err = chip->info->ops->port_disable_learn_limit(chip, port);
2186 if (chip->info->ops->port_disable_pri_override) {
2187 err = chip->info->ops->port_disable_pri_override(chip, port);
2192 if (chip->info->ops->port_tag_remap) {
2193 err = chip->info->ops->port_tag_remap(chip, port);
2198 if (chip->info->ops->port_egress_rate_limiting) {
2199 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2204 err = mv88e6xxx_setup_message_port(chip, port);
2208 /* Port based VLAN map: give each port the same default address
2209 * database, and allow bidirectional communication between the
2210 * CPU and DSA port(s), and the other ports.
2212 err = mv88e6xxx_port_set_fid(chip, port, 0);
2216 err = mv88e6xxx_port_vlan_map(chip, port);
2220 /* Default VLAN ID and priority: don't set a default VLAN
2221 * ID, and set the default packet priority to zero.
2223 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2226 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2227 struct phy_device *phydev)
2229 struct mv88e6xxx_chip *chip = ds->priv;
2232 mutex_lock(&chip->reg_lock);
2233 err = mv88e6xxx_serdes_power(chip, port, true);
2234 mutex_unlock(&chip->reg_lock);
2239 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2240 struct phy_device *phydev)
2242 struct mv88e6xxx_chip *chip = ds->priv;
2244 mutex_lock(&chip->reg_lock);
2245 if (mv88e6xxx_serdes_power(chip, port, false))
2246 dev_err(chip->dev, "failed to power off SERDES\n");
2247 mutex_unlock(&chip->reg_lock);
2250 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2251 unsigned int ageing_time)
2253 struct mv88e6xxx_chip *chip = ds->priv;
2256 mutex_lock(&chip->reg_lock);
2257 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2258 mutex_unlock(&chip->reg_lock);
2263 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2267 /* Initialize the statistics unit */
2268 if (chip->info->ops->stats_set_histogram) {
2269 err = chip->info->ops->stats_set_histogram(chip);
2274 return mv88e6xxx_g1_stats_clear(chip);
2277 static int mv88e6xxx_setup(struct dsa_switch *ds)
2279 struct mv88e6xxx_chip *chip = ds->priv;
2284 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2286 mutex_lock(&chip->reg_lock);
2288 /* Setup Switch Port Registers */
2289 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2290 if (dsa_is_unused_port(ds, i))
2293 err = mv88e6xxx_setup_port(chip, i);
2298 err = mv88e6xxx_irl_setup(chip);
2302 err = mv88e6xxx_mac_setup(chip);
2306 err = mv88e6xxx_phy_setup(chip);
2310 err = mv88e6xxx_vtu_setup(chip);
2314 err = mv88e6xxx_pvt_setup(chip);
2318 err = mv88e6xxx_atu_setup(chip);
2322 err = mv88e6xxx_broadcast_setup(chip, 0);
2326 err = mv88e6xxx_pot_setup(chip);
2330 err = mv88e6xxx_rmu_setup(chip);
2334 err = mv88e6xxx_rsvd2cpu_setup(chip);
2338 err = mv88e6xxx_trunk_setup(chip);
2342 err = mv88e6xxx_devmap_setup(chip);
2346 err = mv88e6xxx_pri_setup(chip);
2350 /* Setup PTP Hardware Clock and timestamping */
2351 if (chip->info->ptp_support) {
2352 err = mv88e6xxx_ptp_setup(chip);
2356 err = mv88e6xxx_hwtstamp_setup(chip);
2361 err = mv88e6xxx_stats_setup(chip);
2366 mutex_unlock(&chip->reg_lock);
2371 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2373 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2374 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2378 if (!chip->info->ops->phy_read)
2381 mutex_lock(&chip->reg_lock);
2382 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2383 mutex_unlock(&chip->reg_lock);
2385 if (reg == MII_PHYSID2) {
2386 /* Some internal PHYS don't have a model number. Use
2387 * the mv88e6390 family model number instead.
2390 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2393 return err ? err : val;
2396 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2398 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2399 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2402 if (!chip->info->ops->phy_write)
2405 mutex_lock(&chip->reg_lock);
2406 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2407 mutex_unlock(&chip->reg_lock);
2412 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2413 struct device_node *np,
2417 struct mv88e6xxx_mdio_bus *mdio_bus;
2418 struct mii_bus *bus;
2422 mutex_lock(&chip->reg_lock);
2423 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2424 mutex_unlock(&chip->reg_lock);
2430 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2434 mdio_bus = bus->priv;
2435 mdio_bus->bus = bus;
2436 mdio_bus->chip = chip;
2437 INIT_LIST_HEAD(&mdio_bus->list);
2438 mdio_bus->external = external;
2441 bus->name = np->full_name;
2442 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2444 bus->name = "mv88e6xxx SMI";
2445 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2448 bus->read = mv88e6xxx_mdio_read;
2449 bus->write = mv88e6xxx_mdio_write;
2450 bus->parent = chip->dev;
2453 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2458 err = of_mdiobus_register(bus, np);
2460 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2461 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2466 list_add_tail(&mdio_bus->list, &chip->mdios);
2468 list_add(&mdio_bus->list, &chip->mdios);
2473 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2474 { .compatible = "marvell,mv88e6xxx-mdio-external",
2475 .data = (void *)true },
2479 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2482 struct mv88e6xxx_mdio_bus *mdio_bus;
2483 struct mii_bus *bus;
2485 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2486 bus = mdio_bus->bus;
2488 if (!mdio_bus->external)
2489 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2491 mdiobus_unregister(bus);
2495 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2496 struct device_node *np)
2498 const struct of_device_id *match;
2499 struct device_node *child;
2502 /* Always register one mdio bus for the internal/default mdio
2503 * bus. This maybe represented in the device tree, but is
2506 child = of_get_child_by_name(np, "mdio");
2507 err = mv88e6xxx_mdio_register(chip, child, false);
2511 /* Walk the device tree, and see if there are any other nodes
2512 * which say they are compatible with the external mdio
2515 for_each_available_child_of_node(np, child) {
2516 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2518 err = mv88e6xxx_mdio_register(chip, child, true);
2520 mv88e6xxx_mdios_unregister(chip);
2529 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2531 struct mv88e6xxx_chip *chip = ds->priv;
2533 return chip->eeprom_len;
2536 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2537 struct ethtool_eeprom *eeprom, u8 *data)
2539 struct mv88e6xxx_chip *chip = ds->priv;
2542 if (!chip->info->ops->get_eeprom)
2545 mutex_lock(&chip->reg_lock);
2546 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2547 mutex_unlock(&chip->reg_lock);
2552 eeprom->magic = 0xc3ec4951;
2557 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2558 struct ethtool_eeprom *eeprom, u8 *data)
2560 struct mv88e6xxx_chip *chip = ds->priv;
2563 if (!chip->info->ops->set_eeprom)
2566 if (eeprom->magic != 0xc3ec4951)
2569 mutex_lock(&chip->reg_lock);
2570 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2571 mutex_unlock(&chip->reg_lock);
2576 static const struct mv88e6xxx_ops mv88e6085_ops = {
2577 /* MV88E6XXX_FAMILY_6097 */
2578 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2579 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2580 .irl_init_all = mv88e6352_g2_irl_init_all,
2581 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2582 .phy_read = mv88e6185_phy_ppu_read,
2583 .phy_write = mv88e6185_phy_ppu_write,
2584 .port_set_link = mv88e6xxx_port_set_link,
2585 .port_set_duplex = mv88e6xxx_port_set_duplex,
2586 .port_set_speed = mv88e6185_port_set_speed,
2587 .port_tag_remap = mv88e6095_port_tag_remap,
2588 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2589 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2590 .port_set_ether_type = mv88e6351_port_set_ether_type,
2591 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2592 .port_pause_limit = mv88e6097_port_pause_limit,
2593 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2594 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2595 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2597 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2598 .stats_get_strings = mv88e6095_stats_get_strings,
2599 .stats_get_stats = mv88e6095_stats_get_stats,
2600 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2601 .set_egress_port = mv88e6095_g1_set_egress_port,
2602 .watchdog_ops = &mv88e6097_watchdog_ops,
2603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2604 .pot_clear = mv88e6xxx_g2_pot_clear,
2605 .ppu_enable = mv88e6185_g1_ppu_enable,
2606 .ppu_disable = mv88e6185_g1_ppu_disable,
2607 .reset = mv88e6185_g1_reset,
2608 .rmu_disable = mv88e6085_g1_rmu_disable,
2609 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2610 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2611 .serdes_power = mv88e6341_serdes_power,
2614 static const struct mv88e6xxx_ops mv88e6095_ops = {
2615 /* MV88E6XXX_FAMILY_6095 */
2616 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2617 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2618 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2619 .phy_read = mv88e6185_phy_ppu_read,
2620 .phy_write = mv88e6185_phy_ppu_write,
2621 .port_set_link = mv88e6xxx_port_set_link,
2622 .port_set_duplex = mv88e6xxx_port_set_duplex,
2623 .port_set_speed = mv88e6185_port_set_speed,
2624 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2625 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2626 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2627 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2628 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2629 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2630 .stats_get_strings = mv88e6095_stats_get_strings,
2631 .stats_get_stats = mv88e6095_stats_get_stats,
2632 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2633 .ppu_enable = mv88e6185_g1_ppu_enable,
2634 .ppu_disable = mv88e6185_g1_ppu_disable,
2635 .reset = mv88e6185_g1_reset,
2636 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2637 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2640 static const struct mv88e6xxx_ops mv88e6097_ops = {
2641 /* MV88E6XXX_FAMILY_6097 */
2642 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2643 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2644 .irl_init_all = mv88e6352_g2_irl_init_all,
2645 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2646 .phy_read = mv88e6xxx_g2_smi_phy_read,
2647 .phy_write = mv88e6xxx_g2_smi_phy_write,
2648 .port_set_link = mv88e6xxx_port_set_link,
2649 .port_set_duplex = mv88e6xxx_port_set_duplex,
2650 .port_set_speed = mv88e6185_port_set_speed,
2651 .port_tag_remap = mv88e6095_port_tag_remap,
2652 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2653 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2654 .port_set_ether_type = mv88e6351_port_set_ether_type,
2655 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2656 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2657 .port_pause_limit = mv88e6097_port_pause_limit,
2658 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2659 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2660 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2661 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2662 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2663 .stats_get_strings = mv88e6095_stats_get_strings,
2664 .stats_get_stats = mv88e6095_stats_get_stats,
2665 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2666 .set_egress_port = mv88e6095_g1_set_egress_port,
2667 .watchdog_ops = &mv88e6097_watchdog_ops,
2668 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2669 .pot_clear = mv88e6xxx_g2_pot_clear,
2670 .reset = mv88e6352_g1_reset,
2671 .rmu_disable = mv88e6085_g1_rmu_disable,
2672 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2673 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2676 static const struct mv88e6xxx_ops mv88e6123_ops = {
2677 /* MV88E6XXX_FAMILY_6165 */
2678 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2679 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2680 .irl_init_all = mv88e6352_g2_irl_init_all,
2681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2682 .phy_read = mv88e6xxx_g2_smi_phy_read,
2683 .phy_write = mv88e6xxx_g2_smi_phy_write,
2684 .port_set_link = mv88e6xxx_port_set_link,
2685 .port_set_duplex = mv88e6xxx_port_set_duplex,
2686 .port_set_speed = mv88e6185_port_set_speed,
2687 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2688 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2689 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2690 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2691 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2692 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2693 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2694 .stats_get_strings = mv88e6095_stats_get_strings,
2695 .stats_get_stats = mv88e6095_stats_get_stats,
2696 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2697 .set_egress_port = mv88e6095_g1_set_egress_port,
2698 .watchdog_ops = &mv88e6097_watchdog_ops,
2699 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2700 .pot_clear = mv88e6xxx_g2_pot_clear,
2701 .reset = mv88e6352_g1_reset,
2702 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2703 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2706 static const struct mv88e6xxx_ops mv88e6131_ops = {
2707 /* MV88E6XXX_FAMILY_6185 */
2708 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2709 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2710 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2711 .phy_read = mv88e6185_phy_ppu_read,
2712 .phy_write = mv88e6185_phy_ppu_write,
2713 .port_set_link = mv88e6xxx_port_set_link,
2714 .port_set_duplex = mv88e6xxx_port_set_duplex,
2715 .port_set_speed = mv88e6185_port_set_speed,
2716 .port_tag_remap = mv88e6095_port_tag_remap,
2717 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2718 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2719 .port_set_ether_type = mv88e6351_port_set_ether_type,
2720 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2721 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2722 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2723 .port_pause_limit = mv88e6097_port_pause_limit,
2724 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2725 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2726 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2727 .stats_get_strings = mv88e6095_stats_get_strings,
2728 .stats_get_stats = mv88e6095_stats_get_stats,
2729 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2730 .set_egress_port = mv88e6095_g1_set_egress_port,
2731 .watchdog_ops = &mv88e6097_watchdog_ops,
2732 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2733 .ppu_enable = mv88e6185_g1_ppu_enable,
2734 .set_cascade_port = mv88e6185_g1_set_cascade_port,
2735 .ppu_disable = mv88e6185_g1_ppu_disable,
2736 .reset = mv88e6185_g1_reset,
2737 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2738 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2741 static const struct mv88e6xxx_ops mv88e6141_ops = {
2742 /* MV88E6XXX_FAMILY_6341 */
2743 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2744 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2745 .irl_init_all = mv88e6352_g2_irl_init_all,
2746 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2747 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2748 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2749 .phy_read = mv88e6xxx_g2_smi_phy_read,
2750 .phy_write = mv88e6xxx_g2_smi_phy_write,
2751 .port_set_link = mv88e6xxx_port_set_link,
2752 .port_set_duplex = mv88e6xxx_port_set_duplex,
2753 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2754 .port_set_speed = mv88e6390_port_set_speed,
2755 .port_tag_remap = mv88e6095_port_tag_remap,
2756 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2757 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2758 .port_set_ether_type = mv88e6351_port_set_ether_type,
2759 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2760 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2761 .port_pause_limit = mv88e6097_port_pause_limit,
2762 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2763 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2764 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2765 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2766 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2767 .stats_get_strings = mv88e6320_stats_get_strings,
2768 .stats_get_stats = mv88e6390_stats_get_stats,
2769 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2770 .set_egress_port = mv88e6390_g1_set_egress_port,
2771 .watchdog_ops = &mv88e6390_watchdog_ops,
2772 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2773 .pot_clear = mv88e6xxx_g2_pot_clear,
2774 .reset = mv88e6352_g1_reset,
2775 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2776 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2777 .gpio_ops = &mv88e6352_gpio_ops,
2780 static const struct mv88e6xxx_ops mv88e6161_ops = {
2781 /* MV88E6XXX_FAMILY_6165 */
2782 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2783 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2784 .irl_init_all = mv88e6352_g2_irl_init_all,
2785 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2786 .phy_read = mv88e6xxx_g2_smi_phy_read,
2787 .phy_write = mv88e6xxx_g2_smi_phy_write,
2788 .port_set_link = mv88e6xxx_port_set_link,
2789 .port_set_duplex = mv88e6xxx_port_set_duplex,
2790 .port_set_speed = mv88e6185_port_set_speed,
2791 .port_tag_remap = mv88e6095_port_tag_remap,
2792 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2793 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2794 .port_set_ether_type = mv88e6351_port_set_ether_type,
2795 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2796 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2797 .port_pause_limit = mv88e6097_port_pause_limit,
2798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2800 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2801 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2802 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2803 .stats_get_strings = mv88e6095_stats_get_strings,
2804 .stats_get_stats = mv88e6095_stats_get_stats,
2805 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2806 .set_egress_port = mv88e6095_g1_set_egress_port,
2807 .watchdog_ops = &mv88e6097_watchdog_ops,
2808 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2809 .pot_clear = mv88e6xxx_g2_pot_clear,
2810 .reset = mv88e6352_g1_reset,
2811 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2812 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2815 static const struct mv88e6xxx_ops mv88e6165_ops = {
2816 /* MV88E6XXX_FAMILY_6165 */
2817 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2818 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2819 .irl_init_all = mv88e6352_g2_irl_init_all,
2820 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2821 .phy_read = mv88e6165_phy_read,
2822 .phy_write = mv88e6165_phy_write,
2823 .port_set_link = mv88e6xxx_port_set_link,
2824 .port_set_duplex = mv88e6xxx_port_set_duplex,
2825 .port_set_speed = mv88e6185_port_set_speed,
2826 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2827 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2828 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2829 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2830 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2831 .stats_get_strings = mv88e6095_stats_get_strings,
2832 .stats_get_stats = mv88e6095_stats_get_stats,
2833 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2834 .set_egress_port = mv88e6095_g1_set_egress_port,
2835 .watchdog_ops = &mv88e6097_watchdog_ops,
2836 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2837 .pot_clear = mv88e6xxx_g2_pot_clear,
2838 .reset = mv88e6352_g1_reset,
2839 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2840 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2843 static const struct mv88e6xxx_ops mv88e6171_ops = {
2844 /* MV88E6XXX_FAMILY_6351 */
2845 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2846 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2847 .irl_init_all = mv88e6352_g2_irl_init_all,
2848 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2849 .phy_read = mv88e6xxx_g2_smi_phy_read,
2850 .phy_write = mv88e6xxx_g2_smi_phy_write,
2851 .port_set_link = mv88e6xxx_port_set_link,
2852 .port_set_duplex = mv88e6xxx_port_set_duplex,
2853 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2854 .port_set_speed = mv88e6185_port_set_speed,
2855 .port_tag_remap = mv88e6095_port_tag_remap,
2856 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2857 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2858 .port_set_ether_type = mv88e6351_port_set_ether_type,
2859 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2860 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2861 .port_pause_limit = mv88e6097_port_pause_limit,
2862 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2863 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2864 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2865 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2866 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2867 .stats_get_strings = mv88e6095_stats_get_strings,
2868 .stats_get_stats = mv88e6095_stats_get_stats,
2869 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2870 .set_egress_port = mv88e6095_g1_set_egress_port,
2871 .watchdog_ops = &mv88e6097_watchdog_ops,
2872 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2873 .pot_clear = mv88e6xxx_g2_pot_clear,
2874 .reset = mv88e6352_g1_reset,
2875 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2876 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2879 static const struct mv88e6xxx_ops mv88e6172_ops = {
2880 /* MV88E6XXX_FAMILY_6352 */
2881 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2882 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2883 .irl_init_all = mv88e6352_g2_irl_init_all,
2884 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2885 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2886 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2887 .phy_read = mv88e6xxx_g2_smi_phy_read,
2888 .phy_write = mv88e6xxx_g2_smi_phy_write,
2889 .port_set_link = mv88e6xxx_port_set_link,
2890 .port_set_duplex = mv88e6xxx_port_set_duplex,
2891 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2892 .port_set_speed = mv88e6352_port_set_speed,
2893 .port_tag_remap = mv88e6095_port_tag_remap,
2894 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2895 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2896 .port_set_ether_type = mv88e6351_port_set_ether_type,
2897 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2898 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2899 .port_pause_limit = mv88e6097_port_pause_limit,
2900 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2901 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2902 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2903 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2904 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2905 .stats_get_strings = mv88e6095_stats_get_strings,
2906 .stats_get_stats = mv88e6095_stats_get_stats,
2907 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2908 .set_egress_port = mv88e6095_g1_set_egress_port,
2909 .watchdog_ops = &mv88e6097_watchdog_ops,
2910 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2911 .pot_clear = mv88e6xxx_g2_pot_clear,
2912 .reset = mv88e6352_g1_reset,
2913 .rmu_disable = mv88e6352_g1_rmu_disable,
2914 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2915 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2916 .serdes_power = mv88e6352_serdes_power,
2917 .gpio_ops = &mv88e6352_gpio_ops,
2920 static const struct mv88e6xxx_ops mv88e6175_ops = {
2921 /* MV88E6XXX_FAMILY_6351 */
2922 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2923 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2924 .irl_init_all = mv88e6352_g2_irl_init_all,
2925 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2926 .phy_read = mv88e6xxx_g2_smi_phy_read,
2927 .phy_write = mv88e6xxx_g2_smi_phy_write,
2928 .port_set_link = mv88e6xxx_port_set_link,
2929 .port_set_duplex = mv88e6xxx_port_set_duplex,
2930 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2931 .port_set_speed = mv88e6185_port_set_speed,
2932 .port_tag_remap = mv88e6095_port_tag_remap,
2933 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2934 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2935 .port_set_ether_type = mv88e6351_port_set_ether_type,
2936 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2937 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2938 .port_pause_limit = mv88e6097_port_pause_limit,
2939 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2940 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2941 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2942 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2943 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2944 .stats_get_strings = mv88e6095_stats_get_strings,
2945 .stats_get_stats = mv88e6095_stats_get_stats,
2946 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2947 .set_egress_port = mv88e6095_g1_set_egress_port,
2948 .watchdog_ops = &mv88e6097_watchdog_ops,
2949 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2950 .pot_clear = mv88e6xxx_g2_pot_clear,
2951 .reset = mv88e6352_g1_reset,
2952 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2953 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2954 .serdes_power = mv88e6341_serdes_power,
2957 static const struct mv88e6xxx_ops mv88e6176_ops = {
2958 /* MV88E6XXX_FAMILY_6352 */
2959 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2960 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2961 .irl_init_all = mv88e6352_g2_irl_init_all,
2962 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2963 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2964 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2965 .phy_read = mv88e6xxx_g2_smi_phy_read,
2966 .phy_write = mv88e6xxx_g2_smi_phy_write,
2967 .port_set_link = mv88e6xxx_port_set_link,
2968 .port_set_duplex = mv88e6xxx_port_set_duplex,
2969 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2970 .port_set_speed = mv88e6352_port_set_speed,
2971 .port_tag_remap = mv88e6095_port_tag_remap,
2972 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2973 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2974 .port_set_ether_type = mv88e6351_port_set_ether_type,
2975 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2976 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2977 .port_pause_limit = mv88e6097_port_pause_limit,
2978 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2979 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2980 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2981 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2982 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2983 .stats_get_strings = mv88e6095_stats_get_strings,
2984 .stats_get_stats = mv88e6095_stats_get_stats,
2985 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2986 .set_egress_port = mv88e6095_g1_set_egress_port,
2987 .watchdog_ops = &mv88e6097_watchdog_ops,
2988 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2989 .pot_clear = mv88e6xxx_g2_pot_clear,
2990 .reset = mv88e6352_g1_reset,
2991 .rmu_disable = mv88e6352_g1_rmu_disable,
2992 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2993 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2994 .serdes_power = mv88e6352_serdes_power,
2995 .gpio_ops = &mv88e6352_gpio_ops,
2998 static const struct mv88e6xxx_ops mv88e6185_ops = {
2999 /* MV88E6XXX_FAMILY_6185 */
3000 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3001 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3002 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3003 .phy_read = mv88e6185_phy_ppu_read,
3004 .phy_write = mv88e6185_phy_ppu_write,
3005 .port_set_link = mv88e6xxx_port_set_link,
3006 .port_set_duplex = mv88e6xxx_port_set_duplex,
3007 .port_set_speed = mv88e6185_port_set_speed,
3008 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3009 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3010 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3011 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3012 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3013 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3014 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3015 .stats_get_strings = mv88e6095_stats_get_strings,
3016 .stats_get_stats = mv88e6095_stats_get_stats,
3017 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3018 .set_egress_port = mv88e6095_g1_set_egress_port,
3019 .watchdog_ops = &mv88e6097_watchdog_ops,
3020 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3021 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3022 .ppu_enable = mv88e6185_g1_ppu_enable,
3023 .ppu_disable = mv88e6185_g1_ppu_disable,
3024 .reset = mv88e6185_g1_reset,
3025 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3026 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3029 static const struct mv88e6xxx_ops mv88e6190_ops = {
3030 /* MV88E6XXX_FAMILY_6390 */
3031 .irl_init_all = mv88e6390_g2_irl_init_all,
3032 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3033 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3034 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3035 .phy_read = mv88e6xxx_g2_smi_phy_read,
3036 .phy_write = mv88e6xxx_g2_smi_phy_write,
3037 .port_set_link = mv88e6xxx_port_set_link,
3038 .port_set_duplex = mv88e6xxx_port_set_duplex,
3039 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3040 .port_set_speed = mv88e6390_port_set_speed,
3041 .port_tag_remap = mv88e6390_port_tag_remap,
3042 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3043 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3044 .port_set_ether_type = mv88e6351_port_set_ether_type,
3045 .port_pause_limit = mv88e6390_port_pause_limit,
3046 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3047 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3048 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3049 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3050 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3051 .stats_get_strings = mv88e6320_stats_get_strings,
3052 .stats_get_stats = mv88e6390_stats_get_stats,
3053 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3054 .set_egress_port = mv88e6390_g1_set_egress_port,
3055 .watchdog_ops = &mv88e6390_watchdog_ops,
3056 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3057 .pot_clear = mv88e6xxx_g2_pot_clear,
3058 .reset = mv88e6352_g1_reset,
3059 .rmu_disable = mv88e6390_g1_rmu_disable,
3060 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3061 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3062 .serdes_power = mv88e6390_serdes_power,
3063 .gpio_ops = &mv88e6352_gpio_ops,
3066 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3067 /* MV88E6XXX_FAMILY_6390 */
3068 .irl_init_all = mv88e6390_g2_irl_init_all,
3069 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3070 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3071 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3072 .phy_read = mv88e6xxx_g2_smi_phy_read,
3073 .phy_write = mv88e6xxx_g2_smi_phy_write,
3074 .port_set_link = mv88e6xxx_port_set_link,
3075 .port_set_duplex = mv88e6xxx_port_set_duplex,
3076 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3077 .port_set_speed = mv88e6390x_port_set_speed,
3078 .port_tag_remap = mv88e6390_port_tag_remap,
3079 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3080 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3081 .port_set_ether_type = mv88e6351_port_set_ether_type,
3082 .port_pause_limit = mv88e6390_port_pause_limit,
3083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3085 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3086 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3087 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3088 .stats_get_strings = mv88e6320_stats_get_strings,
3089 .stats_get_stats = mv88e6390_stats_get_stats,
3090 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3091 .set_egress_port = mv88e6390_g1_set_egress_port,
3092 .watchdog_ops = &mv88e6390_watchdog_ops,
3093 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3094 .pot_clear = mv88e6xxx_g2_pot_clear,
3095 .reset = mv88e6352_g1_reset,
3096 .rmu_disable = mv88e6390_g1_rmu_disable,
3097 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3098 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3099 .serdes_power = mv88e6390_serdes_power,
3100 .gpio_ops = &mv88e6352_gpio_ops,
3103 static const struct mv88e6xxx_ops mv88e6191_ops = {
3104 /* MV88E6XXX_FAMILY_6390 */
3105 .irl_init_all = mv88e6390_g2_irl_init_all,
3106 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3107 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3108 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3109 .phy_read = mv88e6xxx_g2_smi_phy_read,
3110 .phy_write = mv88e6xxx_g2_smi_phy_write,
3111 .port_set_link = mv88e6xxx_port_set_link,
3112 .port_set_duplex = mv88e6xxx_port_set_duplex,
3113 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3114 .port_set_speed = mv88e6390_port_set_speed,
3115 .port_tag_remap = mv88e6390_port_tag_remap,
3116 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3117 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3118 .port_set_ether_type = mv88e6351_port_set_ether_type,
3119 .port_pause_limit = mv88e6390_port_pause_limit,
3120 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3121 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3122 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3123 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3124 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3125 .stats_get_strings = mv88e6320_stats_get_strings,
3126 .stats_get_stats = mv88e6390_stats_get_stats,
3127 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3128 .set_egress_port = mv88e6390_g1_set_egress_port,
3129 .watchdog_ops = &mv88e6390_watchdog_ops,
3130 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3131 .pot_clear = mv88e6xxx_g2_pot_clear,
3132 .reset = mv88e6352_g1_reset,
3133 .rmu_disable = mv88e6390_g1_rmu_disable,
3134 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3135 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3136 .serdes_power = mv88e6390_serdes_power,
3139 static const struct mv88e6xxx_ops mv88e6240_ops = {
3140 /* MV88E6XXX_FAMILY_6352 */
3141 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3142 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3143 .irl_init_all = mv88e6352_g2_irl_init_all,
3144 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3145 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3146 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3147 .phy_read = mv88e6xxx_g2_smi_phy_read,
3148 .phy_write = mv88e6xxx_g2_smi_phy_write,
3149 .port_set_link = mv88e6xxx_port_set_link,
3150 .port_set_duplex = mv88e6xxx_port_set_duplex,
3151 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3152 .port_set_speed = mv88e6352_port_set_speed,
3153 .port_tag_remap = mv88e6095_port_tag_remap,
3154 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3155 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3156 .port_set_ether_type = mv88e6351_port_set_ether_type,
3157 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3158 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3159 .port_pause_limit = mv88e6097_port_pause_limit,
3160 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3161 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3162 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3163 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3164 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3165 .stats_get_strings = mv88e6095_stats_get_strings,
3166 .stats_get_stats = mv88e6095_stats_get_stats,
3167 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3168 .set_egress_port = mv88e6095_g1_set_egress_port,
3169 .watchdog_ops = &mv88e6097_watchdog_ops,
3170 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3171 .pot_clear = mv88e6xxx_g2_pot_clear,
3172 .reset = mv88e6352_g1_reset,
3173 .rmu_disable = mv88e6352_g1_rmu_disable,
3174 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3175 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3176 .serdes_power = mv88e6352_serdes_power,
3177 .gpio_ops = &mv88e6352_gpio_ops,
3178 .avb_ops = &mv88e6352_avb_ops,
3181 static const struct mv88e6xxx_ops mv88e6290_ops = {
3182 /* MV88E6XXX_FAMILY_6390 */
3183 .irl_init_all = mv88e6390_g2_irl_init_all,
3184 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3185 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3186 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3187 .phy_read = mv88e6xxx_g2_smi_phy_read,
3188 .phy_write = mv88e6xxx_g2_smi_phy_write,
3189 .port_set_link = mv88e6xxx_port_set_link,
3190 .port_set_duplex = mv88e6xxx_port_set_duplex,
3191 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3192 .port_set_speed = mv88e6390_port_set_speed,
3193 .port_tag_remap = mv88e6390_port_tag_remap,
3194 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3195 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3196 .port_set_ether_type = mv88e6351_port_set_ether_type,
3197 .port_pause_limit = mv88e6390_port_pause_limit,
3198 .port_set_cmode = mv88e6390x_port_set_cmode,
3199 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3200 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3201 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3202 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3203 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3204 .stats_get_strings = mv88e6320_stats_get_strings,
3205 .stats_get_stats = mv88e6390_stats_get_stats,
3206 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3207 .set_egress_port = mv88e6390_g1_set_egress_port,
3208 .watchdog_ops = &mv88e6390_watchdog_ops,
3209 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3210 .pot_clear = mv88e6xxx_g2_pot_clear,
3211 .reset = mv88e6352_g1_reset,
3212 .rmu_disable = mv88e6390_g1_rmu_disable,
3213 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3214 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3215 .serdes_power = mv88e6390_serdes_power,
3216 .gpio_ops = &mv88e6352_gpio_ops,
3217 .avb_ops = &mv88e6390_avb_ops,
3220 static const struct mv88e6xxx_ops mv88e6320_ops = {
3221 /* MV88E6XXX_FAMILY_6320 */
3222 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3223 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3224 .irl_init_all = mv88e6352_g2_irl_init_all,
3225 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3226 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3227 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3228 .phy_read = mv88e6xxx_g2_smi_phy_read,
3229 .phy_write = mv88e6xxx_g2_smi_phy_write,
3230 .port_set_link = mv88e6xxx_port_set_link,
3231 .port_set_duplex = mv88e6xxx_port_set_duplex,
3232 .port_set_speed = mv88e6185_port_set_speed,
3233 .port_tag_remap = mv88e6095_port_tag_remap,
3234 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3235 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3236 .port_set_ether_type = mv88e6351_port_set_ether_type,
3237 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3238 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3239 .port_pause_limit = mv88e6097_port_pause_limit,
3240 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3241 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3242 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3243 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3244 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3245 .stats_get_strings = mv88e6320_stats_get_strings,
3246 .stats_get_stats = mv88e6320_stats_get_stats,
3247 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3248 .set_egress_port = mv88e6095_g1_set_egress_port,
3249 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3250 .pot_clear = mv88e6xxx_g2_pot_clear,
3251 .reset = mv88e6352_g1_reset,
3252 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3253 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3254 .gpio_ops = &mv88e6352_gpio_ops,
3255 .avb_ops = &mv88e6352_avb_ops,
3258 static const struct mv88e6xxx_ops mv88e6321_ops = {
3259 /* MV88E6XXX_FAMILY_6320 */
3260 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3261 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3262 .irl_init_all = mv88e6352_g2_irl_init_all,
3263 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3264 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3266 .phy_read = mv88e6xxx_g2_smi_phy_read,
3267 .phy_write = mv88e6xxx_g2_smi_phy_write,
3268 .port_set_link = mv88e6xxx_port_set_link,
3269 .port_set_duplex = mv88e6xxx_port_set_duplex,
3270 .port_set_speed = mv88e6185_port_set_speed,
3271 .port_tag_remap = mv88e6095_port_tag_remap,
3272 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3273 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3274 .port_set_ether_type = mv88e6351_port_set_ether_type,
3275 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3276 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3277 .port_pause_limit = mv88e6097_port_pause_limit,
3278 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3279 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3280 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3281 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3282 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3283 .stats_get_strings = mv88e6320_stats_get_strings,
3284 .stats_get_stats = mv88e6320_stats_get_stats,
3285 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3286 .set_egress_port = mv88e6095_g1_set_egress_port,
3287 .reset = mv88e6352_g1_reset,
3288 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3289 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3290 .gpio_ops = &mv88e6352_gpio_ops,
3291 .avb_ops = &mv88e6352_avb_ops,
3294 static const struct mv88e6xxx_ops mv88e6341_ops = {
3295 /* MV88E6XXX_FAMILY_6341 */
3296 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3297 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3298 .irl_init_all = mv88e6352_g2_irl_init_all,
3299 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3300 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3302 .phy_read = mv88e6xxx_g2_smi_phy_read,
3303 .phy_write = mv88e6xxx_g2_smi_phy_write,
3304 .port_set_link = mv88e6xxx_port_set_link,
3305 .port_set_duplex = mv88e6xxx_port_set_duplex,
3306 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3307 .port_set_speed = mv88e6390_port_set_speed,
3308 .port_tag_remap = mv88e6095_port_tag_remap,
3309 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3310 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3311 .port_set_ether_type = mv88e6351_port_set_ether_type,
3312 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3313 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3314 .port_pause_limit = mv88e6097_port_pause_limit,
3315 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3316 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3317 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3318 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3319 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3320 .stats_get_strings = mv88e6320_stats_get_strings,
3321 .stats_get_stats = mv88e6390_stats_get_stats,
3322 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3323 .set_egress_port = mv88e6390_g1_set_egress_port,
3324 .watchdog_ops = &mv88e6390_watchdog_ops,
3325 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3326 .pot_clear = mv88e6xxx_g2_pot_clear,
3327 .reset = mv88e6352_g1_reset,
3328 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3329 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3330 .gpio_ops = &mv88e6352_gpio_ops,
3331 .avb_ops = &mv88e6390_avb_ops,
3334 static const struct mv88e6xxx_ops mv88e6350_ops = {
3335 /* MV88E6XXX_FAMILY_6351 */
3336 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3337 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3338 .irl_init_all = mv88e6352_g2_irl_init_all,
3339 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3340 .phy_read = mv88e6xxx_g2_smi_phy_read,
3341 .phy_write = mv88e6xxx_g2_smi_phy_write,
3342 .port_set_link = mv88e6xxx_port_set_link,
3343 .port_set_duplex = mv88e6xxx_port_set_duplex,
3344 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3345 .port_set_speed = mv88e6185_port_set_speed,
3346 .port_tag_remap = mv88e6095_port_tag_remap,
3347 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3348 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3349 .port_set_ether_type = mv88e6351_port_set_ether_type,
3350 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3351 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3352 .port_pause_limit = mv88e6097_port_pause_limit,
3353 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3354 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3355 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3356 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3357 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3358 .stats_get_strings = mv88e6095_stats_get_strings,
3359 .stats_get_stats = mv88e6095_stats_get_stats,
3360 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3361 .set_egress_port = mv88e6095_g1_set_egress_port,
3362 .watchdog_ops = &mv88e6097_watchdog_ops,
3363 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3364 .pot_clear = mv88e6xxx_g2_pot_clear,
3365 .reset = mv88e6352_g1_reset,
3366 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3367 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3370 static const struct mv88e6xxx_ops mv88e6351_ops = {
3371 /* MV88E6XXX_FAMILY_6351 */
3372 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3373 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3374 .irl_init_all = mv88e6352_g2_irl_init_all,
3375 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3376 .phy_read = mv88e6xxx_g2_smi_phy_read,
3377 .phy_write = mv88e6xxx_g2_smi_phy_write,
3378 .port_set_link = mv88e6xxx_port_set_link,
3379 .port_set_duplex = mv88e6xxx_port_set_duplex,
3380 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3381 .port_set_speed = mv88e6185_port_set_speed,
3382 .port_tag_remap = mv88e6095_port_tag_remap,
3383 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3384 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3385 .port_set_ether_type = mv88e6351_port_set_ether_type,
3386 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3387 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3388 .port_pause_limit = mv88e6097_port_pause_limit,
3389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3391 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3392 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3393 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3394 .stats_get_strings = mv88e6095_stats_get_strings,
3395 .stats_get_stats = mv88e6095_stats_get_stats,
3396 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3397 .set_egress_port = mv88e6095_g1_set_egress_port,
3398 .watchdog_ops = &mv88e6097_watchdog_ops,
3399 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3400 .pot_clear = mv88e6xxx_g2_pot_clear,
3401 .reset = mv88e6352_g1_reset,
3402 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3403 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3404 .avb_ops = &mv88e6352_avb_ops,
3407 static const struct mv88e6xxx_ops mv88e6352_ops = {
3408 /* MV88E6XXX_FAMILY_6352 */
3409 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3410 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3411 .irl_init_all = mv88e6352_g2_irl_init_all,
3412 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3413 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3414 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3415 .phy_read = mv88e6xxx_g2_smi_phy_read,
3416 .phy_write = mv88e6xxx_g2_smi_phy_write,
3417 .port_set_link = mv88e6xxx_port_set_link,
3418 .port_set_duplex = mv88e6xxx_port_set_duplex,
3419 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3420 .port_set_speed = mv88e6352_port_set_speed,
3421 .port_tag_remap = mv88e6095_port_tag_remap,
3422 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3423 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3424 .port_set_ether_type = mv88e6351_port_set_ether_type,
3425 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3426 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3427 .port_pause_limit = mv88e6097_port_pause_limit,
3428 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3429 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3430 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3431 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3432 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3433 .stats_get_strings = mv88e6095_stats_get_strings,
3434 .stats_get_stats = mv88e6095_stats_get_stats,
3435 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3436 .set_egress_port = mv88e6095_g1_set_egress_port,
3437 .watchdog_ops = &mv88e6097_watchdog_ops,
3438 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3439 .pot_clear = mv88e6xxx_g2_pot_clear,
3440 .reset = mv88e6352_g1_reset,
3441 .rmu_disable = mv88e6352_g1_rmu_disable,
3442 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3443 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3444 .serdes_power = mv88e6352_serdes_power,
3445 .gpio_ops = &mv88e6352_gpio_ops,
3446 .avb_ops = &mv88e6352_avb_ops,
3447 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3448 .serdes_get_strings = mv88e6352_serdes_get_strings,
3449 .serdes_get_stats = mv88e6352_serdes_get_stats,
3452 static const struct mv88e6xxx_ops mv88e6390_ops = {
3453 /* MV88E6XXX_FAMILY_6390 */
3454 .irl_init_all = mv88e6390_g2_irl_init_all,
3455 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3456 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3457 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3458 .phy_read = mv88e6xxx_g2_smi_phy_read,
3459 .phy_write = mv88e6xxx_g2_smi_phy_write,
3460 .port_set_link = mv88e6xxx_port_set_link,
3461 .port_set_duplex = mv88e6xxx_port_set_duplex,
3462 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3463 .port_set_speed = mv88e6390_port_set_speed,
3464 .port_tag_remap = mv88e6390_port_tag_remap,
3465 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3466 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3467 .port_set_ether_type = mv88e6351_port_set_ether_type,
3468 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3469 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3470 .port_pause_limit = mv88e6390_port_pause_limit,
3471 .port_set_cmode = mv88e6390x_port_set_cmode,
3472 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3473 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3474 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3475 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3476 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3477 .stats_get_strings = mv88e6320_stats_get_strings,
3478 .stats_get_stats = mv88e6390_stats_get_stats,
3479 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3480 .set_egress_port = mv88e6390_g1_set_egress_port,
3481 .watchdog_ops = &mv88e6390_watchdog_ops,
3482 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3483 .pot_clear = mv88e6xxx_g2_pot_clear,
3484 .reset = mv88e6352_g1_reset,
3485 .rmu_disable = mv88e6390_g1_rmu_disable,
3486 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3487 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3488 .serdes_power = mv88e6390_serdes_power,
3489 .gpio_ops = &mv88e6352_gpio_ops,
3490 .avb_ops = &mv88e6390_avb_ops,
3493 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3494 /* MV88E6XXX_FAMILY_6390 */
3495 .irl_init_all = mv88e6390_g2_irl_init_all,
3496 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3497 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3499 .phy_read = mv88e6xxx_g2_smi_phy_read,
3500 .phy_write = mv88e6xxx_g2_smi_phy_write,
3501 .port_set_link = mv88e6xxx_port_set_link,
3502 .port_set_duplex = mv88e6xxx_port_set_duplex,
3503 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3504 .port_set_speed = mv88e6390x_port_set_speed,
3505 .port_tag_remap = mv88e6390_port_tag_remap,
3506 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3507 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3508 .port_set_ether_type = mv88e6351_port_set_ether_type,
3509 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3510 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3511 .port_pause_limit = mv88e6390_port_pause_limit,
3512 .port_set_cmode = mv88e6390x_port_set_cmode,
3513 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3514 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3515 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3516 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3517 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3518 .stats_get_strings = mv88e6320_stats_get_strings,
3519 .stats_get_stats = mv88e6390_stats_get_stats,
3520 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3521 .set_egress_port = mv88e6390_g1_set_egress_port,
3522 .watchdog_ops = &mv88e6390_watchdog_ops,
3523 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3524 .pot_clear = mv88e6xxx_g2_pot_clear,
3525 .reset = mv88e6352_g1_reset,
3526 .rmu_disable = mv88e6390_g1_rmu_disable,
3527 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3528 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3529 .serdes_power = mv88e6390_serdes_power,
3530 .gpio_ops = &mv88e6352_gpio_ops,
3531 .avb_ops = &mv88e6390_avb_ops,
3534 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3536 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3537 .family = MV88E6XXX_FAMILY_6097,
3538 .name = "Marvell 88E6085",
3539 .num_databases = 4096,
3541 .num_internal_phys = 5,
3543 .port_base_addr = 0x10,
3544 .phy_base_addr = 0x0,
3545 .global1_addr = 0x1b,
3546 .global2_addr = 0x1c,
3547 .age_time_coeff = 15000,
3550 .atu_move_port_mask = 0xf,
3553 .tag_protocol = DSA_TAG_PROTO_DSA,
3554 .ops = &mv88e6085_ops,
3558 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3559 .family = MV88E6XXX_FAMILY_6095,
3560 .name = "Marvell 88E6095/88E6095F",
3561 .num_databases = 256,
3563 .num_internal_phys = 0,
3565 .port_base_addr = 0x10,
3566 .phy_base_addr = 0x0,
3567 .global1_addr = 0x1b,
3568 .global2_addr = 0x1c,
3569 .age_time_coeff = 15000,
3571 .atu_move_port_mask = 0xf,
3573 .tag_protocol = DSA_TAG_PROTO_DSA,
3574 .ops = &mv88e6095_ops,
3578 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3579 .family = MV88E6XXX_FAMILY_6097,
3580 .name = "Marvell 88E6097/88E6097F",
3581 .num_databases = 4096,
3583 .num_internal_phys = 8,
3585 .port_base_addr = 0x10,
3586 .phy_base_addr = 0x0,
3587 .global1_addr = 0x1b,
3588 .global2_addr = 0x1c,
3589 .age_time_coeff = 15000,
3592 .atu_move_port_mask = 0xf,
3595 .tag_protocol = DSA_TAG_PROTO_EDSA,
3596 .ops = &mv88e6097_ops,
3600 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3601 .family = MV88E6XXX_FAMILY_6165,
3602 .name = "Marvell 88E6123",
3603 .num_databases = 4096,
3605 .num_internal_phys = 5,
3607 .port_base_addr = 0x10,
3608 .phy_base_addr = 0x0,
3609 .global1_addr = 0x1b,
3610 .global2_addr = 0x1c,
3611 .age_time_coeff = 15000,
3614 .atu_move_port_mask = 0xf,
3617 .tag_protocol = DSA_TAG_PROTO_EDSA,
3618 .ops = &mv88e6123_ops,
3622 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3623 .family = MV88E6XXX_FAMILY_6185,
3624 .name = "Marvell 88E6131",
3625 .num_databases = 256,
3627 .num_internal_phys = 0,
3629 .port_base_addr = 0x10,
3630 .phy_base_addr = 0x0,
3631 .global1_addr = 0x1b,
3632 .global2_addr = 0x1c,
3633 .age_time_coeff = 15000,
3635 .atu_move_port_mask = 0xf,
3637 .tag_protocol = DSA_TAG_PROTO_DSA,
3638 .ops = &mv88e6131_ops,
3642 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3643 .family = MV88E6XXX_FAMILY_6341,
3644 .name = "Marvell 88E6141",
3645 .num_databases = 4096,
3647 .num_internal_phys = 5,
3650 .port_base_addr = 0x10,
3651 .phy_base_addr = 0x10,
3652 .global1_addr = 0x1b,
3653 .global2_addr = 0x1c,
3654 .age_time_coeff = 3750,
3655 .atu_move_port_mask = 0x1f,
3660 .tag_protocol = DSA_TAG_PROTO_EDSA,
3661 .ops = &mv88e6141_ops,
3665 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3666 .family = MV88E6XXX_FAMILY_6165,
3667 .name = "Marvell 88E6161",
3668 .num_databases = 4096,
3670 .num_internal_phys = 5,
3672 .port_base_addr = 0x10,
3673 .phy_base_addr = 0x0,
3674 .global1_addr = 0x1b,
3675 .global2_addr = 0x1c,
3676 .age_time_coeff = 15000,
3679 .atu_move_port_mask = 0xf,
3682 .tag_protocol = DSA_TAG_PROTO_EDSA,
3683 .ops = &mv88e6161_ops,
3687 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3688 .family = MV88E6XXX_FAMILY_6165,
3689 .name = "Marvell 88E6165",
3690 .num_databases = 4096,
3692 .num_internal_phys = 0,
3694 .port_base_addr = 0x10,
3695 .phy_base_addr = 0x0,
3696 .global1_addr = 0x1b,
3697 .global2_addr = 0x1c,
3698 .age_time_coeff = 15000,
3701 .atu_move_port_mask = 0xf,
3704 .tag_protocol = DSA_TAG_PROTO_DSA,
3705 .ops = &mv88e6165_ops,
3709 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3710 .family = MV88E6XXX_FAMILY_6351,
3711 .name = "Marvell 88E6171",
3712 .num_databases = 4096,
3714 .num_internal_phys = 5,
3716 .port_base_addr = 0x10,
3717 .phy_base_addr = 0x0,
3718 .global1_addr = 0x1b,
3719 .global2_addr = 0x1c,
3720 .age_time_coeff = 15000,
3723 .atu_move_port_mask = 0xf,
3726 .tag_protocol = DSA_TAG_PROTO_EDSA,
3727 .ops = &mv88e6171_ops,
3731 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3732 .family = MV88E6XXX_FAMILY_6352,
3733 .name = "Marvell 88E6172",
3734 .num_databases = 4096,
3736 .num_internal_phys = 5,
3739 .port_base_addr = 0x10,
3740 .phy_base_addr = 0x0,
3741 .global1_addr = 0x1b,
3742 .global2_addr = 0x1c,
3743 .age_time_coeff = 15000,
3746 .atu_move_port_mask = 0xf,
3749 .tag_protocol = DSA_TAG_PROTO_EDSA,
3750 .ops = &mv88e6172_ops,
3754 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3755 .family = MV88E6XXX_FAMILY_6351,
3756 .name = "Marvell 88E6175",
3757 .num_databases = 4096,
3759 .num_internal_phys = 5,
3761 .port_base_addr = 0x10,
3762 .phy_base_addr = 0x0,
3763 .global1_addr = 0x1b,
3764 .global2_addr = 0x1c,
3765 .age_time_coeff = 15000,
3768 .atu_move_port_mask = 0xf,
3771 .tag_protocol = DSA_TAG_PROTO_EDSA,
3772 .ops = &mv88e6175_ops,
3776 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3777 .family = MV88E6XXX_FAMILY_6352,
3778 .name = "Marvell 88E6176",
3779 .num_databases = 4096,
3781 .num_internal_phys = 5,
3784 .port_base_addr = 0x10,
3785 .phy_base_addr = 0x0,
3786 .global1_addr = 0x1b,
3787 .global2_addr = 0x1c,
3788 .age_time_coeff = 15000,
3791 .atu_move_port_mask = 0xf,
3794 .tag_protocol = DSA_TAG_PROTO_EDSA,
3795 .ops = &mv88e6176_ops,
3799 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3800 .family = MV88E6XXX_FAMILY_6185,
3801 .name = "Marvell 88E6185",
3802 .num_databases = 256,
3804 .num_internal_phys = 0,
3806 .port_base_addr = 0x10,
3807 .phy_base_addr = 0x0,
3808 .global1_addr = 0x1b,
3809 .global2_addr = 0x1c,
3810 .age_time_coeff = 15000,
3812 .atu_move_port_mask = 0xf,
3814 .tag_protocol = DSA_TAG_PROTO_EDSA,
3815 .ops = &mv88e6185_ops,
3819 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3820 .family = MV88E6XXX_FAMILY_6390,
3821 .name = "Marvell 88E6190",
3822 .num_databases = 4096,
3823 .num_ports = 11, /* 10 + Z80 */
3824 .num_internal_phys = 11,
3827 .port_base_addr = 0x0,
3828 .phy_base_addr = 0x0,
3829 .global1_addr = 0x1b,
3830 .global2_addr = 0x1c,
3831 .tag_protocol = DSA_TAG_PROTO_DSA,
3832 .age_time_coeff = 3750,
3837 .atu_move_port_mask = 0x1f,
3838 .ops = &mv88e6190_ops,
3842 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3843 .family = MV88E6XXX_FAMILY_6390,
3844 .name = "Marvell 88E6190X",
3845 .num_databases = 4096,
3846 .num_ports = 11, /* 10 + Z80 */
3847 .num_internal_phys = 11,
3850 .port_base_addr = 0x0,
3851 .phy_base_addr = 0x0,
3852 .global1_addr = 0x1b,
3853 .global2_addr = 0x1c,
3854 .age_time_coeff = 3750,
3857 .atu_move_port_mask = 0x1f,
3860 .tag_protocol = DSA_TAG_PROTO_DSA,
3861 .ops = &mv88e6190x_ops,
3865 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3866 .family = MV88E6XXX_FAMILY_6390,
3867 .name = "Marvell 88E6191",
3868 .num_databases = 4096,
3869 .num_ports = 11, /* 10 + Z80 */
3870 .num_internal_phys = 11,
3872 .port_base_addr = 0x0,
3873 .phy_base_addr = 0x0,
3874 .global1_addr = 0x1b,
3875 .global2_addr = 0x1c,
3876 .age_time_coeff = 3750,
3879 .atu_move_port_mask = 0x1f,
3882 .tag_protocol = DSA_TAG_PROTO_DSA,
3883 .ptp_support = true,
3884 .ops = &mv88e6191_ops,
3888 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3889 .family = MV88E6XXX_FAMILY_6352,
3890 .name = "Marvell 88E6240",
3891 .num_databases = 4096,
3893 .num_internal_phys = 5,
3896 .port_base_addr = 0x10,
3897 .phy_base_addr = 0x0,
3898 .global1_addr = 0x1b,
3899 .global2_addr = 0x1c,
3900 .age_time_coeff = 15000,
3903 .atu_move_port_mask = 0xf,
3906 .tag_protocol = DSA_TAG_PROTO_EDSA,
3907 .ptp_support = true,
3908 .ops = &mv88e6240_ops,
3912 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3913 .family = MV88E6XXX_FAMILY_6390,
3914 .name = "Marvell 88E6290",
3915 .num_databases = 4096,
3916 .num_ports = 11, /* 10 + Z80 */
3917 .num_internal_phys = 11,
3920 .port_base_addr = 0x0,
3921 .phy_base_addr = 0x0,
3922 .global1_addr = 0x1b,
3923 .global2_addr = 0x1c,
3924 .age_time_coeff = 3750,
3927 .atu_move_port_mask = 0x1f,
3930 .tag_protocol = DSA_TAG_PROTO_DSA,
3931 .ptp_support = true,
3932 .ops = &mv88e6290_ops,
3936 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3937 .family = MV88E6XXX_FAMILY_6320,
3938 .name = "Marvell 88E6320",
3939 .num_databases = 4096,
3941 .num_internal_phys = 5,
3944 .port_base_addr = 0x10,
3945 .phy_base_addr = 0x0,
3946 .global1_addr = 0x1b,
3947 .global2_addr = 0x1c,
3948 .age_time_coeff = 15000,
3951 .atu_move_port_mask = 0xf,
3954 .tag_protocol = DSA_TAG_PROTO_EDSA,
3955 .ptp_support = true,
3956 .ops = &mv88e6320_ops,
3960 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3961 .family = MV88E6XXX_FAMILY_6320,
3962 .name = "Marvell 88E6321",
3963 .num_databases = 4096,
3965 .num_internal_phys = 5,
3968 .port_base_addr = 0x10,
3969 .phy_base_addr = 0x0,
3970 .global1_addr = 0x1b,
3971 .global2_addr = 0x1c,
3972 .age_time_coeff = 15000,
3975 .atu_move_port_mask = 0xf,
3977 .tag_protocol = DSA_TAG_PROTO_EDSA,
3978 .ptp_support = true,
3979 .ops = &mv88e6321_ops,
3983 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3984 .family = MV88E6XXX_FAMILY_6341,
3985 .name = "Marvell 88E6341",
3986 .num_databases = 4096,
3987 .num_internal_phys = 5,
3991 .port_base_addr = 0x10,
3992 .phy_base_addr = 0x10,
3993 .global1_addr = 0x1b,
3994 .global2_addr = 0x1c,
3995 .age_time_coeff = 3750,
3996 .atu_move_port_mask = 0x1f,
4001 .tag_protocol = DSA_TAG_PROTO_EDSA,
4002 .ptp_support = true,
4003 .ops = &mv88e6341_ops,
4007 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4008 .family = MV88E6XXX_FAMILY_6351,
4009 .name = "Marvell 88E6350",
4010 .num_databases = 4096,
4012 .num_internal_phys = 5,
4014 .port_base_addr = 0x10,
4015 .phy_base_addr = 0x0,
4016 .global1_addr = 0x1b,
4017 .global2_addr = 0x1c,
4018 .age_time_coeff = 15000,
4021 .atu_move_port_mask = 0xf,
4024 .tag_protocol = DSA_TAG_PROTO_EDSA,
4025 .ops = &mv88e6350_ops,
4029 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4030 .family = MV88E6XXX_FAMILY_6351,
4031 .name = "Marvell 88E6351",
4032 .num_databases = 4096,
4034 .num_internal_phys = 5,
4036 .port_base_addr = 0x10,
4037 .phy_base_addr = 0x0,
4038 .global1_addr = 0x1b,
4039 .global2_addr = 0x1c,
4040 .age_time_coeff = 15000,
4043 .atu_move_port_mask = 0xf,
4046 .tag_protocol = DSA_TAG_PROTO_EDSA,
4047 .ops = &mv88e6351_ops,
4051 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4052 .family = MV88E6XXX_FAMILY_6352,
4053 .name = "Marvell 88E6352",
4054 .num_databases = 4096,
4056 .num_internal_phys = 5,
4059 .port_base_addr = 0x10,
4060 .phy_base_addr = 0x0,
4061 .global1_addr = 0x1b,
4062 .global2_addr = 0x1c,
4063 .age_time_coeff = 15000,
4066 .atu_move_port_mask = 0xf,
4069 .tag_protocol = DSA_TAG_PROTO_EDSA,
4070 .ptp_support = true,
4071 .ops = &mv88e6352_ops,
4074 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4075 .family = MV88E6XXX_FAMILY_6390,
4076 .name = "Marvell 88E6390",
4077 .num_databases = 4096,
4078 .num_ports = 11, /* 10 + Z80 */
4079 .num_internal_phys = 11,
4082 .port_base_addr = 0x0,
4083 .phy_base_addr = 0x0,
4084 .global1_addr = 0x1b,
4085 .global2_addr = 0x1c,
4086 .age_time_coeff = 3750,
4089 .atu_move_port_mask = 0x1f,
4092 .tag_protocol = DSA_TAG_PROTO_DSA,
4093 .ptp_support = true,
4094 .ops = &mv88e6390_ops,
4097 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4098 .family = MV88E6XXX_FAMILY_6390,
4099 .name = "Marvell 88E6390X",
4100 .num_databases = 4096,
4101 .num_ports = 11, /* 10 + Z80 */
4102 .num_internal_phys = 11,
4105 .port_base_addr = 0x0,
4106 .phy_base_addr = 0x0,
4107 .global1_addr = 0x1b,
4108 .global2_addr = 0x1c,
4109 .age_time_coeff = 3750,
4112 .atu_move_port_mask = 0x1f,
4115 .tag_protocol = DSA_TAG_PROTO_DSA,
4116 .ptp_support = true,
4117 .ops = &mv88e6390x_ops,
4121 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4125 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4126 if (mv88e6xxx_table[i].prod_num == prod_num)
4127 return &mv88e6xxx_table[i];
4132 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4134 const struct mv88e6xxx_info *info;
4135 unsigned int prod_num, rev;
4139 mutex_lock(&chip->reg_lock);
4140 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4141 mutex_unlock(&chip->reg_lock);
4145 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4146 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4148 info = mv88e6xxx_lookup_info(prod_num);
4152 /* Update the compatible info with the probed one */
4155 err = mv88e6xxx_g2_require(chip);
4159 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4160 chip->info->prod_num, chip->info->name, rev);
4165 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4167 struct mv88e6xxx_chip *chip;
4169 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4175 mutex_init(&chip->reg_lock);
4176 INIT_LIST_HEAD(&chip->mdios);
4181 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4182 struct mii_bus *bus, int sw_addr)
4185 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4186 else if (chip->info->multi_chip)
4187 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4192 chip->sw_addr = sw_addr;
4197 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4200 struct mv88e6xxx_chip *chip = ds->priv;
4202 return chip->info->tag_protocol;
4205 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4206 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4207 struct device *host_dev, int sw_addr,
4210 struct mv88e6xxx_chip *chip;
4211 struct mii_bus *bus;
4214 bus = dsa_host_dev_to_mii_bus(host_dev);
4218 chip = mv88e6xxx_alloc_chip(dsa_dev);
4222 /* Legacy SMI probing will only support chips similar to 88E6085 */
4223 chip->info = &mv88e6xxx_table[MV88E6085];
4225 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4229 err = mv88e6xxx_detect(chip);
4233 mutex_lock(&chip->reg_lock);
4234 err = mv88e6xxx_switch_reset(chip);
4235 mutex_unlock(&chip->reg_lock);
4239 mv88e6xxx_phy_init(chip);
4241 err = mv88e6xxx_mdios_register(chip, NULL);
4247 return chip->info->name;
4249 devm_kfree(dsa_dev, chip);
4255 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4256 const struct switchdev_obj_port_mdb *mdb)
4258 /* We don't need any dynamic resource from the kernel (yet),
4259 * so skip the prepare phase.
4265 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4266 const struct switchdev_obj_port_mdb *mdb)
4268 struct mv88e6xxx_chip *chip = ds->priv;
4270 mutex_lock(&chip->reg_lock);
4271 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4272 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4273 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4275 mutex_unlock(&chip->reg_lock);
4278 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4279 const struct switchdev_obj_port_mdb *mdb)
4281 struct mv88e6xxx_chip *chip = ds->priv;
4284 mutex_lock(&chip->reg_lock);
4285 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4286 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4287 mutex_unlock(&chip->reg_lock);
4292 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4293 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4294 .probe = mv88e6xxx_drv_probe,
4296 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4297 .setup = mv88e6xxx_setup,
4298 .adjust_link = mv88e6xxx_adjust_link,
4299 .phylink_validate = mv88e6xxx_validate,
4300 .phylink_mac_link_state = mv88e6xxx_link_state,
4301 .phylink_mac_config = mv88e6xxx_mac_config,
4302 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
4303 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
4304 .get_strings = mv88e6xxx_get_strings,
4305 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4306 .get_sset_count = mv88e6xxx_get_sset_count,
4307 .port_enable = mv88e6xxx_port_enable,
4308 .port_disable = mv88e6xxx_port_disable,
4309 .get_mac_eee = mv88e6xxx_get_mac_eee,
4310 .set_mac_eee = mv88e6xxx_set_mac_eee,
4311 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4312 .get_eeprom = mv88e6xxx_get_eeprom,
4313 .set_eeprom = mv88e6xxx_set_eeprom,
4314 .get_regs_len = mv88e6xxx_get_regs_len,
4315 .get_regs = mv88e6xxx_get_regs,
4316 .set_ageing_time = mv88e6xxx_set_ageing_time,
4317 .port_bridge_join = mv88e6xxx_port_bridge_join,
4318 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4319 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4320 .port_fast_age = mv88e6xxx_port_fast_age,
4321 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4322 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4323 .port_vlan_add = mv88e6xxx_port_vlan_add,
4324 .port_vlan_del = mv88e6xxx_port_vlan_del,
4325 .port_fdb_add = mv88e6xxx_port_fdb_add,
4326 .port_fdb_del = mv88e6xxx_port_fdb_del,
4327 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4328 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4329 .port_mdb_add = mv88e6xxx_port_mdb_add,
4330 .port_mdb_del = mv88e6xxx_port_mdb_del,
4331 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4332 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4333 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
4334 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
4335 .port_txtstamp = mv88e6xxx_port_txtstamp,
4336 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
4337 .get_ts_info = mv88e6xxx_get_ts_info,
4340 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4341 .ops = &mv88e6xxx_switch_ops,
4344 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4346 struct device *dev = chip->dev;
4347 struct dsa_switch *ds;
4349 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4355 ds->ops = &mv88e6xxx_switch_ops;
4356 ds->ageing_time_min = chip->info->age_time_coeff;
4357 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4359 dev_set_drvdata(dev, ds);
4361 return dsa_register_switch(ds);
4364 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4366 dsa_unregister_switch(chip->ds);
4369 static const void *pdata_device_get_match_data(struct device *dev)
4371 const struct of_device_id *matches = dev->driver->of_match_table;
4372 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
4374 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
4376 if (!strcmp(pdata->compatible, matches->compatible))
4377 return matches->data;
4382 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4384 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4385 const struct mv88e6xxx_info *compat_info = NULL;
4386 struct device *dev = &mdiodev->dev;
4387 struct device_node *np = dev->of_node;
4388 struct mv88e6xxx_chip *chip;
4396 compat_info = of_device_get_match_data(dev);
4399 compat_info = pdata_device_get_match_data(dev);
4404 for (port = 0; port < DSA_MAX_PORTS; port++) {
4405 if (!(pdata->enabled_ports & (1 << port)))
4407 if (strcmp(pdata->cd.port_names[port], "cpu"))
4409 pdata->cd.netdev[port] = &pdata->netdev->dev;
4417 chip = mv88e6xxx_alloc_chip(dev);
4423 chip->info = compat_info;
4425 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4429 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4430 if (IS_ERR(chip->reset)) {
4431 err = PTR_ERR(chip->reset);
4435 err = mv88e6xxx_detect(chip);
4439 mv88e6xxx_phy_init(chip);
4441 if (chip->info->ops->get_eeprom) {
4443 of_property_read_u32(np, "eeprom-length",
4446 chip->eeprom_len = pdata->eeprom_len;
4449 mutex_lock(&chip->reg_lock);
4450 err = mv88e6xxx_switch_reset(chip);
4451 mutex_unlock(&chip->reg_lock);
4455 chip->irq = of_irq_get(np, 0);
4456 if (chip->irq == -EPROBE_DEFER) {
4461 /* Has to be performed before the MDIO bus is created, because
4462 * the PHYs will link their interrupts to these interrupt
4465 mutex_lock(&chip->reg_lock);
4467 err = mv88e6xxx_g1_irq_setup(chip);
4469 err = mv88e6xxx_irq_poll_setup(chip);
4470 mutex_unlock(&chip->reg_lock);
4475 if (chip->info->g2_irqs > 0) {
4476 err = mv88e6xxx_g2_irq_setup(chip);
4481 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4485 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4487 goto out_g1_atu_prob_irq;
4489 err = mv88e6xxx_mdios_register(chip, np);
4491 goto out_g1_vtu_prob_irq;
4493 err = mv88e6xxx_register_switch(chip);
4500 mv88e6xxx_mdios_unregister(chip);
4501 out_g1_vtu_prob_irq:
4502 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4503 out_g1_atu_prob_irq:
4504 mv88e6xxx_g1_atu_prob_irq_free(chip);
4506 if (chip->info->g2_irqs > 0)
4507 mv88e6xxx_g2_irq_free(chip);
4509 mutex_lock(&chip->reg_lock);
4511 mv88e6xxx_g1_irq_free(chip);
4513 mv88e6xxx_irq_poll_free(chip);
4514 mutex_unlock(&chip->reg_lock);
4517 dev_put(pdata->netdev);
4522 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4524 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4525 struct mv88e6xxx_chip *chip = ds->priv;
4527 if (chip->info->ptp_support) {
4528 mv88e6xxx_hwtstamp_free(chip);
4529 mv88e6xxx_ptp_free(chip);
4532 mv88e6xxx_phy_destroy(chip);
4533 mv88e6xxx_unregister_switch(chip);
4534 mv88e6xxx_mdios_unregister(chip);
4536 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4537 mv88e6xxx_g1_atu_prob_irq_free(chip);
4539 if (chip->info->g2_irqs > 0)
4540 mv88e6xxx_g2_irq_free(chip);
4542 mutex_lock(&chip->reg_lock);
4544 mv88e6xxx_g1_irq_free(chip);
4546 mv88e6xxx_irq_poll_free(chip);
4547 mutex_unlock(&chip->reg_lock);
4550 static const struct of_device_id mv88e6xxx_of_match[] = {
4552 .compatible = "marvell,mv88e6085",
4553 .data = &mv88e6xxx_table[MV88E6085],
4556 .compatible = "marvell,mv88e6190",
4557 .data = &mv88e6xxx_table[MV88E6190],
4562 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4564 static struct mdio_driver mv88e6xxx_driver = {
4565 .probe = mv88e6xxx_probe,
4566 .remove = mv88e6xxx_remove,
4568 .name = "mv88e6085",
4569 .of_match_table = mv88e6xxx_of_match,
4573 static int __init mv88e6xxx_init(void)
4575 register_switch_driver(&mv88e6xxx_switch_drv);
4576 return mdio_driver_register(&mv88e6xxx_driver);
4578 module_init(mv88e6xxx_init);
4580 static void __exit mv88e6xxx_cleanup(void)
4582 mdio_driver_unregister(&mv88e6xxx_driver);
4583 unregister_switch_driver(&mv88e6xxx_switch_drv);
4585 module_exit(mv88e6xxx_cleanup);
4587 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4588 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4589 MODULE_LICENSE("GPL");