drivers/net/chelsio/vsc8244_reg.h

   1 /* $Date: 2005/11/23 16:28:53 $ $RCSfile: vsc8244_reg.h,v $ $Revision: 1.1 $ */
   2 #ifndef CHELSIO_MV8E1XXX_H
   3 #define CHELSIO_MV8E1XXX_H
   4
   5 #ifndef BMCR_SPEED1000
   6 # define BMCR_SPEED1000 0x40
   7 #endif
   8
   9 #ifndef ADVERTISE_PAUSE
  10 # define ADVERTISE_PAUSE 0x400
  11 #endif
  12 #ifndef ADVERTISE_PAUSE_ASYM
  13 # define ADVERTISE_PAUSE_ASYM 0x800
  14 #endif
  15
  16 /* Gigabit MII registers */
  17 #define MII_GBMR 1       /* 1000Base-T mode register */
  18 #define MII_GBCR 9       /* 1000Base-T control register */
  19 #define MII_GBSR 10      /* 1000Base-T status register */
  20
  21 /* 1000Base-T control register fields */
  22 #define GBCR_ADV_1000HALF         0x100
  23 #define GBCR_ADV_1000FULL         0x200
  24 #define GBCR_PREFER_MASTER        0x400
  25 #define GBCR_MANUAL_AS_MASTER     0x800
  26 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000
  27
  28 /* 1000Base-T status register fields */
  29 #define GBSR_LP_1000HALF  0x400
  30 #define GBSR_LP_1000FULL  0x800
  31 #define GBSR_REMOTE_OK    0x1000
  32 #define GBSR_LOCAL_OK     0x2000
  33 #define GBSR_LOCAL_MASTER 0x4000
  34 #define GBSR_MASTER_FAULT 0x8000
  35
  36 /* Vitesse PHY interrupt status bits. */
  37 #if 0
  38 #define VSC8244_INTR_JABBER          0x0001
  39 #define VSC8244_INTR_POLARITY_CHNG   0x0002
  40 #define VSC8244_INTR_ENG_DETECT_CHNG 0x0010
  41 #define VSC8244_INTR_DOWNSHIFT       0x0020
  42 #define VSC8244_INTR_MDI_XOVER_CHNG  0x0040
  43 #define VSC8244_INTR_FIFO_OVER_UNDER 0x0080
  44 #define VSC8244_INTR_FALSE_CARRIER   0x0100
  45 #define VSC8244_INTR_SYMBOL_ERROR    0x0200
  46 #define VSC8244_INTR_LINK_CHNG       0x0400
  47 #define VSC8244_INTR_AUTONEG_DONE    0x0800
  48 #define VSC8244_INTR_PAGE_RECV       0x1000
  49 #define VSC8244_INTR_DUPLEX_CHNG     0x2000
  50 #define VSC8244_INTR_SPEED_CHNG      0x4000
  51 #define VSC8244_INTR_AUTONEG_ERR     0x8000
  52 #else
  53 //#define VSC8244_INTR_JABBER          0x0001
  54 //#define VSC8244_INTR_POLARITY_CHNG   0x0002
  55 //#define VSC8244_INTR_BIT2            0x0004
  56 //#define VSC8244_INTR_BIT3            0x0008
  57 #define VSC8244_INTR_RX_ERR          0x0001
  58 #define VSC8244_INTR_MASTER_SLAVE    0x0002
  59 #define VSC8244_INTR_CABLE_IMPAIRED  0x0004
  60 #define VSC8244_INTR_FALSE_CARRIER   0x0008
  61 //#define VSC8244_INTR_ENG_DETECT_CHNG 0x0010
  62 //#define VSC8244_INTR_DOWNSHIFT       0x0020
  63 //#define VSC8244_INTR_MDI_XOVER_CHNG  0x0040
  64 //#define VSC8244_INTR_FIFO_OVER_UNDER 0x0080
  65 #define VSC8244_INTR_BIT4            0x0010
  66 #define VSC8244_INTR_FIFO_RX         0x0020
  67 #define VSC8244_INTR_FIFO_OVER_UNDER 0x0040
  68 #define VSC8244_INTR_LOCK_LOST       0x0080
  69 //#define VSC8244_INTR_FALSE_CARRIER   0x0100
  70 //#define VSC8244_INTR_SYMBOL_ERROR    0x0200
  71 //#define VSC8244_INTR_LINK_CHNG       0x0400
  72 //#define VSC8244_INTR_AUTONEG_DONE    0x0800
  73 #define VSC8244_INTR_SYMBOL_ERROR    0x0100
  74 #define VSC8244_INTR_ENG_DETECT_CHNG 0x0200
  75 #define VSC8244_INTR_AUTONEG_DONE    0x0400
  76 #define VSC8244_INTR_AUTONEG_ERR     0x0800
  77 //#define VSC8244_INTR_PAGE_RECV       0x1000
  78 //#define VSC8244_INTR_DUPLEX_CHNG     0x2000
  79 //#define VSC8244_INTR_SPEED_CHNG      0x4000
  80 //#define VSC8244_INTR_AUTONEG_ERR     0x8000
  81 #define VSC8244_INTR_DUPLEX_CHNG     0x1000
  82 #define VSC8244_INTR_LINK_CHNG       0x2000
  83 #define VSC8244_INTR_SPEED_CHNG      0x4000
  84 #define VSC8244_INTR_STATUS          0x8000
  85 #endif
  86
  87
  88 /* Vitesse PHY specific registers. */
  89 #define VSC8244_SPECIFIC_CNTRL_REGISTER               16
  90 #define VSC8244_SPECIFIC_STATUS_REGISTER              0x1c
  91 #define VSC8244_INTERRUPT_ENABLE_REGISTER             0x19
  92 #define VSC8244_INTERRUPT_STATUS_REGISTER             0x1a
  93 #define VSC8244_EXT_PHY_SPECIFIC_CNTRL_REGISTER       20
  94 #define VSC8244_RECV_ERR_CNTR_REGISTER                21
  95 #define VSC8244_RES_REGISTER                          22
  96 #define VSC8244_GLOBAL_STATUS_REGISTER                23
  97 #define VSC8244_LED_CONTROL_REGISTER                  24
  98 #define VSC8244_MANUAL_LED_OVERRIDE_REGISTER          25
  99 #define VSC8244_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER     26
 100 #define VSC8244_EXT_PHY_SPECIFIC_STATUS_REGISTER      27
 101 #define VSC8244_VIRTUAL_CABLE_TESTER_REGISTER         28
 102 #define VSC8244_EXTENDED_ADDR_REGISTER                29
 103 #define VSC8244_EXTENDED_REGISTER                     30
 104
 105 /* PHY specific control register fields */
 106 #define S_PSCR_MDI_XOVER_MODE    5
 107 #define M_PSCR_MDI_XOVER_MODE    0x3
 108 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
 109 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
 110
 111 /* Extended PHY specific control register fields */
 112 #define S_DOWNSHIFT_ENABLE 8
 113 #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
 114
 115 #define S_DOWNSHIFT_CNT    9
 116 #define M_DOWNSHIFT_CNT    0x7
 117 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
 118 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
 119
 120 /* PHY specific status register fields */
 121 #define S_PSSR_JABBER 0
 122 #define V_PSSR_JABBER (1 << S_PSSR_JABBER)
 123
 124 #define S_PSSR_POLARITY 1
 125 #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
 126
 127 #define S_PSSR_RX_PAUSE 2
 128 #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
 129
 130 #define S_PSSR_TX_PAUSE 3
 131 #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
 132
 133 #define S_PSSR_ENERGY_DETECT 4
 134 #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
 135
 136 #define S_PSSR_DOWNSHIFT_STATUS 5
 137 #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
 138
 139 #define S_PSSR_MDI 6
 140 #define V_PSSR_MDI (1 << S_PSSR_MDI)
 141
 142 #define S_PSSR_CABLE_LEN    7
 143 #define M_PSSR_CABLE_LEN    0x7
 144 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
 145 #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
 146
 147 //#define S_PSSR_LINK 10
 148 //#define S_PSSR_LINK 13
 149 #define S_PSSR_LINK 2
 150 #define V_PSSR_LINK (1 << S_PSSR_LINK)
 151
 152 //#define S_PSSR_STATUS_RESOLVED 11
 153 //#define S_PSSR_STATUS_RESOLVED 10
 154 #define S_PSSR_STATUS_RESOLVED 15
 155 #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
 156
 157 #define S_PSSR_PAGE_RECEIVED 12
 158 #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
 159
 160 //#define S_PSSR_DUPLEX 13
 161 //#define S_PSSR_DUPLEX 12
 162 #define S_PSSR_DUPLEX 5
 163 #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
 164
 165 //#define S_PSSR_SPEED    14
 166 //#define S_PSSR_SPEED    14
 167 #define S_PSSR_SPEED    3
 168 #define M_PSSR_SPEED    0x3
 169 #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
 170 #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
 171
 172 #endif