drivers/mtd/spi-nor/cadence-quadspi.c

   1 /*
   2  * Driver for Cadence QSPI Controller
   3  *
   4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/partitions.h>
  30 #include <linux/mtd/spi-nor.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/sched.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/timer.h>
  37
  38 #define CQSPI_NAME                      "cadence-qspi"
  39 #define CQSPI_MAX_CHIPSELECT            16
  40
  41 /* Quirks */
  42 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  43
  44 struct cqspi_st;
  45
  46 struct cqspi_flash_pdata {
  47         struct spi_nor  nor;
  48         struct cqspi_st *cqspi;
  49         u32             clk_rate;
  50         u32             read_delay;
  51         u32             tshsl_ns;
  52         u32             tsd2d_ns;
  53         u32             tchsh_ns;
  54         u32             tslch_ns;
  55         u8              inst_width;
  56         u8              addr_width;
  57         u8              data_width;
  58         u8              cs;
  59         bool            registered;
  60 };
  61
  62 struct cqspi_st {
  63         struct platform_device  *pdev;
  64
  65         struct clk              *clk;
  66         unsigned int            sclk;
  67
  68         void __iomem            *iobase;
  69         void __iomem            *ahb_base;
  70         struct completion       transfer_complete;
  71         struct mutex            bus_mutex;
  72
  73         int                     current_cs;
  74         int                     current_page_size;
  75         int                     current_erase_size;
  76         int                     current_addr_width;
  77         unsigned long           master_ref_clk_hz;
  78         bool                    is_decoded_cs;
  79         u32                     fifo_depth;
  80         u32                     fifo_width;
  81         u32                     trigger_address;
  82         u32                     wr_delay;
  83         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  84 };
  85
  86 /* Operation timeout value */
  87 #define CQSPI_TIMEOUT_MS                        500
  88 #define CQSPI_READ_TIMEOUT_MS                   10
  89
  90 /* Instruction type */
  91 #define CQSPI_INST_TYPE_SINGLE                  0
  92 #define CQSPI_INST_TYPE_DUAL                    1
  93 #define CQSPI_INST_TYPE_QUAD                    2
  94
  95 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  96 #define CQSPI_DUMMY_BYTES_MAX                   4
  97 #define CQSPI_DUMMY_CLKS_MAX                    31
  98
  99 #define CQSPI_STIG_DATA_LEN_MAX                 8
 100
 101 /* Register map */
 102 #define CQSPI_REG_CONFIG                        0x00
 103 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 104 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 105 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 106 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 107 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 108 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 109 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 110 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 111
 112 #define CQSPI_REG_RD_INSTR                      0x04
 113 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 114 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 115 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 116 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 117 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 118 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 119 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 120 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 121 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 122 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 123
 124 #define CQSPI_REG_WR_INSTR                      0x08
 125 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 126 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 127 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 128
 129 #define CQSPI_REG_DELAY                         0x0C
 130 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 131 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 132 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 133 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 134 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 135 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 136 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 137 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 138
 139 #define CQSPI_REG_READCAPTURE                   0x10
 140 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 141 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 142 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 143
 144 #define CQSPI_REG_SIZE                          0x14
 145 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 146 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 147 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 148 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 149 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 150 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 151
 152 #define CQSPI_REG_SRAMPARTITION                 0x18
 153 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 154
 155 #define CQSPI_REG_DMA                           0x20
 156 #define CQSPI_REG_DMA_SINGLE_LSB                0
 157 #define CQSPI_REG_DMA_BURST_LSB                 8
 158 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 159 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 160
 161 #define CQSPI_REG_REMAP                         0x24
 162 #define CQSPI_REG_MODE_BIT                      0x28
 163
 164 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 165 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 166 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 167 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 168 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 169
 170 #define CQSPI_REG_IRQSTATUS                     0x40
 171 #define CQSPI_REG_IRQMASK                       0x44
 172
 173 #define CQSPI_REG_INDIRECTRD                    0x60
 174 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 175 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 176 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 177
 178 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 179 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 180 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 181
 182 #define CQSPI_REG_CMDCTRL                       0x90
 183 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 184 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 185 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 186 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 187 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 188 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 189 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 190 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 191 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 192 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 193 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 194 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 195
 196 #define CQSPI_REG_INDIRECTWR                    0x70
 197 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 198 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 199 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 200
 201 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 202 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 203 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 204
 205 #define CQSPI_REG_CMDADDRESS                    0x94
 206 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 207 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 208 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 209 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 210
 211 /* Interrupt status bits */
 212 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 213 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 214 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 215 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 216 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 217 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 218 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 219 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 220
 221 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 222                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 223                                          CQSPI_REG_IRQ_IND_COMP)
 224
 225 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 226                                          CQSPI_REG_IRQ_WATERMARK        | \
 227                                          CQSPI_REG_IRQ_UNDERFLOW)
 228
 229 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 230
 231 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 232 {
 233         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 234         u32 val;
 235
 236         while (1) {
 237                 val = readl(reg);
 238                 if (clear)
 239                         val = ~val;
 240                 val &= mask;
 241
 242                 if (val == mask)
 243                         return 0;
 244
 245                 if (time_after(jiffies, end))
 246                         return -ETIMEDOUT;
 247         }
 248 }
 249
 250 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 251 {
 252         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 253
 254         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 255 }
 256
 257 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 258 {
 259         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 260
 261         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 262         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 263 }
 264
 265 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 266 {
 267         struct cqspi_st *cqspi = dev;
 268         unsigned int irq_status;
 269
 270         /* Read interrupt status */
 271         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 272
 273         /* Clear interrupt */
 274         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 275
 276         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 277
 278         if (irq_status)
 279                 complete(&cqspi->transfer_complete);
 280
 281         return IRQ_HANDLED;
 282 }
 283
 284 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 285 {
 286         struct cqspi_flash_pdata *f_pdata = nor->priv;
 287         u32 rdreg = 0;
 288
 289         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 290         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 291         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 292
 293         return rdreg;
 294 }
 295
 296 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 297 {
 298         const unsigned int poll_idle_retry = 3;
 299         unsigned int count = 0;
 300         unsigned long timeout;
 301
 302         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 303         while (1) {
 304                 /*
 305                  * Read few times in succession to ensure the controller
 306                  * is indeed idle, that is, the bit does not transition
 307                  * low again.
 308                  */
 309                 if (cqspi_is_idle(cqspi))
 310                         count++;
 311                 else
 312                         count = 0;
 313
 314                 if (count >= poll_idle_retry)
 315                         return 0;
 316
 317                 if (time_after(jiffies, timeout)) {
 318                         /* Timeout, in busy mode. */
 319                         dev_err(&cqspi->pdev->dev,
 320                                 "QSPI is still busy after %dms timeout.\n",
 321                                 CQSPI_TIMEOUT_MS);
 322                         return -ETIMEDOUT;
 323                 }
 324
 325                 cpu_relax();
 326         }
 327 }
 328
 329 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 330 {
 331         void __iomem *reg_base = cqspi->iobase;
 332         int ret;
 333
 334         /* Write the CMDCTRL without start execution. */
 335         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 336         /* Start execute */
 337         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 338         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 339
 340         /* Polling for completion. */
 341         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 342                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 343         if (ret) {
 344                 dev_err(&cqspi->pdev->dev,
 345                         "Flash command execution timed out.\n");
 346                 return ret;
 347         }
 348
 349         /* Polling QSPI idle status. */
 350         return cqspi_wait_idle(cqspi);
 351 }
 352
 353 static int cqspi_command_read(struct spi_nor *nor,
 354                               const u8 *txbuf, const unsigned n_tx,
 355                               u8 *rxbuf, const unsigned n_rx)
 356 {
 357         struct cqspi_flash_pdata *f_pdata = nor->priv;
 358         struct cqspi_st *cqspi = f_pdata->cqspi;
 359         void __iomem *reg_base = cqspi->iobase;
 360         unsigned int rdreg;
 361         unsigned int reg;
 362         unsigned int read_len;
 363         int status;
 364
 365         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 366                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 367                         n_rx, rxbuf);
 368                 return -EINVAL;
 369         }
 370
 371         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 372
 373         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 374         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 375
 376         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 377
 378         /* 0 means 1 byte. */
 379         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 380                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 381         status = cqspi_exec_flash_cmd(cqspi, reg);
 382         if (status)
 383                 return status;
 384
 385         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 386
 387         /* Put the read value into rx_buf */
 388         read_len = (n_rx > 4) ? 4 : n_rx;
 389         memcpy(rxbuf, &reg, read_len);
 390         rxbuf += read_len;
 391
 392         if (n_rx > 4) {
 393                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 394
 395                 read_len = n_rx - read_len;
 396                 memcpy(rxbuf, &reg, read_len);
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 403                                const u8 *txbuf, const unsigned n_tx)
 404 {
 405         struct cqspi_flash_pdata *f_pdata = nor->priv;
 406         struct cqspi_st *cqspi = f_pdata->cqspi;
 407         void __iomem *reg_base = cqspi->iobase;
 408         unsigned int reg;
 409         unsigned int data;
 410         int ret;
 411
 412         if (n_tx > 4 || (n_tx && !txbuf)) {
 413                 dev_err(nor->dev,
 414                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 415                         n_tx, txbuf);
 416                 return -EINVAL;
 417         }
 418
 419         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 420         if (n_tx) {
 421                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 422                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 423                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 424                 data = 0;
 425                 memcpy(&data, txbuf, n_tx);
 426                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 427         }
 428
 429         ret = cqspi_exec_flash_cmd(cqspi, reg);
 430         return ret;
 431 }
 432
 433 static int cqspi_command_write_addr(struct spi_nor *nor,
 434                                     const u8 opcode, const unsigned int addr)
 435 {
 436         struct cqspi_flash_pdata *f_pdata = nor->priv;
 437         struct cqspi_st *cqspi = f_pdata->cqspi;
 438         void __iomem *reg_base = cqspi->iobase;
 439         unsigned int reg;
 440
 441         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 442         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 443         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 444                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 445
 446         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 447
 448         return cqspi_exec_flash_cmd(cqspi, reg);
 449 }
 450
 451 static int cqspi_indirect_read_setup(struct spi_nor *nor,
 452                                      const unsigned int from_addr)
 453 {
 454         struct cqspi_flash_pdata *f_pdata = nor->priv;
 455         struct cqspi_st *cqspi = f_pdata->cqspi;
 456         void __iomem *reg_base = cqspi->iobase;
 457         unsigned int dummy_clk = 0;
 458         unsigned int reg;
 459
 460         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 461
 462         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 463         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 464
 465         /* Setup dummy clock cycles */
 466         dummy_clk = nor->read_dummy;
 467         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 468                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
 469
 470         if (dummy_clk / 8) {
 471                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 472                 /* Set mode bits high to ensure chip doesn't enter XIP */
 473                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 474
 475                 /* Need to subtract the mode byte (8 clocks). */
 476                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 477                         dummy_clk -= 8;
 478
 479                 if (dummy_clk)
 480                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 481                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 482         }
 483
 484         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 485
 486         /* Set address width */
 487         reg = readl(reg_base + CQSPI_REG_SIZE);
 488         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 489         reg |= (nor->addr_width - 1);
 490         writel(reg, reg_base + CQSPI_REG_SIZE);
 491         return 0;
 492 }
 493
 494 static int cqspi_indirect_read_execute(struct spi_nor *nor,
 495                                        u8 *rxbuf, const unsigned n_rx)
 496 {
 497         struct cqspi_flash_pdata *f_pdata = nor->priv;
 498         struct cqspi_st *cqspi = f_pdata->cqspi;
 499         void __iomem *reg_base = cqspi->iobase;
 500         void __iomem *ahb_base = cqspi->ahb_base;
 501         unsigned int remaining = n_rx;
 502         unsigned int bytes_to_read = 0;
 503         int ret = 0;
 504
 505         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 506
 507         /* Clear all interrupts. */
 508         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 509
 510         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 511
 512         reinit_completion(&cqspi->transfer_complete);
 513         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 514                reg_base + CQSPI_REG_INDIRECTRD);
 515
 516         while (remaining > 0) {
 517                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 518                                                   msecs_to_jiffies
 519                                                   (CQSPI_READ_TIMEOUT_MS));
 520
 521                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 522
 523                 if (!ret && bytes_to_read == 0) {
 524                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 525                         ret = -ETIMEDOUT;
 526                         goto failrd;
 527                 }
 528
 529                 while (bytes_to_read != 0) {
 530                         bytes_to_read *= cqspi->fifo_width;
 531                         bytes_to_read = bytes_to_read > remaining ?
 532                                         remaining : bytes_to_read;
 533                         ioread32_rep(ahb_base, rxbuf,
 534                                      DIV_ROUND_UP(bytes_to_read, 4));
 535                         rxbuf += bytes_to_read;
 536                         remaining -= bytes_to_read;
 537                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 538                 }
 539
 540                 if (remaining > 0)
 541                         reinit_completion(&cqspi->transfer_complete);
 542         }
 543
 544         /* Check indirect done status */
 545         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 546                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 547         if (ret) {
 548                 dev_err(nor->dev,
 549                         "Indirect read completion error (%i)\n", ret);
 550                 goto failrd;
 551         }
 552
 553         /* Disable interrupt */
 554         writel(0, reg_base + CQSPI_REG_IRQMASK);
 555
 556         /* Clear indirect completion status */
 557         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 558
 559         return 0;
 560
 561 failrd:
 562         /* Disable interrupt */
 563         writel(0, reg_base + CQSPI_REG_IRQMASK);
 564
 565         /* Cancel the indirect read */
 566         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 567                reg_base + CQSPI_REG_INDIRECTRD);
 568         return ret;
 569 }
 570
 571 static int cqspi_indirect_write_setup(struct spi_nor *nor,
 572                                       const unsigned int to_addr)
 573 {
 574         unsigned int reg;
 575         struct cqspi_flash_pdata *f_pdata = nor->priv;
 576         struct cqspi_st *cqspi = f_pdata->cqspi;
 577         void __iomem *reg_base = cqspi->iobase;
 578
 579         /* Set opcode. */
 580         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 581         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 582         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 583         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 584
 585         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 586
 587         reg = readl(reg_base + CQSPI_REG_SIZE);
 588         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 589         reg |= (nor->addr_width - 1);
 590         writel(reg, reg_base + CQSPI_REG_SIZE);
 591         return 0;
 592 }
 593
 594 static int cqspi_indirect_write_execute(struct spi_nor *nor,
 595                                         const u8 *txbuf, const unsigned n_tx)
 596 {
 597         const unsigned int page_size = nor->page_size;
 598         struct cqspi_flash_pdata *f_pdata = nor->priv;
 599         struct cqspi_st *cqspi = f_pdata->cqspi;
 600         void __iomem *reg_base = cqspi->iobase;
 601         unsigned int remaining = n_tx;
 602         unsigned int write_bytes;
 603         int ret;
 604
 605         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 606
 607         /* Clear all interrupts. */
 608         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 609
 610         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 611
 612         reinit_completion(&cqspi->transfer_complete);
 613         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 614                reg_base + CQSPI_REG_INDIRECTWR);
 615         /*
 616          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 617          * Controller programming sequence, couple of cycles of
 618          * QSPI_REF_CLK delay is required for the above bit to
 619          * be internally synchronized by the QSPI module. Provide 5
 620          * cycles of delay.
 621          */
 622         if (cqspi->wr_delay)
 623                 ndelay(cqspi->wr_delay);
 624
 625         while (remaining > 0) {
 626                 write_bytes = remaining > page_size ? page_size : remaining;
 627                 iowrite32_rep(cqspi->ahb_base, txbuf,
 628                               DIV_ROUND_UP(write_bytes, 4));
 629
 630                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 631                                                   msecs_to_jiffies
 632                                                   (CQSPI_TIMEOUT_MS));
 633                 if (!ret) {
 634                         dev_err(nor->dev, "Indirect write timeout\n");
 635                         ret = -ETIMEDOUT;
 636                         goto failwr;
 637                 }
 638
 639                 txbuf += write_bytes;
 640                 remaining -= write_bytes;
 641
 642                 if (remaining > 0)
 643                         reinit_completion(&cqspi->transfer_complete);
 644         }
 645
 646         /* Check indirect done status */
 647         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 648                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 649         if (ret) {
 650                 dev_err(nor->dev,
 651                         "Indirect write completion error (%i)\n", ret);
 652                 goto failwr;
 653         }
 654
 655         /* Disable interrupt. */
 656         writel(0, reg_base + CQSPI_REG_IRQMASK);
 657
 658         /* Clear indirect completion status */
 659         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 660
 661         cqspi_wait_idle(cqspi);
 662
 663         return 0;
 664
 665 failwr:
 666         /* Disable interrupt. */
 667         writel(0, reg_base + CQSPI_REG_IRQMASK);
 668
 669         /* Cancel the indirect write */
 670         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 671                reg_base + CQSPI_REG_INDIRECTWR);
 672         return ret;
 673 }
 674
 675 static void cqspi_chipselect(struct spi_nor *nor)
 676 {
 677         struct cqspi_flash_pdata *f_pdata = nor->priv;
 678         struct cqspi_st *cqspi = f_pdata->cqspi;
 679         void __iomem *reg_base = cqspi->iobase;
 680         unsigned int chip_select = f_pdata->cs;
 681         unsigned int reg;
 682
 683         reg = readl(reg_base + CQSPI_REG_CONFIG);
 684         if (cqspi->is_decoded_cs) {
 685                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 686         } else {
 687                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 688
 689                 /* Convert CS if without decoder.
 690                  * CS0 to 4b'1110
 691                  * CS1 to 4b'1101
 692                  * CS2 to 4b'1011
 693                  * CS3 to 4b'0111
 694                  */
 695                 chip_select = 0xF & ~(1 << chip_select);
 696         }
 697
 698         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 699                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 700         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 701             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 702         writel(reg, reg_base + CQSPI_REG_CONFIG);
 703 }
 704
 705 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 706 {
 707         struct cqspi_flash_pdata *f_pdata = nor->priv;
 708         struct cqspi_st *cqspi = f_pdata->cqspi;
 709         void __iomem *iobase = cqspi->iobase;
 710         unsigned int reg;
 711
 712         /* configure page size and block size. */
 713         reg = readl(iobase + CQSPI_REG_SIZE);
 714         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 715         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 716         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 717         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 718         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 719         reg |= (nor->addr_width - 1);
 720         writel(reg, iobase + CQSPI_REG_SIZE);
 721
 722         /* configure the chip select */
 723         cqspi_chipselect(nor);
 724
 725         /* Store the new configuration of the controller */
 726         cqspi->current_page_size = nor->page_size;
 727         cqspi->current_erase_size = nor->mtd.erasesize;
 728         cqspi->current_addr_width = nor->addr_width;
 729 }
 730
 731 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 732                                            const unsigned int ns_val)
 733 {
 734         unsigned int ticks;
 735
 736         ticks = ref_clk_hz / 1000;      /* kHz */
 737         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 738
 739         return ticks;
 740 }
 741
 742 static void cqspi_delay(struct spi_nor *nor)
 743 {
 744         struct cqspi_flash_pdata *f_pdata = nor->priv;
 745         struct cqspi_st *cqspi = f_pdata->cqspi;
 746         void __iomem *iobase = cqspi->iobase;
 747         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 748         unsigned int tshsl, tchsh, tslch, tsd2d;
 749         unsigned int reg;
 750         unsigned int tsclk;
 751
 752         /* calculate the number of ref ticks for one sclk tick */
 753         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 754
 755         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 756         /* this particular value must be at least one sclk */
 757         if (tshsl < tsclk)
 758                 tshsl = tsclk;
 759
 760         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 761         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 762         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 763
 764         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 765                << CQSPI_REG_DELAY_TSHSL_LSB;
 766         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 767                 << CQSPI_REG_DELAY_TCHSH_LSB;
 768         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 769                 << CQSPI_REG_DELAY_TSLCH_LSB;
 770         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 771                 << CQSPI_REG_DELAY_TSD2D_LSB;
 772         writel(reg, iobase + CQSPI_REG_DELAY);
 773 }
 774
 775 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 776 {
 777         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 778         void __iomem *reg_base = cqspi->iobase;
 779         u32 reg, div;
 780
 781         /* Recalculate the baudrate divisor based on QSPI specification. */
 782         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 783
 784         reg = readl(reg_base + CQSPI_REG_CONFIG);
 785         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 786         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 787         writel(reg, reg_base + CQSPI_REG_CONFIG);
 788 }
 789
 790 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 791                                    const unsigned int bypass,
 792                                    const unsigned int delay)
 793 {
 794         void __iomem *reg_base = cqspi->iobase;
 795         unsigned int reg;
 796
 797         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 798
 799         if (bypass)
 800                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 801         else
 802                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 803
 804         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 805                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 806
 807         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 808                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 809
 810         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 811 }
 812
 813 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 814 {
 815         void __iomem *reg_base = cqspi->iobase;
 816         unsigned int reg;
 817
 818         reg = readl(reg_base + CQSPI_REG_CONFIG);
 819
 820         if (enable)
 821                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 822         else
 823                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 824
 825         writel(reg, reg_base + CQSPI_REG_CONFIG);
 826 }
 827
 828 static void cqspi_configure(struct spi_nor *nor)
 829 {
 830         struct cqspi_flash_pdata *f_pdata = nor->priv;
 831         struct cqspi_st *cqspi = f_pdata->cqspi;
 832         const unsigned int sclk = f_pdata->clk_rate;
 833         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 834         int switch_ck = (cqspi->sclk != sclk);
 835
 836         if ((cqspi->current_page_size != nor->page_size) ||
 837             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 838             (cqspi->current_addr_width != nor->addr_width))
 839                 switch_cs = 1;
 840
 841         if (switch_cs || switch_ck)
 842                 cqspi_controller_enable(cqspi, 0);
 843
 844         /* Switch chip select. */
 845         if (switch_cs) {
 846                 cqspi->current_cs = f_pdata->cs;
 847                 cqspi_configure_cs_and_sizes(nor);
 848         }
 849
 850         /* Setup baudrate divisor and delays */
 851         if (switch_ck) {
 852                 cqspi->sclk = sclk;
 853                 cqspi_config_baudrate_div(cqspi);
 854                 cqspi_delay(nor);
 855                 cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
 856         }
 857
 858         if (switch_cs || switch_ck)
 859                 cqspi_controller_enable(cqspi, 1);
 860 }
 861
 862 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 863 {
 864         struct cqspi_flash_pdata *f_pdata = nor->priv;
 865
 866         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 867         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 868         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 869
 870         if (read) {
 871                 switch (nor->read_proto) {
 872                 case SNOR_PROTO_1_1_1:
 873                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 874                         break;
 875                 case SNOR_PROTO_1_1_2:
 876                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 877                         break;
 878                 case SNOR_PROTO_1_1_4:
 879                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 880                         break;
 881                 default:
 882                         return -EINVAL;
 883                 }
 884         }
 885
 886         cqspi_configure(nor);
 887
 888         return 0;
 889 }
 890
 891 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 892                            size_t len, const u_char *buf)
 893 {
 894         int ret;
 895
 896         ret = cqspi_set_protocol(nor, 0);
 897         if (ret)
 898                 return ret;
 899
 900         ret = cqspi_indirect_write_setup(nor, to);
 901         if (ret)
 902                 return ret;
 903
 904         ret = cqspi_indirect_write_execute(nor, buf, len);
 905         if (ret)
 906                 return ret;
 907
 908         return len;
 909 }
 910
 911 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
 912                           size_t len, u_char *buf)
 913 {
 914         int ret;
 915
 916         ret = cqspi_set_protocol(nor, 1);
 917         if (ret)
 918                 return ret;
 919
 920         ret = cqspi_indirect_read_setup(nor, from);
 921         if (ret)
 922                 return ret;
 923
 924         ret = cqspi_indirect_read_execute(nor, buf, len);
 925         if (ret)
 926                 return ret;
 927
 928         return len;
 929 }
 930
 931 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
 932 {
 933         int ret;
 934
 935         ret = cqspi_set_protocol(nor, 0);
 936         if (ret)
 937                 return ret;
 938
 939         /* Send write enable, then erase commands. */
 940         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 941         if (ret)
 942                 return ret;
 943
 944         /* Set up command buffer. */
 945         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
 946         if (ret)
 947                 return ret;
 948
 949         return 0;
 950 }
 951
 952 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
 953 {
 954         struct cqspi_flash_pdata *f_pdata = nor->priv;
 955         struct cqspi_st *cqspi = f_pdata->cqspi;
 956
 957         mutex_lock(&cqspi->bus_mutex);
 958
 959         return 0;
 960 }
 961
 962 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
 963 {
 964         struct cqspi_flash_pdata *f_pdata = nor->priv;
 965         struct cqspi_st *cqspi = f_pdata->cqspi;
 966
 967         mutex_unlock(&cqspi->bus_mutex);
 968 }
 969
 970 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 971 {
 972         int ret;
 973
 974         ret = cqspi_set_protocol(nor, 0);
 975         if (!ret)
 976                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
 977
 978         return ret;
 979 }
 980
 981 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 982 {
 983         int ret;
 984
 985         ret = cqspi_set_protocol(nor, 0);
 986         if (!ret)
 987                 ret = cqspi_command_write(nor, opcode, buf, len);
 988
 989         return ret;
 990 }
 991
 992 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
 993                                     struct cqspi_flash_pdata *f_pdata,
 994                                     struct device_node *np)
 995 {
 996         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
 997                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
 998                 return -ENXIO;
 999         }
1000
1001         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1002                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1003                 return -ENXIO;
1004         }
1005
1006         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1007                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1008                 return -ENXIO;
1009         }
1010
1011         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1012                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1013                 return -ENXIO;
1014         }
1015
1016         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1017                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1018                 return -ENXIO;
1019         }
1020
1021         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1022                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1023                 return -ENXIO;
1024         }
1025
1026         return 0;
1027 }
1028
1029 static int cqspi_of_get_pdata(struct platform_device *pdev)
1030 {
1031         struct device_node *np = pdev->dev.of_node;
1032         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1033
1034         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1035
1036         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1037                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1038                 return -ENXIO;
1039         }
1040
1041         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1042                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1043                 return -ENXIO;
1044         }
1045
1046         if (of_property_read_u32(np, "cdns,trigger-address",
1047                                  &cqspi->trigger_address)) {
1048                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1049                 return -ENXIO;
1050         }
1051
1052         return 0;
1053 }
1054
1055 static void cqspi_controller_init(struct cqspi_st *cqspi)
1056 {
1057         cqspi_controller_enable(cqspi, 0);
1058
1059         /* Configure the remap address register, no remap */
1060         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1061
1062         /* Disable all interrupts. */
1063         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1064
1065         /* Configure the SRAM split to 1:1 . */
1066         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1067
1068         /* Load indirect trigger address. */
1069         writel(cqspi->trigger_address,
1070                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1071
1072         /* Program read watermark -- 1/2 of the FIFO. */
1073         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1074                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1075         /* Program write watermark -- 1/8 of the FIFO. */
1076         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1077                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1078
1079         cqspi_controller_enable(cqspi, 1);
1080 }
1081
1082 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1083 {
1084         const struct spi_nor_hwcaps hwcaps = {
1085                 .mask = SNOR_HWCAPS_READ |
1086                         SNOR_HWCAPS_READ_FAST |
1087                         SNOR_HWCAPS_READ_1_1_2 |
1088                         SNOR_HWCAPS_READ_1_1_4 |
1089                         SNOR_HWCAPS_PP,
1090         };
1091         struct platform_device *pdev = cqspi->pdev;
1092         struct device *dev = &pdev->dev;
1093         struct cqspi_flash_pdata *f_pdata;
1094         struct spi_nor *nor;
1095         struct mtd_info *mtd;
1096         unsigned int cs;
1097         int i, ret;
1098
1099         /* Get flash device data */
1100         for_each_available_child_of_node(dev->of_node, np) {
1101                 ret = of_property_read_u32(np, "reg", &cs);
1102                 if (ret) {
1103                         dev_err(dev, "Couldn't determine chip select.\n");
1104                         goto err;
1105                 }
1106
1107                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1108                         ret = -EINVAL;
1109                         dev_err(dev, "Chip select %d out of range.\n", cs);
1110                         goto err;
1111                 }
1112
1113                 f_pdata = &cqspi->f_pdata[cs];
1114                 f_pdata->cqspi = cqspi;
1115                 f_pdata->cs = cs;
1116
1117                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1118                 if (ret)
1119                         goto err;
1120
1121                 nor = &f_pdata->nor;
1122                 mtd = &nor->mtd;
1123
1124                 mtd->priv = nor;
1125
1126                 nor->dev = dev;
1127                 spi_nor_set_flash_node(nor, np);
1128                 nor->priv = f_pdata;
1129
1130                 nor->read_reg = cqspi_read_reg;
1131                 nor->write_reg = cqspi_write_reg;
1132                 nor->read = cqspi_read;
1133                 nor->write = cqspi_write;
1134                 nor->erase = cqspi_erase;
1135                 nor->prepare = cqspi_prep;
1136                 nor->unprepare = cqspi_unprep;
1137
1138                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1139                                            dev_name(dev), cs);
1140                 if (!mtd->name) {
1141                         ret = -ENOMEM;
1142                         goto err;
1143                 }
1144
1145                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1146                 if (ret)
1147                         goto err;
1148
1149                 ret = mtd_device_register(mtd, NULL, 0);
1150                 if (ret)
1151                         goto err;
1152
1153                 f_pdata->registered = true;
1154         }
1155
1156         return 0;
1157
1158 err:
1159         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1160                 if (cqspi->f_pdata[i].registered)
1161                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1162         return ret;
1163 }
1164
1165 static int cqspi_probe(struct platform_device *pdev)
1166 {
1167         struct device_node *np = pdev->dev.of_node;
1168         struct device *dev = &pdev->dev;
1169         struct cqspi_st *cqspi;
1170         struct resource *res;
1171         struct resource *res_ahb;
1172         unsigned long data;
1173         int ret;
1174         int irq;
1175
1176         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1177         if (!cqspi)
1178                 return -ENOMEM;
1179
1180         mutex_init(&cqspi->bus_mutex);
1181         cqspi->pdev = pdev;
1182         platform_set_drvdata(pdev, cqspi);
1183
1184         /* Obtain configuration from OF. */
1185         ret = cqspi_of_get_pdata(pdev);
1186         if (ret) {
1187                 dev_err(dev, "Cannot get mandatory OF data.\n");
1188                 return -ENODEV;
1189         }
1190
1191         /* Obtain QSPI clock. */
1192         cqspi->clk = devm_clk_get(dev, NULL);
1193         if (IS_ERR(cqspi->clk)) {
1194                 dev_err(dev, "Cannot claim QSPI clock.\n");
1195                 return PTR_ERR(cqspi->clk);
1196         }
1197
1198         /* Obtain and remap controller address. */
1199         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200         cqspi->iobase = devm_ioremap_resource(dev, res);
1201         if (IS_ERR(cqspi->iobase)) {
1202                 dev_err(dev, "Cannot remap controller address.\n");
1203                 return PTR_ERR(cqspi->iobase);
1204         }
1205
1206         /* Obtain and remap AHB address. */
1207         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1208         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1209         if (IS_ERR(cqspi->ahb_base)) {
1210                 dev_err(dev, "Cannot remap AHB address.\n");
1211                 return PTR_ERR(cqspi->ahb_base);
1212         }
1213
1214         init_completion(&cqspi->transfer_complete);
1215
1216         /* Obtain IRQ line. */
1217         irq = platform_get_irq(pdev, 0);
1218         if (irq < 0) {
1219                 dev_err(dev, "Cannot obtain IRQ.\n");
1220                 return -ENXIO;
1221         }
1222
1223         ret = clk_prepare_enable(cqspi->clk);
1224         if (ret) {
1225                 dev_err(dev, "Cannot enable QSPI clock.\n");
1226                 return ret;
1227         }
1228
1229         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1230         data  = (unsigned long)of_device_get_match_data(dev);
1231         if (data & CQSPI_NEEDS_WR_DELAY)
1232                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1233                                                    cqspi->master_ref_clk_hz);
1234
1235         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1236                                pdev->name, cqspi);
1237         if (ret) {
1238                 dev_err(dev, "Cannot request IRQ.\n");
1239                 goto probe_irq_failed;
1240         }
1241
1242         cqspi_wait_idle(cqspi);
1243         cqspi_controller_init(cqspi);
1244         cqspi->current_cs = -1;
1245         cqspi->sclk = 0;
1246
1247         ret = cqspi_setup_flash(cqspi, np);
1248         if (ret) {
1249                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1250                 goto probe_setup_failed;
1251         }
1252
1253         return ret;
1254 probe_irq_failed:
1255         cqspi_controller_enable(cqspi, 0);
1256 probe_setup_failed:
1257         clk_disable_unprepare(cqspi->clk);
1258         return ret;
1259 }
1260
1261 static int cqspi_remove(struct platform_device *pdev)
1262 {
1263         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1264         int i;
1265
1266         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1267                 if (cqspi->f_pdata[i].registered)
1268                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1269
1270         cqspi_controller_enable(cqspi, 0);
1271
1272         clk_disable_unprepare(cqspi->clk);
1273
1274         return 0;
1275 }
1276
1277 #ifdef CONFIG_PM_SLEEP
1278 static int cqspi_suspend(struct device *dev)
1279 {
1280         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1281
1282         cqspi_controller_enable(cqspi, 0);
1283         return 0;
1284 }
1285
1286 static int cqspi_resume(struct device *dev)
1287 {
1288         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1289
1290         cqspi_controller_enable(cqspi, 1);
1291         return 0;
1292 }
1293
1294 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1295         .suspend = cqspi_suspend,
1296         .resume = cqspi_resume,
1297 };
1298
1299 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1300 #else
1301 #define CQSPI_DEV_PM_OPS        NULL
1302 #endif
1303
1304 static const struct of_device_id cqspi_dt_ids[] = {
1305         {
1306                 .compatible = "cdns,qspi-nor",
1307                 .data = (void *)0,
1308         },
1309         {
1310                 .compatible = "ti,k2g-qspi",
1311                 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1312         },
1313         { /* end of table */ }
1314 };
1315
1316 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1317
1318 static struct platform_driver cqspi_platform_driver = {
1319         .probe = cqspi_probe,
1320         .remove = cqspi_remove,
1321         .driver = {
1322                 .name = CQSPI_NAME,
1323                 .pm = CQSPI_DEV_PM_OPS,
1324                 .of_match_table = cqspi_dt_ids,
1325         },
1326 };
1327
1328 module_platform_driver(cqspi_platform_driver);
1329
1330 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1331 MODULE_LICENSE("GPL v2");
1332 MODULE_ALIAS("platform:" CQSPI_NAME);
1333 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1334 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");