1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
6 * https://github.com/yuq/sunxi-nfc-mtd
7 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
9 * https://github.com/hno/Allwinner-Info
10 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
12 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
13 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
16 #include <linux/dma-mapping.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/platform_device.h>
22 #include <linux/of_device.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/dmaengine.h>
29 #include <linux/interrupt.h>
30 #include <linux/iopoll.h>
31 #include <linux/reset.h>
33 #define NFC_REG_CTL 0x0000
34 #define NFC_REG_ST 0x0004
35 #define NFC_REG_INT 0x0008
36 #define NFC_REG_TIMING_CTL 0x000C
37 #define NFC_REG_TIMING_CFG 0x0010
38 #define NFC_REG_ADDR_LOW 0x0014
39 #define NFC_REG_ADDR_HIGH 0x0018
40 #define NFC_REG_SECTOR_NUM 0x001C
41 #define NFC_REG_CNT 0x0020
42 #define NFC_REG_CMD 0x0024
43 #define NFC_REG_RCMD_SET 0x0028
44 #define NFC_REG_WCMD_SET 0x002C
45 #define NFC_REG_IO_DATA 0x0030
46 #define NFC_REG_ECC_CTL 0x0034
47 #define NFC_REG_ECC_ST 0x0038
48 #define NFC_REG_DEBUG 0x003C
49 #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
50 #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
51 #define NFC_REG_SPARE_AREA 0x00A0
52 #define NFC_REG_PAT_ID 0x00A4
53 #define NFC_RAM0_BASE 0x0400
54 #define NFC_RAM1_BASE 0x0800
56 /* define bit use in NFC_CTL */
58 #define NFC_RESET BIT(1)
59 #define NFC_BUS_WIDTH_MSK BIT(2)
60 #define NFC_BUS_WIDTH_8 (0 << 2)
61 #define NFC_BUS_WIDTH_16 (1 << 2)
62 #define NFC_RB_SEL_MSK BIT(3)
63 #define NFC_RB_SEL(x) ((x) << 3)
64 #define NFC_CE_SEL_MSK GENMASK(26, 24)
65 #define NFC_CE_SEL(x) ((x) << 24)
66 #define NFC_CE_CTL BIT(6)
67 #define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
68 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
69 #define NFC_SAM BIT(12)
70 #define NFC_RAM_METHOD BIT(14)
71 #define NFC_DEBUG_CTL BIT(31)
73 /* define bit use in NFC_ST */
74 #define NFC_RB_B2R BIT(0)
75 #define NFC_CMD_INT_FLAG BIT(1)
76 #define NFC_DMA_INT_FLAG BIT(2)
77 #define NFC_CMD_FIFO_STATUS BIT(3)
78 #define NFC_STA BIT(4)
79 #define NFC_NATCH_INT_FLAG BIT(5)
80 #define NFC_RB_STATE(x) BIT(x + 8)
82 /* define bit use in NFC_INT */
83 #define NFC_B2R_INT_ENABLE BIT(0)
84 #define NFC_CMD_INT_ENABLE BIT(1)
85 #define NFC_DMA_INT_ENABLE BIT(2)
86 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
87 NFC_CMD_INT_ENABLE | \
90 /* define bit use in NFC_TIMING_CTL */
91 #define NFC_TIMING_CTL_EDO BIT(8)
93 /* define NFC_TIMING_CFG register layout */
94 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
95 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
96 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
97 (((tCAD) & 0x7) << 8))
99 /* define bit use in NFC_CMD */
100 #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
101 #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
102 #define NFC_CMD(x) (x)
103 #define NFC_ADR_NUM_MSK GENMASK(18, 16)
104 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
105 #define NFC_SEND_ADR BIT(19)
106 #define NFC_ACCESS_DIR BIT(20)
107 #define NFC_DATA_TRANS BIT(21)
108 #define NFC_SEND_CMD1 BIT(22)
109 #define NFC_WAIT_FLAG BIT(23)
110 #define NFC_SEND_CMD2 BIT(24)
111 #define NFC_SEQ BIT(25)
112 #define NFC_DATA_SWAP_METHOD BIT(26)
113 #define NFC_ROW_AUTO_INC BIT(27)
114 #define NFC_SEND_CMD3 BIT(28)
115 #define NFC_SEND_CMD4 BIT(29)
116 #define NFC_CMD_TYPE_MSK GENMASK(31, 30)
117 #define NFC_NORMAL_OP (0 << 30)
118 #define NFC_ECC_OP (1 << 30)
119 #define NFC_PAGE_OP (2U << 30)
121 /* define bit use in NFC_RCMD_SET */
122 #define NFC_READ_CMD_MSK GENMASK(7, 0)
123 #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
124 #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
126 /* define bit use in NFC_WCMD_SET */
127 #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
128 #define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)
129 #define NFC_READ_CMD0_MSK GENMASK(23, 16)
130 #define NFC_READ_CMD1_MSK GENMASK(31, 24)
132 /* define bit use in NFC_ECC_CTL */
133 #define NFC_ECC_EN BIT(0)
134 #define NFC_ECC_PIPELINE BIT(3)
135 #define NFC_ECC_EXCEPTION BIT(4)
136 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
137 #define NFC_ECC_BLOCK_512 BIT(5)
138 #define NFC_RANDOM_EN BIT(9)
139 #define NFC_RANDOM_DIRECTION BIT(10)
140 #define NFC_ECC_MODE_MSK GENMASK(15, 12)
141 #define NFC_ECC_MODE(x) ((x) << 12)
142 #define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
143 #define NFC_RANDOM_SEED(x) ((x) << 16)
145 /* define bit use in NFC_ECC_ST */
146 #define NFC_ECC_ERR(x) BIT(x)
147 #define NFC_ECC_ERR_MSK GENMASK(15, 0)
148 #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
149 #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff)
151 #define NFC_DEFAULT_TIMEOUT_MS 1000
153 #define NFC_SRAM_SIZE 1024
158 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
160 * @cs: the NAND CS id used to communicate with a NAND Chip
161 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
163 struct sunxi_nand_chip_sel {
169 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
171 * @mode: the sunxi ECC mode field deduced from ECC requirements
173 struct sunxi_nand_hw_ecc {
178 * struct sunxi_nand_chip - stores NAND chip device related information
180 * @node: used to store NAND chips into a list
181 * @nand: base NAND chip structure
182 * @clk_rate: clk_rate required for this NAND chip
183 * @timing_cfg: TIMING_CFG register value for this NAND chip
184 * @timing_ctl: TIMING_CTL register value for this NAND chip
185 * @nsels: number of CS lines required by the NAND chip
186 * @sels: array of CS lines descriptions
188 struct sunxi_nand_chip {
189 struct list_head node;
190 struct nand_chip nand;
191 unsigned long clk_rate;
195 struct sunxi_nand_chip_sel sels[0];
198 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
200 return container_of(nand, struct sunxi_nand_chip, nand);
204 * struct sunxi_nfc - stores sunxi NAND controller information
206 * @controller: base controller structure
207 * @dev: parent device (used to print error messages)
208 * @regs: NAND controller registers
209 * @ahb_clk: NAND controller AHB clock
210 * @mod_clk: NAND controller mod clock
211 * @reset: NAND controller reset line
212 * @assigned_cs: bitmask describing already assigned CS lines
213 * @clk_rate: NAND controller current clock rate
214 * @chips: a list containing all the NAND chips attached to this NAND
216 * @complete: a completion object used to wait for NAND controller events
217 * @dmac: the DMA channel attached to the NAND controller
220 struct nand_controller controller;
225 struct reset_control *reset;
226 unsigned long assigned_cs;
227 unsigned long clk_rate;
228 struct list_head chips;
229 struct completion complete;
230 struct dma_chan *dmac;
233 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_controller *ctrl)
235 return container_of(ctrl, struct sunxi_nfc, controller);
238 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
240 struct sunxi_nfc *nfc = dev_id;
241 u32 st = readl(nfc->regs + NFC_REG_ST);
242 u32 ien = readl(nfc->regs + NFC_REG_INT);
247 if ((ien & st) == ien)
248 complete(&nfc->complete);
250 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
251 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
256 static int sunxi_nfc_wait_events(struct sunxi_nfc *nfc, u32 events,
257 bool use_polling, unsigned int timeout_ms)
261 if (events & ~NFC_INT_MASK)
265 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
268 init_completion(&nfc->complete);
270 writel(events, nfc->regs + NFC_REG_INT);
272 ret = wait_for_completion_timeout(&nfc->complete,
273 msecs_to_jiffies(timeout_ms));
279 writel(0, nfc->regs + NFC_REG_INT);
283 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
284 (status & events) == events, 1,
288 writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
291 dev_err(nfc->dev, "wait interrupt timedout\n");
296 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
301 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
302 !(status & NFC_CMD_FIFO_STATUS), 1,
303 NFC_DEFAULT_TIMEOUT_MS * 1000);
305 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
310 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
315 writel(0, nfc->regs + NFC_REG_ECC_CTL);
316 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
318 ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl,
319 !(ctl & NFC_RESET), 1,
320 NFC_DEFAULT_TIMEOUT_MS * 1000);
322 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
327 static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
328 int chunksize, int nchunks,
329 enum dma_data_direction ddir,
330 struct scatterlist *sg)
332 struct dma_async_tx_descriptor *dmad;
333 enum dma_transfer_direction tdir;
337 if (ddir == DMA_FROM_DEVICE)
338 tdir = DMA_DEV_TO_MEM;
340 tdir = DMA_MEM_TO_DEV;
342 sg_init_one(sg, buf, nchunks * chunksize);
343 ret = dma_map_sg(nfc->dev, sg, 1, ddir);
347 dmad = dmaengine_prep_slave_sg(nfc->dmac, sg, 1, tdir, DMA_CTRL_ACK);
353 writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
354 nfc->regs + NFC_REG_CTL);
355 writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
356 writel(chunksize, nfc->regs + NFC_REG_CNT);
357 dmat = dmaengine_submit(dmad);
359 ret = dma_submit_error(dmat);
361 goto err_clr_dma_flag;
366 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
367 nfc->regs + NFC_REG_CTL);
370 dma_unmap_sg(nfc->dev, sg, 1, ddir);
374 static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc,
375 enum dma_data_direction ddir,
376 struct scatterlist *sg)
378 dma_unmap_sg(nfc->dev, sg, 1, ddir);
379 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
380 nfc->regs + NFC_REG_CTL);
383 static void sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs)
385 struct mtd_info *mtd = nand_to_mtd(nand);
386 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
387 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
388 struct sunxi_nand_chip_sel *sel;
391 if (cs > 0 && cs >= sunxi_nand->nsels)
394 ctl = readl(nfc->regs + NFC_REG_CTL) &
395 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
397 sel = &sunxi_nand->sels[cs];
398 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN | NFC_PAGE_SHIFT(nand->page_shift);
400 ctl |= NFC_RB_SEL(sel->rb);
402 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
404 if (nfc->clk_rate != sunxi_nand->clk_rate) {
405 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
406 nfc->clk_rate = sunxi_nand->clk_rate;
409 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
410 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
411 writel(ctl, nfc->regs + NFC_REG_CTL);
414 static void sunxi_nfc_read_buf(struct nand_chip *nand, uint8_t *buf, int len)
416 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
417 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
426 cnt = min(len - offs, NFC_SRAM_SIZE);
428 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
432 writel(cnt, nfc->regs + NFC_REG_CNT);
433 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
434 writel(tmp, nfc->regs + NFC_REG_CMD);
436 /* Arbitrary limit for polling mode */
440 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
445 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
451 static void sunxi_nfc_write_buf(struct nand_chip *nand, const uint8_t *buf,
454 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
455 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
464 cnt = min(len - offs, NFC_SRAM_SIZE);
466 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
470 writel(cnt, nfc->regs + NFC_REG_CNT);
471 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
472 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
474 writel(tmp, nfc->regs + NFC_REG_CMD);
476 /* Arbitrary limit for polling mode */
480 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
488 /* These seed values have been extracted from Allwinner's BSP */
489 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
490 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
491 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
492 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
493 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
494 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
495 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
496 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
497 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
498 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
499 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
500 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
501 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
502 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
503 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
504 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
505 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
509 * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
510 * have been generated using
511 * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
512 * the randomizer engine does internally before de/scrambling OOB data.
514 * Those tables are statically defined to avoid calculating randomizer state
517 static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
518 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
519 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
520 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
521 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
522 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
523 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
524 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
525 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
526 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
527 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
528 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
529 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
530 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
531 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
532 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
533 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
536 static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
537 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
538 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
539 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
540 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
541 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
542 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
543 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
544 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
545 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
546 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
547 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
548 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
549 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
550 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
551 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
552 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
555 static u16 sunxi_nfc_randomizer_step(u16 state, int count)
560 * This loop is just a simple implementation of a Fibonacci LFSR using
561 * the x16 + x15 + 1 polynomial.
564 state = ((state >> 1) |
565 (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
570 static u16 sunxi_nfc_randomizer_state(struct nand_chip *nand, int page,
573 struct mtd_info *mtd = nand_to_mtd(nand);
574 const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
575 int mod = mtd_div_by_ws(mtd->erasesize, mtd);
577 if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
578 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
581 if (mtd->ecc_step_size == 512)
582 seeds = sunxi_nfc_randomizer_ecc512_seeds;
584 seeds = sunxi_nfc_randomizer_ecc1024_seeds;
587 return seeds[page % mod];
590 static void sunxi_nfc_randomizer_config(struct nand_chip *nand, int page,
593 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
594 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
597 if (!(nand->options & NAND_NEED_SCRAMBLING))
600 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
601 state = sunxi_nfc_randomizer_state(nand, page, ecc);
602 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
603 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
606 static void sunxi_nfc_randomizer_enable(struct nand_chip *nand)
608 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
610 if (!(nand->options & NAND_NEED_SCRAMBLING))
613 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
614 nfc->regs + NFC_REG_ECC_CTL);
617 static void sunxi_nfc_randomizer_disable(struct nand_chip *nand)
619 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
621 if (!(nand->options & NAND_NEED_SCRAMBLING))
624 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
625 nfc->regs + NFC_REG_ECC_CTL);
628 static void sunxi_nfc_randomize_bbm(struct nand_chip *nand, int page, u8 *bbm)
630 u16 state = sunxi_nfc_randomizer_state(nand, page, true);
633 bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
636 static void sunxi_nfc_randomizer_write_buf(struct nand_chip *nand,
637 const uint8_t *buf, int len,
640 sunxi_nfc_randomizer_config(nand, page, ecc);
641 sunxi_nfc_randomizer_enable(nand);
642 sunxi_nfc_write_buf(nand, buf, len);
643 sunxi_nfc_randomizer_disable(nand);
646 static void sunxi_nfc_randomizer_read_buf(struct nand_chip *nand, uint8_t *buf,
647 int len, bool ecc, int page)
649 sunxi_nfc_randomizer_config(nand, page, ecc);
650 sunxi_nfc_randomizer_enable(nand);
651 sunxi_nfc_read_buf(nand, buf, len);
652 sunxi_nfc_randomizer_disable(nand);
655 static void sunxi_nfc_hw_ecc_enable(struct nand_chip *nand)
657 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
658 struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
661 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
662 ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
663 NFC_ECC_BLOCK_SIZE_MSK);
664 ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION |
667 if (nand->ecc.size == 512)
668 ecc_ctl |= NFC_ECC_BLOCK_512;
670 writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
673 static void sunxi_nfc_hw_ecc_disable(struct nand_chip *nand)
675 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
677 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
678 nfc->regs + NFC_REG_ECC_CTL);
681 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
684 buf[1] = user_data >> 8;
685 buf[2] = user_data >> 16;
686 buf[3] = user_data >> 24;
689 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
691 return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
694 static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8 *oob,
695 int step, bool bbm, int page)
697 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
699 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
702 /* De-randomize the Bad Block Marker. */
703 if (bbm && (nand->options & NAND_NEED_SCRAMBLING))
704 sunxi_nfc_randomize_bbm(nand, page, oob);
707 static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand,
708 const u8 *oob, int step,
711 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
714 /* Randomize the Bad Block Marker. */
715 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) {
716 memcpy(user_data, oob, sizeof(user_data));
717 sunxi_nfc_randomize_bbm(nand, page, user_data);
721 writel(sunxi_nfc_buf_to_user_data(oob),
722 nfc->regs + NFC_REG_USER_DATA(step));
725 static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand,
726 unsigned int *max_bitflips, int ret)
728 struct mtd_info *mtd = nand_to_mtd(nand);
731 mtd->ecc_stats.failed++;
733 mtd->ecc_stats.corrected += ret;
734 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
738 static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *oob,
739 int step, u32 status, bool *erased)
741 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
742 struct nand_ecc_ctrl *ecc = &nand->ecc;
747 if (status & NFC_ECC_ERR(step))
750 if (status & NFC_ECC_PAT_FOUND(step)) {
753 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) {
761 memset(data, pattern, ecc->size);
764 memset(oob, pattern, ecc->bytes + 4);
769 tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step));
771 return NFC_ECC_ERR_CNT(step, tmp);
774 static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip *nand,
775 u8 *data, int data_off,
776 u8 *oob, int oob_off,
778 unsigned int *max_bitflips,
779 bool bbm, bool oob_required, int page)
781 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
782 struct nand_ecc_ctrl *ecc = &nand->ecc;
787 if (*cur_off != data_off)
788 nand_change_read_column_op(nand, data_off, NULL, 0, false);
790 sunxi_nfc_randomizer_read_buf(nand, NULL, ecc->size, false, page);
792 if (data_off + ecc->size != oob_off)
793 nand_change_read_column_op(nand, oob_off, NULL, 0, false);
795 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
799 sunxi_nfc_randomizer_enable(nand);
800 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
801 nfc->regs + NFC_REG_CMD);
803 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
804 sunxi_nfc_randomizer_disable(nand);
808 *cur_off = oob_off + ecc->bytes + 4;
810 ret = sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0,
811 readl(nfc->regs + NFC_REG_ECC_ST),
818 * Re-read the data with the randomizer disabled to identify
819 * bitflips in erased pages.
821 if (nand->options & NAND_NEED_SCRAMBLING)
822 nand_change_read_column_op(nand, data_off, data,
825 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE,
828 nand_change_read_column_op(nand, oob_off, oob, ecc->bytes + 4,
831 ret = nand_check_erased_ecc_chunk(data, ecc->size,
833 NULL, 0, ecc->strength);
837 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
840 nand_change_read_column_op(nand, oob_off, NULL, 0,
842 sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + 4,
845 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0,
850 sunxi_nfc_hw_ecc_update_stats(nand, max_bitflips, ret);
855 static void sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip *nand,
856 u8 *oob, int *cur_off,
857 bool randomize, int page)
859 struct mtd_info *mtd = nand_to_mtd(nand);
860 struct nand_ecc_ctrl *ecc = &nand->ecc;
861 int offset = ((ecc->bytes + 4) * ecc->steps);
862 int len = mtd->oobsize - offset;
867 if (!cur_off || *cur_off != offset)
868 nand_change_read_column_op(nand, mtd->writesize, NULL, 0,
872 sunxi_nfc_read_buf(nand, oob + offset, len);
874 sunxi_nfc_randomizer_read_buf(nand, oob + offset, len,
878 *cur_off = mtd->oobsize + mtd->writesize;
881 static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf,
882 int oob_required, int page,
885 bool randomized = nand->options & NAND_NEED_SCRAMBLING;
886 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
887 struct mtd_info *mtd = nand_to_mtd(nand);
888 struct nand_ecc_ctrl *ecc = &nand->ecc;
889 unsigned int max_bitflips = 0;
890 int ret, i, raw_mode = 0;
891 struct scatterlist sg;
894 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
898 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks,
899 DMA_FROM_DEVICE, &sg);
903 sunxi_nfc_hw_ecc_enable(nand);
904 sunxi_nfc_randomizer_config(nand, page, false);
905 sunxi_nfc_randomizer_enable(nand);
907 writel((NAND_CMD_RNDOUTSTART << 16) | (NAND_CMD_RNDOUT << 8) |
908 NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
910 dma_async_issue_pending(nfc->dmac);
912 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD | NFC_DATA_TRANS,
913 nfc->regs + NFC_REG_CMD);
915 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
917 dmaengine_terminate_all(nfc->dmac);
919 sunxi_nfc_randomizer_disable(nand);
920 sunxi_nfc_hw_ecc_disable(nand);
922 sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg);
927 status = readl(nfc->regs + NFC_REG_ECC_ST);
929 for (i = 0; i < nchunks; i++) {
930 int data_off = i * ecc->size;
931 int oob_off = i * (ecc->bytes + 4);
932 u8 *data = buf + data_off;
933 u8 *oob = nand->oob_poi + oob_off;
936 ret = sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL,
937 oob_required ? oob : NULL,
940 /* ECC errors are handled in the second loop. */
944 if (oob_required && !erased) {
945 /* TODO: use DMA to retrieve OOB */
946 nand_change_read_column_op(nand,
947 mtd->writesize + oob_off,
948 oob, ecc->bytes + 4, false);
950 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i,
957 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
960 if (status & NFC_ECC_ERR_MSK) {
961 for (i = 0; i < nchunks; i++) {
962 int data_off = i * ecc->size;
963 int oob_off = i * (ecc->bytes + 4);
964 u8 *data = buf + data_off;
965 u8 *oob = nand->oob_poi + oob_off;
967 if (!(status & NFC_ECC_ERR(i)))
971 * Re-read the data with the randomizer disabled to
972 * identify bitflips in erased pages.
973 * TODO: use DMA to read page in raw mode
976 nand_change_read_column_op(nand, data_off,
980 /* TODO: use DMA to retrieve OOB */
981 nand_change_read_column_op(nand,
982 mtd->writesize + oob_off,
983 oob, ecc->bytes + 4, false);
985 ret = nand_check_erased_ecc_chunk(data, ecc->size,
992 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
997 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi,
1001 return max_bitflips;
1004 static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand,
1005 const u8 *data, int data_off,
1006 const u8 *oob, int oob_off,
1007 int *cur_off, bool bbm,
1010 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1011 struct nand_ecc_ctrl *ecc = &nand->ecc;
1014 if (data_off != *cur_off)
1015 nand_change_write_column_op(nand, data_off, NULL, 0, false);
1017 sunxi_nfc_randomizer_write_buf(nand, data, ecc->size, false, page);
1019 if (data_off + ecc->size != oob_off)
1020 nand_change_write_column_op(nand, oob_off, NULL, 0, false);
1022 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1026 sunxi_nfc_randomizer_enable(nand);
1027 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page);
1029 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
1030 NFC_ACCESS_DIR | NFC_ECC_OP,
1031 nfc->regs + NFC_REG_CMD);
1033 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
1034 sunxi_nfc_randomizer_disable(nand);
1038 *cur_off = oob_off + ecc->bytes + 4;
1043 static void sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip *nand,
1044 u8 *oob, int *cur_off,
1047 struct mtd_info *mtd = nand_to_mtd(nand);
1048 struct nand_ecc_ctrl *ecc = &nand->ecc;
1049 int offset = ((ecc->bytes + 4) * ecc->steps);
1050 int len = mtd->oobsize - offset;
1055 if (!cur_off || *cur_off != offset)
1056 nand_change_write_column_op(nand, offset + mtd->writesize,
1059 sunxi_nfc_randomizer_write_buf(nand, oob + offset, len, false, page);
1062 *cur_off = mtd->oobsize + mtd->writesize;
1065 static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *nand, uint8_t *buf,
1066 int oob_required, int page)
1068 struct mtd_info *mtd = nand_to_mtd(nand);
1069 struct nand_ecc_ctrl *ecc = &nand->ecc;
1070 unsigned int max_bitflips = 0;
1071 int ret, i, cur_off = 0;
1072 bool raw_mode = false;
1074 sunxi_nfc_select_chip(nand, nand->cur_cs);
1076 nand_read_page_op(nand, page, 0, NULL, 0);
1078 sunxi_nfc_hw_ecc_enable(nand);
1080 for (i = 0; i < ecc->steps; i++) {
1081 int data_off = i * ecc->size;
1082 int oob_off = i * (ecc->bytes + 4);
1083 u8 *data = buf + data_off;
1084 u8 *oob = nand->oob_poi + oob_off;
1086 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, oob,
1087 oob_off + mtd->writesize,
1088 &cur_off, &max_bitflips,
1089 !i, oob_required, page);
1097 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi, &cur_off,
1100 sunxi_nfc_hw_ecc_disable(nand);
1102 return max_bitflips;
1105 static int sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip *nand, u8 *buf,
1106 int oob_required, int page)
1110 sunxi_nfc_select_chip(nand, nand->cur_cs);
1112 nand_read_page_op(nand, page, 0, NULL, 0);
1114 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, oob_required, page,
1119 /* Fallback to PIO mode */
1120 return sunxi_nfc_hw_ecc_read_page(nand, buf, oob_required, page);
1123 static int sunxi_nfc_hw_ecc_read_subpage(struct nand_chip *nand,
1124 u32 data_offs, u32 readlen,
1125 u8 *bufpoi, int page)
1127 struct mtd_info *mtd = nand_to_mtd(nand);
1128 struct nand_ecc_ctrl *ecc = &nand->ecc;
1129 int ret, i, cur_off = 0;
1130 unsigned int max_bitflips = 0;
1132 sunxi_nfc_select_chip(nand, nand->cur_cs);
1134 nand_read_page_op(nand, page, 0, NULL, 0);
1136 sunxi_nfc_hw_ecc_enable(nand);
1138 for (i = data_offs / ecc->size;
1139 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1140 int data_off = i * ecc->size;
1141 int oob_off = i * (ecc->bytes + 4);
1142 u8 *data = bufpoi + data_off;
1143 u8 *oob = nand->oob_poi + oob_off;
1145 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off,
1147 oob_off + mtd->writesize,
1148 &cur_off, &max_bitflips, !i,
1154 sunxi_nfc_hw_ecc_disable(nand);
1156 return max_bitflips;
1159 static int sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip *nand,
1160 u32 data_offs, u32 readlen,
1163 int nchunks = DIV_ROUND_UP(data_offs + readlen, nand->ecc.size);
1166 sunxi_nfc_select_chip(nand, nand->cur_cs);
1168 nand_read_page_op(nand, page, 0, NULL, 0);
1170 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, false, page, nchunks);
1174 /* Fallback to PIO mode */
1175 return sunxi_nfc_hw_ecc_read_subpage(nand, data_offs, readlen,
1179 static int sunxi_nfc_hw_ecc_write_page(struct nand_chip *nand,
1180 const uint8_t *buf, int oob_required,
1183 struct mtd_info *mtd = nand_to_mtd(nand);
1184 struct nand_ecc_ctrl *ecc = &nand->ecc;
1185 int ret, i, cur_off = 0;
1187 sunxi_nfc_select_chip(nand, nand->cur_cs);
1189 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1191 sunxi_nfc_hw_ecc_enable(nand);
1193 for (i = 0; i < ecc->steps; i++) {
1194 int data_off = i * ecc->size;
1195 int oob_off = i * (ecc->bytes + 4);
1196 const u8 *data = buf + data_off;
1197 const u8 *oob = nand->oob_poi + oob_off;
1199 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
1200 oob_off + mtd->writesize,
1201 &cur_off, !i, page);
1206 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
1207 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
1210 sunxi_nfc_hw_ecc_disable(nand);
1212 return nand_prog_page_end_op(nand);
1215 static int sunxi_nfc_hw_ecc_write_subpage(struct nand_chip *nand,
1216 u32 data_offs, u32 data_len,
1217 const u8 *buf, int oob_required,
1220 struct mtd_info *mtd = nand_to_mtd(nand);
1221 struct nand_ecc_ctrl *ecc = &nand->ecc;
1222 int ret, i, cur_off = 0;
1224 sunxi_nfc_select_chip(nand, nand->cur_cs);
1226 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1228 sunxi_nfc_hw_ecc_enable(nand);
1230 for (i = data_offs / ecc->size;
1231 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1232 int data_off = i * ecc->size;
1233 int oob_off = i * (ecc->bytes + 4);
1234 const u8 *data = buf + data_off;
1235 const u8 *oob = nand->oob_poi + oob_off;
1237 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
1238 oob_off + mtd->writesize,
1239 &cur_off, !i, page);
1244 sunxi_nfc_hw_ecc_disable(nand);
1246 return nand_prog_page_end_op(nand);
1249 static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand,
1254 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1255 struct nand_ecc_ctrl *ecc = &nand->ecc;
1256 struct scatterlist sg;
1259 sunxi_nfc_select_chip(nand, nand->cur_cs);
1261 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1265 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps,
1266 DMA_TO_DEVICE, &sg);
1270 for (i = 0; i < ecc->steps; i++) {
1271 const u8 *oob = nand->oob_poi + (i * (ecc->bytes + 4));
1273 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page);
1276 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1278 sunxi_nfc_hw_ecc_enable(nand);
1279 sunxi_nfc_randomizer_config(nand, page, false);
1280 sunxi_nfc_randomizer_enable(nand);
1282 writel((NAND_CMD_RNDIN << 8) | NAND_CMD_PAGEPROG,
1283 nfc->regs + NFC_REG_WCMD_SET);
1285 dma_async_issue_pending(nfc->dmac);
1287 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD |
1288 NFC_DATA_TRANS | NFC_ACCESS_DIR,
1289 nfc->regs + NFC_REG_CMD);
1291 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
1293 dmaengine_terminate_all(nfc->dmac);
1295 sunxi_nfc_randomizer_disable(nand);
1296 sunxi_nfc_hw_ecc_disable(nand);
1298 sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg);
1303 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
1304 /* TODO: use DMA to transfer extra OOB bytes ? */
1305 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
1308 return nand_prog_page_end_op(nand);
1311 return sunxi_nfc_hw_ecc_write_page(nand, buf, oob_required, page);
1314 static int sunxi_nfc_hw_ecc_read_oob(struct nand_chip *nand, int page)
1318 return nand->ecc.read_page(nand, nand->data_buf, 1, page);
1321 static int sunxi_nfc_hw_ecc_write_oob(struct nand_chip *nand, int page)
1323 struct mtd_info *mtd = nand_to_mtd(nand);
1328 memset(nand->data_buf, 0xff, mtd->writesize);
1329 ret = nand->ecc.write_page(nand, nand->data_buf, 1, page);
1333 /* Send command to program the OOB data */
1334 return nand_prog_page_end_op(nand);
1337 static const s32 tWB_lut[] = {6, 12, 16, 20};
1338 static const s32 tRHW_lut[] = {4, 8, 12, 20};
1340 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1343 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1346 for (i = 0; i < lut_size; i++) {
1347 if (clk_cycles <= lut[i])
1355 #define sunxi_nand_lookup_timing(l, p, c) \
1356 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1358 static int sunxi_nfc_setup_data_interface(struct nand_chip *nand, int csline,
1359 const struct nand_data_interface *conf)
1361 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1362 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1363 const struct nand_sdr_timings *timings;
1364 u32 min_clk_period = 0;
1365 s32 tWB, tADL, tWHR, tRHW, tCAD;
1368 timings = nand_get_sdr_timings(conf);
1369 if (IS_ERR(timings))
1373 if (timings->tCLS_min > min_clk_period)
1374 min_clk_period = timings->tCLS_min;
1377 if (timings->tCLH_min > min_clk_period)
1378 min_clk_period = timings->tCLH_min;
1381 if (timings->tCS_min > min_clk_period)
1382 min_clk_period = timings->tCS_min;
1385 if (timings->tCH_min > min_clk_period)
1386 min_clk_period = timings->tCH_min;
1389 if (timings->tWP_min > min_clk_period)
1390 min_clk_period = timings->tWP_min;
1393 if (timings->tWH_min > min_clk_period)
1394 min_clk_period = timings->tWH_min;
1397 if (timings->tALS_min > min_clk_period)
1398 min_clk_period = timings->tALS_min;
1401 if (timings->tDS_min > min_clk_period)
1402 min_clk_period = timings->tDS_min;
1405 if (timings->tDH_min > min_clk_period)
1406 min_clk_period = timings->tDH_min;
1409 if (timings->tRR_min > (min_clk_period * 3))
1410 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1413 if (timings->tALH_min > min_clk_period)
1414 min_clk_period = timings->tALH_min;
1417 if (timings->tRP_min > min_clk_period)
1418 min_clk_period = timings->tRP_min;
1421 if (timings->tREH_min > min_clk_period)
1422 min_clk_period = timings->tREH_min;
1425 if (timings->tRC_min > (min_clk_period * 2))
1426 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1429 if (timings->tWC_min > (min_clk_period * 2))
1430 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1432 /* T16 - T19 + tCAD */
1433 if (timings->tWB_max > (min_clk_period * 20))
1434 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
1436 if (timings->tADL_min > (min_clk_period * 32))
1437 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
1439 if (timings->tWHR_min > (min_clk_period * 32))
1440 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
1442 if (timings->tRHW_min > (min_clk_period * 20))
1443 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
1446 * In non-EDO, tREA should be less than tRP to guarantee that the
1447 * controller does not sample the IO lines too early. Unfortunately,
1448 * the sunxi NAND controller does not allow us to have different
1449 * values for tRP and tREH (tRP = tREH = tRW / 2).
1451 * We have 2 options to overcome this limitation:
1453 * 1/ Extend tRC to fulfil the tREA <= tRC / 2 constraint
1454 * 2/ Use EDO mode (only works if timings->tRLOH > 0)
1456 if (timings->tREA_max > min_clk_period && !timings->tRLOH_min)
1457 min_clk_period = timings->tREA_max;
1459 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1462 dev_err(nfc->dev, "unsupported tWB\n");
1466 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1468 dev_err(nfc->dev, "unsupported tADL\n");
1472 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1474 dev_err(nfc->dev, "unsupported tWHR\n");
1478 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1481 dev_err(nfc->dev, "unsupported tRHW\n");
1485 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1489 * TODO: according to ONFI specs this value only applies for DDR NAND,
1490 * but Allwinner seems to set this to 0x7. Mimic them for now.
1494 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1495 sunxi_nand->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1497 /* Convert min_clk_period from picoseconds to nanoseconds */
1498 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1501 * Unlike what is stated in Allwinner datasheet, the clk_rate should
1502 * be set to (1 / min_clk_period), and not (2 / min_clk_period).
1503 * This new formula was verified with a scope and validated by
1504 * Allwinner engineers.
1506 sunxi_nand->clk_rate = NSEC_PER_SEC / min_clk_period;
1507 real_clk_rate = clk_round_rate(nfc->mod_clk, sunxi_nand->clk_rate);
1508 if (real_clk_rate <= 0) {
1509 dev_err(nfc->dev, "Unable to round clk %lu\n",
1510 sunxi_nand->clk_rate);
1514 sunxi_nand->timing_ctl = 0;
1517 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1518 * output cycle timings shall be used if the host drives tRC less than
1519 * 30 ns. We should also use EDO mode if tREA is bigger than tRP.
1521 min_clk_period = NSEC_PER_SEC / real_clk_rate;
1522 if (min_clk_period * 2 < 30 || min_clk_period * 1000 < timings->tREA_max)
1523 sunxi_nand->timing_ctl = NFC_TIMING_CTL_EDO;
1528 static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
1529 struct mtd_oob_region *oobregion)
1531 struct nand_chip *nand = mtd_to_nand(mtd);
1532 struct nand_ecc_ctrl *ecc = &nand->ecc;
1534 if (section >= ecc->steps)
1537 oobregion->offset = section * (ecc->bytes + 4) + 4;
1538 oobregion->length = ecc->bytes;
1543 static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section,
1544 struct mtd_oob_region *oobregion)
1546 struct nand_chip *nand = mtd_to_nand(mtd);
1547 struct nand_ecc_ctrl *ecc = &nand->ecc;
1549 if (section > ecc->steps)
1553 * The first 2 bytes are used for BB markers, hence we
1554 * only have 2 bytes available in the first user data
1557 if (!section && ecc->mode == NAND_ECC_HW) {
1558 oobregion->offset = 2;
1559 oobregion->length = 2;
1564 oobregion->offset = section * (ecc->bytes + 4);
1566 if (section < ecc->steps)
1567 oobregion->length = 4;
1569 oobregion->offset = mtd->oobsize - oobregion->offset;
1574 static const struct mtd_ooblayout_ops sunxi_nand_ooblayout_ops = {
1575 .ecc = sunxi_nand_ooblayout_ecc,
1576 .free = sunxi_nand_ooblayout_free,
1579 static void sunxi_nand_hw_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1584 static int sunxi_nand_hw_ecc_ctrl_init(struct nand_chip *nand,
1585 struct nand_ecc_ctrl *ecc,
1586 struct device_node *np)
1588 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1589 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1590 struct mtd_info *mtd = nand_to_mtd(nand);
1591 struct sunxi_nand_hw_ecc *data;
1596 if (ecc->options & NAND_ECC_MAXIMIZE) {
1600 nsectors = mtd->writesize / ecc->size;
1602 /* Reserve 2 bytes for the BBM */
1603 bytes = (mtd->oobsize - 2) / nsectors;
1605 /* 4 non-ECC bytes are added before each ECC bytes section */
1608 /* and bytes has to be even. */
1612 ecc->strength = bytes * 8 / fls(8 * ecc->size);
1614 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1615 if (strengths[i] > ecc->strength)
1622 ecc->strength = strengths[i - 1];
1625 if (ecc->size != 512 && ecc->size != 1024)
1628 data = kzalloc(sizeof(*data), GFP_KERNEL);
1632 /* Prefer 1k ECC chunk over 512 ones */
1633 if (ecc->size == 512 && mtd->writesize > 512) {
1638 /* Add ECC info retrieval from DT */
1639 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1640 if (ecc->strength <= strengths[i]) {
1642 * Update ecc->strength value with the actual strength
1643 * that will be used by the ECC engine.
1645 ecc->strength = strengths[i];
1650 if (i >= ARRAY_SIZE(strengths)) {
1651 dev_err(nfc->dev, "unsupported strength\n");
1658 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1659 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1661 /* HW ECC always work with even numbers of ECC bytes */
1662 ecc->bytes = ALIGN(ecc->bytes, 2);
1664 nsectors = mtd->writesize / ecc->size;
1666 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1671 ecc->read_oob = sunxi_nfc_hw_ecc_read_oob;
1672 ecc->write_oob = sunxi_nfc_hw_ecc_write_oob;
1673 mtd_set_ooblayout(mtd, &sunxi_nand_ooblayout_ops);
1677 ecc->read_page = sunxi_nfc_hw_ecc_read_page_dma;
1678 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage_dma;
1679 ecc->write_page = sunxi_nfc_hw_ecc_write_page_dma;
1680 nand->options |= NAND_USE_BOUNCE_BUFFER;
1682 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1683 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1684 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1687 /* TODO: support DMA for raw accesses and subpage write */
1688 ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1689 ecc->read_oob_raw = nand_read_oob_std;
1690 ecc->write_oob_raw = nand_write_oob_std;
1700 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1702 switch (ecc->mode) {
1704 sunxi_nand_hw_ecc_ctrl_cleanup(ecc);
1712 static int sunxi_nand_attach_chip(struct nand_chip *nand)
1714 struct nand_ecc_ctrl *ecc = &nand->ecc;
1715 struct device_node *np = nand_get_flash_node(nand);
1718 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1719 nand->bbt_options |= NAND_BBT_NO_OOB;
1721 if (nand->options & NAND_NEED_SCRAMBLING)
1722 nand->options |= NAND_NO_SUBPAGE_WRITE;
1724 nand->options |= NAND_SUBPAGE_READ;
1727 ecc->size = nand->ecc_step_ds;
1728 ecc->strength = nand->ecc_strength_ds;
1731 if (!ecc->size || !ecc->strength)
1734 switch (ecc->mode) {
1736 ret = sunxi_nand_hw_ecc_ctrl_init(nand, ecc, np);
1750 static int sunxi_nfc_exec_subop(struct nand_chip *nand,
1751 const struct nand_subop *subop)
1753 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1754 u32 cmd = 0, extcmd = 0, cnt = 0, addrs[2] = { };
1755 unsigned int i, j, remaining, start;
1759 for (i = 0; i < subop->ninstrs; i++) {
1760 const struct nand_op_instr *instr = &subop->instrs[i];
1762 switch (instr->type) {
1763 case NAND_OP_CMD_INSTR:
1764 if (cmd & NFC_SEND_CMD1) {
1765 if (WARN_ON(cmd & NFC_SEND_CMD2))
1768 cmd |= NFC_SEND_CMD2;
1769 extcmd |= instr->ctx.cmd.opcode;
1771 cmd |= NFC_SEND_CMD1 |
1772 NFC_CMD(instr->ctx.cmd.opcode);
1776 case NAND_OP_ADDR_INSTR:
1777 remaining = nand_subop_get_num_addr_cyc(subop, i);
1778 start = nand_subop_get_addr_start_off(subop, i);
1779 for (j = 0; j < 8 && j + start < remaining; j++) {
1780 u32 addr = instr->ctx.addr.addrs[j + start];
1782 addrs[j / 4] |= addr << (j % 4) * 8;
1786 cmd |= NFC_SEND_ADR | NFC_ADR_NUM(j);
1790 case NAND_OP_DATA_IN_INSTR:
1791 case NAND_OP_DATA_OUT_INSTR:
1792 start = nand_subop_get_data_start_off(subop, i);
1793 remaining = nand_subop_get_data_len(subop, i);
1794 cnt = min_t(u32, remaining, NFC_SRAM_SIZE);
1795 cmd |= NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
1797 if (instr->type == NAND_OP_DATA_OUT_INSTR) {
1798 cmd |= NFC_ACCESS_DIR;
1799 memcpy_toio(nfc->regs + NFC_RAM0_BASE,
1800 instr->ctx.data.buf.out + start,
1803 inbuf = instr->ctx.data.buf.in + start;
1808 case NAND_OP_WAITRDY_INSTR:
1809 cmd |= NFC_WAIT_FLAG;
1814 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1818 if (cmd & NFC_SEND_ADR) {
1819 writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW);
1820 writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH);
1823 if (cmd & NFC_SEND_CMD2)
1826 (cmd & NFC_ACCESS_DIR ?
1827 NFC_REG_WCMD_SET : NFC_REG_RCMD_SET));
1829 if (cmd & NFC_DATA_TRANS)
1830 writel(cnt, nfc->regs + NFC_REG_CNT);
1832 writel(cmd, nfc->regs + NFC_REG_CMD);
1834 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG,
1835 !(cmd & NFC_WAIT_FLAG) && cnt < 64,
1841 memcpy_fromio(inbuf, nfc->regs + NFC_RAM0_BASE, cnt);
1846 static int sunxi_nfc_soft_waitrdy(struct nand_chip *nand,
1847 const struct nand_subop *subop)
1849 return nand_soft_waitrdy(nand,
1850 subop->instrs[0].ctx.waitrdy.timeout_ms);
1853 static const struct nand_op_parser sunxi_nfc_op_parser = NAND_OP_PARSER(
1854 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1855 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1856 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1857 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1858 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
1859 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)),
1860 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1861 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1862 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1863 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024),
1864 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1865 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
1868 static const struct nand_op_parser sunxi_nfc_norb_op_parser = NAND_OP_PARSER(
1869 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1870 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1871 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1872 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1873 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)),
1874 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1875 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1876 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1877 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024),
1878 NAND_OP_PARSER_PAT_CMD_ELEM(true)),
1879 NAND_OP_PARSER_PATTERN(sunxi_nfc_soft_waitrdy,
1880 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1883 static int sunxi_nfc_exec_op(struct nand_chip *nand,
1884 const struct nand_operation *op, bool check_only)
1886 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1887 const struct nand_op_parser *parser;
1889 sunxi_nfc_select_chip(nand, op->cs);
1891 if (sunxi_nand->sels[op->cs].rb >= 0)
1892 parser = &sunxi_nfc_op_parser;
1894 parser = &sunxi_nfc_norb_op_parser;
1896 return nand_op_parser_exec_op(nand, parser, op, check_only);
1899 static const struct nand_controller_ops sunxi_nand_controller_ops = {
1900 .attach_chip = sunxi_nand_attach_chip,
1901 .setup_data_interface = sunxi_nfc_setup_data_interface,
1902 .exec_op = sunxi_nfc_exec_op,
1905 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1906 struct device_node *np)
1908 struct sunxi_nand_chip *sunxi_nand;
1909 struct mtd_info *mtd;
1910 struct nand_chip *nand;
1916 if (!of_get_property(np, "reg", &nsels))
1919 nsels /= sizeof(u32);
1921 dev_err(dev, "invalid reg property size\n");
1925 sunxi_nand = devm_kzalloc(dev, struct_size(sunxi_nand, sels, nsels),
1928 dev_err(dev, "could not allocate chip\n");
1932 sunxi_nand->nsels = nsels;
1934 for (i = 0; i < nsels; i++) {
1935 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1937 dev_err(dev, "could not retrieve reg property: %d\n",
1942 if (tmp > NFC_MAX_CS) {
1944 "invalid reg value: %u (max CS = 7)\n",
1949 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1950 dev_err(dev, "CS %d already assigned\n", tmp);
1954 sunxi_nand->sels[i].cs = tmp;
1956 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1958 sunxi_nand->sels[i].rb = tmp;
1960 sunxi_nand->sels[i].rb = -1;
1963 nand = &sunxi_nand->nand;
1964 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1965 nand->controller = &nfc->controller;
1966 nand->controller->ops = &sunxi_nand_controller_ops;
1969 * Set the ECC mode to the default value in case nothing is specified
1972 nand->ecc.mode = NAND_ECC_HW;
1973 nand_set_flash_node(nand, np);
1975 mtd = nand_to_mtd(nand);
1976 mtd->dev.parent = dev;
1978 ret = nand_scan(nand, nsels);
1982 ret = mtd_device_register(mtd, NULL, 0);
1984 dev_err(dev, "failed to register mtd device: %d\n", ret);
1989 list_add_tail(&sunxi_nand->node, &nfc->chips);
1994 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1996 struct device_node *np = dev->of_node;
1997 struct device_node *nand_np;
1998 int nchips = of_get_child_count(np);
2002 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
2006 for_each_child_of_node(np, nand_np) {
2007 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
2009 of_node_put(nand_np);
2017 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
2019 struct sunxi_nand_chip *sunxi_nand;
2021 while (!list_empty(&nfc->chips)) {
2022 sunxi_nand = list_first_entry(&nfc->chips,
2023 struct sunxi_nand_chip,
2025 nand_release(&sunxi_nand->nand);
2026 sunxi_nand_ecc_cleanup(&sunxi_nand->nand.ecc);
2027 list_del(&sunxi_nand->node);
2031 static int sunxi_nfc_probe(struct platform_device *pdev)
2033 struct device *dev = &pdev->dev;
2035 struct sunxi_nfc *nfc;
2039 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
2044 nand_controller_init(&nfc->controller);
2045 INIT_LIST_HEAD(&nfc->chips);
2047 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2048 nfc->regs = devm_ioremap_resource(dev, r);
2049 if (IS_ERR(nfc->regs))
2050 return PTR_ERR(nfc->regs);
2052 irq = platform_get_irq(pdev, 0);
2054 dev_err(dev, "failed to retrieve irq\n");
2058 nfc->ahb_clk = devm_clk_get(dev, "ahb");
2059 if (IS_ERR(nfc->ahb_clk)) {
2060 dev_err(dev, "failed to retrieve ahb clk\n");
2061 return PTR_ERR(nfc->ahb_clk);
2064 ret = clk_prepare_enable(nfc->ahb_clk);
2068 nfc->mod_clk = devm_clk_get(dev, "mod");
2069 if (IS_ERR(nfc->mod_clk)) {
2070 dev_err(dev, "failed to retrieve mod clk\n");
2071 ret = PTR_ERR(nfc->mod_clk);
2072 goto out_ahb_clk_unprepare;
2075 ret = clk_prepare_enable(nfc->mod_clk);
2077 goto out_ahb_clk_unprepare;
2079 nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
2080 if (IS_ERR(nfc->reset)) {
2081 ret = PTR_ERR(nfc->reset);
2082 goto out_mod_clk_unprepare;
2085 ret = reset_control_deassert(nfc->reset);
2087 dev_err(dev, "reset err %d\n", ret);
2088 goto out_mod_clk_unprepare;
2091 ret = sunxi_nfc_rst(nfc);
2093 goto out_ahb_reset_reassert;
2095 writel(0, nfc->regs + NFC_REG_INT);
2096 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
2097 0, "sunxi-nand", nfc);
2099 goto out_ahb_reset_reassert;
2101 nfc->dmac = dma_request_slave_channel(dev, "rxtx");
2103 struct dma_slave_config dmac_cfg = { };
2105 dmac_cfg.src_addr = r->start + NFC_REG_IO_DATA;
2106 dmac_cfg.dst_addr = dmac_cfg.src_addr;
2107 dmac_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2108 dmac_cfg.dst_addr_width = dmac_cfg.src_addr_width;
2109 dmac_cfg.src_maxburst = 4;
2110 dmac_cfg.dst_maxburst = 4;
2111 dmaengine_slave_config(nfc->dmac, &dmac_cfg);
2113 dev_warn(dev, "failed to request rxtx DMA channel\n");
2116 platform_set_drvdata(pdev, nfc);
2118 ret = sunxi_nand_chips_init(dev, nfc);
2120 dev_err(dev, "failed to init nand chips\n");
2121 goto out_release_dmac;
2128 dma_release_channel(nfc->dmac);
2129 out_ahb_reset_reassert:
2130 reset_control_assert(nfc->reset);
2131 out_mod_clk_unprepare:
2132 clk_disable_unprepare(nfc->mod_clk);
2133 out_ahb_clk_unprepare:
2134 clk_disable_unprepare(nfc->ahb_clk);
2139 static int sunxi_nfc_remove(struct platform_device *pdev)
2141 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
2143 sunxi_nand_chips_cleanup(nfc);
2145 reset_control_assert(nfc->reset);
2148 dma_release_channel(nfc->dmac);
2149 clk_disable_unprepare(nfc->mod_clk);
2150 clk_disable_unprepare(nfc->ahb_clk);
2155 static const struct of_device_id sunxi_nfc_ids[] = {
2156 { .compatible = "allwinner,sun4i-a10-nand" },
2159 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
2161 static struct platform_driver sunxi_nfc_driver = {
2163 .name = "sunxi_nand",
2164 .of_match_table = sunxi_nfc_ids,
2166 .probe = sunxi_nfc_probe,
2167 .remove = sunxi_nfc_remove,
2169 module_platform_driver(sunxi_nfc_driver);
2171 MODULE_LICENSE("GPL");
2172 MODULE_AUTHOR("Boris BREZILLON");
2173 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
2174 MODULE_ALIAS("platform:sunxi_nand");