2 * Copyright (C) 2017 Free Electrons
3 * Copyright (C) 2017 NextThing Co
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/sizes.h>
19 #include <linux/slab.h>
21 #include "internals.h"
23 #define NAND_HYNIX_CMD_SET_PARAMS 0x36
24 #define NAND_HYNIX_CMD_APPLY_PARAMS 0x16
26 #define NAND_HYNIX_1XNM_RR_REPEAT 8
29 * struct hynix_read_retry - read-retry data
30 * @nregs: number of register to set when applying a new read-retry mode
31 * @regs: register offsets (NAND chip dependent)
32 * @values: array of values to set in registers. The array size is equal to
35 struct hynix_read_retry {
42 * struct hynix_nand - private Hynix NAND struct
43 * @nand_technology: manufacturing process expressed in picometer
44 * @read_retry: read-retry information
47 const struct hynix_read_retry *read_retry;
51 * struct hynix_read_retry_otp - structure describing how the read-retry OTP
53 * @nregs: number of hynix private registers to set before reading the reading
55 * @regs: registers that should be configured
56 * @values: values that should be set in regs
57 * @page: the address to pass to the READ_PAGE command. Depends on the NAND
59 * @size: size of the read-retry OTP section
61 struct hynix_read_retry_otp {
69 static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip)
74 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid));
78 return !strncmp("JEDEC", jedecid, sizeof(jedecid));
81 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd)
83 if (nand_has_exec_op(chip)) {
84 struct nand_op_instr instrs[] = {
87 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
89 return nand_exec_op(chip, &op);
92 chip->legacy.cmdfunc(chip, cmd, -1, -1);
97 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val)
99 u16 column = ((u16)addr << 8) | addr;
101 if (nand_has_exec_op(chip)) {
102 struct nand_op_instr instrs[] = {
103 NAND_OP_ADDR(1, &addr, 0),
104 NAND_OP_8BIT_DATA_OUT(1, &val, 0),
106 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
108 return nand_exec_op(chip, &op);
111 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);
112 chip->legacy.write_byte(chip, val);
117 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
119 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
123 values = hynix->read_retry->values +
124 (retry_mode * hynix->read_retry->nregs);
126 /* Enter 'Set Hynix Parameters' mode */
127 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
132 * Configure the NAND in the requested read-retry mode.
133 * This is done by setting pre-defined values in internal NAND
136 * The set of registers is NAND specific, and the values are either
137 * predefined or extracted from an OTP area on the NAND (values are
138 * probably tweaked at production in this case).
140 for (i = 0; i < hynix->read_retry->nregs; i++) {
141 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i],
147 /* Apply the new settings. */
148 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
152 * hynix_get_majority - get the value that is occurring the most in a given
154 * @in: the array of values to test
155 * @repeat: the size of the in array
156 * @out: pointer used to store the output value
158 * This function implements the 'majority check' logic that is supposed to
159 * overcome the unreliability of MLC NANDs when reading the OTP area storing
160 * the read-retry parameters.
162 * It's based on a pretty simple assumption: if we repeat the same value
163 * several times and then take the one that is occurring the most, we should
164 * find the correct value.
165 * Let's hope this dummy algorithm prevents us from losing the read-retry
168 static int hynix_get_majority(const u8 *in, int repeat, u8 *out)
170 int i, j, half = repeat / 2;
173 * We only test the first half of the in array because we must ensure
174 * that the value is at least occurring repeat / 2 times.
176 * This loop is suboptimal since we may count the occurrences of the
177 * same value several time, but we are doing that on small sets, which
178 * makes it acceptable.
180 for (i = 0; i < half; i++) {
184 /* Count all values that are matching the one at index i. */
185 for (j = i + 1; j < repeat; j++) {
190 /* We found a value occurring more than repeat / 2. */
200 static int hynix_read_rr_otp(struct nand_chip *chip,
201 const struct hynix_read_retry_otp *info,
206 ret = nand_reset_op(chip);
210 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
214 for (i = 0; i < info->nregs; i++) {
215 ret = hynix_nand_reg_write_op(chip, info->regs[i],
221 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
225 /* Sequence to enter OTP mode? */
226 ret = hynix_nand_cmd_op(chip, 0x17);
230 ret = hynix_nand_cmd_op(chip, 0x4);
234 ret = hynix_nand_cmd_op(chip, 0x19);
238 /* Now read the page */
239 ret = nand_read_page_op(chip, info->page, 0, buf, info->size);
243 /* Put everything back to normal */
244 ret = nand_reset_op(chip);
248 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
252 ret = hynix_nand_reg_write_op(chip, 0x38, 0);
256 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
260 return nand_read_page_op(chip, 0, 0, NULL, 0);
263 #define NAND_HYNIX_1XNM_RR_COUNT_OFFS 0
264 #define NAND_HYNIX_1XNM_RR_REG_COUNT_OFFS 8
265 #define NAND_HYNIX_1XNM_RR_SET_OFFS(x, setsize, inv) \
266 (16 + ((((x) * 2) + ((inv) ? 1 : 0)) * (setsize)))
268 static int hynix_mlc_1xnm_rr_value(const u8 *buf, int nmodes, int nregs,
269 int mode, int reg, bool inv, u8 *val)
271 u8 tmp[NAND_HYNIX_1XNM_RR_REPEAT];
272 int val_offs = (mode * nregs) + reg;
273 int set_size = nmodes * nregs;
276 for (i = 0; i < NAND_HYNIX_1XNM_RR_REPEAT; i++) {
277 int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv);
279 tmp[i] = buf[val_offs + set_offs];
282 ret = hynix_get_majority(tmp, NAND_HYNIX_1XNM_RR_REPEAT, val);
292 static u8 hynix_1xnm_mlc_read_retry_regs[] = {
293 0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf
296 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip,
297 const struct hynix_read_retry_otp *info)
299 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
300 struct hynix_read_retry *rr = NULL;
305 buf = kmalloc(info->size, GFP_KERNEL);
309 ret = hynix_read_rr_otp(chip, info, buf);
313 ret = hynix_get_majority(buf, NAND_HYNIX_1XNM_RR_REPEAT,
318 ret = hynix_get_majority(buf + NAND_HYNIX_1XNM_RR_REPEAT,
319 NAND_HYNIX_1XNM_RR_REPEAT,
324 rr = kzalloc(sizeof(*rr) + (nregs * nmodes), GFP_KERNEL);
330 for (i = 0; i < nmodes; i++) {
331 for (j = 0; j < nregs; j++) {
332 u8 *val = rr->values + (i * nregs);
334 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
339 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
347 rr->regs = hynix_1xnm_mlc_read_retry_regs;
348 hynix->read_retry = rr;
349 chip->setup_read_retry = hynix_nand_setup_read_retry;
350 chip->read_retries = nmodes;
361 static const u8 hynix_mlc_1xnm_rr_otp_regs[] = { 0x38 };
362 static const u8 hynix_mlc_1xnm_rr_otp_values[] = { 0x52 };
364 static const struct hynix_read_retry_otp hynix_mlc_1xnm_rr_otps[] = {
366 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
367 .regs = hynix_mlc_1xnm_rr_otp_regs,
368 .values = hynix_mlc_1xnm_rr_otp_values,
373 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
374 .regs = hynix_mlc_1xnm_rr_otp_regs,
375 .values = hynix_mlc_1xnm_rr_otp_values,
381 static int hynix_nand_rr_init(struct nand_chip *chip)
386 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
389 * We only support read-retry for 1xnm NANDs, and those NANDs all
390 * expose a valid JEDEC ID.
393 u8 nand_tech = chip->id.data[5] >> 4;
395 /* 1xnm technology */
396 if (nand_tech == 4) {
397 for (i = 0; i < ARRAY_SIZE(hynix_mlc_1xnm_rr_otps);
400 * FIXME: Hynix recommend to copy the
401 * read-retry OTP area into a normal page.
403 ret = hynix_mlc_1xnm_rr_init(chip,
404 hynix_mlc_1xnm_rr_otps);
412 pr_warn("failed to initialize read-retry infrastructure");
417 static void hynix_nand_extract_oobsize(struct nand_chip *chip,
420 struct mtd_info *mtd = nand_to_mtd(chip);
421 struct nand_memory_organization *memorg;
424 memorg = nanddev_get_memorg(&chip->base);
426 oobsize = ((chip->id.data[3] >> 2) & 0x3) |
427 ((chip->id.data[3] >> 4) & 0x4);
432 memorg->oobsize = 2048;
435 memorg->oobsize = 1664;
438 memorg->oobsize = 1024;
441 memorg->oobsize = 640;
445 * We should never reach this case, but if that
446 * happens, this probably means Hynix decided to use
447 * a different extended ID format, and we should find
448 * a way to support it.
450 WARN(1, "Invalid OOB size");
456 memorg->oobsize = 128;
459 memorg->oobsize = 224;
462 memorg->oobsize = 448;
465 memorg->oobsize = 64;
468 memorg->oobsize = 32;
471 memorg->oobsize = 16;
474 memorg->oobsize = 640;
478 * We should never reach this case, but if that
479 * happens, this probably means Hynix decided to use
480 * a different extended ID format, and we should find
481 * a way to support it.
483 WARN(1, "Invalid OOB size");
488 * The datasheet of H27UCG8T2BTR mentions that the "Redundant
489 * Area Size" is encoded "per 8KB" (page size). This chip uses
490 * a page size of 16KiB. The datasheet mentions an OOB size of
491 * 1.280 bytes, but the OOB size encoded in the ID bytes (using
492 * the existing logic above) is 640 bytes.
493 * Update the OOB size for this chip by taking the value
494 * determined above and scaling it to the actual page size (so
495 * the actual OOB size for this chip is: 640 * 16k / 8k).
497 if (chip->id.data[1] == 0xde)
498 memorg->oobsize *= memorg->pagesize / SZ_8K;
501 mtd->oobsize = memorg->oobsize;
504 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
507 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;
510 /* Reference: H27UCG8T2E datasheet */
511 chip->base.eccreq.step_size = 1024;
515 chip->base.eccreq.step_size = 0;
516 chip->base.eccreq.strength = 0;
519 chip->base.eccreq.strength = 4;
522 chip->base.eccreq.strength = 24;
525 chip->base.eccreq.strength = 32;
528 chip->base.eccreq.strength = 40;
531 chip->base.eccreq.strength = 50;
534 chip->base.eccreq.strength = 60;
538 * We should never reach this case, but if that
539 * happens, this probably means Hynix decided to use
540 * a different extended ID format, and we should find
541 * a way to support it.
543 WARN(1, "Invalid ECC requirements");
547 * The ECC requirements field meaning depends on the
550 u8 nand_tech = chip->id.data[5] & 0x7;
553 /* > 26nm, reference: H27UBG8T2A datasheet */
555 chip->base.eccreq.step_size = 512;
556 chip->base.eccreq.strength = 1 << ecc_level;
557 } else if (ecc_level < 7) {
559 chip->base.eccreq.step_size = 2048;
561 chip->base.eccreq.step_size = 1024;
562 chip->base.eccreq.strength = 24;
565 * We should never reach this case, but if that
566 * happens, this probably means Hynix decided
567 * to use a different extended ID format, and
568 * we should find a way to support it.
570 WARN(1, "Invalid ECC requirements");
573 /* <= 26nm, reference: H27UBG8T2B datasheet */
575 chip->base.eccreq.step_size = 0;
576 chip->base.eccreq.strength = 0;
577 } else if (ecc_level < 5) {
578 chip->base.eccreq.step_size = 512;
579 chip->base.eccreq.strength = 1 << (ecc_level - 1);
581 chip->base.eccreq.step_size = 1024;
582 chip->base.eccreq.strength = 24 +
583 (8 * (ecc_level - 5));
589 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
594 /* We need scrambling on all TLC NANDs*/
595 if (nanddev_bits_per_cell(&chip->base) > 2)
596 chip->options |= NAND_NEED_SCRAMBLING;
598 /* And on MLC NANDs with sub-3xnm process */
600 nand_tech = chip->id.data[5] >> 4;
604 chip->options |= NAND_NEED_SCRAMBLING;
606 nand_tech = chip->id.data[5] & 0x7;
610 chip->options |= NAND_NEED_SCRAMBLING;
614 static void hynix_nand_decode_id(struct nand_chip *chip)
616 struct mtd_info *mtd = nand_to_mtd(chip);
617 struct nand_memory_organization *memorg;
621 memorg = nanddev_get_memorg(&chip->base);
624 * Exclude all SLC NANDs from this advanced detection scheme.
625 * According to the ranges defined in several datasheets, it might
626 * appear that even SLC NANDs could fall in this extended ID scheme.
627 * If that the case rework the test to let SLC NANDs go through the
630 if (chip->id.len < 6 || nand_is_slc(chip)) {
631 nand_decode_ext_id(chip);
635 /* Extract pagesize */
636 memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);
637 mtd->writesize = memorg->pagesize;
639 tmp = (chip->id.data[3] >> 4) & 0x3;
641 * When bit7 is set that means we start counting at 1MiB, otherwise
642 * we start counting at 128KiB and shift this value the content of
644 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in
645 * this case the erasesize is set to 768KiB.
647 if (chip->id.data[3] & 0x80) {
648 memorg->pages_per_eraseblock = (SZ_1M << tmp) /
650 mtd->erasesize = SZ_1M << tmp;
651 } else if (tmp == 3) {
652 memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) /
654 mtd->erasesize = SZ_512K + SZ_256K;
656 memorg->pages_per_eraseblock = (SZ_128K << tmp) /
658 mtd->erasesize = SZ_128K << tmp;
662 * Modern Toggle DDR NANDs have a valid JEDECID even though they are
663 * not exposing a valid JEDEC parameter table.
664 * These NANDs use a different NAND ID scheme.
666 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
668 hynix_nand_extract_oobsize(chip, valid_jedecid);
669 hynix_nand_extract_ecc_requirements(chip, valid_jedecid);
670 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid);
673 static void hynix_nand_cleanup(struct nand_chip *chip)
675 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
680 kfree(hynix->read_retry);
682 nand_set_manufacturer_data(chip, NULL);
685 static int hynix_nand_init(struct nand_chip *chip)
687 struct hynix_nand *hynix;
690 if (!nand_is_slc(chip))
691 chip->options |= NAND_BBM_LASTPAGE;
693 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
695 hynix = kzalloc(sizeof(*hynix), GFP_KERNEL);
699 nand_set_manufacturer_data(chip, hynix);
701 ret = hynix_nand_rr_init(chip);
703 hynix_nand_cleanup(chip);
708 const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
709 .detect = hynix_nand_decode_id,
710 .init = hynix_nand_init,
711 .cleanup = hynix_nand_cleanup,