drivers/mtd/nand/raw/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/rawnand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/completion.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37
  38 #include <asm/mach/flash.h>
  39 #include <linux/platform_data/mtd-mxc_nand.h>
  40
  41 #define DRIVER_NAME "mxc_nand"
  42
  43 /* Addresses for NFC registers */
  44 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
  45 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
  46 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
  47 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
  48 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
  49 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
  50 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
  51 #define NFC_V21_RSLTSPARE_AREA          (host->regs + 0x10)
  52 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
  53 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
  54 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
  55 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
  56 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
  57 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
  58 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
  59 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
  60 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
  61 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
  62 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
  63 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
  64 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
  65 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
  66
  67 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
  68 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
  69 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
  70 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
  71 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
  72 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
  73 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
  74 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
  75 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
  76 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
  77
  78 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
  79
  80 /*
  81  * Operation modes for the NFC. Valid for v1, v2 and v3
  82  * type controllers.
  83  */
  84 #define NFC_CMD                         (1 << 0)
  85 #define NFC_ADDR                        (1 << 1)
  86 #define NFC_INPUT                       (1 << 2)
  87 #define NFC_OUTPUT                      (1 << 3)
  88 #define NFC_ID                          (1 << 4)
  89 #define NFC_STATUS                      (1 << 5)
  90
  91 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
  92 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
  93
  94 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
  95 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
  96 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
  97
  98 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
  99
 100 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
 101
 102 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
 103 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
 104 #define NFC_V3_WRPROT_LOCK              (1 << 1)
 105 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
 106 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
 107
 108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
 109
 110 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
 111 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
 112 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
 113 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
 114 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
 115 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
 116 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
 117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
 118 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
 119 #define NFC_V3_CONFIG2_PPB(x, shift)            (((x) & 0x3) << shift)
 120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
 121 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
 122 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
 123 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
 124
 125 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
 126 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
 127 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
 128 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
 129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
 130 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
 131 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
 132
 133 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
 134 #define NFC_V3_IPC_CREQ                 (1 << 0)
 135 #define NFC_V3_IPC_INT                  (1 << 31)
 136
 137 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
 138
 139 struct mxc_nand_host;
 140
 141 struct mxc_nand_devtype_data {
 142         void (*preset)(struct mtd_info *);
 143         int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
 144                          int page);
 145         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
 146         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
 147         void (*send_page)(struct mtd_info *, unsigned int);
 148         void (*send_read_id)(struct mxc_nand_host *);
 149         uint16_t (*get_dev_status)(struct mxc_nand_host *);
 150         int (*check_int)(struct mxc_nand_host *);
 151         void (*irq_control)(struct mxc_nand_host *, int);
 152         u32 (*get_ecc_status)(struct mxc_nand_host *);
 153         const struct mtd_ooblayout_ops *ooblayout;
 154         void (*select_chip)(struct mtd_info *mtd, int chip);
 155         int (*setup_data_interface)(struct mtd_info *mtd, int csline,
 156                                     const struct nand_data_interface *conf);
 157         void (*enable_hwecc)(struct nand_chip *chip, bool enable);
 158
 159         /*
 160          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
 161          * (CONFIG1:INT_MSK is set). To handle this the driver uses
 162          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
 163          */
 164         int irqpending_quirk;
 165         int needs_ip;
 166
 167         size_t regs_offset;
 168         size_t spare0_offset;
 169         size_t axi_offset;
 170
 171         int spare_len;
 172         int eccbytes;
 173         int eccsize;
 174         int ppb_shift;
 175 };
 176
 177 struct mxc_nand_host {
 178         struct nand_chip        nand;
 179         struct device           *dev;
 180
 181         void __iomem            *spare0;
 182         void __iomem            *main_area0;
 183
 184         void __iomem            *base;
 185         void __iomem            *regs;
 186         void __iomem            *regs_axi;
 187         void __iomem            *regs_ip;
 188         int                     status_request;
 189         struct clk              *clk;
 190         int                     clk_act;
 191         int                     irq;
 192         int                     eccsize;
 193         int                     used_oobsize;
 194         int                     active_cs;
 195
 196         struct completion       op_completion;
 197
 198         uint8_t                 *data_buf;
 199         unsigned int            buf_start;
 200
 201         const struct mxc_nand_devtype_data *devtype_data;
 202         struct mxc_nand_platform_data pdata;
 203 };
 204
 205 static const char * const part_probes[] = {
 206         "cmdlinepart", "RedBoot", "ofpart", NULL };
 207
 208 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
 209 {
 210         int i;
 211         u32 *t = trg;
 212         const __iomem u32 *s = src;
 213
 214         for (i = 0; i < (size >> 2); i++)
 215                 *t++ = __raw_readl(s++);
 216 }
 217
 218 static void memcpy16_fromio(void *trg, const void __iomem  *src, size_t size)
 219 {
 220         int i;
 221         u16 *t = trg;
 222         const __iomem u16 *s = src;
 223
 224         /* We assume that src (IO) is always 32bit aligned */
 225         if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
 226                 memcpy32_fromio(trg, src, size);
 227                 return;
 228         }
 229
 230         for (i = 0; i < (size >> 1); i++)
 231                 *t++ = __raw_readw(s++);
 232 }
 233
 234 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
 235 {
 236         /* __iowrite32_copy use 32bit size values so divide by 4 */
 237         __iowrite32_copy(trg, src, size / 4);
 238 }
 239
 240 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
 241 {
 242         int i;
 243         __iomem u16 *t = trg;
 244         const u16 *s = src;
 245
 246         /* We assume that trg (IO) is always 32bit aligned */
 247         if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
 248                 memcpy32_toio(trg, src, size);
 249                 return;
 250         }
 251
 252         for (i = 0; i < (size >> 1); i++)
 253                 __raw_writew(*s++, t++);
 254 }
 255
 256 /*
 257  * The controller splits a page into data chunks of 512 bytes + partial oob.
 258  * There are writesize / 512 such chunks, the size of the partial oob parts is
 259  * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
 260  * contains additionally the byte lost by rounding (if any).
 261  * This function handles the needed shuffling between host->data_buf (which
 262  * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
 263  * spare) and the NFC buffer.
 264  */
 265 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
 266 {
 267         struct nand_chip *this = mtd_to_nand(mtd);
 268         struct mxc_nand_host *host = nand_get_controller_data(this);
 269         u16 i, oob_chunk_size;
 270         u16 num_chunks = mtd->writesize / 512;
 271
 272         u8 *d = buf;
 273         u8 __iomem *s = host->spare0;
 274         u16 sparebuf_size = host->devtype_data->spare_len;
 275
 276         /* size of oob chunk for all but possibly the last one */
 277         oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
 278
 279         if (bfrom) {
 280                 for (i = 0; i < num_chunks - 1; i++)
 281                         memcpy16_fromio(d + i * oob_chunk_size,
 282                                         s + i * sparebuf_size,
 283                                         oob_chunk_size);
 284
 285                 /* the last chunk */
 286                 memcpy16_fromio(d + i * oob_chunk_size,
 287                                 s + i * sparebuf_size,
 288                                 host->used_oobsize - i * oob_chunk_size);
 289         } else {
 290                 for (i = 0; i < num_chunks - 1; i++)
 291                         memcpy16_toio(&s[i * sparebuf_size],
 292                                       &d[i * oob_chunk_size],
 293                                       oob_chunk_size);
 294
 295                 /* the last chunk */
 296                 memcpy16_toio(&s[i * sparebuf_size],
 297                               &d[i * oob_chunk_size],
 298                               host->used_oobsize - i * oob_chunk_size);
 299         }
 300 }
 301
 302 /*
 303  * MXC NANDFC can only perform full page+spare or spare-only read/write.  When
 304  * the upper layers perform a read/write buf operation, the saved column address
 305  * is used to index into the full page. So usually this function is called with
 306  * column == 0 (unless no column cycle is needed indicated by column == -1)
 307  */
 308 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 309 {
 310         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 311         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 312
 313         /* Write out column address, if necessary */
 314         if (column != -1) {
 315                 host->devtype_data->send_addr(host, column & 0xff,
 316                                               page_addr == -1);
 317                 if (mtd->writesize > 512)
 318                         /* another col addr cycle for 2k page */
 319                         host->devtype_data->send_addr(host,
 320                                                       (column >> 8) & 0xff,
 321                                                       false);
 322         }
 323
 324         /* Write out page address, if necessary */
 325         if (page_addr != -1) {
 326                 /* paddr_0 - p_addr_7 */
 327                 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
 328
 329                 if (mtd->writesize > 512) {
 330                         if (mtd->size >= 0x10000000) {
 331                                 /* paddr_8 - paddr_15 */
 332                                 host->devtype_data->send_addr(host,
 333                                                 (page_addr >> 8) & 0xff,
 334                                                 false);
 335                                 host->devtype_data->send_addr(host,
 336                                                 (page_addr >> 16) & 0xff,
 337                                                 true);
 338                         } else
 339                                 /* paddr_8 - paddr_15 */
 340                                 host->devtype_data->send_addr(host,
 341                                                 (page_addr >> 8) & 0xff, true);
 342                 } else {
 343                         if (nand_chip->options & NAND_ROW_ADDR_3) {
 344                                 /* paddr_8 - paddr_15 */
 345                                 host->devtype_data->send_addr(host,
 346                                                 (page_addr >> 8) & 0xff,
 347                                                 false);
 348                                 host->devtype_data->send_addr(host,
 349                                                 (page_addr >> 16) & 0xff,
 350                                                 true);
 351                         } else
 352                                 /* paddr_8 - paddr_15 */
 353                                 host->devtype_data->send_addr(host,
 354                                                 (page_addr >> 8) & 0xff, true);
 355                 }
 356         }
 357 }
 358
 359 static int check_int_v3(struct mxc_nand_host *host)
 360 {
 361         uint32_t tmp;
 362
 363         tmp = readl(NFC_V3_IPC);
 364         if (!(tmp & NFC_V3_IPC_INT))
 365                 return 0;
 366
 367         tmp &= ~NFC_V3_IPC_INT;
 368         writel(tmp, NFC_V3_IPC);
 369
 370         return 1;
 371 }
 372
 373 static int check_int_v1_v2(struct mxc_nand_host *host)
 374 {
 375         uint32_t tmp;
 376
 377         tmp = readw(NFC_V1_V2_CONFIG2);
 378         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
 379                 return 0;
 380
 381         if (!host->devtype_data->irqpending_quirk)
 382                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
 383
 384         return 1;
 385 }
 386
 387 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
 388 {
 389         uint16_t tmp;
 390
 391         tmp = readw(NFC_V1_V2_CONFIG1);
 392
 393         if (activate)
 394                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
 395         else
 396                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
 397
 398         writew(tmp, NFC_V1_V2_CONFIG1);
 399 }
 400
 401 static void irq_control_v3(struct mxc_nand_host *host, int activate)
 402 {
 403         uint32_t tmp;
 404
 405         tmp = readl(NFC_V3_CONFIG2);
 406
 407         if (activate)
 408                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
 409         else
 410                 tmp |= NFC_V3_CONFIG2_INT_MSK;
 411
 412         writel(tmp, NFC_V3_CONFIG2);
 413 }
 414
 415 static void irq_control(struct mxc_nand_host *host, int activate)
 416 {
 417         if (host->devtype_data->irqpending_quirk) {
 418                 if (activate)
 419                         enable_irq(host->irq);
 420                 else
 421                         disable_irq_nosync(host->irq);
 422         } else {
 423                 host->devtype_data->irq_control(host, activate);
 424         }
 425 }
 426
 427 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
 428 {
 429         return readw(NFC_V1_V2_ECC_STATUS_RESULT);
 430 }
 431
 432 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
 433 {
 434         return readl(NFC_V1_V2_ECC_STATUS_RESULT);
 435 }
 436
 437 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
 438 {
 439         return readl(NFC_V3_ECC_STATUS_RESULT);
 440 }
 441
 442 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 443 {
 444         struct mxc_nand_host *host = dev_id;
 445
 446         if (!host->devtype_data->check_int(host))
 447                 return IRQ_NONE;
 448
 449         irq_control(host, 0);
 450
 451         complete(&host->op_completion);
 452
 453         return IRQ_HANDLED;
 454 }
 455
 456 /* This function polls the NANDFC to wait for the basic operation to
 457  * complete by checking the INT bit of config2 register.
 458  */
 459 static int wait_op_done(struct mxc_nand_host *host, int useirq)
 460 {
 461         int ret = 0;
 462
 463         /*
 464          * If operation is already complete, don't bother to setup an irq or a
 465          * loop.
 466          */
 467         if (host->devtype_data->check_int(host))
 468                 return 0;
 469
 470         if (useirq) {
 471                 unsigned long timeout;
 472
 473                 reinit_completion(&host->op_completion);
 474
 475                 irq_control(host, 1);
 476
 477                 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
 478                 if (!timeout && !host->devtype_data->check_int(host)) {
 479                         dev_dbg(host->dev, "timeout waiting for irq\n");
 480                         ret = -ETIMEDOUT;
 481                 }
 482         } else {
 483                 int max_retries = 8000;
 484                 int done;
 485
 486                 do {
 487                         udelay(1);
 488
 489                         done = host->devtype_data->check_int(host);
 490                         if (done)
 491                                 break;
 492
 493                 } while (--max_retries);
 494
 495                 if (!done) {
 496                         dev_dbg(host->dev, "timeout polling for completion\n");
 497                         ret = -ETIMEDOUT;
 498                 }
 499         }
 500
 501         WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
 502
 503         return ret;
 504 }
 505
 506 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 507 {
 508         /* fill command */
 509         writel(cmd, NFC_V3_FLASH_CMD);
 510
 511         /* send out command */
 512         writel(NFC_CMD, NFC_V3_LAUNCH);
 513
 514         /* Wait for operation to complete */
 515         wait_op_done(host, useirq);
 516 }
 517
 518 /* This function issues the specified command to the NAND device and
 519  * waits for completion. */
 520 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 521 {
 522         dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 523
 524         writew(cmd, NFC_V1_V2_FLASH_CMD);
 525         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
 526
 527         if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
 528                 int max_retries = 100;
 529                 /* Reset completion is indicated by NFC_CONFIG2 */
 530                 /* being set to 0 */
 531                 while (max_retries-- > 0) {
 532                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
 533                                 break;
 534                         }
 535                         udelay(1);
 536                 }
 537                 if (max_retries < 0)
 538                         dev_dbg(host->dev, "%s: RESET failed\n", __func__);
 539         } else {
 540                 /* Wait for operation to complete */
 541                 wait_op_done(host, useirq);
 542         }
 543 }
 544
 545 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
 546 {
 547         /* fill address */
 548         writel(addr, NFC_V3_FLASH_ADDR0);
 549
 550         /* send out address */
 551         writel(NFC_ADDR, NFC_V3_LAUNCH);
 552
 553         wait_op_done(host, 0);
 554 }
 555
 556 /* This function sends an address (or partial address) to the
 557  * NAND device. The address is used to select the source/destination for
 558  * a NAND command. */
 559 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
 560 {
 561         dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast);
 562
 563         writew(addr, NFC_V1_V2_FLASH_ADDR);
 564         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
 565
 566         /* Wait for operation to complete */
 567         wait_op_done(host, islast);
 568 }
 569
 570 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
 571 {
 572         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 573         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 574         uint32_t tmp;
 575
 576         tmp = readl(NFC_V3_CONFIG1);
 577         tmp &= ~(7 << 4);
 578         writel(tmp, NFC_V3_CONFIG1);
 579
 580         /* transfer data from NFC ram to nand */
 581         writel(ops, NFC_V3_LAUNCH);
 582
 583         wait_op_done(host, false);
 584 }
 585
 586 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
 587 {
 588         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 589         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 590
 591         /* NANDFC buffer 0 is used for page read/write */
 592         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 593
 594         writew(ops, NFC_V1_V2_CONFIG2);
 595
 596         /* Wait for operation to complete */
 597         wait_op_done(host, true);
 598 }
 599
 600 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
 601 {
 602         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 603         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 604         int bufs, i;
 605
 606         if (mtd->writesize > 512)
 607                 bufs = 4;
 608         else
 609                 bufs = 1;
 610
 611         for (i = 0; i < bufs; i++) {
 612
 613                 /* NANDFC buffer 0 is used for page read/write */
 614                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 615
 616                 writew(ops, NFC_V1_V2_CONFIG2);
 617
 618                 /* Wait for operation to complete */
 619                 wait_op_done(host, true);
 620         }
 621 }
 622
 623 static void send_read_id_v3(struct mxc_nand_host *host)
 624 {
 625         /* Read ID into main buffer */
 626         writel(NFC_ID, NFC_V3_LAUNCH);
 627
 628         wait_op_done(host, true);
 629
 630         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 631 }
 632
 633 /* Request the NANDFC to perform a read of the NAND device ID. */
 634 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 635 {
 636         /* NANDFC buffer 0 is used for device ID output */
 637         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 638
 639         writew(NFC_ID, NFC_V1_V2_CONFIG2);
 640
 641         /* Wait for operation to complete */
 642         wait_op_done(host, true);
 643
 644         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 645 }
 646
 647 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
 648 {
 649         writew(NFC_STATUS, NFC_V3_LAUNCH);
 650         wait_op_done(host, true);
 651
 652         return readl(NFC_V3_CONFIG1) >> 16;
 653 }
 654
 655 /* This function requests the NANDFC to perform a read of the
 656  * NAND device status and returns the current status. */
 657 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
 658 {
 659         void __iomem *main_buf = host->main_area0;
 660         uint32_t store;
 661         uint16_t ret;
 662
 663         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 664
 665         /*
 666          * The device status is stored in main_area0. To
 667          * prevent corruption of the buffer save the value
 668          * and restore it afterwards.
 669          */
 670         store = readl(main_buf);
 671
 672         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
 673         wait_op_done(host, true);
 674
 675         ret = readw(main_buf);
 676
 677         writel(store, main_buf);
 678
 679         return ret;
 680 }
 681
 682 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
 683 {
 684         struct mxc_nand_host *host = nand_get_controller_data(chip);
 685         uint16_t config1;
 686
 687         if (chip->ecc.mode != NAND_ECC_HW)
 688                 return;
 689
 690         config1 = readw(NFC_V1_V2_CONFIG1);
 691
 692         if (enable)
 693                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 694         else
 695                 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 696
 697         writew(config1, NFC_V1_V2_CONFIG1);
 698 }
 699
 700 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
 701 {
 702         struct mxc_nand_host *host = nand_get_controller_data(chip);
 703         uint32_t config2;
 704
 705         if (chip->ecc.mode != NAND_ECC_HW)
 706                 return;
 707
 708         config2 = readl(NFC_V3_CONFIG2);
 709
 710         if (enable)
 711                 config2 |= NFC_V3_CONFIG2_ECC_EN;
 712         else
 713                 config2 &= ~NFC_V3_CONFIG2_ECC_EN;
 714
 715         writel(config2, NFC_V3_CONFIG2);
 716 }
 717
 718 /* This functions is used by upper layer to checks if device is ready */
 719 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 720 {
 721         /*
 722          * NFC handles R/B internally. Therefore, this function
 723          * always returns status as ready.
 724          */
 725         return 1;
 726 }
 727
 728 static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
 729                                  bool ecc, int page)
 730 {
 731         struct mtd_info *mtd = nand_to_mtd(chip);
 732         struct mxc_nand_host *host = nand_get_controller_data(chip);
 733         unsigned int bitflips_corrected = 0;
 734         int no_subpages;
 735         int i;
 736
 737         host->devtype_data->enable_hwecc(chip, ecc);
 738
 739         host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
 740         mxc_do_addr_cycle(mtd, 0, page);
 741
 742         if (mtd->writesize > 512)
 743                 host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
 744
 745         no_subpages = mtd->writesize >> 9;
 746
 747         for (i = 0; i < no_subpages; i++) {
 748                 uint16_t ecc_stats;
 749
 750                 /* NANDFC buffer 0 is used for page read/write */
 751                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 752
 753                 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2);
 754
 755                 /* Wait for operation to complete */
 756                 wait_op_done(host, true);
 757
 758                 ecc_stats = get_ecc_status_v1(host);
 759
 760                 ecc_stats >>= 2;
 761
 762                 if (buf && ecc) {
 763                         switch (ecc_stats & 0x3) {
 764                         case 0:
 765                         default:
 766                                 break;
 767                         case 1:
 768                                 mtd->ecc_stats.corrected++;
 769                                 bitflips_corrected = 1;
 770                                 break;
 771                         case 2:
 772                                 mtd->ecc_stats.failed++;
 773                                 break;
 774                         }
 775                 }
 776         }
 777
 778         if (buf)
 779                 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
 780         if (oob)
 781                 copy_spare(mtd, true, oob);
 782
 783         return bitflips_corrected;
 784 }
 785
 786 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf,
 787                                     void *oob, bool ecc, int page)
 788 {
 789         struct mtd_info *mtd = nand_to_mtd(chip);
 790         struct mxc_nand_host *host = nand_get_controller_data(chip);
 791         unsigned int max_bitflips = 0;
 792         u32 ecc_stat, err;
 793         int no_subpages;
 794         u8 ecc_bit_mask, err_limit;
 795
 796         host->devtype_data->enable_hwecc(chip, ecc);
 797
 798         host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
 799         mxc_do_addr_cycle(mtd, 0, page);
 800
 801         if (mtd->writesize > 512)
 802                 host->devtype_data->send_cmd(host,
 803                                 NAND_CMD_READSTART, true);
 804
 805         host->devtype_data->send_page(mtd, NFC_OUTPUT);
 806
 807         if (buf)
 808                 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
 809         if (oob)
 810                 copy_spare(mtd, true, oob);
 811
 812         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
 813         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
 814
 815         no_subpages = mtd->writesize >> 9;
 816
 817         ecc_stat = host->devtype_data->get_ecc_status(host);
 818
 819         do {
 820                 err = ecc_stat & ecc_bit_mask;
 821                 if (err > err_limit) {
 822                         mtd->ecc_stats.failed++;
 823                 } else {
 824                         mtd->ecc_stats.corrected += err;
 825                         max_bitflips = max_t(unsigned int, max_bitflips, err);
 826                 }
 827
 828                 ecc_stat >>= 4;
 829         } while (--no_subpages);
 830
 831         return max_bitflips;
 832 }
 833
 834 static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 835                               uint8_t *buf, int oob_required, int page)
 836 {
 837         struct mxc_nand_host *host = nand_get_controller_data(chip);
 838         void *oob_buf;
 839
 840         if (oob_required)
 841                 oob_buf = chip->oob_poi;
 842         else
 843                 oob_buf = NULL;
 844
 845         return host->devtype_data->read_page(chip, buf, oob_buf, 1, page);
 846 }
 847
 848 static int mxc_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 849                                   uint8_t *buf, int oob_required, int page)
 850 {
 851         struct mxc_nand_host *host = nand_get_controller_data(chip);
 852         void *oob_buf;
 853
 854         if (oob_required)
 855                 oob_buf = chip->oob_poi;
 856         else
 857                 oob_buf = NULL;
 858
 859         return host->devtype_data->read_page(chip, buf, oob_buf, 0, page);
 860 }
 861
 862 static int mxc_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 863                              int page)
 864 {
 865         struct mxc_nand_host *host = nand_get_controller_data(chip);
 866
 867         return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
 868                                              page);
 869 }
 870
 871 static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
 872                                bool ecc, int page)
 873 {
 874         struct mtd_info *mtd = nand_to_mtd(chip);
 875         struct mxc_nand_host *host = nand_get_controller_data(chip);
 876
 877         host->devtype_data->enable_hwecc(chip, ecc);
 878
 879         host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false);
 880         mxc_do_addr_cycle(mtd, 0, page);
 881
 882         memcpy32_toio(host->main_area0, buf, mtd->writesize);
 883         copy_spare(mtd, false, chip->oob_poi);
 884
 885         host->devtype_data->send_page(mtd, NFC_INPUT);
 886         host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true);
 887         mxc_do_addr_cycle(mtd, 0, page);
 888
 889         return 0;
 890 }
 891
 892 static int mxc_nand_write_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
 893                                    const uint8_t *buf, int oob_required,
 894                                    int page)
 895 {
 896         return mxc_nand_write_page(chip, buf, true, page);
 897 }
 898
 899 static int mxc_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 900                                    const uint8_t *buf, int oob_required, int page)
 901 {
 902         return mxc_nand_write_page(chip, buf, false, page);
 903 }
 904
 905 static int mxc_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 906                               int page)
 907 {
 908         struct mxc_nand_host *host = nand_get_controller_data(chip);
 909
 910         memset(host->data_buf, 0xff, mtd->writesize);
 911
 912         return mxc_nand_write_page(chip, host->data_buf, false, page);
 913 }
 914
 915 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 916 {
 917         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 918         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 919         uint8_t ret;
 920
 921         /* Check for status request */
 922         if (host->status_request)
 923                 return host->devtype_data->get_dev_status(host) & 0xFF;
 924
 925         if (nand_chip->options & NAND_BUSWIDTH_16) {
 926                 /* only take the lower byte of each word */
 927                 ret = *(uint16_t *)(host->data_buf + host->buf_start);
 928
 929                 host->buf_start += 2;
 930         } else {
 931                 ret = *(uint8_t *)(host->data_buf + host->buf_start);
 932                 host->buf_start++;
 933         }
 934
 935         dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
 936         return ret;
 937 }
 938
 939 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 940 {
 941         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 942         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 943         uint16_t ret;
 944
 945         ret = *(uint16_t *)(host->data_buf + host->buf_start);
 946         host->buf_start += 2;
 947
 948         return ret;
 949 }
 950
 951 /* Write data of length len to buffer buf. The data to be
 952  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 953  * Operation by the NFC, the data is written to NAND Flash */
 954 static void mxc_nand_write_buf(struct mtd_info *mtd,
 955                                 const u_char *buf, int len)
 956 {
 957         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 958         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 959         u16 col = host->buf_start;
 960         int n = mtd->oobsize + mtd->writesize - col;
 961
 962         n = min(n, len);
 963
 964         memcpy(host->data_buf + col, buf, n);
 965
 966         host->buf_start += n;
 967 }
 968
 969 /* Read the data buffer from the NAND Flash. To read the data from NAND
 970  * Flash first the data output cycle is initiated by the NFC, which copies
 971  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 972  */
 973 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 974 {
 975         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 976         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 977         u16 col = host->buf_start;
 978         int n = mtd->oobsize + mtd->writesize - col;
 979
 980         n = min(n, len);
 981
 982         memcpy(buf, host->data_buf + col, n);
 983
 984         host->buf_start += n;
 985 }
 986
 987 /* This function is used by upper layer for select and
 988  * deselect of the NAND chip */
 989 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
 990 {
 991         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 992         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 993
 994         if (chip == -1) {
 995                 /* Disable the NFC clock */
 996                 if (host->clk_act) {
 997                         clk_disable_unprepare(host->clk);
 998                         host->clk_act = 0;
 999                 }
1000                 return;
1001         }
1002
1003         if (!host->clk_act) {
1004                 /* Enable the NFC clock */
1005                 clk_prepare_enable(host->clk);
1006                 host->clk_act = 1;
1007         }
1008 }
1009
1010 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
1011 {
1012         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1013         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1014
1015         if (chip == -1) {
1016                 /* Disable the NFC clock */
1017                 if (host->clk_act) {
1018                         clk_disable_unprepare(host->clk);
1019                         host->clk_act = 0;
1020                 }
1021                 return;
1022         }
1023
1024         if (!host->clk_act) {
1025                 /* Enable the NFC clock */
1026                 clk_prepare_enable(host->clk);
1027                 host->clk_act = 1;
1028         }
1029
1030         host->active_cs = chip;
1031         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
1032 }
1033
1034 #define MXC_V1_ECCBYTES         5
1035
1036 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
1037                                 struct mtd_oob_region *oobregion)
1038 {
1039         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1040
1041         if (section >= nand_chip->ecc.steps)
1042                 return -ERANGE;
1043
1044         oobregion->offset = (section * 16) + 6;
1045         oobregion->length = MXC_V1_ECCBYTES;
1046
1047         return 0;
1048 }
1049
1050 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
1051                                  struct mtd_oob_region *oobregion)
1052 {
1053         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1054
1055         if (section > nand_chip->ecc.steps)
1056                 return -ERANGE;
1057
1058         if (!section) {
1059                 if (mtd->writesize <= 512) {
1060                         oobregion->offset = 0;
1061                         oobregion->length = 5;
1062                 } else {
1063                         oobregion->offset = 2;
1064                         oobregion->length = 4;
1065                 }
1066         } else {
1067                 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
1068                 if (section < nand_chip->ecc.steps)
1069                         oobregion->length = (section * 16) + 6 -
1070                                             oobregion->offset;
1071                 else
1072                         oobregion->length = mtd->oobsize - oobregion->offset;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
1079         .ecc = mxc_v1_ooblayout_ecc,
1080         .free = mxc_v1_ooblayout_free,
1081 };
1082
1083 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
1084                                 struct mtd_oob_region *oobregion)
1085 {
1086         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1087         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1088
1089         if (section >= nand_chip->ecc.steps)
1090                 return -ERANGE;
1091
1092         oobregion->offset = (section * stepsize) + 7;
1093         oobregion->length = nand_chip->ecc.bytes;
1094
1095         return 0;
1096 }
1097
1098 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
1099                                  struct mtd_oob_region *oobregion)
1100 {
1101         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1102         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1103
1104         if (section >= nand_chip->ecc.steps)
1105                 return -ERANGE;
1106
1107         if (!section) {
1108                 if (mtd->writesize <= 512) {
1109                         oobregion->offset = 0;
1110                         oobregion->length = 5;
1111                 } else {
1112                         oobregion->offset = 2;
1113                         oobregion->length = 4;
1114                 }
1115         } else {
1116                 oobregion->offset = section * stepsize;
1117                 oobregion->length = 7;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
1124         .ecc = mxc_v2_ooblayout_ecc,
1125         .free = mxc_v2_ooblayout_free,
1126 };
1127
1128 /*
1129  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
1130  * on how much oob the nand chip has. For 8bit ecc we need at least
1131  * 26 bytes of oob data per 512 byte block.
1132  */
1133 static int get_eccsize(struct mtd_info *mtd)
1134 {
1135         int oobbytes_per_512 = 0;
1136
1137         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
1138
1139         if (oobbytes_per_512 < 26)
1140                 return 4;
1141         else
1142                 return 8;
1143 }
1144
1145 static void preset_v1(struct mtd_info *mtd)
1146 {
1147         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1148         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1149         uint16_t config1 = 0;
1150
1151         if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
1152                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1153
1154         if (!host->devtype_data->irqpending_quirk)
1155                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1156
1157         host->eccsize = 1;
1158
1159         writew(config1, NFC_V1_V2_CONFIG1);
1160         /* preset operation */
1161
1162         /* Unlock the internal RAM Buffer */
1163         writew(0x2, NFC_V1_V2_CONFIG);
1164
1165         /* Blocks to be unlocked */
1166         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1167         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1168
1169         /* Unlock Block Command for given address range */
1170         writew(0x4, NFC_V1_V2_WRPROT);
1171 }
1172
1173 static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd, int csline,
1174                                         const struct nand_data_interface *conf)
1175 {
1176         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1177         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1178         int tRC_min_ns, tRC_ps, ret;
1179         unsigned long rate, rate_round;
1180         const struct nand_sdr_timings *timings;
1181         u16 config1;
1182
1183         timings = nand_get_sdr_timings(conf);
1184         if (IS_ERR(timings))
1185                 return -ENOTSUPP;
1186
1187         config1 = readw(NFC_V1_V2_CONFIG1);
1188
1189         tRC_min_ns = timings->tRC_min / 1000;
1190         rate = 1000000000 / tRC_min_ns;
1191
1192         /*
1193          * For tRC < 30ns we have to use EDO mode. In this case the controller
1194          * does one access per clock cycle. Otherwise the controller does one
1195          * access in two clock cycles, thus we have to double the rate to the
1196          * controller.
1197          */
1198         if (tRC_min_ns < 30) {
1199                 rate_round = clk_round_rate(host->clk, rate);
1200                 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1201                 tRC_ps = 1000000000 / (rate_round / 1000);
1202         } else {
1203                 rate *= 2;
1204                 rate_round = clk_round_rate(host->clk, rate);
1205                 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1206                 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1207         }
1208
1209         /*
1210          * The timing values compared against are from the i.MX25 Automotive
1211          * datasheet, Table 50. NFC Timing Parameters
1212          */
1213         if (timings->tCLS_min > tRC_ps - 1000 ||
1214             timings->tCLH_min > tRC_ps - 2000 ||
1215             timings->tCS_min > tRC_ps - 1000 ||
1216             timings->tCH_min > tRC_ps - 2000 ||
1217             timings->tWP_min > tRC_ps - 1500 ||
1218             timings->tALS_min > tRC_ps ||
1219             timings->tALH_min > tRC_ps - 3000 ||
1220             timings->tDS_min > tRC_ps ||
1221             timings->tDH_min > tRC_ps - 5000 ||
1222             timings->tWC_min > 2 * tRC_ps ||
1223             timings->tWH_min > tRC_ps - 2500 ||
1224             timings->tRR_min > 6 * tRC_ps ||
1225             timings->tRP_min > 3 * tRC_ps / 2 ||
1226             timings->tRC_min > 2 * tRC_ps ||
1227             timings->tREH_min > (tRC_ps / 2) - 2500) {
1228                 dev_dbg(host->dev, "Timing out of bounds\n");
1229                 return -EINVAL;
1230         }
1231
1232         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1233                 return 0;
1234
1235         ret = clk_set_rate(host->clk, rate);
1236         if (ret)
1237                 return ret;
1238
1239         writew(config1, NFC_V1_V2_CONFIG1);
1240
1241         dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1242                 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1243                 "normal");
1244
1245         return 0;
1246 }
1247
1248 static void preset_v2(struct mtd_info *mtd)
1249 {
1250         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1251         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1252         uint16_t config1 = 0;
1253
1254         config1 |= NFC_V2_CONFIG1_FP_INT;
1255
1256         if (!host->devtype_data->irqpending_quirk)
1257                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1258
1259         if (mtd->writesize) {
1260                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1261
1262                 if (nand_chip->ecc.mode == NAND_ECC_HW)
1263                         config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1264
1265                 host->eccsize = get_eccsize(mtd);
1266                 if (host->eccsize == 4)
1267                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1268
1269                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1270         } else {
1271                 host->eccsize = 1;
1272         }
1273
1274         writew(config1, NFC_V1_V2_CONFIG1);
1275         /* preset operation */
1276
1277         /* spare area size in 16-bit half-words */
1278         writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1279
1280         /* Unlock the internal RAM Buffer */
1281         writew(0x2, NFC_V1_V2_CONFIG);
1282
1283         /* Blocks to be unlocked */
1284         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1285         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1286         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1287         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1288         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1289         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1290         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1291         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1292
1293         /* Unlock Block Command for given address range */
1294         writew(0x4, NFC_V1_V2_WRPROT);
1295 }
1296
1297 static void preset_v3(struct mtd_info *mtd)
1298 {
1299         struct nand_chip *chip = mtd_to_nand(mtd);
1300         struct mxc_nand_host *host = nand_get_controller_data(chip);
1301         uint32_t config2, config3;
1302         int i, addr_phases;
1303
1304         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1305         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1306
1307         /* Unlock the internal RAM Buffer */
1308         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1309                         NFC_V3_WRPROT);
1310
1311         /* Blocks to be unlocked */
1312         for (i = 0; i < NAND_MAX_CHIPS; i++)
1313                 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1314
1315         writel(0, NFC_V3_IPC);
1316
1317         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1318                 NFC_V3_CONFIG2_2CMD_PHASES |
1319                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1320                 NFC_V3_CONFIG2_ST_CMD(0x70) |
1321                 NFC_V3_CONFIG2_INT_MSK |
1322                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1323
1324         addr_phases = fls(chip->pagemask) >> 3;
1325
1326         if (mtd->writesize == 2048) {
1327                 config2 |= NFC_V3_CONFIG2_PS_2048;
1328                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1329         } else if (mtd->writesize == 4096) {
1330                 config2 |= NFC_V3_CONFIG2_PS_4096;
1331                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1332         } else {
1333                 config2 |= NFC_V3_CONFIG2_PS_512;
1334                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1335         }
1336
1337         if (mtd->writesize) {
1338                 if (chip->ecc.mode == NAND_ECC_HW)
1339                         config2 |= NFC_V3_CONFIG2_ECC_EN;
1340
1341                 config2 |= NFC_V3_CONFIG2_PPB(
1342                                 ffs(mtd->erasesize / mtd->writesize) - 6,
1343                                 host->devtype_data->ppb_shift);
1344                 host->eccsize = get_eccsize(mtd);
1345                 if (host->eccsize == 8)
1346                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1347         }
1348
1349         writel(config2, NFC_V3_CONFIG2);
1350
1351         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1352                         NFC_V3_CONFIG3_NO_SDMA |
1353                         NFC_V3_CONFIG3_RBB_MODE |
1354                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1355                         NFC_V3_CONFIG3_ADD_OP(0);
1356
1357         if (!(chip->options & NAND_BUSWIDTH_16))
1358                 config3 |= NFC_V3_CONFIG3_FW8;
1359
1360         writel(config3, NFC_V3_CONFIG3);
1361
1362         writel(0, NFC_V3_DELAY_LINE);
1363 }
1364
1365 /* Used by the upper layer to write command to NAND Flash for
1366  * different operations to be carried out on NAND Flash */
1367 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1368                                 int column, int page_addr)
1369 {
1370         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1371         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1372
1373         dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1374               command, column, page_addr);
1375
1376         /* Reset command state information */
1377         host->status_request = false;
1378
1379         /* Command pre-processing step */
1380         switch (command) {
1381         case NAND_CMD_RESET:
1382                 host->devtype_data->preset(mtd);
1383                 host->devtype_data->send_cmd(host, command, false);
1384                 break;
1385
1386         case NAND_CMD_STATUS:
1387                 host->buf_start = 0;
1388                 host->status_request = true;
1389
1390                 host->devtype_data->send_cmd(host, command, true);
1391                 WARN_ONCE(column != -1 || page_addr != -1,
1392                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1393                           command, column, page_addr);
1394                 mxc_do_addr_cycle(mtd, column, page_addr);
1395                 break;
1396
1397         case NAND_CMD_READID:
1398                 host->devtype_data->send_cmd(host, command, true);
1399                 mxc_do_addr_cycle(mtd, column, page_addr);
1400                 host->devtype_data->send_read_id(host);
1401                 host->buf_start = 0;
1402                 break;
1403
1404         case NAND_CMD_ERASE1:
1405         case NAND_CMD_ERASE2:
1406                 host->devtype_data->send_cmd(host, command, false);
1407                 WARN_ONCE(column != -1,
1408                           "Unexpected column value (cmd=%u, col=%d)\n",
1409                           command, column);
1410                 mxc_do_addr_cycle(mtd, column, page_addr);
1411
1412                 break;
1413         case NAND_CMD_PARAM:
1414                 host->devtype_data->send_cmd(host, command, false);
1415                 mxc_do_addr_cycle(mtd, column, page_addr);
1416                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1417                 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1418                 host->buf_start = 0;
1419                 break;
1420         default:
1421                 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1422                           command);
1423                 break;
1424         }
1425 }
1426
1427 static int mxc_nand_set_features(struct mtd_info *mtd, struct nand_chip *chip,
1428                                  int addr, u8 *subfeature_param)
1429 {
1430         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1431         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1432         int i;
1433
1434         host->buf_start = 0;
1435
1436         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1437                 chip->write_byte(mtd, subfeature_param[i]);
1438
1439         memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1440         host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1441         mxc_do_addr_cycle(mtd, addr, -1);
1442         host->devtype_data->send_page(mtd, NFC_INPUT);
1443
1444         return 0;
1445 }
1446
1447 static int mxc_nand_get_features(struct mtd_info *mtd, struct nand_chip *chip,
1448                                  int addr, u8 *subfeature_param)
1449 {
1450         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1451         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1452         int i;
1453
1454         host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1455         mxc_do_addr_cycle(mtd, addr, -1);
1456         host->devtype_data->send_page(mtd, NFC_OUTPUT);
1457         memcpy32_fromio(host->data_buf, host->main_area0, 512);
1458         host->buf_start = 0;
1459
1460         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1461                 *subfeature_param++ = chip->read_byte(mtd);
1462
1463         return 0;
1464 }
1465
1466 /*
1467  * The generic flash bbt decriptors overlap with our ecc
1468  * hardware, so define some i.MX specific ones.
1469  */
1470 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1471 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1472
1473 static struct nand_bbt_descr bbt_main_descr = {
1474         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1475             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1476         .offs = 0,
1477         .len = 4,
1478         .veroffs = 4,
1479         .maxblocks = 4,
1480         .pattern = bbt_pattern,
1481 };
1482
1483 static struct nand_bbt_descr bbt_mirror_descr = {
1484         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1485             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1486         .offs = 0,
1487         .len = 4,
1488         .veroffs = 4,
1489         .maxblocks = 4,
1490         .pattern = mirror_pattern,
1491 };
1492
1493 /* v1 + irqpending_quirk: i.MX21 */
1494 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1495         .preset = preset_v1,
1496         .read_page = mxc_nand_read_page_v1,
1497         .send_cmd = send_cmd_v1_v2,
1498         .send_addr = send_addr_v1_v2,
1499         .send_page = send_page_v1,
1500         .send_read_id = send_read_id_v1_v2,
1501         .get_dev_status = get_dev_status_v1_v2,
1502         .check_int = check_int_v1_v2,
1503         .irq_control = irq_control_v1_v2,
1504         .get_ecc_status = get_ecc_status_v1,
1505         .ooblayout = &mxc_v1_ooblayout_ops,
1506         .select_chip = mxc_nand_select_chip_v1_v3,
1507         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1508         .irqpending_quirk = 1,
1509         .needs_ip = 0,
1510         .regs_offset = 0xe00,
1511         .spare0_offset = 0x800,
1512         .spare_len = 16,
1513         .eccbytes = 3,
1514         .eccsize = 1,
1515 };
1516
1517 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1518 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1519         .preset = preset_v1,
1520         .read_page = mxc_nand_read_page_v1,
1521         .send_cmd = send_cmd_v1_v2,
1522         .send_addr = send_addr_v1_v2,
1523         .send_page = send_page_v1,
1524         .send_read_id = send_read_id_v1_v2,
1525         .get_dev_status = get_dev_status_v1_v2,
1526         .check_int = check_int_v1_v2,
1527         .irq_control = irq_control_v1_v2,
1528         .get_ecc_status = get_ecc_status_v1,
1529         .ooblayout = &mxc_v1_ooblayout_ops,
1530         .select_chip = mxc_nand_select_chip_v1_v3,
1531         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1532         .irqpending_quirk = 0,
1533         .needs_ip = 0,
1534         .regs_offset = 0xe00,
1535         .spare0_offset = 0x800,
1536         .axi_offset = 0,
1537         .spare_len = 16,
1538         .eccbytes = 3,
1539         .eccsize = 1,
1540 };
1541
1542 /* v21: i.MX25, i.MX35 */
1543 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1544         .preset = preset_v2,
1545         .read_page = mxc_nand_read_page_v2_v3,
1546         .send_cmd = send_cmd_v1_v2,
1547         .send_addr = send_addr_v1_v2,
1548         .send_page = send_page_v2,
1549         .send_read_id = send_read_id_v1_v2,
1550         .get_dev_status = get_dev_status_v1_v2,
1551         .check_int = check_int_v1_v2,
1552         .irq_control = irq_control_v1_v2,
1553         .get_ecc_status = get_ecc_status_v2,
1554         .ooblayout = &mxc_v2_ooblayout_ops,
1555         .select_chip = mxc_nand_select_chip_v2,
1556         .setup_data_interface = mxc_nand_v2_setup_data_interface,
1557         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1558         .irqpending_quirk = 0,
1559         .needs_ip = 0,
1560         .regs_offset = 0x1e00,
1561         .spare0_offset = 0x1000,
1562         .axi_offset = 0,
1563         .spare_len = 64,
1564         .eccbytes = 9,
1565         .eccsize = 0,
1566 };
1567
1568 /* v3.2a: i.MX51 */
1569 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1570         .preset = preset_v3,
1571         .read_page = mxc_nand_read_page_v2_v3,
1572         .send_cmd = send_cmd_v3,
1573         .send_addr = send_addr_v3,
1574         .send_page = send_page_v3,
1575         .send_read_id = send_read_id_v3,
1576         .get_dev_status = get_dev_status_v3,
1577         .check_int = check_int_v3,
1578         .irq_control = irq_control_v3,
1579         .get_ecc_status = get_ecc_status_v3,
1580         .ooblayout = &mxc_v2_ooblayout_ops,
1581         .select_chip = mxc_nand_select_chip_v1_v3,
1582         .enable_hwecc = mxc_nand_enable_hwecc_v3,
1583         .irqpending_quirk = 0,
1584         .needs_ip = 1,
1585         .regs_offset = 0,
1586         .spare0_offset = 0x1000,
1587         .axi_offset = 0x1e00,
1588         .spare_len = 64,
1589         .eccbytes = 0,
1590         .eccsize = 0,
1591         .ppb_shift = 7,
1592 };
1593
1594 /* v3.2b: i.MX53 */
1595 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1596         .preset = preset_v3,
1597         .read_page = mxc_nand_read_page_v2_v3,
1598         .send_cmd = send_cmd_v3,
1599         .send_addr = send_addr_v3,
1600         .send_page = send_page_v3,
1601         .send_read_id = send_read_id_v3,
1602         .get_dev_status = get_dev_status_v3,
1603         .check_int = check_int_v3,
1604         .irq_control = irq_control_v3,
1605         .get_ecc_status = get_ecc_status_v3,
1606         .ooblayout = &mxc_v2_ooblayout_ops,
1607         .select_chip = mxc_nand_select_chip_v1_v3,
1608         .enable_hwecc = mxc_nand_enable_hwecc_v3,
1609         .irqpending_quirk = 0,
1610         .needs_ip = 1,
1611         .regs_offset = 0,
1612         .spare0_offset = 0x1000,
1613         .axi_offset = 0x1e00,
1614         .spare_len = 64,
1615         .eccbytes = 0,
1616         .eccsize = 0,
1617         .ppb_shift = 8,
1618 };
1619
1620 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1621 {
1622         return host->devtype_data == &imx21_nand_devtype_data;
1623 }
1624
1625 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1626 {
1627         return host->devtype_data == &imx27_nand_devtype_data;
1628 }
1629
1630 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1631 {
1632         return host->devtype_data == &imx25_nand_devtype_data;
1633 }
1634
1635 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1636 {
1637         return host->devtype_data == &imx51_nand_devtype_data;
1638 }
1639
1640 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1641 {
1642         return host->devtype_data == &imx53_nand_devtype_data;
1643 }
1644
1645 static const struct platform_device_id mxcnd_devtype[] = {
1646         {
1647                 .name = "imx21-nand",
1648                 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1649         }, {
1650                 .name = "imx27-nand",
1651                 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1652         }, {
1653                 .name = "imx25-nand",
1654                 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1655         }, {
1656                 .name = "imx51-nand",
1657                 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1658         }, {
1659                 .name = "imx53-nand",
1660                 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1661         }, {
1662                 /* sentinel */
1663         }
1664 };
1665 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1666
1667 #ifdef CONFIG_OF
1668 static const struct of_device_id mxcnd_dt_ids[] = {
1669         {
1670                 .compatible = "fsl,imx21-nand",
1671                 .data = &imx21_nand_devtype_data,
1672         }, {
1673                 .compatible = "fsl,imx27-nand",
1674                 .data = &imx27_nand_devtype_data,
1675         }, {
1676                 .compatible = "fsl,imx25-nand",
1677                 .data = &imx25_nand_devtype_data,
1678         }, {
1679                 .compatible = "fsl,imx51-nand",
1680                 .data = &imx51_nand_devtype_data,
1681         }, {
1682                 .compatible = "fsl,imx53-nand",
1683                 .data = &imx53_nand_devtype_data,
1684         },
1685         { /* sentinel */ }
1686 };
1687 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1688
1689 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1690 {
1691         struct device_node *np = host->dev->of_node;
1692         const struct of_device_id *of_id =
1693                 of_match_device(mxcnd_dt_ids, host->dev);
1694
1695         if (!np)
1696                 return 1;
1697
1698         host->devtype_data = of_id->data;
1699
1700         return 0;
1701 }
1702 #else
1703 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1704 {
1705         return 1;
1706 }
1707 #endif
1708
1709 static int mxcnd_probe(struct platform_device *pdev)
1710 {
1711         struct nand_chip *this;
1712         struct mtd_info *mtd;
1713         struct mxc_nand_host *host;
1714         struct resource *res;
1715         int err = 0;
1716
1717         /* Allocate memory for MTD device structure and private data */
1718         host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1719                         GFP_KERNEL);
1720         if (!host)
1721                 return -ENOMEM;
1722
1723         /* allocate a temporary buffer for the nand_scan_ident() */
1724         host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1725         if (!host->data_buf)
1726                 return -ENOMEM;
1727
1728         host->dev = &pdev->dev;
1729         /* structures must be linked */
1730         this = &host->nand;
1731         mtd = nand_to_mtd(this);
1732         mtd->dev.parent = &pdev->dev;
1733         mtd->name = DRIVER_NAME;
1734
1735         /* 50 us command delay time */
1736         this->chip_delay = 5;
1737
1738         nand_set_controller_data(this, host);
1739         nand_set_flash_node(this, pdev->dev.of_node),
1740         this->dev_ready = mxc_nand_dev_ready;
1741         this->cmdfunc = mxc_nand_command;
1742         this->read_byte = mxc_nand_read_byte;
1743         this->read_word = mxc_nand_read_word;
1744         this->write_buf = mxc_nand_write_buf;
1745         this->read_buf = mxc_nand_read_buf;
1746         this->set_features = mxc_nand_set_features;
1747         this->get_features = mxc_nand_get_features;
1748
1749         host->clk = devm_clk_get(&pdev->dev, NULL);
1750         if (IS_ERR(host->clk))
1751                 return PTR_ERR(host->clk);
1752
1753         err = mxcnd_probe_dt(host);
1754         if (err > 0) {
1755                 struct mxc_nand_platform_data *pdata =
1756                                         dev_get_platdata(&pdev->dev);
1757                 if (pdata) {
1758                         host->pdata = *pdata;
1759                         host->devtype_data = (struct mxc_nand_devtype_data *)
1760                                                 pdev->id_entry->driver_data;
1761                 } else {
1762                         err = -ENODEV;
1763                 }
1764         }
1765         if (err < 0)
1766                 return err;
1767
1768         this->setup_data_interface = host->devtype_data->setup_data_interface;
1769
1770         if (host->devtype_data->needs_ip) {
1771                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1772                 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1773                 if (IS_ERR(host->regs_ip))
1774                         return PTR_ERR(host->regs_ip);
1775
1776                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1777         } else {
1778                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1779         }
1780
1781         host->base = devm_ioremap_resource(&pdev->dev, res);
1782         if (IS_ERR(host->base))
1783                 return PTR_ERR(host->base);
1784
1785         host->main_area0 = host->base;
1786
1787         if (host->devtype_data->regs_offset)
1788                 host->regs = host->base + host->devtype_data->regs_offset;
1789         host->spare0 = host->base + host->devtype_data->spare0_offset;
1790         if (host->devtype_data->axi_offset)
1791                 host->regs_axi = host->base + host->devtype_data->axi_offset;
1792
1793         this->ecc.bytes = host->devtype_data->eccbytes;
1794         host->eccsize = host->devtype_data->eccsize;
1795
1796         this->select_chip = host->devtype_data->select_chip;
1797         this->ecc.size = 512;
1798         mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1799
1800         if (host->pdata.hw_ecc) {
1801                 this->ecc.mode = NAND_ECC_HW;
1802         } else {
1803                 this->ecc.mode = NAND_ECC_SOFT;
1804                 this->ecc.algo = NAND_ECC_HAMMING;
1805         }
1806
1807         /* NAND bus width determines access functions used by upper layer */
1808         if (host->pdata.width == 2)
1809                 this->options |= NAND_BUSWIDTH_16;
1810
1811         /* update flash based bbt */
1812         if (host->pdata.flash_bbt)
1813                 this->bbt_options |= NAND_BBT_USE_FLASH;
1814
1815         init_completion(&host->op_completion);
1816
1817         host->irq = platform_get_irq(pdev, 0);
1818         if (host->irq < 0)
1819                 return host->irq;
1820
1821         /*
1822          * Use host->devtype_data->irq_control() here instead of irq_control()
1823          * because we must not disable_irq_nosync without having requested the
1824          * irq.
1825          */
1826         host->devtype_data->irq_control(host, 0);
1827
1828         err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1829                         0, DRIVER_NAME, host);
1830         if (err)
1831                 return err;
1832
1833         err = clk_prepare_enable(host->clk);
1834         if (err)
1835                 return err;
1836         host->clk_act = 1;
1837
1838         /*
1839          * Now that we "own" the interrupt make sure the interrupt mask bit is
1840          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1841          * on this machine.
1842          */
1843         if (host->devtype_data->irqpending_quirk) {
1844                 disable_irq_nosync(host->irq);
1845                 host->devtype_data->irq_control(host, 1);
1846         }
1847
1848         /* first scan to find the device and get the page size */
1849         err = nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL);
1850         if (err)
1851                 goto escan;
1852
1853         switch (this->ecc.mode) {
1854         case NAND_ECC_HW:
1855                 this->ecc.read_page = mxc_nand_read_page;
1856                 this->ecc.read_page_raw = mxc_nand_read_page_raw;
1857                 this->ecc.read_oob = mxc_nand_read_oob;
1858                 this->ecc.write_page = mxc_nand_write_page_ecc;
1859                 this->ecc.write_page_raw = mxc_nand_write_page_raw;
1860                 this->ecc.write_oob = mxc_nand_write_oob;
1861                 break;
1862
1863         case NAND_ECC_SOFT:
1864                 break;
1865
1866         default:
1867                 err = -EINVAL;
1868                 goto escan;
1869         }
1870
1871         if (this->bbt_options & NAND_BBT_USE_FLASH) {
1872                 this->bbt_td = &bbt_main_descr;
1873                 this->bbt_md = &bbt_mirror_descr;
1874         }
1875
1876         /* allocate the right size buffer now */
1877         devm_kfree(&pdev->dev, (void *)host->data_buf);
1878         host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1879                                         GFP_KERNEL);
1880         if (!host->data_buf) {
1881                 err = -ENOMEM;
1882                 goto escan;
1883         }
1884
1885         /* Call preset again, with correct writesize this time */
1886         host->devtype_data->preset(mtd);
1887
1888         if (!this->ecc.bytes) {
1889                 if (host->eccsize == 8)
1890                         this->ecc.bytes = 18;
1891                 else if (host->eccsize == 4)
1892                         this->ecc.bytes = 9;
1893         }
1894
1895         /*
1896          * Experimentation shows that i.MX NFC can only handle up to 218 oob
1897          * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1898          * into copying invalid data to/from the spare IO buffer, as this
1899          * might cause ECC data corruption when doing sub-page write to a
1900          * partially written page.
1901          */
1902         host->used_oobsize = min(mtd->oobsize, 218U);
1903
1904         if (this->ecc.mode == NAND_ECC_HW) {
1905                 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1906                         this->ecc.strength = 1;
1907                 else
1908                         this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1909         }
1910
1911         /* second phase scan */
1912         err = nand_scan_tail(mtd);
1913         if (err)
1914                 goto escan;
1915
1916         /* Register the partitions */
1917         err = mtd_device_parse_register(mtd, part_probes, NULL,
1918                                         host->pdata.parts,
1919                                         host->pdata.nr_parts);
1920         if (err)
1921                 goto cleanup_nand;
1922
1923         platform_set_drvdata(pdev, host);
1924
1925         return 0;
1926
1927 cleanup_nand:
1928         nand_cleanup(this);
1929 escan:
1930         if (host->clk_act)
1931                 clk_disable_unprepare(host->clk);
1932
1933         return err;
1934 }
1935
1936 static int mxcnd_remove(struct platform_device *pdev)
1937 {
1938         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1939
1940         nand_release(nand_to_mtd(&host->nand));
1941         if (host->clk_act)
1942                 clk_disable_unprepare(host->clk);
1943
1944         return 0;
1945 }
1946
1947 static struct platform_driver mxcnd_driver = {
1948         .driver = {
1949                    .name = DRIVER_NAME,
1950                    .of_match_table = of_match_ptr(mxcnd_dt_ids),
1951         },
1952         .id_table = mxcnd_devtype,
1953         .probe = mxcnd_probe,
1954         .remove = mxcnd_remove,
1955 };
1956 module_platform_driver(mxcnd_driver);
1957
1958 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1959 MODULE_DESCRIPTION("MXC NAND MTD driver");
1960 MODULE_LICENSE("GPL");