1 // SPDX-License-Identifier: GPL-2.0
3 * NAND Flash Controller Device Driver for DT
5 * Copyright © 2011, Picochip.
9 #include <linux/delay.h>
10 #include <linux/err.h>
12 #include <linux/ioport.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
22 struct denali_controller controller;
23 struct clk *clk; /* core clock */
24 struct clk *clk_x; /* bus interface clock */
25 struct clk *clk_ecc; /* ECC circuit clock */
26 struct reset_control *rst; /* core reset */
27 struct reset_control *rst_reg; /* register reset */
30 struct denali_dt_data {
31 unsigned int revision;
33 unsigned int oob_skip_bytes;
34 const struct nand_ecc_caps *ecc_caps;
37 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
39 static const struct denali_dt_data denali_socfpga_data = {
40 .caps = DENALI_CAP_HW_ECC_FIXUP,
42 .ecc_caps = &denali_socfpga_ecc_caps,
45 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
47 static const struct denali_dt_data denali_uniphier_v5a_data = {
48 .caps = DENALI_CAP_HW_ECC_FIXUP |
51 .ecc_caps = &denali_uniphier_v5a_ecc_caps,
54 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
56 static const struct denali_dt_data denali_uniphier_v5b_data = {
58 .caps = DENALI_CAP_HW_ECC_FIXUP |
61 .ecc_caps = &denali_uniphier_v5b_ecc_caps,
64 static const struct of_device_id denali_nand_dt_ids[] = {
66 .compatible = "altr,socfpga-denali-nand",
67 .data = &denali_socfpga_data,
70 .compatible = "socionext,uniphier-denali-nand-v5a",
71 .data = &denali_uniphier_v5a_data,
74 .compatible = "socionext,uniphier-denali-nand-v5b",
75 .data = &denali_uniphier_v5b_data,
79 MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
81 static int denali_dt_chip_init(struct denali_controller *denali,
82 struct device_node *chip_np)
84 struct denali_chip *dchip;
88 nsels = of_property_count_u32_elems(chip_np, "reg");
92 dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
99 for (i = 0; i < nsels; i++) {
100 ret = of_property_read_u32_index(chip_np, "reg", i, &bank);
104 dchip->sels[i].bank = bank;
106 nand_set_flash_node(&dchip->chip, chip_np);
109 return denali_chip_init(denali, dchip);
112 static int denali_dt_probe(struct platform_device *pdev)
114 struct device *dev = &pdev->dev;
115 struct denali_dt *dt;
116 const struct denali_dt_data *data;
117 struct denali_controller *denali;
118 struct device_node *np;
121 dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
124 denali = &dt->controller;
126 data = of_device_get_match_data(dev);
130 denali->revision = data->revision;
131 denali->caps = data->caps;
132 denali->oob_skip_bytes = data->oob_skip_bytes;
133 denali->ecc_caps = data->ecc_caps;
136 denali->irq = platform_get_irq(pdev, 0);
140 denali->reg = devm_platform_ioremap_resource_byname(pdev, "denali_reg");
141 if (IS_ERR(denali->reg))
142 return PTR_ERR(denali->reg);
144 denali->host = devm_platform_ioremap_resource_byname(pdev, "nand_data");
145 if (IS_ERR(denali->host))
146 return PTR_ERR(denali->host);
148 dt->clk = devm_clk_get(dev, "nand");
150 return PTR_ERR(dt->clk);
152 dt->clk_x = devm_clk_get(dev, "nand_x");
153 if (IS_ERR(dt->clk_x))
154 return PTR_ERR(dt->clk_x);
156 dt->clk_ecc = devm_clk_get(dev, "ecc");
157 if (IS_ERR(dt->clk_ecc))
158 return PTR_ERR(dt->clk_ecc);
160 dt->rst = devm_reset_control_get_optional_shared(dev, "nand");
162 return PTR_ERR(dt->rst);
164 dt->rst_reg = devm_reset_control_get_optional_shared(dev, "reg");
165 if (IS_ERR(dt->rst_reg))
166 return PTR_ERR(dt->rst_reg);
168 ret = clk_prepare_enable(dt->clk);
172 ret = clk_prepare_enable(dt->clk_x);
174 goto out_disable_clk;
176 ret = clk_prepare_enable(dt->clk_ecc);
178 goto out_disable_clk_x;
180 denali->clk_rate = clk_get_rate(dt->clk);
181 denali->clk_x_rate = clk_get_rate(dt->clk_x);
184 * Deassert the register reset, and the core reset in this order.
185 * Deasserting the core reset while the register reset is asserted
186 * will cause unpredictable behavior in the controller.
188 ret = reset_control_deassert(dt->rst_reg);
190 goto out_disable_clk_ecc;
192 ret = reset_control_deassert(dt->rst);
194 goto out_assert_rst_reg;
197 * When the reset is deasserted, the initialization sequence is kicked
198 * (bootstrap process). The driver must wait until it finished.
199 * Otherwise, it will result in unpredictable behavior.
201 usleep_range(200, 1000);
203 ret = denali_init(denali);
207 for_each_child_of_node(dev->of_node, np) {
208 ret = denali_dt_chip_init(denali, np);
211 goto out_remove_denali;
215 platform_set_drvdata(pdev, dt);
220 denali_remove(denali);
222 reset_control_assert(dt->rst);
224 reset_control_assert(dt->rst_reg);
226 clk_disable_unprepare(dt->clk_ecc);
228 clk_disable_unprepare(dt->clk_x);
230 clk_disable_unprepare(dt->clk);
235 static void denali_dt_remove(struct platform_device *pdev)
237 struct denali_dt *dt = platform_get_drvdata(pdev);
239 denali_remove(&dt->controller);
240 reset_control_assert(dt->rst);
241 reset_control_assert(dt->rst_reg);
242 clk_disable_unprepare(dt->clk_ecc);
243 clk_disable_unprepare(dt->clk_x);
244 clk_disable_unprepare(dt->clk);
247 static struct platform_driver denali_dt_driver = {
248 .probe = denali_dt_probe,
249 .remove_new = denali_dt_remove,
251 .name = "denali-nand-dt",
252 .of_match_table = denali_nand_dt_ids,
255 module_platform_driver(denali_dt_driver);
257 MODULE_LICENSE("GPL v2");
258 MODULE_AUTHOR("Jamie Iles");
259 MODULE_DESCRIPTION("DT driver for Denali NAND controller");