2 * Copyright (C) 2004 Embedded Edge, LLC
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/rawnand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/platform_device.h>
18 #include <asm/mach-au1x00/au1000.h>
19 #include <asm/mach-au1x00/au1550nd.h>
23 struct nand_chip chip;
27 void (*write_byte)(struct nand_chip *, u_char);
31 * au_read_byte - read one byte from the chip
32 * @this: NAND chip object
34 * read function for 8bit buswidth
36 static u_char au_read_byte(struct nand_chip *this)
38 u_char ret = readb(this->legacy.IO_ADDR_R);
39 wmb(); /* drain writebuffer */
44 * au_write_byte - write one byte to the chip
45 * @this: NAND chip object
46 * @byte: pointer to data byte to write
48 * write function for 8it buswidth
50 static void au_write_byte(struct nand_chip *this, u_char byte)
52 writeb(byte, this->legacy.IO_ADDR_W);
53 wmb(); /* drain writebuffer */
57 * au_read_byte16 - read one byte endianness aware from the chip
58 * @this: NAND chip object
60 * read function for 16bit buswidth with endianness conversion
62 static u_char au_read_byte16(struct nand_chip *this)
64 u_char ret = (u_char) cpu_to_le16(readw(this->legacy.IO_ADDR_R));
65 wmb(); /* drain writebuffer */
70 * au_write_byte16 - write one byte endianness aware to the chip
71 * @this: NAND chip object
72 * @byte: pointer to data byte to write
74 * write function for 16bit buswidth with endianness conversion
76 static void au_write_byte16(struct nand_chip *this, u_char byte)
78 writew(le16_to_cpu((u16) byte), this->legacy.IO_ADDR_W);
79 wmb(); /* drain writebuffer */
83 * au_write_buf - write buffer to chip
84 * @this: NAND chip object
86 * @len: number of bytes to write
88 * write function for 8bit buswidth
90 static void au_write_buf(struct nand_chip *this, const u_char *buf, int len)
94 for (i = 0; i < len; i++) {
95 writeb(buf[i], this->legacy.IO_ADDR_W);
96 wmb(); /* drain writebuffer */
101 * au_read_buf - read chip data into buffer
102 * @this: NAND chip object
103 * @buf: buffer to store date
104 * @len: number of bytes to read
106 * read function for 8bit buswidth
108 static void au_read_buf(struct nand_chip *this, u_char *buf, int len)
112 for (i = 0; i < len; i++) {
113 buf[i] = readb(this->legacy.IO_ADDR_R);
114 wmb(); /* drain writebuffer */
119 * au_write_buf16 - write buffer to chip
120 * @this: NAND chip object
122 * @len: number of bytes to write
124 * write function for 16bit buswidth
126 static void au_write_buf16(struct nand_chip *this, const u_char *buf, int len)
129 u16 *p = (u16 *) buf;
132 for (i = 0; i < len; i++) {
133 writew(p[i], this->legacy.IO_ADDR_W);
134 wmb(); /* drain writebuffer */
140 * au_read_buf16 - read chip data into buffer
141 * @mtd: MTD device structure
142 * @buf: buffer to store date
143 * @len: number of bytes to read
145 * read function for 16bit buswidth
147 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
150 struct nand_chip *this = mtd_to_nand(mtd);
151 u16 *p = (u16 *) buf;
154 for (i = 0; i < len; i++) {
155 p[i] = readw(this->legacy.IO_ADDR_R);
156 wmb(); /* drain writebuffer */
160 /* Select the chip by setting nCE to low */
161 #define NAND_CTL_SETNCE 1
162 /* Deselect the chip by setting nCE to high */
163 #define NAND_CTL_CLRNCE 2
164 /* Select the command latch by setting CLE to high */
165 #define NAND_CTL_SETCLE 3
166 /* Deselect the command latch by setting CLE to low */
167 #define NAND_CTL_CLRCLE 4
168 /* Select the address latch by setting ALE to high */
169 #define NAND_CTL_SETALE 5
170 /* Deselect the address latch by setting ALE to low */
171 #define NAND_CTL_CLRALE 6
173 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
175 struct nand_chip *this = mtd_to_nand(mtd);
176 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
181 case NAND_CTL_SETCLE:
182 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
185 case NAND_CTL_CLRCLE:
186 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
189 case NAND_CTL_SETALE:
190 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
193 case NAND_CTL_CLRALE:
194 this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
195 /* FIXME: Nobody knows why this is necessary,
196 * but it works only that way */
200 case NAND_CTL_SETNCE:
201 /* assert (force assert) chip enable */
202 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
205 case NAND_CTL_CLRNCE:
206 /* deassert chip enable */
207 alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
211 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W;
213 wmb(); /* Drain the writebuffer */
216 int au1550_device_ready(struct nand_chip *this)
218 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
222 * au1550_select_chip - control -CE line
223 * Forbid driving -CE manually permitting the NAND controller to do this.
224 * Keeping -CE asserted during the whole sector reads interferes with the
225 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
226 * We only have to hold -CE low for the NAND read commands since the flash
227 * chip needs it to be asserted during chip not ready time but the NAND
228 * controller keeps it released.
230 * @this: NAND chip object
231 * @chip: chipnumber to select, -1 for deselect
233 static void au1550_select_chip(struct nand_chip *this, int chip)
238 * au1550_command - Send command to NAND device
239 * @this: NAND chip object
240 * @command: the command to be sent
241 * @column: the column address for this command, -1 if none
242 * @page_addr: the page address for this command, -1 if none
244 static void au1550_command(struct nand_chip *this, unsigned command,
245 int column, int page_addr)
247 struct mtd_info *mtd = nand_to_mtd(this);
248 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
250 int ce_override = 0, i;
251 unsigned long flags = 0;
253 /* Begin command latch cycle */
254 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
256 * Write out the command to the device.
258 if (command == NAND_CMD_SEQIN) {
261 if (column >= mtd->writesize) {
263 column -= mtd->writesize;
264 readcmd = NAND_CMD_READOOB;
265 } else if (column < 256) {
266 /* First 256 bytes --> READ0 */
267 readcmd = NAND_CMD_READ0;
270 readcmd = NAND_CMD_READ1;
272 ctx->write_byte(this, readcmd);
274 ctx->write_byte(this, command);
276 /* Set ALE and clear CLE to start address cycle */
277 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
279 if (column != -1 || page_addr != -1) {
280 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
282 /* Serially input address */
284 /* Adjust columns for 16 bit buswidth */
285 if (this->options & NAND_BUSWIDTH_16 &&
286 !nand_opcode_8bits(command))
288 ctx->write_byte(this, column);
290 if (page_addr != -1) {
291 ctx->write_byte(this, (u8)(page_addr & 0xff));
293 if (command == NAND_CMD_READ0 ||
294 command == NAND_CMD_READ1 ||
295 command == NAND_CMD_READOOB) {
297 * NAND controller will release -CE after
298 * the last address byte is written, so we'll
299 * have to forcibly assert it. No interrupts
300 * are allowed while we do this as we don't
301 * want the NOR flash or PCMCIA drivers to
302 * steal our precious bytes of data...
305 local_irq_save(flags);
306 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
309 ctx->write_byte(this, (u8)(page_addr >> 8));
311 if (this->options & NAND_ROW_ADDR_3)
312 ctx->write_byte(this,
313 ((page_addr >> 16) & 0x0f));
315 /* Latch in address */
316 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
320 * Program and erase have their own busy handlers.
321 * Status and sequential in need no delay.
325 case NAND_CMD_PAGEPROG:
326 case NAND_CMD_ERASE1:
327 case NAND_CMD_ERASE2:
329 case NAND_CMD_STATUS:
337 case NAND_CMD_READOOB:
338 /* Check if we're really driving -CE low (just in case) */
339 if (unlikely(!ce_override))
342 /* Apply a short delay always to ensure that we do wait tWB. */
344 /* Wait for a chip to become ready... */
345 for (i = this->legacy.chip_delay;
346 !this->legacy.dev_ready(this) && i > 0; --i)
349 /* Release -CE and re-enable interrupts. */
350 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
351 local_irq_restore(flags);
354 /* Apply this short delay always to ensure that we do wait tWB. */
357 while(!this->legacy.dev_ready(this));
360 static int find_nand_cs(unsigned long nand_base)
363 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
364 unsigned long addr, staddr, start, mask, end;
367 for (i = 0; i < 4; i++) {
368 addr = 0x1000 + (i * 0x10); /* CSx */
369 staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
370 /* figure out the decoded range of this CS */
371 start = (staddr << 4) & 0xfffc0000;
372 mask = (staddr << 18) & 0xfffc0000;
373 end = (start | (start - 1)) & ~(start ^ mask);
374 if ((nand_base >= start) && (nand_base < end))
381 static int au1550nd_probe(struct platform_device *pdev)
383 struct au1550nd_platdata *pd;
384 struct au1550nd_ctx *ctx;
385 struct nand_chip *this;
386 struct mtd_info *mtd;
390 pd = dev_get_platdata(&pdev->dev);
392 dev_err(&pdev->dev, "missing platform data\n");
396 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
400 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
402 dev_err(&pdev->dev, "no NAND memory resource\n");
406 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
407 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
412 ctx->base = ioremap_nocache(r->start, 0x1000);
414 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
420 mtd = nand_to_mtd(this);
421 mtd->dev.parent = &pdev->dev;
423 /* figure out which CS# r->start belongs to */
424 cs = find_nand_cs(r->start);
426 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
432 this->legacy.dev_ready = au1550_device_ready;
433 this->select_chip = au1550_select_chip;
434 this->legacy.cmdfunc = au1550_command;
436 /* 30 us command delay time */
437 this->legacy.chip_delay = 30;
438 this->ecc.mode = NAND_ECC_SOFT;
439 this->ecc.algo = NAND_ECC_HAMMING;
442 this->options |= NAND_BUSWIDTH_16;
444 this->legacy.read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
445 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
446 this->legacy.write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
447 this->legacy.read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
449 ret = nand_scan(this, 1);
451 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
455 mtd_device_register(mtd, pd->parts, pd->num_parts);
457 platform_set_drvdata(pdev, ctx);
464 release_mem_region(r->start, resource_size(r));
470 static int au1550nd_remove(struct platform_device *pdev)
472 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
473 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475 nand_release(&ctx->chip);
477 release_mem_region(r->start, 0x1000);
482 static struct platform_driver au1550nd_driver = {
484 .name = "au1550-nand",
486 .probe = au1550nd_probe,
487 .remove = au1550nd_remove,
490 module_platform_driver(au1550nd_driver);
492 MODULE_LICENSE("GPL");
493 MODULE_AUTHOR("Embedded Edge, LLC");
494 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");