drivers/mtd/nand/fsl_ifc_nand.c

   1 /*
   2  * Freescale Integrated Flash Controller NAND driver
   3  *
   4  * Copyright 2011-2012 Freescale Semiconductor, Inc
   5  *
   6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/of_address.h>
  27 #include <linux/slab.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/nand.h>
  30 #include <linux/mtd/partitions.h>
  31 #include <linux/mtd/nand_ecc.h>
  32 #include <linux/fsl_ifc.h>
  33
  34 #define ERR_BYTE                0xFF /* Value returned for read
  35                                         bytes when read failed  */
  36 #define IFC_TIMEOUT_MSECS       500  /* Maximum number of mSecs to wait
  37                                         for IFC NAND Machine    */
  38
  39 struct fsl_ifc_ctrl;
  40
  41 /* mtd information per set */
  42 struct fsl_ifc_mtd {
  43         struct nand_chip chip;
  44         struct fsl_ifc_ctrl *ctrl;
  45
  46         struct device *dev;
  47         int bank;               /* Chip select bank number              */
  48         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  49         u8 __iomem *vbase;      /* Chip select base virtual address     */
  50 };
  51
  52 /* overview of the fsl ifc controller */
  53 struct fsl_ifc_nand_ctrl {
  54         struct nand_hw_control controller;
  55         struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
  56
  57         void __iomem *addr;     /* Address of assigned IFC buffer       */
  58         unsigned int page;      /* Last page written to / read from     */
  59         unsigned int read_bytes;/* Number of bytes read during command  */
  60         unsigned int column;    /* Saved column from SEQIN              */
  61         unsigned int index;     /* Pointer to next byte to 'read'       */
  62         unsigned int oob;       /* Non zero if operating on OOB data    */
  63         unsigned int eccread;   /* Non zero for a full-page ECC read    */
  64         unsigned int counter;   /* counter for the initializations      */
  65         unsigned int max_bitflips;  /* Saved during READ0 cmd           */
  66 };
  67
  68 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
  69
  70 /*
  71  * Generic flash bbt descriptors
  72  */
  73 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  74 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  75
  76 static struct nand_bbt_descr bbt_main_descr = {
  77         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  78                    NAND_BBT_2BIT | NAND_BBT_VERSION,
  79         .offs = 2, /* 0 on 8-bit small page */
  80         .len = 4,
  81         .veroffs = 6,
  82         .maxblocks = 4,
  83         .pattern = bbt_pattern,
  84 };
  85
  86 static struct nand_bbt_descr bbt_mirror_descr = {
  87         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  88                    NAND_BBT_2BIT | NAND_BBT_VERSION,
  89         .offs = 2, /* 0 on 8-bit small page */
  90         .len = 4,
  91         .veroffs = 6,
  92         .maxblocks = 4,
  93         .pattern = mirror_pattern,
  94 };
  95
  96 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
  97                                  struct mtd_oob_region *oobregion)
  98 {
  99         struct nand_chip *chip = mtd_to_nand(mtd);
 100
 101         if (section)
 102                 return -ERANGE;
 103
 104         oobregion->offset = 8;
 105         oobregion->length = chip->ecc.total;
 106
 107         return 0;
 108 }
 109
 110 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
 111                                   struct mtd_oob_region *oobregion)
 112 {
 113         struct nand_chip *chip = mtd_to_nand(mtd);
 114
 115         if (section > 1)
 116                 return -ERANGE;
 117
 118         if (mtd->writesize == 512 &&
 119             !(chip->options & NAND_BUSWIDTH_16)) {
 120                 if (!section) {
 121                         oobregion->offset = 0;
 122                         oobregion->length = 5;
 123                 } else {
 124                         oobregion->offset = 6;
 125                         oobregion->length = 2;
 126                 }
 127
 128                 return 0;
 129         }
 130
 131         if (!section) {
 132                 oobregion->offset = 2;
 133                 oobregion->length = 6;
 134         } else {
 135                 oobregion->offset = chip->ecc.total + 8;
 136                 oobregion->length = mtd->oobsize - oobregion->offset;
 137         }
 138
 139         return 0;
 140 }
 141
 142 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
 143         .ecc = fsl_ifc_ooblayout_ecc,
 144         .free = fsl_ifc_ooblayout_free,
 145 };
 146
 147 /*
 148  * Set up the IFC hardware block and page address fields, and the ifc nand
 149  * structure addr field to point to the correct IFC buffer in memory
 150  */
 151 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 152 {
 153         struct nand_chip *chip = mtd_to_nand(mtd);
 154         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 155         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 156         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 157         int buf_num;
 158
 159         ifc_nand_ctrl->page = page_addr;
 160         /* Program ROW0/COL0 */
 161         ifc_out32(page_addr, &ifc->ifc_nand.row0);
 162         ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
 163
 164         buf_num = page_addr & priv->bufnum_mask;
 165
 166         ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 167         ifc_nand_ctrl->index = column;
 168
 169         /* for OOB data point to the second half of the buffer */
 170         if (oob)
 171                 ifc_nand_ctrl->index += mtd->writesize;
 172 }
 173
 174 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
 175 {
 176         struct nand_chip *chip = mtd_to_nand(mtd);
 177         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 178         u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 179         u32 __iomem *mainarea = (u32 __iomem *)addr;
 180         u8 __iomem *oob = addr + mtd->writesize;
 181         struct mtd_oob_region oobregion = { };
 182         int i, section = 0;
 183
 184         for (i = 0; i < mtd->writesize / 4; i++) {
 185                 if (__raw_readl(&mainarea[i]) != 0xffffffff)
 186                         return 0;
 187         }
 188
 189         mtd_ooblayout_ecc(mtd, section++, &oobregion);
 190         while (oobregion.length) {
 191                 for (i = 0; i < oobregion.length; i++) {
 192                         if (__raw_readb(&oob[oobregion.offset + i]) != 0xff)
 193                                 return 0;
 194                 }
 195
 196                 mtd_ooblayout_ecc(mtd, section++, &oobregion);
 197         }
 198
 199         return 1;
 200 }
 201
 202 /* returns nonzero if entire page is blank */
 203 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 204                           u32 *eccstat, unsigned int bufnum)
 205 {
 206         u32 reg = eccstat[bufnum / 4];
 207         int errors;
 208
 209         errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
 210
 211         return errors;
 212 }
 213
 214 /*
 215  * execute IFC NAND command and wait for it to complete
 216  */
 217 static void fsl_ifc_run_command(struct mtd_info *mtd)
 218 {
 219         struct nand_chip *chip = mtd_to_nand(mtd);
 220         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 221         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 222         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 223         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 224         u32 eccstat[4];
 225         int i;
 226
 227         /* set the chip select for NAND Transaction */
 228         ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
 229                   &ifc->ifc_nand.nand_csel);
 230
 231         dev_vdbg(priv->dev,
 232                         "%s: fir0=%08x fcr0=%08x\n",
 233                         __func__,
 234                         ifc_in32(&ifc->ifc_nand.nand_fir0),
 235                         ifc_in32(&ifc->ifc_nand.nand_fcr0));
 236
 237         ctrl->nand_stat = 0;
 238
 239         /* start read/write seq */
 240         ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 241
 242         /* wait for command complete flag or timeout */
 243         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 244                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 245
 246         /* ctrl->nand_stat will be updated from IRQ context */
 247         if (!ctrl->nand_stat)
 248                 dev_err(priv->dev, "Controller is not responding\n");
 249         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
 250                 dev_err(priv->dev, "NAND Flash Timeout Error\n");
 251         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
 252                 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
 253
 254         nctrl->max_bitflips = 0;
 255
 256         if (nctrl->eccread) {
 257                 int errors;
 258                 int bufnum = nctrl->page & priv->bufnum_mask;
 259                 int sector = bufnum * chip->ecc.steps;
 260                 int sector_end = sector + chip->ecc.steps - 1;
 261                 __be32 *eccstat_regs;
 262
 263                 if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
 264                         eccstat_regs = ifc->ifc_nand.v2_nand_eccstat;
 265                 else
 266                         eccstat_regs = ifc->ifc_nand.v1_nand_eccstat;
 267
 268                 for (i = sector / 4; i <= sector_end / 4; i++)
 269                         eccstat[i] = ifc_in32(&eccstat_regs[i]);
 270
 271                 for (i = sector; i <= sector_end; i++) {
 272                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 273
 274                         if (errors == 15) {
 275                                 /*
 276                                  * Uncorrectable error.
 277                                  * OK only if the whole page is blank.
 278                                  *
 279                                  * We disable ECCER reporting due to...
 280                                  * erratum IFC-A002770 -- so report it now if we
 281                                  * see an uncorrectable error in ECCSTAT.
 282                                  */
 283                                 if (!is_blank(mtd, bufnum))
 284                                         ctrl->nand_stat |=
 285                                                 IFC_NAND_EVTER_STAT_ECCER;
 286                                 break;
 287                         }
 288
 289                         mtd->ecc_stats.corrected += errors;
 290                         nctrl->max_bitflips = max_t(unsigned int,
 291                                                     nctrl->max_bitflips,
 292                                                     errors);
 293                 }
 294
 295                 nctrl->eccread = 0;
 296         }
 297 }
 298
 299 static void fsl_ifc_do_read(struct nand_chip *chip,
 300                             int oob,
 301                             struct mtd_info *mtd)
 302 {
 303         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 304         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 305         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 306
 307         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 308         if (mtd->writesize > 512) {
 309                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 310                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 311                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 312                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 313                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
 314                           &ifc->ifc_nand.nand_fir0);
 315                 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
 316
 317                 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 318                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
 319                           &ifc->ifc_nand.nand_fcr0);
 320         } else {
 321                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 322                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 323                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 324                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
 325                           &ifc->ifc_nand.nand_fir0);
 326                 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
 327
 328                 if (oob)
 329                         ifc_out32(NAND_CMD_READOOB <<
 330                                   IFC_NAND_FCR0_CMD0_SHIFT,
 331                                   &ifc->ifc_nand.nand_fcr0);
 332                 else
 333                         ifc_out32(NAND_CMD_READ0 <<
 334                                   IFC_NAND_FCR0_CMD0_SHIFT,
 335                                   &ifc->ifc_nand.nand_fcr0);
 336         }
 337 }
 338
 339 /* cmdfunc send commands to the IFC NAND Machine */
 340 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 341                              int column, int page_addr) {
 342         struct nand_chip *chip = mtd_to_nand(mtd);
 343         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 344         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 345         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 346
 347         /* clear the read buffer */
 348         ifc_nand_ctrl->read_bytes = 0;
 349         if (command != NAND_CMD_PAGEPROG)
 350                 ifc_nand_ctrl->index = 0;
 351
 352         switch (command) {
 353         /* READ0 read the entire buffer to use hardware ECC. */
 354         case NAND_CMD_READ0:
 355                 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 356                 set_addr(mtd, 0, page_addr, 0);
 357
 358                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 359                 ifc_nand_ctrl->index += column;
 360
 361                 if (chip->ecc.mode == NAND_ECC_HW)
 362                         ifc_nand_ctrl->eccread = 1;
 363
 364                 fsl_ifc_do_read(chip, 0, mtd);
 365                 fsl_ifc_run_command(mtd);
 366                 return;
 367
 368         /* READOOB reads only the OOB because no ECC is performed. */
 369         case NAND_CMD_READOOB:
 370                 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
 371                 set_addr(mtd, column, page_addr, 1);
 372
 373                 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 374
 375                 fsl_ifc_do_read(chip, 1, mtd);
 376                 fsl_ifc_run_command(mtd);
 377
 378                 return;
 379
 380         case NAND_CMD_READID:
 381         case NAND_CMD_PARAM: {
 382                 int timing = IFC_FIR_OP_RB;
 383                 if (command == NAND_CMD_PARAM)
 384                         timing = IFC_FIR_OP_RBCD;
 385
 386                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 387                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 388                           (timing << IFC_NAND_FIR0_OP2_SHIFT),
 389                           &ifc->ifc_nand.nand_fir0);
 390                 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
 391                           &ifc->ifc_nand.nand_fcr0);
 392                 ifc_out32(column, &ifc->ifc_nand.row3);
 393
 394                 /*
 395                  * although currently it's 8 bytes for READID, we always read
 396                  * the maximum 256 bytes(for PARAM)
 397                  */
 398                 ifc_out32(256, &ifc->ifc_nand.nand_fbcr);
 399                 ifc_nand_ctrl->read_bytes = 256;
 400
 401                 set_addr(mtd, 0, 0, 0);
 402                 fsl_ifc_run_command(mtd);
 403                 return;
 404         }
 405
 406         /* ERASE1 stores the block and page address */
 407         case NAND_CMD_ERASE1:
 408                 set_addr(mtd, 0, page_addr, 0);
 409                 return;
 410
 411         /* ERASE2 uses the block and page address from ERASE1 */
 412         case NAND_CMD_ERASE2:
 413                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 414                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 415                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
 416                           &ifc->ifc_nand.nand_fir0);
 417
 418                 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 419                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
 420                           &ifc->ifc_nand.nand_fcr0);
 421
 422                 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 423                 ifc_nand_ctrl->read_bytes = 0;
 424                 fsl_ifc_run_command(mtd);
 425                 return;
 426
 427         /* SEQIN sets up the addr buffer and all registers except the length */
 428         case NAND_CMD_SEQIN: {
 429                 u32 nand_fcr0;
 430                 ifc_nand_ctrl->column = column;
 431                 ifc_nand_ctrl->oob = 0;
 432
 433                 if (mtd->writesize > 512) {
 434                         nand_fcr0 =
 435                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 436                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 437                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 438
 439                         ifc_out32(
 440                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 441                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 442                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 443                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
 444                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
 445                                 &ifc->ifc_nand.nand_fir0);
 446                         ifc_out32(
 447                                 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 448                                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
 449                                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
 450                                 &ifc->ifc_nand.nand_fir1);
 451                 } else {
 452                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 453                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 454                                     (NAND_CMD_SEQIN <<
 455                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 456                                     (NAND_CMD_STATUS <<
 457                                         IFC_NAND_FCR0_CMD3_SHIFT));
 458
 459                         ifc_out32(
 460                                 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 461                                 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 462                                 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 463                                 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 464                                 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
 465                                 &ifc->ifc_nand.nand_fir0);
 466                         ifc_out32(
 467                                 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 468                                 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 469                                 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
 470                                 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
 471                                 &ifc->ifc_nand.nand_fir1);
 472
 473                         if (column >= mtd->writesize)
 474                                 nand_fcr0 |=
 475                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 476                         else
 477                                 nand_fcr0 |=
 478                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 479                 }
 480
 481                 if (column >= mtd->writesize) {
 482                         /* OOB area --> READOOB */
 483                         column -= mtd->writesize;
 484                         ifc_nand_ctrl->oob = 1;
 485                 }
 486                 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
 487                 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
 488                 return;
 489         }
 490
 491         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 492         case NAND_CMD_PAGEPROG: {
 493                 if (ifc_nand_ctrl->oob) {
 494                         ifc_out32(ifc_nand_ctrl->index -
 495                                   ifc_nand_ctrl->column,
 496                                   &ifc->ifc_nand.nand_fbcr);
 497                 } else {
 498                         ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 499                 }
 500
 501                 fsl_ifc_run_command(mtd);
 502                 return;
 503         }
 504
 505         case NAND_CMD_STATUS: {
 506                 void __iomem *addr;
 507
 508                 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 509                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
 510                           &ifc->ifc_nand.nand_fir0);
 511                 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 512                           &ifc->ifc_nand.nand_fcr0);
 513                 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
 514                 set_addr(mtd, 0, 0, 0);
 515                 ifc_nand_ctrl->read_bytes = 1;
 516
 517                 fsl_ifc_run_command(mtd);
 518
 519                 /*
 520                  * The chip always seems to report that it is
 521                  * write-protected, even when it is not.
 522                  */
 523                 addr = ifc_nand_ctrl->addr;
 524                 if (chip->options & NAND_BUSWIDTH_16)
 525                         ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
 526                 else
 527                         ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
 528                 return;
 529         }
 530
 531         case NAND_CMD_RESET:
 532                 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
 533                           &ifc->ifc_nand.nand_fir0);
 534                 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
 535                           &ifc->ifc_nand.nand_fcr0);
 536                 fsl_ifc_run_command(mtd);
 537                 return;
 538
 539         default:
 540                 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
 541                                         __func__, command);
 542         }
 543 }
 544
 545 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 546 {
 547         /* The hardware does not seem to support multiple
 548          * chips per bank.
 549          */
 550 }
 551
 552 /*
 553  * Write buf to the IFC NAND Controller Data Buffer
 554  */
 555 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 556 {
 557         struct nand_chip *chip = mtd_to_nand(mtd);
 558         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 559         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 560
 561         if (len <= 0) {
 562                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 563                 return;
 564         }
 565
 566         if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
 567                 dev_err(priv->dev,
 568                         "%s: beyond end of buffer (%d requested, %u available)\n",
 569                         __func__, len, bufsize - ifc_nand_ctrl->index);
 570                 len = bufsize - ifc_nand_ctrl->index;
 571         }
 572
 573         memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
 574         ifc_nand_ctrl->index += len;
 575 }
 576
 577 /*
 578  * Read a byte from either the IFC hardware buffer
 579  * read function for 8-bit buswidth
 580  */
 581 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
 582 {
 583         struct nand_chip *chip = mtd_to_nand(mtd);
 584         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 585         unsigned int offset;
 586
 587         /*
 588          * If there are still bytes in the IFC buffer, then use the
 589          * next byte.
 590          */
 591         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 592                 offset = ifc_nand_ctrl->index++;
 593                 return ifc_in8(ifc_nand_ctrl->addr + offset);
 594         }
 595
 596         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 597         return ERR_BYTE;
 598 }
 599
 600 /*
 601  * Read two bytes from the IFC hardware buffer
 602  * read function for 16-bit buswith
 603  */
 604 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 605 {
 606         struct nand_chip *chip = mtd_to_nand(mtd);
 607         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 608         uint16_t data;
 609
 610         /*
 611          * If there are still bytes in the IFC buffer, then use the
 612          * next byte.
 613          */
 614         if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 615                 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
 616                 ifc_nand_ctrl->index += 2;
 617                 return (uint8_t) data;
 618         }
 619
 620         dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 621         return ERR_BYTE;
 622 }
 623
 624 /*
 625  * Read from the IFC Controller Data Buffer
 626  */
 627 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 628 {
 629         struct nand_chip *chip = mtd_to_nand(mtd);
 630         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 631         int avail;
 632
 633         if (len < 0) {
 634                 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 635                 return;
 636         }
 637
 638         avail = min((unsigned int)len,
 639                         ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
 640         memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
 641         ifc_nand_ctrl->index += avail;
 642
 643         if (len > avail)
 644                 dev_err(priv->dev,
 645                         "%s: beyond end of buffer (%d requested, %d available)\n",
 646                         __func__, len, avail);
 647 }
 648
 649 /*
 650  * This function is called after Program and Erase Operations to
 651  * check for success or failure.
 652  */
 653 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 654 {
 655         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 656         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 657         struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 658         u32 nand_fsr;
 659
 660         /* Use READ_STATUS command, but wait for the device to be ready */
 661         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 662                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
 663                   &ifc->ifc_nand.nand_fir0);
 664         ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 665                   &ifc->ifc_nand.nand_fcr0);
 666         ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
 667         set_addr(mtd, 0, 0, 0);
 668         ifc_nand_ctrl->read_bytes = 1;
 669
 670         fsl_ifc_run_command(mtd);
 671
 672         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 673
 674         /*
 675          * The chip always seems to report that it is
 676          * write-protected, even when it is not.
 677          */
 678         return nand_fsr | NAND_STATUS_WP;
 679 }
 680
 681 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 682                              uint8_t *buf, int oob_required, int page)
 683 {
 684         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 685         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 686         struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 687
 688         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 689         if (oob_required)
 690                 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 691
 692         if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
 693                 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
 694
 695         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 696                 mtd->ecc_stats.failed++;
 697
 698         return nctrl->max_bitflips;
 699 }
 700
 701 /* ECC will be calculated automatically, and errors will be detected in
 702  * waitfunc.
 703  */
 704 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 705                                const uint8_t *buf, int oob_required, int page)
 706 {
 707         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 708         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 709
 710         return 0;
 711 }
 712
 713 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
 714 {
 715         struct nand_chip *chip = mtd_to_nand(mtd);
 716         struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 717
 718         dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 719                                                         chip->numchips);
 720         dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
 721                                                         chip->chipsize);
 722         dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
 723                                                         chip->pagemask);
 724         dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
 725                                                         chip->chip_delay);
 726         dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
 727                                                         chip->badblockpos);
 728         dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
 729                                                         chip->chip_shift);
 730         dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
 731                                                         chip->page_shift);
 732         dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
 733                                                         chip->phys_erase_shift);
 734         dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
 735                                                         chip->ecc.mode);
 736         dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
 737                                                         chip->ecc.steps);
 738         dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
 739                                                         chip->ecc.bytes);
 740         dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
 741                                                         chip->ecc.total);
 742         dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
 743                                                         mtd->ooblayout);
 744         dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
 745         dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
 746         dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
 747                                                         mtd->erasesize);
 748         dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
 749                                                         mtd->writesize);
 750         dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
 751                                                         mtd->oobsize);
 752
 753         return 0;
 754 }
 755
 756 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 757 {
 758         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 759         struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 760         struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
 761         uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
 762         uint32_t cs = priv->bank;
 763
 764         /* Save CSOR and CSOR_ext */
 765         csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
 766         csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
 767
 768         /* chage PageSize 8K and SpareSize 1K*/
 769         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 770         ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
 771         ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
 772
 773         /* READID */
 774         ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 775                     (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 776                     (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
 777                     &ifc_runtime->ifc_nand.nand_fir0);
 778         ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
 779                     &ifc_runtime->ifc_nand.nand_fcr0);
 780         ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
 781
 782         ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
 783
 784         /* Program ROW0/COL0 */
 785         ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
 786         ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
 787
 788         /* set the chip select for NAND Transaction */
 789         ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
 790                 &ifc_runtime->ifc_nand.nand_csel);
 791
 792         /* start read seq */
 793         ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
 794                 &ifc_runtime->ifc_nand.nandseq_strt);
 795
 796         /* wait for command complete flag or timeout */
 797         wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 798                            msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 799
 800         if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 801                 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
 802
 803         /* Restore CSOR and CSOR_ext */
 804         ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
 805         ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
 806 }
 807
 808 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 809 {
 810         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 811         struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
 812         struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 813         struct nand_chip *chip = &priv->chip;
 814         struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 815         u32 csor;
 816
 817         /* Fill in fsl_ifc_mtd structure */
 818         mtd->dev.parent = priv->dev;
 819         nand_set_flash_node(chip, priv->dev->of_node);
 820
 821         /* fill in nand_chip structure */
 822         /* set up function call table */
 823         if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
 824                 & CSPR_PORT_SIZE_16)
 825                 chip->read_byte = fsl_ifc_read_byte16;
 826         else
 827                 chip->read_byte = fsl_ifc_read_byte;
 828
 829         chip->write_buf = fsl_ifc_write_buf;
 830         chip->read_buf = fsl_ifc_read_buf;
 831         chip->select_chip = fsl_ifc_select_chip;
 832         chip->cmdfunc = fsl_ifc_cmdfunc;
 833         chip->waitfunc = fsl_ifc_wait;
 834
 835         chip->bbt_td = &bbt_main_descr;
 836         chip->bbt_md = &bbt_mirror_descr;
 837
 838         ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
 839
 840         /* set up nand options */
 841         chip->bbt_options = NAND_BBT_USE_FLASH;
 842         chip->options = NAND_NO_SUBPAGE_WRITE;
 843
 844         if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
 845                 & CSPR_PORT_SIZE_16) {
 846                 chip->read_byte = fsl_ifc_read_byte16;
 847                 chip->options |= NAND_BUSWIDTH_16;
 848         } else {
 849                 chip->read_byte = fsl_ifc_read_byte;
 850         }
 851
 852         chip->controller = &ifc_nand_ctrl->controller;
 853         nand_set_controller_data(chip, priv);
 854
 855         chip->ecc.read_page = fsl_ifc_read_page;
 856         chip->ecc.write_page = fsl_ifc_write_page;
 857
 858         csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
 859
 860         switch (csor & CSOR_NAND_PGS_MASK) {
 861         case CSOR_NAND_PGS_512:
 862                 if (!(chip->options & NAND_BUSWIDTH_16)) {
 863                         /* Avoid conflict with bad block marker */
 864                         bbt_main_descr.offs = 0;
 865                         bbt_mirror_descr.offs = 0;
 866                 }
 867
 868                 priv->bufnum_mask = 15;
 869                 break;
 870
 871         case CSOR_NAND_PGS_2K:
 872                 priv->bufnum_mask = 3;
 873                 break;
 874
 875         case CSOR_NAND_PGS_4K:
 876                 priv->bufnum_mask = 1;
 877                 break;
 878
 879         case CSOR_NAND_PGS_8K:
 880                 priv->bufnum_mask = 0;
 881                 break;
 882
 883         default:
 884                 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
 885                 return -ENODEV;
 886         }
 887
 888         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
 889         if (csor & CSOR_NAND_ECC_DEC_EN) {
 890                 chip->ecc.mode = NAND_ECC_HW;
 891                 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
 892
 893                 /* Hardware generates ECC per 512 Bytes */
 894                 chip->ecc.size = 512;
 895                 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
 896                         chip->ecc.bytes = 8;
 897                         chip->ecc.strength = 4;
 898                 } else {
 899                         chip->ecc.bytes = 16;
 900                         chip->ecc.strength = 8;
 901                 }
 902         } else {
 903                 chip->ecc.mode = NAND_ECC_SOFT;
 904                 chip->ecc.algo = NAND_ECC_HAMMING;
 905         }
 906
 907         if (ctrl->version == FSL_IFC_VERSION_1_1_0)
 908                 fsl_ifc_sram_init(priv);
 909
 910         return 0;
 911 }
 912
 913 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
 914 {
 915         struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 916
 917         nand_release(mtd);
 918
 919         kfree(mtd->name);
 920
 921         if (priv->vbase)
 922                 iounmap(priv->vbase);
 923
 924         ifc_nand_ctrl->chips[priv->bank] = NULL;
 925
 926         return 0;
 927 }
 928
 929 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
 930                       phys_addr_t addr)
 931 {
 932         u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
 933
 934         if (!(cspr & CSPR_V))
 935                 return 0;
 936         if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
 937                 return 0;
 938
 939         return (cspr & CSPR_BA) == convert_ifc_address(addr);
 940 }
 941
 942 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
 943
 944 static int fsl_ifc_nand_probe(struct platform_device *dev)
 945 {
 946         struct fsl_ifc_runtime __iomem *ifc;
 947         struct fsl_ifc_mtd *priv;
 948         struct resource res;
 949         static const char *part_probe_types[]
 950                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
 951         int ret;
 952         int bank;
 953         struct device_node *node = dev->dev.of_node;
 954         struct mtd_info *mtd;
 955
 956         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
 957                 return -ENODEV;
 958         ifc = fsl_ifc_ctrl_dev->rregs;
 959
 960         /* get, allocate and map the memory resource */
 961         ret = of_address_to_resource(node, 0, &res);
 962         if (ret) {
 963                 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
 964                 return ret;
 965         }
 966
 967         /* find which chip select it is connected to */
 968         for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
 969                 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
 970                         break;
 971         }
 972
 973         if (bank >= fsl_ifc_ctrl_dev->banks) {
 974                 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
 975                         __func__);
 976                 return -ENODEV;
 977         }
 978
 979         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
 980         if (!priv)
 981                 return -ENOMEM;
 982
 983         mutex_lock(&fsl_ifc_nand_mutex);
 984         if (!fsl_ifc_ctrl_dev->nand) {
 985                 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
 986                 if (!ifc_nand_ctrl) {
 987                         mutex_unlock(&fsl_ifc_nand_mutex);
 988                         return -ENOMEM;
 989                 }
 990
 991                 ifc_nand_ctrl->read_bytes = 0;
 992                 ifc_nand_ctrl->index = 0;
 993                 ifc_nand_ctrl->addr = NULL;
 994                 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
 995
 996                 nand_hw_control_init(&ifc_nand_ctrl->controller);
 997         } else {
 998                 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
 999         }
1000         mutex_unlock(&fsl_ifc_nand_mutex);
1001
1002         ifc_nand_ctrl->chips[bank] = priv;
1003         priv->bank = bank;
1004         priv->ctrl = fsl_ifc_ctrl_dev;
1005         priv->dev = &dev->dev;
1006
1007         priv->vbase = ioremap(res.start, resource_size(&res));
1008         if (!priv->vbase) {
1009                 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1010                 ret = -ENOMEM;
1011                 goto err;
1012         }
1013
1014         dev_set_drvdata(priv->dev, priv);
1015
1016         ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1017                   IFC_NAND_EVTER_EN_FTOER_EN |
1018                   IFC_NAND_EVTER_EN_WPER_EN,
1019                   &ifc->ifc_nand.nand_evter_en);
1020
1021         /* enable NAND Machine Interrupts */
1022         ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1023                   IFC_NAND_EVTER_INTR_FTOERIR_EN |
1024                   IFC_NAND_EVTER_INTR_WPERIR_EN,
1025                   &ifc->ifc_nand.nand_evter_intr_en);
1026
1027         mtd = nand_to_mtd(&priv->chip);
1028         mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1029         if (!mtd->name) {
1030                 ret = -ENOMEM;
1031                 goto err;
1032         }
1033
1034         ret = fsl_ifc_chip_init(priv);
1035         if (ret)
1036                 goto err;
1037
1038         ret = nand_scan_ident(mtd, 1, NULL);
1039         if (ret)
1040                 goto err;
1041
1042         ret = fsl_ifc_chip_init_tail(mtd);
1043         if (ret)
1044                 goto err;
1045
1046         ret = nand_scan_tail(mtd);
1047         if (ret)
1048                 goto err;
1049
1050         /* First look for RedBoot table or partitions on the command
1051          * line, these take precedence over device tree information */
1052         mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1053
1054         dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1055                  (unsigned long long)res.start, priv->bank);
1056         return 0;
1057
1058 err:
1059         fsl_ifc_chip_remove(priv);
1060         return ret;
1061 }
1062
1063 static int fsl_ifc_nand_remove(struct platform_device *dev)
1064 {
1065         struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1066
1067         fsl_ifc_chip_remove(priv);
1068
1069         mutex_lock(&fsl_ifc_nand_mutex);
1070         ifc_nand_ctrl->counter--;
1071         if (!ifc_nand_ctrl->counter) {
1072                 fsl_ifc_ctrl_dev->nand = NULL;
1073                 kfree(ifc_nand_ctrl);
1074         }
1075         mutex_unlock(&fsl_ifc_nand_mutex);
1076
1077         return 0;
1078 }
1079
1080 static const struct of_device_id fsl_ifc_nand_match[] = {
1081         {
1082                 .compatible = "fsl,ifc-nand",
1083         },
1084         {}
1085 };
1086 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1087
1088 static struct platform_driver fsl_ifc_nand_driver = {
1089         .driver = {
1090                 .name   = "fsl,ifc-nand",
1091                 .of_match_table = fsl_ifc_nand_match,
1092         },
1093         .probe       = fsl_ifc_nand_probe,
1094         .remove      = fsl_ifc_nand_remove,
1095 };
1096
1097 module_platform_driver(fsl_ifc_nand_driver);
1098
1099 MODULE_LICENSE("GPL");
1100 MODULE_AUTHOR("Freescale");
1101 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");