drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <kernel@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include <linux/pm_runtime.h>
  31 #include "sdhci-pltfm.h"
  32 #include "sdhci-esdhc.h"
  33
  34 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  35 #define ESDHC_CTRL_D3CD                 0x08
  36 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  37 /* VENDOR SPEC register */
  38 #define ESDHC_VENDOR_SPEC               0xc0
  39 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  40 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  41 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  42 #define ESDHC_WTMK_LVL                  0x44
  43 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  44 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  45 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  46 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  47 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  48 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  49 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  50 #define ESDHC_MIX_CTRL                  0x48
  51 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  52 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  53 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  54 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  55 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  56 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  57 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  58 /* Bits 3 and 6 are not SDHCI standard definitions */
  59 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  60 /* Tuning bits */
  61 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  62
  63 /* dll control register */
  64 #define ESDHC_DLL_CTRL                  0x60
  65 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  66 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  67
  68 /* tune control register */
  69 #define ESDHC_TUNE_CTRL_STATUS          0x68
  70 #define  ESDHC_TUNE_CTRL_STEP           1
  71 #define  ESDHC_TUNE_CTRL_MIN            0
  72 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  73
  74 /* strobe dll register */
  75 #define ESDHC_STROBE_DLL_CTRL           0x70
  76 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  77 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  78 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  79
  80 #define ESDHC_STROBE_DLL_STATUS         0x74
  81 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  82 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  83
  84 #define ESDHC_TUNING_CTRL               0xcc
  85 #define ESDHC_STD_TUNING_EN             (1 << 24)
  86 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  87 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
  88 #define ESDHC_TUNING_START_TAP_MASK     0xff
  89 #define ESDHC_TUNING_STEP_MASK          0x00070000
  90 #define ESDHC_TUNING_STEP_SHIFT         16
  91
  92 /* pinctrl state */
  93 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  94 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  95
  96 /*
  97  * Our interpretation of the SDHCI_HOST_CONTROL register
  98  */
  99 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 100 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 101 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 102
 103 /*
 104  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 105  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 106  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 107  * Define this macro DMA error INT for fsl eSDHC
 108  */
 109 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 110
 111 /*
 112  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 113  * "11" when the STOP CMD12 is issued on imx53 to abort one
 114  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 115  * be generated.
 116  * In exact block transfer, the controller doesn't complete the
 117  * operations automatically as required at the end of the
 118  * transfer and remains on hold if the abort command is not sent.
 119  * As a result, the TC flag is not asserted and SW received timeout
 120  * exception. Bit1 of Vendor Spec register is used to fix it.
 121  */
 122 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 123 /*
 124  * The flag tells that the ESDHC controller is an USDHC block that is
 125  * integrated on the i.MX6 series.
 126  */
 127 #define ESDHC_FLAG_USDHC                BIT(3)
 128 /* The IP supports manual tuning process */
 129 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 130 /* The IP supports standard tuning process */
 131 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 132 /* The IP has SDHCI_CAPABILITIES_1 register */
 133 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 134 /*
 135  * The IP has erratum ERR004536
 136  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 137  * when reading data from the card
 138  * This flag is also set for i.MX25 and i.MX35 in order to get
 139  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 140  */
 141 #define ESDHC_FLAG_ERR004536            BIT(7)
 142 /* The IP supports HS200 mode */
 143 #define ESDHC_FLAG_HS200                BIT(8)
 144 /* The IP supports HS400 mode */
 145 #define ESDHC_FLAG_HS400                BIT(9)
 146
 147 /* A clock frequency higher than this rate requires strobe dll control */
 148 #define ESDHC_STROBE_DLL_CLK_FREQ       100000000
 149
 150 struct esdhc_soc_data {
 151         u32 flags;
 152 };
 153
 154 static struct esdhc_soc_data esdhc_imx25_data = {
 155         .flags = ESDHC_FLAG_ERR004536,
 156 };
 157
 158 static struct esdhc_soc_data esdhc_imx35_data = {
 159         .flags = ESDHC_FLAG_ERR004536,
 160 };
 161
 162 static struct esdhc_soc_data esdhc_imx51_data = {
 163         .flags = 0,
 164 };
 165
 166 static struct esdhc_soc_data esdhc_imx53_data = {
 167         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 168 };
 169
 170 static struct esdhc_soc_data usdhc_imx6q_data = {
 171         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 172 };
 173
 174 static struct esdhc_soc_data usdhc_imx6sl_data = {
 175         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 176                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 177                         | ESDHC_FLAG_HS200,
 178 };
 179
 180 static struct esdhc_soc_data usdhc_imx6sx_data = {
 181         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 182                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
 183 };
 184
 185 static struct esdhc_soc_data usdhc_imx7d_data = {
 186         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 187                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 188                         | ESDHC_FLAG_HS400,
 189 };
 190
 191 struct pltfm_imx_data {
 192         u32 scratchpad;
 193         struct pinctrl *pinctrl;
 194         struct pinctrl_state *pins_default;
 195         struct pinctrl_state *pins_100mhz;
 196         struct pinctrl_state *pins_200mhz;
 197         const struct esdhc_soc_data *socdata;
 198         struct esdhc_platform_data boarddata;
 199         struct clk *clk_ipg;
 200         struct clk *clk_ahb;
 201         struct clk *clk_per;
 202         unsigned int actual_clock;
 203         enum {
 204                 NO_CMD_PENDING,      /* no multiblock command pending */
 205                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 206                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 207         } multiblock_status;
 208         u32 is_ddr;
 209 };
 210
 211 static const struct platform_device_id imx_esdhc_devtype[] = {
 212         {
 213                 .name = "sdhci-esdhc-imx25",
 214                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 215         }, {
 216                 .name = "sdhci-esdhc-imx35",
 217                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 218         }, {
 219                 .name = "sdhci-esdhc-imx51",
 220                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 221         }, {
 222                 /* sentinel */
 223         }
 224 };
 225 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 226
 227 static const struct of_device_id imx_esdhc_dt_ids[] = {
 228         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 229         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 230         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 231         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 232         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 233         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 234         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 235         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 236         { /* sentinel */ }
 237 };
 238 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 239
 240 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 241 {
 242         return data->socdata == &esdhc_imx25_data;
 243 }
 244
 245 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 246 {
 247         return data->socdata == &esdhc_imx53_data;
 248 }
 249
 250 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 251 {
 252         return data->socdata == &usdhc_imx6q_data;
 253 }
 254
 255 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 256 {
 257         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 258 }
 259
 260 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 261 {
 262         void __iomem *base = host->ioaddr + (reg & ~0x3);
 263         u32 shift = (reg & 0x3) * 8;
 264
 265         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 266 }
 267
 268 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 269 {
 270         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 271         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 272         u32 val = readl(host->ioaddr + reg);
 273
 274         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 275                 u32 fsl_prss = val;
 276                 /* save the least 20 bits */
 277                 val = fsl_prss & 0x000FFFFF;
 278                 /* move dat[0-3] bits */
 279                 val |= (fsl_prss & 0x0F000000) >> 4;
 280                 /* move cmd line bit */
 281                 val |= (fsl_prss & 0x00800000) << 1;
 282         }
 283
 284         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 285                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 286                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 287                         val &= 0xffff0000;
 288
 289                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 290                  * ADMA2 capability of esdhc, but this bit is messed up on
 291                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 292                  * don't actually support ADMA2). So set the BROKEN_ADMA
 293                  * quirk on MX25/35 platforms.
 294                  */
 295
 296                 if (val & SDHCI_CAN_DO_ADMA1) {
 297                         val &= ~SDHCI_CAN_DO_ADMA1;
 298                         val |= SDHCI_CAN_DO_ADMA2;
 299                 }
 300         }
 301
 302         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 303                 if (esdhc_is_usdhc(imx_data)) {
 304                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 305                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 306                         else
 307                                 /* imx6q/dl does not have cap_1 register, fake one */
 308                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 309                                         | SDHCI_SUPPORT_SDR50
 310                                         | SDHCI_USE_SDR50_TUNING
 311                                         | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
 312
 313                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
 314                                 val |= SDHCI_SUPPORT_HS400;
 315
 316                         /*
 317                          * Do not advertise faster UHS modes if there are no
 318                          * pinctrl states for 100MHz/200MHz.
 319                          */
 320                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
 321                             IS_ERR_OR_NULL(imx_data->pins_200mhz))
 322                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
 323                                          | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 324                 }
 325         }
 326
 327         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 328                 val = 0;
 329                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 330                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 331                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 332         }
 333
 334         if (unlikely(reg == SDHCI_INT_STATUS)) {
 335                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 336                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 337                         val |= SDHCI_INT_ADMA_ERROR;
 338                 }
 339
 340                 /*
 341                  * mask off the interrupt we get in response to the manually
 342                  * sent CMD12
 343                  */
 344                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 345                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 346                         val &= ~SDHCI_INT_RESPONSE;
 347                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 348                                                    SDHCI_INT_STATUS);
 349                         imx_data->multiblock_status = NO_CMD_PENDING;
 350                 }
 351         }
 352
 353         return val;
 354 }
 355
 356 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 357 {
 358         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 359         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 360         u32 data;
 361
 362         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 363                         reg == SDHCI_INT_STATUS)) {
 364                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 365                         /*
 366                          * Clear and then set D3CD bit to avoid missing the
 367                          * card interrupt. This is an eSDHC controller problem
 368                          * so we need to apply the following workaround: clear
 369                          * and set D3CD bit will make eSDHC re-sample the card
 370                          * interrupt. In case a card interrupt was lost,
 371                          * re-sample it by the following steps.
 372                          */
 373                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 374                         data &= ~ESDHC_CTRL_D3CD;
 375                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 376                         data |= ESDHC_CTRL_D3CD;
 377                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 378                 }
 379
 380                 if (val & SDHCI_INT_ADMA_ERROR) {
 381                         val &= ~SDHCI_INT_ADMA_ERROR;
 382                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 383                 }
 384         }
 385
 386         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 387                                 && (reg == SDHCI_INT_STATUS)
 388                                 && (val & SDHCI_INT_DATA_END))) {
 389                         u32 v;
 390                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 391                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 392                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 393
 394                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 395                         {
 396                                 /* send a manual CMD12 with RESPTYP=none */
 397                                 data = MMC_STOP_TRANSMISSION << 24 |
 398                                        SDHCI_CMD_ABORTCMD << 16;
 399                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 400                                 imx_data->multiblock_status = WAIT_FOR_INT;
 401                         }
 402         }
 403
 404         writel(val, host->ioaddr + reg);
 405 }
 406
 407 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 408 {
 409         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 410         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 411         u16 ret = 0;
 412         u32 val;
 413
 414         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 415                 reg ^= 2;
 416                 if (esdhc_is_usdhc(imx_data)) {
 417                         /*
 418                          * The usdhc register returns a wrong host version.
 419                          * Correct it here.
 420                          */
 421                         return SDHCI_SPEC_300;
 422                 }
 423         }
 424
 425         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 426                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 427                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 428                         ret |= SDHCI_CTRL_VDD_180;
 429
 430                 if (esdhc_is_usdhc(imx_data)) {
 431                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 432                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 433                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 434                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 435                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 436                 }
 437
 438                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 439                         ret |= SDHCI_CTRL_EXEC_TUNING;
 440                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 441                         ret |= SDHCI_CTRL_TUNED_CLK;
 442
 443                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 444
 445                 return ret;
 446         }
 447
 448         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 449                 if (esdhc_is_usdhc(imx_data)) {
 450                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 451                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 452                         /* Swap AC23 bit */
 453                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 454                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 455                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 456                         }
 457                 } else {
 458                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 459                 }
 460
 461                 return ret;
 462         }
 463
 464         return readw(host->ioaddr + reg);
 465 }
 466
 467 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 468 {
 469         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 470         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 471         u32 new_val = 0;
 472
 473         switch (reg) {
 474         case SDHCI_CLOCK_CONTROL:
 475                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 476                 if (val & SDHCI_CLOCK_CARD_EN)
 477                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 478                 else
 479                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 480                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 481                 return;
 482         case SDHCI_HOST_CONTROL2:
 483                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 484                 if (val & SDHCI_CTRL_VDD_180)
 485                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 486                 else
 487                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 488                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 489                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 490                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 491                         if (val & SDHCI_CTRL_TUNED_CLK) {
 492                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 493                                 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 494                         } else {
 495                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 496                                 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 497                         }
 498                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 499                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 500                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 501                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 502                         if (val & SDHCI_CTRL_TUNED_CLK) {
 503                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 504                         } else {
 505                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 506                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 507                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 508                         }
 509
 510                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 511                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 512                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 513                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 514                         } else {
 515                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 516                         }
 517
 518                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
 519                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 520                 }
 521                 return;
 522         case SDHCI_TRANSFER_MODE:
 523                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 524                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 525                                 && (host->cmd->data->blocks > 1)
 526                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 527                         u32 v;
 528                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 529                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 530                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 531                 }
 532
 533                 if (esdhc_is_usdhc(imx_data)) {
 534                         u32 wml;
 535                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 536                         /* Swap AC23 bit */
 537                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 538                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 539                                 val |= ESDHC_MIX_CTRL_AC23EN;
 540                         }
 541                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 542                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 543
 544                         /* Set watermark levels for PIO access to maximum value
 545                          * (128 words) to accommodate full 512 bytes buffer.
 546                          * For DMA access restore the levels to default value.
 547                          */
 548                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 549                         if (val & SDHCI_TRNS_DMA)
 550                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 551                         else
 552                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 553                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 554                                ESDHC_WTMK_LVL_WR_WML_MASK);
 555                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 556                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 557                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 558                 } else {
 559                         /*
 560                          * Postpone this write, we must do it together with a
 561                          * command write that is down below.
 562                          */
 563                         imx_data->scratchpad = val;
 564                 }
 565                 return;
 566         case SDHCI_COMMAND:
 567                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 568                         val |= SDHCI_CMD_ABORTCMD;
 569
 570                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 571                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 572                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 573
 574                 if (esdhc_is_usdhc(imx_data))
 575                         writel(val << 16,
 576                                host->ioaddr + SDHCI_TRANSFER_MODE);
 577                 else
 578                         writel(val << 16 | imx_data->scratchpad,
 579                                host->ioaddr + SDHCI_TRANSFER_MODE);
 580                 return;
 581         case SDHCI_BLOCK_SIZE:
 582                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 583                 break;
 584         }
 585         esdhc_clrset_le(host, 0xffff, val, reg);
 586 }
 587
 588 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 589 {
 590         u8 ret;
 591         u32 val;
 592
 593         switch (reg) {
 594         case SDHCI_HOST_CONTROL:
 595                 val = readl(host->ioaddr + reg);
 596
 597                 ret = val & SDHCI_CTRL_LED;
 598                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 599                 ret |= (val & ESDHC_CTRL_4BITBUS);
 600                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 601                 return ret;
 602         }
 603
 604         return readb(host->ioaddr + reg);
 605 }
 606
 607 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 608 {
 609         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 610         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 611         u32 new_val = 0;
 612         u32 mask;
 613
 614         switch (reg) {
 615         case SDHCI_POWER_CONTROL:
 616                 /*
 617                  * FSL put some DMA bits here
 618                  * If your board has a regulator, code should be here
 619                  */
 620                 return;
 621         case SDHCI_HOST_CONTROL:
 622                 /* FSL messed up here, so we need to manually compose it. */
 623                 new_val = val & SDHCI_CTRL_LED;
 624                 /* ensure the endianness */
 625                 new_val |= ESDHC_HOST_CONTROL_LE;
 626                 /* bits 8&9 are reserved on mx25 */
 627                 if (!is_imx25_esdhc(imx_data)) {
 628                         /* DMA mode bits are shifted */
 629                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 630                 }
 631
 632                 /*
 633                  * Do not touch buswidth bits here. This is done in
 634                  * esdhc_pltfm_bus_width.
 635                  * Do not touch the D3CD bit either which is used for the
 636                  * SDIO interrupt erratum workaround.
 637                  */
 638                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 639
 640                 esdhc_clrset_le(host, mask, new_val, reg);
 641                 return;
 642         case SDHCI_SOFTWARE_RESET:
 643                 if (val & SDHCI_RESET_DATA)
 644                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 645                 break;
 646         }
 647         esdhc_clrset_le(host, 0xff, val, reg);
 648
 649         if (reg == SDHCI_SOFTWARE_RESET) {
 650                 if (val & SDHCI_RESET_ALL) {
 651                         /*
 652                          * The esdhc has a design violation to SDHC spec which
 653                          * tells that software reset should not affect card
 654                          * detection circuit. But esdhc clears its SYSCTL
 655                          * register bits [0..2] during the software reset. This
 656                          * will stop those clocks that card detection circuit
 657                          * relies on. To work around it, we turn the clocks on
 658                          * back to keep card detection circuit functional.
 659                          */
 660                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 661                         /*
 662                          * The reset on usdhc fails to clear MIX_CTRL register.
 663                          * Do it manually here.
 664                          */
 665                         if (esdhc_is_usdhc(imx_data)) {
 666                                 /*
 667                                  * the tuning bits should be kept during reset
 668                                  */
 669                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 670                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 671                                                 host->ioaddr + ESDHC_MIX_CTRL);
 672                                 imx_data->is_ddr = 0;
 673                         }
 674                 } else if (val & SDHCI_RESET_DATA) {
 675                         /*
 676                          * The eSDHC DAT line software reset clears at least the
 677                          * data transfer width on i.MX25, so make sure that the
 678                          * Host Control register is unaffected.
 679                          */
 680                         esdhc_clrset_le(host, 0xff, new_val,
 681                                         SDHCI_HOST_CONTROL);
 682                 }
 683         }
 684 }
 685
 686 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 687 {
 688         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 689
 690         return pltfm_host->clock;
 691 }
 692
 693 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 694 {
 695         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 696
 697         return pltfm_host->clock / 256 / 16;
 698 }
 699
 700 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 701                                          unsigned int clock)
 702 {
 703         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 704         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 705         unsigned int host_clock = pltfm_host->clock;
 706         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 707         int pre_div = 1;
 708         int div = 1;
 709         u32 temp, val;
 710
 711         if (clock == 0) {
 712                 host->mmc->actual_clock = 0;
 713
 714                 if (esdhc_is_usdhc(imx_data)) {
 715                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 716                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 717                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 718                 }
 719                 return;
 720         }
 721
 722         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 723         if (is_imx53_esdhc(imx_data)) {
 724                 /*
 725                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 726                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 727                  */
 728                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 729                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 730                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 731                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 732                 if (temp & BIT(10))
 733                         pre_div = 2;
 734         }
 735
 736         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 737         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 738                 | ESDHC_CLOCK_MASK);
 739         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 740
 741         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 742                         pre_div < 256)
 743                 pre_div *= 2;
 744
 745         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 746                 div++;
 747
 748         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 749         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 750                 clock, host->mmc->actual_clock);
 751
 752         pre_div >>= 1;
 753         div--;
 754
 755         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 756         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 757                 | (div << ESDHC_DIVIDER_SHIFT)
 758                 | (pre_div << ESDHC_PREDIV_SHIFT));
 759         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 760
 761         if (esdhc_is_usdhc(imx_data)) {
 762                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 763                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 764                 host->ioaddr + ESDHC_VENDOR_SPEC);
 765         }
 766
 767         mdelay(1);
 768 }
 769
 770 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 771 {
 772         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 773         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 774         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 775
 776         switch (boarddata->wp_type) {
 777         case ESDHC_WP_GPIO:
 778                 return mmc_gpio_get_ro(host->mmc);
 779         case ESDHC_WP_CONTROLLER:
 780                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 781                                SDHCI_WRITE_PROTECT);
 782         case ESDHC_WP_NONE:
 783                 break;
 784         }
 785
 786         return -ENOSYS;
 787 }
 788
 789 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 790 {
 791         u32 ctrl;
 792
 793         switch (width) {
 794         case MMC_BUS_WIDTH_8:
 795                 ctrl = ESDHC_CTRL_8BITBUS;
 796                 break;
 797         case MMC_BUS_WIDTH_4:
 798                 ctrl = ESDHC_CTRL_4BITBUS;
 799                 break;
 800         default:
 801                 ctrl = 0;
 802                 break;
 803         }
 804
 805         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 806                         SDHCI_HOST_CONTROL);
 807 }
 808
 809 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 810 {
 811         u32 reg;
 812
 813         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 814         mdelay(1);
 815
 816         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 817         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 818                         ESDHC_MIX_CTRL_FBCLK_SEL;
 819         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 820         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 821         dev_dbg(mmc_dev(host->mmc),
 822                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 823                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 824 }
 825
 826 static void esdhc_post_tuning(struct sdhci_host *host)
 827 {
 828         u32 reg;
 829
 830         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 831         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 832         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 833         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 834 }
 835
 836 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 837 {
 838         int min, max, avg, ret;
 839
 840         /* find the mininum delay first which can pass tuning */
 841         min = ESDHC_TUNE_CTRL_MIN;
 842         while (min < ESDHC_TUNE_CTRL_MAX) {
 843                 esdhc_prepare_tuning(host, min);
 844                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
 845                         break;
 846                 min += ESDHC_TUNE_CTRL_STEP;
 847         }
 848
 849         /* find the maxinum delay which can not pass tuning */
 850         max = min + ESDHC_TUNE_CTRL_STEP;
 851         while (max < ESDHC_TUNE_CTRL_MAX) {
 852                 esdhc_prepare_tuning(host, max);
 853                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
 854                         max -= ESDHC_TUNE_CTRL_STEP;
 855                         break;
 856                 }
 857                 max += ESDHC_TUNE_CTRL_STEP;
 858         }
 859
 860         /* use average delay to get the best timing */
 861         avg = (min + max) / 2;
 862         esdhc_prepare_tuning(host, avg);
 863         ret = mmc_send_tuning(host->mmc, opcode, NULL);
 864         esdhc_post_tuning(host);
 865
 866         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
 867                 ret ? "failed" : "passed", avg, ret);
 868
 869         return ret;
 870 }
 871
 872 static int esdhc_change_pinstate(struct sdhci_host *host,
 873                                                 unsigned int uhs)
 874 {
 875         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 876         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 877         struct pinctrl_state *pinctrl;
 878
 879         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 880
 881         if (IS_ERR(imx_data->pinctrl) ||
 882                 IS_ERR(imx_data->pins_default) ||
 883                 IS_ERR(imx_data->pins_100mhz) ||
 884                 IS_ERR(imx_data->pins_200mhz))
 885                 return -EINVAL;
 886
 887         switch (uhs) {
 888         case MMC_TIMING_UHS_SDR50:
 889         case MMC_TIMING_UHS_DDR50:
 890                 pinctrl = imx_data->pins_100mhz;
 891                 break;
 892         case MMC_TIMING_UHS_SDR104:
 893         case MMC_TIMING_MMC_HS200:
 894         case MMC_TIMING_MMC_HS400:
 895                 pinctrl = imx_data->pins_200mhz;
 896                 break;
 897         default:
 898                 /* back to default state for other legacy timing */
 899                 pinctrl = imx_data->pins_default;
 900         }
 901
 902         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 903 }
 904
 905 /*
 906  * For HS400 eMMC, there is a data_strobe line. This signal is generated
 907  * by the device and used for data output and CRC status response output
 908  * in HS400 mode. The frequency of this signal follows the frequency of
 909  * CLK generated by host. The host receives the data which is aligned to the
 910  * edge of data_strobe line. Due to the time delay between CLK line and
 911  * data_strobe line, if the delay time is larger than one clock cycle,
 912  * then CLK and data_strobe line will be misaligned, read error shows up.
 913  * So when the CLK is higher than 100MHz, each clock cycle is short enough,
 914  * host should configure the delay target.
 915  */
 916 static void esdhc_set_strobe_dll(struct sdhci_host *host)
 917 {
 918         u32 v;
 919
 920         if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
 921                 /* disable clock before enabling strobe dll */
 922                 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
 923                        ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 924                        host->ioaddr + ESDHC_VENDOR_SPEC);
 925
 926                 /* force a reset on strobe dll */
 927                 writel(ESDHC_STROBE_DLL_CTRL_RESET,
 928                         host->ioaddr + ESDHC_STROBE_DLL_CTRL);
 929                 /*
 930                  * enable strobe dll ctrl and adjust the delay target
 931                  * for the uSDHC loopback read clock
 932                  */
 933                 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
 934                         (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
 935                 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
 936                 /* wait 1us to make sure strobe dll status register stable */
 937                 udelay(1);
 938                 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
 939                 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
 940                         dev_warn(mmc_dev(host->mmc),
 941                                 "warning! HS400 strobe DLL status REF not lock!\n");
 942                 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
 943                         dev_warn(mmc_dev(host->mmc),
 944                                 "warning! HS400 strobe DLL status SLV not lock!\n");
 945         }
 946 }
 947
 948 static void esdhc_reset_tuning(struct sdhci_host *host)
 949 {
 950         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 951         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 952         u32 ctrl;
 953
 954         /* Reset the tuning circuit */
 955         if (esdhc_is_usdhc(imx_data)) {
 956                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 957                         ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
 958                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 959                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 960                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
 961                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 962                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 963                         ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 964                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 965                         writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR);
 966                 }
 967         }
 968 }
 969
 970 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 971 {
 972         u32 m;
 973         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 974         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 975         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 976
 977         /* disable ddr mode and disable HS400 mode */
 978         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 979         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
 980         imx_data->is_ddr = 0;
 981
 982         switch (timing) {
 983         case MMC_TIMING_UHS_SDR12:
 984         case MMC_TIMING_UHS_SDR25:
 985         case MMC_TIMING_UHS_SDR50:
 986         case MMC_TIMING_UHS_SDR104:
 987         case MMC_TIMING_MMC_HS200:
 988                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 989                 break;
 990         case MMC_TIMING_UHS_DDR50:
 991         case MMC_TIMING_MMC_DDR52:
 992                 m |= ESDHC_MIX_CTRL_DDREN;
 993                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 994                 imx_data->is_ddr = 1;
 995                 if (boarddata->delay_line) {
 996                         u32 v;
 997                         v = boarddata->delay_line <<
 998                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
 999                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1000                         if (is_imx53_esdhc(imx_data))
1001                                 v <<= 1;
1002                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1003                 }
1004                 break;
1005         case MMC_TIMING_MMC_HS400:
1006                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1007                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1008                 imx_data->is_ddr = 1;
1009                 /* update clock after enable DDR for strobe DLL lock */
1010                 host->ops->set_clock(host, host->clock);
1011                 esdhc_set_strobe_dll(host);
1012                 break;
1013         case MMC_TIMING_LEGACY:
1014         default:
1015                 esdhc_reset_tuning(host);
1016                 break;
1017         }
1018
1019         esdhc_change_pinstate(host, timing);
1020 }
1021
1022 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1023 {
1024         sdhci_reset(host, mask);
1025
1026         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1027         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1028 }
1029
1030 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1031 {
1032         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1033         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1034
1035         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1036         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1037 }
1038
1039 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1040 {
1041         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1042         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1043
1044         /* use maximum timeout counter */
1045         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1046                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1047                         SDHCI_TIMEOUT_CONTROL);
1048 }
1049
1050 static struct sdhci_ops sdhci_esdhc_ops = {
1051         .read_l = esdhc_readl_le,
1052         .read_w = esdhc_readw_le,
1053         .read_b = esdhc_readb_le,
1054         .write_l = esdhc_writel_le,
1055         .write_w = esdhc_writew_le,
1056         .write_b = esdhc_writeb_le,
1057         .set_clock = esdhc_pltfm_set_clock,
1058         .get_max_clock = esdhc_pltfm_get_max_clock,
1059         .get_min_clock = esdhc_pltfm_get_min_clock,
1060         .get_max_timeout_count = esdhc_get_max_timeout_count,
1061         .get_ro = esdhc_pltfm_get_ro,
1062         .set_timeout = esdhc_set_timeout,
1063         .set_bus_width = esdhc_pltfm_set_bus_width,
1064         .set_uhs_signaling = esdhc_set_uhs_signaling,
1065         .reset = esdhc_reset,
1066 };
1067
1068 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1069         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1070                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1071                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1072                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1073         .ops = &sdhci_esdhc_ops,
1074 };
1075
1076 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1077 {
1078         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1079         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1080         int tmp;
1081
1082         if (esdhc_is_usdhc(imx_data)) {
1083                 /*
1084                  * The imx6q ROM code will change the default watermark
1085                  * level setting to something insane.  Change it back here.
1086                  */
1087                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1088
1089                 /*
1090                  * ROM code will change the bit burst_length_enable setting
1091                  * to zero if this usdhc is chosen to boot system. Change
1092                  * it back here, otherwise it will impact the performance a
1093                  * lot. This bit is used to enable/disable the burst length
1094                  * for the external AHB2AXI bridge. It's useful especially
1095                  * for INCR transfer because without burst length indicator,
1096                  * the AHB2AXI bridge does not know the burst length in
1097                  * advance. And without burst length indicator, AHB INCR
1098                  * transfer can only be converted to singles on the AXI side.
1099                  */
1100                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1101                         | ESDHC_BURST_LEN_EN_INCR,
1102                         host->ioaddr + SDHCI_HOST_CONTROL);
1103                 /*
1104                 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1105                 * TO1.1, it's harmless for MX6SL
1106                 */
1107                 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1108                         host->ioaddr + 0x6c);
1109
1110                 /* disable DLL_CTRL delay line settings */
1111                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1112
1113                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1114                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1115                         tmp |= ESDHC_STD_TUNING_EN |
1116                                 ESDHC_TUNING_START_TAP_DEFAULT;
1117                         if (imx_data->boarddata.tuning_start_tap) {
1118                                 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1119                                 tmp |= imx_data->boarddata.tuning_start_tap;
1120                         }
1121
1122                         if (imx_data->boarddata.tuning_step) {
1123                                 tmp &= ~ESDHC_TUNING_STEP_MASK;
1124                                 tmp |= imx_data->boarddata.tuning_step
1125                                         << ESDHC_TUNING_STEP_SHIFT;
1126                         }
1127                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1128                 }
1129         }
1130 }
1131
1132 #ifdef CONFIG_OF
1133 static int
1134 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1135                          struct sdhci_host *host,
1136                          struct pltfm_imx_data *imx_data)
1137 {
1138         struct device_node *np = pdev->dev.of_node;
1139         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1140         int ret;
1141
1142         if (of_get_property(np, "fsl,wp-controller", NULL))
1143                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1144
1145         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1146         if (gpio_is_valid(boarddata->wp_gpio))
1147                 boarddata->wp_type = ESDHC_WP_GPIO;
1148
1149         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1150         of_property_read_u32(np, "fsl,tuning-start-tap",
1151                              &boarddata->tuning_start_tap);
1152
1153         if (of_find_property(np, "no-1-8-v", NULL))
1154                 boarddata->support_vsel = false;
1155         else
1156                 boarddata->support_vsel = true;
1157
1158         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1159                 boarddata->delay_line = 0;
1160
1161         mmc_of_parse_voltage(np, &host->ocr_mask);
1162
1163         /* sdr50 and sdr104 need work on 1.8v signal voltage */
1164         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1165             !IS_ERR(imx_data->pins_default)) {
1166                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1167                                                 ESDHC_PINCTRL_STATE_100MHZ);
1168                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1169                                                 ESDHC_PINCTRL_STATE_200MHZ);
1170         }
1171
1172         /* call to generic mmc_of_parse to support additional capabilities */
1173         ret = mmc_of_parse(host->mmc);
1174         if (ret)
1175                 return ret;
1176
1177         if (mmc_gpio_get_cd(host->mmc) >= 0)
1178                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1179
1180         return 0;
1181 }
1182 #else
1183 static inline int
1184 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1185                          struct sdhci_host *host,
1186                          struct pltfm_imx_data *imx_data)
1187 {
1188         return -ENODEV;
1189 }
1190 #endif
1191
1192 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1193                          struct sdhci_host *host,
1194                          struct pltfm_imx_data *imx_data)
1195 {
1196         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1197         int err;
1198
1199         if (!host->mmc->parent->platform_data) {
1200                 dev_err(mmc_dev(host->mmc), "no board data!\n");
1201                 return -EINVAL;
1202         }
1203
1204         imx_data->boarddata = *((struct esdhc_platform_data *)
1205                                 host->mmc->parent->platform_data);
1206         /* write_protect */
1207         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1208                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1209                 if (err) {
1210                         dev_err(mmc_dev(host->mmc),
1211                                 "failed to request write-protect gpio!\n");
1212                         return err;
1213                 }
1214                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1215         }
1216
1217         /* card_detect */
1218         switch (boarddata->cd_type) {
1219         case ESDHC_CD_GPIO:
1220                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1221                 if (err) {
1222                         dev_err(mmc_dev(host->mmc),
1223                                 "failed to request card-detect gpio!\n");
1224                         return err;
1225                 }
1226                 /* fall through */
1227
1228         case ESDHC_CD_CONTROLLER:
1229                 /* we have a working card_detect back */
1230                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1231                 break;
1232
1233         case ESDHC_CD_PERMANENT:
1234                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1235                 break;
1236
1237         case ESDHC_CD_NONE:
1238                 break;
1239         }
1240
1241         switch (boarddata->max_bus_width) {
1242         case 8:
1243                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1244                 break;
1245         case 4:
1246                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1247                 break;
1248         case 1:
1249         default:
1250                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1251                 break;
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1258 {
1259         const struct of_device_id *of_id =
1260                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1261         struct sdhci_pltfm_host *pltfm_host;
1262         struct sdhci_host *host;
1263         int err;
1264         struct pltfm_imx_data *imx_data;
1265
1266         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1267                                 sizeof(*imx_data));
1268         if (IS_ERR(host))
1269                 return PTR_ERR(host);
1270
1271         pltfm_host = sdhci_priv(host);
1272
1273         imx_data = sdhci_pltfm_priv(pltfm_host);
1274
1275         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1276                                                   pdev->id_entry->driver_data;
1277
1278         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1279         if (IS_ERR(imx_data->clk_ipg)) {
1280                 err = PTR_ERR(imx_data->clk_ipg);
1281                 goto free_sdhci;
1282         }
1283
1284         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1285         if (IS_ERR(imx_data->clk_ahb)) {
1286                 err = PTR_ERR(imx_data->clk_ahb);
1287                 goto free_sdhci;
1288         }
1289
1290         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1291         if (IS_ERR(imx_data->clk_per)) {
1292                 err = PTR_ERR(imx_data->clk_per);
1293                 goto free_sdhci;
1294         }
1295
1296         pltfm_host->clk = imx_data->clk_per;
1297         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1298         err = clk_prepare_enable(imx_data->clk_per);
1299         if (err)
1300                 goto free_sdhci;
1301         err = clk_prepare_enable(imx_data->clk_ipg);
1302         if (err)
1303                 goto disable_per_clk;
1304         err = clk_prepare_enable(imx_data->clk_ahb);
1305         if (err)
1306                 goto disable_ipg_clk;
1307
1308         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1309         if (IS_ERR(imx_data->pinctrl)) {
1310                 err = PTR_ERR(imx_data->pinctrl);
1311                 goto disable_ahb_clk;
1312         }
1313
1314         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1315                                                 PINCTRL_STATE_DEFAULT);
1316         if (IS_ERR(imx_data->pins_default))
1317                 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1318
1319         if (esdhc_is_usdhc(imx_data)) {
1320                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1321                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1322                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1323                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1324
1325                 /* clear tuning bits in case ROM has set it already */
1326                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1327                 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
1328                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1329         }
1330
1331         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1332                 sdhci_esdhc_ops.platform_execute_tuning =
1333                                         esdhc_executing_tuning;
1334
1335         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1336                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1337
1338         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1339                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1340
1341         if (of_id)
1342                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1343         else
1344                 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1345         if (err)
1346                 goto disable_ahb_clk;
1347
1348         sdhci_esdhc_imx_hwinit(host);
1349
1350         err = sdhci_add_host(host);
1351         if (err)
1352                 goto disable_ahb_clk;
1353
1354         pm_runtime_set_active(&pdev->dev);
1355         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1356         pm_runtime_use_autosuspend(&pdev->dev);
1357         pm_suspend_ignore_children(&pdev->dev, 1);
1358         pm_runtime_enable(&pdev->dev);
1359
1360         return 0;
1361
1362 disable_ahb_clk:
1363         clk_disable_unprepare(imx_data->clk_ahb);
1364 disable_ipg_clk:
1365         clk_disable_unprepare(imx_data->clk_ipg);
1366 disable_per_clk:
1367         clk_disable_unprepare(imx_data->clk_per);
1368 free_sdhci:
1369         sdhci_pltfm_free(pdev);
1370         return err;
1371 }
1372
1373 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1374 {
1375         struct sdhci_host *host = platform_get_drvdata(pdev);
1376         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1377         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1378         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1379
1380         pm_runtime_get_sync(&pdev->dev);
1381         pm_runtime_disable(&pdev->dev);
1382         pm_runtime_put_noidle(&pdev->dev);
1383
1384         sdhci_remove_host(host, dead);
1385
1386         clk_disable_unprepare(imx_data->clk_per);
1387         clk_disable_unprepare(imx_data->clk_ipg);
1388         clk_disable_unprepare(imx_data->clk_ahb);
1389
1390         sdhci_pltfm_free(pdev);
1391
1392         return 0;
1393 }
1394
1395 #ifdef CONFIG_PM_SLEEP
1396 static int sdhci_esdhc_suspend(struct device *dev)
1397 {
1398         struct sdhci_host *host = dev_get_drvdata(dev);
1399
1400         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1401                 mmc_retune_needed(host->mmc);
1402
1403         return sdhci_suspend_host(host);
1404 }
1405
1406 static int sdhci_esdhc_resume(struct device *dev)
1407 {
1408         struct sdhci_host *host = dev_get_drvdata(dev);
1409
1410         /* re-initialize hw state in case it's lost in low power mode */
1411         sdhci_esdhc_imx_hwinit(host);
1412
1413         return sdhci_resume_host(host);
1414 }
1415 #endif
1416
1417 #ifdef CONFIG_PM
1418 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1419 {
1420         struct sdhci_host *host = dev_get_drvdata(dev);
1421         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1422         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1423         int ret;
1424
1425         ret = sdhci_runtime_suspend_host(host);
1426         if (ret)
1427                 return ret;
1428
1429         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1430                 mmc_retune_needed(host->mmc);
1431
1432         if (!sdhci_sdio_irq_enabled(host)) {
1433                 imx_data->actual_clock = host->mmc->actual_clock;
1434                 esdhc_pltfm_set_clock(host, 0);
1435                 clk_disable_unprepare(imx_data->clk_per);
1436                 clk_disable_unprepare(imx_data->clk_ipg);
1437         }
1438         clk_disable_unprepare(imx_data->clk_ahb);
1439
1440         return ret;
1441 }
1442
1443 static int sdhci_esdhc_runtime_resume(struct device *dev)
1444 {
1445         struct sdhci_host *host = dev_get_drvdata(dev);
1446         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1447         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1448         int err;
1449
1450         err = clk_prepare_enable(imx_data->clk_ahb);
1451         if (err)
1452                 return err;
1453
1454         if (!sdhci_sdio_irq_enabled(host)) {
1455                 err = clk_prepare_enable(imx_data->clk_per);
1456                 if (err)
1457                         goto disable_ahb_clk;
1458                 err = clk_prepare_enable(imx_data->clk_ipg);
1459                 if (err)
1460                         goto disable_per_clk;
1461                 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1462         }
1463
1464         err = sdhci_runtime_resume_host(host);
1465         if (err)
1466                 goto disable_ipg_clk;
1467
1468         return 0;
1469
1470 disable_ipg_clk:
1471         if (!sdhci_sdio_irq_enabled(host))
1472                 clk_disable_unprepare(imx_data->clk_ipg);
1473 disable_per_clk:
1474         if (!sdhci_sdio_irq_enabled(host))
1475                 clk_disable_unprepare(imx_data->clk_per);
1476 disable_ahb_clk:
1477         clk_disable_unprepare(imx_data->clk_ahb);
1478         return err;
1479 }
1480 #endif
1481
1482 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1483         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1484         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1485                                 sdhci_esdhc_runtime_resume, NULL)
1486 };
1487
1488 static struct platform_driver sdhci_esdhc_imx_driver = {
1489         .driver         = {
1490                 .name   = "sdhci-esdhc-imx",
1491                 .of_match_table = imx_esdhc_dt_ids,
1492                 .pm     = &sdhci_esdhc_pmops,
1493         },
1494         .id_table       = imx_esdhc_devtype,
1495         .probe          = sdhci_esdhc_imx_probe,
1496         .remove         = sdhci_esdhc_imx_remove,
1497 };
1498
1499 module_platform_driver(sdhci_esdhc_imx_driver);
1500
1501 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1502 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1503 MODULE_LICENSE("GPL v2");